From 9de7189ed43bb7524fe8bcb3e9f57a6516d0990d Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 5 Oct 2025 03:44:03 +0100 Subject: [PATCH] mediatek: build image for MT7987 RFB Import and clean DT and DT-overlay files from MediaTek's SDK to build an image with various DT-overlays for the MT7987 reference board. Signed-off-by: Daniel Golle --- target/linux/mediatek/dts/mt7987.dtsi | 1153 +++++++++++++++++ .../linux/mediatek/dts/mt7987a-rfb-emmc.dtso | 101 ++ .../dts/mt7987a-rfb-eth0-an8801sb.dtso | 32 + .../mediatek/dts/mt7987a-rfb-eth0-an8855.dtso | 204 +++ .../mediatek/dts/mt7987a-rfb-eth0-e2p5g.dtso | 32 + .../mediatek/dts/mt7987a-rfb-eth0-mt7531.dtso | 90 ++ .../mediatek/dts/mt7987a-rfb-eth1-i2p5g.dtso | 30 + .../dts/mt7987a-rfb-eth2-an8801sb.dtso | 33 + .../mediatek/dts/mt7987a-rfb-eth2-e2p5g.dtso | 30 + .../mediatek/dts/mt7987a-rfb-eth2-sfp.dtso | 41 + .../mediatek/dts/mt7987a-rfb-eth2-usb.dtso | 25 + target/linux/mediatek/dts/mt7987a-rfb-sd.dtso | 74 ++ .../mediatek/dts/mt7987a-rfb-spim-nand.dtso | 130 ++ .../mediatek/dts/mt7987a-rfb-spim-nor.dtso | 60 + target/linux/mediatek/dts/mt7987a-rfb.dts | 87 ++ target/linux/mediatek/dts/mt7987a.dtsi | 70 + target/linux/mediatek/dts/mt7987b.dtsi | 31 + target/linux/mediatek/image/filogic.mk | 59 + 18 files changed, 2282 insertions(+) create mode 100644 target/linux/mediatek/dts/mt7987.dtsi create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-emmc.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-eth0-an8801sb.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-eth0-an8855.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-eth0-e2p5g.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-eth0-mt7531.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-eth1-i2p5g.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-eth2-an8801sb.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-eth2-e2p5g.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-eth2-sfp.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-eth2-usb.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-sd.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-spim-nand.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb-spim-nor.dtso create mode 100644 target/linux/mediatek/dts/mt7987a-rfb.dts create mode 100644 target/linux/mediatek/dts/mt7987a.dtsi create mode 100644 target/linux/mediatek/dts/mt7987b.dtsi diff --git a/target/linux/mediatek/dts/mt7987.dtsi b/target/linux/mediatek/dts/mt7987.dtsi new file mode 100644 index 0000000000..e9c7685315 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987.dtsi @@ -0,0 +1,1153 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TOPRGU resets */ +#define MT7987_TOPRGU_SGMII0_GRST 1 +#define MT7987_TOPRGU_SGMII1_GRST 2 + +/ { + compatible = "mediatek,mt7987"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clkxtal: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + }; + + vproc: regulator-vproc { + compatible = "regulator-fixed"; + regulator-name = "proc"; + regulator-min-microvolt = <8500000>; + regulator-max-microvolt = <8500000>; + regulator-boot-on; + regulator-always-on; + }; + + firmware { + optee { + method = "smc"; + compatible = "linaro,optee-tz"; + status = "okay"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x0>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x1>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x2>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x3>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <850000>; + }; + opp01 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <850000>; + }; + opp02 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <850000>; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + clk40m: clk40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + clkitg: clkitg { + compatible = "simple-bus"; + status = "disabled"; + }; + + clksys: soc_clksys { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7987-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7987-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7987-apmixedsys", "syscon"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7987-sgmiisys", + "mediatek,mt7987-sgmiisys0", + "syscon", + "simple-mfd"; + reg = <0 0x10060000 0 0x1000>; + resets = <&watchdog MT7987_TOPRGU_SGMII0_GRST>; + mediatek,phya_trx_ck; + #clock-cells = <1>; + + sgmiipcs0: pcs { + compatible = "mediatek,mt7987-sgmii"; + clocks = <&topckgen CLK_TOP_SGM_0_SEL>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>; + clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; + }; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7987-sgmiisys", + "mediatek,mt7987-sgmiisys1", + "syscon", + "simple-mfd"; + reg = <0 0x10070000 0 0x1000>; + resets = <&watchdog MT7987_TOPRGU_SGMII1_GRST>; + mediatek,phya_trx_ck; + #clock-cells = <1>; + + sgmiipcs1: pcs { + compatible = "mediatek,mt7987-sgmii"; + clocks = <&topckgen CLK_TOP_SGM_1_SEL>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>; + clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; + }; + }; + + mcusys: mcusys@10400000 { + compatible = "mediatek,mt7987-mcusys", "syscon"; + reg = <0 0x10400000 0 0x1000>; + #clock-cells = <1>; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7987-ethdma", + "mediatek,mt7987-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + ethsysrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = + <0x34 4 0x34 4 0x34 4 + (ASSERT_SET | DEASSERT_CLEAR | + STATUS_SET)>; + }; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 128 255>; + #cooling-cells = <2>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + wmcpu_emi: wmcpu-reserved@50000000 { + compatible = "mediatek,wmcpu-reserved"; + no-map; + reg = <0 0x50000000 0 0x00100000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 0>; + + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_hot: active-hot { + temperature = <117000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-hot { + /* active: dynamic cpu frequency scaling */ + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&cpu_trip_active_hot>; + }; + + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + hwver: hwver@8000000 { + compatible = "mediatek,hwver", "syscon"; + reg = <0 0x8000000 0 0x1000>; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupts = ; + }; + + infra_bus_prot: infra_bus_prot@1000310c { + compatible = "mediatek,infracfg_ao_bus_hang_prot"; + reg = <0 0x1000310c 0 0x14>; + status = "disabled"; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7987-wdt", + "mediatek,mt7988-wdt", + "mediatek,mt6589-wdt", + "syscon"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + }; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7987-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f40000 0 0x1000>, + <0 0x11f60000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", + "iocfg_rt2", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 50>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + mmc_pins_default: mmc-pins-default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = ; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = ; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "USB_VBUS"; + drive-strength = ; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc_pins_uhs: mmc-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = ; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = ; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "USB_VBUS"; + drive-strength = ; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + sd_pins_default: sd-pins-default { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = ; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = ; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + }; + + sd_pins_uhs: sd-pins-uhs { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = ; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = ; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + }; + + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + + conf { + groups = "mdc_mdio"; + drive-strength = ; + }; + }; + + i2p5gbe_led0_pins: i2p5gbe0-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + + i2p5gbe_led1_0_pins: i2p5gbe1-pins { + mux { + function = "led"; + groups = "2p5gbe_led1_0"; + }; + }; + + i2p5gbe_led1_1_pins: i2p5gbe2-pins { + mux { + function = "led"; + groups = "2p5gbe_led1_1"; + }; + }; + + i2c0_pins: i2c0-pins-g2 { + mux { + function = "i2c"; + groups = "i2c0_2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pereset", "pcie0_clkreq", + "pcie0_wake"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pereset", "pcie1_clkreq", + "pcie1_wake"; + }; + }; + + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + + spic_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1"; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + }; + + i2c1_pins: i2c1-pins { + mux { + function = "i2c"; + groups = "i2c0_2"; + }; + }; + + i2s_pins: i2s-pins { + mux { + function = "i2s"; + groups = "pcm0_1"; + }; + }; + + pcm_pins: pcm-pins { + mux { + function = "pcm"; + groups = "pcm0_1"; + }; + }; + + pwm_pins: pwm-pins { + mux { + /* + * - pwm0 : PWM0@PIN13 + * - pwm1_0 : PWM1@PIN7 (share with JTAG) + * pwm1_1 : PWM1@PIN43 (share with i2c0) + * - pwm2_0 : PWM2@PIN12 (share with PCM) + * pwm2_1 : PWM2@PIN44 (share with i2c0) + */ + function = "pwm"; + groups = "pwm0"; + }; + }; + + pwm_rgb_pins: pwm-rgb-pins { + mux { + /* + * - pwm0 1 : PWM0@PIN13 + * - pwm1_0 :; PWM@PIN7 (share with JTAG) + * pwm1_1 : PWM1@PIN43 (share with i2c0) + * - pwm2_0 : PWM2@PIN12 (share with PCM) + * pwm2_1 : PWM2@PIN44 (share with i2c0) + */ + function = "pwm"; + groups = "pwm0", "pwm1_0", "pwm2_0"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + }; + + boottrap: boottrap@1001f6f0 { + compatible = "mediatek,boottrap"; + reg = <0 0x1001f6f0 0 0x20>; + status = "disabled"; + }; + + trng: trng@1020f000 { + compatible = "mediatek,mt7987-rng"; + status = "disabled"; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7987-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + status = "disabled"; + }; + + uart0: serial@11000000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART0_CK>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11000100 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000100 0 0x100>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_52M_UART1_CK>, + <&infracfg CLK_INFRA_66M_UART1_PCK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART1_SEL>; + assigned-clock-parents = <&topckgen + CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart2: serial@11000200 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000200 0 0x100>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_52M_UART2_CK>, + <&infracfg CLK_INFRA_66M_UART2_PCK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART2_SEL>; + assigned-clock-parents = <&topckgen + CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + i2c0: i2c@11003000 { + compatible = "mediatek,mt7988-i2c", + "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@11007800 { + compatible = "mediatek,ipm-spi-quad", + "mediatek,spi-ipm"; + reg = <0 0x11007800 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI0>, + <&infracfg CLK_INFRA_66M_SPI0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_MUX_SPI0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "hclk"; + status = "disabled"; + }; + + spi1: spi@11008800 { + compatible = "mediatek,ipm-spi-single", + "mediatek,spi-ipm"; + reg = <0 0x11008800 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI1>, + <&infracfg CLK_INFRA_66M_SPI1_HCK>; + assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_MUX_SPI1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen + CLK_TOP_SPIM_MST_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "hclk"; + status = "disabled"; + }; + + spi2: spi@11009800 { + compatible = "mediatek,ipm-spi-quad", + "mediatek,spi-ipm"; + reg = <0 0x11009800 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI2_BCK>, + <&infracfg CLK_INFRA_66M_SPI2_HCK>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg + CLK_INFRA_MUX_SPI2_BCK_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "hclk"; + status = "disabled"; + }; + + lvts: lvts@1100a000 { + compatible = "mediatek,mt7987-lvts-ap"; + reg = <0 0x1100a000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; + clock-names = "lvts_clk"; + resets = <&infracfg MT7987_INFRA_RST1_THERM_CTRL_SWRST>; + nvmem-cells = <&lvts_calibration>; + nvmem-cell-names = "lvts-calib-data-1"; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + usbtphy: usb-phy@11c50000 { + compatible = "mediatek,mt7987", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tphyu2port0: usb-phy@11c50000 { + reg = <0 0x11c50000 0 0x700>; + clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + auto_load_valid; + nvmem-cells = <&u2_intr_p0>, + <&u2_auto_load_valid_p0>; + nvmem-cell-names = "intr", "auto_load_valid"; + }; + tphyu3port0: usb-phy@11c50700 { + reg = <0 0x11c50700 0 0x900>; + clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + auto_load_valid; + nvmem-cells = <&comb_intr_p0>, + <&comb_rx_imp_p0>, + <&comb_tx_imp_p0>, + <&comb_auto_load_valid>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp", + "auto_load_valid"; + mediatek,syscon-type = <&topmisc 0x218 0>; + status = "disabled"; + }; + }; + + ssusb: usb@11200000 { + compatible = "mediatek,mt7987-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + phys = <&tphyu2port0 PHY_TYPE_USB2>; + usb2-lpm-disable; + mediatek,u3p-dis-msk=<1>; + status = "disabled"; + }; + + afe: audio-controller@11210000 { + compatible = "mediatek,mt7987-afe", + "mediatek,mt7986-afe"; + reg = <0 0x11210000 0 0x9000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, + <&infracfg CLK_INFRA_AUD_26M>, + <&infracfg CLK_INFRA_AUD_L>, + <&infracfg CLK_INFRA_AUD_AUD>, + <&infracfg CLK_INFRA_AUD_EG2>, + <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_AUD_I2S_M>; + clock-names = "aud_bus_ck", + "aud_26m_ck", + "aud_l_ck", + "aud_aud_ck", + "aud_eg2_ck", + "aud_sel", /* Not used in the driver */ + "aud_i2s_m"; /* Not used in the driver */ + assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_A1SYS_SEL>, + <&topckgen CLK_TOP_AUD_L_SEL>, + <&topckgen CLK_TOP_A_TUNER_SEL>; + assigned-clock-parents = <&apmixedsys + CLK_APMIXED_APLL2>, + <&topckgen + CLK_TOP_CB_APLL2_D4>, + <&apmixedsys + CLK_APMIXED_APLL2>, + <&topckgen + CLK_TOP_CB_APLL2_D4>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mediatek,mt7986-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_EMMC_200M_SEL>, + <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_MSDC200_SRC>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>; + clock-names = "source", "bus_clk", "axi_cg", "hclk", + "source_cg", "ahb_cg"; + status = "disabled"; + }; + + wed0: wed@15010000 { + compatible = "mediatek,mt7987-wed", + "syscon"; + reg = <0 0x15010000 0 0x2000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + wdma: wdma@15104800 { + compatible = "mediatek,wed-wdma"; + reg = <0 0x15104800 0 0x400>; + }; + + pcie0: pcie@11280000 { + compatible = "mediatek,mt7987-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11280000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <0>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x00200000>, + <0x82000000 0x00 0x20200000 0x00 + 0x20200000 0x00 0x0fe00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P0>, + <&topckgen CLK_TOP_PEXTP_TL_SEL>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m", "pextp_clk"; + status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, + <0 0 0 2 &pcie_intc2 1>, + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + pcie_intc2: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@11290000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11290000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <1>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x30000000 0x00 + 0x30000000 0x00 0x00200000>, + <0x82000000 0x00 0x30200000 0x00 + 0x30200000 0x00 0x0fe00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P1>, + <&topckgen CLK_TOP_PEXTP_TL_P1_SEL>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m", "pextp_clk"; + status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + slot1: pcie@0,0 { + reg = <0x0000 0 0 0 0>; + }; + }; + + topmisc: topmisc@10021000 { + compatible = "mediatek,mt7987-topmisc", "syscon", + "mediatek,mt7987-power-controller"; + reg = <0 0x10021000 0 0x10000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + /* power domain of the SoC */ + /* eth2p5@MT7988_POWER_DOMAIN_ETH2P5 { + * reg = ; + * #power-domain-cells = <0>; + * }; + */ + }; + + efuse: efuse@11d30000 { + compatible = "mediatek,efuse"; + reg = <0 0x11d30000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + lvts_calibration: calib@918 { + reg = <0x918 0x10>; + }; + + comb_auto_load_valid: usb3-alv-imp@8ee { + reg = <0x8ee 1>; + bits = <0 1>; + }; + + comb_rx_imp_p0: usb3-rx-imp@8ec,1 { + reg = <0x8ec 1>; + bits = <0 5>; + }; + + comb_tx_imp_p0: usb3-tx-imp@8ec,2 { + reg = <0x8ec 2>; + bits = <5 5>; + }; + + comb_intr_p0: usb3-intr@8ec,3 { + reg = <0x8ed 1>; + bits = <2 6>; + }; + + u2_auto_load_valid_p0: usb2-alv-p0@8cc,1 { + reg = <0x8cc 1>; + bits = <0 1>; + }; + + u2_intr_p0: usb2-intr-p0@8cc,2 { + reg = <0x8cc 1>; + bits = <1 5>; + }; + }; + + devapc: devapc@1a110000 { + compatible = "mediatek,mt7987-devapc"; + reg = <0 0x1a110000 0 0x1000>; + interrupts = ; + }; + + ethwarp: syscon@15031000 { + compatible = "mediatek,mt7988-ethwarp", "syscon"; + reg = <0 0x15031000 0 0x1000>; + #clock-cells = <1>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7987-eth"; + reg = <0 0x15100000 0 0x80000>, + <0 0x15400000 0 0x20000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_2X_SEL>; + clock-names = "fe", "gp2", "gp1", "gp3", + "top_eth_gmii_sel", "top_eth_refck_50m_sel", + "top_eth_sys_200m_sel", "top_eth_sys_sel", + "top_eth_xgmii_sel", "top_eth_mii_sel", + "top_netsys_sel", "top_netsys_500m_sel", + "top_netsys_pao_2x_sel"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,wed = <&wed0>; + mediatek,infracfg = <&topmisc>; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + pcs-handle = <&sgmiipcs0>; + status = "disabled"; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + pcs-handle = <&sgmiipcs1>; + status = "disabled"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + crypto: crypto@15600000 { + compatible = "inside-secure,safexcel-eip197b", + "security-ip-197-srv"; + reg = <0 0x15600000 0 0x180000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + eth = <ð>; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7987a-rfb-emmc.dtso b/target/linux/mediatek/dts/mt7987a-rfb-emmc.dtso new file mode 100644 index 0000000000..2a6f96a2a0 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-emmc.dtso @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path = "/"; + __overlay__ { + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + fragment@1 { + target-path = "/soc/spi@11007800"; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc_pins_default>; + pinctrl-1 = <&mmc_pins_uhs>; + bus-width = <8>; + max-frequency = <48000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + partitions { + block-partition-env { + partname = "ubootenv"; + nvmem-layout { + compatible = "u-boot,env"; + }; + }; + + block-partition-factory { + partname = "factory"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1e00>; + }; + }; + }; + + emmc_rootfs: block-partition-production { + partname = "production"; + }; + }; + }; + }; + }; + }; + + fragment@3 { + target-path = "/chosen"; + __overlay__ { + rootdisk-emmc = <&emmc_rootfs>; + }; + }; + + fragment@4 { + target = <&pcie0>; + __overlay__ { + slot0: pcie@0,0 { + reg = <0x0000 0 0 0 0>; + mt7996@0,0 { + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + }; + }; + }; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7987a-rfb-eth0-an8801sb.dtso b/target/linux/mediatek/dts/mt7987a-rfb-eth0-an8801sb.dtso new file mode 100644 index 0000000000..bfe990b557 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-eth0-an8801sb.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +#include + +/ { + fragment@0 { + target = <&gmac0>; + __overlay__ { + phy-handle = <&phy31>; + phy-mode = "sgmii"; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/soc_netsys/ethernet@15100000/mdio-bus"; + __overlay__ { + phy31: phy@31 { + compatible = "ethernet-phy-idc0ff.0421"; + reg = <31>; + reset-gpios = <&pio 48 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + eee-broken-100tx; + eee-broken-1000t; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7987a-rfb-eth0-an8855.dtso b/target/linux/mediatek/dts/mt7987a-rfb-eth0-an8855.dtso new file mode 100644 index 0000000000..c5ad39083f --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-eth0-an8855.dtso @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +#include + +/ { + fragment@0 { + target = <&gmac0>; + __overlay__ { + phy-mode = "2500base-x"; + status = "okay"; + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + + fragment@1 { + target-path = "/soc_netsys/ethernet@15100000/mdio-bus"; + __overlay__ { + mfd: mfd@1 { + compatible = "airoha,an8855-mfd"; + reg = <1>; + status = "okay"; + + efuse { + compatible = "airoha,an8855-efuse"; + #nvmem-cell-cells = <0>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + shift_sel_port0_tx_a: shift-sel-port0-tx-a@c { + reg = <0xc 0x4>; + }; + + shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 { + reg = <0x10 0x4>; + }; + + shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 { + reg = <0x14 0x4>; + }; + + shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 { + reg = <0x18 0x4>; + }; + + shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c { + reg = <0x1c 0x4>; + }; + + shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 { + reg = <0x20 0x4>; + }; + + shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 { + reg = <0x24 0x4>; + }; + + shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 { + reg = <0x28 0x4>; + }; + + shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c { + reg = <0x2c 0x4>; + }; + + shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 { + reg = <0x30 0x4>; + }; + + shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 { + reg = <0x34 0x4>; + }; + + shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 { + reg = <0x38 0x4>; + }; + + shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c { + reg = <0x4c 0x4>; + }; + + shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 { + reg = <0x50 0x4>; + }; + + shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 { + reg = <0x54 0x4>; + }; + + shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 { + reg = <0x58 0x4>; + }; + }; + }; + + ethernet-switch { + compatible = "airoha,an8855-switch"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + airoha,ext-surge; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "internal"; + phy-handle = <&internal_phy1>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&internal_phy2>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&internal_phy3>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&internal_phy4>; + }; + + port@5 { + reg = <5>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + + mdio { + compatible = "airoha,an8855-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy1: phy@1 { + reg = <1>; + + nvmem-cells = <&shift_sel_port0_tx_a>, + <&shift_sel_port0_tx_b>, + <&shift_sel_port0_tx_c>, + <&shift_sel_port0_tx_d>; + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; + }; + + internal_phy2: phy@2 { + reg = <2>; + + nvmem-cells = <&shift_sel_port1_tx_a>, + <&shift_sel_port1_tx_b>, + <&shift_sel_port1_tx_c>, + <&shift_sel_port1_tx_d>; + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; + }; + + internal_phy3: phy@3 { + reg = <3>; + + nvmem-cells = <&shift_sel_port2_tx_a>, + <&shift_sel_port2_tx_b>, + <&shift_sel_port2_tx_c>, + <&shift_sel_port2_tx_d>; + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; + }; + + internal_phy4: phy@4 { + reg = <4>; + + nvmem-cells = <&shift_sel_port3_tx_a>, + <&shift_sel_port3_tx_b>, + <&shift_sel_port3_tx_c>, + <&shift_sel_port3_tx_d>; + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7987a-rfb-eth0-e2p5g.dtso b/target/linux/mediatek/dts/mt7987a-rfb-eth0-e2p5g.dtso new file mode 100644 index 0000000000..3951ec1007 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-eth0-e2p5g.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +#include + +/ { + fragment@0 { + target = <&gmac0>; + __overlay__ { + phy-handle = <&phy12>; + phy-mode = "2500base-x"; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/soc_netsys/ethernet@15100000/mdio-bus"; + __overlay__ { + phy12: phy@12 { + compatible = "ethernet-phy-id03a2.a411"; + reg = <12>; + reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + full-duplex; + pause; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7987a-rfb-eth0-mt7531.dtso b/target/linux/mediatek/dts/mt7987a-rfb-eth0-mt7531.dtso new file mode 100644 index 0000000000..c770b9214b --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-eth0-mt7531.dtso @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&gmac0>; + __overlay__ { + phy-mode = "2500base-x"; + status = "okay"; + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + + fragment@1 { + target-path = "/soc_netsys/ethernet@15100000/mdio-bus"; + __overlay__ { + phy12: phy@12 { + compatible = "ethernet-phy-id03a2.a411"; + reg = <12>; + reset-gpios = <&pio 49 1>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + phy-mode = "2500base-x"; + full-duplex; + pause; + airoha,pnswap-rx; + }; + + switch31: switch@31 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 42 0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@5 { + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; + phy-handle = <&phy12>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + + }; + }; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7987a-rfb-eth1-i2p5g.dtso b/target/linux/mediatek/dts/mt7987a-rfb-eth1-i2p5g.dtso new file mode 100644 index 0000000000..87d3e391c2 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-eth1-i2p5g.dtso @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&gmac1>; + __overlay__ { + phy-mode = "internal"; + phy-handle = <&phy15>; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/soc_netsys/ethernet@15100000/mdio-bus"; + __overlay__ { + /* built-in 2.5G Ethernet PHY */ + phy15: phy@15 { + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <15>; + phy-mode = "internal"; + }; + }; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7987a-rfb-eth2-an8801sb.dtso b/target/linux/mediatek/dts/mt7987a-rfb-eth2-an8801sb.dtso new file mode 100644 index 0000000000..14118a34ff --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-eth2-an8801sb.dtso @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +#include + +/ { + fragment@0 { + target = <&gmac2>; + __overlay__ { + phy-handle = <&phy31>; + phy-mode = "sgmii"; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/soc_netsys/ethernet@15100000/mdio-bus"; + __overlay__ { + phy31: phy@31 { + compatible = "ethernet-phy-idc0ff.0421"; + reg = <31>; + reset-gpios = <&pio 48 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + eee-broken-100tx; + eee-broken-1000t; + }; + }; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7987a-rfb-eth2-e2p5g.dtso b/target/linux/mediatek/dts/mt7987a-rfb-eth2-e2p5g.dtso new file mode 100644 index 0000000000..e944d78f83 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-eth2-e2p5g.dtso @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +#include + +/ { + fragment@0 { + target = <&gmac2>; + __overlay__ { + phy-handle = <&phy11>; + phy-mode = "2500base-x"; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/soc_netsys/ethernet@15100000/mdio-bus"; + __overlay__ { + reset-gpios = <&pio 48 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + + phy11: phy@11 { + compatible = "ethernet-phy-id03a2.a411"; + reg = <11>; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7987a-rfb-eth2-sfp.dtso b/target/linux/mediatek/dts/mt7987a-rfb-eth2-sfp.dtso new file mode 100644 index 0000000000..dbb2c859a6 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-eth2-sfp.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +#include + +/ { + fragment@0 { + target-path = "/"; + __overlay__ { + sfp_cage0: sfp@0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + }; + }; + + fragment@1 { + target = <&gmac2>; + __overlay__ { + phy-mode = "2500base-x"; + managed = "in-band-status"; + sfp = <&sfp_cage0>; + status = "okay"; + }; + }; + + fragment@2 { + target-path = "/soc/i2c@11003000"; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7987a-rfb-eth2-usb.dtso b/target/linux/mediatek/dts/mt7987a-rfb-eth2-usb.dtso new file mode 100644 index 0000000000..3e2bea0353 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-eth2-usb.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +#include + +/ { + fragment@0 { + target-path = "/soc/usb-phy@11c50000/usb-phy@11c50700"; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/soc/usb@11200000"; + __overlay__ { + phys = <&tphyu2port0 PHY_TYPE_USB2>, + <&tphyu3port0 PHY_TYPE_USB3>; + mediatek,u3p-dis-msk=<0>; + }; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7987a-rfb-sd.dtso b/target/linux/mediatek/dts/mt7987a-rfb-sd.dtso new file mode 100644 index 0000000000..10ce996f8a --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-sd.dtso @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path = "/"; + __overlay__ { + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + fragment@1 { + target-path = "/soc/spi@11007800"; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@2 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd_pins_default>; + pinctrl-1 = <&sd_pins_uhs>; + bus-width = <4>; + max-frequency = <48000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + no-mmc; + no-sdio; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + partitions { + block-partition-env { + partname = "ubootenv"; + nvmem-layout { + compatible = "u-boot,env"; + }; + }; + sd_rootfs: block-partition-production { + partname = "production"; + }; + }; + }; + }; + }; + }; + + fragment@3 { + target-path = "/chosen"; + __overlay__ { + rootdisk-sd = <&sd_rootfs>; + }; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7987a-rfb-spim-nand.dtso b/target/linux/mediatek/dts/mt7987a-rfb-spim-nand.dtso new file mode 100644 index 0000000000..cd19574d31 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-spim-nand.dtso @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path = "/soc/spi@11007800"; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0400000>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + gmac2_mac: eeprom@fffee { + reg = <0xfffee 0x6>; + }; + + gmac1_mac: eeprom@ffffa { + reg = <0xffffa 0x6>; + }; + + gmac0_mac: eeprom@ffff4 { + reg = <0xffff4 0x6>; + }; + }; + }; + + partition@580000 { + label = "FIP"; + reg = <0x580000 0x0200000>; + }; + + partition@780000 { + label = "ubi"; + reg = <0x780000 0x7080000>; + compatible = "linux,ubi"; + + volumes { + ubi_rootfs: ubi-volume-fit { + volname = "firmware"; + }; + }; + }; + }; + }; + }; + }; + + fragment@1 { + target-path = "/chosen"; + __overlay__ { + rootdisk-spim-nand = <&ubi_rootfs>; + }; + }; + + fragment@2 { + target = <&pcie0>; + __overlay__ { + slot0: pcie@0,0 { + reg = <0x0000 0 0 0 0>; + + mt7996@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0>; + }; + }; + }; + }; + + fragment@3 { + target = <&gmac0>; + __overlay__ { + nvmem-cell-names = "mac-address"; + nvmem-cells = <&gmac0_mac>; + }; + }; + + fragment@4 { + target = <&gmac1>; + __overlay__ { + nvmem-cell-names = "mac-address"; + nvmem-cells = <&gmac1_mac>; + }; + }; + + fragment@5 { + target = <&gmac2>; + __overlay__ { + nvmem-cell-names = "mac-address"; + nvmem-cells = <&gmac2_mac>; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7987a-rfb-spim-nor.dtso b/target/linux/mediatek/dts/mt7987a-rfb-spim-nor.dtso new file mode 100644 index 0000000000..55ec61285d --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb-spim-nor.dtso @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path = "/soc/spi@11009800"; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 < + 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; + spi-cal-addrlen = <1>; + spi-cal-addr = /bits/ 32 <0x0>; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partition@00000 { + label = "BL2"; + reg = <0x00000 0x0040000>; + }; + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x0010000>; + }; + partition@50000 { + label = "Factory"; + reg = <0x50000 0x0200000>; + }; + partition@250000 { + label = "FIP"; + reg = <0x250000 0x0080000>; + }; + nor_rootdisk: partition@2D0000 { + label = "firmware"; + reg = <0x2D0000 0x1D30000>; + }; + }; + }; + }; + + fragment@1 { + target-path = "/chosen"; + __overlay__ { + rootdisk-nor = <&nor_rootdisk>; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7987a-rfb.dts b/target/linux/mediatek/dts/mt7987a-rfb.dts new file mode 100644 index 0000000000..2824daa1d5 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a-rfb.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7987a.dtsi" +#include + +/* MT7987A RFB DTS for DT overlay-based device tree */ +/ { + model = "MediaTek MT7987A RFB"; + compatible = "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf ubi.block=0,firmware \ + root=/dev/fit0 rootwait nosmp"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; + + /* use pwm0 as led: share with fan/pwm_rgb */ + pwm_led { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; + + led { + pwms = <&pwm 0 50000 0>; + max-brightness = <255>; + active-low; + linux,default-trigger = "default-on"; + }; + }; + + /* use pwm0/1/2 as multicolor LED: share with fan/pwm_led */ + pwm_rgb { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_rgb_pins>; + status = "disabled"; + + multi-led { + color = ; + function = LED_FUNCTION_INDICATOR; + max-brightness = <255>; + + led-red { + pwms = <&pwm 0 50000>; + color = ; + }; + + led-green { + pwms = <&pwm 1 50000>; + color = ; + }; + + led-blue { + pwms = <&pwm 2 50000>; + color = ; + }; + }; + }; +}; + +&fan { + pwms = <&pwm 0 50000 0>; + status = "disabled"; +}; diff --git a/target/linux/mediatek/dts/mt7987a.dtsi b/target/linux/mediatek/dts/mt7987a.dtsi new file mode 100644 index 0000000000..1ace91a5f9 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987a.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include +#include "mt7987.dtsi" + +/ { + compatible = "mediatek,mt7987a", "mediatek,mt7987"; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; + +}; + +&boottrap { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&infra_bus_prot { + status = "okay"; +}; + +&lvts { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "disabled"; +}; + +&pwm { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&ssusb { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7987b.dtsi b/target/linux/mediatek/dts/mt7987b.dtsi new file mode 100644 index 0000000000..7d159a8053 --- /dev/null +++ b/target/linux/mediatek/dts/mt7987b.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7987a.dtsi" +#include "mt7987-netsys-eth2-usb.dtsi" + +/ { + compatible = "mediatek,mt7987b", "mediatek,mt7987"; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; + + cpus { + /delete-node/ cpu@2; + /delete-node/ cpu@3; + }; +}; + +&cpu_thermal { + cooling-maps { + cpu-active-hot { + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index e1026180c7..51fe387dea 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -24,6 +24,14 @@ define Build/mt7986-bl31-uboot cat $(STAGING_DIR_IMAGE)/mt7986_$1-u-boot.fip >> $@ endef +define Build/mt7987-bl2 + cat $(STAGING_DIR_IMAGE)/mt7987-$1-bl2.img >> $@ +endef + +define Build/mt7987-bl31-uboot + cat $(STAGING_DIR_IMAGE)/mt7987_$1-u-boot.fip >> $@ +endef + define Build/mt7988-bl2 cat $(STAGING_DIR_IMAGE)/mt7988-$1-bl2.img >> $@ endef @@ -1612,6 +1620,57 @@ define Device/mediatek_mt7986b-rfb endef TARGET_DEVICES += mediatek_mt7986b-rfb +define Device/mediatek_mt7987a-rfb + DEVICE_VENDOR := MediaTek + DEVICE_MODEL := MT7987A rfb + DEVICE_DTS := mt7987a-rfb + DEVICE_DTS_OVERLAY:= \ + mt7987a-rfb-spim-nand \ + mt7987a-rfb-spim-nor \ + mt7987a-rfb-emmc \ + mt7987a-rfb-sd \ + mt7987a-rfb-eth0-an8801sb \ + mt7987a-rfb-eth0-an8855 \ + mt7987a-rfb-eth0-e2p5g \ + mt7987a-rfb-eth0-mt7531 \ + mt7987a-rfb-eth1-i2p5g \ + mt7987a-rfb-eth2-an8801sb \ + mt7987a-rfb-eth2-e2p5g \ + mt7987a-rfb-eth2-sfp \ + mt7987a-rfb-eth2-usb + DEVICE_DTS_DIR := ../dts + DEVICE_DTC_FLAGS := --pad 4096 + DEVICE_DTS_LOADADDR := 0x4ff00000 + DEVICE_PACKAGES := mt798x-2p5g-phy-firmware-internal kmod-sfp blkid + KERNEL_LOADADDR := 0x40000000 + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := .itb + KERNEL_IN_UBI := 1 + IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m + IMAGES := sysupgrade.itb + IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata + ARTIFACTS := \ + snand-preloader.bin \ + snand-bl31-uboot.fip \ + sdcard.img.gz + ARTIFACT/snand-preloader.bin := mt7987-bl2 spim-nand0-ubi-comb + ARTIFACT/snand-bl31-uboot.fip := mt7987-bl31-uboot rfb-spim-nand + ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\ + pad-to 17k | mt7987-bl2 sdmmc-comb |\ + pad-to 6656k | mt7987-bl31-uboot rfb-sd |\ + $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\ + pad-to 12M | append-image-stage initramfs.itb | check-size 44m |\ + ) \ + $(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\ + pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\ + ) \ + gzip +endef +TARGET_DEVICES += mediatek_mt7987a-rfb + define Device/mediatek_mt7988a-rfb DEVICE_VENDOR := MediaTek DEVICE_MODEL := MT7988A rfb -- 2.30.2