From 95f62f1fe216c852eeded26e880b4368fb1c9366 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 21 Nov 2025 23:42:09 +0100 Subject: [PATCH] imx: drop support for kernel 6.6 Drop support for kernel 6.6 as now kernel 6.12 is set as default kernel version. Link: https://github.com/openwrt/openwrt/pull/20856 Signed-off-by: Christian Marangi --- target/linux/imx/config-6.6 | 490 ------ .../linux/imx/patches-6.6/100-bootargs.patch | 11 - ...apalis-ixora-add-status-LEDs-aliases.patch | 96 -- ...alis-ixora-make-switch3-reset-button.patch | 78 - ...10-ARM-dts-imx7d-pico-pi-set-aliases.patch | 24 - ...-pico-pi.dts-add-default-stdout-path.patch | 23 - ...x8mp-add-imx8mp-venice-gw74xx-imx219.patch | 136 -- ...-imx8mm-venice-gw73xx-add-TPM-device.patch | 39 - ...-imx8mp-venice-gw73xx-add-TPM-device.patch | 39 - ...-imx8mm-venice-gw72xx-add-TPM-device.patch | 39 - ...-imx8mp-venice-gw72xx-add-TPM-device.patch | 39 - ...-imx8mm-venice-gw71xx-add-TPM-device.patch | 39 - ...-imx8mp-venice-gw71xx-add-TPM-device.patch | 39 - ...x8mm-venice-gw7901-add-digital-I-O-d.patch | 34 - ...-imx8mm-venice-gw7901-add-TPM-device.patch | 45 - ...eescale-imx8mp-venice-gw72xx-2x-fix-.patch | 38 - ...eescale-imx8mp-venice-gw73xx-2x-fix-.patch | 38 - ...mx8mp-venice-gw74xx-add-ADC-rail-for.patch | 30 - ...mx8mp-venice-gw72xx-add-mac-addr-for.patch | 80 - ...mx8mp-venice-gw73xx-add-mac-addr-for.patch | 82 - ...64-dts-imx8mm-venice-add-RTC-aliases.patch | 189 --- ...-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch | 36 - ...ts-freescale-rename-gw7905-to-gw75xx.patch | 1426 ----------------- ...nice-gw75xx-add-Accelerometer-device.patch | 79 - ...X8M-Plus-Gateworks-GW82XX-2X-support.patch | 1107 ------------- ...-max-gen-first-for-IMX8MM-and-IMX8MP.patch | 121 -- 26 files changed, 4397 deletions(-) delete mode 100644 target/linux/imx/config-6.6 delete mode 100644 target/linux/imx/patches-6.6/100-bootargs.patch delete mode 100644 target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch delete mode 100644 target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch delete mode 100644 target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch delete mode 100644 target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch delete mode 100644 target/linux/imx/patches-6.6/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch delete mode 100644 target/linux/imx/patches-6.6/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch delete mode 100644 target/linux/imx/patches-6.6/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch delete mode 100644 target/linux/imx/patches-6.6/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch delete mode 100644 target/linux/imx/patches-6.6/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch delete mode 100644 target/linux/imx/patches-6.6/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch delete mode 100644 target/linux/imx/patches-6.6/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch delete mode 100644 target/linux/imx/patches-6.6/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch delete mode 100644 target/linux/imx/patches-6.6/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch delete mode 100644 target/linux/imx/patches-6.6/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch delete mode 100644 target/linux/imx/patches-6.6/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch delete mode 100644 target/linux/imx/patches-6.6/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch delete mode 100644 target/linux/imx/patches-6.6/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch delete mode 100644 target/linux/imx/patches-6.6/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch delete mode 100644 target/linux/imx/patches-6.6/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch delete mode 100644 target/linux/imx/patches-6.6/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch delete mode 100644 target/linux/imx/patches-6.6/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch delete mode 100644 target/linux/imx/patches-6.6/503-6.13-arm64-dts-imx8m-venice-gw75xx-add-Accelerometer-device.patch delete mode 100644 target/linux/imx/patches-6.6/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch delete mode 100644 target/linux/imx/patches-6.6/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch diff --git a/target/linux/imx/config-6.6 b/target/linux/imx/config-6.6 deleted file mode 100644 index 33478f29b9..0000000000 --- a/target/linux/imx/config-6.6 +++ /dev/null @@ -1,490 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_ARM_ERRATA_814220=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_HEAVY_MB=y -# CONFIG_ARM_IMX6Q_CPUFREQ is not set -# CONFIG_ARM_IMX_CPUFREQ_DT is not set -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASN1=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_ATA=y -CONFIG_ATAGS=y -# CONFIG_ATA_SFF is not set -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_PM=y -CONFIG_CACHE_L2X0=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CLKSRC_IMX_GPT=y -CONFIG_CLKSRC_MMIO=y -# CONFIG_CLK_IMX8MM is not set -# CONFIG_CLK_IMX8MN is not set -# CONFIG_CLK_IMX8MP is not set -# CONFIG_CLK_IMX8MQ is not set -# CONFIG_CLK_IMX8ULP is not set -# CONFIG_CLK_IMX93 is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_THERMAL=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AES_ARM_BS=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_BLAKE2S_ARM=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CHACHA20=y -CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32_ARM_CE=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_CTS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_FSL_CAAM=y -CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y -CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y -# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set -# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set -CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y -CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 -CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y -# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_ENGINE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM=y -CONFIG_CRYPTO_SHA1_ARM_NEON=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA512_ARM=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_XTS=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set -# CONFIG_DRM_FSL_LDB is not set -# CONFIG_DRM_IMX8QM_LDB is not set -# CONFIG_DRM_IMX8QXP_LDB is not set -# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set -# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set -# CONFIG_DRM_IMX_LCDC is not set -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ENCRYPTED_KEYS=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FEC=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FSL_DPAA2_SWITCH is not set -CONFIG_FSL_GUTS=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FS_ENCRYPTION_ALGS=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -# CONFIG_GIANFAR is not set -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MXC=y -CONFIG_GPIO_VF610=y -CONFIG_GRO_CELLS=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IMX=y -# CONFIG_I2C_IMX_LPI2C is not set -CONFIG_I2C_SLAVE=y -# CONFIG_I2C_SLAVE_TESTUNIT is not set -CONFIG_IMX2_WDT=y -# CONFIG_IMX7ULP_WDT is not set -# CONFIG_IMX8MM_THERMAL is not set -# CONFIG_IMX93_ADC is not set -CONFIG_IMX_DMA=y -# CONFIG_IMX_GPCV2_PM_DOMAINS is not set -CONFIG_IMX_INTMUX=y -CONFIG_IMX_IRQSTEER=y -CONFIG_IMX_MU_MSI=m -CONFIG_IMX_SDMA=y -CONFIG_IMX_THERMAL=y -# CONFIG_IMX_WEIM is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_INPUT_BBNSM_PWRKEY is not set -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -# CONFIG_JFFS2_FS is not set -CONFIG_KEYS=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -# CONFIG_MMC_MXC is not set -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MPILIB=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_GPMI_NAND=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -# CONFIG_MX3_IPU is not set -CONFIG_MXC_CLK=y -CONFIG_MXS_DMA=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -# CONFIG_NET_DSA_MICROCHIP_KSZ_PTP is not set -CONFIG_NET_DSA_TAG_DSA=y -CONFIG_NET_DSA_TAG_DSA_COMMON=y -CONFIG_NET_DSA_TAG_EDSA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -# CONFIG_NVMEM_IMX_IIM is not set -CONFIG_NVMEM_IMX_OCOTP=y -# CONFIG_NVMEM_IMX_OCOTP_ELE is not set -CONFIG_NVMEM_LAYOUTS=y -# CONFIG_NVMEM_SNVS_LPGPR is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0x80000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI_IMX6_HOST=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_IMX8ULP is not set -# CONFIG_PINCTRL_IMX93 is not set -# CONFIG_PINCTRL_IMXRT1050 is not set -# CONFIG_PINCTRL_IMXRT1170 is not set -CONFIG_PL310_ERRATA_769419=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_OPP=y -CONFIG_PPS=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -# CONFIG_PWM_IMX1 is not set -CONFIG_PWM_IMX27=y -# CONFIG_PWM_IMX_TPM is not set -CONFIG_PWM_SYSFS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RD_LZO=y -CONFIG_RD_XZ=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_ANATOP=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_BBNSM is not set -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_IMXDI is not set -# CONFIG_RTC_DRV_MXC is not set -# CONFIG_RTC_DRV_MXC_V2 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_THERMAL_PRESSURE=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_IMX_EARLYCON=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -# CONFIG_SOC_IMX50 is not set -# CONFIG_SOC_IMX51 is not set -# CONFIG_SOC_IMX53 is not set -# CONFIG_SOC_IMX6Q is not set -# CONFIG_SOC_IMX6SL is not set -# CONFIG_SOC_IMX6SLL is not set -# CONFIG_SOC_IMX6SX is not set -# CONFIG_SOC_IMX6UL is not set -# CONFIG_SOC_IMX7D is not set -# CONFIG_SOC_IMX7ULP is not set -# CONFIG_SOC_IMX8M is not set -# CONFIG_SOC_IMX9 is not set -# CONFIG_SOC_LS1021A is not set -# CONFIG_SOC_VF610 is not set -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -# CONFIG_SPI_FSL_LPSPI is not set -# CONFIG_SPI_FSL_QUADSPI is not set -CONFIG_SPI_IMX=y -CONFIG_SPI_MASTER=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_STMP_DEVICE=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_CHIPIDEA_IMX=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_GADGET=y -CONFIG_USB_MXS_PHY=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -# CONFIG_VIDEO_DW100 is not set -# CONFIG_VIDEO_HANTRO is not set -# CONFIG_VIDEO_IMX7_CSI is not set -# CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set -# CONFIG_VIDEO_IMX8_ISI is not set -# CONFIG_VIDEO_IMX_MIPI_CSIS is not set -# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set -CONFIG_VMSPLIT_2G=y -# CONFIG_VMSPLIT_3G is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/imx/patches-6.6/100-bootargs.patch b/target/linux/imx/patches-6.6/100-bootargs.patch deleted file mode 100644 index 7afcebecb0..0000000000 --- a/target/linux/imx/patches-6.6/100-bootargs.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts -@@ -16,4 +16,8 @@ - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -+ -+ chosen { -+ bootargs = "console=ttymxc0,115200"; -+ }; - }; diff --git a/target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch b/target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch deleted file mode 100644 index 5a8e9550fd..0000000000 --- a/target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 68604e89335ccb3e893b5a05b2c0d5cd2eaaf6ec Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Petr=20=C5=A0tetiar?= -Date: Tue, 3 Mar 2020 15:14:40 +0100 -Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: add status LEDs aliases -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Petr Å tetiar ---- - arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts | 16 ++++++++++------ - arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts | 12 ++++++++---- - 2 files changed, 18 insertions(+), 10 deletions(-) - ---- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts -@@ -24,6 +24,10 @@ - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; -+ led-boot = &led_boot; -+ led-failsafe = &led_failsafe; -+ led-running = &led_running; -+ led-upgrade = &led_upgrade; - }; - - chosen { -@@ -35,22 +39,22 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - -- led4-green { -+ led_running: led4-green { - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - label = "LED_4_GREEN"; - }; - -- led4-red { -+ led_upgrade: led4-red { - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - label = "LED_4_RED"; - }; - -- led5-green { -+ led_boot: led5-green { - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - label = "LED_5_GREEN"; - }; - -- led5-red { -+ led_failsafe: led5-red { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - label = "LED_5_RED"; - }; ---- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts -@@ -24,6 +24,10 @@ - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; -+ led-boot = &led_boot; -+ led-failsafe = &led_failsafe; -+ led-running = &led_running; -+ led-upgrade = &led_upgrade; - }; - - chosen { -@@ -36,22 +40,22 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - -- led4-green { -- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; -+ led_running: led4-green { -+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - label = "LED_4_GREEN"; - }; - -- led4-red { -- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; -+ led_upgrade: led4-red { -+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - label = "LED_4_RED"; - }; - -- led5-green { -+ led_boot: led5-green { - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - label = "LED_5_GREEN"; - }; - -- led5-red { -+ led_failsafe: led5-red { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - label = "LED_5_RED"; - }; diff --git a/target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch b/target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch deleted file mode 100644 index 0a3b696128..0000000000 --- a/target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch +++ /dev/null @@ -1,78 +0,0 @@ -From b6764bb27c819cdcf854371db485a43d71f579f3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Petr=20=C5=A0tetiar?= -Date: Tue, 3 Mar 2020 15:15:57 +0100 -Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: make switch3 reset button -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Petr Å tetiar ---- - arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts | 15 ++++++++++++++- - arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts | 15 ++++++++++++++- - 2 files changed, 28 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts -@@ -59,6 +59,17 @@ - label = "LED_5_RED"; - }; - }; -+ -+ gpio-keys { -+ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <10>; -+ }; -+ }; - }; - - &can1 { -@@ -183,4 +194,10 @@ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; -+ -+ pinctrl_switch3_ixora: switch3ixora { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 -+ >; -+ }; - }; ---- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts -@@ -61,6 +61,17 @@ - }; - }; - -+ gpio-keys { -+ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <10>; -+ }; -+ }; -+ - reg_3v3_vmmc: regulator-3v3-vmmc { - compatible = "regulator-fixed"; - enable-active-high; -@@ -264,6 +275,12 @@ - >; - }; - -+ pinctrl_switch3_ixora: switch3ixora { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 -+ >; -+ }; -+ - pinctrl_mmc_cd_sleep: mmccdslpgrp { - fsl,pins = < - /* MMC1 CD */ diff --git a/target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch b/target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch deleted file mode 100644 index d71787b3ac..0000000000 --- a/target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts -@@ -8,12 +8,20 @@ - model = "TechNexion PICO-IMX7D Board and PI baseboard"; - compatible = "technexion,imx7d-pico-pi", "fsl,imx7d"; - -+ aliases { -+ led-boot = &led_system; -+ led-failsafe = &led_system; -+ led-running = &led_system; -+ led-upgrade = &led_system; -+ label-mac-device = &fec1; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - -- led { -+ led_system: led { - label = "gpio-led"; - gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - }; diff --git a/target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch b/target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch deleted file mode 100644 index 244b7595ae..0000000000 --- a/target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 6e8e5ccfbee7a531b035ffce3f95f3901946fa9d Mon Sep 17 00:00:00 2001 -From: Robert Nelson -Date: Wed, 9 Jan 2019 14:33:24 -0600 -Subject: [PATCH] ARM: imx7d-pico-pi.dts: add default stdout-path - -Signed-off-by: Robert Nelson ---- - arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts -+++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts -@@ -16,6 +16,10 @@ - label-mac-device = &fec1; - }; - -+ chosen { -+ stdout-path = "serial4:115200n8"; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; diff --git a/target/linux/imx/patches-6.6/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch b/target/linux/imx/patches-6.6/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch deleted file mode 100644 index 36025a185c..0000000000 --- a/target/linux/imx/patches-6.6/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 60fd951029603a0a6e019f16d53fb329dbd001f4 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Fri, 7 Jul 2023 16:24:19 -0700 -Subject: [PATCH 400/413] 6.7: arm64: dts: imx8mp: add - imx8mp-venice-gw74xx-imx219 overlay for rpi v2 camera - -Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - - has its own on-board 24MHz osc so no clock required from baseboard - - pin 11 enables 1.8V and 2.8V LDO which is connected to - GW74xx MIPI_GPIO4 (IMX8MP GPIO1_IO4) so we use this as a gpio - -Support is added via a device-tree overlay. - -The IMX219 supports RAW8/RAW10 image formats. - -Example configuration: -media-ctl -l "'imx219 3-0010':0->'csis-32e40000.csi':0[1]" -media-ctl -v -V "'imx219 3-0010':0 [fmt:SRGGB8/640x480 field:none]" -media-ctl -v -V "'crossbar':0 [fmt:SRGGB8/640x480 field:none]" -media-ctl -v -V "'mxc_isi.0':0 [fmt:SRGGB8/640x480 field:none]" -v4l2-ctl --set-fmt-video=width=640,height=480,pixelformat=RGGB -v4l2-ctl --stream-mmap --stream-to=frame.raw --stream-count=1 -convert -size 640x480 -depth 8 gray:frame.raw frame.png -gst-launch-1.0 v4l2src ! \ - video/x-bayer,format=rggb,width=640,height=480,framerate=10/1 ! \ - bayer2rgb ! fbdevsink - -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/Makefile | 2 + - .../imx8mp-venice-gw74xx-imx219.dtso | 80 +++++++++++++++++++ - 2 files changed, 82 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso - ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -159,6 +159,7 @@ imx8mm-venice-gw73xx-0x-rpidsi-dtbs := i - imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo - imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo - imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo -+imx8mp-venice-gw74xx-imx219-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-imx219.dtbo - imx8mp-venice-gw74xx-rpidsi-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo - - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb -@@ -171,6 +172,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice- - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb - - dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso -@@ -0,0 +1,80 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+#include -+ -+#include "imx8mp-pinfunc.h" -+ -+/dts-v1/; -+/plugin/; -+ -+&{/} { -+ compatible = "gw,imx8mp-gw74xx", "fsl,imx8mp"; -+ -+ reg_cam: regulator-cam { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_cam>; -+ compatible = "regulator-fixed"; -+ regulator-name = "reg_cam"; -+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ cam24m: cam24m { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "cam24m"; -+ }; -+}; -+ -+&i2c4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ imx219: sensor@10 { -+ compatible = "sony,imx219"; -+ reg = <0x10>; -+ clocks = <&cam24m>; -+ VDIG-supply = <®_cam>; -+ -+ port { -+ /* MIPI CSI-2 bus endpoint */ -+ imx219_to_mipi_csi2: endpoint { -+ remote-endpoint = <&mipi_csi_0_in>; -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ link-frequencies = /bits/ 64 <456000000>; -+ }; -+ }; -+ }; -+}; -+ -+&isi_0 { -+ status = "okay"; -+}; -+ -+&mipi_csi_0 { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ mipi_csi_0_in: endpoint { -+ remote-endpoint = <&imx219_to_mipi_csi2>; -+ data-lanes = <1 2>; -+ }; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl_reg_cam: regcamgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41 -+ >; -+ }; -+}; diff --git a/target/linux/imx/patches-6.6/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch deleted file mode 100644 index 782573f6d0..0000000000 --- a/target/linux/imx/patches-6.6/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 816e40232faaa4aa0364ca8da7f86eaf27b0d9ff Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Mon, 26 Jun 2023 11:51:13 -0700 -Subject: [PATCH 401/413] 6.7: arm64: dts: imx8mm-venice-gw73xx: add TPM device - -Add the TPM device found on the GW73xx revision F PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi -@@ -104,8 +104,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio1 { -@@ -362,6 +369,7 @@ - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 -+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - diff --git a/target/linux/imx/patches-6.6/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch deleted file mode 100644 index a106c0bc21..0000000000 --- a/target/linux/imx/patches-6.6/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 916ffc08e8cdd3beccd78291eac9dc5592d83de1 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 24 Aug 2023 11:07:48 -0700 -Subject: [PATCH 402/413] 6.7: arm64: dts: imx8mp-venice-gw73xx: add TPM device - -Add the TPM device found on the GW73xx revision F PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -@@ -95,8 +95,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio4 { -@@ -327,6 +334,7 @@ - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - diff --git a/target/linux/imx/patches-6.6/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch deleted file mode 100644 index 01b79e26e8..0000000000 --- a/target/linux/imx/patches-6.6/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0adf19579692623d9d9202d2868aa7cd81451148 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 28 Sep 2023 14:10:39 -0700 -Subject: [PATCH 403/413] 6.8: arm64: dts: imx8mm-venice-gw72xx: add TPM device - -Add the TPM device found on the GW72xx revision F PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi -@@ -84,8 +84,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio1 { -@@ -313,6 +320,7 @@ - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 -+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - diff --git a/target/linux/imx/patches-6.6/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch deleted file mode 100644 index 1e399f72f5..0000000000 --- a/target/linux/imx/patches-6.6/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 9d3932717327f6086a9a81a41df5bf5250aee782 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 28 Sep 2023 14:11:01 -0700 -Subject: [PATCH 404/413] 6.8: arm64: dts: imx8mp-venice-gw72xx: add TPM device - -Add the TPM device found on the GW72xx revision F PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -@@ -83,8 +83,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio4 { -@@ -286,6 +293,7 @@ - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - diff --git a/target/linux/imx/patches-6.6/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch deleted file mode 100644 index 57ad826668..0000000000 --- a/target/linux/imx/patches-6.6/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 6cea7c46172eca323e9ce7e6aab8f8506eb92b4b Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 29 Nov 2023 09:53:04 -0800 -Subject: [PATCH 405/413] 6.9: arm64: dts: imx8mm-venice-gw71xx: add TPM device - -Add the TPM device found on the GW71xx revision E PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi -@@ -53,8 +53,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio1 { -@@ -201,6 +208,7 @@ - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 -+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - diff --git a/target/linux/imx/patches-6.6/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch b/target/linux/imx/patches-6.6/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch deleted file mode 100644 index b96fc907a4..0000000000 --- a/target/linux/imx/patches-6.6/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 9095a68c0b7084a7819e697ef38d0c987531c8ab Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 29 Nov 2023 17:11:51 -0800 -Subject: [PATCH 406/413] 6.9: arm64: dts: imx8mp-venice-gw71xx: add TPM device - -Add the TPM device found on the GW71xx revision E PCB. - -Signed-off-by: Tim Harvey ---- - .../arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi -@@ -48,8 +48,15 @@ - &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &gpio4 { -@@ -217,6 +224,7 @@ - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - diff --git a/target/linux/imx/patches-6.6/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch b/target/linux/imx/patches-6.6/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch deleted file mode 100644 index ebee3c4be1..0000000000 --- a/target/linux/imx/patches-6.6/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch +++ /dev/null @@ -1,34 +0,0 @@ -From e5bc89e60590581b0d31e8c6c6361c6caf5583bb Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Tue, 21 Nov 2023 11:12:24 -0800 -Subject: [PATCH 407/413] 6.9: arm64: dts: imx8mm-venice-gw7901: add digital - I/O direction control GPIO's - -The GW7901 has GPIO's to configure the direction of its isolated -digital I/O signals. Add the GPIO pinmux and line names. - -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -@@ -319,7 +319,7 @@ - - &gpio4 { - gpio-line-names = "", "", "", "", -- "", "", "uart3_rs232#", "uart3_rs422#", -+ "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#", - "uart3_rs485#", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; -@@ -842,6 +842,8 @@ - - pinctrl_hog: hoggrp { - fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */ -+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */ - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ diff --git a/target/linux/imx/patches-6.6/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch b/target/linux/imx/patches-6.6/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch deleted file mode 100644 index e86c29fbb8..0000000000 --- a/target/linux/imx/patches-6.6/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch +++ /dev/null @@ -1,45 +0,0 @@ -From f905e9a03cdf8edf6fa719ba89f37e6138c33834 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Tue, 21 Nov 2023 11:44:38 -0800 -Subject: [PATCH 408/413] 6.9: arm64: dts: imx8mm-venice-gw7901: add TPM device - -Add the TPM device found on the GW7901 revision D PCB. - -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -@@ -285,7 +285,8 @@ - &ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; -- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; -+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, -+ <&gpio4 24 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { -@@ -294,6 +295,12 @@ - spi-max-frequency = <40000000>; - status = "okay"; - }; -+ -+ tpm@1 { -+ compatible = "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; - }; - - &fec1 { -@@ -989,6 +996,7 @@ - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 -+ MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 - >; - }; - diff --git a/target/linux/imx/patches-6.6/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch b/target/linux/imx/patches-6.6/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch deleted file mode 100644 index 2c63d7c339..0000000000 --- a/target/linux/imx/patches-6.6/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch +++ /dev/null @@ -1,38 +0,0 @@ -From fddb089c2ccfb8bc4bd3aba605f7eadfd9f36cfd Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 28 Feb 2024 10:22:11 -0800 -Subject: [PATCH 409/413] 6.9: arm64: dts: freescale: imx8mp-venice-gw72xx-2x: - fix USB vbus regulator - -When using usb-conn-gpio to control USB role and VBUS, the vbus-supply -property must be present in the usb-conn-gpio node. Additionally it -should not be present in the phy node as that isn't what controls vbus -and will upset the use count. - -This resolves an issue where VBUS is enabled with OTG in peripheral -mode. - -Fixes: 86c43ae03ab9 ("arm64: dts: freescale: Add imx8mp-venice-gw72xx-2x") -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -@@ -169,7 +169,6 @@ - }; - - &usb3_phy0 { -- vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; - -@@ -189,6 +188,7 @@ - pinctrl-0 = <&pinctrl_usbcon1>; - type = "micro"; - label = "otg"; -+ vbus-supply = <®_usb1_vbus>; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/target/linux/imx/patches-6.6/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch b/target/linux/imx/patches-6.6/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch deleted file mode 100644 index 53851b9d1b..0000000000 --- a/target/linux/imx/patches-6.6/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 69e3ce6d0c2f518bf9574112f3d4cc619c38602c Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 28 Feb 2024 10:24:19 -0800 -Subject: [PATCH 410/413] 6.9: arm64: dts: freescale: imx8mp-venice-gw73xx-2x: - fix USB vbus regulator - -When using usb-conn-gpio to control USB role and VBUS, the vbus-supply -property must be present in the usb-conn-gpio node. Additionally it -should not be present in the phy node as that isn't what controls vbus -and will upset the use count. - -This resolves an issue where VBUS is enabled with OTG in peripheral -mode. - -Fixes: 716ced308234 ("arm64: dts: freescale: Add imx8mp-venice-gw73xx-2x") -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -@@ -188,7 +188,6 @@ - }; - - &usb3_phy0 { -- vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; - -@@ -208,6 +207,7 @@ - pinctrl-0 = <&pinctrl_usbcon1>; - type = "micro"; - label = "otg"; -+ vbus-supply = <®_usb1_vbus>; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/target/linux/imx/patches-6.6/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch b/target/linux/imx/patches-6.6/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch deleted file mode 100644 index afebad1748..0000000000 --- a/target/linux/imx/patches-6.6/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 9d75bdd797d32c859d0dd9f54acc30de63831eb1 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Mon, 29 Jan 2024 15:28:39 -0800 -Subject: [PATCH 411/413] 6.10: arm64: dts: imx8mp-venice-gw74xx: add ADC rail - for VDD_1P0 - -The imx8mp-venice-gw74xx revB PCB added an ADC rail for -VDD_1P0. Add it to the GSC ADC rails. - -Fixes: 531936b218d8 ("arm64: dts: imx8mp-venice-gw74xx: update to revB PCB") -Signed-off-by: Tim Harvey ---- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -@@ -391,6 +391,12 @@ - label = "vdd_dram"; - }; - -+ channel@9e { -+ gw,mode = <2>; -+ reg = <0x9e>; -+ label = "vdd_1p0"; -+ }; -+ - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; diff --git a/target/linux/imx/patches-6.6/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch b/target/linux/imx/patches-6.6/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch deleted file mode 100644 index 567571c15e..0000000000 --- a/target/linux/imx/patches-6.6/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 482fe0cb90d3376051304531a01edccac9ca1868 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 29 Feb 2024 10:05:26 -0800 -Subject: [PATCH 412/413] 6.10: arm64: dts: imx8mp-venice-gw72xx: add mac addr - for eth1 - -Add the PCI bus topology for eth1 so that boot firmware can set the -local-mac-address property. - -The eth1 device is behind a PCI switch: - # lspci -n - 00:00.0 0604: 16c3:abcd (rev 01) - 01:00.0 0604: 12d8:b404 (rev 01) - 02:01.0 0604: 12d8:b404 (rev 01) - 02:02.0 0604: 12d8:b404 (rev 01) - 02:03.0 0604: 12d8:b404 (rev 01) - 05:00.0 0200: 11ab:4380 - # lspci -t - -[0000:00]---00.0-[01-ff]----00.0-[02-05]--+-01.0-[03]-- - +-02.0-[04]-- - \-03.0-[05]----00.0 - -Signed-off-by: Tim Harvey ---- - .../dts/freescale/imx8mp-venice-gw72xx.dtsi | 37 +++++++++++++++++++ - 1 file changed, 37 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi -@@ -8,6 +8,10 @@ - #include - - / { -+ aliases { -+ ethernet1 = ð1; -+ }; -+ - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -137,6 +141,39 @@ - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@3,0 { -+ reg = <0x1800 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ eth1: ethernet@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ local-mac-address = [00 00 00 00 00 00]; -+ }; -+ }; -+ }; -+ }; - }; - - /* GPS */ diff --git a/target/linux/imx/patches-6.6/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch b/target/linux/imx/patches-6.6/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch deleted file mode 100644 index faf9373ec3..0000000000 --- a/target/linux/imx/patches-6.6/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch +++ /dev/null @@ -1,82 +0,0 @@ -From caac9b614ee63f875b290fda429706f6ef36e2f1 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 29 Feb 2024 10:12:49 -0800 -Subject: [PATCH 413/413] 6.10: arm64: dts: imx8mp-venice-gw73xx: add mac addr - for eth1 - -Add the PCI bus topology for eth1 so that boot firmware can set the -local-mac-address property. - -The eth1 device is behind a PCI switch: - # lspci -n - 00:00.0 0604: 16c3:abcd (rev 01) - 01:00.0 0604: 12d8:2608 - 02:01.0 0604: 12d8:2608 - 02:02.0 0604: 12d8:2608 - 02:03.0 0604: 12d8:2608 - 02:04.0 0604: 12d8:2608 - c0:00.0 0200: 1055:7430 (rev 11) - # lspci -t - -[0000:00]---00.0-[01-ff]----00.0-[02-fe]--+-01.0-[03-41]-- - +-02.0-[42-80]-- - +-03.0-[81-bf]-- - \-04.0-[c0-fe]----00.0 - -Signed-off-by: Tim Harvey ---- - .../dts/freescale/imx8mp-venice-gw73xx.dtsi | 37 +++++++++++++++++++ - 1 file changed, 37 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi -@@ -8,6 +8,10 @@ - #include - - / { -+ aliases { -+ ethernet1 = ð1; -+ }; -+ - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -149,6 +153,39 @@ - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@4,0 { -+ reg = <0x2000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ eth1: ethernet@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ local-mac-address = [00 00 00 00 00 00]; -+ }; -+ }; -+ }; -+ }; - }; - - /* GPS */ diff --git a/target/linux/imx/patches-6.6/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch b/target/linux/imx/patches-6.6/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch deleted file mode 100644 index 2d398defc4..0000000000 --- a/target/linux/imx/patches-6.6/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 82b521f4bb8cab09aa016acf2c1b55ffc736eb2e Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Mon, 9 Sep 2024 15:15:01 -0700 -Subject: [PATCH] arm64: dts: imx8mm-venice-*: add RTC aliases - -Add aliases for the RTCs on the Gateworks Venice boards and on the imx8m -SoC. This ensures that the primary RTC is always the one on-board -provided by the Gateworks System Controller (GSC) which is battery -backed as opposed to the one in the IMX8M. - -Signed-off-by: Tim Harvey -Signed-off-by: Shawn Guo ---- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi | 7 ++++++- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 4 +++- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 4 +++- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 4 +++- - arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts | 7 ++++++- - arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 4 +++- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi | 4 +++- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 4 +++- - 8 files changed, 30 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi -@@ -8,6 +8,11 @@ - #include - - / { -+ aliases { -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; -+ }; -+ - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; -@@ -272,7 +277,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts -@@ -22,6 +22,8 @@ - ethernet2 = &lan2; - ethernet3 = &lan3; - ethernet4 = &lan4; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; -@@ -495,7 +497,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts -@@ -19,6 +19,8 @@ - - aliases { - ethernet1 = ð1; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; -@@ -562,7 +564,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts -@@ -18,6 +18,8 @@ - - aliases { - ethernet0 = &fec1; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - usb0 = &usbotg1; - }; - -@@ -392,7 +394,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts -@@ -16,6 +16,11 @@ - model = "Gateworks Venice GW7904 i.MX8MM board"; - compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm"; - -+ aliases { -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; -+ }; -+ - chosen { - stdout-path = &uart2; - }; -@@ -436,7 +441,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts -@@ -17,6 +17,8 @@ - compatible = "gw,imx8mn-gw7902", "fsl,imx8mn"; - - aliases { -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - usb0 = &usbotg1; - }; - -@@ -560,7 +562,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi -@@ -10,6 +10,8 @@ - / { - aliases { - ethernet0 = &eqos; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - }; - - memory@40000000 { -@@ -260,7 +262,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -@@ -24,6 +24,8 @@ - ethernet4 = &lan3; - ethernet5 = &lan4; - ethernet6 = &lan5; -+ rtc0 = &gsc_rtc; -+ rtc1 = &snvs_rtc; - }; - - chosen { -@@ -444,7 +446,7 @@ - pagesize = <16>; - }; - -- rtc@68 { -+ gsc_rtc: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; diff --git a/target/linux/imx/patches-6.6/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch b/target/linux/imx/patches-6.6/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch deleted file mode 100644 index 14c8f88e31..0000000000 --- a/target/linux/imx/patches-6.6/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e6d8fd29bd3d796a00ff9b69f9fae011aec3cb40 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 5 Sep 2024 11:32:28 -0700 -Subject: [PATCH] arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio - configuration - -The GW74xx D revision has added a M2SKT_GPIO10 GPIO which routes to the -GPIO10 pin of the M.2 socket for compatibility with certain devices. - -Add the iomux and a line name for this. - -Signed-off-by: Tim Harvey -Signed-off-by: Shawn Guo ---- - arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts -@@ -264,7 +264,7 @@ - &gpio3 { - gpio-line-names = - "", "", "", "", "", "", "m2_rst", "", -- "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "m2_gpio10", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; -@@ -786,6 +786,7 @@ - MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ - MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ - MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ -+ MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_GPIO10 */ - MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ - MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ - MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ diff --git a/target/linux/imx/patches-6.6/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch b/target/linux/imx/patches-6.6/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch deleted file mode 100644 index 056b85002e..0000000000 --- a/target/linux/imx/patches-6.6/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch +++ /dev/null @@ -1,1426 +0,0 @@ -From 14c3de96e14b30b1b83016abe607034a5a7e1c6b Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Wed, 24 Jan 2024 10:16:03 -0800 -Subject: [PATCH] arm64: dts: freescale: rename gw7905 to gw75xx - -The GW7905 was renamed to GW7500 before production release. - -Signed-off-by: Tim Harvey ---- - Documentation/devicetree/bindings/arm/fsl.yaml | 4 ++-- - arch/arm64/boot/dts/freescale/Makefile | 4 ++-- - ...8mm-venice-gw7905-0x.dts => imx8mm-venice-gw75xx-0x.dts} | 6 +++--- - ...{imx8mm-venice-gw7905.dtsi => imx8mm-venice-gw75xx.dtsi} | 0 - ...8mp-venice-gw7905-2x.dts => imx8mp-venice-gw75xx-2x.dts} | 6 +++--- - ...{imx8mp-venice-gw7905.dtsi => imx8mp-venice-gw75xx.dtsi} | 0 - 6 files changed, 10 insertions(+), 10 deletions(-) - rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw7905-0x.dts => imx8mm-venice-gw75xx-0x.dts} (67%) - rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw7905.dtsi => imx8mm-venice-gw75xx.dtsi} (100%) - rename arch/arm64/boot/dts/freescale/{imx8mp-venice-gw7905-2x.dts => imx8mp-venice-gw75xx-2x.dts} (67%) - rename arch/arm64/boot/dts/freescale/{imx8mp-venice-gw7905.dtsi => imx8mp-venice-gw75xx.dtsi} (100%) - ---- a/Documentation/devicetree/bindings/arm/fsl.yaml -+++ b/Documentation/devicetree/bindings/arm/fsl.yaml -@@ -908,8 +908,8 @@ properties: - - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - - fsl,imx8mm-evk # i.MX8MM EVK Board - - fsl,imx8mm-evkb # i.MX8MM EVKB Board -+ - gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board - - gateworks,imx8mm-gw7904 -- - gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board - - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit - - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit -@@ -1036,7 +1036,7 @@ properties: - - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board - - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board - - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board -- - gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board -+ - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -72,11 +72,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw75xx-0x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7905-0x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb -@@ -107,7 +107,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice- - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb --dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905-0x.dts -+++ /dev/null -@@ -1,28 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright 2023 Gateworks Corporation -- */ -- --/dts-v1/; -- --#include "imx8mm.dtsi" --#include "imx8mm-venice-gw700x.dtsi" --#include "imx8mm-venice-gw7905.dtsi" -- --/ { -- model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit"; -- compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm"; -- -- chosen { -- stdout-path = &uart2; -- }; --}; -- --/* Disable SOM interfaces not used on baseboard */ --&fec1 { -- status = "disabled"; --}; -- --&usdhc1 { -- status = "disabled"; --}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dts -@@ -0,0 +1,28 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm.dtsi" -+#include "imx8mm-venice-gw700x.dtsi" -+#include "imx8mm-venice-gw75xx.dtsi" -+ -+/ { -+ model = "Gateworks Venice GW75xx-0x i.MX8MM Development Kit"; -+ compatible = "gateworks,imx8mm-gw75xx-0x", "fsl,imx8mm"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+}; -+ -+/* Disable SOM interfaces not used on baseboard */ -+&fec1 { -+ status = "disabled"; -+}; -+ -+&usdhc1 { -+ status = "disabled"; -+}; ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts -+++ /dev/null -@@ -1,28 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright 2023 Gateworks Corporation -- */ -- --/dts-v1/; -- --#include "imx8mp.dtsi" --#include "imx8mp-venice-gw702x.dtsi" --#include "imx8mp-venice-gw7905.dtsi" -- --/ { -- model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit"; -- compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp"; -- -- chosen { -- stdout-path = &uart2; -- }; --}; -- --/* Disable SOM interfaces not used on baseboard */ --&eqos { -- status = "disabled"; --}; -- --&usdhc1 { -- status = "disabled"; --}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dts -@@ -0,0 +1,28 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mp.dtsi" -+#include "imx8mp-venice-gw702x.dtsi" -+#include "imx8mp-venice-gw75xx.dtsi" -+ -+/ { -+ model = "Gateworks Venice GW75xx-2x i.MX8MP Development Kit"; -+ compatible = "gateworks,imx8mp-gw75xx-2x", "fsl,imx8mp"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+}; -+ -+/* Disable SOM interfaces not used on baseboard */ -+&eqos { -+ status = "disabled"; -+}; -+ -+&usdhc1 { -+ status = "disabled"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi -@@ -0,0 +1,303 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+#include -+#include -+#include -+ -+/ { -+ led-controller { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ -+ led-0 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ pcie0_refclk: clock-pcie0 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pps>; -+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+ reg_usb2_vbus: regulator-usb2-vbus { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb2_en>; -+ regulator-name = "usb2_vbus"; -+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usdhc2_vmmc: regulator-usdhc2 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; -+ regulator-name = "SD2_3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+}; -+ -+/* off-board header */ -+&ecspi2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spi2>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "gpioa", "gpiob", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ "", "", "", "pci_usb_sel", -+ "", "", "", "pci_wdis#", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio5 { -+ gpio-line-names = -+ "", "", "", "", -+ "gpioc", "gpiod", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ eeprom@52 { -+ compatible = "atmel,24c32"; -+ reg = <0x52>; -+ pagesize = <32>; -+ }; -+}; -+ -+/* off-board header */ -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ fsl,refclk-pad-mode = ; -+ fsl,clkreq-unsupported; -+ clocks = <&pcie0_refclk>; -+ clock-names = "ref"; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+/* GPS */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+/* USB1 - Type C front panel SINK port J14 */ -+&usbotg1 { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+/* USB2 4-port USB3.0 HUB: -+ * P1 - USBC connector (host only) -+ * P2 - USB2 test connector -+ * P3 - miniPCIe full card -+ * P4 - miniPCIe half card -+ */ -+&usbotg2 { -+ dr_mode = "host"; -+ vbus-supply = <®_usb2_vbus>; -+ status = "okay"; -+}; -+ -+/* microSD */ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ -+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ -+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ -+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ -+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ -+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ -+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 -+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 -+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_pcie0: pciegrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 -+ >; -+ }; -+ -+ pinctrl_pps: ppsgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 -+ >; -+ }; -+ -+ pinctrl_reg_usb2_en: regusb2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ -+ >; -+ }; -+ -+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 -+ >; -+ }; -+ -+ pinctrl_spi2: spi2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 -+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 -+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 -+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 -+ >; -+ }; -+}; ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905.dtsi -+++ /dev/null -@@ -1,303 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright 2023 Gateworks Corporation -- */ -- --#include --#include --#include -- --/ { -- led-controller { -- compatible = "gpio-leds"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gpio_leds>; -- -- led-0 { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; -- default-state = "on"; -- linux,default-trigger = "heartbeat"; -- }; -- -- led-1 { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- }; -- -- pcie0_refclk: clock-pcie0 { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-frequency = <100000000>; -- }; -- -- pps { -- compatible = "pps-gpio"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_pps>; -- gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; -- status = "okay"; -- }; -- -- reg_usb2_vbus: regulator-usb2-vbus { -- compatible = "regulator-fixed"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_reg_usb2_en>; -- regulator-name = "usb2_vbus"; -- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; -- enable-active-high; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- }; -- -- reg_usdhc2_vmmc: regulator-usdhc2 { -- compatible = "regulator-fixed"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; -- regulator-name = "SD2_3P3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -- enable-active-high; -- }; --}; -- --/* off-board header */ --&ecspi2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -- status = "okay"; --}; -- --&gpio1 { -- gpio-line-names = -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "gpioa", "gpiob", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio4 { -- gpio-line-names = -- "", "", "", "pci_usb_sel", -- "", "", "", "pci_wdis#", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio5 { -- gpio-line-names = -- "", "", "", "", -- "gpioc", "gpiod", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", ""; --}; -- --&i2c2 { -- clock-frequency = <400000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_i2c2>; -- status = "okay"; -- -- eeprom@52 { -- compatible = "atmel,24c32"; -- reg = <0x52>; -- pagesize = <32>; -- }; --}; -- --/* off-board header */ --&i2c3 { -- clock-frequency = <400000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_i2c3>; -- status = "okay"; --}; -- --&pcie_phy { -- fsl,refclk-pad-mode = ; -- fsl,clkreq-unsupported; -- clocks = <&pcie0_refclk>; -- clock-names = "ref"; -- status = "okay"; --}; -- --&pcie0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_pcie0>; -- reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; -- status = "okay"; --}; -- --/* GPS */ --&uart1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_uart1>; -- status = "okay"; --}; -- --/* USB1 - Type C front panel SINK port J14 */ --&usbotg1 { -- dr_mode = "peripheral"; -- status = "okay"; --}; -- --/* USB2 4-port USB3.0 HUB: -- * P1 - USBC connector (host only) -- * P2 - USB2 test connector -- * P3 - miniPCIe full card -- * P4 - miniPCIe half card -- */ --&usbotg2 { -- dr_mode = "host"; -- vbus-supply = <®_usb2_vbus>; -- status = "okay"; --}; -- --/* microSD */ --&usdhc2 { -- pinctrl-names = "default", "state_100mhz", "state_200mhz"; -- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -- vmmc-supply = <®_usdhc2_vmmc>; -- bus-width = <4>; -- status = "okay"; --}; -- --&iomuxc { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_hog>; -- -- pinctrl_hog: hoggrp { -- fsl,pins = < -- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ -- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ -- MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ -- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ -- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ -- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ -- >; -- }; -- -- pinctrl_gpio_leds: gpioledgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ -- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ -- >; -- }; -- -- pinctrl_i2c2: i2c2grp { -- fsl,pins = < -- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 -- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 -- >; -- }; -- -- pinctrl_i2c3: i2c3grp { -- fsl,pins = < -- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 -- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 -- >; -- }; -- -- pinctrl_pcie0: pciegrp { -- fsl,pins = < -- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 -- >; -- }; -- -- pinctrl_pps: ppsgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 -- >; -- }; -- -- pinctrl_reg_usb2_en: regusb2grp { -- fsl,pins = < -- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ -- >; -- }; -- -- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 -- >; -- }; -- -- pinctrl_spi2: spi2grp { -- fsl,pins = < -- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 -- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 -- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 -- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 -- >; -- }; -- -- pinctrl_uart1: uart1grp { -- fsl,pins = < -- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -- >; -- }; -- -- pinctrl_usdhc2: usdhc2grp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_gpio: usdhc2gpiogrp { -- fsl,pins = < -- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 -- >; -- }; --}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi -@@ -0,0 +1,309 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2023 Gateworks Corporation -+ */ -+ -+#include -+#include -+#include -+ -+/ { -+ led-controller { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ -+ led-0 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pps>; -+ gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+ reg_usb2_vbus: regulator-usb2-vbus { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb2_en>; -+ compatible = "regulator-fixed"; -+ regulator-name = "usb2_vbus"; -+ gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usdhc2_vmmc: regulator-usdhc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; -+ compatible = "regulator-fixed"; -+ regulator-name = "SD2_3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+}; -+ -+/* off-board header */ -+&ecspi2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spi2>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "gpioa", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ "", "gpiod", "", "", -+ "gpiob", "gpioc", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "pci_usb_sel", "", -+ "pci_wdis#", "", "", ""; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ eeprom@52 { -+ compatible = "atmel,24c32"; -+ reg = <0x52>; -+ pagesize = <32>; -+ }; -+}; -+ -+/* off-board header */ -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ fsl,refclk-pad-mode = ; -+ fsl,clkreq-unsupported; -+ clocks = <&pcie0_refclk>; -+ clock-names = "ref"; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+/* GPS */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+/* USB1 - Type C front panel SINK port J14 */ -+&usb3_0 { -+ status = "okay"; -+}; -+ -+&usb3_phy0 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_0 { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+/* USB2 4-port USB3.0 HUB: -+ * P1 - USBC connector (host only) -+ * P2 - USB2 test connector -+ * P3 - miniPCIe full card -+ * P4 - miniPCIe half card -+ */ -+&usb3_phy1 { -+ vbus-supply = <®_usb2_vbus>; -+ status = "okay"; -+}; -+ -+&usb3_1 { -+ fsl,permanently-attached; -+ fsl,disable-port-power-control; -+ status = "okay"; -+}; -+ -+&usb_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+/* microSD */ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ -+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ -+ MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ -+ MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ -+ MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ -+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ -+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 -+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 -+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 -+ >; -+ }; -+ -+ pinctrl_pcie0: pciegrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 -+ >; -+ }; -+ -+ pinctrl_pps: ppsgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 -+ >; -+ }; -+ -+ pinctrl_reg_usb2_en: regusb2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ -+ >; -+ }; -+ -+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 -+ >; -+ }; -+ -+ pinctrl_spi2: spi2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 -+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 -+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 -+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 -+ >; -+ }; -+}; ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi -+++ /dev/null -@@ -1,309 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --/* -- * Copyright 2023 Gateworks Corporation -- */ -- --#include --#include --#include -- --/ { -- led-controller { -- compatible = "gpio-leds"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gpio_leds>; -- -- led-0 { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; -- default-state = "on"; -- linux,default-trigger = "heartbeat"; -- }; -- -- led-1 { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- }; -- -- pcie0_refclk: pcie0-refclk { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-frequency = <100000000>; -- }; -- -- pps { -- compatible = "pps-gpio"; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_pps>; -- gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; -- status = "okay"; -- }; -- -- reg_usb2_vbus: regulator-usb2-vbus { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_reg_usb2_en>; -- compatible = "regulator-fixed"; -- regulator-name = "usb2_vbus"; -- gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; -- enable-active-high; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- }; -- -- reg_usdhc2_vmmc: regulator-usdhc2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; -- compatible = "regulator-fixed"; -- regulator-name = "SD2_3P3V"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -- enable-active-high; -- }; --}; -- --/* off-board header */ --&ecspi2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_spi2>; -- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; -- status = "okay"; --}; -- --&gpio4 { -- gpio-line-names = -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "gpioa", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio4 { -- gpio-line-names = -- "", "gpiod", "", "", -- "gpiob", "gpioc", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "", "", -- "", "", "pci_usb_sel", "", -- "pci_wdis#", "", "", ""; --}; -- --&i2c2 { -- clock-frequency = <400000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_i2c2>; -- status = "okay"; -- -- eeprom@52 { -- compatible = "atmel,24c32"; -- reg = <0x52>; -- pagesize = <32>; -- }; --}; -- --/* off-board header */ --&i2c3 { -- clock-frequency = <400000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_i2c3>; -- status = "okay"; --}; -- --&pcie_phy { -- fsl,refclk-pad-mode = ; -- fsl,clkreq-unsupported; -- clocks = <&pcie0_refclk>; -- clock-names = "ref"; -- status = "okay"; --}; -- --&pcie { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_pcie0>; -- reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; -- status = "okay"; --}; -- --/* GPS */ --&uart1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_uart1>; -- status = "okay"; --}; -- --/* USB1 - Type C front panel SINK port J14 */ --&usb3_0 { -- status = "okay"; --}; -- --&usb3_phy0 { -- status = "okay"; --}; -- --&usb_dwc3_0 { -- dr_mode = "peripheral"; -- status = "okay"; --}; -- --/* USB2 4-port USB3.0 HUB: -- * P1 - USBC connector (host only) -- * P2 - USB2 test connector -- * P3 - miniPCIe full card -- * P4 - miniPCIe half card -- */ --&usb3_phy1 { -- vbus-supply = <®_usb2_vbus>; -- status = "okay"; --}; -- --&usb3_1 { -- fsl,permanently-attached; -- fsl,disable-port-power-control; -- status = "okay"; --}; -- --&usb_dwc3_1 { -- dr_mode = "host"; -- status = "okay"; --}; -- --/* microSD */ --&usdhc2 { -- pinctrl-names = "default", "state_100mhz", "state_200mhz"; -- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -- vmmc-supply = <®_usdhc2_vmmc>; -- bus-width = <4>; -- status = "okay"; --}; -- --&iomuxc { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_hog>; -- -- pinctrl_hog: hoggrp { -- fsl,pins = < -- MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ -- MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ -- MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ -- MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ -- MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ -- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ -- >; -- }; -- -- pinctrl_gpio_leds: gpioledgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ -- MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ -- >; -- }; -- -- pinctrl_i2c2: i2c2grp { -- fsl,pins = < -- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 -- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 -- >; -- }; -- -- pinctrl_i2c3: i2c3grp { -- fsl,pins = < -- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 -- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 -- >; -- }; -- -- pinctrl_pcie0: pciegrp { -- fsl,pins = < -- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 -- >; -- }; -- -- pinctrl_pps: ppsgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 -- >; -- }; -- -- pinctrl_reg_usb2_en: regusb2grp { -- fsl,pins = < -- MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ -- >; -- }; -- -- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 -- >; -- }; -- -- pinctrl_spi2: spi2grp { -- fsl,pins = < -- MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 -- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 -- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 -- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 -- >; -- }; -- -- pinctrl_uart1: uart1grp { -- fsl,pins = < -- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 -- >; -- }; -- -- pinctrl_usdhc2: usdhc2grp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 -- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 -- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 -- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 -- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 -- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 -- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 -- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 -- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 -- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 -- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 -- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 -- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 -- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 -- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 -- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 -- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 -- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 -- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 -- >; -- }; -- -- pinctrl_usdhc2_gpio: usdhc2gpiogrp { -- fsl,pins = < -- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 -- >; -- }; --}; diff --git a/target/linux/imx/patches-6.6/503-6.13-arm64-dts-imx8m-venice-gw75xx-add-Accelerometer-device.patch b/target/linux/imx/patches-6.6/503-6.13-arm64-dts-imx8m-venice-gw75xx-add-Accelerometer-device.patch deleted file mode 100644 index f30b690423..0000000000 --- a/target/linux/imx/patches-6.6/503-6.13-arm64-dts-imx8m-venice-gw75xx-add-Accelerometer-device.patch +++ /dev/null @@ -1,79 +0,0 @@ -From ede044113c0418f11dbee09069ff1dd68f284dfa Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Fri, 18 Oct 2024 10:36:08 -0700 -Subject: [PATCH] arm64: dts: imx8m*-venice-gw75xx: add Accelerometer device - -The GW75xx has a LIS2DE12TR 3-axis accelerometer on the I2C bus with an -interrupt pin. Add it to the device-tree. - -Signed-off-by: Tim Harvey -Signed-off-by: Shawn Guo ---- - .../boot/dts/freescale/imx8mm-venice-gw75xx.dtsi | 16 ++++++++++++++++ - .../boot/dts/freescale/imx8mp-venice-gw75xx.dtsi | 16 ++++++++++++++++ - 2 files changed, 32 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi -@@ -116,6 +116,16 @@ - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - -+ accelerometer@19 { -+ compatible = "st,lis2de12"; -+ reg = <0x19>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_accel>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>; -+ st,drdy-int-pin = <1>; -+ }; -+ - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; -@@ -198,6 +208,12 @@ - >; - }; - -+ pinctrl_accel: accelgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x159 -+ >; -+ }; -+ - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ ---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi -@@ -104,6 +104,16 @@ - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - -+ accelerometer@19 { -+ compatible = "st,lis2de12"; -+ reg = <0x19>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_accel>; -+ interrupt-parent = <&gpio5>; -+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>; -+ st,drdy-int-pin = <1>; -+ }; -+ - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; -@@ -204,6 +214,12 @@ - >; - }; - -+ pinctrl_accel: accelgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x159 -+ >; -+ }; -+ - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ diff --git a/target/linux/imx/patches-6.6/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch b/target/linux/imx/patches-6.6/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch deleted file mode 100644 index 8765474a8a..0000000000 --- a/target/linux/imx/patches-6.6/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch +++ /dev/null @@ -1,1107 +0,0 @@ -From a79d2638a7150d1605fcadebb6baa36d27cdc48e Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Thu, 30 May 2024 10:21:45 -0700 -Subject: [PATCH] arm64: dts: imx: Add i.MX8M Plus Gateworks GW82XX-2X support - -The Gateworks GW82XX-2X is an ARM based single board computer (SBC) -comprised of the i.MX8M Plus based gw702x SoM and the gw82xx -baseboard featuring: - - i.MX8M Plus SoC - - LPDDR4 DRAM - - eMMC FLASH - - Gateworks System Controller (GSC) - - microSD (1.8V/3.3V Capable) - - panel status bi-color LED - - pushbutton switch - - fan controller with tachometer - - USB Type-C connector - - PCIe switch - - 2x GbE RJ45 connectors - - multi-protocol RS232/RS485/RS422 Serial ports - - 2x Flexible Socket Adapters with SDIO/UART/USB/PCIe - (for M.2 and miniPCIe expansion) - - 2x isolated CAN - - GPS - - accelerometer - - magnetometer - - off-board connectors for: SPI, GPIO, I2C, ADC - - Wide range DC power input - - support for 802.3at PoE (via adapter) - -Signed-off-by: Tim Harvey ---- - .../devicetree/bindings/arm/fsl.yaml | 1 + - arch/arm64/boot/dts/freescale/Makefile | 1 + - .../dts/freescale/imx8mm-venice-gw82xx.dtsi | 460 +++++++++++++++ - .../boot/dts/freescale/imx8mp-venice-gw82xx-2 | 19 + - .../dts/freescale/imx8mp-venice-gw82xx-2x.dts | 19 + - .../dts/freescale/imx8mp-venice-gw82xx.dtsi | 533 ++++++++++++++++++ - 6 files changed, 1033 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw82xx.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2 - create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts - create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi - ---- a/Documentation/devicetree/bindings/arm/fsl.yaml -+++ b/Documentation/devicetree/bindings/arm/fsl.yaml -@@ -1037,6 +1037,7 @@ properties: - - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board - - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board -+ - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board - - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice- - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb -+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw82xx-2x.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw82xx.dtsi -@@ -0,0 +1,460 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2020 Gateworks Corporation -+ */ -+ -+#include -+#include -+#include -+ -+/ { -+ aliases { -+ ethernet1 = ð1; -+ usb0 = &usbotg1; -+ usb1 = &usbotg2; -+ }; -+ -+ led-controller { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ -+ led-0 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ pcie0_refclk: pcie0-refclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pps>; -+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "1P8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_otg1_vbus: regulator-usb-otg1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb1_en>; -+ compatible = "regulator-fixed"; -+ regulator-name = "usb_otg1_vbus"; -+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usb_otg2_vbus: regulator-usb-otg2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb2_en>; -+ compatible = "regulator-fixed"; -+ regulator-name = "usb_otg2_vbus"; -+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_wifi_en: regulator-wifi-en { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_wl>; -+ compatible = "regulator-fixed"; -+ regulator-name = "wl"; -+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+}; -+ -+/* off-board header */ -+&ecspi2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spi2>; -+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, -+ <&gpio1 10 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ tpm@1 { -+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; -+ reg = <0x1>; -+ spi-max-frequency = <36000000>; -+ }; -+}; -+ -+&gpio1 { -+ gpio-line-names = "rs485_term", "mipi_gpio4", "", "", -+ "", "", "pci_usb_sel", "dio0", -+ "", "dio1", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", -+ "mipi_gpio1", "", "", "pci_wdis#", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ accelerometer@19 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_accel>; -+ compatible = "st,lis2de12"; -+ reg = <0x19>; -+ st,drdy-int-pin = <1>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>; -+ }; -+ -+ // TODO: 0x6f PCIe switch -+}; -+ -+/* off-board header */ -+// TODO: i2c expander -+&i2c3 { -+ clock-frequency = <400000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ fsl,refclk-pad-mode = ; -+ fsl,clkreq-unsupported; -+ clocks = <&pcie0_refclk>; -+ clock-names = "ref"; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; -+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, -+ <&clk IMX8MM_CLK_PCIE1_AUX>; -+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, -+ <&clk IMX8MM_CLK_PCIE1_CTRL>; -+ assigned-clock-rates = <10000000>, <250000000>; -+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, -+ <&clk IMX8MM_SYS_PLL2_250M>; -+ status = "okay"; -+ -+ // TODO: this changes - new switch -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@4,0 { -+ reg = <0x2000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ eth1: ethernet@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ local-mac-address = [00 00 00 00 00 00]; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+/* off-board header */ -+&sai3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sai3>; -+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>; -+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -+ assigned-clock-rates = <24576000>; -+ status = "okay"; -+}; -+ -+/* GPS */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+/* bluetooth HCI */ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; -+ cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; -+ rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4330-bt"; -+ shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+/* RS232 */ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart4>; -+ status = "okay"; -+}; -+ -+&usbotg1 { -+ dr_mode = "otg"; -+ over-current-active-low; -+ vbus-supply = <®_usb_otg1_vbus>; -+ status = "okay"; -+}; -+ -+&usbotg2 { -+ dr_mode = "host"; -+ disable-over-current; -+ vbus-supply = <®_usb_otg2_vbus>; -+ status = "okay"; -+}; -+ -+/* SDIO WiFi */ -+&usdhc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ bus-width = <4>; -+ non-removable; -+ vmmc-supply = <®_wifi_en>; -+ status = "okay"; -+}; -+ -+/* microSD */ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ vmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ -+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ -+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ -+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ -+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ -+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ -+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ -+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ -+ >; -+ }; -+ -+ pinctrl_accel: accelgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 -+ >; -+ }; -+ -+ pinctrl_bten: btengrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 -+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 -+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 -+ >; -+ }; -+ -+ pinctrl_pps: ppsgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 -+ >; -+ }; -+ -+ pinctrl_reg_wl: regwlgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 -+ >; -+ }; -+ -+ pinctrl_reg_usb1_en: regusb1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 -+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 -+ >; -+ }; -+ -+ pinctrl_reg_usb2_en: regusb2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 -+ >; -+ }; -+ -+ pinctrl_sai3: sai3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 -+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 -+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 -+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 -+ >; -+ }; -+ -+ pinctrl_spi2: spi2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 -+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 -+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 -+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 -+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 -+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140 -+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 -+ >; -+ }; -+ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 -+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 -+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 -+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 -+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 -+ MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 -+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 -+ >; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2 -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2024 Gateworks Corporation -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mm.dtsi" -+#include "imx8mm-venice-gw700x.dtsi" -+#include "imx8mm-venice-gw82xx.dtsi" -+ -+/ { -+ model = "Gateworks Venice GW82xx-0x i.MX8MM Development Kit"; -+ compatible = "gw,imx8mm-gw82xx-0x", "fsl,imx8mm"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2024 Gateworks Corporation -+ */ -+ -+/dts-v1/; -+ -+#include "imx8mp.dtsi" -+#include "imx8mp-venice-gw702x.dtsi" -+#include "imx8mp-venice-gw82xx.dtsi" -+ -+/ { -+ model = "Gateworks Venice GW82xx-2x i.MX8MP Development Kit"; -+ compatible = "gateworks,imx8mp-gw82xx-2x", "fsl,imx8mp"; -+ -+ chosen { -+ stdout-path = &uart2; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi -@@ -0,0 +1,533 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2024 Gateworks Corporation -+ */ -+ -+#include -+#include -+#include -+ -+/ { -+ aliases { -+ ethernet1 = ð1; -+ fsa1 = &fsa0; -+ fsa2 = &fsa1; -+ }; -+ -+ led-controller { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ -+ led-0 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ pcie0_refclk: clock-pcie0 { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pps>; -+ gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ reg_usb2_vbus: regulator-usb2 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_reg_usb2_en>; -+ regulator-name = "usb2_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc2_vmmc>; -+ regulator-name = "VDD_3V3_SD"; -+ regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <3300000>; -+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ off-on-delay-us = <12000>; -+ startup-delay-us = <100>; -+ }; -+}; -+ -+&ecspi2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spi2>; -+ cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>, /* CS0 onboard TPM */ -+ <&gpio5 13 GPIO_ACTIVE_LOW>, /* CS1 off-board J32 SPI */ -+ <&gpio1 12 GPIO_ACTIVE_LOW>, /* CS3 off-board J52 FSA1 */ -+ <&gpio4 26 GPIO_ACTIVE_LOW>; /* CS2 off-board J51 FSA2 */ -+ status = "okay"; -+ -+ tpm@0 { -+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; -+ reg = <0x0>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_can1>; -+ status = "okay"; -+}; -+ -+&flexcan2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_can2>; -+ status = "okay"; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "fsa2_gpio1", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ "", "", "", "", -+ "", "", "", "", -+ "dio1", "fsa1_gpio2", "", "dio0", -+ "", "", "", "", -+ "", "", "", "", -+ "", "", "rs485_en", "rs485_term", -+ "fsa2_gpio2", "fsa1_gpio1", "", "rs485_half", -+ "", "", "", ""; -+}; -+ -+&i2c2 { -+ accelerometer@19 { -+ compatible = "st,lis2de12"; -+ reg = <0x19>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_accel>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ st,drdy-int-pin = <1>; -+ }; -+ -+ magnetometer@1e { -+ compatible = "st,lis2mdl"; -+ reg = <0x1e>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mag>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>; -+ }; -+}; -+ -+&i2c3 { -+ i2c-mux@70 { -+ compatible = "nxp,pca9548"; -+ reg = <0x70>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* J30 */ -+ fsa1: i2c@0 { -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fsa2i2c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gpio@20 { -+ compatible = "nxp,pca9555"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ eeprom@54 { -+ compatible = "atmel,24c02"; -+ reg = <0x54>; -+ pagesize = <16>; -+ }; -+ -+ eeprom@55 { -+ compatible = "atmel,24c02"; -+ reg = <0x55>; -+ pagesize = <16>; -+ }; -+ }; -+ -+ /* J29 */ -+ fsa0: i2c@1 { -+ reg = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fsa1i2c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ gpio@20 { -+ compatible = "nxp,pca9555"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio4>; -+ interrupts = <14 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ eeprom@54 { -+ compatible = "atmel,24c02"; -+ reg = <0x54>; -+ pagesize = <16>; -+ }; -+ -+ eeprom@55 { -+ compatible = "atmel,24c02"; -+ reg = <0x55>; -+ pagesize = <16>; -+ }; -+ }; -+ -+ /* J33 */ -+ i2c@2 { -+ reg = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+}; -+ -+&pcie_phy { -+ clocks = <&pcie0_refclk>; -+ clock-names = "ref"; -+ fsl,refclk-pad-mode = ; -+ fsl,clkreq-unsupported; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie0>; -+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ pcie@7,0 { -+ reg = <0x3800 0 0 0 0>; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ eth1: ethernet@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ local-mac-address = [00 00 00 00 00 00]; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+/* GPS */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+/* RS232 */ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart4>; -+ status = "okay"; -+}; -+ -+/* USB1 - FSA1 */ -+&usb3_0 { -+ fsl,permanently-attached; -+ fsl,disable-port-power-control; -+ status = "okay"; -+}; -+ -+&usb3_phy0 { -+ status = "okay"; -+}; -+ -+&usb_dwc3_0 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+/* USB2 - USB3.0 Hub */ -+&usb3_1 { -+ fsl,permanently-attached; -+ fsl,disable-port-power-control; -+ status = "okay"; -+}; -+ -+&usb3_phy1 { -+ vbus-supply = <®_usb2_vbus>; -+ status = "okay"; -+}; -+ -+&usb_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+/* SDIO 1.8V */ -+&usdhc1 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+}; -+ -+/* microSD */ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; /* CD is active high */ -+ bus-width = <4>; -+ vmmc-supply = <®_usdhc2_vmmc>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ -+ MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ -+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ -+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ -+ MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ -+ >; -+ }; -+ -+ pinctrl_accel: accelgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ# */ -+ >; -+ }; -+ -+ pinctrl_can1: can1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 -+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 -+ >; -+ }; -+ -+ pinctrl_can2: can2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 -+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ -+ MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ -+ >; -+ }; -+ -+ pinctrl_fsa1i2c: fsa1i2cgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1d0 /* FSA1_ALERT# */ -+ MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x400001d0 /* FSA1_GPIO1 */ -+ MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x400001d0 /* FSA1_GPIO2 */ -+ >; -+ }; -+ -+ pinctrl_fsa2i2c: fsa2i2cgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x1d0 /* FSA2_ALERT# */ -+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x400001d0 /* FSA2_GPIO1 */ -+ MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x400001d0 /* FSA2_GPIO2 */ -+ >; -+ }; -+ -+ pinctrl_mag: maggrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x140 /* IRQ# */ -+ >; -+ }; -+ -+ pinctrl_pcie0: pcie0grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 /* PERST# */ -+ >; -+ }; -+ -+ pinctrl_pps: ppsgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 -+ >; -+ }; -+ -+ pinctrl_reg_usb2_en: regusb2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ -+ >; -+ }; -+ -+ pinctrl_spi2: spi2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0xd0 -+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0xd0 -+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0xd0 -+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 /* J32_CS */ -+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 /* TPM_CS */ -+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 /* FSA1_CS */ -+ MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x140 /* FSA2_CS */ -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 -+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 -+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 -+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 -+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 -+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 -+ >; -+ }; -+ -+ pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1d0 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 -+ >; -+ }; -+}; diff --git a/target/linux/imx/patches-6.6/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch b/target/linux/imx/patches-6.6/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch deleted file mode 100644 index c9878e55ad..0000000000 --- a/target/linux/imx/patches-6.6/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch +++ /dev/null @@ -1,121 +0,0 @@ -From cf983e4a04eecb5be93af7b53cb10805ee448998 Mon Sep 17 00:00:00 2001 -From: Tim Harvey -Date: Mon, 21 Aug 2023 09:20:17 -0700 -Subject: [PATCH] PCI: imx6: Start link at max gen first for IMX8MM and IMX8MP - -commit fa33a6d87eac ("PCI: imx6: Start link in Gen1 before negotiating -for Gen2 mode") started link negotiation at Gen1 before attempting -faster speeds in order to work around an issue with a particular switch -on an IMX6Q SoC. - -This behavior is not the norm for PCI link negotiation and it has been -found to cause issues in other cases: -- IMX8MM with PI7C9X2G608GP switch: various endpoints (such as qca988x) - will fail to link more than 50% of the time -- IMX8MP with PI7C9X2G608GP switch: occasionally will fail to link with - switch and cause a CPU hang about 30% of the time - -Disable this behavior for IMX8MM and IMX8MP. - -Signed-off-by: Tim Harvey ---- - drivers/pci/controller/dwc/pci-imx6.c | 53 ++++++++++++++------------- - 1 file changed, 27 insertions(+), 26 deletions(-) - ---- a/drivers/pci/controller/dwc/pci-imx6.c -+++ b/drivers/pci/controller/dwc/pci-imx6.c -@@ -60,6 +60,7 @@ enum imx6_pcie_variants { - #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) - #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) - #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) -+#define IMX6_PCIE_FLAG_GEN1_LAST BIT(3) - - #define IMX6_PCIE_MAX_CLKS 6 - -@@ -836,26 +837,28 @@ static int imx6_pcie_start_link(struct d - u32 tmp; - int ret; - -- /* -- * Force Gen1 operation when starting the link. In case the link is -- * started in Gen2 mode, there is a possibility the devices on the -- * bus will not be detected at all. This happens with PCIe switches. -- */ -- dw_pcie_dbi_ro_wr_en(pci); -- tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); -- tmp &= ~PCI_EXP_LNKCAP_SLS; -- tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; -- dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); -- dw_pcie_dbi_ro_wr_dis(pci); -+ if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_GEN1_LAST)) { -+ /* -+ * Force Gen1 operation when starting the link. In case the link is -+ * started in Gen2 mode, there is a possibility the devices on the -+ * bus will not be detected at all. This happens with PCIe switches. -+ */ -+ dw_pcie_dbi_ro_wr_en(pci); -+ tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); -+ tmp &= ~PCI_EXP_LNKCAP_SLS; -+ tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; -+ dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); -+ dw_pcie_dbi_ro_wr_dis(pci); -+ } - - /* Start LTSSM. */ - imx6_pcie_ltssm_enable(dev); - -- ret = dw_pcie_wait_for_link(pci); -- if (ret) -- goto err_reset_phy; -+ if ((pci->link_gen > 1) && !(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_GEN1_LAST)) { -+ ret = dw_pcie_wait_for_link(pci); -+ if (ret) -+ goto err_reset_phy; - -- if (pci->link_gen > 1) { - /* Allow faster modes after the link is up */ - dw_pcie_dbi_ro_wr_en(pci); - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); -@@ -889,18 +892,14 @@ static int imx6_pcie_start_link(struct d - goto err_reset_phy; - } - } -- -- /* Make sure link training is finished as well! */ -- ret = dw_pcie_wait_for_link(pci); -- if (ret) -- goto err_reset_phy; -- } else { -- dev_info(dev, "Link: Only Gen1 is enabled\n"); - } - -+ ret = dw_pcie_wait_for_link(pci); -+ if (ret) -+ goto err_reset_phy; -+ - imx6_pcie->link_is_up = true; -- tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); -- dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); -+ - return 0; - - err_reset_phy: -@@ -1458,14 +1457,16 @@ static const struct imx6_pcie_drvdata dr - }, - [IMX8MM] = { - .variant = IMX8MM, -- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, -+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | -+ IMX6_PCIE_FLAG_GEN1_LAST, - .gpr = "fsl,imx8mm-iomuxc-gpr", - .clk_names = imx8mm_clks, - .clks_cnt = ARRAY_SIZE(imx8mm_clks), - }, - [IMX8MP] = { - .variant = IMX8MP, -- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, -+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | -+ IMX6_PCIE_FLAG_GEN1_LAST, - .gpr = "fsl,imx8mp-iomuxc-gpr", - .clk_names = imx8mm_clks, - .clks_cnt = ARRAY_SIZE(imx8mm_clks), -- 2.30.2