From 24eb59779a9944721c1c88b19d99522c84cb998a Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 13 Sep 2025 19:49:36 +0800 Subject: [PATCH] uboot-rockchip: add Radxa ROCK 4D support Add support for the Radxa ROCK 4D board. Signed-off-by: Tianling Shen Link: https://github.com/openwrt/openwrt/pull/20041 Signed-off-by: Hauke Mehrtens --- package/boot/uboot-rockchip/Makefile | 20 + ...rockchip_sfc-Support-sclk_x2-version.patch | 64 ++ ...Add-a-read_brom_bootsource_id-helper.patch | 65 ++ ...ip-rk3576-Add-SPI-Flash-boot-support.patch | 156 +++ ...108-board-rockchip-Add-Radxa-ROCK-4D.patch | 901 ++++++++++++++++++ 5 files changed, 1206 insertions(+) create mode 100644 package/boot/uboot-rockchip/patches/105-spi-rockchip_sfc-Support-sclk_x2-version.patch create mode 100644 package/boot/uboot-rockchip/patches/106-rockchip-spl-Add-a-read_brom_bootsource_id-helper.patch create mode 100644 package/boot/uboot-rockchip/patches/107-rockchip-rk3576-Add-SPI-Flash-boot-support.patch create mode 100644 package/boot/uboot-rockchip/patches/108-board-rockchip-Add-Radxa-ROCK-4D.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index c7a4f941b8..36bb78d0f6 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -264,6 +264,25 @@ define U-Boot/rock-3b-rk3568 endef +# RK3576 boards + +define U-Boot/rk3576/Default + BUILD_SUBTARGET:=armv8 + DEPENDS:= \ + +PACKAGE_u-boot-$(1):trusted-firmware-a-rk3576 \ + +PACKAGE_u-boot-$(1):trusted-firmware-a-rk3576-tpl + ATF:=rk3576_bl31.elf + TPL:=rk3576_ddr_lp4_2112MHz_lp5_2736MHz_v1.09.bin +endef + +define U-Boot/rock-4d-rk3576 + $(U-Boot/rk3576/Default) + NAME:=ROCK 4D + BUILD_DEVICES:= \ + radxa_rock-4d +endef + + # RK358x boards define U-Boot/rk358x/Default @@ -373,6 +392,7 @@ UBOOT_TARGETS := \ radxa-e25-rk3568 \ rock-3a-rk3568 \ rock-3b-rk3568 \ + rock-4d-rk3576 \ generic-rk3588 \ nanopc-t6-rk3588 \ rock-5-itx-rk3588 \ diff --git a/package/boot/uboot-rockchip/patches/105-spi-rockchip_sfc-Support-sclk_x2-version.patch b/package/boot/uboot-rockchip/patches/105-spi-rockchip_sfc-Support-sclk_x2-version.patch new file mode 100644 index 0000000000..a1fafb2979 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/105-spi-rockchip_sfc-Support-sclk_x2-version.patch @@ -0,0 +1,64 @@ +From: Jonas Karlman +To: Kever Yang , + Simon Glass , + Philipp Tomsich , + Tom Rini , + Jagan Teki +Cc: Quentin Schulz , + u-boot@lists.denx.de, Jonas Karlman , + Jon Lin +Subject: [PATCH v3 01/10] spi: rockchip_sfc: Support sclk_x2 version +Date: Sun, 31 Aug 2025 11:20:22 +0000 [thread overview] +Message-ID: <20250831112046.2642363-2-jonas@kwiboo.se> (raw) +In-Reply-To: <20250831112046.2642363-1-jonas@kwiboo.se> + +From: Jon Lin + +SFC after version 8 supports dtr mode, so the IO is the binary output of +the controller clock. + +Signed-off-by: Jon Lin +Signed-off-by: Jonas Karlman +--- +v3: No change +v2: No change +--- + drivers/spi/rockchip_sfc.c | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +--- a/drivers/spi/rockchip_sfc.c ++++ b/drivers/spi/rockchip_sfc.c +@@ -108,6 +108,7 @@ + #define SFC_VER_3 0x3 + #define SFC_VER_4 0x4 + #define SFC_VER_5 0x5 ++#define SFC_VER_8 0x8 + + /* Delay line controller resiter */ + #define SFC_DLL_CTRL0 0x3C +@@ -589,6 +590,16 @@ static int rockchip_sfc_adjust_op_size(s + return 0; + } + ++#if CONFIG_IS_ENABLED(CLK) ++static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, uint speed) ++{ ++ if (sfc->version >= SFC_VER_8) ++ return clk_set_rate(&sfc->clk, speed * 2); ++ else ++ return clk_set_rate(&sfc->clk, speed); ++} ++#endif ++ + static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) + { + struct rockchip_sfc *sfc = dev_get_plat(bus); +@@ -600,7 +611,7 @@ static int rockchip_sfc_set_speed(struct + return 0; + + #if CONFIG_IS_ENABLED(CLK) +- int ret = clk_set_rate(&sfc->clk, speed); ++ int ret = rockchip_sfc_clk_set_rate(sfc, speed); + + if (ret < 0) { + dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", diff --git a/package/boot/uboot-rockchip/patches/106-rockchip-spl-Add-a-read_brom_bootsource_id-helper.patch b/package/boot/uboot-rockchip/patches/106-rockchip-spl-Add-a-read_brom_bootsource_id-helper.patch new file mode 100644 index 0000000000..39aa334ee6 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/106-rockchip-spl-Add-a-read_brom_bootsource_id-helper.patch @@ -0,0 +1,65 @@ +From: Jonas Karlman +To: Kever Yang , + Simon Glass , + Philipp Tomsich , + Tom Rini +Cc: Quentin Schulz , + u-boot@lists.denx.de, Jonas Karlman +Subject: [PATCH v3 02/10] rockchip: spl: Add a read_brom_bootsource_id() helper +Date: Sun, 31 Aug 2025 11:20:23 +0000 [thread overview] +Message-ID: <20250831112046.2642363-3-jonas@kwiboo.se> (raw) +In-Reply-To: <20250831112046.2642363-1-jonas@kwiboo.se> + +The bootsource ids reported by BootROM of RK3528 and RK3576 for e.g. +SPI NOR and USB differs slightly compared to prior SoCs: + +- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3. +- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23. +- Booting from sfc1 M0 has not been tested (no board using this config). +- Booting from USB report a new bootsource id 0x81 on RK3528 and RK3576. + +Add a helper function to read the bootsource id. This helper function +will be used to translate the new values to the common BROM_BOOTSOURCE +enum values on RK3528 and RK3576. + +Signed-off-by: Jonas Karlman +--- +v3: Mention RK3528 in commit message +v2: No change +--- + arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++ + arch/arm/mach-rockchip/spl.c | 7 ++++++- + 2 files changed, 8 insertions(+), 1 deletion(-) + +--- a/arch/arm/include/asm/arch-rockchip/bootrom.h ++++ b/arch/arm/include/asm/arch-rockchip/bootrom.h +@@ -64,4 +64,6 @@ extern const char * const boot_devices[B + */ + #define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10) + ++u32 read_brom_bootsource_id(void); ++ + #endif +--- a/arch/arm/mach-rockchip/spl.c ++++ b/arch/arm/mach-rockchip/spl.c +@@ -31,6 +31,11 @@ int board_return_to_bootrom(struct spl_i + __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + }; + ++__weak u32 read_brom_bootsource_id(void) ++{ ++ return readl(BROM_BOOTSOURCE_ID_ADDR); ++} ++ + const char *board_spl_was_booted_from(void) + { + static u32 brom_bootsource_id_cache = BROM_BOOTSOURCE_UNKNOWN; +@@ -40,7 +45,7 @@ const char *board_spl_was_booted_from(vo + if (brom_bootsource_id_cache != BROM_BOOTSOURCE_UNKNOWN) + bootdevice_brom_id = brom_bootsource_id_cache; + else +- bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); ++ bootdevice_brom_id = read_brom_bootsource_id(); + + if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) + bootdevice_ofpath = boot_devices[bootdevice_brom_id]; diff --git a/package/boot/uboot-rockchip/patches/107-rockchip-rk3576-Add-SPI-Flash-boot-support.patch b/package/boot/uboot-rockchip/patches/107-rockchip-rk3576-Add-SPI-Flash-boot-support.patch new file mode 100644 index 0000000000..030c794b46 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/107-rockchip-rk3576-Add-SPI-Flash-boot-support.patch @@ -0,0 +1,156 @@ +From: Jonas Karlman +To: Kever Yang , + Simon Glass , + Philipp Tomsich , + Tom Rini +Cc: Quentin Schulz , + u-boot@lists.denx.de, Jonas Karlman +Subject: [PATCH v3 04/10] rockchip: rk3576: Add SPI Flash boot support +Date: Sun, 31 Aug 2025 11:20:25 +0000 [thread overview] +Message-ID: <20250831112046.2642363-5-jonas@kwiboo.se> (raw) +In-Reply-To: <20250831112046.2642363-1-jonas@kwiboo.se> + +The bootsource ids reported by BootROM of RK3576 for SPI NOR and USB +differs slightly compared to prior SoCs: + +- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3. +- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23. +- Booting from sfc1 M0 has not been tested (no board using this config). +- Booting from USB report a new bootsource id 0x81. + +Add a RK3576 specific read_brom_bootsource_id() function to help decode +the new bootsource id values and the required boot_devices mapping of +sfc0 and sfc1 to help support booting from SPI flash on RK3576. + +Signed-off-by: Jonas Karlman +--- +Changes in v3: +- Add fspi1m1 pinctrl bootph- props to SoC u-boot.dtsi +- Drop the incomplete support for FSPI1_M0 +- Add a short code comment about the re-mapping of bootsource id + +v2: No change +--- + arch/arm/dts/rk3576-u-boot.dtsi | 46 ++++++++++++++++++++++++++ + arch/arm/mach-rockchip/rk3576/rk3576.c | 25 ++++++++++++++ + 2 files changed, 71 insertions(+) + +--- a/arch/arm/dts/rk3576-u-boot.dtsi ++++ b/arch/arm/dts/rk3576-u-boot.dtsi +@@ -6,6 +6,11 @@ + #include "rockchip-u-boot.dtsi" + + / { ++ aliases { ++ spi5 = &sfc0; ++ spi6 = &sfc1; ++ }; ++ + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; +@@ -16,6 +21,17 @@ + }; + }; + ++#ifdef CONFIG_ROCKCHIP_SPI_IMAGE ++&binman { ++ simple-bin-spi { ++ mkimage { ++ args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; ++ offset = <0x8000>; ++ }; ++ }; ++}; ++#endif ++ + &cru { + bootph-all; + }; +@@ -45,6 +61,26 @@ + bootph-some-ram; + }; + ++&fspi0_csn0 { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ ++&fspi0_pins { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ ++&fspi1m1_csn0 { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ ++&fspi1m1_pins { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ + &ioc_grf { + bootph-all; + }; +@@ -116,6 +152,16 @@ + bootph-some-ram; + }; + ++&sfc0 { ++ bootph-some-ram; ++ u-boot,spl-sfc-no-dma; ++}; ++ ++&sfc1 { ++ bootph-some-ram; ++ u-boot,spl-sfc-no-dma; ++}; ++ + &sys_grf { + bootph-all; + }; +--- a/arch/arm/mach-rockchip/rk3576/rk3576.c ++++ b/arch/arm/mach-rockchip/rk3576/rk3576.c +@@ -36,8 +36,15 @@ + #define USB_GRF_BASE 0x2601E000 + #define USB3OTG0_CON1 0x0030 + ++enum { ++ BROM_BOOTSOURCE_FSPI0 = 3, ++ BROM_BOOTSOURCE_FSPI1_M1 = 6, ++}; ++ + const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", ++ [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0", ++ [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0", + [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", + }; + +@@ -85,6 +92,24 @@ void board_debug_uart_init(void) + { + } + ++u32 read_brom_bootsource_id(void) ++{ ++ u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR); ++ ++ /* Re-map the raw value read from reg to a redefined or existing ++ * BROM_BOOTSOURCE enum value to avoid having to create a larger ++ * boot_devices table. ++ */ ++ if (bootsource_id == 0x23) ++ return BROM_BOOTSOURCE_FSPI1_M1; ++ else if (bootsource_id == 0x81) ++ return BROM_BOOTSOURCE_USB; ++ else if (bootsource_id > BROM_LAST_BOOTSOURCE) ++ log_debug("Unknown bootsource %x\n", bootsource_id); ++ ++ return bootsource_id; ++} ++ + #define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE + #define HP_CTRL_REG 0x04 + #define TIMER_EN BIT(0) diff --git a/package/boot/uboot-rockchip/patches/108-board-rockchip-Add-Radxa-ROCK-4D.patch b/package/boot/uboot-rockchip/patches/108-board-rockchip-Add-Radxa-ROCK-4D.patch new file mode 100644 index 0000000000..417bdd53c7 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/108-board-rockchip-Add-Radxa-ROCK-4D.patch @@ -0,0 +1,901 @@ +From: Jonas Karlman +To: Kever Yang , + Simon Glass , + Philipp Tomsich , + Tom Rini , Jonas Karlman +Cc: Quentin Schulz , u-boot@lists.denx.de +Subject: [PATCH v3 10/10] board: rockchip: Add Radxa ROCK 4D +Date: Sun, 31 Aug 2025 11:20:31 +0000 [thread overview] +Message-ID: <20250831112046.2642363-11-jonas@kwiboo.se> (raw) +In-Reply-To: <20250831112046.2642363-1-jonas@kwiboo.se> + +The Radxa ROCK 4D is a compact single-board computer (SBC) featuring +numerous top-tier functions, features, and expansion options. + +Equipped with the Rockchip RK3576 or RK3576J SoC, the ROCK 4D boasts an +octa-core CPU (4x Cortex-A72 + 4x Cortex-A53), Mali-G52 GPU, and a +powerful 6 TOPS NPU, making it ideal for AI and multimedia tasks. + +Features tested on a Radxa ROCK 4D v1.112: +- SPI Flash boot +- Ethernet +- PCIe/NVMe +- USB host + +ROCK 4D boards with SPI Flash is configured to boot from FSPI0->UFS->USB, +or directly from USB when the MASKROM button is pressed, booting +directly from SD-card is not possible on these boards. + +Signed-off-by: Jonas Karlman +--- +v3: Drop the reset-gpios prop rename +v2: Add comment about the reset-gpios prop rename +--- + arch/arm/dts/rk3576-rock-4d-u-boot.dtsi | 10 ++++ + arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++ + configs/rock-4d-rk3576_defconfig | 68 +++++++++++++++++++++++ + doc/board/rockchip/rockchip.rst | 1 + + 4 files changed, 85 insertions(+) + create mode 100644 arch/arm/dts/rk3576-rock-4d-u-boot.dtsi + create mode 100644 configs/rock-4d-rk3576_defconfig + +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts +@@ -0,0 +1,751 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "rk3576.dtsi" ++ ++/ { ++ model = "Radxa ROCK 4D"; ++ compatible = "radxa,rock-4d", "rockchip,rk3576"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ mmc0 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds: leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_g &led_rgb_r>; ++ ++ power-led { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ user-led { ++ color = ; ++ function = LED_FUNCTION_HEARTBEAT; ++ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ vcc_12v0_dcin: regulator-vcc-12v0-dcin { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-name = "vcc_12v0_dcin"; ++ }; ++ ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++ ++ vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc_1v2_ufs_vccq_s0"; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++ ++ vcc_1v8_s0: regulator-vcc-1v8-s0 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ vin-supply = <&vcc_1v8_s3>; ++ }; ++ ++ vcc_1v8_ufs_vccq2_s0: regulator-vcc-1v8-ufs-vccq2-s0 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_ufs_vccq2_s0"; ++ vin-supply = <&vcc_1v8_s3>; ++ }; ++ ++ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-name = "vcc_2v0_pldo_s3"; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++ ++ vcc_3v3_pcie: regulator-vcc-3v3-pcie { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pwren>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_pcie"; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++ ++ vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_rtc_s5"; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++ ++ vcc_3v3_s0: regulator-vcc-3v3-s0 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s0"; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_ufs_s0"; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++ ++ vcc_5v0_device: regulator-vcc-5v0-device { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vcc_5v0_device"; ++ vin-supply = <&vcc_12v0_dcin>; ++ }; ++ ++ vcc_5v0_host: regulator-vcc-5v0-host { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_host_pwren>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vcc5v0_host"; ++ vin-supply = <&vcc_5v0_device>; ++ }; ++ ++ vcc_5v0_sys: regulator-vcc-5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vcc_5v0_sys"; ++ vin-supply = <&vcc_12v0_dcin>; ++ }; ++}; ++ ++&combphy1_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gmac0 { ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii-id"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <ð0m0_miim ++ ð0m0_tx_bus2 ++ ð0m0_rx_bus2 ++ ð0m0_rgmii_clk ++ ð0m0_rgmii_bus ++ ðm0_clk0_25m_out>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdptxphy { ++ status = "okay"; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ pmic@23 { ++ compatible = "rockchip,rk806"; ++ reg = <0x23>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-parent = <&gpio0>; ++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins ++ &rk806_dvs1_null ++ &rk806_dvs2_null ++ &rk806_dvs3_null>; ++ system-power-controller; ++ vcc1-supply = <&vcc_5v0_sys>; ++ vcc2-supply = <&vcc_5v0_sys>; ++ vcc3-supply = <&vcc_5v0_sys>; ++ vcc4-supply = <&vcc_5v0_sys>; ++ vcc5-supply = <&vcc_5v0_sys>; ++ vcc6-supply = <&vcc_5v0_sys>; ++ vcc7-supply = <&vcc_5v0_sys>; ++ vcc8-supply = <&vcc_5v0_sys>; ++ vcc9-supply = <&vcc_5v0_sys>; ++ vcc10-supply = <&vcc_5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc_5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc_5v0_sys>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs1_pwrdn: dvs1-pwrdn-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun2"; ++ }; ++ ++ rk806_dvs1_rst: dvs1-rst-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun3"; ++ }; ++ ++ rk806_dvs1_slp: dvs1-slp-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun1"; ++ }; ++ ++ rk806_dvs2_dvs: dvs2-dvs-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun4"; ++ }; ++ ++ rk806_dvs2_gpio: dvs2-gpio-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun5"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_pwrdn: dvs2-pwrdn-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun2"; ++ }; ++ ++ rk806_dvs2_rst: dvs2-rst-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun3"; ++ }; ++ ++ rk806_dvs2_slp: dvs2-slp-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun1"; ++ }; ++ ++ rk806_dvs3_dvs: dvs3-dvs-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun4"; ++ }; ++ ++ rk806_dvs3_gpio: dvs3-gpio-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun5"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_pwrdn: dvs3-pwrdn-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun2"; ++ }; ++ ++ rk806_dvs3_rst: dvs3-rst-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun3"; ++ }; ++ ++ rk806_dvs3_slp: dvs3-slp-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun1"; ++ }; ++ ++ regulators { ++ vdd_cpu_big_s0: dcdc-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-enable-ramp-delay = <400>; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-name = "vdd_cpu_big_s0"; ++ regulator-ramp-delay = <12500>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_npu_s0: dcdc-reg2 { ++ regulator-boot-on; ++ regulator-enable-ramp-delay = <400>; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-name = "vdd_npu_s0"; ++ regulator-ramp-delay = <12500>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ regulator-ramp-delay = <12500>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vdd_gpu_s0: dcdc-reg5 { ++ regulator-boot-on; ++ regulator-enable-ramp-delay = <400>; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-ramp-delay = <12500>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_logic_s0: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <800000>; ++ regulator-name = "vdd_logic_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vdd_ddr_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca_1v8_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pldo2_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_pldo2_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vdda_1v2_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcca_3v3_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_sd_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_pldo6_s3"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdda_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdda_ddr_pll_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v75_hdmi_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <837500>; ++ regulator-max-microvolt = <837500>; ++ regulator-name = "vdda0v75_hdmi_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdda_0v85_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdda_0v75_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x1>; ++ clocks = <&cru REFCLKO25M_GMAC0_OUT>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtl8211f_rst>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pinctrl { ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ leds { ++ led_rgb_g: led-green-en { ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ led_rgb_r: led-red-en { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ rtl8211f { ++ rtl8211f_rst: rtl8211f-rst { ++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie_pwren: pcie-pwren { ++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ usb_host_pwren: usb-host-pwren { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <200000000>; ++ no-sdio; ++ no-mmc; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++ ++&sfc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fspi0_pins &fspi0_csn0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ vcc-supply = <&vcc_1v8_s3>; ++ }; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-0 = <&uart0m0_xfer>; ++ status = "okay"; ++}; ++ ++&usb_drd1_dwc3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi +@@ -0,0 +1,10 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk3576-u-boot.dtsi" ++ ++&sfc0 { ++ flash@0 { ++ bootph-pre-ram; ++ bootph-some-ram; ++ }; ++}; +--- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS ++++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS +@@ -3,3 +3,9 @@ M: Jonas Karlman + S: Maintained + F: arch/arm/dts/rk3576-generic* + F: configs/generic-rk3576_defconfig ++ ++ROCK-4D-RK3576 ++M: Jonas Karlman ++S: Maintained ++F: arch/arm/dts/rk3576-rock-4d* ++F: configs/rock-4d-rk3576_defconfig +--- /dev/null ++++ b/configs/rock-4d-rk3576_defconfig +@@ -0,0 +1,68 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=50000000 ++CONFIG_SF_DEFAULT_MODE=0x2000 ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-rock-4d" ++CONFIG_ROCKCHIP_RK3576=y ++CONFIG_ROCKCHIP_SPI_IMAGE=y ++CONFIG_SYS_LOAD_ADDR=0x40c00800 ++CONFIG_SF_DEFAULT_BUS=5 ++CONFIG_DEBUG_UART_BASE=0x2AD40000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-rock-4d.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_SPL_MAX_SIZE=0x40000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MEMINFO_MAP=y ++CONFIG_CMD_ADC=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MISC=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_RNG=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y ++CONFIG_NVME_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_PHY_ROCKCHIP_USBDP=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SFC=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_ERRNO_STR=y +--- a/doc/board/rockchip/rockchip.rst ++++ b/doc/board/rockchip/rockchip.rst +@@ -137,6 +137,7 @@ List of mainline supported Rockchip boar + * rk3576 + - Firefly ROC-RK3576-PC (roc-pc-rk3576) + - Generic RK3576 (generic-rk3576) ++ - Radxa ROCK 4D (rock-4d-rk3576) + + * rk3588 + - ArmSoM Sige7 (sige7-rk3588) -- 2.30.2