From 1c3b32c45a25a6b80b9b1541a5ec4ce082939e5e Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 18 Nov 2025 11:17:39 +0000 Subject: [PATCH] mediatek: fix uart clocks in MT7987 infracfg clock driver MediaTek has applied a fix for the MT7987 infracfg clock driver in their SDK, pick it. Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/fe98d04c6036a5e142f02021145e528216a8d831/master/files/target/linux/mediatek/patches-6.12/999-clk-01-clk-mediatek-fix-mt7987-infracfg-clk-driver.patch Signed-off-by: Daniel Golle --- .../361-clk-mediatek-add-mt7987-clock-drivers-support.patch | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch b/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch index 577b2b7dfc..249e239086 100644 --- a/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch +++ b/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch @@ -273,7 +273,7 @@ Signed-off-by: Daniel Golle +MODULE_LICENSE("GPL"); --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7987-infracfg.c -@@ -0,0 +1,328 @@ +@@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 MediaTek Inc. @@ -301,15 +301,12 @@ Signed-off-by: Daniel Golle +static DEFINE_SPINLOCK(mt7987_clk_lock); + +static const char *const infra_mux_uart0_parents[] = { "csw_infra_f26m_sel", -+ "infra_hf_66m_uart0_pck", + "uart_sel" }; + +static const char *const infra_mux_uart1_parents[] = { "csw_infra_f26m_sel", -+ "infra_hf_66m_uart1_pck", + "uart_sel" }; + +static const char *const infra_mux_uart2_parents[] = { "csw_infra_f26m_sel", -+ "infra_hf_66m_uart1_pck", + "uart_sel" }; + +static const char *const infra_mux_spi0_parents[] = { -- 2.30.2