perf: Fix LLC-* events on Intel Nehalem/Westmere

perf: Fix LLC-* events on Intel Nehalem/Westmere

On Intel Nehalem and Westmere CPUs the generic perf LLC-* events count the
L2 caches, not the real L3 LLC - this was inconsistent with behavior on
other CPUs.

Fixing this requires the use of the special OFFCORE_RESPONSE
events which need a separate mask register.

This has been implemented by the previous patch, now use this infrastructure
to set correct events for the LLC-* on Nehalem and Westmere.

Signed-off-by: Andi Kleen <[email protected]>
Signed-off-by: Lin Ming <[email protected]>
Signed-off-by: Peter Zijlstra <[email protected]>
LKML-Reference: <1299119690[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>