dt-bindings: clk: Hi6220: Document stub clock driver

Document the new compatible for stub clock driver which is used for CPU
and DDR's dynamic frequency scaling.

Signed-off-by: Leo Yan <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: arm: Hi6220: add doc for SRAM controller

Document "hisilicon,hi6220-sramctrl" for SRAM controller.

Signed-off-by: Leo Yan <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: atlas7: fix pll missed divide NR in fraction mode

PLL VCO frequency is given by Fvco = Fref * 2 * NF / NR
in integer-N mode, or by Fvco = Fref * SSN / NR in Spread
Spectrum (fractional-N) mode. Thus fix the missing part
of NR

Signed-off-by: Guo Zeng <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: atlas7: fix bit field and its root clk for coresight_tpiu

bit4 thcpum_cpudiv4_clken  r/w
thcpum_cpudiv4_clk clock enable (default: 1)
Root clock CPU_CLK must be enabled for this clock to be enabled

bit3 coresight_tpiu_clken  r/w
coresight_tpiu_clk clock enable (default: 0)
Root clock TPIU_CLK must be enabled for this clock to be enabled

Signed-off-by: Guo Zeng <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: atlas7: replace dto resolution magic number by macro

Signed-off-by: Yibo Cai <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: atlas7: fix integer overflow in dto rate calculation

I cannot believe that I spend quite a lot time in finding this bug.
It seems a pitfall people tend to fall in.

In "int64 = int32 * int32", conversion from 32-bits to 64-bits comes
after the multiplication. So this statement may not work as expected.

Signed-off-by: Yibo Cai <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: atlas7: export mux clks so that consumers can get them

this patch makes mux clks can be referenced by device drivers.

Signed-off-by: Guo Zeng <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: atlas7: add lost pwm unit clks

Signed-off-by: Guo Zeng <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: socfpga: Add a second parent option for the dbg_base_clk

The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.

This patch adds the option to get the correct parent for the debug base
clock.

Signed-off-by: Dinh Nguyen <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: ux500: delete the non-DT U8500 clock implementation

This code is unused and not coming back. Let's kill it off.

Cc: Ulf Hansson <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: Remove unused provider APIs

Remove these APIs now that we've converted all users to the
replacement struct clk_hw based versions.

Signed-off-by: Stephen Boyd <[email protected]>

clk: si5351: Convert __clk_get_name() to clk_hw_get_name()

This driver uses __clk_get_name() when it's dealing with struct
clk_hw pointers. Use the simpler form so that we can get rid of
the clk member in struct clk_hw one day.

Acked-by: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

drm/msm/dsi: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Wentao Xu <[email protected]>
Cc: Rob Clark <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: versatile: Switch to assigned clock parents

We're removing struct clk from the clk provider API. This code is
calling the consumer APIs to change the parent to a 1 MHz fixed
rate clock for each of the clocks that the driver provides. Move
to using the assigned-clock-parents DT property for this instead.
Because this is an ABI break, detect if the property is missing
and fall back to setting the parent explicitly before the clocks
are registered.

Acked-by: Pawel Moll <[email protected]>
Cc: Linus Walleij <[email protected]>
Tested-by: Sudeep Holla <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: versatile: Add SP810 device tree bindings document

Signed-off-by: Pawel Moll <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: ti: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: tegra: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Tomeu Vizoso <[email protected]>
Cc: Thierry Reding <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: sunxi: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Maxime Ripard <[email protected]>
Cc: "Emilio López" <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: spear: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Acked-by: Viresh Kumar <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: sirf: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Barry Song <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: samsung: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Chanwoo Choi <[email protected]>
Acked-by: Sylwester Nawrocki <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Kukjin Kim <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: rockchip: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Signed-off-by: Stephen Boyd <[email protected]>

clk: stm32f4: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Daniel Thompson <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mvebu: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs. This also
removes a clk_get() in this driver that can just as easily use
of_clk_get_parent_name() instead.

Cc: Gregory CLEMENT <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mmp: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Chao Xie <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: Convert basic types to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Signed-off-by: Stephen Boyd <[email protected]>

clk: bcm: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Reviewed-by: Alex Elder <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

MIPS: alchemy: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Manuel Lauss <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Linux-MIPS <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

ARM: OMAP: Convert __clk_get_rate() to provider/consumer APIs

We're removing struct clk from the clk provider API, so switch to
clk_get_rate() and clk_hw_get_rate() here appropriately.

Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: ti: Remove CLK_IS_BASIC check

This code is never called with a basic clock type, so the check
here is not doing anything useful and is blocking the removal of
__clk_get_flags(). Remove the check so we can delete the
__clk_get_flags() API.

Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: Convert __clk_get_flags() to clk_hw_get_flags()

Mostly converted with the following snippet:

@@
struct clk_hw *E;
@@

-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)

Acked-by: Tero Kristo <[email protected]>
Cc: Maxime Ripard <[email protected]>
Cc: Max Filippov <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
Cc: Daniel Thompson <[email protected]>
Cc: Coquelin <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()

Mostly converted with the following semantic patch:

@@
struct clk_hw *E;
@@

-__clk_get_num_parents(E->clk)
+clk_hw_get_num_parents(E)

Acked-by: Boris Brezillon <[email protected]>
Cc: Chao Xie <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Javier Martinez Canillas <[email protected]>
Cc: Tomasz Figa <[email protected]>
Cc: Maxime Ripard <[email protected]>
Cc: "Emilio López" <[email protected]>
Acked-by: Tero Kristo <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Acked-by: Sylwester Nawrocki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: Add clk_hw_*() APIs for use by clk providers

clk providers shouldn't need to use the consumer APIs (clk.h).
Add provider APIs to replace the __clk_*() APIs that take a
struct clk_hw as their first argument instead of a struct clk.

Signed-off-by: Stephen Boyd <[email protected]>

clk: rockchip: Fix SPIF special clock definition

Neither spdif_src nor spdif_pll exists, judging by the vendor kernel in
both cases spdif_pre was meant. This brings the naming in line and
hierachy in line with that of sclk_i2s0.

Also allow sclk_spdif and spdif_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_spdif

Signed-off-by: Sjoerd Simons <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

clk: bcm2835: Drop the fixed sys_pclk.

Nothing uses it, and I can't find any evidence that anything ever has.
Its role is now filled by the core clock in the firmware driver.

Signed-off-by: Eric Anholt <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

clk: track the orphan status of clocks and their children

While children of orphan clocks are not carried in the orphan-list itself,
they're nevertheless orphans in their own right as they also don't have an
input-rate available. To ease tracking if a clock is an orphan or has an
orphan in its parent path introduce an orphan field into struct clk and
update it and the fields in child-clocks when a clock gets added or removed
from the orphan-list.

Suggested-by: Stephen Boyd <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Cc: Boris Brezillon <[email protected]>
Cc: Alex Elder <[email protected]>
Cc: Alexandre Belloni <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Max Filippov <[email protected]>
Cc: [email protected]
Cc: Zhangfei Gao <[email protected]>
Cc: Santosh Shilimkar <[email protected]>
Cc: Chao Xie <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Stefan Wahren <[email protected]>
Cc: Andrew Bresticker <[email protected]>
Cc: Robert Jarzmik <[email protected]>
Cc: Georgi Djakov <[email protected]>
Cc: Sylwester Nawrocki <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Cc: Barry Song <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Viresh Kumar <[email protected]>
Cc: Gabriel FERNANDEZ <[email protected]>
Cc: [email protected]
Cc: Peter De Schrijver <[email protected]>
Cc: Tero Kristo <[email protected]>
Cc: Ulf Hansson <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Michal Simek <[email protected]>
[[email protected]: s/clk/core/ in new function]
Signed-off-by: Stephen Boyd <[email protected]>

clk: sunxi: Add a simple gates driver

The gates were handled with a common piece of framework that was
registering all gates array, that was not using the CLK_OF_DECLARE logic,
and was not using clock-indices but some private masks that were pretty
much equivalent.

Move this code in a new driver that handles all the gates array and solves
both these issues.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>
[[email protected]: Include clk.h for consumer API usage]
Signed-off-by: Stephen Boyd <[email protected]>

ARM: sun9i: Wrap the clock-indices

Wrap the clock-indices to match the wrapping of the clock-output-names in
order to make it easier to match indices to names.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

ARM: sun8i: Add clock indices

The A23 and A33 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

ARM: sun7i: Add clock indices

The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

ARM: sun6i: Add clock indices

The A31 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

ARM: sun5i: Add clock indices

The A10s and A13 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

ARM: sun4i: Add clock indices

The A10 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

Merge tag 'imx-clk-4.3' of git://git./linux/kernel/git/shawnguo/linux into clk-next

The i.MX clock updates for 4.3:
 - Provide a better IPU clock initial settings on imx6dl for getting
   HDMI and LVDS at the same time.
 - Add clock driver support for i.MX6UL SoC
 - Add a second clock for RTC device on i.MX31 and i.MX35

clk/mmp: use kmemdup rather than duplicating its implementation

The patch was generated using fixed coccinelle semantic patch
scripts/coccinelle/api/memdup.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2014320

Signed-off-by: Andrzej Hajda <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: imx35: define two clocks for rtc

The imx35 don't define clocks for rtc.
This patch add two clocks, as needed
by the mxc rtc driver.

Signed-off-by: Philippe Reynes <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>

clk: imx31: add a second rtc clock

The mxc rtc driver needs two clock.
It was defined only one clock, so we
define the second clock.

Signed-off-by: Philippe Reynes <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>

clk: hisi: refine parameter checking for init

*of_iomap()* will check the device node pointer, and if the pointer is
NULL it will return error code. So refine clock's init flow by checking
the device node with this simple way; and polish a little for the print
out message.

Signed-off-by: Leo Yan <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: versatile: off by one in clk_sp810_timerclken_of_get()

The ">" should be ">=" or we end up reading beyond the end of the array.

Fixes: 6e973d2c4385 ('clk: vexpress: Add separate SP810 driver')
Signed-off-by: Dan Carpenter <[email protected]>
Acked-by: Pawel Moll <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: exynos4: Fix wrong clock for Exynos4x12 ADC

The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
However TSADC is present only on Exynos4210 so on Trats2 board (with
Exynos4412 SoC) the exynos-adc driver could not be probed:
   ERROR: could not get clock /adc@126C0000:adc(0)
   exynos-adc 126c0000.adc: failed getting clock, err = -2
   exynos-adc: probe of 126c0000.adc failed with error -2

Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
Converter is located in different register and it is named in datasheet
as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
is the same as purpose of TSADC from Exynos4210.

The patch adds gate clock for Exynos4x12 using the proper register so
backward compatibility is preserved. This fixes the probe of exynos-adc
driver on Exynos4x12 boards and allows accessing sensors connected to it
on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).

Signed-off-by: Krzysztof Kozlowski <[email protected]>
Cc: <[email protected]>
Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
Reviewed-by: Javier Martinez Canillas <[email protected]>
Acked-by: Tomasz Figa <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: kill off set_irq_flags usage

set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:

IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN

For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.

Signed-off-by: Rob Herring <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Cc: Mike Turquette <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Cc: [email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: zx: Constify parent names in clock init data

The array of parent names can be made as array of const pointers to
const strings.

Signed-off-by: Jun Nie <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: zx: Add audio and GPIO clock for zx296702

Add SPDIF/I2S and GPIO clock for zx296702

Signed-off-by: Jun Nie <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: zx: Add audio div clock method for zx296702

Add SPDIF/I2S divider clock method for zx296702

Signed-off-by: Jun Nie <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: s2mps11: Use kcalloc instead of kzalloc for array allocation

This patch cleans up the driver for,

  - Use devm_kcalloc() variant instead of devm_kzalloc() for array
    allocation.
  - clk_prepare()/unprepare(), remove "ret" variable as it is not required
  - use __exit for cleanup function

As I am referring this driver as a reference for my 88pm800 clk driver,
applying same changes here as well.

Signed-off-by: Vaibhav Hiremath <[email protected]>
Tested-by: Anand Moon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: Silence warnings about lock imbalances

The recursive spinlock implementation trips up sparse and it
complains that these functions have lock imbalances. That isn't
really true though, so add some __acquires() and __releases()
information so that sparse is quiet.

drivers/clk/clk.c:116:22: warning: context imbalance in 'clk_enable_lock' - wrong count at exit
drivers/clk/clk.c:141:9: warning: context imbalance in 'clk_enable_unlock' - unexpected unlock

Signed-off-by: Stephen Boyd <[email protected]>

clk: basic-type: Silence warnings about lock imbalances

The basic clock types use conditional locking for the register
accessor spinlocks. Add __acquire() and __release() markings in
the right locations so that sparse isn't tripped up on the
conditional locking.

drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block
drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block
drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block

Cc: Andy Shevchenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: Give clk-qcom.ko module a GPLv2 license

The missing license causes the clk-qcom.ko module to taint the
kernel. Add the appropriate license to avoid taint.

Signed-off-by: Stephen Boyd <[email protected]>

clk: gpio: Mark parent_names array const

Let's encourage const arrays of parent names like other basic
clock types.

Cc: Sergej Sawazki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

Merge branch 'v4.3-topic/clk-samsung' of git://git./linux/kernel/git/kgene/linux-samsung into clk-next

clk: allow a clk divider with max divisor when zero

This commit allows certain Broadcom STB clock dividers to be used with
clk-divider.c.  It allows for a clock whose field value is the equal
to the divisor, execpt when the field value is zero, in which case the
divisor is 2^width.  For example, consider a divisor clock with a two
bit field:

value divisor
0 4
1 1
2 2
3 3

Signed-off-by: Jim Quinlan <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

clk: socfpga: switch to GENMASK()

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: pxa: fix core frequency reporting unit

Legacy drivers which are not yet ported, such as cpufreq-pxa[23]xx, rely
on pxaXXx_get_clk_frequency_khz() to find the CPU core frequency.

This reporting was broken because the expected unit is kHz and not
Hz. Fix the reporting for pxa25x, pxa27x and pxa3xx.

Fixes: fe7710fae477 ("clk: add pxa25x clock drivers")
Fixes: d40670dc6169 ("clk: add pxa27x clock drivers")
Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver")
Signed-off-by: Robert Jarzmik <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: rockchip: Fix PLL bandwidth

In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
 NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.

So:
  NB = NF / 2
  BWADJ[11:0] + 1 = NF / 2
  BWADJ[11:0] = NF / 2 - 1

Right now, we have:

{                                               \
        .rate   = _rate##U,                     \
        .nr = _nr,                              \
        .nf = _nf,                              \
        .no = _no,                              \
        .bwadj = (_nf >> 1),                    \
}

That means we set bwadj to NF / 2, not NF / 2 - 1

All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).

Let's change to working with "NB" and fix the off by one error.  This
may affect PLL jitter in a small way (hopefully for the better).

Signed-off-by: Douglas Anderson <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

Merge branch 'cleanup-clk-h-includes' into clk-next

* cleanup-clk-h-includes: (62 commits)
  clk: Remove clk.h from clk-provider.h
  clk: h8300: Remove clk.h and clkdev.h includes
  clk: at91: Include clk.h and slab.h
  clk: ti: Switch clk-provider.h include to clk.h
  clk: pistachio: Include clk.h
  clk: ingenic: Include clk.h
  clk: si570: Include clk.h
  clk: moxart: Include clk.h
  clk: cdce925: Include clk.h
  clk: Include clk.h in clk.c
  clk: zynq: Include clk.h
  clk: ti: Include clk.h
  clk: sunxi: Include clk.h and remove unused clkdev.h includes
  clk: st: Include clk.h
  clk: qcom: Include clk.h
  clk: highbank: Include clk.h
  clk: bcm: Include clk.h
  clk: versatile: Remove clk.h and clkdev.h includes
  clk: ux500: Remove clk.h and clkdev.h includes
  clk: tegra: Properly include clk.h
  ...

clk: ti: make use of of_clk_parent_fill helper function

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <[email protected]>
Cc: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: sunxi: make use of of_clk_parent_fill helper function

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Cc: "Emilio López" <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: st: make use of of_clk_parent_fill helper function

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <[email protected]>
Tested-by Gabriel Fernandez <[email protected]>
Cc: Peter Griffin <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: keystone: make use of of_clk_parent_fill helper function

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: make use of of_clk_parent_fill helper function

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <[email protected]>
Cc: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8173 MMPLL change rate support

MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting by adding
div-rate table to lookup suitable post divider setting under a
specified frequency.

Signed-off-by: James Liao <[email protected]>
Acked-by: Sascha Hauer <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Fix calculation of PLL rate settings

Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <[email protected]>
Acked-by: Sascha Hauer <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Fix PLL registers setting flow

Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.

Signed-off-by: James Liao <[email protected]>
Acked-by: Sascha Hauer <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: Allow providers to configure min/max rates

clk providers are using the consumer APIs to set min/max rates on
the clock they're providing. To encourage clk providers to move
away from the consumer APIs, add a provider API to set the
min/max rate of a clock. The assumption is that this is done
before the clock can be requested via clk_get() and that the
clock rate is already within the boundaries of the min/max that's
configured.

Tested-by: Sudeep Holla <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: twl6040: Convert to use devm_clk_register

Use devm_clk_register() to simplify the code by removing
twl6040_clk_remove().

Signed-off-by: Axel Lin <[email protected]>
Acked-by: Peter Ujfalusi <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: s2mps11: Simplify s2mps11_clk_probe unwind paths

The devm_clk_unregister() in .probe error case is not necessary as it will
be automatically called when probe fails.

Signed-off-by: Axel Lin <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: shmobile: Remove unneeded #include <linux/clkdev.h>

The CCF implementations for the various shmobile SoCs don't use clkdev
functionality, hence drop the inclusion of <linux/clkdev.h>.

Add the missing #include <linux/slab.h>, which was included implicitly
through <asm/clkdev.h> before.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: ti: Force pointer to be __iomem

Add __force here so that sparse doesn't complain about us playing
tricks with __iomem.

Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: ti: clk-3xxx: Remove unused structures

Sparse complains about these structures missing static, but they
also don't look to be used. Remove them.

drivers/clk/ti/clk-3xxx.c:74:30: warning: symbol 'clkhwops_omap3430es2_ssi_wait' was not declared. Should it be static?
drivers/clk/ti/clk-3xxx.c:157:30: warning: symbol 'clkhwops_omap3430es2_hsotgusb_wait' was not declared. Should it be static?

Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: ti: Mark ti_clk_features static

This variable isn't exported outside of this file so mark it
static. Silences the following sparse warning:

drivers/clk/ti/clk.c:36:24: warning: symbol 'ti_clk_features' was not declared. Should it be static?

Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: ti: Check kzalloc() for failures

smatch reports a failure to check kzalloc() here:

drivers/clk/ti/clk.c:232
omap2_clk_provider_init() error: potential null dereference 'io'.
(kzalloc returns null)

Check for an allocation failure and return -ENOMEM.

Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

Merge branch 'for-4.2/ti-clk-move' of https://github.com/t-kristo/linux-pm into clk-next

From Tero Kristo:
  "This pull request contains the TI clock driver set to move the
   clock implementations under clock driver. Some small portions of
   the clock driver code still remain under mach-omap2 after this,
   it should be decided whether this code is now obsolete and should
   be deleted or should someone try to fix it."

Slight merge conflicts with determine_rate prototype changes.

clk: h8300: Fix signness bug

of_clk_get_parent_count() may return negative error code, so num_parents
needs to be int rather than unsigned int.

Signed-off-by: Axel Lin <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks

The other ce clocks have the flag set, but ce1 doesn't, so
clk_set_rate() doesn't propagate up the tree to the ce1_src_clk.
Set the flag as this is supported.

Reported-by: Bjorn Andersson <[email protected]>
Tested-by: Bjorn Andersson <[email protected]>
Fixes: 02824653200b ("clk: qcom: Add APQ8084 Global Clock Controller support")
Fixes: d33faa9ead8d ("clk: qcom: Add support for MSM8974's global clock controller (GCC)")
Signed-off-by: Stephen Boyd <[email protected]>

clk: gpio: Unlock mutex on error path

We don't unlock the mutex if we fail to allocate the parent names
array. Unlock it and return an error in this case as well.

Reported-by: kbuild test robot <[email protected]>
Acked-by: Julia Lawall <[email protected]>
Cc: Sergej Sawazki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: h8300: Use standard Linux I/O accessors

There doesn't seem to be any reason why we can't use the standard
readb()/writeb() accessors here because ctrl_inb() and
ctrl_outb() match the generic implementation of readb() and
writeb() that the h8300 architecture uses. This allows us to test
compile this driver on other architectures besides h8300.

Cc: Yoshinori Sato <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: h8300: Drop allocation printk and cleanup sizeof style

We don't need to print an error on allocation failures, drop it.
While we're here, change the sizeof() to be sizeof(*<ptr>) to
make code more future proof.

Cc: Yoshinori Sato <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

Merge branch 'clk-determine-rate-struct' into clk-next

* clk-determine-rate-struct:
  clk: fix some determine_rate implementations
  clk: change clk_ops' ->determine_rate() prototype

clk: fix some determine_rate implementations

Some determine_rate implementations are not returning an error
when they failed to adapt the rate according to the rate request.
Fix them so that they return an error instead of silently
returning 0.

Signed-off-by: Boris Brezillon <[email protected]>
CC: Jonathan Corbet <[email protected]>
CC: Tony Lindgren <[email protected]>
CC: Ralf Baechle <[email protected]>
CC: "Emilio López" <[email protected]>
CC: Maxime Ripard <[email protected]>
Cc: Tero Kristo <[email protected]>
CC: Peter De Schrijver <[email protected]>
CC: Prashant Gaikwad <[email protected]>
CC: Stephen Warren <[email protected]>
CC: Thierry Reding <[email protected]>
CC: Alexandre Courbot <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: change clk_ops' ->determine_rate() prototype

Clock rates are stored in an unsigned long field, but ->determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.

Change ->determine_rate() prototype to return 0 or an error code, and pass
a pointer to a clk_rate_request structure containing the expected target
rate and the rate constraints imposed by clk users.

The clk_rate_request structure might be extended in the future to contain
other kind of constraints like the rounding policy, the maximum clock
inaccuracy or other things that are not yet supported by the CCF
(power consumption constraints ?).

Signed-off-by: Boris Brezillon <[email protected]>
CC: Jonathan Corbet <[email protected]>
CC: Tony Lindgren <[email protected]>
CC: Ralf Baechle <[email protected]>
CC: "Emilio López" <[email protected]>
CC: Maxime Ripard <[email protected]>
Acked-by: Tero Kristo <[email protected]>
CC: Peter De Schrijver <[email protected]>
CC: Prashant Gaikwad <[email protected]>
CC: Stephen Warren <[email protected]>
CC: Thierry Reding <[email protected]>
CC: Alexandre Courbot <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
[[email protected]: Fix parent dereference problem in
__clk_determine_rate()]
Signed-off-by: Stephen Boyd <[email protected]>
Tested-by: Romain Perier <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
[[email protected]: Folded in fix from Heiko for fixed-rate
clocks without parents or a rate determining op]
Signed-off-by: Stephen Boyd <[email protected]>

clk: exynos3250: Add cpu clock configuration data and instaniate cpu clock

This patch add CPU clock configuration data and instantiate the CPU
clock type for Exynos3250 to support Samsung specific cpu-clock type.

Cc: Sylwester Nawrocki <[email protected]>
Cc: Tomasz Figa <[email protected]>
Signed-off-by: Chanwoo Choi <[email protected]>
Acked-by: Kyungmin Park <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bartlomiej Zolnierkiewicz <[email protected]>
Acked-by: Michael Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>

clk: exynos5250: add cpu clock configuration data and instantiate cpu clock

With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5250.

Cc: Tomasz Figa <[email protected]>
Signed-off-by: Thomas Abraham <[email protected]>
[b.zolnierkie: split exynos5250 support from the original patch]
[b.zolnierkie: moved E5250_CPU_DIV[0,1] macros to clk-exynos5250.c]
Signed-off-by: Bartlomiej Zolnierkiewicz <[email protected]>
Reviewed-by: Javier Martinez Canillas <[email protected]>
Tested-by: Javier Martinez Canillas <[email protected]>
Acked-by: Sylwester Nawrocki <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Michael Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>

clk: Remove clk.h from clk-provider.h

Remove clk.h from clk-provider.h so that we can clearly split clk
providers from clk consumers. This will allow us to quickly
detect when clock providers are using the consumer APIs by
looking at the includes.

Signed-off-by: Stephen Boyd <[email protected]>

clk: h8300: Remove clk.h and clkdev.h includes

Neither of these includes are used in these files, remove them.

Cc: Yoshinori Sato <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: Include clk.h and slab.h

This clock provider uses the consumer API, so include clk.h
explicitly. Also include slab.h instead of relying on clkdev.h
for it.

Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: ti: Switch clk-provider.h include to clk.h

This file isn't a clock provider but uses the consumer API, so
include clk.h instead of clk-provider.h.

Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: pistachio: Include clk.h

This clock provider uses the consumer API, so include clk.h
explicitly.

Cc: Andrew Bresticker <[email protected]>
Cc: Ralf Baechle <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: ingenic: Include clk.h

This clock provider uses the consumer API, so include clk.h
explicitly.

Cc: Paul Burton <[email protected]>
Cc: Paul Cercueil <[email protected]>
Cc: Ralf Baechle <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>