drm/amd/display: Fix unbalanced locking in surface apply

also simplifying syntax and removing unused variable in
dce110_apply_ctx_for_surface()

Signed-off-by: Roman Li <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Apply work around for stutter.

Power on one plane after disable all the planes, for
a hw bug work around to resolve stutter efficiency issue.

Signed-off-by: Yongqiang Sun <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: remove dcn10 wait on tg unlock

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Loosen plane_info and scaling_info checks

Make it so that differing dcc and plane size fields don't necessarily
result in a full update, along with upscaling modes. This allows us to
save some unnecessary full updates.

Signed-off-by: Andrew Jiang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Report pitch_alignment for DCN

Signed-off-by: Andrew Jiang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: combine output signal and signal

output signal used to be a public member to be used by DM to override
the stream signal. Now since there is no longer separation between
public and private part of stream, they are combined. The overriding
was not working properly as well, which is addressed by this change

Signed-off-by: Eric Yang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: A few more color indentation changes

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Remove unused register read in program_pwl

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Bunch more color indentation cleanups

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Remove extra arr_points element

arr_points[1] and [2] were duplicated. Remove the extra
one. If we ever need more points we can add them but the
current state of affairs is confusing.

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: dal 3.1.16

Signed-off-by: Tony Cheng <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: always call set output tf

Temporary solution to fix gamma adjustment not
working.

Signed-off-by: Eric Yang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Fixed not set scaler bug.

New scaler parameter assign to dpp is after early return,
cause next flip scaler not program.

Signed-off-by: Yongqiang Sun <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: dal 3.1.15

Signed-off-by: Tony Cheng <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Remove unused OPP functions from interface

Signed-off-by: Eric Bernstein <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix dcn10_hubbub_wm_read_state

The ALLOW_SR registers might not always be available.

Signed-off-by: Ken Chalmers <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Add transfer function to dc_surface_update

Signed-off-by: SivapiriyanKumarasamy <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: send display_count msg so SMU can enter S0i2

SMU can future lower voltages in long idle case when all display is off.

If all display output is turned off via DPMS, send display_count = 0
after all output are turned off.

otherwise send display_count msg before turning on display to make sure
SMU exit S0i2 state.  before is not neccessary as we are out of S0i2
when driver execute code, but send message before anyways for correctness.

Signed-off-by: Hersen Wu <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Modified front end initiail in init_hw

Optimized front end initial sequence, reset MPC module
properly.

Signed-off-by: Yongqiang Sun <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: add warning on long reg_wait

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: remove unnecessary waits in dcn10

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix uninitialized variable warning

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix regamma programming

When new coefficients match cached we would skip setting regamma mode
Also, when doing a stream update we would program regamma for all pipes,
even thos that are not yet powered on. This resulted in never setting
regamma since we would cache before the pipe is powered.

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Fix some more color indentations

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Bunch of indentation cleanups in color stuff

Trying to align with kernel coding style and make it a bit more
readable.

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Refactor disable front end pipes.

There are different code to disable front end, it is
difficult to debug and adding new process.
This refactor makes all disable front end call the same
functions.

Signed-off-by: Yongqiang Sun <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: dal 3.1.14

Signed-off-by: Tony Cheng <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: renaming dpp function to follow naming convention

Signed-off-by: Yue Hin Lau <[email protected]>
Reviewed-by: Yuehin Lau <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: dal 3.1.13

Signed-off-by: Tony Cheng <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: call set csc_default if enable adjustment is false

Signed-off-by: Yue Hin Lau <[email protected]>
Reviewed-by: Eric Bernstein <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Add OPP DPG blank function

Added a function to blank data using OPP DPG.
Clean up code to prepare for pseudocode review with HW.

Signed-off-by: Eric Bernstein <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: dal 3.1.12

Signed-off-by: Tony Cheng <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: cache pwl params and scl_data to avoid extra programming

This saves us about 5000 reg writes per full update. This translates to about
40000 writes over the course of single eDP bootup.

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Don't use dc_link in link_encoder

dc_link is at a higher level than link_encoder, and we only want
higher-level components to be able to access lower-level ones,
not the other way around.

Signed-off-by: Andrew Jiang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Both timing_sync and multisync need stream_count > 1

Previous code threw a warning about misleading indentation

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Mikita Lipski <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Add tg_init interface.

Clear OPTC underflow status when init_hw.

Signed-off-by: Yongqiang Sun <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Enalbe blank data double buffer after mpc disconnected.

Signed-off-by: Yongqiang Sun <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: get remote dpcd caps for timing validation

Signed-off-by: Eric Yang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Only update dchub if hubbub is available

Signed-off-by: Yue Hin Lau <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Call ipp_program_bias_and_scale only if available

Also move some register definitions to common DCN regs.

Signed-off-by: Eric Bernstein <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: dal 3.1.11

Signed-off-by: Tony Cheng <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: hubbub function flipping true and false

no logic change

Signed-off-by: Yue Hin Lau <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Do post_update_surfaces on new state

Signed-off-by: Charlene Liu <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: function renaming for hubbub

following the naming convention with correct prefix

Signed-off-by: Yue Hin Lau <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: create new function prototype update_dchub for dcn

dcn version of update_dchub now uses hubbub instead of hwseq

Signed-off-by: Yue Hin Lau <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/virt: remove redundant variable pf2vf_ver

Variable pf2vf_ver is assigned but never read, it is redundant and
hence can be removed.

Cleans up clang warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:310:3: warning: Value stored
to 'pf2vf_ver' is never read

Reivewed-by: Horace Chen <[email protected]>
Signed-off-by: Colin Ian King <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/amdgpu: fix UVD mc offsets

When UVD bo is created, its size is based on the information from firmware
header (ucode_size_bytes). The same value should be be used when programming
UVD mc controller offsets, otherwise it can happen that
(mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point
AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end.

Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register,
AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't,
(mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point
AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end.

v2: move firmware size calculation into macro definition
v3: align firmware size to the gpu page size

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Piotr Redlewski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Multi display synchronization logic

This feature synchronizes multiple displays with various timings
to a display with the highest refresh rate
it is enabled if edid caps flag multi_display_sync is set to one

There are limitations on refresh rates allowed
that can be synchronized. That would
prevent from underflow and other potential
corruptions.

Multi display synchronization is using the
same functions as timing_sync in order to minimize
redunduncy and decision to disable synchronization is
based on trigger parametre set in DM

Feature is developed for DCN1 and DCE11

Signed-off-by: Mikita Lipski <[email protected]>
Reviewed-by: Mikita Lipski <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: Implement BO size validation V2

Validates BO size against each requested domain's total memory.

v2:
Make GTT size check a MUST to allow fall back to GTT.
Rmove redundant NULL check.

Signed-off-by: Andrey Grodzovsky <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: cleanup vm_size handling

It's pointless to have the same value twice, just always use max_pfn.

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result

Not sure what that should originally been good for, but it doesn't seem
to make any sense any more.

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: use dep_sync for CS dependency/syncobj

Otherwise, they could be optimized by scheduled fence.

Signed-off-by: Chunming Zhou <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/gfx8: Fix compute ring failure after resetting

Do ring clear before ring test, otherwise compute ring test will
fail after gpu resetting. Still can't find the root cause, just
workaround it.

Signed-off-by: Xiangliang.Yu <[email protected]>
Acked-by: Monk Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/ttm: remove ttm_bo_unreserve_ticket

Just another alias for ttm_bo_unreserve.

Signed-off-by: Christian König <[email protected]>
Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/ttm: user reservation object wrappers v2

Consistently use the reservation object wrappers instead of accessing
the ww_mutex directly.

Additional to that use the reservation object wrappers directly instead of
calling __ttm_bo_reserve with fixed parameters.

v2: fix typo

Signed-off-by: Christian König <[email protected]>
Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/ttm: consistently use reservation_object_unlock

Instead of having a confusing wrapper or call the underlying ww_mutex
function directly.

Signed-off-by: Christian König <[email protected]>
Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/ttm: move unlocking out of ttm_bo_cleanup_memtype_use

Needed for the next patch and makes the code quite a bit easier to
understand.

Signed-off-by: Christian König <[email protected]>
Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/scheduler: add WARN_ON for s_fence->parent

Signed-off-by: Chunming Zhou <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/scheduler: fix page protection of cb

We must remove the fence callback.

Signed-off-by: Chunming Zhou <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: revise retry init to fully cleanup driver

Retry at drm_dev_register instead of amdgpu_device_init.

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Pixel Ding <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

amdgpu/dm: Remove fb_location form fill_plane_attributes

We no longer set the framebuffer address here so this is now
dead code.

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Andrey Grodzovsky <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu:fix gpu recover missing skipping(v2)

if app close CTX right after IB submit, gpu recover
will fail to find out the entity behind this guilty
job thus lead to no job skipping for this guilty job.

to fix this corner case just move the increasement of
job->karma out of the entity iteration.

v2:
only do karma increasment if bad->s_priority != KERNEL
because we always consider KERNEL job be correct and always
want to recover an unfinished kernel job (sometimes kernel
job is interrupted by VF FLR or other GPU hang event)

Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Reviewed-By: Xiangliang Yu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu:read VRAMLOST from gim

Signed-off-by: Monk Liu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: bypass FB resizing for SRIOV VF

It introduces 900ms latency in exclusive mode which causes failure
of driver loading. Host can resize the BAR before guest staring,
so the resizing is not necessary here.

Signed-off-by: Pixel Ding <[email protected]>
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: release exclusive mode after hw_init

Signed-off-by: pding <[email protected]>
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdkfd: initialise kfd inside amdgpu_device_init

Also finalize kfd inside amdgpu_device_fini. kfd device_init needs
SRIOV exclusive accessing. Try to gather exclusive accessing to
reduce time consuming.

Signed-off-by: pding <[email protected]>
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: don't use ttm_bo_move_ttm in amdgpu_ttm_bind v2

Just allocate the GART space and fill it.

This prevents forcing the BO to be idle.

v2: don't unbind/bind at all, just fill the allocated GART space

Signed-off-by: Christian König <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: rename amdgpu_ttm_bind to amdgpu_ttm_alloc_gart

We actually don't bind here, but rather allocate GART space if necessary.

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: switch to use new SOC15 reg read/write macros for soc15 ih

Signed-off-by: Hawking Zhang <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: resize VRAM BAR for CPU access v6

Try to resize BAR0 to let CPU access all of VRAM.

v2: rebased, style cleanups, disable mem decode before resize,
    handle gmc_v9 as well, round size up to power of two.
v3: handle gmc_v6 as well, release and reassign all BARs in the driver.
v4: rename new function to amdgpu_device_resize_fb_bar,
    reenable mem decoding only if all resources are assigned.
v5: reorder resource release, return -ENODEV instead of BUG_ON().
v6: squash in rebase fix

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: refine SR-IOV firmware VRAM reservation to protect data

The previous solution will create a zero buffer on the system
domain and then move the zeroes to the VRAM. This will break the
original data on the VRAM.

Refine the code to create bo on VRAM domain directly and then remove
and re-create mem node to the exact position before bo_pin. This can
avoid breaking the data and will not cause eviction.

Signed-off-by: Horace Chen <[email protected]>
Reviewed-by: monk liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: retry init if exclusive mode request is failed

This is caused of that hypervisor fails to handle request, one known
issue is MMIO unblocking timeout. In theory we can retry init here.

Signed-off-by: pding <[email protected]>
Reviewed-by: Xiangliang Yu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: return error when sriov access requests get timeout

Reported-by: Sun Gary <[email protected]>
Signed-off-by: pding <[email protected]>
Reviewed-by: Xiangliang Yu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Remove fb_location parameter from get_fb_info

It's dead code.

Signed-off-by: Michel Dänzer <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

amdgpu: Remove AMDGPU_{HPD,CRTC_IRQ,PAGEFLIP_IRQ}_LAST

Not used anymore.

Signed-off-by: Michel Dänzer <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Use real number of CRTCs and HPDs in set_irq_funcs

Corresponding to the previous non-DC change.

Signed-off-by: Michel Dänzer <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

amdgpu/dce: Use actual number of CRTCs and HPDs in set_irq_funcs

Hardcoding the maximum numbers could result in spurious error messages
from the IRQ state callbacks, e.g. on Polaris 11/12:

[drm:dce_v11_0_set_pageflip_irq_state [amdgpu]] *ERROR* invalid pageflip crtc 5
[drm:amdgpu_irq_disable_all [amdgpu]] *ERROR* error disabling interrupt (-22)

Signed-off-by: Michel Dänzer <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Move conn_state to header

We'll need it in amdgpu_dm_mst_types.c as well.

Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Reviewed-by: Andrey Grodzovsky <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: dal 3.1.10

Signed-off-by: Tony Cheng <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: correct DP is always in full range or bt609

Signed-off-by: Charlene Liu <[email protected]>
Reviewed-by: Krunoslav Kovac <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix bug from last commit for hubbub

fix memory leak

Signed-off-by: Yue Hin Lau <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Move hdr_metadata from plane to stream

Need to move HDR Metadata from Surface to Stream since there is only one
infoframe possible per stream.

Also cleaning up some duplicate definitions.

Signed-off-by: Anthony Koo <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Apply VQ adjustments in MPO case

Signed-off-by: SivapiriyanKumarasamy <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: create new structure for hubbub

instantiating new structure hubbub in resource.c

Signed-off-by: Yue Hin Lau <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: dal 3.1.09

Signed-off-by: Tony Cheng <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Added disconnect dchub.

Add disable ttu interface to dcn10, when remove
mpc, disable ttu as well.

Signed-off-by: Yongqiang Sun <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: dal 3.1.08

Signed-off-by: Tony Cheng <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Not reset front end when program back end.

Since front end is programmed before back end programming,
no need to reset front end in back end programming.

Signed-off-by: Yongqiang Sun <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Power down front end in init_hw.

front end is initialized during init_hw, but not
power gated. There are some left over valuse and will
cause some diags test failed. Power gated all front
end pipes will make sure every test has same starting
point.

Signed-off-by: Yongqiang Sun <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Reject PPLib clock values if they are invalid

We should be sticking with the default clock values if the values
obtained from PPLib are bogus.

Signed-off-by: Andrew Jiang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: create new files for hubbub functions

moving hubbub functions to new file

Signed-off-by: Yue Hin Lau <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Complete TODO item: use new DRM iterator

Abandon new_crtcs array and use for_each_new iterator to acquire new
crtcs.

Signed-off-by: Leo (Sunpeng) Li <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Fix styling of freesync code in commit_tail

For better readability.

Signed-off-by: Leo (Sunpeng) Li <[email protected]>
Reviewed-by: Bhawanpreet Lakha <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Reviewed-by: Andrey Grodzovsky <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: move GART recovery into GTT manager v2

The GTT manager handles the GART address space anyway, so it is
completely pointless to keep the same information around twice.

v2: rebased

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Chunming Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: nuke amdgpu_ttm_is_bound() v2

Rename amdgpu_gtt_mgr_is_allocated() to amdgpu_gtt_mgr_has_gart_addr() and use
that instead.

v2: rename the function as well.

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Chunming Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu:fix random missing of FLR NOTIFY

Signed-off-by: Monk Liu <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/sriov:fix memory leak in psp_load_fw

for SR-IOV when doing gpu reset this routine shouldn't do
resource allocating otherwise memory leak

Signed-off-by: Monk Liu <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu:cleanup ucode_init_bo

1,no sriov check since gpu recover is unified
2,need CPU_ACCESS_REQUIRED flag for VRAM if SRIOV
because otherwise after following PIN the first allocated
VRAM bo is wasted due to some TTM mgr reason.

Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu:cleanup in_sriov_reset and lock_reset

since now gpu reset is unified with gpu_recover
for both bare-metal and SR-IOV:

1)rename in_sriov_reset to in_gpu_reset
2)move lock_reset from adev->virt to adev

Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu:implement new GPU recover(v3)

1,new imple names amdgpu_gpu_recover which gives more hint
on what it does compared with gpu_reset

2,gpu_recover unify bare-metal and SR-IOV, only the asic reset
part is implemented differently

3,gpu_recover will increase hang job karma and mark its entity/context
as guilty if exceeds limit

V2:

4,in scheduler main routine the job from guilty context  will be immedialy
fake signaled after it poped from queue and its fence be set with
"-ECANCELED" error

5,in scheduler recovery routine all jobs from the guilty entity would be
dropped

6,in run_job() routine the real IB submission would be skipped if @skip parameter
equales true or there was VRAM lost occured.

V3:

7,replace deprecated gpu reset, use new gpu recover

Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>