From: Felix Fietkau Date: Sun, 28 Sep 2008 22:11:40 +0000 (+0000) Subject: remove some targets which are not scheduled for inclusion in 8.09 X-Git-Tag: 8.09_rc1~68 X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=d5031914c2fb81609e3a76d54d6420dd820e4c2a;p=openwrt%2Fsvn-archive%2Fopenwrt.git remove some targets which are not scheduled for inclusion in 8.09 SVN-Revision: 12778 --- diff --git a/target/linux/amazon/Makefile b/target/linux/amazon/Makefile deleted file mode 100644 index 576f8508b9..0000000000 --- a/target/linux/amazon/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=mips -BOARD:=amazon -BOARDNAME:=Infineon Amazon -FEATURES:=squashfs jffs2 broken -LINUX_VERSION:=2.6.21.7 - -include $(INCLUDE_DIR)/target.mk - -define Target/Description - Build firmware images for Infineon Amazon boards -endef - -KERNELNAME:="uImage" - -$(eval $(call BuildTarget)) diff --git a/target/linux/amazon/base-files/etc/config/network b/target/linux/amazon/base-files/etc/config/network deleted file mode 100644 index 72e39f88a4..0000000000 --- a/target/linux/amazon/base-files/etc/config/network +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (C) 2006 OpenWrt.org - -config interface loopback - option ifname lo - option proto static - option ipaddr 127.0.0.1 - option netmask 255.0.0.0 - -config interface lan - option ifname eth1 - option type bridge - option proto static - option ipaddr 192.168.1.1 - option netmask 255.255.255.0 diff --git a/target/linux/amazon/config-2.6.21 b/target/linux/amazon/config-2.6.21 deleted file mode 100644 index 1da6b9b702..0000000000 --- a/target/linux/amazon/config-2.6.21 +++ /dev/null @@ -1,210 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_AMAZON=y -CONFIG_AMAZON_ASC_UART=y -CONFIG_AMAZON_MTD=y -CONFIG_AMAZON_NET_SW=y -CONFIG_AMAZON_PCI=y -CONFIG_AMAZON_WDT=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -# CONFIG_ATM is not set -# CONFIG_ATMEL is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BCM43XX is not set -CONFIG_BITREVERSE=y -# CONFIG_BT is not set -CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/bin/sh" -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR1=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_DDB5477 is not set -# CONFIG_DM9000 is not set -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_EARLY_PRINTK=y -CONFIG_FS_POSIX_ACL=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -# CONFIG_GENERIC_GPIO is not set -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -# CONFIG_GEN_RTC is not set -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_STD_PC_SERIAL_PORT=y -# CONFIG_HERMES is not set -# CONFIG_HOSTAP is not set -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -# CONFIG_I2C is not set -# CONFIG_IDE is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IPW2100 is not set -# CONFIG_IPW2200 is not set -CONFIG_IRQ_CPU=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -CONFIG_MIPS=y -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_EV64120 is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_MTX1 is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -CONFIG_MTD_AMAZON_BUS_WIDTH_16=y -# CONFIG_MTD_AMAZON_BUS_WIDTH_32 is not set -# CONFIG_MTD_AMAZON_BUS_WIDTH_8 is not set -# CONFIG_MTD_AMAZON_FLASH_SIZE_16 is not set -# CONFIG_MTD_AMAZON_FLASH_SIZE_2 is not set -CONFIG_MTD_AMAZON_FLASH_SIZE_4=y -# CONFIG_MTD_AMAZON_FLASH_SIZE_8 is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_GEOMETRY is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set -# CONFIG_MTD_ONENAND is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PCI is not set -# CONFIG_MTD_PHRAM is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_BANKWIDTH=0 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_START=0x0 -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3 -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_NET_PCI is not set -CONFIG_NET_SCH_FIFO=y -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_PAGE_SIZE_16KB is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_64KB is not set -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNPACPI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_PRISM54 is not set -# CONFIG_RTC is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_SERIAL_8250 is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_TRAD_SIGNALS=y -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_USB is not set diff --git a/target/linux/amazon/files/arch/mips/amazon/Kconfig b/target/linux/amazon/files/arch/mips/amazon/Kconfig deleted file mode 100644 index 179e35efd2..0000000000 --- a/target/linux/amazon/files/arch/mips/amazon/Kconfig +++ /dev/null @@ -1,63 +0,0 @@ -# copyright 2007 john crispin - -menu "Amazon built-in" - -config AMAZON_ASC_UART - bool "Amazon asc uart" - select SERIAL_CORE - select SERIAL_CORE_CONSOLE - default y - -config AMAZON_PCI - bool "Amazon PCI support" - default y - select HW_HAS_PCI - select PCI - -config AMAZON_NET_SW - bool "Amazon network" - default y - -config AMAZON_WDT - bool "Amazon watchdog timer" - default y - -config AMAZON_MTD - bool "Amazon MTD map" - default y - -choice - prompt "Flash Size" - depends on AMAZON_MTD - -config MTD_AMAZON_FLASH_SIZE_2 - bool "2MB" - -config MTD_AMAZON_FLASH_SIZE_4 - bool "4MB" - -config MTD_AMAZON_FLASH_SIZE_8 - bool "8MB" - -config MTD_AMAZON_FLASH_SIZE_16 - bool "16MB" - -endchoice - -choice - prompt "Bus Width" - depends on AMAZON_MTD - -config MTD_AMAZON_BUS_WIDTH_8 - bool "8-bit" - -config MTD_AMAZON_BUS_WIDTH_16 - bool "16-bit" - -config MTD_AMAZON_BUS_WIDTH_32 - bool "32-bit" - -endchoice - - -endmenu diff --git a/target/linux/amazon/files/arch/mips/amazon/Makefile b/target/linux/amazon/files/arch/mips/amazon/Makefile deleted file mode 100644 index 9cdc100b8c..0000000000 --- a/target/linux/amazon/files/arch/mips/amazon/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright 2007 openwrt.org -# John Crispin -# -# Makefile for Infineon Amazon -# -obj-y := dma-core.o interrupt.o prom.o setup.o -obj-$(CONFIG_PCI) += pci.o - diff --git a/target/linux/amazon/files/arch/mips/amazon/dma-core.c b/target/linux/amazon/files/arch/mips/amazon/dma-core.c deleted file mode 100644 index 242bc77af2..0000000000 --- a/target/linux/amazon/files/arch/mips/amazon/dma-core.c +++ /dev/null @@ -1,1455 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - */ -//----------------------------------------------------------------------- -/* - * Description: - * Driver for Infineon Amazon DMA - */ -//----------------------------------------------------------------------- -/* Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com] - * Created: 7-April-2004 - */ -//----------------------------------------------------------------------- -/* History - * Last changed on: 4-May-2004 - * Last changed by: - * Reason: debug - */ -//----------------------------------------------------------------------- -/* Last changed on: 03-Dec-2004 - * Last changed by: peng.liu@infineon.com - * Reason: recover from TPE bug - */ - -//000004:fchang 2005/6/2 Modified by Linpeng as described below -//----------------------------------------------------------------------- -/* Last changed on: 28-Jan-2004 - * Last changed by: peng.liu@infineon.com - * Reason: - * - handle "out of memory" bug - */ -//000003:tc.chen 2005/06/16 fix memory leak when Tx buffer full (heaving traffic). -//507261:tc.chen 2005/07/26 re-organize code address map to improve performance. - -#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -#define MODVERSIONS -#endif - -#if defined(MODVERSIONS) && !defined(__GENKSYMS__) -#include -#endif - -#ifndef EXPORT_SYMTAB -#define EXPORT_SYMTAB /* need this one 'cause we export symbols */ -#endif - -#undef DMA_NO_POLLING - -/* no TX interrupt handling */ -#define NO_TX_INT -/* need for DMA workaround */ -#undef AMAZON_DMA_TPE_AAL5_RECOVERY - -#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY -#define MAX_SYNC_FAILS 1000000 // 000004:fchang -unsigned int dma_sync_fails = 0; -unsigned int total_dma_tpe_reset = 0; -int (*tpe_reset) (void); -int (*tpe_start) (void); -int (*tpe_inject) (void); -#endif // AMAZON_DMA_TPE_AAL5_RECOVERY - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include "dma-core.h" - -#define AMAZON_DMA_EMSG(fmt, args...) printk( KERN_ERR "%s: " fmt,__FUNCTION__, ## args) - -static irqreturn_t dma_interrupt(int irq, void *dev_id); -extern void mask_and_ack_amazon_irq(unsigned int irq_nr); - -/***************************************** global data *******************************************/ -u64 *g_desc_list; -dev_list *g_current_dev = NULL; -dev_list *g_head_dev = NULL; -dev_list *g_tail_dev = NULL; -channel_info g_log_chan[CHAN_TOTAL_NUM + 1]; -struct proc_dir_entry *g_amazon_dma_dir; -static u8 rx_chan_list_len = 0; -static u8 tx_chan_list_len = 0; -static int rx_chan_list[RX_CHAN_NUM + 1]; -static int tx_chan_list[TX_CHAN_NUM + 1]; -static u32 comb_isr_mask[CHAN_TOTAL_NUM]; - -static inline int is_rx_chan(int chan_no) -/*judge if this is an rx channel*/ -{ - int result = 0; - if (chan_no < RX_CHAN_NUM) - result = 1; - return result; -} - -/* Ugly, Channel ON register is badly mapped to channel no. */ -static u8 ch_on_mapping[CHAN_TOTAL_NUM] = - { 0, 1, 2, 3, 6, 7, 10, 4, 5, 8, 9, 11 }; - -/* Brief: check wether the chan_no is legal - * Parameter: chan_no: logical channel number - * Return: 0 if is not valid - * 1 if is valid - */ -static inline int is_valid_dma_ch(int chan_no) -{ - return ((chan_no >= 0) && (chan_no < CHAN_TOTAL_NUM)); -} - -/* Brief: check whether a channel is open through Channel ON register - * Parameter: chan_no: logical channel number - * Return: 1 channel is open - * 0 not yet - * EINVAL: invalid parameter - */ -static inline int is_channel_open(int chan_no) -{ - return (AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) & - (1 << ch_on_mapping[chan_no])); -} - -/* Brief: add a list entry - * Description: - * always add to the tail and no redundancy allowed. (i.e. entries are unique) - * 0 : entry deleted - * <0 : not deleted (due to not unique) - */ -static inline int _add_list_entry(int *list, int size_of_list, int entry) -{ - int i; - for (i = 0; i < size_of_list; i++) { - if (list[i] == entry) - break; - if (list[i] < 0) { - list[i] = entry; - return 0; - } - } - return -1; -} - -/* Brief: delete a list entry - * Description: - * find the entry and remove it. shift all entries behind it one step forward if necessary\ - * Return: - * 0 : entry deleted - * <0 : not deleted (due to not found?) - */ -static inline int _delete_list_entry(int *list, int size_of_list, - int entry) -{ - int i, j; - for (i = 0; i < size_of_list; i++) { - if (list[i] == entry) { - for (j = i; j < size_of_list; j++) { - list[j] = list[j + 1]; - if (list[j + 1] < 0) { - break; - } - } - return 0; - } - } - return -1; -} - -/* Brief: enable a channel through Channel ON register - * Parameter: chan_no: logical channel number - * Description: - * Please don't open a channel without a valid descriptor (hardware pitfall) - */ -static inline void open_channel(int chan_no) -{ - AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) |= (1 << ch_on_mapping[chan_no]); - if (is_rx_chan(chan_no)) { - if (_add_list_entry(rx_chan_list, RX_CHAN_NUM, chan_no) == 0) { - rx_chan_list_len++; - } else { - AMAZON_DMA_DMSG("cannot add chan %d to open list\n", chan_no); - } - } else { - if (_add_list_entry(tx_chan_list, TX_CHAN_NUM, chan_no) == 0) { - tx_chan_list_len++; - } else { - AMAZON_DMA_DMSG("cannot add chan %d to open list\n", chan_no); - } - } -} - -/* Brief: disable a channel through Channel ON register - * Parameter: chan_no: logical channel number - */ - -static inline void close_channel(int chan_no) -{ - AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &= ~(1 << ch_on_mapping[chan_no]); - if (is_rx_chan(chan_no)) { - if (_delete_list_entry(rx_chan_list, RX_CHAN_NUM, chan_no) == 0) { - rx_chan_list_len--; - } else { - AMAZON_DMA_DMSG("cannot remove chan %d from open list \n", - chan_no); - } - } else { - if (_delete_list_entry(tx_chan_list, TX_CHAN_NUM, chan_no) == 0) { - tx_chan_list_len--; - } else { - AMAZON_DMA_DMSG("cannot remove chan %d from open list \n", - chan_no); - } - } -} - -/* Brief: clear RX interrupt - */ -inline void rx_chan_clear_isr(int chan_no) -{ -#ifdef DMA_NO_POLLING - AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) = - (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * - AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP | DMA_ISR_CMDCPT - | DMA_ISR_DURR)); -#else - AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) = - (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * - AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP | - DMA_ISR_CMDCPT)); -#endif -} - - -/* Brief: hacking function, this will reset all descriptors back to DMA - */ -static void dma_reset_all_descriptors(int chan_no) -{ - volatile struct rx_desc *rx_desc_p = NULL; - int i; - rx_desc_p = - (struct rx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base; - for (i = 0; i < g_log_chan[chan_no].desc_len; i++) { - rx_desc_p->status.word &= - (~(DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | DMA_DESC_CPT_SET)); - rx_desc_p->status.word |= - (DMA_DESC_OWN_DMA | g_log_chan[chan_no].packet_size); - rx_desc_p++; - } -} - -#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY -/* Brief: Reset DMA descriptors - */ -static void amazon_dma_reset_tpe_rx(int chan_no) -{ - struct tx_desc *tx_desc_p = NULL; - int j, i = 0; - - // wait until all TX channels stop transmitting - for (j = 9; j <= 10; j++) { - tx_desc_p = - (struct tx_desc *) g_desc_list + - g_log_chan[j].offset_from_base; - for (i = 0; i < g_log_chan[j].desc_len; i++) { - while ((tx_desc_p->status.field.OWN != CPU_OWN)) { - AMAZON_DMA_DMSG("DMA TX in progress\n"); // 000004:fchang - udelay(100); - } - tx_desc_p++; - } - } - - if (tpe_reset) { - total_dma_tpe_reset++; - AMAZON_DMA_DMSG - ("\n===============resetting TPE========================== \n"); - if ((*tpe_reset) ()) { - panic("cannot reset TPE engien\n"); // 000004:fchang - } - } else { - panic("no tpe_reset function\n"); // 000004:fchang - return; - } - dma_reset_all_descriptors(chan_no); - rx_chan_clear_isr(chan_no); - mb(); - - // send EoP - if (tpe_inject) { - if ((*tpe_inject) ()) { - panic("cannot inject a cell\n"); // 000004:fchang - } - } else { - AMAZON_DMA_EMSG("no tpe_inject function\n"); - return; - } - mb(); - while (1) { - if (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT)) { - rx_chan_clear_isr(chan_no); - mb(); - dma_reset_all_descriptors(chan_no); - if (g_log_chan[chan_no].current_desc == - (g_log_chan[chan_no].desc_len - 1)) { - g_log_chan[chan_no].current_desc = 0; - } else { - g_log_chan[chan_no].current_desc++; - } - break; - } - mdelay(1); - } - mb(); -#if 0 - AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &= ~(1 << ch_on_mapping[chan_no]); - while (AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) & - (1 << ch_on_mapping[chan_no])) { - printk("TPE channel still on\n"); - mdelay(1); - } - - // AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = (1<current_rx_chan = - chan_no - g_log_chan[chan_no].dma_dev->logic_rx_chan_base; - - // workaround for DMA pitfall: complete bit set happends before the - // other two bits (own,eop) are ready - if ((rx_desc_p->status.field.EoP != 1) - || (rx_desc_p->status.field.OWN != CPU_OWN) - || (rx_desc_p->status.field.data_length == - g_log_chan[chan_no].packet_size)) { -#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY - if (chan_no == 4 || chan_no == 5) { - dma_sync_fails++; - if (dma_sync_fails > MAX_SYNC_FAILS) { - // detect bug - rx_desc_p0 = - (struct rx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base; - rx_desc_p1 = - (struct rx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base + 1; - if ((rx_desc_p0->status.field.OWN == CPU_OWN - && rx_desc_p0->status.field.EoP != 1) - && (rx_desc_p1->status.field.OWN == CPU_OWN - && rx_desc_p1->status.field.EoP != 1)) { - amazon_dma_reset_tpe_rx(chan_no); - dma_sync_fails = 0; - return; - } - dma_sync_fails = 0; - AMAZON_DMA_DMSG("too many times ch:%d\n", chan_no); // 000004:fchang - return; - } - udelay(10); // 000004:fchang - } -#endif // //AMAZON_DMA_TPE_AAL5_RECOVERY - return; - } - - /* inform the upper layer to receive the packet */ - g_log_chan[chan_no].intr_handler(g_log_chan[chan_no].dma_dev, RCV_INT); - /* check the next descriptor, if still contains the incoming packet, - then do not clear the interrupt status */ - rx_desc_p = - (struct rx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base + - g_log_chan[chan_no].current_desc; - if (! - ((rx_desc_p->status.field.OWN == CPU_OWN) - && (rx_desc_p->status.field.C == 1))) { - rx_chan_clear_isr(chan_no); - } -} - - -/* Brief: TX channel interrupt handler - * Parameter: TX channel no - * Description: the interrupt handler for each TX channel - * 1. check all the descripters,if any of them had transmitted a packet, then free buffer - * because we cannot garantee the which one has already transmitted out, we have to go through all the descriptors here - * 2. clear the interrupt status bit - */ -inline void tx_chan_intr_handler(int chan_no) -{ - struct tx_desc *tx_desc_p = NULL; - int i = 0; - - tx_desc_p = - (struct tx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base; - - for (i = 0; i < g_log_chan[chan_no].desc_len; i++) { - if ((tx_desc_p->status.field.OWN == CPU_OWN) - && (tx_desc_p->status.field.C == 1)) { - /* if already transmitted, then free the buffer */ - g_log_chan[chan_no]. - buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), - g_log_chan[chan_no].opt[i]); - tx_desc_p->status.field.C = 0; - /* inform the upper layer about the completion of the - transmitted packet, the upper layer may want to free the - packet */ - g_log_chan[chan_no].intr_handler(g_log_chan[chan_no].dma_dev, - TRANSMIT_CPT_INT); - } - tx_desc_p++; - } - - /* after all these operations, clear the interrupt status bit */ - AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) = - (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * - AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP | - DMA_ISR_CMDCPT)); -} - -/* Brief: DMA interrupt handler - */ -static irqreturn_t dma_interrupt(int irq, void *dev_id) -{ - int i = 0; - int chan_no; - u32 isr = 0; -#ifdef NO_TX_INT // 000004:fchang - static int cnt = 0; // 000004:fchang -#endif // 000004:fchang - while ((isr = - AMAZON_DMA_REG32(AMAZON_DMA_COMB_ISR)) & (COMB_ISR_RX_MASK | - COMB_ISR_TX_MASK)) { - if (isr & COMB_ISR_RX_MASK) { - // RX Channels: start WFQ algorithm - chan_no = CHAN_TOTAL_NUM; - for (i = 0; i < RX_CHAN_NUM; i++) { - if ((isr & (comb_isr_mask[i])) - && (g_log_chan[i].weight > 0)) { - if (g_log_chan[chan_no].weight < g_log_chan[i].weight) { - chan_no = i; - } - } - } - if (chan_no < CHAN_TOTAL_NUM) { - rx_chan_intr_handler(chan_no); - } else { - for (i = 0; i < RX_CHAN_NUM; i++) { - g_log_chan[i].weight = g_log_chan[i].default_weight; - } - } - } -#ifdef NO_TX_INT - cnt++; - if (cnt == 10) { - cnt = 0; - for (i = 0; i < tx_chan_list_len; i++) { - if (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - tx_chan_list[i] * - AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP)) { - tx_chan_intr_handler(tx_chan_list[i]); - } - } - } -#else - if (isr & COMB_ISR_TX_MASK) { - // TX channels: RR - for (i = 0; i < tx_chan_list_len; i++) { - if (isr & (comb_isr_mask[tx_chan_list[i]])) { - tx_chan_intr_handler(tx_chan_list[i]); - } - } - } -#endif - } // while - return IRQ_HANDLED; -} - - -/* Brief: read a packet from DMA RX channel - * Parameter: - * Return: packet length - * Description: - * This is called back in a context of DMA interrupt - * 1. prepare new descriptor - * 2. read data - * 3. update WFQ weight - */ -//507261:tc.chen int dma_device_read(struct dma_device_info* dma_dev, u8** dataptr, void** opt) -int asmlinkage dma_device_read(struct dma_device_info *dma_dev, - u8 ** dataptr, void **opt) -{ - u8 *buf; - int len; - int chan_no = 0; - int byte_offset = 0; - - struct rx_desc *rx_desc_p; - void *p = NULL; - int current_desc; - - chan_no = dma_dev->logic_rx_chan_base + dma_dev->current_rx_chan; - current_desc = g_log_chan[chan_no].current_desc; - rx_desc_p = - (struct rx_desc *) (g_desc_list + - g_log_chan[chan_no].offset_from_base + - current_desc); - buf = (u8 *) __va(rx_desc_p->Data_Pointer); /* extract the virtual - address of the data - pointer */ - len = rx_desc_p->status.field.data_length; /* extract the data length */ -#ifndef CONFIG_MIPS_UNCACHED - dma_cache_inv((unsigned long) buf, len); -#endif // CONFIG_MIPS_UNCACHED - *(u32 *) dataptr = (u32) buf; - if (opt) { - *(int *) opt = (int) g_log_chan[chan_no].opt[current_desc]; /* read - out - the - opt - information */ - } - - buf = - (u8 *) g_log_chan[chan_no].buffer_alloc(g_log_chan[chan_no]. - packet_size, &byte_offset, - &p); - // should check null!!!! - if (buf == NULL || p == NULL) { - *(u32 *) dataptr = 0; - *(int *) opt = 0; - len = 0; - } else { - g_log_chan[chan_no].opt[current_desc] = p; - /* reduce the weight for WFQ algorithm */ - g_log_chan[chan_no].weight -= len; - rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf); - } - if (current_desc == g_log_chan[chan_no].desc_len - 1) { - current_desc = 0; - } else { - current_desc++; - } - g_log_chan[chan_no].current_desc = current_desc; - - rx_desc_p->status.word = DMA_DESC_OWN_DMA - | (byte_offset << DMA_DESC_BYTEOFF_SHIFT) - | g_log_chan[chan_no].packet_size; - return len; -} - -/* Brief: write a packet through DMA RX channel to peripheral - * Parameter: - * Return: packet length - * Description: - * - */ -u64 dma_tx_drop = 0; -//507261:tc.chen int dma_device_write(struct dma_device_info* dma_dev, u8* dataptr, int len,void* opt) -int asmlinkage dma_device_write(struct dma_device_info *dma_dev, - u8 * dataptr, int len, void *opt) -{ - int chan_no = 0; - struct tx_desc *tx_desc_p; - - int byte_offset = 0; - int current_desc; - static int cnt = 0; // 000004:fchang - - unsigned long flag; - local_irq_save(flag); - - chan_no = dma_dev->logic_tx_chan_base + dma_dev->current_tx_chan; - current_desc = g_log_chan[chan_no].current_desc; - tx_desc_p = - (struct tx_desc *) (g_desc_list + - g_log_chan[chan_no].offset_from_base + - current_desc); - // 000003:tc.chen if(tx_desc_p->status.field.OWN==DMA_OWN){ - if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C == 1) { // 000003:tc.chen - AMAZON_DMA_DMSG("no TX desc for CPU, drop packet\n"); - dma_tx_drop++; - g_log_chan[chan_no].intr_handler(dma_dev, TX_BUF_FULL_INT); - local_irq_restore(flag); - return 0; - } - g_log_chan[chan_no].opt[current_desc] = opt; - - /* byte offset----to adjust the starting address of the data buffer, - should be multiple of the burst length. */ - byte_offset = - ((u32) CPHYSADDR((u32) dataptr)) % (g_log_chan[chan_no].burst_len * - 4); -#ifndef CONFIG_MIPS_UNCACHED - dma_cache_wback((unsigned long) dataptr, len); - wmb(); -#endif // CONFIG_MIPS_UNCACHED - - tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset; - wmb(); - tx_desc_p->status.word = DMA_DESC_OWN_DMA - | DMA_DESC_SOP_SET - | DMA_DESC_EOP_SET | (byte_offset << DMA_DESC_BYTEOFF_SHIFT) - | len; - wmb(); - if (is_channel_open(chan_no) == 0) { - // turn on if necessary - open_channel(chan_no); - } -#ifdef DMA_NO_POLLING - if ((AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * AMAZON_DMA_CH_STEP) & (DMA_ISR_DURR | DMA_ISR_CPT)) == - (DMA_ISR_DURR)) { - // clear DURR if (CPT is AND set and DURR is set) - AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + - chan_no * AMAZON_DMA_CH_STEP) = DMA_ISR_DURR; - } -#endif - - if (current_desc == (g_log_chan[chan_no].desc_len - 1)) { - current_desc = 0; - } else { - current_desc++; - } - - - g_log_chan[chan_no].current_desc = current_desc; - tx_desc_p = - (struct tx_desc *) (g_desc_list + - g_log_chan[chan_no].offset_from_base + - current_desc); - // 000003:tc.chen if(tx_desc_p->status.field.OWN==DMA_OWN){ - if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C == 1) { // 000003:tc.chen - g_log_chan[chan_no].intr_handler(dma_dev, TX_BUF_FULL_INT); - } -#ifdef NO_TX_INT -//000004:fchang Start - cnt++; - if (cnt == 5) { - cnt = 0; - tx_chan_intr_handler(chan_no); - } -//000004:fchang End -#endif - local_irq_restore(flag); // 000004:fchang - return len; -} - - - -int desc_list_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int i; - u32 *p = (u32 *) g_desc_list; - int len = 0; - len += sprintf(buf + len, "descriptor list:\n"); - for (i = 0; i < 120; i++) { - len += sprintf(buf + len, "%d\n", i); - len += sprintf(buf + len, "%08x\n", *(p + i * 2 + 1)); - len += sprintf(buf + len, "%08x\n", *(p + i * 2)); - - } - - return len; - -} - -int channel_weight_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - - // int i=0; - int len = 0; - len += sprintf(buf + len, "Qos dma channel weight list\n"); - len += - sprintf(buf + len, - "channel_num default_weight current_weight device Tx/Rx\n"); - len += - sprintf(buf + len, - " 0 %08x %08x Switch Rx0\n", - g_log_chan[0].default_weight, g_log_chan[0].weight); - len += - sprintf(buf + len, - " 1 %08x %08x Switch Rx1\n", - g_log_chan[1].default_weight, g_log_chan[1].weight); - len += - sprintf(buf + len, - " 2 %08x %08x Switch Rx2\n", - g_log_chan[2].default_weight, g_log_chan[2].weight); - len += - sprintf(buf + len, - " 3 %08x %08x Switch Rx3\n", - g_log_chan[3].default_weight, g_log_chan[3].weight); - len += - sprintf(buf + len, - " 4 %08x %08x Switch Tx0\n", - g_log_chan[4].default_weight, g_log_chan[4].weight); - len += - sprintf(buf + len, - " 5 %08x %08x Switch Tx1\n", - g_log_chan[5].default_weight, g_log_chan[5].weight); - /* - len+=sprintf(buf+len," 6 %08x %08x TPE - Rx0\n",g_log_chan[6].default_weight, g_log_chan[6].weight); - len+=sprintf(buf+len," 7 %08x %08x TPE - Rx0\n",g_log_chan[7].default_weight, g_log_chan[7].weight); - len+=sprintf(buf+len," 8 %08x %08x TPE - Tx0\n",g_log_chan[8].default_weight, g_log_chan[8].weight); - len+=sprintf(buf+len," 9 %08x %08x TPE - Rx0\n",g_log_chan[9].default_weight, g_log_chan[9].weight); - len+=sprintf(buf+len," 10 %08x %08x DPLUS - Rx0\n",g_log_chan[10].default_weight, g_log_chan[10].weight); - len+=sprintf(buf+len," 11 %08x %08x DPLUS - Rx0\n",g_log_chan[11].default_weight, g_log_chan[11].weight); */ - return len; -} - -int dma_register_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - dev_list *temp_dev; - int len = 0;; - - len += sprintf(buf + len, "amazon dma driver\n"); - len += sprintf(buf + len, "version 1.0\n"); - len += sprintf(buf + len, "devices registered:\n"); - for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) { - len += sprintf(buf + len, "%s ", temp_dev->dev->device_name); - } - len += sprintf(buf + len, "\n"); - len += sprintf(buf + len, "CH_ON=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH_ON)); - len += sprintf(buf + len, "CH_RST=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH_RST)); - len += sprintf(buf + len, "CH0_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR)); - len += sprintf(buf + len, "CH1_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH1_ISR)); - len += sprintf(buf + len, "CH2_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH2_ISR)); - len += sprintf(buf + len, "CH3_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH3_ISR)); - len += sprintf(buf + len, "CH4_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH4_ISR)); - len += sprintf(buf + len, "CH5_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH5_ISR)); - len += sprintf(buf + len, "CH6_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH6_ISR)); - len += sprintf(buf + len, "CH7_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH7_ISR)); - len += sprintf(buf + len, "CH8_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH8_ISR)); - len += - sprintf(buf + len, "CH9_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH9_ISR)); - len += - sprintf(buf + len, "CH10_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH10_ISR)); - len += - sprintf(buf + len, "CH11_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH11_ISR)); - len += - sprintf(buf + len, "LCH0_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK)); - len += - sprintf(buf + len, "LCH1_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH1_MSK)); - len += - sprintf(buf + len, "LCH2_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH2_MSK)); - len += - sprintf(buf + len, "LCH3_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH3_MSK)); - len += - sprintf(buf + len, "LCH4_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH4_MSK)); - len += - sprintf(buf + len, "LCH5_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH5_MSK)); - len += - sprintf(buf + len, "LCH6_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH6_MSK)); - len += - sprintf(buf + len, "LCH7_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH7_MSK)); - len += - sprintf(buf + len, "LCH8_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH8_MSK)); - len += - sprintf(buf + len, "LCH9_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH9_MSK)); - len += - sprintf(buf + len, "LCH10_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH10_MSK)); - len += - sprintf(buf + len, "LCH11_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH11_MSK)); - len += - sprintf(buf + len, "Desc_BA=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_Desc_BA)); - len += - sprintf(buf + len, "LCH0_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN)); - len += - sprintf(buf + len, "LCH1_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_LEN)); - len += - sprintf(buf + len, "LCH2_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH2_DES_LEN)); - len += - sprintf(buf + len, "LCH3_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH3_DES_LEN)); - len += - sprintf(buf + len, "LCH4_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH4_DES_LEN)); - len += - sprintf(buf + len, "LCH5_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH5_DES_LEN)); - len += - sprintf(buf + len, "LCH6_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH6_DES_LEN)); - len += - sprintf(buf + len, "LCH7_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH7_DES_LEN)); - len += - sprintf(buf + len, "LCH8_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH8_DES_LEN)); - len += - sprintf(buf + len, "LCH9_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH9_DES_LEN)); - len += - sprintf(buf + len, "LCH10_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH10_DES_LEN)); - len += - sprintf(buf + len, "LCH11_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH11_DES_LEN)); - len += - sprintf(buf + len, "LCH1_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_OFST)); - len += - sprintf(buf + len, "LCH2_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH2_DES_OFST)); - len += - sprintf(buf + len, "LCH3_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH3_DES_OFST)); - len += - sprintf(buf + len, "LCH4_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH4_DES_OFST)); - len += - sprintf(buf + len, "LCH5_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH5_DES_OFST)); - len += - sprintf(buf + len, "LCH6_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH6_DES_OFST)); - len += - sprintf(buf + len, "LCH7_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH7_DES_OFST)); - len += - sprintf(buf + len, "LCH8_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH8_DES_OFST)); - len += - sprintf(buf + len, "LCH9_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH9_DES_OFST)); - len += - sprintf(buf + len, "LCH10_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH10_DES_OFST)); - len += - sprintf(buf + len, "LCH11_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH11_DES_OFST)); - len += - sprintf(buf + len, "AMAZON_DMA_SW_BL=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_SW_BL)); - len += - sprintf(buf + len, "AMAZON_DMA_TPE_BL=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_TPE_BL)); - len += - sprintf(buf + len, "DPlus2FPI_BL=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_DPlus2FPI_BL)); - len += - sprintf(buf + len, "GRX_BUF_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_GRX_BUF_LEN)); - len += - sprintf(buf + len, "DMA_ECON_REG=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG)); - len += - sprintf(buf + len, "POLLING_REG=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG)); - len += - sprintf(buf + len, "CH_WGT=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH_WGT)); - len += - sprintf(buf + len, "TX_WGT=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_TX_WGT)); - len += - sprintf(buf + len, "DPlus2FPI_CLASS=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_DPLus2FPI_CLASS)); - len += - sprintf(buf + len, "COMB_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_COMB_ISR)); -#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY - len += sprintf(buf + len, "TPE fails:%u\n", total_dma_tpe_reset); // 000004:fchang -#endif - return len; -} - -/* Brief: initialize DMA registers - * Description: - */ -static void dma_chip_init(void) -{ - int i; - for (i = 0; i < CHAN_TOTAL_NUM; i++) { - AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_OFST + - i * AMAZON_DMA_CH_STEP) = DEFAULT_OFFSET; - } -#ifdef DMA_NO_POLLING - AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG) = 0; -#else - // enable poll mode and set polling counter - AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG) = DMA_POLLING_CNT | DMA_POLLING_ENABLE; -#endif - // to enable DMA drop - AMAZON_DMA_REG32(AMAZON_DMA_GRX_BUF_LEN) = 0x10000; -} - -int insert_dev_list(dev_list * dev) -{ - dev_list *temp_dev; - if (g_head_dev == NULL) { - g_head_dev = dev; - g_tail_dev = dev; - dev->prev = NULL; - dev->next = NULL; - } else { - for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) { - if (temp_dev->weight < dev->weight) { - if (temp_dev->prev) - temp_dev->prev->next = dev; - - dev->prev = temp_dev->prev; - dev->next = temp_dev; - temp_dev->prev = dev; - if (temp_dev == g_head_dev) - g_head_dev = dev; - break; - } - } - - if (!temp_dev) { - g_tail_dev->next = dev; - dev->prev = g_tail_dev; - dev->next = NULL; - g_tail_dev = dev; - } - - } - - return 1; -} - -u8 *common_buffer_alloc(int len, int *byte_offset, void **opt) -{ - u8 *buffer = (u8 *) kmalloc(len * sizeof(u8), GFP_KERNEL); - *byte_offset = 0; - return buffer; - -} - -int common_buffer_free(u8 * dataptr, void *opt) -{ - if (dataptr) - kfree(dataptr); - return 0; -} - - -int register_dev(struct dma_device_info *dma_dev) -{ - int i, j, temp; - int burst_reg = 0; - u8 *buffer; - void *p = NULL; - int byte_offset = 0; - - struct rx_desc *rx_desc_p; - struct tx_desc *tx_desc_p; - if (strcmp(dma_dev->device_name, "switch1") == 0) { - AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = SWITCH1_RST_MASK; // resest - // channel - // 1st - AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG) |= 0x3; // endian - // conversion - // for Switch - burst_reg = AMAZON_DMA_SW_BL; - dma_dev->logic_rx_chan_base = switch_rx_chan_base; - dma_dev->logic_tx_chan_base = switch_tx_chan_base; - } - - else if (strcmp(dma_dev->device_name, "switch2") == 0) { - AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = SWITCH2_RST_MASK; // resest - // channel - // 1st - AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG) |= 0x3; // endian - // conversion - // for Switch - burst_reg = AMAZON_DMA_SW_BL; - dma_dev->logic_rx_chan_base = switch2_rx_chan_base; - dma_dev->logic_tx_chan_base = switch2_tx_chan_base; - - } else if (strcmp(dma_dev->device_name, "TPE") == 0) { - AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = TPE_RST_MASK; // resest - // channel 1st - // - burst_reg = AMAZON_DMA_TPE_BL; - dma_dev->logic_rx_chan_base = TPE_rx_chan_base; - dma_dev->logic_tx_chan_base = TPE_tx_chan_base; - } - - else if (strcmp(dma_dev->device_name, "DPlus") == 0) { - AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = DPlus2FPI_RST_MASK; // resest - // channel - // 1st - dma_dev->logic_rx_chan_base = DPLus2FPI_rx_chan_base; - dma_dev->logic_tx_chan_base = DPLus2FPI_tx_chan_base; - - } - - i = 0; - for (temp = dma_dev->tx_burst_len; temp > 2; temp /= 2) { - i += 1; - } - - - AMAZON_DMA_REG32(burst_reg) = i << 1; - i = 0; - for (temp = dma_dev->rx_burst_len; temp > 2; temp /= 2) { - i += 1; - } - AMAZON_DMA_REG32(burst_reg) += i; - - for (i = 0; i < dma_dev->num_rx_chan; i++) { - - temp = dma_dev->logic_rx_chan_base + i; - g_log_chan[temp].dma_dev = dma_dev; - g_log_chan[temp].weight = dma_dev->rx_chan[i].weight; - g_log_chan[temp].default_weight = dma_dev->rx_chan[i].weight; - g_log_chan[temp].current_desc = 0; - g_log_chan[temp].desc_ofst = DEFAULT_OFFSET; - g_log_chan[temp].desc_len = dma_dev->rx_chan[i].desc_num; - g_log_chan[temp].offset_from_base = temp * DEFAULT_OFFSET; - g_log_chan[temp].packet_size = dma_dev->rx_chan[i].packet_size; - - AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN + temp * AMAZON_DMA_CH_STEP) = dma_dev->rx_chan[i].desc_num; - // enable interrupt mask - if (temp == 4 || temp == 5) { - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x32; - } else { - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x36; - } - strcpy(g_log_chan[temp].device_name, dma_dev->device_name); - g_log_chan[temp].burst_len = dma_dev->rx_burst_len; - g_log_chan[temp].control = dma_dev->rx_chan[i].control; - - - /* specify the buffer allocation and free method */ - if (dma_dev->buffer_alloc) - g_log_chan[temp].buffer_alloc = dma_dev->buffer_alloc; - else - g_log_chan[temp].buffer_alloc = common_buffer_alloc; - - if (dma_dev->buffer_free) - g_log_chan[temp].buffer_free = dma_dev->buffer_free; - else - g_log_chan[temp].buffer_free = common_buffer_free; - - if (dma_dev->intr_handler) - g_log_chan[temp].intr_handler = dma_dev->intr_handler; - else - g_log_chan[temp].intr_handler = NULL; - - for (j = 0; j < g_log_chan[temp].desc_len; j++) { - rx_desc_p = (struct rx_desc *) (g_desc_list + g_log_chan[temp].offset_from_base + j); - rx_desc_p->status.word = 0; - rx_desc_p->status.field.data_length = g_log_chan[temp].packet_size; - buffer = (u8 *) g_log_chan[temp].buffer_alloc(g_log_chan[temp].packet_size, &byte_offset, &p); - rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buffer); - rx_desc_p->status.field.byte_offset = byte_offset; - /* fix me, should check if the addresss comply with the burst - lenght requirment */ - g_log_chan[temp].opt[j] = p; - rx_desc_p->status.field.OWN = DMA_OWN; - - } - /* open or close the channel */ - if (g_log_chan[temp].control) - open_channel(temp); - else - close_channel(temp); - } - - for (i = 0; i < dma_dev->num_tx_chan; i++) { - temp = dma_dev->logic_tx_chan_base + i; - g_log_chan[temp].dma_dev = dma_dev; - g_log_chan[temp].weight = dma_dev->tx_chan[i].weight; - g_log_chan[temp].default_weight = dma_dev->tx_chan[i].weight; - g_log_chan[temp].current_desc = 0; - g_log_chan[temp].desc_ofst = DEFAULT_OFFSET; - g_log_chan[temp].desc_len = dma_dev->tx_chan[i].desc_num; - g_log_chan[temp].offset_from_base = temp * DEFAULT_OFFSET; - g_log_chan[temp].packet_size = dma_dev->tx_chan[i].packet_size; - - AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN + temp * AMAZON_DMA_CH_STEP) = dma_dev->tx_chan[i].desc_num; - // enable interrupt mask -#ifdef NO_TX_INT - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x3e; -#else - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x36; -#endif - - strcpy(g_log_chan[temp].device_name, dma_dev->device_name); - g_log_chan[temp].burst_len = dma_dev->tx_burst_len; - g_log_chan[temp].control = dma_dev->tx_chan[i].control; - - if (dma_dev->buffer_alloc) - g_log_chan[temp].buffer_alloc = dma_dev->buffer_alloc; - else - g_log_chan[temp].buffer_alloc = common_buffer_alloc; - - if (dma_dev->buffer_free) - g_log_chan[temp].buffer_free = dma_dev->buffer_free; - else - g_log_chan[temp].buffer_free = common_buffer_free; - - if (dma_dev->intr_handler) - g_log_chan[temp].intr_handler = dma_dev->intr_handler; - else - g_log_chan[temp].intr_handler = NULL; - - for (j = 0; j < g_log_chan[temp].desc_len; j++) { - - tx_desc_p = - (struct tx_desc *) (g_desc_list + - g_log_chan[temp].offset_from_base + j); - tx_desc_p->status.word = 0; - tx_desc_p->status.field.data_length = - g_log_chan[temp].packet_size; - tx_desc_p->status.field.OWN = CPU_OWN; - - } - /* workaround DMA pitfall, we never turn on channel if we don't - have proper descriptors */ - if (!g_log_chan[temp].control) { - close_channel(temp); - } - - } - - return 0; -} - -int dma_device_register(struct dma_device_info *dma_dev) -{ - dev_list *temp_dev; - temp_dev = (dev_list *) kmalloc(sizeof(dev_list), GFP_KERNEL); - temp_dev->dev = dma_dev; - temp_dev->weight = dma_dev->weight; - insert_dev_list(temp_dev); - /* check whether this is a known device */ - if ((strcmp(dma_dev->device_name, "switch1") == 0) - || (strcmp(dma_dev->device_name, "TPE") == 0) - || (strcmp(dma_dev->device_name, "switch2") == 0) - || (strcmp(dma_dev->device_name, "DPlus") == 0)) { - register_dev(dma_dev); - } - - return 0; -} - - -int unregister_dev(struct dma_device_info *dma_dev) -{ - int i, j, temp; - u8 *buffer; - struct rx_desc *rx_desc_p; - - for (i = 0; i < dma_dev->num_rx_chan; i++) { - temp = dma_dev->logic_rx_chan_base + i; - close_channel(temp); - for (j = 0; j < g_log_chan[temp].desc_len; j++) { - rx_desc_p = - (struct rx_desc *) (g_desc_list + - g_log_chan[temp].offset_from_base + j); - buffer = (u8 *) __va(rx_desc_p->Data_Pointer); - g_log_chan[temp].buffer_free(buffer, g_log_chan[temp].opt[j]); - } - } - for (i = 0; i < dma_dev->num_tx_chan; i++) { - temp = dma_dev->logic_tx_chan_base + i; - close_channel(temp); - } - return 0; -} - -int dma_device_unregister(struct dma_device_info *dev) -{ - dev_list *temp_dev; - for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) { - if (strcmp(dev->device_name, temp_dev->dev->device_name) == 0) { - if ((strcmp(dev->device_name, "switch1") == 0) - || (strcmp(dev->device_name, "TPE") == 0) - || (strcmp(dev->device_name, "switch2") == 0) - || (strcmp(dev->device_name, "DPlus") == 0)) - unregister_dev(dev); - if (temp_dev == g_head_dev) { - g_head_dev = temp_dev->next; - kfree(temp_dev); - } else { - if (temp_dev == g_tail_dev) - g_tail_dev = temp_dev->prev; - if (temp_dev->prev) - temp_dev->prev->next = temp_dev->next; - if (temp_dev->next) - temp_dev->next->prev = temp_dev->prev; - kfree(temp_dev); - } - break; - } - - } - return 0; -} - -void dma_device_update_rx(struct dma_device_info *dma_dev) -{ - int i, temp; - for (i = 0; i < dma_dev->num_rx_chan; i++) { - temp = dma_dev->logic_rx_chan_base + i; - g_log_chan[temp].control = dma_dev->rx_chan[i].control; - - if (g_log_chan[temp].control) - open_channel(temp); - else - close_channel(temp); - } - -} - -void dma_device_update_tx(struct dma_device_info *dma_dev) -{ - int i, temp; - for (i = 0; i < dma_dev->num_tx_chan; i++) { - temp = dma_dev->logic_tx_chan_base + i; - g_log_chan[temp].control = dma_dev->tx_chan[i].control; - if (g_log_chan[temp].control) { - /* we turn on channel when send out the very first packet */ - // open_channel(temp); - } else - close_channel(temp); - } -} - -int dma_device_update(struct dma_device_info *dma_dev) -{ - dma_device_update_rx(dma_dev); - dma_device_update_tx(dma_dev); - return 0; -} - -static int dma_open(struct inode *inode, struct file *file) -{ - return 0; -} - -static int dma_release(struct inode *inode, struct file *file) -{ - /* release the resources */ - return 0; -} - -static int dma_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -{ - int value = 0; - int result = 0; - int chan_no = 0; - - switch (cmd) { - case 0: /* get register value */ - break; - case 1: /* return channel weight */ - chan_no = *((int *) arg); - *((int *) arg + 1) = g_log_chan[chan_no].default_weight; - break; - case 2: /* set channel weight */ - chan_no = *((int *) arg); - value = *((int *) arg + 1); - printk("new weight=%08x\n", value); - g_log_chan[chan_no].default_weight = value; - break; - default: - break; - } - return result; -} - - -static struct file_operations dma_fops = { - owner:THIS_MODULE, - open:dma_open, - release:dma_release, - ioctl:dma_ioctl, -}; - -static int dma_init(void) -{ - int result = 0; - int i; - printk("initialising dma core\n"); - result = register_chrdev(DMA_MAJOR, "dma-core", &dma_fops); - if (result) { - AMAZON_DMA_EMSG("cannot register device dma-core!\n"); - return result; - } - result = request_irq(AMAZON_DMA_INT, dma_interrupt, SA_INTERRUPT, "dma-core", (void *) &dma_interrupt); - if (result) { - AMAZON_DMA_EMSG("error, cannot get dma_irq!\n"); - free_irq(AMAZON_DMA_INT, (void *) &dma_interrupt); - return -EFAULT; - } - - g_desc_list = (u64 *) KSEG1ADDR(__get_free_page(GFP_DMA)); - - if (g_desc_list == NULL) { - AMAZON_DMA_EMSG("no memory for desriptor\n"); - return -ENOMEM; - } - memset(g_desc_list, 0, PAGE_SIZE); - AMAZON_DMA_REG32(AMAZON_DMA_Desc_BA) = (u32) CPHYSADDR((u32) g_desc_list); - g_amazon_dma_dir = proc_mkdir("amazon_dma", NULL); - create_proc_read_entry("dma_register", 0, g_amazon_dma_dir, dma_register_proc_read, NULL); - create_proc_read_entry("g_desc_list", 0, g_amazon_dma_dir, desc_list_proc_read, NULL); - create_proc_read_entry("channel_weight", 0, g_amazon_dma_dir, channel_weight_proc_read, NULL); - - dma_chip_init(); - for (i = 0; i < (RX_CHAN_NUM + 1); i++) { - rx_chan_list[i] = -1; - } - for (i = 0; i < (TX_CHAN_NUM + 1); i++) { - tx_chan_list[i] = -1; - } - - for (i = 0; i < CHAN_TOTAL_NUM; i++) { - comb_isr_mask[i] = 0x80000000 >> (i); - } - - g_log_chan[CHAN_TOTAL_NUM].weight = 0; - printk("initialising dma core ... done\n"); - - return 0; -} - -arch_initcall(dma_init); - - -void dma_cleanup(void) -{ - dev_list *temp_dev; - - unregister_chrdev(DMA_MAJOR, "dma-core"); - for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) { - kfree(temp_dev); - } - free_page(KSEG0ADDR((unsigned long) g_desc_list)); - remove_proc_entry("channel_weight", g_amazon_dma_dir); - remove_proc_entry("dma_list", g_amazon_dma_dir); - remove_proc_entry("dma_register", g_amazon_dma_dir); - remove_proc_entry("amazon_dma", NULL); - /* release the resources */ - free_irq(AMAZON_DMA_INT, (void *) &dma_interrupt); -} - -EXPORT_SYMBOL(dma_device_register); -EXPORT_SYMBOL(dma_device_unregister); -EXPORT_SYMBOL(dma_device_read); -EXPORT_SYMBOL(dma_device_write); -EXPORT_SYMBOL(dma_device_update); -EXPORT_SYMBOL(dma_device_update_rx); - -MODULE_LICENSE("GPL"); diff --git a/target/linux/amazon/files/arch/mips/amazon/dma-core.h b/target/linux/amazon/files/arch/mips/amazon/dma-core.h deleted file mode 100644 index cb3d456c95..0000000000 --- a/target/linux/amazon/files/arch/mips/amazon/dma-core.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef DMA_CORE_H -#define DMA_CORE_H - -#define AMAZON_DMA_REG32(reg_num) *((volatile u32*)(reg_num)) -#define AMAZON_DMA_CH_STEP 4 - -#define COMB_ISR_RX_MASK 0xfe000000 -#define COMB_ISR_TX_MASK 0x01f00000 - - -#define DMA_OWN 1 -#define CPU_OWN 0 -#define DMA_MAJOR 250 - -//Descriptors -#define DMA_DESC_OWN_CPU 0x0 -#define DMA_DESC_OWN_DMA 0x80000000 -#define DMA_DESC_CPT_SET 0x40000000 -#define DMA_DESC_SOP_SET 0x20000000 -#define DMA_DESC_EOP_SET 0x10000000 - -#define switch_rx_chan_base 0 -#define switch_tx_chan_base 7 -#define switch2_rx_chan_base 2 -#define switch2_tx_chan_base 8 -#define TPE_rx_chan_base 4 -#define TPE_tx_chan_base 9 -#define DPLus2FPI_rx_chan_base 6 -#define DPLus2FPI_tx_chan_base 11 - -#define RX_CHAN_NUM 7 -#define TX_CHAN_NUM 5 -#define CHAN_TOTAL_NUM (RX_CHAN_NUM+TX_CHAN_NUM) -#define DEFAULT_OFFSET 20 -#define DESCRIPTOR_SIZE 8 - -typedef struct dev_list{ - struct dma_device_info* dev; - int weight; - struct dev_list* prev; - struct dev_list* next; -}dev_list; - -typedef struct channel_info{ - char device_name[16]; - int occupied; - enum attr_t attr; - int current_desc; - int weight; - int default_weight; - int desc_num; - int burst_len; - int desc_len; - int desc_ofst; - int packet_size; - int offset_from_base; - int control; - void* opt[DEFAULT_OFFSET]; - u8* (*buffer_alloc)(int len,int* offset, void** opt); - int (*buffer_free)(u8* dataptr,void* opt); - int (*intr_handler)(struct dma_device_info* info,int status); - - struct dma_device_info* dma_dev; -}channel_info; - - - -#endif - diff --git a/target/linux/amazon/files/arch/mips/amazon/interrupt.c b/target/linux/amazon/files/arch/mips/amazon/interrupt.c deleted file mode 100644 index 5e34e0577b..0000000000 --- a/target/linux/amazon/files/arch/mips/amazon/interrupt.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Gary Jennejohn (C) 2003 - * Copyright (C) 2007 Felix Fietkau - * Copyright (C) 2007 John Crispin - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Routines for generic manipulation of the interrupts found on the - * AMAZON boards. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -static void amazon_disable_irq(unsigned int irq_nr) -{ - int i; - u32 amazon_ier = AMAZON_ICU_IM0_IER; - - if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0) - amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier); - else { - irq_nr -= INT_NUM_IRQ0; - for (i = 0; i <= 4; i++) - { - if (irq_nr <= 31) - amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier); - amazon_ier += 0x10; - irq_nr -= 32; - } - } -} - -static void amazon_mask_and_ack_irq(unsigned int irq_nr) -{ - int i; - u32 amazon_ier = AMAZON_ICU_IM0_IER; - u32 amazon_isr = AMAZON_ICU_IM0_ISR; - - if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0){ - amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier); - amazon_writel(AMAZON_DMA_H_MASK, amazon_isr); - } else { - irq_nr -= INT_NUM_IRQ0; - for (i = 0; i <= 4; i++) - { - if (irq_nr <= 31){ - amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier); - amazon_writel((1 << irq_nr ), amazon_isr); - } - amazon_ier += 0x10; - amazon_isr += 0x10; - irq_nr -= 32; - } - } -} - -static void amazon_enable_irq(unsigned int irq_nr) -{ - int i; - u32 amazon_ier = AMAZON_ICU_IM0_IER; - - if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0) - amazon_writel(amazon_readl(amazon_ier) | AMAZON_DMA_H_MASK, amazon_ier); - else { - irq_nr -= INT_NUM_IRQ0; - for (i = 0; i <= 4; i++) - { - if (irq_nr <= 31) - amazon_writel(amazon_readl(amazon_ier) | (1 << irq_nr ), amazon_ier); - amazon_ier += 0x10; - irq_nr -= 32; - } - } -} - -static unsigned int amazon_startup_irq(unsigned int irq) -{ - amazon_enable_irq(irq); - return 0; -} - -static void amazon_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { - amazon_enable_irq(irq); - } -} - -static struct hw_interrupt_type amazon_irq_type = { - "AMAZON", - .startup = amazon_startup_irq, - .enable = amazon_enable_irq, - .disable = amazon_disable_irq, - .unmask = amazon_enable_irq, - .ack = amazon_mask_and_ack_irq, - .mask = amazon_disable_irq, - .mask_ack = amazon_mask_and_ack_irq, - .end = amazon_end_irq -}; - -/* Cascaded interrupts from IM0-4 */ -static inline void amazon_hw_irqdispatch(u8 line) -{ - u32 irq; - - irq = (amazon_readl(AMAZON_ICU_IM_VEC) >> (line * 5)) & AMAZON_ICU_IM0_VEC_MASK; - if (line == 0 && irq <= 11 && irq >= 0) { - //DMA fixed to IM0_IRL0 - irq = 0; - } - do_IRQ(irq + INT_NUM_IRQ0 + (line * 32)); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - if (pending & CAUSEF_IP7){ - do_IRQ(MIPS_CPU_TIMER_IRQ); - goto out; - } else { - unsigned int i; - for (i = 0; i <= 4; i++) - { - if(pending & (CAUSEF_IP2 << i)){ - amazon_hw_irqdispatch(i); - goto out; - } - } - } - printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); -out: - return; -} - -static struct irqaction cascade = { - .handler = no_action, - .flags = SA_INTERRUPT, - .name = "cascade", -}; - -void __init arch_init_irq(void) -{ - int i; - - /* mask all interrupt sources */ - for(i = 0; i <= 4; i++){ - amazon_writel(0, AMAZON_ICU_IM0_IER + (i * 0x10)); - } - - mips_cpu_irq_init(); - - /* set up irq cascade */ - for (i = 2; i <= 6; i++) { - setup_irq(i, &cascade); - } - - for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - set_irq_chip(i, &amazon_irq_type); - } -} diff --git a/target/linux/amazon/files/arch/mips/amazon/pci.c b/target/linux/amazon/files/arch/mips/amazon/pci.c deleted file mode 100644 index ab305a983c..0000000000 --- a/target/linux/amazon/files/arch/mips/amazon/pci.c +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2007 Felix Fietkau - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -/* FIXME: convert nasty volatile register derefs to readl/writel calls */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define AMAZON_PCI_REG32( addr ) (*(volatile u32 *)(addr)) -#ifndef AMAZON_PCI_MEM_BASE -#define AMAZON_PCI_MEM_BASE 0xb2000000 -#endif -#define AMAZON_PCI_MEM_SIZE 0x00400000 -#define AMAZON_PCI_IO_BASE 0xb2400000 -#define AMAZON_PCI_IO_SIZE 0x00002000 - -#define AMAZON_PCI_CFG_BUSNUM_SHF 16 -#define AMAZON_PCI_CFG_DEVNUM_SHF 11 -#define AMAZON_PCI_CFG_FUNNUM_SHF 8 - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -static inline u32 amazon_r32(u32 addr) -{ - u32 *ptr = (u32 *) addr; - return __raw_readl(ptr); -} - -static inline void amazon_w32(u32 addr, u32 val) -{ - u32 *ptr = (u32 *) addr; - __raw_writel(val, ptr); -} - - -static struct resource pci_io_resource = { - .name = "io pci IO space", -#if 0 - .start = AMAZON_PCI_IO_BASE, - .end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1, -#endif - .start = 0, - .end = AMAZON_PCI_IO_SIZE - 1, - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = { - .name = "ext pci memory space", - .start = AMAZON_PCI_MEM_BASE, - .end = AMAZON_PCI_MEM_BASE + AMAZON_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - -static inline u32 amazon_pci_swap(u32 val) -{ -#ifdef CONFIG_AMAZON_PCI_HW_SWAP - return swab32(val); -#else - return val; -#endif -} - -static int amazon_pci_config_access(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data) -{ - unsigned long flags; - u32 pci_addr; - u32 val; - int ret; - - /* Amazon support slot from 0 to 15 */ - /* devfn 0 & 0x20 is itself */ - if ((bus != 0) || (devfn == 0) || (devfn == 0x20)) - return 1; - - pci_addr=AMAZON_PCI_CFG_BASE | - bus->number << AMAZON_PCI_CFG_BUSNUM_SHF | - devfn << AMAZON_PCI_CFG_FUNNUM_SHF | - (where & ~0x3); - - local_irq_save(flags); - if (access_type == PCI_ACCESS_WRITE) { - val = amazon_pci_swap(*data); - ret = put_dbe(val, (u32 *)pci_addr); - } else { - ret = get_dbe(val, (u32 *)pci_addr); - *data = amazon_pci_swap(val); - } - - amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<> ((where & 3) << 3)) & 0xff; - break; - case 2: - *((u16 *) val) = (data >> ((where & 3) << 3)) & 0xffff; - break; - case 4: - *val = data; - break; - default: - return -1; - } - - return ret; -} - - -static int amazon_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) -{ - if (size != 4) { - u32 data; - - if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - - if (size == 1) - val = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); - else if (size == 2) - val = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); - else - return -1; - } - - if (amazon_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops amazon_pci_ops = { - amazon_pci_read, - amazon_pci_write -}; - -static struct pci_controller amazon_pci_controller = { - .pci_ops = &amazon_pci_ops, - .mem_resource = &pci_mem_resource, - .io_resource = &pci_io_resource -}; - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - switch (slot) { - case 13: - /* IDSEL = AD29 --> USB Host Controller */ - return INT_NUM_IM2_IRL15; - case 14: - /* IDSEL = AD30 --> mini PCI connector */ - return INT_NUM_IM2_IRL14; - default: - printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin); - return 0; - } -} - -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - switch(dev->irq) { - case INT_NUM_IM2_IRL15: - /* - * IDSEL = AD29 --> USB Host Controller - * PCI_INTA/B/C--GPIO Port0.2--EXIN3 - * IN/ALT0:1 ALT1:0 - * PULL UP - */ - (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffb; - (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 4; - (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffb; - (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 4; - (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 4; - //External Interrupt Node - (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x6000; /* Low Level triggered */ - (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x8; - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - break; - case INT_NUM_IM2_IRL14: - /* - * IDSEL = AD30 --> mini PCI connector - * PCI_INTA--GPIO Port0.1--EXIN2 - * IN/ALT0:1 ALT1:0 - * PULL UP - */ - (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffd; - (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 2; - (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffd; - (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 2; - (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 2; - //External Interrupt Node - (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x600; - (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x4; - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - break; - default: - return 1; - } - return 0; -} - -int amazon_pci_init(void) -{ - u32 temp_buffer; - -#ifdef CONFIG_AMAZON_PCI_HW_SWAP - AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28); - wmb(); -#endif - - AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1< - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void prom_putchar(char c) -{ - /* Wait for FIFO to empty */ - while ((amazon_readl(AMAZON_ASC_FSTAT) >> 8) != 0x00) ; - /* Crude cr/nl handling is better than none */ - if(c == '\n') - amazon_writel('\r', AMAZON_ASC_TBUF); - amazon_writel(c, AMAZON_ASC_TBUF); -} - -void prom_printf(const char * fmt, ...) -{ - va_list args; - int l; - char *p, *buf_end; - char buf[1024]; - - va_start(args, fmt); - /* FIXME - hopefully i < sizeof(buf) */ - l = vsprintf(buf, fmt, args); - va_end(args); - buf_end = buf + l; - - for (p = buf; p < buf_end; p++) - prom_putchar(*p); -} - - -void __init prom_init(void) -{ - mips_machgroup = MACH_GROUP_INFINEON; - mips_machtype = MACH_INFINEON_AMAZON; - - strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit"); - - add_memory_region(0x00000000, 0x1000000, BOOT_MEM_RAM); -} - -void prom_free_prom_memory(void) -{ -} - -const char *get_system_type(void) -{ - return BOARD_SYSTEM_TYPE; -} diff --git a/target/linux/amazon/files/arch/mips/amazon/setup.c b/target/linux/amazon/files/arch/mips/amazon/setup.c deleted file mode 100644 index a96b565c69..0000000000 --- a/target/linux/amazon/files/arch/mips/amazon/setup.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (C) 2004 Peng Liu - * Copyright (C) 2007 John Crispin - * Copyright (C) 2007 Felix Fietkau - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void prom_printf(const char * fmt, ...); -static void amazon_reboot_setup(void); - -/* the CPU clock rate - lifted from u-boot */ -unsigned int amazon_get_cpu_hz(void) -{ - /*-----------------------------------*/ - /**CGU CPU Clock Reduction Register***/ - /*-----------------------------------*/ - switch(amazon_readl(AMAZON_CGU_CPUCRD) & 0x3){ - case 0: - /*divider ration 1/1, 235 MHz clock */ - return 235000000; - case 1: - /*divider ration 2/3, 235 MHz clock, clock not accurate, here */ - return 150000000; - case 2: - /*divider ration 1/2, 235 MHz clock */ - return 117500000; - default: - /*divider ration 1/4, 235 MHz clock */ - return 58750000; - } -} - -/* the FPI clock rate - lifted from u-boot */ -unsigned int amazon_get_fpi_hz(void) -{ - unsigned int clkCPU; - clkCPU = amazon_get_cpu_hz(); - - /*-------------------------------------*/ - /***CGU Clock Divider Select Register***/ - /*-------------------------------------*/ - switch (amazon_readl(AMAZON_CGU_DIV) & 0x3) - { - case 1: - return clkCPU >> 1; - case 2: - return clkCPU >> 2; - default: - return clkCPU; - /* '11' is reserved */ - } -} - -/* this doesn't really belong here, but it's a convenient location */ -unsigned int amazon_get_cpu_ver(void) -{ - static unsigned int cpu_ver = 0; - if (cpu_ver == 0) - cpu_ver = amazon_readl(AMAZON_MCD_CHIPID) & 0xFFFFF000; - return cpu_ver; -} - -void amazon_time_init(void) -{ - mips_hpt_frequency = amazon_get_cpu_hz()/2; - printk("mips_hpt_frequency:%d\n", mips_hpt_frequency); -} - -extern int hr_time_resolution; - -/* ISR GPTU Timer 6 for high resolution timer */ -static void amazon_timer6_interrupt(int irq, void *dev_id) -{ - timer_interrupt(AMAZON_TIMER6_INT, NULL); -} - -static struct irqaction hrt_irqaction = { - .handler = amazon_timer6_interrupt, - .flags = SA_INTERRUPT, - .name = "hrt", -}; - -/* - * THe CPU counter for System timer, set to HZ - * GPTU Timer 6 for high resolution timer, set to hr_time_resolution - * Also misuse this routine to print out the CPU type and clock. - */ -void __init plat_timer_setup(struct irqaction *irq) -{ - /* cpu counter for timer interrupts */ - setup_irq(MIPS_CPU_TIMER_IRQ, irq); - - /* enable the timer in the PMU */ - amazon_writel(amazon_readl(AMAZON_PMU_PWDCR)| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI, AMAZON_PMU_PWDCR); - - /* setup the GPTU for timer tick f_fpi == f_gptu*/ - amazon_writel(0x0100, AMAZON_GPTU_CLC); - amazon_writel(0xffff, AMAZON_GPTU_CAPREL); - amazon_writel(0x80C0, AMAZON_GPTU_T6CON); -} - -void __init plat_mem_setup(void) -{ - u32 chipid = 0; - u32 part_no = 0; - - chipid = amazon_readl(AMAZON_MCD_CHIPID); - part_no = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid); - - if(part_no == AMAZON_CHIPID_YANGTSE){ - prom_printf("Yangtse Version\n"); - } else if (part_no == AMAZON_CHIPID_STANDARD) { - prom_printf(SYSTEM_MODEL_NAME "\n"); - } else { - prom_printf("unknown version %8x\n",part_no); - } - - amazon_reboot_setup(); - board_time_init = amazon_time_init; - - //stop reset TPE and DFE - amazon_writel(0, AMAZON_RST_REQ); - //clock - amazon_writel(0x3fff, AMAZON_PMU_PWDCR); - //reenable trace capability - part_no = readl(AMAZON_BCU_ECON); -} - -static void amazon_machine_restart(char *command) -{ - local_irq_disable(); - amazon_writel(AMAZON_RST_ALL, AMAZON_RST_REQ); - for (;;) ; -} - -static void amazon_machine_halt(void) -{ - printk(KERN_NOTICE "System halted.\n"); - local_irq_disable(); - for (;;) ; -} - -static void amazon_machine_power_off(void) -{ - printk(KERN_NOTICE "Please turn off the power now.\n"); - local_irq_disable(); - for (;;) ; -} - -static void amazon_reboot_setup(void) -{ - _machine_restart = amazon_machine_restart; - _machine_halt = amazon_machine_halt; - pm_power_off = amazon_machine_power_off; -} diff --git a/target/linux/amazon/files/drivers/atm/amazon_tpe.c b/target/linux/amazon/files/drivers/atm/amazon_tpe.c deleted file mode 100644 index cf3e407329..0000000000 --- a/target/linux/amazon/files/drivers/atm/amazon_tpe.c +++ /dev/null @@ -1,3074 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - */ -//----------------------------------------------------------------------- -/* - * Description: - * Driver for Infineon Amazon TPE - */ -//----------------------------------------------------------------------- -/* Author: peng.liu@infineon.com - * Created: 12-April-2004 - */ -//----------------------------------------------------------------------- -/* History - * Last changed on: 13 Oct. 2004 - * Last changed by: peng.liu@infineon.com - * Last changed on: 28 Jan. 2004 - * Last changed by: peng.liu@infineon.com - * Last changed Reason: - * - AAL5R may send more bytes than expected in MFL (so far, confirmed as 64 bytes) - */ -// 507261:tc.chen 2005/07/26 re-organize code address map to improve performance. -// 507281:tc.chen 2005/07/28 fix f4 segment isssue -/* 511045:linmars 2005/11/04 from Liu.Peng: change NRT_VBR bandwidth calculation based on scr instead of pcr */ - -#ifndef __KERNEL__ -#define __KERNEL__ -#endif -#ifndef EXPORT_SYMTAB -#define EXPORT_SYMTAB -#endif - -/*TPE level loopback, bypass AWARE DFE */ -#undef TPE_LOOPBACK - -/* enable debug options */ -#undef AMAZON_ATM_DEBUG - -/* enable rx error packet analysis */ -#undef AMAZON_ATM_DEBUG_RX - -/* test AAL5 Interrupt */ -#undef AMAZON_TPE_TEST_AAL5_INT - -/* dump packet */ -#undef AMAZON_TPE_DUMP - -/* read ARC register*/ -/* this register is located in side DFE module*/ -#undef AMAZON_TPE_READ_ARC - -/* software controlled reassembly */ -#undef AMAZON_TPE_SCR - -/* recovery from AAL5 bug */ -#undef AMAZON_TPE_AAL5_RECOVERY - -#if defined(AMAZON_TPE_READ_ARC) || defined(AMAZON_TPE_AAL5_RECOVERY) -#define ALPHAEUS_BASE_ADDR 0x31c00 -#define A_CFG_ADDR (ALPHAEUS_BASE_ADDR+0x04) -#define AR_CB0_STATUS_ADDR (ALPHAEUS_BASE_ADDR+0x2c) -#define AR_CB1_STATUS_ADDR (ALPHAEUS_BASE_ADDR+0x30) -#define AT_CELL0_ADDR (ALPHAEUS_BASE_ADDR+0x90) -#define AR_CELL0_ADDR (ALPHAEUS_BASE_ADDR+0x1a0) -#define AR_CD_CNT0_ADDR (ALPHAEUS_BASE_ADDR+0x1c8) -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(AMAZON_TPE_READ_ARC) || defined(AMAZON_TPE_AAL5_RECOVERY) -#include -#include -#endif - -#define AMAZON_TPE_EMSG(fmt, args...) printk( KERN_ERR "%s: " fmt,__FUNCTION__, ## args) - -/***************************************** External Functions *******************************************/ -extern unsigned int amazon_get_fpi_hz(void); -extern void mask_and_ack_amazon_irq(unsigned int irq_nr); -extern void amz_push_oam(unsigned char *); - -//amazon_mei.c -#if defined(AMAZON_TPE_READ_ARC) || defined(AMAZON_TPE_AAL5_RECOVERY) -extern MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize); -extern MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize); -#endif - -/***************************************** Internal Functions *******************************************/ -int amazon_atm_read_procmem(char *buf, char **start, off_t offset,int count, int *eof, void *data); -/***************************************** Global Data *******************************************/ -amazon_atm_dev_t g_atm_dev; //device data -static struct tq_struct swex_start_task; //BH task -static struct tq_struct swex_complete_task; //BH task -#ifdef AMAZON_TPE_SCR -static struct tq_struct a5r_task; //BH task -#endif -static struct dma_device_info g_dma_dev; //for DMA -static struct atm_dev * amazon_atm_devs[AMAZON_ATM_PORT_NUM]; -static struct oam_last_activity g_oam_time_stamp[AMAZON_ATM_MAX_VCC_NUM]; -static u8 g_oam_cell[AMAZON_AAL0_SDU+4]; //for OAM cells -#ifdef AMAZON_CHECK_LINK -static int adsl_link_status; //ADSL link status, 0:down, 1:up -#endif //AMAZON_CHECK_LINK -/***************************************** Module Parameters *************************************/ -// Parameter Definition for module -static int port_enable0 = 1; // Variable for parameter port_enable0 -static int port_enable1 = 0; // Variable for parameter port_enable1 -static int port_max_conn0 = 15; // Variable for parameter port_max_conn0 -static int port_max_conn1 = 0; // Variable for parameter port_max_conn1 -static int port_cell_rate_up0 = 7500; // Variable for parameter port_cell_rate_up0 -static int port_cell_rate_up1 = 7500; // Variable for parameter port_cell_rate_up1 - - -static int qsb_tau = 1; // Variable for parameter qsb_tau -static int qsb_srvm = 0xf; // Variable for parameter qsb_srvm -static int qsb_tstep = 4 ; // Variable for parameter qsb_tstep - -static int cbm_nrt = 3900; // Variable for parameter cbm_nrt -static int cbm_clp0 =3500; // Variable for parameter cbm_clp0 -static int cbm_clp1 =3200; // Variable for parameter cbm_clp1 -static int cbm_free_cell_no = AMAZON_ATM_FREE_CELLS; // Variable for parameter cbm_free_cell_no - -static int a5_fill_pattern = 0x7e; // Variable for parameter a5_fill_pattern '~' -static int a5s_mtu = 0x700; // mtu for tx -static int a5r_mtu = 0x700; // mtu for rx - -static int oam_q_threshold = 64; // oam queue threshold, minium value 64 -static int rx_q_threshold = 1000; // rx queue threshold, minium value 64 -static int tx_q_threshold = 800; // tx queue threshold, minium value 64 - -MODULE_PARM(port_max_conn0, "i"); -MODULE_PARM_DESC(port_max_conn0, "Maximum atm connection for port #0"); -MODULE_PARM(port_max_conn1, "i"); -MODULE_PARM_DESC(port_max_conn1, "Maximum atm connection for port #1"); -MODULE_PARM(port_enable0, "i"); -MODULE_PARM_DESC(port_enable0, "0 -> port disabled, 1->port enabled"); -MODULE_PARM(port_enable1, "i"); -MODULE_PARM_DESC(port_enable1, "0 -> port disabled, 1->port enabled"); -MODULE_PARM(port_cell_rate_up0, "i"); -MODULE_PARM_DESC(port_cell_rate_up0, "ATM port upstream rate in cells/s"); -MODULE_PARM(port_cell_rate_up1, "i"); -MODULE_PARM_DESC(port_cell_rate_up1, "ATM port upstream rate in cells/s"); - -MODULE_PARM(qsb_tau,"i"); -MODULE_PARM_DESC(qsb_tau, "Cell delay variation. value must be > 0"); -MODULE_PARM(qsb_srvm, "i"); -MODULE_PARM_DESC(qsb_srvm, "Maximum burst size"); -MODULE_PARM(qsb_tstep, "i"); -MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4"); - -MODULE_PARM(cbm_nrt, "i"); -MODULE_PARM_DESC(cbm_nrt, "Non real time threshold for cell buffer"); -MODULE_PARM(cbm_clp0, "i"); -MODULE_PARM_DESC(cbm_clp0, "Threshold for cells with cell loss priority 0"); -MODULE_PARM(cbm_clp1, "i"); -MODULE_PARM_DESC(cbm_clp1, "Threshold for cells with cell loss priority 1"); -MODULE_PARM(cbm_free_cell_no, "i"); -MODULE_PARM_DESC(cbm_free_cell_no, "Number of cells in the cell buffer manager"); - -MODULE_PARM(a5_fill_pattern, "i"); -MODULE_PARM_DESC(a5_fill_pattern, "filling pattern (PAD) for aal5 frames"); -MODULE_PARM(a5s_mtu, "i"); -MODULE_PARM_DESC(a5s_mtu, "max. SDU for upstream"); -MODULE_PARM(a5r_mtu, "i"); -MODULE_PARM_DESC(a5r_mtu, "max. SDU for downstream"); - -MODULE_PARM(oam_q_threshold, "i"); -MODULE_PARM_DESC(oam_q_threshold, "oam queue threshold"); - -MODULE_PARM(rx_q_threshold, "i"); -MODULE_PARM_DESC(rx_q_threshold, "downstream/rx queue threshold"); - -MODULE_PARM(tx_q_threshold, "i"); -MODULE_PARM_DESC(tx_q_threshold, "upstream/tx queue threshold"); - -/***************************************** local functions *************************************/ -/* Brief: valid QID - * Return: 1 if valid - * 0 if not - */ -static inline int valid_qid(int qid) -{ - return ( (qid>0) && (qiddata)) & 15) != 0){ - AMAZON_TPE_DMSG("need to adjust the alignment manually\n"); - skb_reserve(skb, 16 - (((u32) (skb->data)) & 15) ); - } - -} - -/* - * Brief: initialize the device according to the module paramters - * Return: not NULL - ok - * NULL - fails - * Description: arrange load parameters and call the hardware initialization routines - */ -static void atm_init_parameters(amazon_atm_dev_t *dev) -{ - //port setting - dev->ports[0].enable = port_enable0; - dev->ports[0].max_conn = port_max_conn0; - dev->ports[0].tx_max_cr = port_cell_rate_up0; - if (port_enable1){ - dev->ports[1].enable = port_enable1; - dev->ports[1].max_conn = port_max_conn1; - dev->ports[1].tx_max_cr = port_cell_rate_up1; - } - - //aal5 - dev->aal5.padding_byte = a5_fill_pattern; - dev->aal5.tx_max_sdu = a5s_mtu; - dev->aal5.rx_max_sdu = a5r_mtu; - - //cbm - dev->cbm.nrt_thr = cbm_nrt; - dev->cbm.clp0_thr = cbm_clp0; - dev->cbm.clp1_thr = cbm_clp1; - dev->cbm.free_cell_cnt = cbm_free_cell_no; - - //qsb - dev->qsb.tau = qsb_tau; - dev->qsb.tstepc =qsb_tstep; - dev->qsb.sbl = qsb_srvm; - - //allocate on the fly - dev->cbm.mem_addr = NULL; - dev->cbm.qd_addr = NULL; -} - - -/* Brief: Find QID for VCC - * Parameters: vcc - VCC data structure - * Return Value: -EINVAL - VCC not found - * qid - QID for this VCC - * Description: - * This function returns the QID of a given VCC - */ -static int amazon_atm_get_queue(struct atm_vcc* vcc) -{ - int i; - for (i=0;ivpi == vpi) && (vcc->vci == vci)) return i; - } - } - return -EINVAL; -} - -/* Brief: Find QID for VPI - * Parameters: vpi - VPI to found - * Return Value: -EINVAL - VPI not found - * qid - QID for this VPI - * - * Description: - * This function returns the QID for a given VPI. itf and VCI don't matter - */ -static int amazon_atm_find_vpi(u8 vpi) -{ - int i; - for (i=0;ivpi == vpi) return i; - } - } - return -EINVAL; -} - -/* - * Brief: Clears QID entries for VCC - * - * Parameters: vcc - VCC to found - * - * Description: - * This function searches for the given VCC and sets it to NULL if found. - */ -static inline void amazon_atm_clear_vcc(int i) -{ - g_atm_dev.queues[i].vcc = NULL; - g_atm_dev.queues[i].free = 1; -} - - -/* - * Brief: dump skb data - */ -static inline void dump_skb(u32 len, char * data) -{ -#ifdef AMAZON_TPE_DUMP - int i; - for(i=0;ipop != NULL) { - vcc->pop(vcc, skb); - } else { - dev_kfree_skb_any(skb); - } -} -/* - * Brief: release TX skbuff - */ -static inline void amazon_atm_free_tx_skb(struct sk_buff *skb) -{ - struct atm_vcc* vcc = ATM_SKB(skb)->vcc; - if (vcc!=NULL){ - amazon_atm_free_tx_skb_vcc(vcc,skb); - } else { - dev_kfree_skb_any(skb);//fchang:Added - } -} - -/* Brief: divide by 64 and round up - */ -static inline u32 divide_by_64_round_up(int input) -{ - u32 tmp1; - tmp1 = (u32) input; - tmp1 = (tmp1%64)?(tmp1/64 + 1): (tmp1/64); - if (tmp1 == 0) tmp1 = 1; - return tmp1; -} - -/* - * Brief: statistics - */ -#ifdef AMAZON_ATM_DEBUG -static inline void queue_statics(int qid, qs_t idx) -{ - if (valid_qid(qid)){ - g_atm_dev.queues[qid].qs[idx]++; - } -} -#else //not AMAZON_ATM_DEBUG -static inline void queue_statics(int qid, qs_t idx){} -#endif //AMAZON_ATM_DEBUG - - -/* Brief: set dma tx full, i.e. there is no available descriptors - */ -static void inline atm_dma_full(void) -{ - AMAZON_TPE_DMSG("ch0 is full\n"); - atomic_set(&g_atm_dev.dma_tx_free_0,0); -} - -/* - * Brief set dma tx free (at least one descript is available) - */ -inline static void atm_dma_free(void) -{ - AMAZON_TPE_DMSG("ch0 is free\n"); - atomic_set(&g_atm_dev.dma_tx_free_0,1); -} - - -/* Brief: return the status of DMA TX descriptors - * Parameters: TX channel (DMA_TX_CH0, TX_CH1) - * Return: - * 1: there are availabel TX descriptors - * 0: no available - * Description: - * - */ -inline int dma_may_send(int ch) -{ - if (atomic_read(&g_atm_dev.dma_tx_free_0)){ - return 1; - } - return 0; -} - -/******************************* global functions *********************************/ -/* - * Brief: SWIE Cell Extraction Start Routine - * and task routine for swex_complete_task - * Parameters: irq_stat - interrupt status - * - * Description: - * This is the routine for extracting cell. It will schedule itself if the hardware is busy. - * This routine runs in interrupt context - */ -void amazon_atm_swex(void * irq_stat) -{ - u32 ex_stat=0; - u32 addr; - // Read extraction status register - ex_stat = readl(CBM_HWEXSTAT0_ADDR); - - // Check if extraction/insertion is in progress - if ( (ex_stat & CBM_EXSTAT_SCB) || (ex_stat & CBM_EXSTAT_FB) || (test_and_set_bit(SWIE_LOCK, &(g_atm_dev.swie.lock))!=0)) { - AMAZON_TPE_DMSG(" extraction in progress. Will wait\n"); - swex_start_task.data = irq_stat; - queue_task(&swex_start_task, &tq_immediate); - mark_bh(IMMEDIATE_BH); - }else { - // Extract QID - g_atm_dev.swie.qid = (((u32)irq_stat) >> 24); - AMAZON_TPE_DMSG("extracting from qid=%u\n",g_atm_dev.swie.qid); - //read status word - addr = KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr); - addr = readl((addr + g_atm_dev.swie.qid * 0x10 + 4) & 0xFFFFFFC0); - addr = KSEG1ADDR(addr); - g_atm_dev.swie.sw = readl(addr+52)&SWIE_ADDITION_DATA_MASK; - AMAZON_TPE_DMSG("cell addition word: %8x \n", g_atm_dev.swie.sw); - - // Start extraction - AMAZON_WRITE_REGISTER_L(g_atm_dev.swie.qid | SWIE_CBM_PID_SUBADDR, CBM_HWEXPAR0_ADDR); - AMAZON_WRITE_REGISTER_L(SWIE_CBM_SCE0, CBM_HWEXCMD_ADDR); - } -} -#ifdef AMAZON_TPE_SCR -u32 g_a5r_wait=0; -/* - * Brief: AAL5 Packet Extraction Routine and task routine for a5r_task - * Parameters: irq_stat - interrupt status - * - * Description: - * This is the routine for extracting frame. It will schedule itself if the hardware is busy. - * This routine runs in interrupt context - */ -void amazon_atm_a5r(void* qid) -{ - volatile u32 ex_stat=0; - u32 addr; - u32 a5r_wait=0; - - ex_stat = readl(CBM_HWEXSTAT0_ADDR); -#if 0 - // Check if extraction/insertion is in progress - if ( (ex_stat & CBM_EXSTAT_SCB) || (ex_stat & CBM_EXSTAT_FB) ) { - AMAZON_TPE_DMSG(" extraction in progress. Will wait\n"); - a5r_task.data = qid; - queue_task(&a5r_task, &tq_immediate); - mark_bh(IMMEDIATE_BH); - }else { - AMAZON_TPE_DMSG("extracting from qid=%u\n",(u8)qid); - // Start extraction - AMAZON_WRITE_REGISTER_L(((u8)qid) | CBM_HWEXPAR_PN_A5, CBM_HWEXPAR0_ADDR); - AMAZON_WRITE_REGISTER_L(CBM_HWEXCMD_FE0, CBM_HWEXCMD_ADDR); - } -#else - //while ( (ex_stat & CBM_EXSTAT_SCB) || (ex_stat & CBM_EXSTAT_FB) ) { - while ( ex_stat != 0x80){ - a5r_wait++; - ex_stat = readl(CBM_HWEXSTAT0_ADDR); -#if 0 - if (a5r_wait >= 0xffffff){ - a5r_wait=0; - printk("."); - } -#endif - } - if (a5r_wait > g_a5r_wait){ - g_a5r_wait = a5r_wait; - } - AMAZON_WRITE_REGISTER_L(((u8)qid) | CBM_HWEXPAR_PN_A5, CBM_HWEXPAR0_ADDR); - AMAZON_WRITE_REGISTER_L(CBM_HWEXCMD_FE0, CBM_HWEXCMD_ADDR); -#endif -} - -#endif //AMAZON_TPE_SCR - -/* Brief: Handle F4/F5 OAM cell - * Return: - * 0 ok - * <0 fails - */ -static int inline amazon_handle_oam_cell(void *data, u8 vpi, u16 vci,u32 status) -{ - struct atm_vcc* vcc=NULL; - int qid; - if (!status&SWIE_EOAM_MASK){ - AMAZON_TPE_EMSG("unknown cell received, discarded\n"); - goto amazon_handle_oam_cell_err_exit; - }else if (status&SWIE_ECRC10ERROR_MASK){ - AMAZON_TPE_EMSG("CRC-10 Error Status:%8x, discarded\n", status); - goto amazon_handle_oam_cell_err_exit; - }else{ - if(status & (SWIE_EVCI3_MASK |SWIE_EVCI4_MASK)){ - //F4 level (VPI) OAM, Assume duplex - qid = amazon_atm_find_vpi(vpi)+CBM_RX_OFFSET; - }else if (status & (SWIE_EPTI4_MASK|SWIE_EPTI5_MASK)){ - //F5 level (VCI) OAM, Assume duplex - qid = amazon_atm_find_vpivci(vpi,vci)+CBM_RX_OFFSET; - }else{ - qid = -1; - AMAZON_TPE_EMSG("non-F4/F5 OAM cells?, discarded\n"); - goto amazon_handle_oam_cell_err_exit; - } - } - if (valid_qid(qid) && ((vcc = g_atm_dev.queues[qid].vcc)!=NULL)){ - //TODO, should we do this for ALL OAM types? (Actually only User and CC) - g_atm_dev.queues[qid].access_time=xtime; - if (vcc->push_oam){ - (*vcc->push_oam)(vcc,data); - }else{ - amz_push_oam(data); - } - }else{ - AMAZON_TPE_EMSG("no VCC yet\n"); - goto amazon_handle_oam_cell_err_exit; - } - return 0; -amazon_handle_oam_cell_err_exit: - dump_skb(AMAZON_AAL0_SDU,(char *)data); - return -1; -} - -/* Brief: SWIE Cell Extraction Finish Routine - * and task routine for swex_complete_task - * Description: - * 1.Allocate a buffer of type struct sk_buff - * 2.Copy the data from the temporary memory to this buffer - * 3.Push the data to upper layer - * 4.Update the statistical data if necessary - * 5.Release the temporary data - - */ -void amazon_atm_swex_push(void * data) -{ - struct atm_vcc* vcc=NULL; - struct sk_buff* skb=NULL; - struct amazon_atm_cell_header * cell_header; - u32 status; - int qid; - if (!data){ - AMAZON_TPE_EMSG("data is NULL\n"); - return; - } - qid = ((u8*)data)[AMAZON_AAL0_SDU]; - status = ((u32*)data)[ATM_AAL0_SDU/4]; - cell_header = (struct amazon_atm_cell_header *) data; - if (valid_qid(qid) != 1){ - AMAZON_TPE_EMSG("error qid: %u\n",qid); - AMAZON_TPE_EMSG("unknown cells recieved\n"); - }else if (qid == AMAZON_ATM_OAM_Q_ID){ - //OAM or RM or OTHER cell - //Find real connection - -#ifdef IKOS_MINI_BOOT - //for OAM loop back test - dump_skb(56,(char *)data); - //kfree(data); using g_oam_cell - return; -#endif //IKOS_MINI_BOOT -#ifdef TPE_LOOPBACK - amz_push_oam(data); - return; -#endif//TPE_LOOPBACK - int ret = 0; - ret = amazon_handle_oam_cell(data,cell_header->bit.vpi,cell_header->bit.vci,status); - if (ret == 0) - return; - }else{ - //should be normal AAL0 cells - // Get VCC - vcc = g_atm_dev.queues[qid].vcc; - if (vcc != NULL) { - AMAZON_TPE_DMSG("push to upper layer\n"); - skb = dev_alloc_skb(AMAZON_AAL0_SDU); - if (skb != NULL) { - //skb->dev=vcc->dev; - memcpy(skb_put(skb, AMAZON_AAL0_SDU), data, AMAZON_AAL0_SDU); - skb->stamp = xtime; - ATM_SKB(skb)->vcc = vcc; - (*g_atm_dev.queues[qid].push)(vcc,skb,0); - }else{ - AMAZON_TPE_EMSG(" No memory left for incoming AAL0 cell! Cell discarded!\n"); - //inform the upper layer - (*g_atm_dev.queues[qid].push)(vcc,skb,-ENOMEM); - atomic_inc(&vcc->stats->rx_drop); - } - }else{ - AMAZON_TPE_EMSG("invalid qid %u\n",qid); - } - } - //kfree(data); using g_oam_cell -} - -/* - * Brief: Interrupt handler for software cell extraction (done) - * Parameters: irq - CPPN for this interrupt - * data - Device ID for this interrupt - * regs - Register file - * - * Description: - * When a software extraction is finished this interrupt is issued. - * It reads the cell data and sends it to the ATM stack. - */ -void amazon_atm_swex_isr(int irq, void *data, struct pt_regs *regs) -{ - u32 * cell = NULL; - int i; - //ATM_AAL0 SDU + QID - AMAZON_TPE_DMSG("SWIE extraction done\n"); - cell = (u32 *) g_oam_cell; - if (cell != NULL){ - //convert to host byte order from big endian - for(i=0;i>CBM_INTINF0_QID_SHIFT); -#ifdef AMAZON_TPE_SCR - if (irq_stat & CBM_INTINF0_EF){ - amazon_atm_a5r((void*)qid); - } -#endif - // Check if Any Cell Arrived - if (irq_stat & CBM_INTINF0_ACA) { - amazon_atm_swex((void *)irq_stat); - } - //TX AAL5 PDU discard - if (irq_stat & CBM_INTINF0_OPF){ - if ( (qid) < CBM_RX_OFFSET ){ - g_atm_dev.mib_counter.tx_drop++; - } - queue_statics(qid, QS_HW_DROP); - } - if (irq_stat & (CBM_INTINF0_ERR|CBM_INTINF0_Q0E|CBM_INTINF0_Q0I|CBM_INTINF0_RDE)){ - AMAZON_TPE_EMSG("CBM INT status: %8x\n",irq_stat); - if (irq_stat & CBM_INTINF0_ERR){ - AMAZON_TPE_EMSG("CBM Error: FPI Bus Error\n"); - } - if (irq_stat & CBM_INTINF0_Q0E){ - AMAZON_TPE_EMSG("CBM Error: Queue 0 Extract\n"); - } - if (irq_stat & CBM_INTINF0_Q0I){ - AMAZON_TPE_EMSG("CBM Error: Queue 0 Extract\n"); - } - if (irq_stat & CBM_INTINF0_RDE){ - AMAZON_TPE_EMSG("CBM Error: Read Empty Queue %u\n",qid); - dump_qd(qid); - } - } - } - mask_and_ack_amazon_irq(AMAZON_CBM_INT); -} - -/* Brief: check the status word after AAL SDU after reassembly - */ -static inline void check_aal5_error(u8 stw0, u8 stw1, int qid) -{ - if (stw0 & AAL5_STW0_MFL){ - AMAZON_TPE_DMSG("Maximum Frame Length\n"); - g_atm_dev.queues[qid].aal5VccOverSizedSDUs++; - } - if (stw0 & AAL5_STW0_CRC){ - AMAZON_TPE_DMSG("CRC\n"); - g_atm_dev.queues[qid].aal5VccCrcErrors++; - } -#ifdef AMAZON_ATM_DEBUG_RX - AMAZON_TPE_EMSG("qid:%u stw0:%8x stw1:%8x\n",qid,stw0,stw1); -#endif -} - -/* Brief: Process DMA rx data - * Parameters: - dma_dev: pointer to the dma_device_info, provided by us when register the dma device - * Return: no - * Description: DMA interrupt handerl with OoS support. It is called when there is some data in rx direction. - * - */ -//507261:tc.chen void atm_process_dma_rx(struct dma_device_info* dma_dev) -void __system atm_process_dma_rx(struct dma_device_info* dma_dev) -{ - u8 * head=NULL; - u32 length=0; - u8 stw0=0; - u8 stw1=0; - - struct sk_buff * skb=NULL; - struct atm_vcc * vcc=NULL; - int qid=0; -#ifdef AMAZON_ATM_DEBUG_RX - static int dma_rx_dump=0; - static u32 seq=0; - - seq++; - if (dma_rx_dump>0){ - printk("\n=========================[%u]=========================\n",seq); - } -#endif - length=dma_device_read(dma_dev,&head,(void**)&skb); - AMAZON_TPE_DMSG("receive %8p[%u] from DMA\n", head,length); - if (head == NULL||length<=0) { - AMAZON_TPE_DMSG("dma_read null \n"); - goto error_exit; - } - - if (length > (g_atm_dev.aal5.rx_max_sdu+64)){ - AMAZON_TPE_EMSG("received packet too large (%u)\n",length); - goto error_exit; - } - //check AAL5R trail for error and qid - //last byte is qid - length--; - qid = (int) head[length]; - AMAZON_TPE_DMSG("head[%u] qid %u\n",length, qid); - //STW0 is always 4 bytes before qid - length -= 4; - stw0 = head[length]&0xff; - AMAZON_TPE_DMSG("head[%u] stw0 %8x\n",length, stw0); - //position of STW1 depends on the BE bits - length = length-4 + (stw0&AAL5_STW0_BE); - stw1 = head[length]&0xff; - AMAZON_TPE_DMSG("head[%u] stw1 %8x\n",length, stw1); - if ( (stw0 & AAL5_STW0_MASK) || (stw1 & AAL5_STW1_MASK) ){ - //AAL5 Error - check_aal5_error(stw0, stw1,qid); - goto error_exit; - } - //make data pointers consistent - //UU + CPI - length -= 2; - AMAZON_TPE_DMSG("packet length %u\n", length); - - //error: cannot restore the qid - if (valid_qid(qid) != 1){ - AMAZON_TPE_EMSG("received frame in invalid qid %u!\n", qid); - goto error_exit; - } - vcc = g_atm_dev.queues[qid].vcc; - if (vcc == NULL){ - AMAZON_TPE_EMSG("received frame in invalid vcc, qid=%u!\n",qid); - goto error_exit; - } - if (skb == NULL){ - AMAZON_TPE_EMSG("cannot restore skb pointer!\n"); - goto error_exit; - } - skb_put(skb,length); - skb->stamp = xtime; - g_atm_dev.queues[qid].access_time=xtime; - if ((*g_atm_dev.queues[qid].push)(vcc,skb,0)){ - g_atm_dev.mib_counter.rx_drop++; - queue_statics(qid, QS_SW_DROP); - }else{ - g_atm_dev.mib_counter.rx++; - adsl_led_flash();//joelin adsl led - queue_statics(qid, QS_PKT); - AMAZON_TPE_DMSG("push successful!\n"); - } -#ifdef AMAZON_ATM_DEBUG_RX - if (dma_rx_dump>0){ - printk("\nOK packet [dump=%u] length=%u\n",dma_rx_dump,length); - dump_skb(length+7, head); - } - if (dma_rx_dump >0) dma_rx_dump--; -#endif - return ; -error_exit: -#ifdef AMAZON_ATM_DEBUG_RX - if ( (head!=NULL) && (length >0)){ - AMAZON_TPE_EMSG("length=%u\n",length); - dump_skb(length+5, head); - } - dma_rx_dump++; -#endif - g_atm_dev.mib_counter.rx_err++; - queue_statics(qid, QS_ERR); - /* - if (vcc){ - (*g_atm_dev.queues[qid].push)(vcc,skb,1); - } - */ - if (skb != NULL) { - dev_kfree_skb_any(skb); - } - return; -} - -/*Brief: ISR for DMA pseudo interrupt - *Parameter: - dma_dev: pointer to the dma_device_info, provided by us when register the dma device - intr_status: - RCV_INT: rx data available - TX_BUF_FULL_INT: tx descriptor run out of - TRANSMIT_CPT_INT: tx descriptor available again - *Return: - 0 for success??? - */ -//507261:tc.chen int amazon_atm_dma_handler(struct dma_device_info* dma_dev, int intr_status) -int __system amazon_atm_dma_handler(struct dma_device_info* dma_dev, int intr_status) -{ - AMAZON_TPE_DMSG("status:%u\n",intr_status); - switch (intr_status) { - case RCV_INT: - atm_process_dma_rx(dma_dev); - break; - case TX_BUF_FULL_INT: - //TX full: no descriptors - atm_dma_full(); - break; - case TRANSMIT_CPT_INT: - //TX free: at least one descriptor - atm_dma_free(); - break; - default: - AMAZON_TPE_EMSG("unknown status!\n"); - } - return 0; -} - -/*Brief: free buffer for DMA tx - *Parameter: - dataptr: pointers to data buffer - opt: optional parameter, used to convey struct skb pointer, passwd in dma_device_write - *Return: - 0 for success??? - *Description: - called by DMA module to release data buffer after DMA tx transaction - *Error: - cannot restore skb pointer - */ -int amazon_atm_free_tx(u8*dataptr, void* opt) -{ - struct sk_buff *skb; - if (opt){ - AMAZON_TPE_DMSG("free skb%8p\n",opt); - skb = (struct sk_buff *)opt; - amazon_atm_free_tx_skb(skb); - }else{ - AMAZON_TPE_EMSG("BUG: cannot restore skb pointer!\n"); - } - return 0; -} - -/*Brief: allocate buffer & do alignment - */ -inline struct sk_buff * amazon_atm_alloc_buffer(int len) -{ - struct sk_buff *skb; - skb = dev_alloc_skb(len+16); - if (skb){ - //alignment requriements (4x32 bits (16 bytes) boundary) - alloc_align_16(skb); - } - return skb; -} - -/*Brief: allocate buffer for DMA rx - *Parameter: - len: length - opt: optional data to convey the skb pointer, which will be returned to me in interrupt handler, - *Return: - pointer to buffer, NULL means error? - *Description: - must make sure byte alignment - */ - -u8* amazon_atm_alloc_rx(int len, int* offset, void **opt) -{ - struct sk_buff *skb; - *offset = 0; - skb = amazon_atm_alloc_buffer(len); - if (skb){ - AMAZON_TPE_DMSG("alloc skb->data:%8p len:%u\n",skb->data,len); - *(struct sk_buff**)opt = skb; - }else{ - AMAZON_TPE_DMSG("no memory for receiving atm frame!\n"); - return NULL; - } - return skb->data; -} - - - - -/* Brief: Allocate kernel memory for sending a datagram. - * Parameters - * vcc virtual connection - * size data buffer size - * Return: - * NULL fail - * sk_buff a pointer to a sk_buff - * Description: - * This function can allocate our own additional memory for AAL5S inbound - * header (8bytes). We have to replace the protocol default one (alloc_tx in /net/atm/common.c) - * when we open the device. - * byte alignment is done is DMA driver. - */ -struct sk_buff *amazon_atm_alloc_tx(struct atm_vcc *vcc,unsigned int size) -{ - struct sk_buff *skb; - - if (!dma_may_send(DMA_TX_CH0)){ - AMAZON_TPE_EMSG("no DMA descriptor available!\n"); - return NULL; - } - //AAL5 inbound header space + alignment extra buffer - size+=8+AAL5S_INBOUND_HEADER; - - if (atomic_read(&vcc->tx_inuse) && !atm_may_send(vcc,size)) { - AMAZON_TPE_EMSG("Sorry tx_inuse = %u, size = %u, sndbuf = %u\n", - atomic_read(&vcc->tx_inuse),size,vcc->sk->sndbuf); - return NULL; - } - - skb = amazon_atm_alloc_buffer(size); - if (skb == NULL){ - AMAZON_TPE_EMSG("no memory\n"); - return NULL; - } - AMAZON_TPE_DMSG("dev_alloc_skb(%u) = %x\n", skb->len, (u32)skb); - AMAZON_TPE_DMSG("tx_inuse %u += %u\n",atomic_read(&vcc->tx_inuse),skb->truesize); - atomic_add(skb->truesize+ATM_PDU_OVHD,&vcc->tx_inuse); - - //reserve for AAL5 inbound header - skb_reserve(skb,AAL5S_INBOUND_HEADER); - return skb; -} - - -/* Brief: change per queue QSB setting according to vcc qos parameters - * Paramters: - * vcc: atm_vcc pointer - * qid: CBM queue id (1~15) - * Return: - */ -static inline void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, int qid) -{ - qsb_qptl_t qptl; - qsb_qvpt_t qvpt; - u32 tmp=0; - unsigned int qsb_clk; - - qsb_clk = amazon_get_fpi_hz()>>1; - - AMAZON_TPE_EMSG("Class=%u MAX_PCR=%u PCR=%u MIN_PCR=%u SCR=%u MBS=%u CDV=%u\n" - ,qos->txtp.traffic_class - ,qos->txtp.max_pcr - ,qos->txtp.pcr - ,qos->txtp.min_pcr - ,qos->txtp.scr - ,qos->txtp.mbs - ,qos->txtp.cdv - ); - - // PCR limiter - if (qos->txtp.max_pcr == 0){ - qptl.bit.tprs = 0; /* 0 disables the PCR limiter */ - }else { - // peak cell rate will be slightly lower than requested (maximum rate / pcr)= (qsbclock/2^3 * timestep/4)/pcr - tmp = (( (qsb_clk * g_atm_dev.qsb.tstepc)>>5)/ qos->txtp.max_pcr ) + 1; - // check if an overfow occured - if (tmp > QSB_TP_TS_MAX) { - AMAZON_TPE_EMSG("max_pcr is too small, max_pcr:%u tprs:%u\n",qos->txtp.max_pcr, tmp); - qptl.bit.tprs = QSB_TP_TS_MAX; - }else{ - qptl.bit.tprs = tmp; - } - } - //WFQ - if (qos->txtp.traffic_class == ATM_CBR || qos->txtp.traffic_class ==ATM_VBR_RT){ - // real time queue gets weighted fair queueing bypass - qptl.bit.twfq = 0; - }else if (qos->txtp.traffic_class ==ATM_VBR_NRT ||qos->txtp.traffic_class ==ATM_UBR_PLUS ){ - // wfq calculation here are based on virtual cell rates, to reduce granularity for large rates - // wfq factor is maximum cell rate / garenteed cell rate. - //qptl.bit.twfq = g_atm_dev.qsb.min_cr * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr; - if (qos->txtp.min_pcr == 0) { - AMAZON_TPE_EMSG(" MIN_PCR should not be zero\n"); - qptl.bit.twfq = QSB_WFQ_NONUBR_MAX; - }else{ - tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr; - if (tmp == 0 ){ - qptl.bit.twfq = 1; - }else if (tmp > QSB_WFQ_NONUBR_MAX){ - AMAZON_TPE_EMSG("min_pcr is too small, min_pcr:%u twfq:%u\n",qos->txtp.min_pcr, tmp); - qptl.bit.twfq = QSB_WFQ_NONUBR_MAX; - }else{ - qptl.bit.twfq = tmp; - } - } - }else if (qos->txtp.traffic_class == ATM_UBR){ - // ubr bypass, twfq set to maximum value - qptl.bit.twfq = QSB_WFQ_UBR_BYPASS; - }else{ - //tx is diabled, treated as UBR - AMAZON_TPE_EMSG(" unsupported traffic class %u \n", qos->txtp.traffic_class); - qos->txtp.traffic_class = ATM_UBR; - qptl.bit.twfq = QSB_WFQ_UBR_BYPASS; - } - - //SCR Leaky Bucket Shaper VBR.0/VBR.1 - if (qos->txtp.traffic_class ==ATM_VBR_RT || qos->txtp.traffic_class ==ATM_VBR_NRT){ - if (qos->txtp.scr == 0){ - //SCR == 0 disable the shaper - qvpt.bit.ts = 0; - qvpt.bit.taus = 0; - }else{ - //CLP - if (vcc->atm_options&ATM_ATMOPT_CLP){ - //CLP1 - qptl.bit.vbr = 1; - }else{ - //CLP0 - qptl.bit.vbr = 0; - } - //TS and TauS - tmp = (( (qsb_clk * g_atm_dev.qsb.tstepc)>>5)/ qos->txtp.scr ) + 1; - if (tmp > QSB_TP_TS_MAX) { - AMAZON_TPE_EMSG("scr is too small, scr:%u ts:%u\n",qos->txtp.scr, tmp); - qvpt.bit.ts = QSB_TP_TS_MAX; - }else{ - qvpt.bit.ts = tmp; - } - tmp = (qos->txtp.mbs - 1)*(qvpt.bit.ts - qptl.bit.tprs)/64; - if (tmp > QSB_TAUS_MAX){ - AMAZON_TPE_EMSG("mbs is too large, mbr:%u taus:%u\n",qos->txtp.mbs, tmp); - qvpt.bit.taus = QSB_TAUS_MAX; - }else if (tmp == 0){ - qvpt.bit.taus = 1; - }else{ - qvpt.bit.taus = tmp; - } - } - }else{ - qvpt.w0 = 0; - } - //write the QSB Queue Parameter Table (QPT) - AMAZON_WRITE_REGISTER_L(QSB_QPT_SET_MASK,QSB_RTM_ADDR); - AMAZON_WRITE_REGISTER_L(qptl.w0, QSB_RTD_ADDR); - AMAZON_WRITE_REGISTER_L((QSB_TABLESEL_QPT<itf; - u32 dma_qos=0; - u8 * qd_addr=NULL; - - tx_config|=CBM_QD_W3_WM_EN|CBM_QD_W3_CLPt; - //RT: check if the connection is a real time connection - if (vcc->qos.txtp.traffic_class == ATM_CBR || vcc->qos.txtp.traffic_class == ATM_VBR_RT){ - tx_config|= CBM_QD_W3_RT; - }else{ - tx_config|= CBM_QD_W3_AAL5; //don't set the AAL5 flag if it is a RT service - } - rx_config = tx_config; - - if(vcc->qos.aal == ATM_AAL5){ - //QoS: DMA QoS according to the traffic class - switch (vcc->qos.txtp.traffic_class){ - case ATM_CBR: dma_qos = CBR_DMA_QOS;break; - case ATM_VBR_RT: dma_qos = VBR_RT_DMA_QOS;break; - case ATM_VBR_NRT: dma_qos = VBR_NRT_DMA_QOS;break; - case ATM_UBR_PLUS: dma_qos = UBR_PLUS_DMA_QOS;break; - case ATM_UBR: dma_qos = UBR_DMA_QOS;break; - } - - //TX: upstream, AAL5(EPD or PPD), NOINT, SBid - tx_config |= CBM_QD_W3_DIR_UP|CBM_QD_W3_INT_NOINT|(itf&CBM_QD_W3_SBID_MASK); - //RX: DMA QoS, downstream, no interrupt, AAL5(EPD, PPD), NO INT, HCR -#ifdef AMAZON_TPE_SCR - rx_config |= dma_qos|CBM_QD_W3_DIR_DOWN|CBM_QD_W3_INT_EOF; -#else - rx_config |= dma_qos|CBM_QD_W3_DIR_DOWN|CBM_QD_W3_INT_NOINT|CBM_QD_W3_HCR; -#endif - }else { - //should be AAL0 - //upstream, NOINT, SBid - tx_config |= CBM_QD_W3_DIR_UP|CBM_QD_W3_INT_NOINT|(itf&CBM_QD_W3_SBID_MASK); - //RX: downstream, ACA interrupt, - rx_config |= CBM_QD_W3_DIR_DOWN|CBM_QD_W3_INT_ACA; - } - - //Threshold: maximum threshold for tx/rx queue, which is adjustable in steps of 64 cells - tx_config |= ( (divide_by_64_round_up(tx_q_threshold)&0xffff)< 1024) - { - AMAZON_TPE_EMSG("timeout\n"); - return -EIO; - } - // write address register, - AMAZON_WRITE_REGISTER_L(idx, HTU_RAMADDR_ADDR); - // configure transmit queue - tmp1 = vpi<<24|vci<<8; - tmp1|= HTU_RAMDAT1_VCON // valid connection the entry is not validated here !!!!!!!!!!!!!!!! - |HTU_RAMDAT1_VCI3 // vci3 -> oam queue - |HTU_RAMDAT1_VCI4 // vci4 -> oam queue - |HTU_RAMDAT1_VCI6 // vci6 -> rm queue - |HTU_RAMDAT1_PTI4 // pti4 -> oam queue - |HTU_RAMDAT1_PTI5; // pti5 -> oam queue - - // ramdat 1 (in params & oam handling) - AMAZON_WRITE_REGISTER_L( tmp1, HTU_RAMDAT1_ADDR); - // ramdat 2 (out params & oam handling) - tmp1 = ((qid+CBM_RX_OFFSET)&HTU_RAMDAT2_QID_MASK) - |HTU_RAMDAT2_PTI6 - |HTU_RAMDAT2_PTI7 - |HTU_RAMDAT2_F4U - |HTU_RAMDAT2_F5U - ; - AMAZON_WRITE_REGISTER_L( tmp1, HTU_RAMDAT2_ADDR); - wmb(); - // write HTU entry - AMAZON_WRITE_REGISTER_L(HTU_RAMCMD_WR, HTU_RAMCMD_ADDR); - return 0; -} -/* - * Brief: add HTU table entry - * Parameter: - * vcc: atm_vcc pointer - * qid: CBM queue id - * Return: - * 0: sucessful - * EIO: HTU table entry cannot be written - */ -inline static int set_htu(struct atm_vcc *vcc, u32 qid) -{ - return set_htu_entry(vcc->vpi, vcc->vci, qid, (qid - CBM_DEFAULT_Q_OFFSET)); -} - -/* - * Brief: allocate a queue - * Return: - * <=0 no available queues - * >0 qid - */ -static int atm_allocate_q(short itf) -{ - int i; - u32 tmp1=0; - int qid=0; - amazon_atm_port_t * dev; - dev = &g_atm_dev.ports[itf]; - //find start queue id for this interface - for (i=0; i< itf; i++) - { - qid+= g_atm_dev.ports[i].max_conn; - } - // apply default queue offset ( oam, free cell queue, others, rm ) - qid += CBM_DEFAULT_Q_OFFSET; - tmp1 = qid; - // search for a free queue - while ( (qidmax_conn) - && ( g_atm_dev.queues[qid].free != 1)) { - qid++;; - } - // if none was found, send failure message and return - if ( tmp1+dev->max_conn == qid) - { - return -EFAULT; - } - return qid; - -} -/* Brief: open a aal5 or aal0 connection - */ -static int atm_open(struct atm_vcc *vcc, push_back_t push) -{ - int err=0; - int qid=0; - amazon_atm_port_t * port = & g_atm_dev.ports[vcc->itf]; - unsigned long flags; - /***************** check bandwidth ******************/ - /* 511045:linmars change ATM_VBR_NRT to use scr instead of pcr */ - if ((vcc->qos.txtp.traffic_class==ATM_CBR&&vcc->qos.txtp.max_pcr>port->tx_rem_cr) - ||(vcc->qos.txtp.traffic_class==ATM_VBR_RT&&vcc->qos.txtp.max_pcr>port->tx_rem_cr) - ||(vcc->qos.txtp.traffic_class==ATM_VBR_NRT&&vcc->qos.txtp.scr>port->tx_rem_cr) - ||(vcc->qos.txtp.traffic_class==ATM_UBR_PLUS&&vcc->qos.txtp.min_pcr>port->tx_rem_cr) - ) { - AMAZON_TPE_EMSG("not enough bandwidth left (%u) cells per seconds \n",port->tx_rem_cr); - return -EINVAL; - } - if ( (qid = amazon_atm_find_vpivci(vcc->vpi, vcc->vci)) >0 ){ - AMAZON_TPE_EMSG("vpi:%u vci:%u is alreay open on queue:%u\n", vcc->vpi, vcc->vci, qid); - return -EADDRINUSE; - } - - /***************** allocate entry queueID for this port *****************/ - if ( (qid=atm_allocate_q(vcc->itf)) <= 0){ - AMAZON_TPE_EMSG("port: %u max:%u qid: %u\n", vcc->itf, port->max_conn, qid); - AMAZON_TPE_EMSG("no availabel connections for this port:%u\n",vcc->itf); - return -EINVAL; - } - /**************QSB parameters and CBM descriptors*************/ - set_qsb(vcc, &vcc->qos, qid); - set_qd(vcc, qid); - mb(); - err=set_htu(vcc,qid); - if (err){ - AMAZON_TPE_EMSG("set htu entry fails %u\n",err); - return err; - } - /************set internal mapping*************/ - local_irq_save(flags); - g_atm_dev.queues[qid].free = 0; - g_atm_dev.queues[qid].vcc = vcc; - g_atm_dev.queues[qid].push = push; - g_atm_dev.queues[qid+CBM_RX_OFFSET].free = 0; - g_atm_dev.queues[qid+CBM_RX_OFFSET].vcc = vcc; - g_atm_dev.queues[qid+CBM_RX_OFFSET].push = push; - /******************reserve bandwidth**********************/ - if (vcc->qos.txtp.traffic_class == ATM_CBR){ - //CBR, real time connection, reserve PCR - port->tx_cur_cr += vcc->qos.txtp.max_pcr; - port->tx_rem_cr -= vcc->qos.txtp.max_pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_VBR_RT){ - //VBR_RT, real time connection, reserve PCR - port->tx_cur_cr += vcc->qos.txtp.max_pcr; - port->tx_rem_cr -= vcc->qos.txtp.max_pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_VBR_NRT){ - //VBR_NRT, reserve SCR - port->tx_cur_cr += vcc->qos.txtp.pcr; - port->tx_rem_cr -= vcc->qos.txtp.pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS){ - //UBR_PLUS, reserve MCR - port->tx_cur_cr += vcc->qos.txtp.min_pcr; - port->tx_rem_cr -= vcc->qos.txtp.min_pcr; - } - local_irq_restore(flags); - return err; -} -/* Brief: Open ATM connection - * Parameters: atm_vcc - Pointer to VCC data structure - * vpi - VPI value for new connection - * vci - VCI value for new connection - * - * Return: 0 - sucessful - * -ENOMEM - No memory available - * -EINVAL - No bandwidth/queue/ or unsupported AAL type - * Description: - * This function opens an ATM connection on a specific device/interface - * - */ -int amazon_atm_open(struct atm_vcc *vcc,push_back_t push) -{ - int err=0; - - AMAZON_TPE_DMSG("vpi %u vci %u itf %u aal %u\n" - ,vcc->vpi - ,vcc->vci - ,vcc->itf - ,vcc->qos.aal - ); - - AMAZON_TPE_DMSG("tx cl %u bw %u mtu %u\n" - ,vcc->qos.txtp.traffic_class - ,vcc->qos.txtp.max_pcr - ,vcc->qos.txtp.max_sdu - ); - AMAZON_TPE_DMSG("rx cl %u bw %u mtu %u\n" - ,vcc->qos.rxtp.traffic_class - ,vcc->qos.rxtp.max_pcr - ,vcc->qos.rxtp.max_sdu - ); - if (vcc->qos.aal == ATM_AAL5 || vcc->qos.aal == ATM_AAL0){ - err = atm_open(vcc,push); - }else{ - AMAZON_TPE_EMSG("unsupported aal type %u\n", vcc->qos.aal); - err = -EPROTONOSUPPORT; - }; - if (err == 0 ){ - //replace the default memory allocation function with our own - vcc->alloc_tx = amazon_atm_alloc_tx; - set_bit(ATM_VF_READY,&vcc->flags); - } - return err; -} - -/* Brief: Send ATM OAM cell - * Parameters: atm_vcc - Pointer to VCC data structure - * skb - Pointer to sk_buff structure, that contains the data - * Return: 0 - sucessful - * -ENOMEM - No memory available - * -EINVAL - Not supported - * Description: - * This function sends a cell over and ATM connection - * We always release the skb - * TODO: flags handling (ATM_OF_IMMED, ATM_OF_INRATE) - */ -int amazon_atm_send_oam(struct atm_vcc *vcc, void * cell, int flags) -{ - int err=0; - int qid=0; - struct amazon_atm_cell_header * cell_header; - // Get cell header - cell_header = (struct amazon_atm_cell_header*) cell; - if ((cell_header->bit.pti == ATM_PTI_SEGF5) || (cell_header->bit.pti == ATM_PTI_E2EF5)) { - qid = amazon_atm_find_vpivci( cell_header->bit.vpi, cell_header->bit.vci); - }else if (cell_header->bit.vci == 0x3 || cell_header->bit.vci == 0x4) { - //507281:tc.chen qid = amazon_atm_find_vpi((int) cell_header->bit.vpi); - // 507281:tc.chen start - u8 f4_vpi; - f4_vpi = cell_header->bit.vpi; - qid = amazon_atm_find_vpi(f4_vpi ); - // 507281:tc.chen end - }else{ - //non-OAM cells, always invalid - qid = -EINVAL; - } - if (qid == -EINVAL) { - err = -EINVAL; - AMAZON_TPE_EMSG("not valid AAL0 packet\n"); - }else{ - //send the cell using swie -#ifdef TPE_LOOPBACK - err = amazon_atm_swin(AMAZON_ATM_OAM_Q_ID, cell); -#else - err = amazon_atm_swin(qid, cell); -#endif - } - //kfree(cell); - return err; -} - -/* Brief: Send AAL5 frame through DMA - * Parameters: vpi - virtual path id - * vci - virtual circuit id - * clp - cell loss priority - * qid - CBM queue to be sent to - * skb - packet to be sent - * Return: 0 - sucessful - * -ENOMEM - No memory available - * -EINVAL - Not supported - * Description: - * This function sends a AAL5 frame over and ATM connection - * 1. make sure that the data is aligned to 4x32-bit boundary - * 2. provide the inbound data (CPCS-UU and CPI, not used here) - * 3. set CLPn - * 4. send the frame by DMA - * 5. release the buffer ??? - ** use our own allocation alloc_tx - ** we make sure the alignment and additional memory - *** we always release the skb - - */ -int amazon_atm_dma_tx(u8 vpi, u16 vci, u8 clp, u8 qid, struct sk_buff *skb) -{ - int err=0,need_pop=1; - u32 * data=NULL; - int nwrite=0; - struct sk_buff *skb_tmp; - u32 len=skb->len; - - //AAL5S inbound header 8 bytes - if (skb->len > g_atm_dev.aal5.tx_max_sdu - AAL5S_INBOUND_HEADER) { - AMAZON_TPE_DMSG("tx_max_sdu:%u\n",g_atm_dev.aal5.tx_max_sdu); - AMAZON_TPE_DMSG("skb too large [%u]!\n",skb->len); - err = -EMSGSIZE; - goto atm_dma_tx_error_exit; - } - - //Check the byte alignment requirement and header space - if ( ( ((u32)(skb->data)%16) !=AAL5S_INBOUND_HEADER)|| (skb_headroom(skb)len+16); - if (skb_tmp==NULL){ - err = - ENOMEM; - goto atm_dma_tx_error_exit; - } - alloc_align_16(skb_tmp); - g_atm_dev.aal5.cnt_cpy++; - skb_reserve(skb_tmp,AAL5S_INBOUND_HEADER); - memcpy(skb_put(skb_tmp,skb->len), skb->data, skb->len); - amazon_atm_free_tx_skb(skb); - need_pop=0; - skb = skb_tmp; - } - //Provide AAL5S inbound header - data = (u32 *)skb_push(skb,8); - data[0] = __be32_to_cpu(vpi<<20|vci<<4|clp); - data[1] = __be32_to_cpu(g_atm_dev.aal5.padding_byte<<8|qid); - - len = skb->len; - - //send through DMA - AMAZON_TPE_DMSG("AAL5S header 0 %8x\n", data[0]); - AMAZON_TPE_DMSG("AAL5S header 0 %8x\n", data[1]); - AMAZON_TPE_DMSG("about to call dma_write len: %u\n", len); - nwrite=dma_device_write( &g_dma_dev,skb->data,len,skb); - if (nwrite != len) { - //DMA descriptors full -// AMAZON_TPE_EMSG("AAL5 packet drop due to DMA nwrite:%u skb->len:%u\n", nwrite,len); - AMAZON_TPE_DMSG("AAL5 packet drop due to DMA nwrite:%u skb->len:%u\n", nwrite,len); - err = -EAGAIN; - goto atm_dma_tx_drop_exit; - } - AMAZON_TPE_DMSG("just finish call dma_write\n"); - //release in the "dma done" call-back - return 0; -atm_dma_tx_error_exit: - g_atm_dev.mib_counter.tx_err++; - queue_statics(qid, QS_ERR); - goto atm_dma_tx_exit; - -atm_dma_tx_drop_exit: - g_atm_dev.mib_counter.tx_drop++; - queue_statics(qid, QS_SW_DROP); -atm_dma_tx_exit: - if (need_pop){ - amazon_atm_free_tx_skb(skb); - }else{ - dev_kfree_skb_any(skb); - } - return err; -} - -/* Brief: Send AAL0/AAL5 packet - * Parameters: atm_vcc - Pointer to VCC data structure - * skb - Pointer to sk_buff structure, that contains the data - * Return: 0 - sucessful - * -ENOMEM - No memory available - * -EINVAL - Not supported - * Description: - * See amazon_atm_dma_tx - */ -int amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb) -{ - int qid=0; - u8 clp=0; - int err=0; - u32 wm=0; - - if (vcc == NULL || skb == NULL){ - AMAZON_TPE_EMSG("invalid parameter\n"); - return -EINVAL; - } - ATM_SKB(skb)->vcc = vcc; - qid = amazon_atm_get_queue(vcc); - if (valid_qid(qid) != 1) { - AMAZON_TPE_EMSG("invalid vcc!\n"); - err = -EINVAL; - goto atm_send_err_exit; - } - - //Send AAL0 using SWIN - if (vcc->qos.aal == ATM_AAL0){ -#ifdef TPE_LOOPBACK - err=amazon_atm_swin((qid+CBM_RX_OFFSET), skb->data); -#else - err=amazon_atm_swin(qid, skb->data); -#endif - if (err){ - goto atm_send_err_exit; - } - goto atm_send_exit; - } - - //Should be AAl5 - //MIB counter - g_atm_dev.mib_counter.tx++; - adsl_led_flash();//joelin adsl led - queue_statics(qid, QS_PKT); - -#ifdef AMAZON_CHECK_LINK - //check adsl link - if (adsl_link_status == 0){ - //link down - AMAZON_TPE_DMSG("ADSL link down, discarded!\n"); - err=-EFAULT; - goto atm_send_drop_exit; - } -#endif - clp = (vcc->atm_options&ATM_ATMOPT_CLP)?1:0; - //check watermark first - wm = readl(CBM_WMSTAT0_ADDR); - if ( (wm & (1<qos.txtp.traffic_class != ATM_CBR - &&vcc->qos.txtp.traffic_class != ATM_VBR_RT) - &(wm & (CBM_WM_NRT_MASK | (clp&CBM_WM_CLP1_MASK)) ))){ - //wm hit: discard - AMAZON_TPE_DMSG("watermark hit, discarded!\n"); - err=-EFAULT; - goto atm_send_drop_exit; - } -#ifdef TPE_LOOPBACK - return amazon_atm_dma_tx(vcc->vpi, vcc->vci,clp, (qid+CBM_RX_OFFSET),skb); -#else - return amazon_atm_dma_tx(vcc->vpi, vcc->vci,clp, qid,skb); -#endif - -atm_send_exit: - amazon_atm_free_tx_skb_vcc(vcc,skb); - return 0; - -atm_send_drop_exit: - g_atm_dev.mib_counter.tx_drop++; - queue_statics(qid,QS_SW_DROP); -atm_send_err_exit: - amazon_atm_free_tx_skb_vcc(vcc,skb); - return err; -} - -/* Brief: Return ATM port related MIB - * Parameter: interface number - atm_cell_ifEntry_t - */ -int amazon_atm_cell_mib(atm_cell_ifEntry_t* to,u32 itf) -{ - g_atm_dev.mib_counter.htu_unp += readl(HTU_MIBCIUP); - to->ifInUnknownProtos = g_atm_dev.mib_counter.htu_unp; -#ifdef AMAZON_TPE_READ_ARC - u32 reg_val=0; - meiDebugRead((AR_CELL0_ADDR+itf*4),®_val,1); - g_atm_dev.mib_counter.rx_cells += reg_val; - reg_val=0; - meiDebugWrite((AR_CELL0_ADDR+itf*4),®_val,1); - to->ifHCInOctets_h = (g_atm_dev.mib_counter.rx_cells * 53)>>32; - to->ifHCInOctets_l = (g_atm_dev.mib_counter.rx_cells * 53) & 0xffff; - - meiDebugRead((AT_CELL0_ADDR+itf*4),®_val,1); - g_atm_dev.mib_counter.tx_cells += reg_val; - reg_val=0; - meiDebugWrite((AT_CELL0_ADDR+itf*4),®_val,1); - to->ifHCOutOctets_h = (g_atm_dev.mib_counter.tx_cells * 53)>>32; - to->ifHCOutOctets_l = (g_atm_dev.mib_counter.rx_cells * 53) & 0xffff; - - meiDebugRead((AR_CD_CNT0_ADDR+itf*4),®_val,1); - g_atm_dev.mib_counter.rx_err_cells += reg_val; - reg_val=0; - meiDebugWrite((AR_CD_CNT0_ADDR+itf*4),®_val,1); - to->ifInErrors = g_atm_dev.mib_counter.rx_err_cells; - - to->ifOutErrors = 0; -#else - to->ifHCInOctets_h = 0; - to->ifHCInOctets_l = 0; - to->ifHCOutOctets_h = 0; - to->ifHCOutOctets_l = 0; - to->ifInErrors = 0; - to->ifOutErrors = 0; -#endif - return 0; -} - -/* Brief: Return ATM AAL5 related MIB - * Parameter: - atm_aal5_ifEntry_t - */ -int amazon_atm_aal5_mib(atm_aal5_ifEntry_t* to) -{ - u32 reg_l,reg_h; - //AAL5R received Octets from ATM - reg_l = readl(AAL5_RIOL_ADDR); - reg_h = readl(AAL5_RIOM_ADDR); - g_atm_dev.mib_counter.rx_cnt_h +=reg_h; - if (reg_l + g_atm_dev.mib_counter.rx_cnt_l < reg_l){ - g_atm_dev.mib_counter.rx_cnt_h++; - } - - g_atm_dev.mib_counter.rx_cnt_l+= reg_l; - //AAL5S sent Octets to ATM - reg_l = readl(AAL5_SOOL_ADDR); - reg_h = readl(AAL5_SOOM_ADDR); - g_atm_dev.mib_counter.tx_cnt_h +=reg_h; - if (reg_l + g_atm_dev.mib_counter.tx_cnt_l < reg_l){ - g_atm_dev.mib_counter.tx_cnt_h++; - } - g_atm_dev.mib_counter.tx_cnt_l+= reg_l; - - - g_atm_dev.mib_counter.tx_ppd += readl(CBM_AAL5ODIS_ADDR); - g_atm_dev.mib_counter.rx_drop += readl(CBM_AAL5IDIS_ADDR); - - //store - to->ifHCInOctets_h = g_atm_dev.mib_counter.rx_cnt_h; - to->ifHCInOctets_l = g_atm_dev.mib_counter.rx_cnt_l; - to->ifHCOutOctets_h = g_atm_dev.mib_counter.tx_cnt_h; - to->ifHCOutOctets_l = g_atm_dev.mib_counter.tx_cnt_l; - to->ifOutDiscards = g_atm_dev.mib_counter.tx_drop; - to->ifInDiscards = g_atm_dev.mib_counter.rx_drop; - - //Software provided counters - //packets passed to higher layer - to->ifInUcastPkts = g_atm_dev.mib_counter.rx; - //packets passed from higher layer - to->ifOutUcastPkts = g_atm_dev.mib_counter.tx; - //number of wrong downstream packets - to->ifInErrors = g_atm_dev.mib_counter.rx_err; - //number of wrong upstream packets - to->ifOutErros = g_atm_dev.mib_counter.tx_err; - - return 0; -} -/* Brief: Return ATM AAL5 VCC related MIB from internale use - * Parameter: - * qid - * atm_aal5_vcc_t - */ -static int __amazon_atm_vcc_mib(int qid, atm_aal5_vcc_t* to) -{ - //aal5VccCrcErrors - to->aal5VccCrcErrors = g_atm_dev.queues[qid].aal5VccCrcErrors; - to->aal5VccOverSizedSDUs =g_atm_dev.queues[qid].aal5VccOverSizedSDUs; - to->aal5VccSarTimeOuts = 0; //not supported yet - return 0; -} -/* Brief: Return ATM AAL5 VCC related MIB from vpi/vci - * Parameter: atm_vcc - * atm_aal5_vcc_t - */ -int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to) -{ - int qid=0; - int err=0; - qid = amazon_atm_find_vpivci(vpi, vci); - if (qid >0 ){ - err = __amazon_atm_vcc_mib(qid,to); - }else{ - return -EINVAL; - } - return err; -} - - -/* Brief: Return ATM AAL5 VCC related MIB - * Parameter: atm_vcc - * atm_aal5_vcc_t - */ -int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t* to) -{ - int qid=0; - int err=0; - qid = amazon_atm_get_queue(vcc); - if (qid >0 ){ - err = __amazon_atm_vcc_mib(qid,to); - }else{ - return -EINVAL; - } - return err; -} - -/* Brief: Close ATM connection - * Parameters: atm_vcc - Pointer to VCC data structure - * Return: no - * Description: - * This function closes the given ATM connection - */ -void amazon_atm_close(struct atm_vcc *vcc){ - int i; - int qid=0; - u32 tmp1; - u8 * qd_addr; - unsigned long flags; - if (vcc == NULL){ - AMAZON_TPE_EMSG("invalid parameter. vcc is null\n"); - return; - } - u32 itf = (u32) vcc->itf; - //release bandwidth - if (vcc->qos.txtp.traffic_class == ATM_CBR){ - g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.max_pcr; - g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.max_pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_VBR_RT){ - g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.max_pcr; - g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.max_pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_VBR_NRT){ - g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.pcr; - g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS){ - g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.min_pcr; - g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.min_pcr; - } - - qid = amazon_atm_get_queue(vcc); - if (qid == -EINVAL){ - AMAZON_TPE_EMSG("unknown vcc %u.%u.%u\n", vcc->itf, vcc->vpi, vcc->vci); - return; - } - local_irq_save(flags); - //Disable HTU entry - i=0; - while ((tmp1 = readl(HTU_RAMSTAT_ADDR))!=0 && i < HTU_RAM_ACCESS_MAX) i++; - if (i == HTU_RAM_ACCESS_MAX){ - AMAZON_TPE_EMSG("HTU RAM ACCESS out of time\n"); - } - - // write address register - AMAZON_WRITE_REGISTER_L(qid - CBM_DEFAULT_Q_OFFSET, HTU_RAMADDR_ADDR); - // invalidate the connection - AMAZON_WRITE_REGISTER_L(0, HTU_RAMDAT1_ADDR); - // write command - AMAZON_WRITE_REGISTER_L(HTU_RAMCMD_WR,HTU_RAMCMD_ADDR); - - qd_addr = (u8 *) KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr); -#ifdef AMAZON_ATM_DEBUG - tmp1 = readl(qd_addr+qid*CBM_QD_SIZE+0x8) & 0xffff; - AMAZON_TPE_DMSG("TX queue has %u cells \n", tmp1); - tmp1 = readl( qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE+0x08)&0xffff; - AMAZON_TPE_DMSG("RX queue has %u cells \n", tmp1); -#endif - // set threshold of txqueue to 0 - tmp1 = readl(qd_addr+qid*CBM_QD_SIZE+0x0c); - tmp1&= (~ CBM_QD_W3_THRESHOLD_MASK); - AMAZON_WRITE_REGISTER_L(tmp1, (qd_addr+qid*CBM_QD_SIZE+0x0c)); - // set threshold of rxqueue to 0 - tmp1 = readl( qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE+0x0c); - tmp1&= (~ CBM_QD_W3_THRESHOLD_MASK); - AMAZON_WRITE_REGISTER_L(tmp1,(qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE+0x0c)); - - //clear internal mapping - amazon_atm_clear_vcc(qid); - amazon_atm_clear_vcc(qid+CBM_RX_OFFSET); - - local_irq_restore(flags); -} - - -/* Brief: initialize internal data structure - */ -static void atm_constructor(amazon_atm_dev_t * dev) -{ - int i; - memset(dev,0,sizeof(amazon_atm_dev_t)); - atm_init_parameters(dev); - //internal: queue "free" flag - for(i=1;iqueues[i].vcc=NULL; - dev->queues[i].free = 1; - } - for(i=0;iports[i].tx_rem_cr = dev->ports[i].tx_max_cr; - } - //MIB - atomic_set(&dev->dma_tx_free_0,1); //initially there should be free descriptors -} - -/* Brief: return round up base-2 logarithm - */ -static inline int get_log_2(u32 value) -{ - int i=0,j=1; - while (i<11){ - if (j>=value) break; - j=j<<1; - i++; - } - AMAZON_TPE_DMSG("round up base-2 logarithm of %u is %u\n", value, i); - return i; -} - -/* Brief: TPE hardware initialization - * Parameter: specifiy the configurations of the hardware - */ -static inline int atm_init_hard(amazon_atm_dev_t * dev) -{ - int i; - u32 tmp1, tmp2, tmp3; - u8 * mem_addr=NULL; - u8 * qd_addr=NULL; - //PMU power on the module 1st - *(AMAZON_PMU_PWDCR) = (*AMAZON_PMU_PWDCR) | (AMAZON_PMU_PWDCR_TPE); - //Reset the module - *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) | (AMAZON_RST_REQ_TPE); - mb(); - mdelay(100); - *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) & (~(AMAZON_RST_REQ_TPE)); - mb(); - - unsigned long qsb_clk = amazon_get_fpi_hz()>>1; - /*********allocate & arrange memory for CBM *********/ - if (dev->cbm.mem_addr == NULL){ - dev->cbm.allocated = 1; - mem_addr = (u8 *)__get_free_pages(GFP_KERNEL, get_log_2(((CBM_CELL_SIZE * dev->cbm.free_cell_cnt) >>PAGE_SHIFT) + 1)); - if (mem_addr != NULL){ - dev->cbm.mem_addr = mem_addr; - } else { - goto init_no_mem; - } - } - if (dev->cbm.qd_addr == NULL){ -#ifdef CONFIG_USE_VENUS - //to work around a bug, bit15 of QDOFF address should be 1,Aug4, 2004 - //thus, we allocate 64k memory - qd_addr = (u8 *)__get_free_pages(GFP_KERNEL, 4); - if (qd_addr != NULL) { - dev->cbm.qd_addr_free = (u8*) (((unsigned long) qd_addr)); - dev->cbm.qd_addr = (u8*) (((unsigned long) qd_addr) | 0x8000); - }else{ - goto init_no_mem; - } -#else //CONFIG_USE_VENUS - qd_addr = (u8 *)kmalloc( CBM_QD_SIZE * AMAZON_ATM_MAX_QUEUE_NUM, GFP_KERNEL); - if (qd_addr != NULL) { - dev->cbm.qd_addr = qd_addr; - }else { - goto init_no_mem; - } -#endif //CONFIG_USE_VENUS - } -//#ifndef CONFIG_MIPS_UNCACHED - mem_addr = (u8 *)KSEG1ADDR((unsigned long)dev->cbm.mem_addr); - qd_addr = (u8 *)KSEG1ADDR((unsigned long)dev->cbm.qd_addr); -//#endif - //CBM reset cell queue memory, 64 bytes / cell - memset_io(mem_addr, 0, CBM_CELL_SIZE * dev->cbm.free_cell_cnt); - //make a link list, last 4 bytes is pointer - for(i=1;icbm.free_cell_cnt;i++){ - AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr + CBM_CELL_SIZE * i)),(mem_addr + CBM_CELL_SIZE * (i-1) + 0x3c)); - } - //reset queue descriptor - memset_io(qd_addr, 0, CBM_QD_SIZE * AMAZON_ATM_MAX_QUEUE_NUM); - //init word 0-2 of q0 (free cell list) - //address of last cell - AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr + CBM_CELL_SIZE * (dev->cbm.free_cell_cnt-1))), qd_addr); - //address of first cell - AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr)), (qd_addr + 4)); - //no. of free cells - AMAZON_WRITE_REGISTER_L(dev->cbm.free_cell_cnt,(qd_addr + 8)); - //init q descriptor for OAM receiving - AMAZON_WRITE_REGISTER_L((CBM_QD_W3_INT_ACA | (divide_by_64_round_up(oam_q_threshold)&0xff)<< CBM_QD_W3_THRESHOLD_SHIFT), (qd_addr + AMAZON_ATM_OAM_Q_ID * CBM_QD_SIZE + 0x0c)); -// AMAZON_WRITE_REGISTER_L((CBM_QD_W3_INT_ACA | (u32)oam_q_threshold<< CBM_QD_W3_THRESHOLD_SHIFT), (qd_addr + AMAZON_ATM_OAM_Q_ID * CBM_QD_SIZE + 0x0c)); - //config CBM - //set offset address and threshold - AMAZON_WRITE_REGISTER_L(CPHYSADDR(qd_addr), CBM_QDOFF_ADDR); - AMAZON_WRITE_REGISTER_L(((dev->cbm.nrt_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_NRTTHR_ADDR); - AMAZON_WRITE_REGISTER_L(((dev->cbm.clp0_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_CLP0THR_ADDR); - AMAZON_WRITE_REGISTER_L(((dev->cbm.clp1_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_CLP1THR_ADDR); - //config interrupts - AMAZON_WRITE_REGISTER_L( CBM_IMR_MASK & (~(CBM_IMR_ACA|CBM_IMR_Q0E|CBM_IMR_Q0I|CBM_IMR_RDE|CBM_IMR_OPF|CBM_IMR_ERR -#ifdef AMAZON_ATM_DEBUG - |CBM_IMR_DISC|CBM_IMR_QFD|CBM_IMR_NFCA|CBM_IMR_CLP1TR|CBM_IMR_CLP0TR|CBM_IMR_NRTTR|CBM_IMR_QTR -#endif -#ifdef AMAZON_TPE_SCR - |CBM_IMR_EF -#endif - )), CBM_IMR0_ADDR); - AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_CBM_INT, CBM_SRC0_ADDR); - - //HTU - //RAM entry for number of possible connections per interface - tmp1 = dev->ports[0].max_conn?dev->ports[0].max_conn-1:0; - AMAZON_WRITE_REGISTER_L(tmp1, HTU_RX0_ADDR); - for(i=1;iports[i].max_conn; - AMAZON_WRITE_REGISTER_L(tmp1, HTU_RX0_ADDR + 4 * i); - } - dev->cbm.max_q_off = tmp1+1; - //Queue ID for OAM/RM/Other cells - AMAZON_WRITE_REGISTER_L (AMAZON_ATM_OAM_Q_ID, HTU_DESTOAM_ADDR); - AMAZON_WRITE_REGISTER_L( AMAZON_ATM_RM_Q_ID, HTU_DESTRM_ADDR); - AMAZON_WRITE_REGISTER_L( AMAZON_ATM_OTHER_Q_ID, HTU_DESTOTHER_ADDR); - //Timeout - AMAZON_WRITE_REGISTER_L((u32) HTUTIMEOUT, HTU_TIMEOUT_ADDR); -#ifdef AMAZON_ATM_DEBUG - AMAZON_WRITE_REGISTER_L((u32) HTU_ISR_MASK - &(~(HTU_ISR_NE|HTU_ISR_TORD|HTU_ISR_OTOC|HTU_ISR_ONEC|HTU_ISR_PNE|HTU_ISR_PT)), HTU_IMR0_ADDR); - AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS|SRC_SRE_ENABLE|AMAZON_HTU_INT,HTU_SRC0_ADDR); -#endif - //QSB - //global setting, TstepC, SBL, Tau - //Tau - AMAZON_WRITE_REGISTER_L(dev->qsb.tau, QSB_TAU_ADDR); - //SBL - AMAZON_WRITE_REGISTER_L(dev->qsb.sbl, QSB_SBL_ADDR); - //tstep - AMAZON_WRITE_REGISTER_L(dev->qsb.tstepc>>1, QSB_CONFIG_ADDR); - - //port settting - for(i=0;iports[i].enable) && (dev->ports[i].tx_max_cr!=0) ){ - tmp1 = ((qsb_clk * dev->qsb.tstepc) >>1) / dev->ports[i].tx_max_cr; - tmp2 = tmp1 / 64; //integer value of Tsb - tmp3 = tmp1%64 + 1; //fractional part of Tsb - //carry over to integer part (?) - if (tmp3 == 64) { - tmp3 = 0; - tmp2++; - } - if (tmp2 == 0){ - tmp2 = 1; - tmp3 = 1; - } - //1. set mask 2. write value to data transfer register 3. start the transfer - //SCT(FracRate) - AMAZON_WRITE_REGISTER_L(QSB_SET_SCT_MASK, QSB_RTM_ADDR); - AMAZON_WRITE_REGISTER_L(tmp3,QSB_RTD_ADDR); - AMAZON_WRITE_REGISTER_L(((QSB_TABLESEL_SCT<aal5.tx_max_sdu,AAL5_SMFL_ADDR); - AMAZON_WRITE_REGISTER_L(dev->aal5.rx_max_sdu,AAL5_RMFL_ADDR); - AMAZON_WRITE_REGISTER_L(AAL5_SCMD_MODE_POLL // enable polling mode - |AAL5_SCMD_SS - |AAL5_SCMD_AR - ,AAL5_SCMD_ADDR); - //start CBM - AMAZON_WRITE_REGISTER_L(CBM_CFG_START,CBM_CFG_ADDR); - wmb(); - return 0; -init_no_mem: - if (mem_addr != NULL) free_pages((unsigned long)mem_addr,get_log_2(((CBM_CELL_SIZE * dev->cbm.free_cell_cnt) >>PAGE_SHIFT) + 1)); - -#ifdef CONFIG_USE_VENUS - //to work around a bug, bit15 of QDOFF address should be 1 - if (qd_addr != NULL) free_pages((unsigned long)qd_addr,4); -#else //CONFIG_USE_VENUS - if (qd_addr != NULL) kfree(qd_addr); -#endif //CONFIG_USE_VENUS - return -ENOMEM; -} - -/* - * Brief: Create entry in /proc for status information - */ -void atm_create_proc(void) -{ - create_proc_read_entry("amazon_atm", 0,NULL, amazon_atm_read_procmem,(void*)PROC_ATM); - create_proc_read_entry("amazon_atm_mib", 0,NULL, amazon_atm_read_procmem,(void*)PROC_MIB); - create_proc_read_entry("amazon_atm_vcc", 0,NULL, amazon_atm_read_procmem,(void*)PROC_VCC); -#if 0 - create_proc_read_entry("amazon_atm_aal5", 0,NULL, amazon_atm_read_procmem,(void*)PROC_AAL5); - create_proc_read_entry("amazon_atm_cbm", 0,NULL, amazon_atm_read_procmem,(void*)PROC_CBM); - create_proc_read_entry("amazon_atm_htu", 0,NULL, amazon_atm_read_procmem,(void*)PROC_HTU); - create_proc_read_entry("amazon_atm_qsb", 0,NULL, amazon_atm_read_procmem,(void*)PROC_QSB); - create_proc_read_entry("amazon_atm_swie", 0,NULL, amazon_atm_read_procmem,(void*)PROC_SWIE); -#endif -} - -/* - * Brief: Delete entry in /proc for status information - */ -void atm_delete_proc(void) -{ - remove_proc_entry("amazon_atm", NULL); - remove_proc_entry("amazon_atm_mib", NULL); - remove_proc_entry("amazon_atm_vcc", NULL); -#if 0 - remove_proc_entry("amazon_atm_aal5", NULL); - remove_proc_entry("amazon_atm_cbm", NULL); - remove_proc_entry("amazon_atm_htu", NULL); - remove_proc_entry("amazon_atm_qsb", NULL); - remove_proc_entry("amazon_atm_swie", NULL); -#endif -} -/* Brief: Initialize ATM module - * Parameters: no - * Return: &g_atm_dev - sucessful - * NULL - fails: - * 1. invalid parameter - * 2. No memory available - * Description: - * This function configure the TPE components according to the input info, - * -CBM - * -HTU - * -QSB - * -AAL5 - * - */ -amazon_atm_dev_t * amazon_atm_create(void) -{ - int i; - AMAZON_TPE_DMSG("atm_init\n"); - /************initialize global data structure****************/ - atm_constructor(&g_atm_dev); - /***********allocate kernel resources****************/ - //bottom halfs for SWEX - swex_start_task.routine = amazon_atm_swex; - swex_start_task.data = NULL; - swex_complete_task.routine = amazon_atm_swex_push; - swex_complete_task.data = NULL; -#ifdef AMAZON_TPE_SCR - a5r_task.routine = amazon_atm_a5r; - a5r_task.data = NULL; -#endif //AMAZON_TPE_SCR - //SWIN semaphore - sema_init(&(g_atm_dev.swie.in_sem), 1); - //SWIE lock - clear_bit(SWIE_LOCK, &(g_atm_dev.swie.lock)); - //SWIE wait queue - init_waitqueue_head(&(g_atm_dev.swie.sleep)); - atm_create_proc(); - - //register DMA - memset(&g_dma_dev,0,sizeof(struct dma_device_info)); - strcpy(g_dma_dev.device_name,"TPE"); - g_dma_dev.weight=1; - g_dma_dev.num_tx_chan=2; - g_dma_dev.num_rx_chan=2; - g_dma_dev.ack=1; - g_dma_dev.tx_burst_len=4; - g_dma_dev.rx_burst_len=4; - //DMA TX - - for(i=0;i<1;i++){ - g_dma_dev.tx_chan[i].weight=QOS_DEFAULT_WGT; - g_dma_dev.tx_chan[i].desc_num=10; - g_dma_dev.tx_chan[i].packet_size=g_atm_dev.aal5.tx_max_sdu + AAL5S_INBOUND_HEADER; - g_dma_dev.tx_chan[i].control=1; - } - //DMA RX - for(i=0;i<2;i++){ - g_dma_dev.rx_chan[i].weight=QOS_DEFAULT_WGT; - /* BingTao's suggestion, change from 5->10 will prevent packet loss in NO_TX_INT mode */ - g_dma_dev.rx_chan[i].desc_num=10; - g_dma_dev.rx_chan[i].packet_size=(g_atm_dev.aal5.rx_max_sdu + AAL5R_TRAILER_LEN+0x10f)&(~0xf); - g_dma_dev.rx_chan[i].control=1; - } - g_dma_dev.intr_handler=amazon_atm_dma_handler; - g_dma_dev.buffer_alloc=amazon_atm_alloc_rx; - g_dma_dev.buffer_free=amazon_atm_free_tx; - dma_device_register(&g_dma_dev); -/***********intialize the atm hardware ****************/ - if ( atm_init_hard(&g_atm_dev) != 0){ - return NULL; - } - //start CBM - AMAZON_WRITE_REGISTER_L(CBM_CFG_START,CBM_CFG_ADDR); - wmb(); - - //Start HTU - AMAZON_WRITE_REGISTER_L(HTU_CFG_START ,HTU_CFG_ADDR); - wmb(); - - - // Register interrupts for insertion and extraction - request_irq(AMAZON_SWIE_INT, amazon_atm_swie_isr, SA_INTERRUPT, "tpe_swie", NULL); - request_irq(AMAZON_CBM_INT, amazon_atm_cbm_isr, SA_INTERRUPT, "tpe_cbm", NULL); -#ifdef AMAZON_ATM_DEBUG - request_irq(AMAZON_HTU_INT , amazon_atm_htu_isr, SA_INTERRUPT, "tpe_htu", NULL); -#endif -#ifdef AMAZON_TPE_TEST_AAL5_INT - request_irq(AMAZON_AAL5_INT, amazon_atm_aal5_isr, SA_INTERRUPT, "tpe_aal5", NULL); -#endif - return &g_atm_dev; -} - -/* Brief: clean up atm - * Parameters: no - * Return: no - * Description: - * Disable the device. - */ -void amazon_atm_cleanup(void){ - int i; - clear_bit(SWIE_LOCK, &(g_atm_dev.swie.lock)); - wake_up(&g_atm_dev.swie.sleep); - up(&g_atm_dev.swie.in_sem); - // diable SWIE interrupts - AMAZON_WRITE_REGISTER_L(0, SWIE_ISRC_ADDR); - AMAZON_WRITE_REGISTER_L(0, SWIE_ESRC_ADDR); - wmb(); - - // Disable schedulers ( including interrupts )----------------------- - for (i = 0; i < AMAZON_ATM_PORT_NUM; i++); - { - AMAZON_WRITE_REGISTER_L(QSB_SET_SPT_SBVALID_MASK, QSB_RTM_ADDR); - AMAZON_WRITE_REGISTER_L( 0 ,QSB_RTD_ADDR); - AMAZON_WRITE_REGISTER_L( (QSB_TABLESEL_SPT<>PAGE_SHIFT)+1)); -#ifdef CONFIG_USE_VENUS - //to work around a bug, bit15 of QDOFF address should be 1 - free_pages((unsigned long)g_atm_dev.cbm.qd_addr_free,4); -#else //CONFIG_USE_VENUS - kfree(g_atm_dev.cbm.qd_addr); -#endif //CONFIG_USE_VENUS - } - atm_delete_proc(); - // free interrupts for insertion and extraction - dma_device_unregister(&g_dma_dev); - free_irq(AMAZON_SWIE_INT, NULL); - free_irq(AMAZON_CBM_INT, NULL); -#ifdef AMAZON_ATM_DEBUG - free_irq(AMAZON_HTU_INT, NULL); -#endif -#ifdef AMAZON_TPE_TEST_AAL5_INT - free_irq(AMAZON_AAL5_INT, NULL); -#endif - -} - -/************************ ATM network interface ***********************************************/ -/* Brief: getsockopt - */ -int amazon_atm_getsockopt(struct atm_vcc *vcc, int level, int optname, char *optval, int optlen) -{ - int err=0; - atm_aal5_vcc_t mib_vcc; - AMAZON_TPE_DMSG("1\n"); - switch (optname){ - case SO_AMAZON_ATM_MIB_VCC: - AMAZON_TPE_DMSG("2\n"); - err = amazon_atm_vcc_mib(vcc, &mib_vcc); - AMAZON_TPE_DMSG("%u\n",mib_vcc.aal5VccCrcErrors); - err = copy_to_user((void *)optval,&mib_vcc, sizeof(mib_vcc)); - AMAZON_TPE_DMSG("err %u\n",err); - break; - default: - return -EFAULT; - } - return err; -} - -/* Brief: IOCTL - */ - -int amazon_atm_ioctl(struct atm_dev *dev,unsigned int cmd,void *arg) -{ - int err=0; - //MIB - atm_cell_ifEntry_t mib_cell; - atm_aal5_ifEntry_t mib_aal5; - atm_aal5_vcc_x_t mib_vcc; - if (_IOC_TYPE(cmd) != AMAZON_ATM_IOC_MAGIC) return -ENOTTY; - if (_IOC_NR(cmd) > AMAZON_ATM_IOC_MAXNR) return -ENOTTY; - - if (_IOC_DIR(cmd) & _IOC_READ) - err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd)); - else if (_IOC_DIR(cmd) & _IOC_WRITE) - err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd)); - if (err) { - AMAZON_TPE_EMSG("acess verification fails \n"); - return -EFAULT; - } - switch(cmd) { - case AMAZON_ATM_MIB_CELL: - err = amazon_atm_cell_mib(&mib_cell,(u32)arg); - if (err==0){ - err = __copy_to_user((void *)arg,&mib_cell,sizeof(mib_cell)); - }else{ - AMAZON_TPE_EMSG("cannot get MIB ATM_CELL\n"); - } - break; - case AMAZON_ATM_MIB_AAL5: - err = amazon_atm_aal5_mib(&mib_aal5); - if (err==0){ - err=__copy_to_user(arg, &mib_aal5, sizeof(mib_aal5)); - }else{ - AMAZON_TPE_EMSG("cannot get MIB ATM_AAL5\n"); - } - break; - case AMAZON_ATM_MIB_VCC: - err=__copy_from_user(&mib_vcc,arg, sizeof(mib_vcc)); - AMAZON_TPE_DMSG("return of copy_from_user %x\n",err); - err = amazon_atm_vcc_mib_x(mib_vcc.vpi, mib_vcc.vci, &(mib_vcc.mib_vcc)); - if (err==0){ - err=__copy_to_user(arg, &mib_vcc, sizeof(mib_vcc)); - }else{ - AMAZON_TPE_EMSG("cannot get MIB ATM_VCC\n"); - } - - default: - return -ENOTTY; - } - return err; -} -/* Brief: return a link list of OAM related time stamp info - * Parameter: none - * Return: - a link list of "struct oam_last_activity" data - * Description: - Each time, a F4/F5 cell or AAL5 packet is received, the time stamp is updated. - Through this call, u get a list of this time stamp for all active connection. - Please note that u have read-only access. - */ -const struct oam_last_activity* get_oam_time_stamp() -{ - int i,j; - for(i=CBM_DEFAULT_Q_OFFSET+CBM_RX_OFFSET,j=0;ivpi; - g_oam_time_stamp[j].vci = g_atm_dev.queues[i].vcc->vci; - g_oam_time_stamp[j].stamp = g_atm_dev.queues[i].access_time; - g_oam_time_stamp[j].next = NULL; - j++; - } - } - if (j==0) { - return NULL; - }else{ - return g_oam_time_stamp; - } -} - - -/* Brief: call back routine for rx - * Parameter: - * vcc atm_vcc pointer - * skb data if no error - err error flag, 0: no error, 1:error - * Return: - * 0 - * <>0 cannot push up - * Description: - * release the packet if cannot push up - */ -static int amazon_atm_net_push(struct atm_vcc *vcc,struct sk_buff *skb, int err) -{ - if (err){ - if (vcc && vcc->stats) { - atomic_inc(&vcc->stats->rx_err); - } - }else{ - ATM_SKB(skb)->vcc = vcc; - - if (!atm_charge(vcc, skb->truesize)){ - //no space this vcc - AMAZON_TPE_EMSG("no space for this vcc\n"); - dev_kfree_skb_any(skb); - return -ENOMEM; - } - atomic_inc(&vcc->stats->rx); - AMAZON_TPE_DMSG("push to vcc\n"); - vcc->push(vcc,skb); - } - return 0; -} -int amazon_atm_net_send_oam(struct atm_vcc*vcc, void *cell, int flags) -{ - return amazon_atm_send_oam(vcc,cell,flags); -} - -int amazon_atm_net_send(struct atm_vcc *vcc,struct sk_buff *skb) -{ - int err=0; - if (vcc->qos.aal == ATM_AAL0 || vcc->qos.aal == ATM_AAL5) { - err=amazon_atm_send(vcc,skb); - }else{ - //not supported - err = -EPROTONOSUPPORT; - } - if (err){ - atomic_inc(&vcc->stats->tx_err); - }else{ - atomic_inc(&vcc->stats->tx); - } - AMAZON_TPE_DMSG("sent, tx_inuse:%u\n", atomic_read(&vcc->tx_inuse)); - return err; -} - -int amazon_atm_net_open(struct atm_vcc *vcc,short vpi, int vci) -{ - vcc->itf = (int) vcc->dev->dev_data; - vcc->vpi = vpi; - vcc->vci = vci; - return(amazon_atm_open(vcc,amazon_atm_net_push)); -} - -static int amazon_atm_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flgs) -{ - int qid; - - if (vcc == NULL || qos == NULL){ - AMAZON_TPE_EMSG("invalid parameters\n"); - return -EINVAL; - } - qid = amazon_atm_get_queue(vcc); - if (valid_qid(qid) != 1) { - AMAZON_TPE_EMSG("no vcc connection opened\n"); - return -EINVAL; - } - set_qsb(vcc,qos,qid); - return 0; -} - -static struct atmdev_ops amazon_atm_ops = { - open: amazon_atm_net_open, - close: amazon_atm_close, - ioctl: amazon_atm_ioctl, - send: amazon_atm_net_send, - send_oam: amazon_atm_net_send_oam, -// getsockopt: amazon_atm_getsockopt, - change_qos: amazon_atm_change_qos, -// proc_read: amazon_atm_proc_read, - owner: THIS_MODULE, -}; // ATM device callback functions - -/* - * brief "/proc" function - */ -int amazon_atm_read_procmem(char *buf, char **start, off_t offset,int count, int *eof, void *data) -{ - int buf_off=0; /* for buf */ - int i=0,j=0; - int type= (u32)data;//which module - atm_aal5_ifEntry_t mib_aal5; - atm_cell_ifEntry_t mib_cell; - atm_aal5_vcc_t mib_vcc; - switch(type){ - case PROC_MIB: - //MIB counter - amazon_atm_aal5_mib(&mib_aal5); - //TX: - buf_off+=sprintf(buf+buf_off,"\n============= AAL5 Upstream =========\n"); - buf_off+=sprintf(buf+buf_off,"received %u (pkts) from upper layer\n", mib_aal5.ifOutUcastPkts); - buf_off+=sprintf(buf+buf_off,"errors: %u (pkts)\n",mib_aal5.ifOutErros); - buf_off+=sprintf(buf+buf_off,"discards: %u (ptks)\n", mib_aal5.ifOutDiscards); - buf_off+=sprintf(buf+buf_off,"transmitted: %x-%x (bytes) \n", - mib_aal5.ifHCOutOctets_h, mib_aal5.ifHCOutOctets_l); - //RX: - buf_off+=sprintf(buf+buf_off,"\n============= AAL5 Downstream =========\n"); - buf_off+=sprintf(buf+buf_off,"received %x-%x (bytes)\n", - mib_aal5.ifHCInOctets_h,mib_aal5.ifHCInOctets_l); - buf_off+=sprintf(buf+buf_off,"discards: %u (ptks)\n",mib_aal5.ifInDiscards); - buf_off+=sprintf(buf+buf_off,"errors: %u (ptks)\n",mib_aal5.ifInErrors); - buf_off+=sprintf(buf+buf_off,"passed %u (ptks) to upper layer\n",mib_aal5.ifInUcastPkts); - - //Cell level - buf_off+=sprintf(buf+buf_off,"\n============= ATM Cell =========\n"); - amazon_atm_cell_mib(&mib_cell,0); -#ifdef AMAZON_TPE_READ_ARC - buf_off+=sprintf(buf+buf_off,"Port 0: downstream received: %x-%x (bytes)\n",mib_cell.ifHCInOctets_h,mib_cell.ifHCInOctets_l); - buf_off+=sprintf(buf+buf_off,"Port 0: upstream transmitted: %x-%x (bytes)\n",mib_cell.ifHCOutOctets_h,mib_cell.ifHCOutOctets_l); - buf_off+=sprintf(buf+buf_off,"Port 0: downstream errors: %u (cells)\n",mib_cell.ifInErrors); - amazon_atm_cell_mib(&mib_cell,1); - buf_off+=sprintf(buf+buf_off,"Port 1: downstream received: %x-%x (bytes)\n",mib_cell.ifHCInOctets_h,mib_cell.ifHCInOctets_l); - buf_off+=sprintf(buf+buf_off,"Port 1: upstream transmitted: %x-%x (bytes)\n",mib_cell.ifHCOutOctets_h,mib_cell.ifHCOutOctets_l); - buf_off+=sprintf(buf+buf_off,"Port 1: downstream errors: %u (cells)\n",mib_cell.ifInErrors); -#endif - buf_off+=sprintf(buf+buf_off,"HTU discards: %u (cells)\n",mib_cell.ifInUnknownProtos); - - buf_off+=sprintf(buf+buf_off,"\n====== Specials =====\n"); - buf_off+=sprintf(buf+buf_off,"AAL5S PPD: %u (cells)\n",g_atm_dev.mib_counter.tx_ppd); -#ifdef AMAZON_TPE_SCR - buf_off+=sprintf(buf+buf_off,"Reassembly wait: %u \n",g_a5r_wait); -#endif - break; - case PROC_ATM: - //Interface (Port) - buf_off+=sprintf(buf+buf_off,"[Interfaces]\n"); - for(i=0;ivpi - ,g_atm_dev.queues[i].vcc->vci - ,g_atm_dev.queues[i].vcc->itf - ,i - ,(u32)g_atm_dev.queues[i+CBM_RX_OFFSET].access_time.tv_sec - ,(u32)g_atm_dev.queues[i+CBM_RX_OFFSET].access_time.tv_usec - ); - buf_off+=sprintf(buf+buf_off,"\tqos_tx class=%u max_pcr=%u pcr=%u min_pcr=%u scr=%u mbs=%u cdv=%u\n" - ,g_atm_dev.queues[i].vcc->qos.txtp.traffic_class - ,g_atm_dev.queues[i].vcc->qos.txtp.max_pcr - ,g_atm_dev.queues[i].vcc->qos.txtp.pcr - ,g_atm_dev.queues[i].vcc->qos.txtp.min_pcr - ,g_atm_dev.queues[i].vcc->qos.txtp.scr - ,g_atm_dev.queues[i].vcc->qos.txtp.mbs - ,g_atm_dev.queues[i].vcc->qos.txtp.cdv - ); - buf_off+=sprintf(buf+buf_off,"\tqos_rx class=%u max_pcr=%u pcr=%u min_pcr=%u scr=%u mbs=%u cdv=%u\n" - ,g_atm_dev.queues[i].vcc->qos.rxtp.traffic_class - ,g_atm_dev.queues[i].vcc->qos.rxtp.max_pcr - ,g_atm_dev.queues[i].vcc->qos.rxtp.pcr - ,g_atm_dev.queues[i].vcc->qos.rxtp.min_pcr - ,g_atm_dev.queues[i].vcc->qos.rxtp.scr - ,g_atm_dev.queues[i].vcc->qos.rxtp.mbs - ,g_atm_dev.queues[i].vcc->qos.rxtp.cdv - ); - __amazon_atm_vcc_mib((i+CBM_RX_OFFSET),&mib_vcc); - buf_off+=sprintf(buf+buf_off,"\tCRC error=%u\n", mib_vcc.aal5VccCrcErrors); - buf_off+=sprintf(buf+buf_off,"\toversized packet=%u\n", mib_vcc.aal5VccOverSizedSDUs); -#ifdef AMAZON_ATM_DEBUG - if ( valid_qid(i+CBM_RX_OFFSET)){ - buf_off+=sprintf(buf+buf_off,"\tdownstream statics\n" ); - buf_off+=sprintf(buf+buf_off,"\t\tpackets=%u\n",g_atm_dev.queues[i+CBM_RX_OFFSET].qs[QS_PKT]); - buf_off+=sprintf(buf+buf_off,"\t\terr_packets=%u\n",g_atm_dev.queues[i+CBM_RX_OFFSET].qs[QS_ERR] ); - buf_off+=sprintf(buf+buf_off,"\t\tsw_dropped=%u\n",g_atm_dev.queues[i+CBM_RX_OFFSET].qs[QS_SW_DROP] ); - } - - buf_off+=sprintf(buf+buf_off,"\tupstream statics\n" ); - buf_off+=sprintf(buf+buf_off,"\t\tpackets=%u\n",g_atm_dev.queues[i].qs[QS_PKT]); - buf_off+=sprintf(buf+buf_off,"\t\terr_packets=%u\n",g_atm_dev.queues[i].qs[QS_ERR] ); - buf_off+=sprintf(buf+buf_off,"\t\thw_dropped=%u\n",g_atm_dev.queues[i].qs[QS_HW_DROP] ); - buf_off+=sprintf(buf+buf_off,"\t\tsw_dropped=%u\n",g_atm_dev.queues[i].qs[QS_SW_DROP] ); - -#endif - - } - - } - break; - default: - break; - } - if(buf_off>0) *eof = 1; - return buf_off; -} - -#ifdef AMAZON_TPE_AAL5_RECOVERY -extern int (*tpe_reset)(void); -extern int (*tpe_start)(void); -extern int (*tpe_inject)(void); -/* Brief: Reset TPE hardware - * Description - * This is a wordaround for AAL5 bug. It tries to reset TPE. - * take care of software - * setup all previous connection - */ -int amazon_tpe_reset(void) -{ - struct atm_vcc * vcc; - int err=0; - int i; - u8 * qd_addr; - u32 reg_l, reg_h; - unsigned int a_cfg_value=0; - unsigned int a_cfg_old_value=0; - atm_aal5_ifEntry_t mib_aal5; - atm_cell_ifEntry_t mib_cell; - - //make sure all cells transmitting out first - //Segmentation done - amazon_atm_aal5_mib(&mib_aal5); - reg_l = g_atm_dev.mib_counter.tx_cnt_l; - reg_h = g_atm_dev.mib_counter.tx_cnt_h; - while(1){ - mdelay(10); - amazon_atm_aal5_mib(&mib_aal5); - if( (reg_l == g_atm_dev.mib_counter.tx_cnt_l) && (reg_h == g_atm_dev.mib_counter.tx_cnt_h) ){ - break; - } - AMAZON_TPE_DMSG("AAL5 Segmentation still in progress!\n"); - reg_l = g_atm_dev.mib_counter.tx_cnt_l; - reg_h = g_atm_dev.mib_counter.tx_cnt_h; - } - //QSB done - qd_addr = (u8 *) KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr); - for (i=1;i<15;i++){ - while ( (err=readl(qd_addr+i*CBM_QD_SIZE+0x8)&0xffff) !=0 ){ - mdelay(20); - AMAZON_TPE_DMSG("queue %u not empty (%u)\n",i,err); - } - } - //insurance for interfaces between Aware and CARB - mdelay(100); - amazon_atm_cell_mib(&mib_cell,0); - amazon_atm_cell_mib(&mib_cell,1); - amazon_atm_aal5_mib(&mib_aal5); - - mb(); - while ( (AMAZON_READ_REGISTER_L(AR_CELLRDY_BC0) != 0 ) || (AMAZON_READ_REGISTER_L(AR_CELLRDY_BC0) != 0 ) ){ - AMAZON_TPE_EMSG("\nwaiting for AWARE"); - AMAZON_TPE_EMSG(" BC0 %u ", AMAZON_READ_REGISTER_L(AR_CELLRDY_BC0)); - AMAZON_TPE_EMSG(" BC1 %u ", AMAZON_READ_REGISTER_L(AR_CELLRDY_BC1)); - AMAZON_TPE_EMSG("\n"); - mdelay(1); - } - // disable AAI module - meiDebugRead(A_CFG_ADDR,&a_cfg_value,1); - a_cfg_old_value=a_cfg_value; - a_cfg_value &= (~(0x2800)); - meiDebugWrite(A_CFG_ADDR,&a_cfg_value,1); - //clear buffer - a_cfg_value = 0x1; - meiDebugWrite(AR_CB0_STATUS_ADDR,&a_cfg_value,1); - meiDebugWrite(AR_CB1_STATUS_ADDR,&a_cfg_value,1); - - if ( atm_init_hard(&g_atm_dev) != 0){ - return -EIO; - } - sema_init(&(g_atm_dev.swie.in_sem), 1); - //SWIE lock - clear_bit(SWIE_LOCK, &(g_atm_dev.swie.lock)); - //SWIE wait queue - init_waitqueue_head(&(g_atm_dev.swie.sleep)); - - for (i=CBM_DEFAULT_Q_OFFSET;iqos, i); - set_qd(vcc, i); - mb(); - err=set_htu(vcc,i); - if (err){ - AMAZON_TPE_EMSG("set htu entry fails %u\n",err); - } - } - } - meiDebugWrite(A_CFG_ADDR,&a_cfg_old_value,1); -#if 0 - //reset DFE - *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) | (AMAZON_RST_REQ_DFE); - mb(); - *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) & (~AMAZON_RST_REQ_DFE); - mb(); -#endif - - return 0; -} - -/* Brief: Send a ATM EoP packet to save DMA channel - */ -int amazon_tpe_inject_debug_cell(void) -{ - //Send a ATM cell to save DMA channel - u8 qid; - unsigned char atm_cell[48]; - qid = 0x11; - AMAZON_TPE_DMSG("qid = %d\n",qid); - memset(atm_cell,0,48); - atm_cell[3] = 0x2; - if ( amazon_atm_swin(qid,atm_cell)) { - AMAZON_TPE_EMSG("cannot insert EoP cell\n"); - return -1; - } - return 0; -} - -/* Brief: start HTU (TPE) - */ - -int amazon_tpe_start(void) -{ - AMAZON_WRITE_REGISTER_L(HTU_CFG_START ,HTU_CFG_ADDR); - wmb(); - return 0; -} -#endif //AMAZON_TPE_AAL5_RECOVERY - -#ifdef AMAZON_CHECK_LINK -extern int (*adsl_link_notify)(int); -/* Brief: notify link status of ADSL link - * Parameters: 0 link down - * 1 link up - * Returns: 0 OK - * Details: called by MEI driver - * should update status and inform upper layer - */ -int amazon_tpe_link_notify(int status) -{ - adsl_link_status = status; - AMAZON_TPE_DMSG("link status %s\n",(status==1)?"Up":"Down"); - if (status == 0){ - //wait until no cells in upstream queues - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(2*HZ); - } - return 0; -} -#endif //ifdef AMAZON_CHECK_LINK - -/* - * Brief: Initialize ATM module - * - * Return Value: ENOMEM - No memory available - * EBUSY - Cannot register atm device - * ERESTARTSYS - Process interrupted by other signal - * 0 - OK, module initialized - * - * Description: - * This function registers an atm device for all UTOPIA devices. - * It also allocates memory for the private device data structures - */ -int __init amazon_atm_net_init(void) -{ - int i; - int err=0; - amazon_atm_dev_t *dev = NULL; - - if ((dev=amazon_atm_create()) != NULL){ - for(i=0;iports[i].enable){ - amazon_atm_devs[i] = NULL; - continue; - } - amazon_atm_devs[i] =atm_dev_register("amazon_atm",&amazon_atm_ops,-1,0UL); - if (amazon_atm_devs[i] == NULL){ - AMAZON_TPE_EMSG("atm_dev_register fails\n"); - err = -EIO; - goto amazon_atm_net_init_exit; - }else{ - AMAZON_TPE_DMSG("registering device %u\n",i); - amazon_atm_devs[i]->ci_range.vpi_bits = 8; - amazon_atm_devs[i]->ci_range.vci_bits = 16; - amazon_atm_devs[i]->link_rate = dev->ports[i].tx_max_cr; - amazon_atm_devs[i]->dev_data = (void *) i; - } - } - - }else{ - err = -ENOMEM; - AMAZON_TPE_EMSG("cannot init atm device\n"); - goto amazon_atm_net_init_exit; - } -#ifdef AMAZON_TPE_AAL5_RECOVERY - tpe_reset = & amazon_tpe_reset; - tpe_start = & amazon_tpe_start; - tpe_inject = & amazon_tpe_inject_debug_cell; -#endif //AMAZON_TPE_AAL5_RECOVERY -#ifdef AMAZON_CHECK_LINK - adsl_link_notify=amazon_tpe_link_notify; -#endif //AMAZON_CHECK_LINK -amazon_atm_net_init_exit: - return err; -} - -void __exit amazon_atm_net_cleanup(void) -{ - int i; - amazon_atm_cleanup(); - for(i=0;i ADM6996LC and ADM6996I will be in MDIO/MDC(SMI)(16 bit) mode, -// amazon should contrl ADM6996 by MDC/MDIO pin -// if undef ADM6996_MDC_MDIO_MODE==> ADM6996 will be in EEProm(32 bit) mode, -// amazon should contrl ADM6996 by GPIO15,16,17,18 pin -/* 507281:linmars 2005/07/28 support MDIO/EEPROM config mode */ -/* 509201:linmars remove driver testing codes */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -//#include - - -unsigned int ifx_sw_conf[ADM_SW_MAX_PORT_NUM+1] = \ - {ADM_SW_PORT0_CONF, ADM_SW_PORT1_CONF, ADM_SW_PORT2_CONF, \ - ADM_SW_PORT3_CONF, ADM_SW_PORT4_CONF, ADM_SW_PORT5_CONF}; -unsigned int ifx_sw_bits[8] = \ - {0x1, 0x3, 0x7, 0xf, 0x1f, 0x3f, 0x7f, 0xff}; -unsigned int ifx_sw_vlan_port[6] = {0, 2, 4, 6, 7, 8}; -//050613:fchang -/* 507281:linmars start */ -#ifdef CONFIG_SWITCH_ADM6996_MDIO -#define ADM6996_MDC_MDIO_MODE 1 //000001.joelin -#else -#undef ADM6996_MDC_MDIO_MODE -#endif -/* 507281:linmars end */ -#define adm6996i 0 -#define adm6996lc 1 -#define adm6996l 2 -unsigned int adm6996_mode=adm6996i; -/* - initialize GPIO pins. - output mode, low -*/ -void ifx_gpio_init(void) -{ - //GPIO16,17,18 direction:output - //GPIO16,17,18 output 0 - - AMAZON_SW_REG(AMAZON_GPIO_P1_DIR) |= (GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT) =AMAZON_SW_REG(AMAZON_GPIO_P1_IN)& ~(GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - -} - -/* read one bit from mdio port */ -int ifx_sw_mdio_readbit(void) -{ - //int val; - - //val = (AMAZON_SW_REG(GPIO_conf0_REG) & GPIO0_INPUT_MASK) >> 8; - //return val; - //GPIO16 - return AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&1; -} - -/* - MDIO mode selection - 1 -> output - 0 -> input - - switch input/output mode of GPIO 0 -*/ -void ifx_mdio_mode(int mode) -{ -// AMAZON_SW_REG(GPIO_conf0_REG) = mode ? GPIO_ENABLEBITS : -// ((GPIO_ENABLEBITS | MDIO_INPUT) & ~MDIO_OUTPUT_EN); - mode?(AMAZON_SW_REG(AMAZON_GPIO_P1_DIR)|=GPIO_MDIO): - (AMAZON_SW_REG(AMAZON_GPIO_P1_DIR)&=~GPIO_MDIO); - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_DIR); - mode?(r|=GPIO_MDIO):(r&=~GPIO_MDIO); - AMAZON_SW_REG(AMAZON_GPIO_P1_DIR)=r;*/ -} - -void ifx_mdc_hi(void) -{ - //GPIO_SET_HI(GPIO_MDC); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)|=GPIO_MDC; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r|=GPIO_MDC; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)|GPIO_MDC; -} - -void ifx_mdio_hi(void) -{ - //GPIO_SET_HI(GPIO_MDIO); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)|=GPIO_MDIO; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r|=GPIO_MDIO; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)|GPIO_MDIO; -} - -void ifx_mdcs_hi(void) -{ - //GPIO_SET_HI(GPIO_MDCS); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)|=GPIO_MDCS; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r|=GPIO_MDCS; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)|GPIO_MDCS; -} - -void ifx_mdc_lo(void) -{ - //GPIO_SET_LOW(GPIO_MDC); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)&=~GPIO_MDC; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r&=~GPIO_MDC; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&(~GPIO_MDC); -} - -void ifx_mdio_lo(void) -{ - //GPIO_SET_LOW(GPIO_MDIO); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)&=~GPIO_MDIO; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r&=~GPIO_MDIO; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&(~GPIO_MDIO); -} - -void ifx_mdcs_lo(void) -{ - //GPIO_SET_LOW(GPIO_MDCS); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)&=~GPIO_MDCS; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r&=~GPIO_MDCS; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&(~GPIO_MDCS); -} - -/* - mdc pulse - 0 -> 1 -> 0 -*/ -static void ifx_sw_mdc_pulse(void) -{ - ifx_mdc_lo(); - udelay(ADM_SW_MDC_DOWN_DELAY); - ifx_mdc_hi(); - udelay(ADM_SW_MDC_UP_DELAY); - ifx_mdc_lo(); -} - -/* - mdc toggle - 1 -> 0 -*/ -static void ifx_sw_mdc_toggle(void) -{ - ifx_mdc_hi(); - udelay(ADM_SW_MDC_UP_DELAY); - ifx_mdc_lo(); - udelay(ADM_SW_MDC_DOWN_DELAY); -} - -/* - enable eeprom write - For ATC 93C66 type EEPROM; accessing ADM6996 internal EEPROM type registers -*/ -static void ifx_sw_eeprom_write_enable(void) -{ - unsigned int op; - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_hi(); - udelay(ADM_SW_CS_DELAY); - /* enable chip select */ - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - /* start bit */ - ifx_mdio_hi(); - ifx_sw_mdc_pulse(); - - /* eeprom write enable */ - op = ADM_SW_BIT_MASK_4; - while (op) - { - if (op & ADM_SW_EEPROM_WRITE_ENABLE) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 3); - while (op) - { - ifx_mdio_lo(); - ifx_sw_mdc_pulse(); - op >>= 1; - } - /* disable chip select */ - ifx_mdcs_lo(); - udelay(ADM_SW_CS_DELAY); - ifx_sw_mdc_pulse(); -} - -/* - disable eeprom write -*/ -static void ifx_sw_eeprom_write_disable(void) -{ - unsigned int op; - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_hi(); - udelay(ADM_SW_CS_DELAY); - /* enable chip select */ - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - /* start bit */ - ifx_mdio_hi(); - ifx_sw_mdc_pulse(); - /* eeprom write disable */ - op = ADM_SW_BIT_MASK_4; - while (op) - { - if (op & ADM_SW_EEPROM_WRITE_DISABLE) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 3); - while (op) - { - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - /* disable chip select */ - ifx_mdcs_lo(); - udelay(ADM_SW_CS_DELAY); - ifx_sw_mdc_pulse(); -} - -/* - read registers from ADM6996 - serial registers start at 0x200 (addr bit 9 = 1b) - EEPROM registers -> 16bits; Serial registers -> 32bits -*/ -#ifdef ADM6996_MDC_MDIO_MODE //smi mode//000001.joelin -static int ifx_sw_read_adm6996i_smi(unsigned int addr, unsigned int *dat) -{ - addr=(addr<<16)&0x3ff0000; - AMAZON_SW_REG(AMAZON_SW_MDIO_ACC) =(0xC0000000|addr); - while ((AMAZON_SW_REG(AMAZON_SW_MDIO_ACC))&0x80000000){}; - *dat=((AMAZON_SW_REG(AMAZON_SW_MDIO_ACC))&0x0FFFF); - return 0; -} -#endif - -static int ifx_sw_read_adm6996i(unsigned int addr, unsigned int *dat) -{ - unsigned int op; - - ifx_gpio_init(); - - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_lo(); - - udelay(ADM_SW_CS_DELAY); - - /* preamble, 32 bit 1 */ - ifx_mdio_hi(); - op = ADM_SW_BIT_MASK_32; - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* command start (01b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_START) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* read command (10b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_READ) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* send address A9 ~ A0 */ - op = ADM_SW_BIT_MASK_10; - while (op) - { - if (op & addr) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* turnaround bits */ - op = ADM_SW_BIT_MASK_2; - ifx_mdio_hi(); - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - udelay(ADM_SW_MDC_DOWN_DELAY); - - /* set MDIO pin to input mode */ - ifx_mdio_mode(ADM_SW_MDIO_INPUT); - - /* start read data */ - *dat = 0; -//adm6996i op = ADM_SW_BIT_MASK_32; - op = ADM_SW_BIT_MASK_16;//adm6996i - while (op) - { - *dat <<= 1; - if (ifx_sw_mdio_readbit()) *dat |= 1; - ifx_sw_mdc_toggle(); - - op >>= 1; - } - - /* set MDIO to output mode */ - ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); - - /* dummy clock */ - op = ADM_SW_BIT_MASK_4; - ifx_mdio_lo(); - while(op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - ifx_mdc_lo(); - ifx_mdio_lo(); - ifx_mdcs_hi(); - - /* EEPROM registers */ -//adm6996i if (!(addr & 0x200)) -//adm6996i { -//adm6996i if (addr % 2) -//adm6996i *dat >>= 16; -//adm6996i else -//adm6996i *dat &= 0xffff; -//adm6996i } - - return 0; -} -//adm6996 -static int ifx_sw_read_adm6996l(unsigned int addr, unsigned int *dat) -{ - unsigned int op; - - ifx_gpio_init(); - - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_lo(); - - udelay(ADM_SW_CS_DELAY); - - /* preamble, 32 bit 1 */ - ifx_mdio_hi(); - op = ADM_SW_BIT_MASK_32; - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* command start (01b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_START) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* read command (10b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_READ) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* send address A9 ~ A0 */ - op = ADM_SW_BIT_MASK_10; - while (op) - { - if (op & addr) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* turnaround bits */ - op = ADM_SW_BIT_MASK_2; - ifx_mdio_hi(); - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - udelay(ADM_SW_MDC_DOWN_DELAY); - - /* set MDIO pin to input mode */ - ifx_mdio_mode(ADM_SW_MDIO_INPUT); - - /* start read data */ - *dat = 0; - op = ADM_SW_BIT_MASK_32; - while (op) - { - *dat <<= 1; - if (ifx_sw_mdio_readbit()) *dat |= 1; - ifx_sw_mdc_toggle(); - - op >>= 1; - } - - /* set MDIO to output mode */ - ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); - - /* dummy clock */ - op = ADM_SW_BIT_MASK_4; - ifx_mdio_lo(); - while(op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - ifx_mdc_lo(); - ifx_mdio_lo(); - ifx_mdcs_hi(); - - /* EEPROM registers */ - if (!(addr & 0x200)) - { - if (addr % 2) - *dat >>= 16; - else - *dat &= 0xffff; - } - - return 0; -} - -static int ifx_sw_read(unsigned int addr, unsigned int *dat) -{ -#ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin - ifx_sw_read_adm6996i_smi(addr,dat); -#else - if (adm6996_mode==adm6996i) ifx_sw_read_adm6996i(addr,dat); - else ifx_sw_read_adm6996l(addr,dat); -#endif - return 0; - -} - -/* - write register to ADM6996 eeprom registers -*/ -//for adm6996i -start -#ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin -static int ifx_sw_write_adm6996i_smi(unsigned int addr, unsigned int dat) -{ - - AMAZON_SW_REG(AMAZON_SW_MDIO_ACC) = ((addr<<16)&0x3ff0000)|dat|0x80000000; - while ((AMAZON_SW_REG(AMAZON_SW_MDIO_ACC))&0x80000000){}; - - return 0; - -} -#endif //ADM6996_MDC_MDIO_MODE //000001.joelin - -static int ifx_sw_write_adm6996i(unsigned int addr, unsigned int dat) -{ - unsigned int op; - - ifx_gpio_init(); - - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_lo(); - - udelay(ADM_SW_CS_DELAY); - - /* preamble, 32 bit 1 */ - ifx_mdio_hi(); - op = ADM_SW_BIT_MASK_32; - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* command start (01b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_START) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* write command (01b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_WRITE) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* send address A9 ~ A0 */ - op = ADM_SW_BIT_MASK_10; - while (op) - { - if (op & addr) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* turnaround bits */ - op = ADM_SW_BIT_MASK_2; - ifx_mdio_hi(); - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - udelay(ADM_SW_MDC_DOWN_DELAY); - - /* set MDIO pin to output mode */ - ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); - - - /* start write data */ - op = ADM_SW_BIT_MASK_16; - while (op) - { - if (op & dat) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_toggle(); - op >>= 1; - } - - // /* set MDIO to output mode */ - // ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); - - /* dummy clock */ - op = ADM_SW_BIT_MASK_4; - ifx_mdio_lo(); - while(op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - ifx_mdc_lo(); - ifx_mdio_lo(); - ifx_mdcs_hi(); - - /* EEPROM registers */ -//adm6996i if (!(addr & 0x200)) -//adm6996i { -//adm6996i if (addr % 2) -//adm6996i *dat >>= 16; -//adm6996i else -//adm6996i *dat &= 0xffff; -//adm6996i } - - return 0; -} -//for adm6996i-end -static int ifx_sw_write_adm6996l(unsigned int addr, unsigned int dat) -{ - unsigned int op; - - ifx_gpio_init(); - - /* enable write */ - ifx_sw_eeprom_write_enable(); - - /* chip select */ - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - /* issue write command */ - /* start bit */ - ifx_mdio_hi(); - ifx_sw_mdc_pulse(); - - /* EEPROM write command */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_EEPROM_WRITE) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* send address A7 ~ A0 */ - op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 1); - - while (op) - { - if (op & addr) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_toggle(); - op >>= 1; - } - - /* start write data */ - op = ADM_SW_BIT_MASK_16; - while (op) - { - if (op & dat) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_toggle(); - op >>= 1; - } - - /* disable cs & wait 1 clock */ - ifx_mdcs_lo(); - udelay(ADM_SW_CS_DELAY); - ifx_sw_mdc_toggle(); - - ifx_sw_eeprom_write_disable(); - - return 0; -} - -static int ifx_sw_write(unsigned int addr, unsigned int dat) -{ -#ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin - ifx_sw_write_adm6996i_smi(addr,dat); -#else //000001.joelin - if (adm6996_mode==adm6996i) ifx_sw_write_adm6996i(addr,dat); - else ifx_sw_write_adm6996l(addr,dat); -#endif //000001.joelin - return 0; -} - -/* - do switch PHY reset -*/ -int ifx_sw_reset(void) -{ - /* reset PHY */ - ifx_sw_write(ADM_SW_PHY_RESET, 0); - - return 0; -} - -/* 509201:linmars start */ -#if 0 -/* - check port status -*/ -int ifx_check_port_status(int port) -{ - unsigned int val; - - if ((port < 0) || (port > ADM_SW_MAX_PORT_NUM)) - { - ifx_printf(("error on port number (%d)!!\n", port)); - return -1; - } - - ifx_sw_read(ifx_sw_conf[port], &val); - if (ifx_sw_conf[port]%2) val >>= 16; - /* only 16bits are effective */ - val &= 0xFFFF; - - ifx_printf(("Port %d status (%.8x): \n", port, val)); - - if (val & ADM_SW_PORT_FLOWCTL) - ifx_printf(("\t802.3x flow control supported!\n")); - else - ifx_printf(("\t802.3x flow control not supported!\n")); - - if (val & ADM_SW_PORT_AN) - ifx_printf(("\tAuto negotiation ON!\n")); - else - ifx_printf(("\tAuto negotiation OFF!\n")); - - if (val & ADM_SW_PORT_100M) - ifx_printf(("\tLink at 100M!\n")); - else - ifx_printf(("\tLink at 10M!\n")); - - if (val & ADM_SW_PORT_FULL) - ifx_printf(("\tFull duplex!\n")); - else - ifx_printf(("\tHalf duplex!\n")); - - if (val & ADM_SW_PORT_DISABLE) - ifx_printf(("\tPort disabled!\n")); - else - ifx_printf(("\tPort enabled!\n")); - - if (val & ADM_SW_PORT_TOS) - ifx_printf(("\tTOS enabled!\n")); - else - ifx_printf(("\tTOS disabled!\n")); - - if (val & ADM_SW_PORT_PPRI) - ifx_printf(("\tPort priority first!\n")); - else - ifx_printf(("\tVLAN or TOS priority first!\n")); - - if (val & ADM_SW_PORT_MDIX) - ifx_printf(("\tAuto MDIX!\n")); - else - ifx_printf(("\tNo auto MDIX\n")); - - ifx_printf(("\tPVID: %d\n", \ - ((val >> ADM_SW_PORT_PVID_SHIFT)&ifx_sw_bits[ADM_SW_PORT_PVID_BITS]))); - - return 0; -} -/* - initialize a VLAN - clear all VLAN bits -*/ -int ifx_sw_vlan_init(int vlanid) -{ - ifx_sw_write(ADM_SW_VLAN0_CONF + vlanid, 0); - - return 0; -} - -/* - add a port to certain vlan -*/ -int ifx_sw_vlan_add(int port, int vlanid) -{ - int reg = 0; - - if ((port < 0) || (port > ADM_SW_MAX_PORT_NUM) || (vlanid < 0) || - (vlanid > ADM_SW_MAX_VLAN_NUM)) - { - ifx_printf(("Port number or VLAN number ERROR!!\n")); - return -1; - } - ifx_sw_read(ADM_SW_VLAN0_CONF + vlanid, ®); - reg |= (1 << ifx_sw_vlan_port[port]); - ifx_sw_write(ADM_SW_VLAN0_CONF + vlanid, reg); - - return 0; -} - -/* - delete a given port from certain vlan -*/ -int ifx_sw_vlan_del(int port, int vlanid) -{ - unsigned int reg = 0; - - if ((port < 0) || (port > ADM_SW_MAX_PORT_NUM) || (vlanid < 0) || (vlanid > ADM_SW_MAX_VLAN_NUM)) - { - ifx_printf(("Port number or VLAN number ERROR!!\n")); - return -1; - } - ifx_sw_read(ADM_SW_VLAN0_CONF + vlanid, ®); - reg &= ~(1 << ifx_sw_vlan_port[port]); - ifx_sw_write(ADM_SW_VLAN0_CONF + vlanid, reg); - - return 0; -} - -/* - default VLAN setting - - port 0~3 as untag port and PVID = 1 - VLAN1: port 0~3 and port 5 (MII) -*/ -static int ifx_sw_init(void) -{ - ifx_printf(("Setting default ADM6996 registers... \n")); - - /* MAC clone, 802.1q based VLAN */ - ifx_sw_write(ADM_SW_VLAN_MODE, 0xff30); - /* auto MDIX, PVID=1, untag */ - ifx_sw_write(ADM_SW_PORT0_CONF, 0x840f); - ifx_sw_write(ADM_SW_PORT1_CONF, 0x840f); - ifx_sw_write(ADM_SW_PORT2_CONF, 0x840f); - ifx_sw_write(ADM_SW_PORT3_CONF, 0x840f); - /* auto MDIX, PVID=2, untag */ - ifx_sw_write(ADM_SW_PORT5_CONF, 0x880f); - /* port 0~3 & 5 as VLAN1 */ - ifx_sw_write(ADM_SW_VLAN0_CONF+1, 0x0155); - - return 0; -} -#endif -/* 509201:linmars end */ - -int adm_open(struct inode *node, struct file *filp) -{ - MOD_INC_USE_COUNT; - return 0; -} - -ssize_t adm_read(struct file *filep, char *buf, size_t count, loff_t *ppos) -{ - return count; -} - -ssize_t adm_write(struct file *filep, const char *buf, size_t count, loff_t *ppos) -{ - return count; -} - -/* close */ -int adm_release(struct inode *inode, struct file *filp) -{ - MOD_DEC_USE_COUNT; - return 0; -} - -/* IOCTL function */ -int adm_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long args) -{ - PREGRW uREGRW; - unsigned int rtval; - unsigned int val; //6996i - unsigned int control[6] ; //6996i - unsigned int status[6] ; //6996i - - PMACENTRY mMACENTRY;//adm6996i - PPROTOCOLFILTER uPROTOCOLFILTER ;///adm6996i - - if (_IOC_TYPE(cmd) != ADM_MAGIC) - { - printk("adm_ioctl: IOC_TYPE(%x) != ADM_MAGIC(%x)! \n", _IOC_TYPE(cmd), ADM_MAGIC); - return (-EINVAL); - } - - if(_IOC_NR(cmd) >= KEY_IOCTL_MAX_KEY) - { - printk(KERN_WARNING "adm_ioctl: IOC_NR(%x) invalid! \n", _IOC_NR(cmd)); - return (-EINVAL); - } - - switch (cmd) - { - case ADM_IOCTL_REGRW: - { - uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL); - rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW)); - if (rtval != 0) - { - printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n"); - return (-EFAULT); - } - - switch(uREGRW->mode) - { - case REG_READ: - uREGRW->value = 0x12345678;//inl(uREGRW->addr); - copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW)); - break; - case REG_WRITE: - //outl(uREGRW->value, uREGRW->addr); - break; - - default: - printk("No such Register Read/Write function!! \n"); - return (-EFAULT); - } - kfree(uREGRW); - break; - } - - case ADM_SW_IOCTL_REGRW: - { - unsigned int val = 0xff; - - uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL); - rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW)); - if (rtval != 0) - { - printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n"); - return (-EFAULT); - } - - switch(uREGRW->mode) - { - case REG_READ: - ifx_sw_read(uREGRW->addr, &val); - uREGRW->value = val; - copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW)); - break; - - case REG_WRITE: - ifx_sw_write(uREGRW->addr, uREGRW->value); - break; - default: - printk("No such Register Read/Write function!! \n"); - return (-EFAULT); - } - kfree(uREGRW); - break; - } -/* 509201:linmars start */ -#if 0 - case ADM_SW_IOCTL_PORTSTS: - for (rtval = 0; rtval < ADM_SW_MAX_PORT_NUM+1; rtval++) - ifx_check_port_status(rtval); - break; - case ADM_SW_IOCTL_INIT: - ifx_sw_init(); - break; -#endif -/* 509201:linmars end */ -//adm6996i - case ADM_SW_IOCTL_MACENTRY_ADD: - case ADM_SW_IOCTL_MACENTRY_DEL: - case ADM_SW_IOCTL_MACENTRY_GET_INIT: - case ADM_SW_IOCTL_MACENTRY_GET_MORE: - - - mMACENTRY = (PMACENTRY)kmalloc(sizeof(MACENTRY), GFP_KERNEL); - rtval = copy_from_user(mMACENTRY, (PMACENTRY)args, sizeof(MACENTRY)); - if (rtval != 0) - { - printk("ADM_SW_IOCTL_MACENTRY: copy from user FAILED!! \n"); - return (-EFAULT); - } - control[0]=(mMACENTRY->mac_addr[1]<<8)+mMACENTRY->mac_addr[0] ; - control[1]=(mMACENTRY->mac_addr[3]<<8)+mMACENTRY->mac_addr[2] ; - control[2]=(mMACENTRY->mac_addr[5]<<8)+mMACENTRY->mac_addr[4] ; - control[3]=(mMACENTRY->fid&0xf)+((mMACENTRY->portmap&0x3f)<<4); - if (((mMACENTRY->info_type)&0x01)) control[4]=(mMACENTRY->ctrl.info_ctrl)+0x1000; //static ,info control - else control[4]=((mMACENTRY->ctrl.age_timer)&0xff);//not static ,agetimer - if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) { - //initial the pointer to the first address - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - control[5]=0x030;//initial the first address - ifx_sw_write(0x11f,control[5]); - - - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - - } //if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) - if (cmd==ADM_SW_IOCTL_MACENTRY_ADD) control[5]=0x07;//create a new address - else if (cmd==ADM_SW_IOCTL_MACENTRY_DEL) control[5]=0x01f;//erased an existed address - else if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) - control[5]=0x02c;//search by the mac address field - - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - ifx_sw_write(0x11a,control[0]); - ifx_sw_write(0x11b,control[1]); - ifx_sw_write(0x11c,control[2]); - ifx_sw_write(0x11d,control[3]); - ifx_sw_write(0x11e,control[4]); - ifx_sw_write(0x11f,control[5]); - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - val=((val&0x7000)>>12);//result ,status5[14:12] - mMACENTRY->result=val; - - if (!val) { - printk(" Command OK!! \n"); - if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) { - ifx_sw_read(0x120,&(status[0])); - ifx_sw_read(0x121,&(status[1])); - ifx_sw_read(0x122,&(status[2])); - ifx_sw_read(0x123,&(status[3])); - ifx_sw_read(0x124,&(status[4])); - ifx_sw_read(0x125,&(status[5])); - - - mMACENTRY->mac_addr[0]=(status[0]&0x00ff) ; - mMACENTRY->mac_addr[1]=(status[0]&0xff00)>>8 ; - mMACENTRY->mac_addr[2]=(status[1]&0x00ff) ; - mMACENTRY->mac_addr[3]=(status[1]&0xff00)>>8 ; - mMACENTRY->mac_addr[4]=(status[2]&0x00ff) ; - mMACENTRY->mac_addr[5]=(status[2]&0xff00)>>8 ; - mMACENTRY->fid=(status[3]&0xf); - mMACENTRY->portmap=((status[3]>>4)&0x3f); - if (status[5]&0x2) {//static info_ctrl //status5[1]???? - mMACENTRY->ctrl.info_ctrl=(status[4]&0x00ff); - mMACENTRY->info_type=1; - } - else {//not static age_timer - mMACENTRY->ctrl.age_timer=(status[4]&0x00ff); - mMACENTRY->info_type=0; - } -//status5[13]???? mMACENTRY->occupy=(status[5]&0x02)>>1;//status5[1] - mMACENTRY->occupy=(status[5]&0x02000)>>13;//status5[13] ??? - mMACENTRY->bad=(status[5]&0x04)>>2;//status5[2] - }//if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) - - } - else if (val==0x001) - printk(" All Entry Used!! \n"); - else if (val==0x002) - printk(" Entry Not Found!! \n"); - else if (val==0x003) - printk(" Try Next Entry!! \n"); - else if (val==0x005) - printk(" Command Error!! \n"); - else - printk(" UnKnown Error!! \n"); - - copy_to_user((PMACENTRY)args, mMACENTRY,sizeof(MACENTRY)); - - break; - - case ADM_SW_IOCTL_FILTER_ADD: - case ADM_SW_IOCTL_FILTER_DEL: - case ADM_SW_IOCTL_FILTER_GET: - - uPROTOCOLFILTER = (PPROTOCOLFILTER)kmalloc(sizeof(PROTOCOLFILTER), GFP_KERNEL); - rtval = copy_from_user(uPROTOCOLFILTER, (PPROTOCOLFILTER)args, sizeof(PROTOCOLFILTER)); - if (rtval != 0) - { - printk("ADM_SW_IOCTL_FILTER_ADD: copy from user FAILED!! \n"); - return (-EFAULT); - } - - if(cmd==ADM_SW_IOCTL_FILTER_DEL) { //delete filter - uPROTOCOLFILTER->ip_p=00; //delet filter - uPROTOCOLFILTER->action=00; //delete filter - } //delete filter - - ifx_sw_read(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), &val);//rx68~rx6b,protocol filter0~7 - - if (((uPROTOCOLFILTER->protocol_filter_num)%2)==00){ - if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= val&0x00ff;//get filter ip_p - else val=(val&0xff00)|(uPROTOCOLFILTER->ip_p);//set filter ip_p - } - else { - if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= (val>>8);//get filter ip_p - else val=(val&0x00ff)|((uPROTOCOLFILTER->ip_p)<<8);//set filter ip_p - } - if(cmd!=ADM_SW_IOCTL_FILTER_GET) ifx_sw_write(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), val);//write rx68~rx6b,protocol filter0~7 - - ifx_sw_read(0x95, &val); //protocol filter action - if(cmd==ADM_SW_IOCTL_FILTER_GET) { - uPROTOCOLFILTER->action= ((val>>(uPROTOCOLFILTER->protocol_filter_num*2))&0x3);//get filter action - copy_to_user((PPROTOCOLFILTER)args, uPROTOCOLFILTER, sizeof(PROTOCOLFILTER)); - - } - else { - val=(val&(~(0x03<<(uPROTOCOLFILTER->protocol_filter_num*2))))|(((uPROTOCOLFILTER->action)&0x03)<<(uPROTOCOLFILTER->protocol_filter_num*2)); - // printk("%d----\n",val); - ifx_sw_write(0x95, val); //write protocol filter action - } - - break; -//adm6996i - - /* others */ - default: - return -EFAULT; - } - /* end of switch */ - return 0; -} - -/* Santosh: handle IGMP protocol filter ADD/DEL/GET */ -int adm_process_protocol_filter_request (unsigned int cmd, PPROTOCOLFILTER uPROTOCOLFILTER) -{ - unsigned int val; //6996i - - if(cmd==ADM_SW_IOCTL_FILTER_DEL) { //delete filter - uPROTOCOLFILTER->ip_p=00; //delet filter - uPROTOCOLFILTER->action=00; //delete filter - } //delete filter - - ifx_sw_read(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), &val);//rx68~rx6b,protocol filter0~7 - - if (((uPROTOCOLFILTER->protocol_filter_num)%2)==00){ - if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= val&0x00ff;//get filter ip_p - else val=(val&0xff00)|(uPROTOCOLFILTER->ip_p);//set filter ip_p - } - else { - if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= (val>>8);//get filter ip_p - else val=(val&0x00ff)|((uPROTOCOLFILTER->ip_p)<<8);//set filter ip_p - } - if(cmd!=ADM_SW_IOCTL_FILTER_GET) ifx_sw_write(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), val);//write rx68~rx6b,protocol filter0~7 - - ifx_sw_read(0x95, &val); //protocol filter action - if(cmd==ADM_SW_IOCTL_FILTER_GET) { - uPROTOCOLFILTER->action= ((val>>(uPROTOCOLFILTER->protocol_filter_num*2))&0x3);//get filter action - } - else { - val=(val&(~(0x03<<(uPROTOCOLFILTER->protocol_filter_num*2))))|(((uPROTOCOLFILTER->action)&0x03)<<(uPROTOCOLFILTER->protocol_filter_num*2)); - ifx_sw_write(0x95, val); //write protocol filter action - } - - return 0; -} - - -/* Santosh: function for MAC ENTRY ADD/DEL/GET */ - -int adm_process_mac_table_request (unsigned int cmd, PMACENTRY mMACENTRY) -{ - unsigned int rtval; - unsigned int val; //6996i - unsigned int control[6] ; //6996i - unsigned int status[6] ; //6996i - - // printk ("adm_process_mac_table_request: enter\n"); - - control[0]=(mMACENTRY->mac_addr[1]<<8)+mMACENTRY->mac_addr[0] ; - control[1]=(mMACENTRY->mac_addr[3]<<8)+mMACENTRY->mac_addr[2] ; - control[2]=(mMACENTRY->mac_addr[5]<<8)+mMACENTRY->mac_addr[4] ; - control[3]=(mMACENTRY->fid&0xf)+((mMACENTRY->portmap&0x3f)<<4); - - if (((mMACENTRY->info_type)&0x01)) control[4]=(mMACENTRY->ctrl.info_ctrl)+0x1000; //static ,info control - else control[4]=((mMACENTRY->ctrl.age_timer)&0xff);//not static ,agetimer - if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) { - //initial the pointer to the first address - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - control[5]=0x030;//initial the first address - ifx_sw_write(0x11f,control[5]); - - - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - - } //if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) - if (cmd==ADM_SW_IOCTL_MACENTRY_ADD) control[5]=0x07;//create a new address - else if (cmd==ADM_SW_IOCTL_MACENTRY_DEL) control[5]=0x01f;//erased an existed address - else if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) - control[5]=0x02c;//search by the mac address field - - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - ifx_sw_write(0x11a,control[0]); - ifx_sw_write(0x11b,control[1]); - ifx_sw_write(0x11c,control[2]); - ifx_sw_write(0x11d,control[3]); - ifx_sw_write(0x11e,control[4]); - ifx_sw_write(0x11f,control[5]); - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - val=((val&0x7000)>>12);//result ,status5[14:12] - mMACENTRY->result=val; - - if (!val) { - printk(" Command OK!! \n"); - if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) { - ifx_sw_read(0x120,&(status[0])); - ifx_sw_read(0x121,&(status[1])); - ifx_sw_read(0x122,&(status[2])); - ifx_sw_read(0x123,&(status[3])); - ifx_sw_read(0x124,&(status[4])); - ifx_sw_read(0x125,&(status[5])); - - - mMACENTRY->mac_addr[0]=(status[0]&0x00ff) ; - mMACENTRY->mac_addr[1]=(status[0]&0xff00)>>8 ; - mMACENTRY->mac_addr[2]=(status[1]&0x00ff) ; - mMACENTRY->mac_addr[3]=(status[1]&0xff00)>>8 ; - mMACENTRY->mac_addr[4]=(status[2]&0x00ff) ; - mMACENTRY->mac_addr[5]=(status[2]&0xff00)>>8 ; - mMACENTRY->fid=(status[3]&0xf); - mMACENTRY->portmap=((status[3]>>4)&0x3f); - if (status[5]&0x2) {//static info_ctrl //status5[1]???? - mMACENTRY->ctrl.info_ctrl=(status[4]&0x00ff); - mMACENTRY->info_type=1; - } - else {//not static age_timer - mMACENTRY->ctrl.age_timer=(status[4]&0x00ff); - mMACENTRY->info_type=0; - } -//status5[13]???? mMACENTRY->occupy=(status[5]&0x02)>>1;//status5[1] - mMACENTRY->occupy=(status[5]&0x02000)>>13;//status5[13] ??? - mMACENTRY->bad=(status[5]&0x04)>>2;//status5[2] - }//if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) - - } - else if (val==0x001) - printk(" All Entry Used!! \n"); - else if (val==0x002) - printk(" Entry Not Found!! \n"); - else if (val==0x003) - printk(" Try Next Entry!! \n"); - else if (val==0x005) - printk(" Command Error!! \n"); - else - printk(" UnKnown Error!! \n"); - - // printk ("adm_process_mac_table_request: Exit\n"); - return 0; -} - -/* Santosh: End of function for MAC ENTRY ADD/DEL*/ -struct file_operations adm_ops = -{ - read: adm_read, - write: adm_write, - open: adm_open, - release: adm_release, - ioctl: adm_ioctl -}; - -int adm_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data) -{ - int len = 0; - - len += sprintf(buf+len, " ************ Registers ************ \n"); - *eof = 1; - return len; -} - -int __init init_adm6996_module(void) -{ - unsigned int val = 000; - unsigned int val1 = 000; - - printk("Loading ADM6996 driver... \n"); - - /* if running on adm5120 */ - /* set GPIO 0~2 as adm6996 control pins */ - //outl(0x003f3f00, 0x12000028); - /* enable switch port 5 (MII) as RMII mode (5120MAC <-> 6996MAC) */ - //outl(0x18a, 0x12000030); - /* group adm5120 port 1 ~ 5 as VLAN0, port 5 & 6(CPU) as VLAN1 */ - //outl(0x417e, 0x12000040); - /* end adm5120 fixup */ -#ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin - register_chrdev(69, "adm6996", &adm_ops); - AMAZON_SW_REG(AMAZON_SW_MDIO_CFG) = 0x27be; - AMAZON_SW_REG(AMAZON_SW_EPHY) = 0xfc; - adm6996_mode=adm6996i; - ifx_sw_read(0xa0, &val); - ifx_sw_read(0xa1, &val1); - val=((val1&0x0f)<<16)|val; - printk ("\nADM6996 SMI Mode-"); - printk ("Chip ID:%5x \n ", val); -#else //000001.joelin - - AMAZON_SW_REG(AMAZON_SW_MDIO_CFG) = 0x2c50; - AMAZON_SW_REG(AMAZON_SW_EPHY) = 0xff; - - AMAZON_SW_REG(AMAZON_GPIO_P1_ALTSEL0) &= ~(GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - AMAZON_SW_REG(AMAZON_GPIO_P1_ALTSEL1) &= ~(GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - AMAZON_SW_REG(AMAZON_GPIO_P1_OD) |= (GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - - ifx_gpio_init(); - register_chrdev(69, "adm6996", &adm_ops); - mdelay(100); - - /* create proc entries */ - // create_proc_read_entry("admide", 0, NULL, admide_proc, NULL); - -//joelin adm6996i support start - adm6996_mode=adm6996i; - ifx_sw_read(0xa0, &val); - adm6996_mode=adm6996l; - ifx_sw_read(0x200, &val1); -// printk ("\n %0x \n",val1); - if ((val&0xfff0)==0x1020) { - printk ("\n ADM6996I .. \n"); - adm6996_mode=adm6996i; - } - else if ((val1&0xffffff00)==0x71000) {//71010 or 71020 - printk ("\n ADM6996LC .. \n"); - adm6996_mode=adm6996lc; - } - else { - printk ("\n ADM6996L .. \n"); - adm6996_mode=adm6996l; - } -#endif //ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin - - if ((adm6996_mode==adm6996lc)||(adm6996_mode==adm6996i)){ -#if 0 /* removed by MarsLin */ - ifx_sw_write(0x29,0xc000); - ifx_sw_write(0x30,0x0985); -#else - ifx_sw_read(0xa0, &val); - if (val == 0x1021) // for both 6996LC and 6996I, only AB version need the patch - ifx_sw_write(0x29, 0x9000); - ifx_sw_write(0x30,0x0985); -#endif - } -//joelin adm6996i support end - return 0; -} - -void __exit cleanup_adm6996_module(void) -{ - printk("Free ADM device driver... \n"); - - unregister_chrdev(69, "adm6996"); - - /* remove proc entries */ - // remove_proc_entry("admide", NULL); -} - -/* MarsLin, add start */ -#if defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT) || defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT_MODULE) - #define SET_BIT(reg, mask) reg |= (mask) - #define CLEAR_BIT(reg, mask) reg &= (~mask) - static int ifx_hw_reset(void) - { - CLEAR_BIT((*AMAZON_GPIO_P0_ALTSEL0),0x2000); - CLEAR_BIT((*AMAZON_GPIO_P0_ALTSEL1),0x2000); - SET_BIT((*AMAZON_GPIO_P0_OD),0x2000); - SET_BIT((*AMAZON_GPIO_P0_DIR), 0x2000); - CLEAR_BIT((*AMAZON_GPIO_P0_OUT), 0x2000); - mdelay(500); - SET_BIT((*AMAZON_GPIO_P0_OUT), 0x2000); - cleanup_adm6996_module(); - return init_adm6996_module(); - } - int (*adm6996_hw_reset)(void) = ifx_hw_reset; - EXPORT_SYMBOL(adm6996_hw_reset); - EXPORT_SYMBOL(adm6996_mode); - int (*adm6996_sw_read)(unsigned int addr, unsigned int *data) = ifx_sw_read; - EXPORT_SYMBOL(adm6996_sw_read); - int (*adm6996_sw_write)(unsigned int addr, unsigned int data) = ifx_sw_write; - EXPORT_SYMBOL(adm6996_sw_write); -#endif -/* MarsLin, add end */ - -/* Santosh: for IGMP proxy/snooping, Begin */ -EXPORT_SYMBOL (adm_process_mac_table_request); -EXPORT_SYMBOL (adm_process_protocol_filter_request); -/* Santosh: for IGMP proxy/snooping, End */ - -MODULE_DESCRIPTION("ADMtek 6996 Driver"); -MODULE_AUTHOR("Joe Lin "); -MODULE_LICENSE("GPL"); - -module_init(init_adm6996_module); -module_exit(cleanup_adm6996_module); - diff --git a/target/linux/amazon/files/drivers/char/amazon_mei.c b/target/linux/amazon/files/drivers/char/amazon_mei.c deleted file mode 100644 index 7efe52ed60..0000000000 --- a/target/linux/amazon/files/drivers/char/amazon_mei.c +++ /dev/null @@ -1,7918 +0,0 @@ -/* ============================================================================ - * Copyright (C) 2004 -Infineon Technologies AG. - * - * All rights reserved. - * ============================================================================ - * - *============================================================================ - * Licensed under GNU GPL v2 - * ============================================================================ - */ - - -/* =========================================================================== - * - * File Name: amazon_mei.c - * Author : Ou Ke - * - * =========================================================================== - * - * Project: Amazon - * - * =========================================================================== - * Contents:This file implements the MEI driver for Amazon ADSL/ADSL2+ - * controller. - * - * =========================================================================== - * References: - * - */ - - -/* =========================================================================== - * Revision History: - * 12/1/2005 : Ritesh Banerjee - * - Create a kernel thread kmibpoll to poll for periodic RFC 2662 - * and RFC 3440 counters. Removes the need for user space - * adsl_mibpoll_daemon and saves atleast 30KB of RAM. - * - * $Log$ - * =========================================================================== - */ - -/* - * =========================================================================== - * INCLUDE FILES - * =========================================================================== - */ -//000002:fchang 2005/6/2 joelin 04/27/2005 for pcm clock -//000003:fchang 2005/6/2 Henry added for Amazon-E support -//165001:henryhsu 2005/9/6 Modify for adsl firmware version 1.2.1.2.0.1 DATA_LED can't flash. -// 509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC -// 603221:tc.chen 2006/03/21 added APIs to support the WEB related parameters for ADSL Statistics - -#ifndef EXPORT_SYMTAB -#define EXPORT_SYMTAB -#endif -#define AMAZON_MEI_MIB_RFC3440 - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - -extern void mask_and_ack_amazon_irq(unsigned int irq_nr); - -#ifdef AMAZON_CHECK_LINK -//amazon_tpe.c -extern int (*adsl_link_notify)(int); -#endif //AMAZON_CHECK_LINK - -// for ARC memory access -#define WHILE_DELAY 20000 -#define AMAZON_DMA_DEBUG_MUTEX - - -//TODO -#undef DFE_LOOPBACK -#define ARC_READY_ACK - -static amazon_mei_mib * current_intvl; -static struct list_head interval_list; -static amazon_mei_mib * mei_mib; - -static int reboot_firsttime=1;//000002:fchang - - //PCM -#define PCM_CHANNEL_NUM 2 //1 rx, 1 tx -static pcm_data_struct pcm_data[PCM_CHANNEL_NUM]__attribute__ ((aligned(4))); //0=tx0, 1=rx0, 2=tx1, 3=rx1 -static u32 pcm_start_addr; -//#define PCM_HRT_TIME_HZ 4000 //?us -#define PCM_ACCESS_DEBUG -static int irqtimes=0; -#undef DATA_LED_ON_MODE -#define ADSL_LED_SUPPORT //joelin for adsl led -#ifdef ADSL_LED_SUPPORT -static int firmware_support_led=0; //joelin version check for adsl led -static int stop_led_module=0; //wakeup and clean led module -static int led_support_check=0; //1.1.2.7.1.1 -#endif //ADSL_LED_SUPPORT -#define IFX_DYING_GASP -#ifdef IFX_DYING_GASP -static wait_queue_head_t wait_queue_dying_gasp; //dying gasp -//struct tq_struct dying_gasp_task; //dying gasp -static wait_queue_head_t wait_queue_uas_poll; //joelin 04/16/2005 -static u16 unavailable_seconds=0; //joelin 04/16/2005 -static meidebug lop_debugwr; //dying gasp -#endif //IFX_DYING_GASP -static int dbg_int=0; -//#define DEBUG_ACCESS_DELAY for(dbg_int=0;dbg_int<100;dbg_int++){;} -#define DEBUG_ACCESS_DELAY -static u8 sampledata[512]; -static int firsttime[PCM_CHANNEL_NUM]={0,1}; -static int num_cmp[PCM_CHANNEL_NUM]={0,0}; -static int pcm_start_loc[PCM_CHANNEL_NUM]={0,0}; - - // for clearEoC -//#define MEI_CLREOC_BUFF_SIZE 512 //double the receive fifo size, bytes -//static u8 clreoc[MEI_CLREOC_BUFF_SIZE]__attribute__ ((aligned(4))); //buffer to hold clearEoC data in bytes -#undef AMAZON_CLEAR_EOC -#ifdef AMAZON_CLEAR_EOC -extern void ifx_push_eoc(struct sk_buff * pkt); -#endif -static int meiResetArc(void); -#define IFX_POP_EOC_DONE 0 -#define IFX_POP_EOC_FAIL -1 -static struct list_head clreoc_list; -static amazon_clreoc_pkt * clreoc_pkt; -#define CLREOC_BUFF_SIZE 12 //number of clreoc commands being buffered -//static int clreoc_wr=0; -//static int clreoc_rd=0; //used to control clreoc circular buffer -static wait_queue_head_t wait_queue_clreoc; -#ifdef ADSL_LED_SUPPORT -static wait_queue_head_t wait_queue_led; //adsl led -static wait_queue_head_t wait_queue_led_polling;// adsl led -struct tq_struct led_task; // adsl led -static DECLARE_TASK_QUEUE(tq_ifx_led); // task -int adsl_led_flash_task(void *ptr); // adsl led -#endif //ADSL_LED_SUPPORT -static void * clreoc_command_pkt=NULL; -static int clreoc_max_tx_len=0; - -// 603221:tc.chen start -#define ME_HDLC_IDLE 0 -#define ME_HDLC_INVALID_MSG 1 -#define ME_HDLC_MSG_QUEUED 2 -#define ME_HDLC_MSG_SENT 3 -#define ME_HDLC_RESP_RCVD 4 -#define ME_HDLC_RESP_TIMEOUT 5 -#define ME_HDLC_RX_BUF_OVERFLOW 6 -#define ME_HDLC_UNRESOLVED 1 -#define ME_HDLC_RESOLVED 2 -// 603221:tc.chen end - -#ifdef LOCK_RETRY -static int reboot_lock=0; -#endif - -static mib_previous_read mib_pread={0,0,0,0,0,0,0,0,0,0,0,0}; -static mib_flags_pretime mib_pflagtime;// initialized when module loaded - - static u32 ATUC_PERF_LOFS=0; - static u32 ATUC_PERF_LOSS=0; - static u32 ATUC_PERF_ESS=0; - static u32 ATUC_PERF_INITS=0; - static u32 ATUR_PERF_LOFS=0; - static u32 ATUR_PERF_LOSS=0; - static u32 ATUR_PERF_LPR=0; - static u32 ATUR_PERF_ESS=0; - static u32 ATUR_CHAN_RECV_BLK=0; - static u32 ATUR_CHAN_TX_BLK=0; - static u32 ATUR_CHAN_CORR_BLK=0; - static u32 ATUR_CHAN_UNCORR_BLK=0; - //RFC-3440 - static u32 ATUC_PERF_STAT_FASTR=0; - static u32 ATUC_PERF_STAT_FAILED_FASTR=0; - static u32 ATUC_PERF_STAT_SESL=0; - static u32 ATUC_PERF_STAT_UASL=0; - static u32 ATUR_PERF_STAT_SESL=0; - static u32 ATUR_PERF_STAT_UASL=0; - - static adslChanPrevTxRate PrevTxRate={0,0}; - static adslPhysCurrStatus CurrStatus={0,0}; - static ChanType chantype={0,0}; - static adslLineAlarmConfProfileEntry AlarmConfProfile={"No Name\0",0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}; -// 603221:tc.chen start - static adslFarEndPerfStats FarendStatsData; - struct timeval FarendData_acquire_time={0}; - static u32 adsl_mode,adsl_mode_extend; // adsl mode : adsl/ 2/ 2+ - static adslInitStats AdslInitStatsData; -//603221:tc.chen end -static u32 loop_diagnostics_mode=0; -static wait_queue_head_t wait_queue_loop_diagnostic; -#ifdef AMAZON_MEI_MIB_RFC3440 - static adslLineAlarmConfProfileExtEntry AlarmConfProfileExt={"No Name\0",0,0,0,0,0,0}; -#endif - -static int showtime=0; -static int loop_diagnostics_completed=0; -////////////////////////////////////////////////////////////////////////////////// -static int phy_mei_net_init(struct net_device * dev); -static int interleave_mei_net_init(struct net_device * dev); -static int fast_mei_net_init(struct net_device * dev); -static struct net_device_stats * phy_mei_net_get_stats(struct net_device * dev); -static struct net_device_stats * interleave_mei_net_get_stats(struct net_device * dev); -static struct net_device_stats * fast_mei_net_get_stats(struct net_device * dev); - -typedef struct mei_priv{ - struct net_device_stats stats; -}mei_priv; - -static struct net_device phy_mei_net = { init: phy_mei_net_init, name: "MEI_PHY"}; -static struct net_device interleave_mei_net = { init: interleave_mei_net_init, name: "MEI_INTL"}; -static struct net_device fast_mei_net = { init: fast_mei_net_init, name: "MEI_FAST"}; -/////////////////////////////////////////////////////////////////////////////////// - -static int major=AMAZON_MEI_MAJOR; - -static struct semaphore mei_sema; - -// Mei to ARC CMV count, reply count, ARC Indicator count -static int indicator_count=0; -static int cmv_count=0; -static int reply_count=0; -static u16 Recent_indicator[MSG_LENGTH]; - -// Used in interrupt handler as flags -static int arcmsgav=0; -static int cmv_reply=0; -static int cmv_waiting=0; - -#define PROC_ITEMS 8 - -long mei_debug_mode = 0; //509221:tc.chen for adsl firmware debug - -// to wait for arc cmv reply, sleep on wait_queue_arcmsgav; -static wait_queue_head_t wait_queue_arcmsgav; -static wait_queue_head_t wait_queue_codeswap; -static wait_queue_head_t wait_queue_mibdaemon; -static wait_queue_head_t wait_queue_reboot; -static u32 * image_buffer=NULL; // holding adsl firmware image -static u16 RxMessage[MSG_LENGTH]__attribute__ ((aligned(4))); -static u16 TxMessage[MSG_LENGTH]__attribute__ ((aligned(4))); -static u32 * mei_arc_swap_buff=NULL; // holding swap pages -static ARC_IMG_HDR * img_hdr; -static int reboot_flag; - -#ifdef DFE_LOOPBACK -#include "arc_pm.h" -#endif - - -///////////////// net device /////////////////////////////////////////////////// -static int phy_mei_net_init(struct net_device * dev) -{ - //ether_setup(dev); - dev->get_stats = phy_mei_net_get_stats; - dev->ip_ptr = NULL; - dev->type = 94; - -// dev->mtu=12345; - dev->flags=IFF_UP; - - dev->priv = kmalloc(sizeof(struct mei_priv), GFP_KERNEL); - if(dev->priv == NULL) - return -ENOMEM; - memset(dev->priv, 0, sizeof(struct mei_priv)); - return 0; -} - -static int interleave_mei_net_init(struct net_device * dev) -{ - //ether_setup(dev); - dev->get_stats = interleave_mei_net_get_stats; - dev->ip_ptr = NULL; - dev->type = 124; - dev->flags=IFF_UP; - dev->priv = kmalloc(sizeof(struct mei_priv), GFP_KERNEL); - if(dev->priv == NULL) - return -ENOMEM; - memset(dev->priv, 0, sizeof(struct mei_priv)); - return 0; -} - -static int fast_mei_net_init(struct net_device * dev) -{ - //ether_setup(dev); - dev->get_stats = fast_mei_net_get_stats; - dev->ip_ptr = NULL; - dev->type = 125; - dev->flags=IFF_UP; - dev->priv = kmalloc(sizeof(struct mei_priv), GFP_KERNEL); - if(dev->priv == NULL) - return -ENOMEM; - memset(dev->priv, 0, sizeof(struct mei_priv)); - return 0; -} - -static struct net_device_stats * phy_mei_net_get_stats(struct net_device * dev) -{ - struct mei_priv * priv; - priv = (struct mei_priv *)dev->priv; - // update statistics - (priv->stats).rx_packets = ATUR_CHAN_RECV_BLK; - (priv->stats).tx_packets = ATUR_CHAN_TX_BLK; - (priv->stats).rx_errors = ATUR_CHAN_CORR_BLK + ATUR_CHAN_UNCORR_BLK; - (priv->stats).rx_dropped = ATUR_CHAN_UNCORR_BLK; - - return &(priv->stats); -} - -static struct net_device_stats * interleave_mei_net_get_stats(struct net_device * dev) -{ - struct mei_priv * priv; - priv = (struct mei_priv *)dev->priv; - // update statistics - (priv->stats).rx_packets = ATUR_CHAN_RECV_BLK; - (priv->stats).tx_packets = ATUR_CHAN_TX_BLK; - (priv->stats).rx_errors = ATUR_CHAN_CORR_BLK + ATUR_CHAN_UNCORR_BLK; - (priv->stats).rx_dropped = ATUR_CHAN_UNCORR_BLK; - - return &(priv->stats); -} - -static struct net_device_stats * fast_mei_net_get_stats(struct net_device * dev) -{ - struct mei_priv * priv; - priv = (struct mei_priv *)dev->priv; - // update statistics - (priv->stats).rx_packets = ATUR_CHAN_RECV_BLK; - (priv->stats).tx_packets = ATUR_CHAN_TX_BLK; - (priv->stats).rx_errors = ATUR_CHAN_CORR_BLK + ATUR_CHAN_UNCORR_BLK; - (priv->stats).rx_dropped = ATUR_CHAN_UNCORR_BLK; - - return &(priv->stats); -} -///////////////// mei access Rd/Wr methods /////////////////////////////////////////////////// -void meiLongwordWrite(u32 ul_address, u32 ul_data) -{ - *((volatile u32 *)ul_address) = ul_data; - asm("SYNC"); - return; -} // end of "meiLongwordWrite(..." - -void meiLongwordRead(u32 ul_address, u32 *pul_data) -{ - *pul_data = *((volatile u32 *)ul_address); - asm("SYNC"); - return; -} // end of "meiLongwordRead(..." - -MEI_ERROR meiDMAWrite(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( destaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the write transfer address - meiLongwordWrite(MEI_XFR_ADDR, destaddr); - - // Write the data pushed across DMA - while (databuffsize--) - { - temp = *p; - if(databuff==(u32 *)TxMessage) // swap half word - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16); - meiLongwordWrite(MEI_DATA_XFR, temp); - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMAWrite(..." - -MEI_ERROR meiDMAWrite_16(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( destaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the write transfer address - meiLongwordWrite(MEI_XFR_ADDR, destaddr); - - // Write the data pushed across DMA - while (databuffsize--) - { - temp = *p; - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);//swap half word - meiLongwordWrite(MEI_DATA_XFR, temp); - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMAWrite_16(..." - -MEI_ERROR meiDMAWrite_8(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( destaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the write transfer address - meiLongwordWrite(MEI_XFR_ADDR, destaddr); - - // Write the data pushed across DMA - while (databuffsize--) - { - temp = *p; - temp = ((temp & 0xff)<<24) + ((temp & 0xff00)<<8)+ ((temp & 0xff0000)>>8)+ ((temp & 0xff000000)>>24);//swap byte - meiLongwordWrite(MEI_DATA_XFR, temp); - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMAWrite_8(..." - -MEI_ERROR meiDMARead(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( srcaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the read transfer address - meiLongwordWrite(MEI_XFR_ADDR, srcaddr); - - // Read the data popped across DMA - while (databuffsize--) - { - meiLongwordRead(MEI_DATA_XFR, &temp); - if(databuff==(u32 *)RxMessage) // swap half word - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16); - *p=temp; - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMARead(..." - -MEI_ERROR meiDMARead_16(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( srcaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the read transfer address - meiLongwordWrite(MEI_XFR_ADDR, srcaddr); - - // Read the data popped across DMA - while (databuffsize--) - { - meiLongwordRead(MEI_DATA_XFR, &temp); - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16); - *p=temp; - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMARead_16(..." - -MEI_ERROR meiDMARead_8(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( srcaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the read transfer address - meiLongwordWrite(MEI_XFR_ADDR, srcaddr); - - // Read the data popped across DMA - while (databuffsize--) - { - meiLongwordRead(MEI_DATA_XFR, &temp); - temp = ((temp & 0xff)<<24) + ((temp & 0xff00)<<8)+ ((temp & 0xff0000)>>8)+ ((temp & 0xff000000)>>24);//swap byte - *p=temp; - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMARead_8(..." - -void meiPollForDbgDone(void) -{ - u32 query = 0; - int i=0; - while (i>8)+ ((temp & 0xff000000)>>24);//swap byte - meiLongwordWrite(MEI_DEBUG_DATA, temp); - DEBUG_ACCESS_DELAY; - meiPollForDbgDone(); - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugWrite_8(..." - -MEI_ERROR meiDebugRead_8(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP2_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and read the data - address = srcaddr; - buffer = databuff; - for (i=0; i>8)+ ((temp & 0xff000000)>>24);//swap byte - *buffer=temp; - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugRead_8(..." - -MEI_ERROR meiDebugWrite_16(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and write the data - address = destaddr; - buffer = databuff; - for (i=0; i < databuffsize; i++) - { - meiLongwordWrite(MEI_DEBUG_WAD, address); - DEBUG_ACCESS_DELAY; - temp=*buffer; - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);//swap half word - meiLongwordWrite(MEI_DEBUG_DATA, temp); - DEBUG_ACCESS_DELAY; - meiPollForDbgDone(); - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugWrite_16(..." - -MEI_ERROR meiDebugRead_16(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP2_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and read the data - address = srcaddr; - buffer = databuff; - for (i=0; i>16);//swap half word - *buffer=temp; - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugRead_16(..." - -MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and write the data - address = destaddr; - buffer = databuff; - for (i=0; i < databuffsize; i++) - { - meiLongwordWrite(MEI_DEBUG_WAD, address); - DEBUG_ACCESS_DELAY; - temp=*buffer; - meiLongwordWrite(MEI_DEBUG_DATA, temp); - DEBUG_ACCESS_DELAY; - meiPollForDbgDone(); - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugWrite(..." - -MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP2_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and read the data - address = srcaddr; - buffer = databuff; - for (i=0; icount; boot_loop++) - { - if( img_hdr->page[boot_loop].p_size & BOOT_FLAG) - { - page_size = meiGetPage( boot_loop, GET_PROG, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( page_size > 0) - { - meiDMAWrite(dest_addr, mei_arc_swap_buff, page_size); - } - } - if( img_hdr->page[boot_loop].d_size & BOOT_FLAG) - { - page_size = meiGetPage( boot_loop, GET_DATA, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( page_size > 0) - { - meiDMAWrite( dest_addr, mei_arc_swap_buff, page_size); - } - } - } -#ifdef AMAZON_MEI_DEBUG_ON -// printk("\n\n pages downloaded"); -#endif - return MEI_SUCCESS; - -} // end of "meiDownloadBootCode(..." - -MEI_ERROR meiRunArc(void) -{ - u32 arc_control_mode = 0x0; - u32 arc_debug_addr = 0x0; - u32 arc_debug_data = 0x0; - - // Switch arc control from JTAG mode to MEI mode- write '1' to bit0 - meiLongwordRead(MEI_CONTROL, &arc_control_mode); - arc_control_mode |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, arc_control_mode); - - // Write arc aux reg access mask (0x0) into debug addr decode reg - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_AUX_MASK); - - // Write arc status aux reg addr (0x0) into debug read addr reg - meiLongwordWrite(MEI_DEBUG_RAD, arc_debug_addr); - meiPollForDbgDone(); - - // Read debug data reg and save content - meiLongwordRead(MEI_DEBUG_DATA, &arc_debug_data); - - // Write arc status aux reg addr (0x0) into debug write addr reg - meiLongwordWrite(MEI_DEBUG_WAD, arc_debug_addr); - - // Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared) - arc_debug_data &= ~(BIT25); - meiLongwordWrite(MEI_DEBUG_DATA, arc_debug_data); - meiPollForDbgDone(); - - // Switch arc control from MEI mode to JTAG mode- write '0' to bit0 - meiLongwordRead(MEI_CONTROL, &arc_control_mode); - arc_control_mode &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, arc_control_mode); - - // Enable mask for arc codeswap interrupts - meiMailboxInterruptsEnable(); - - // Return - return MEI_SUCCESS; - -} // end of "meiActivate(..." - -int meiGetPage( u32 Page, u32 data, u32 MaxSize, u32 *Buffer, u32 *Dest) -{ - u32 size; - u32 i; - u32 *p; - - if( Page > img_hdr->count) - return -2; - - /* - ** Get program or data size, depending on "data" flag - */ - size = (data == GET_DATA) ? img_hdr->page[ Page].d_size : img_hdr->page[ Page].p_size; - - size &= BOOT_FLAG_MASK; // Clear boot bit! - if( size > MaxSize) - return -1; - - if( size == 0) - return 0; - /* - ** Get program or data offset, depending on "data" flag - */ - i = data ? img_hdr->page[ Page].d_offset : img_hdr->page[ Page].p_offset; - - /* - ** Copy data/program to buffer - */ - - i /= 4; // Adjust offset for byte-to-UINT for array operation - - p = (u32 *)img_hdr + i; - for(i = 0; i < size; i++) - Buffer[i] = *p++; - /* - ** Pass back data/program destination address - */ - *Dest = data ? img_hdr->page[Page].d_dest : img_hdr->page[Page].p_dest; - - return size; -} - -MEI_ERROR meiCMV(u16 * request, int reply) // write cmv to arc, if reply needed, wait for reply -{ - MEI_ERROR meierror; - wait_queue_t wait; - - cmv_reply=reply; - - meierror = meiMailboxWrite(request, MSG_LENGTH); - - if(meierror != MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n MailboxWrite Fail."); -#endif - return meierror; - } - else{ - cmv_count++; - } - - if(cmv_reply == NO_REPLY) - return MEI_SUCCESS; - - init_waitqueue_entry(&wait, current); - add_wait_queue(&wait_queue_arcmsgav, &wait); - set_current_state(TASK_INTERRUPTIBLE); -// cmv_waiting=1; - - if(arcmsgav==1){ - set_current_state(TASK_RUNNING); - remove_wait_queue(&wait_queue_arcmsgav, &wait); - } - else{ - schedule_timeout(CMV_TIMEOUT); - remove_wait_queue(&wait_queue_arcmsgav, &wait); - } - if(arcmsgav==0){//CMV_timeout - cmv_waiting=0; - arcmsgav=0; -#ifdef AMAZON_MEI_DEBUG_ON - printk("\nmeiCMV: MEI_MAILBOX_TIMEOUT\n"); -#endif - return MEI_MAILBOX_TIMEOUT; - } - else{ - arcmsgav=0; - reply_count++; - return MEI_SUCCESS; - } -} - -//TODO, for loopback test -#ifdef DFE_LOOPBACK -#define mte_reg_base (0x4800*4+0x20000) - -/* Iridia Registers Address Constants */ -#define MTE_Reg(r) (int)(mte_reg_base + (r*4)) - -#define IT_AMODE MTE_Reg(0x0004) - - -#define OMBOX_BASE 0x15F80 -#define IMBOX_BASE 0x15FC0 - -#define TIMER_DELAY (1024) -#define BC0_BYTES (32) -#define BC1_BYTES (30) -#define NUM_MB (12) -#define TIMEOUT_VALUE 2000 - -void BFMWait (u32 cycle) { - u32 i; - for (i = 0 ; i< cycle ; i++); -} - -void WriteRegLong(u32 addr, u32 data){ - //printk("[%8x] <= %8x \n\n", addr, data); - *((volatile u32 *)(addr)) = data; -} - -u32 ReadRegLong (u32 addr) { - u32 rd_val; - - rd_val = *((volatile u32 *)(addr)); - //printk("[%8x] => %8x \n\n", addr, rd_val); - return rd_val; - -} - -/* This routine writes the mailbox with the data in an input array */ -void WriteMbox(u32 *mboxarray,u32 size) { - u32 i; - - WriteRegLong(MEI_XFR_ADDR,IMBOX_BASE); - for (i=0;if_dentry->d_inode)->i_ino; - char outputbuf[64]; - int count=0; - int i; - u32 version=0; - reg_entry_t* current_reg=NULL; - - for (i=0;iflag == (int *) 8){ - ///proc/mei/version - //format: - //Firmware version: major.minor.sub_version.int_version.rel_state.spl_appl - //Firmware Date Time Code: date/month min:hour - if (*ppos>0) /* Assume reading completed in previous read*/ - return 0; // indicates end of file - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - //if (indicator_count != 1){ - if (indicator_count < 1){ - up(&mei_sema); - return -EAGAIN; - } - //major:bits 0-7 - //minor:bits 8-15 - makeCMV(H2D_CMV_READ, INFO, 54, 0, 1, NULL); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#if 0 -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n WINHOST CMV fail"); -#endif -#endif - up(&mei_sema); - return -EIO; - } - version = RxMessage[4]; - count = sprintf(outputbuf, "%d.%d.",(version)&0xff,(version>>8)&0xff); - - //sub_version:bits 4-7 - //int_version:bits 0-3 - //spl_appl:bits 8-13 - //rel_state:bits 14-15 - makeCMV(H2D_CMV_READ, INFO, 54, 1, 1, NULL); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#if 0 -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n WINHOST CMV fail"); -#endif -#endif - up(&mei_sema); - return -EFAULT; - } - version =RxMessage[4]; - count += sprintf(outputbuf+count, "%d.%d.%d.%d", - (version>>4)&0xf, - version&0xf, - (version>>14)&0x3, - (version>>8)&0x3f); -#ifdef ADSL_LED_SUPPORT -// version check -start for adsl led - if ((((version>>4)&0xf)==2)&&((version&0xf)>=3)&&((version&0xf)<7)) firmware_support_led=1; - else if ((((version>>4)&0xf)==2)&&((version&0xf)>=7)) firmware_support_led=2; - else if (((version>>4)&0xf)>2) firmware_support_led=2; - -//165001:henryhsu:20050906:Modify for adsl firmware version 1.2.1.2.0.1 DATA_LED can't flash. - //else firmware_support_led=0; - else firmware_support_led=2; -//165001 - - -// version check -end -#endif - //Date:bits 0-7 - //Month:bits 8-15 - makeCMV(H2D_CMV_READ, INFO, 55, 0, 1, NULL); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#if 0 -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n WINHOST CMV fail"); -#endif -#endif - up(&mei_sema); - return -EIO; - } - version = RxMessage[4]; - - //Hour:bits 0-7 - //Minute:bits 8-15 - makeCMV(H2D_CMV_READ, INFO, 55, 1, 1, NULL); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#if 0 -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n WINHOST CMV fail"); -#endif -#endif - up(&mei_sema); - return -EFAULT; - } - version += (RxMessage[4]<<16); - count += sprintf(outputbuf+count, " %d/%d %d:%d\n" - ,version&0xff - ,(version>>8)&0xff - ,(version>>25)&0xff - ,(version>>16)&0xff); - - up(&mei_sema); - - *ppos+=count; - }else if(current_reg->flag != (int *)Recent_indicator){ - if (*ppos>0) /* Assume reading completed in previous read*/ - return 0; // indicates end of file - count = sprintf(outputbuf, "0x%08X\n\n", *(current_reg->flag)); - *ppos+=count; - if (count>nbytes) /* Assume output can be read at one time */ - return -EINVAL; - }else{ - if((int)(*ppos)/((int)7)==16) - return 0; // indicate end of the message - count = sprintf(outputbuf, "0x%04X\n\n", *(((u16 *)(current_reg->flag))+ (int)(*ppos)/((int)7))); - *ppos+=count; - } - if (copy_to_user(buf, outputbuf, count)) - return -EFAULT; - return count; -} - -static ssize_t proc_write(struct file * file, const char * buffer, size_t count, loff_t *ppos) -{ - int i_ino = (file->f_dentry->d_inode)->i_ino; - reg_entry_t* current_reg=NULL; - int i; - unsigned long newRegValue; - char *endp; - - for (i=0;iflag == (int *)Recent_indicator)) - return -EINVAL; - - newRegValue = simple_strtoul(buffer,&endp,0); - *(current_reg->flag)=(int)newRegValue; - return (count+endp-buffer); -} -////////////////makeCMV(Opcode, Group, Address, Index, Size, Data), CMV in u16 TxMessage[MSG_LENGTH]/////////////////////////// -void makeCMV(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data) -{ - memset(TxMessage, 0, MSG_LENGTH*2); - TxMessage[0]= (opcode<<4) + (size&0xf); - TxMessage[1]= (((index==0)?0:1)<<7) + (group&0x7f); - TxMessage[2]= address; - TxMessage[3]= index; - if(opcode == H2D_CMV_WRITE) - memcpy(TxMessage+4, data, size*2); - return; -} - -////////////////makeCMV(Opcode, Group, Address, Index, Size, Data), CMV in u16 TxMessage[MSG_LENGTH]/////////////////////////// -void makeCMV_local(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data,u16 *CMVMSG) -{ - memset(CMVMSG, 0, MSG_LENGTH*2); - CMVMSG[0]= (opcode<<4) + (size&0xf); - CMVMSG[1]= (((index==0)?0:1)<<7) + (group&0x7f); - CMVMSG[2]= address; - CMVMSG[3]= index; - if(opcode == H2D_CMV_WRITE) - memcpy(CMVMSG+4, data, size*2); - return; -} - -//////////////// Driver Structure ///////////////////////////////////////////////////////////////////////////// -static ssize_t mei_write(struct file *, const char *, size_t, loff_t *); -static int mei_ioctl(struct inode *, struct file *, unsigned int, unsigned long); - -static struct file_operations mei_operations = { - write: mei_write, - ioctl: mei_ioctl, -}; - - -static ssize_t mei_write(struct file * filp, const char * buf, size_t size, loff_t * loff) -{ -// printk("\n\n mei_write entered"); -// image_buffer = (u32 *)kmalloc(size, GFP_KERNEL); - image_buffer = (u32 *)vmalloc(size); -// printk("\n\n image_buffer kmalloc done"); - if(image_buffer == NULL){ -#ifdef AMAZON_MEI_DEBUG_ON -// printk("\n\n kmalloc for firmware image fail"); - printk("\n\n vmalloc for firmware image fail"); -#endif - return -1; - } - copy_from_user((char *)image_buffer, buf, size); -// printk("\n\n copy_from_user done"); - return size; -} - - ////////// ISR GPTU Timer 6 for high resolution timer ///////////// -void amazon_timer6_interrupt_MEI(int irq, void *dev_id, struct pt_regs *regs) -{ - int i,j; - u32 temp; - u16 temp16; - u16 rdindex, wrindex; - u16 num_rd=0; //num of byte can be read - u16 bytes_to_wr=0; - -// printk("\n\nenter timer\n\n"); - irqtimes++; -// printk("\n%d\n",irqtimes); - - -/* -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_8(0x30f20, &temp, 1); -#else - meiDMARead_8(0x30f20, &temp, 1); -#endif - if((temp&0x4000)!=0){ - printk("\nER_ERR"); -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_8(0x30f20, &temp, 1); -#else - meiDMAWrite_8(0x30f20, &temp, 1); -#endif -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_8(0x30f20, &temp, 1); -#else - meiDMARead_8(0x30f20, &temp, 1); -#endif - if((temp&0x4000)!=0) - printk("\nER_ERR not cleared"); - } -*/ - - for(i=PCM_CHANNEL_NUM-1;i>=0;i--){// start from last channel, which is rx -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_16(pcm_start_addr+i*16+12, &temp, 1); -#else - meiDMARead_16(pcm_start_addr+i*16+12, &temp, 1); -#endif - wrindex = (u16)((temp & 0xffff0000)>>16); -// printk(" %d",wrindex); -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_16(pcm_start_addr+i*16+8, &temp, 1); -#else - meiDMARead_16(pcm_start_addr+i*16+8, &temp, 1); -#endif - rdindex = (u16)(temp & 0xffff); -// printk(" %d",rdindex); - if(rdindex<=wrindex) - num_rd=((wrindex-rdindex)/4)*4; //read multiply of 4 bytes - else - num_rd=((pcm_data[i].len-(rdindex-wrindex))/4)*4; //read multiply of 4 bytes - - if(i%2!=0){//rx channel - pcm_data[i].point=0; - for(j=0;j=pcm_data[i].len) - temp16=(rdindex+j*4) - pcm_data[i].len; - else - temp16=rdindex+j*4; -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16, (u32*)(pcm_data[i].buff+pcm_data[i].point), 1); -#else - meiDMARead_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16, (u32*)(pcm_data[i].buff+pcm_data[i].point), 1); -#endif - // printk(" %8x", *((u32*)(pcm_data[i].buff+pcm_data[i].point))); - /* if(pcm_data[i].point==0){ - if(pcm_data[i].buff[0]==0xA5){// start of loopback data - pcm_data[i].point+=4; - printk("\nstart receive data"); - } - } - else*/ - pcm_data[i].point+=4; - /* if(pcm_data[i].point==PCM_BUFF_SIZE){ //finish rx - pcm_data[i].finish=1; - printk("\nchannel[%d] finished", i); - } */ - } - } - if(firsttime[i]==1){ - for(j=0;j=256) - pcm_start_loc[i]=pcm_start_loc[i]-256; - } - } - - rdindex +=num_rd; - if(rdindex>=pcm_data[i].len) - rdindex=rdindex-pcm_data[i].len; -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_16(pcm_start_addr+i*16+8, &temp, 1); -#else - meiDMARead_16(pcm_start_addr+i*16+8, &temp, 1); -#endif - temp= (temp & 0xffff0000) + rdindex; -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_16(pcm_start_addr+i*16+8, &temp, 1); // update rdindex -#else - meiDMAWrite_16(pcm_start_addr+i*16+8, &temp, 1); // update rdindex -#endif - - bytes_to_wr = num_rd; - - // if(bytes_to_wr>0){ - // printk(" %d", num_rd); - // printk(" %d", rdindex); -// printk("\n\nrdindex = %d", rdindex); - //} - } - else{ //tx channel - // if((bytes_to_wr + num_rd) < pcm_data[i].len){ - for(j=0;j=pcm_data[i].len) - temp16=(wrindex+j*4) - pcm_data[i].len; - else - temp16=wrindex + j*4; -/* -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i+1].buff+j*4), 1); -#else - meiDMAWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i+1].buff+j*4), 1); -#endif*/ - -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i].buff+pcm_data[i].point), 1); - // meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i].buff), 1); -#else - meiDMAWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i].buff+pcm_data[i].point), 1); -#endif - pcm_data[i].point+=4; - if(pcm_data[i].point==PCM_BUFF_SIZE){ - // pcm_data[i].finish=1; - // printk("\nchannel[%d] finished", i); - pcm_data[i].point=0; - } - } - } - wrindex+=bytes_to_wr; - if(wrindex>=pcm_data[i].len) - wrindex=wrindex-pcm_data[i].len; -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_16(pcm_start_addr+i*16+12, &temp, 1); -#else - meiDMARead_16(pcm_start_addr+i*16+12, &temp, 1); -#endif - temp=(temp&0xffff) + (wrindex<<16); -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_16(pcm_start_addr+i*16+12, &temp, 1); // update wrindex -#else - meiDMAWrite_16(pcm_start_addr+i*16+12, &temp, 1); // update wrindex -#endif - - //if(bytes_to_wr>0){ - // printk(" %d", bytes_to_wr); - // printk(" %d", wrindex); -// printk("\n\nwrindex = %d", wrindex); - //} - // } - } - } - return; -} -//000002:fchang Start -static int meiResetArc(void) -{ - u32 auxreg0; - u32 auxreg5; - int flshcnt=0; - int flshcnt1=0; - int flshcnt2=0; - - meiLongwordWrite(MEI_CONTROL, 1); - meiLongwordWrite(MEI_DEBUG_DEC, 3); - meiLongwordWrite(MEI_DEBUG_WAD, 0x3c); - meiLongwordWrite(MEI_DEBUG_DATA, 0x10); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_DEC, 0x0); - meiLongwordWrite(MEI_DEBUG_WAD, 0x2); - meiLongwordWrite(MEI_DEBUG_DATA, 0x0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_WAD, 0x3); - meiLongwordWrite(MEI_DEBUG_DATA, 0x0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_DEC, 0x0); - meiLongwordWrite(MEI_DEBUG_RAD, 0x0); - meiPollForDbgDone(); - meiLongwordRead(MEI_DEBUG_DATA, &auxreg0); - auxreg0 = auxreg0 & 0x03ffffff; - meiLongwordWrite(MEI_DEBUG_WAD, 0x0); - meiLongwordWrite(MEI_DEBUG_DATA, auxreg0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_WAD, 0x10a); - meiLongwordWrite(MEI_DEBUG_DATA, 0x0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_DEC, 0x2); - meiLongwordWrite(MEI_DEBUG_WAD, 0xfffc); - meiLongwordWrite(MEI_DEBUG_DATA, 0x1fffffff); - meiPollForDbgDone(); - while(flshcnt<3){ - meiLongwordWrite(MEI_DEBUG_DEC, 0x0); - meiLongwordWrite(MEI_DEBUG_RAD, 0x0); - meiPollForDbgDone(); - meiLongwordRead(MEI_DEBUG_DATA, &auxreg0); - auxreg0 = auxreg0 & 0xff000000; - auxreg0 = auxreg0 | 0x3fff; - meiLongwordWrite(MEI_DEBUG_WAD, 0x0); - meiLongwordWrite(MEI_DEBUG_DATA, auxreg0); - meiPollForDbgDone(); - - meiLongwordWrite(MEI_DEBUG_DEC, 0x0); - meiLongwordWrite(MEI_DEBUG_RAD, 0x5); - meiPollForDbgDone(); - meiLongwordRead(MEI_DEBUG_DATA, &auxreg5); - auxreg5 = auxreg5 | 0x801; - meiLongwordWrite(MEI_DEBUG_WAD, 0x5); - meiLongwordWrite(MEI_DEBUG_DATA, auxreg5); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_RAD, 0x0); - meiPollForDbgDone(); - meiLongwordRead(MEI_DEBUG_DATA, &auxreg0); - auxreg0 = auxreg0 & 0x00ffffff; - if(auxreg0 == 0x4000) - flshcnt = flshcnt+1; - else{ - if(flshcnt == 0) - flshcnt1 = flshcnt1 +1; - else - flshcnt2 = flshcnt2 +1; - } - } - - return 1; -} - -static int meiResetCore(void) -{ - meiLongwordWrite(MEI_CONTROL, 0x1); - meiLongwordWrite(MEI_DEBUG_DEC, 0x2); - meiLongwordWrite(MEI_DEBUG_WAD, 0x31f10); - meiLongwordWrite(MEI_DEBUG_DATA, 0xf); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_WAD, 0x31f10); - meiLongwordWrite(MEI_DEBUG_DATA, 0x0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_WAD, 0x31f00); - meiLongwordWrite(MEI_DEBUG_DATA, 0x55); - meiPollForDbgDone(); - return 1; -} - -static int meiEnalbeMailboxInt(void) -{ - u32 arc2meiintmsk; - meiLongwordRead(ARC_TO_MEI_INT_MASK, &arc2meiintmsk); - arc2meiintmsk = arc2meiintmsk | 0x1; - meiLongwordWrite(ARC_TO_MEI_INT_MASK, arc2meiintmsk); - meiLongwordWrite(MEI_CONTROL, 0x0); - return 1; -} - - - -//000002:fchang End - -static int mei_ioctl(struct inode * ino, struct file * fil, unsigned int command, unsigned long lon) -{ - int i,k; - u32 boot_loop; - u32 page_size; - u32 dest_addr; - u32 j; - u32 temp; - u32 temp2; - u16 trapsflag=0; - amazon_clreoc_pkt * current_clreoc; - struct timeval time_now; - struct timeval time_fini; - struct list_head * ptr; - amazon_mei_mib * mib_ptr; -// u16 buff[MSG_LENGTH]__attribute__ ((aligned(4))); - structpts pts; - int meierr=MEI_SUCCESS; - u16 data[12]; //used in makeCMV, to pass in payload when CMV set, ignored when CMV read. - meireg regrdwr; - meidebug debugrdwr; - amazon_mei_mib * temp_intvl; - struct sk_buff * eoc_skb; -// 603221:tc.chen start - u16 hdlc_cmd[2]; - u16 hdlc_rx_buffer[32]; - int hdlc_rx_len=0; -// 603221:tc.chen end - - int from_kernel = 0;//joelin - if (ino == (struct inode *)0) from_kernel = 1;//joelin - -// printk("\n switch.command = %i\n", command); - switch(command){ - case GET_ADSL_LINE_CODE: - pts.adslLineTableEntry_pt = (adslLineTableEntry *)kmalloc(sizeof(adslLineTableEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineTableEntry_pt, (char *)lon, sizeof(adslLineTableEntry)); - if(IS_FLAG_SET((&(pts.adslLineTableEntry_pt->flags)), LINE_CODE_FLAG)){ - pts.adslLineTableEntry_pt->adslLineCode = 2; - } - copy_to_user((char *)lon, (char *)pts.adslLineTableEntry_pt, sizeof(adslLineTableEntry)); - kfree(pts.adslLineTableEntry_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUC_LINE_EXT: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - pts.adslLineExtTableEntry_pt = (adslLineExtTableEntry *)kmalloc(sizeof(adslLineExtTableEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineExtTableEntry_pt, (char *)lon, sizeof(adslLineExtTableEntry)); - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CAP_FLAG)){ - ATUC_LINE_TRANS_CAP_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 67 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CAP_FLAG); - } - else{ - memcpy((&(pts.adslLineExtTableEntry_pt->adslLineTransAtucCap)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG)){ - ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 67 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG); - } - else{ - memcpy((&(pts.adslLineExtTableEntry_pt->adslLineTransAtucConfig)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_ACTUAL_FLAG)){ - ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 2 Address 1 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_ACTUAL_FLAG); - } - else{ - memcpy((&(pts.adslLineExtTableEntry_pt->adslLineTransAtucActual)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG)){ // not supported currently -/* - LINE_GLITE_POWER_STATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 2 Address 0 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG); - } - else{ - memcpy((&(pts.adslLineExtTableEntry_pt->adslLineGlitePowerState)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } -*/ - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG); - } - copy_to_user((char *)lon, (char *)pts.adslLineExtTableEntry_pt, sizeof(adslLineExtTableEntry)); - kfree(pts.adslLineTableEntry_pt); - up(&mei_sema); - break; -#endif - -#ifdef AMAZON_MEI_MIB_RFC3440 - case SET_ADSL_ATUC_LINE_EXT: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - pts.adslLineExtTableEntry_pt = (adslLineExtTableEntry *)kmalloc(sizeof(adslLineExtTableEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineExtTableEntry_pt, (char *)lon, sizeof(adslLineExtTableEntry)); - - //only adslLineTransAtucConfig can be set. - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CAP_FLAG); - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG)){ - memcpy(data,(&(pts.adslLineExtTableEntry_pt->adslLineTransAtucConfig)), 2); - ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 67 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG); - } - } - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_ACTUAL_FLAG); - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG); - - copy_to_user((char *)lon, (char *)pts.adslLineExtTableEntry_pt, sizeof(adslLineExtTableEntry)); - kfree(pts.adslLineTableEntry_pt); - up(&mei_sema); - break; -#endif - - case GET_ADSL_ATUC_PHY: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslAtucPhysEntry_pt = (adslAtucPhysEntry *)kmalloc(sizeof(adslAtucPhysEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucPhysEntry_pt, (char *)lon, sizeof(adslAtucPhysEntry)); - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_SER_NUM_FLAG)){ - ATUC_PHY_SER_NUM_FLAG_MAKECMV1; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 57 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_SER_NUM_FLAG); - } - else{ - memcpy(pts.adslAtucPhysEntry_pt->serial_no, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - ATUC_PHY_SER_NUM_FLAG_MAKECMV2; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 57 Index 12"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_SER_NUM_FLAG); - } - else{ - memcpy((pts.adslAtucPhysEntry_pt->serial_no+24), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VENDOR_ID_FLAG)){ - ATUC_PHY_VENDOR_ID_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 64 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VENDOR_ID_FLAG); - } - else{ - memcpy(pts.adslAtucPhysEntry_pt->vendor_id.vendor_id, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VER_NUM_FLAG)){ - ATUC_PHY_VER_NUM_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 58 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VER_NUM_FLAG); - } - else{ - memcpy(pts.adslAtucPhysEntry_pt->version_no, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_STAT_FLAG)){ - pts.adslAtucPhysEntry_pt->status = CurrStatus.adslAtucCurrStatus; - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_OUT_PWR_FLAG)){ - ATUC_CURR_OUT_PWR_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 68 Index 5"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_OUT_PWR_FLAG); - } - else{ - memcpy((&(pts.adslAtucPhysEntry_pt->outputPwr)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_ATTR_FLAG)){ - ATUC_CURR_ATTR_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 69 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_ATTR_FLAG); - } - else{ - memcpy((&(pts.adslAtucPhysEntry_pt->attainableRate)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - copy_to_user((char *)lon, (char *)pts.adslAtucPhysEntry_pt, sizeof(adslAtucPhysEntry)); - kfree(pts.adslAtucPhysEntry_pt); - - up(&mei_sema); - break; - case GET_ADSL_ATUR_PHY: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslAturPhysEntry_pt = (adslAturPhysEntry *)kmalloc(sizeof(adslAturPhysEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslAturPhysEntry_pt, (char *)lon, sizeof(adslAturPhysEntry)); - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_SER_NUM_FLAG)){ - ATUR_PHY_SER_NUM_FLAG_MAKECMV1; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 62 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_SER_NUM_FLAG); - } - else{ - memcpy(pts.adslAturPhysEntry_pt->serial_no, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - ATUR_PHY_SER_NUM_FLAG_MAKECMV2; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 62 Index 12"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_SER_NUM_FLAG); - } - else{ - memcpy((pts.adslAturPhysEntry_pt->serial_no+24), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VENDOR_ID_FLAG)){ - ATUR_PHY_VENDOR_ID_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 65 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VENDOR_ID_FLAG); - } - else{ - memcpy(pts.adslAturPhysEntry_pt->vendor_id.vendor_id, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VER_NUM_FLAG)){ - ATUR_PHY_VER_NUM_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 61 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VER_NUM_FLAG); - } - else{ - memcpy(pts.adslAturPhysEntry_pt->version_no, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_SNRMGN_FLAG)){ - ATUR_SNRMGN_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 68 Index 4"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_SNRMGN_FLAG); - } - else{ - memcpy((&(pts.adslAturPhysEntry_pt->SnrMgn)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_ATTN_FLAG)){ - ATUR_ATTN_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 68 Index 2"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_ATTN_FLAG); - } - else{ - memcpy((&(pts.adslAturPhysEntry_pt->Attn)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_STAT_FLAG)){ - pts.adslAturPhysEntry_pt->status = CurrStatus.adslAturCurrStatus; - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_OUT_PWR_FLAG)){ - ATUR_CURR_OUT_PWR_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 69 Index 5"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_OUT_PWR_FLAG); - } - else{ - memcpy((&(pts.adslAturPhysEntry_pt->outputPwr)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_ATTR_FLAG)){ - ATUR_CURR_ATTR_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 68 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_ATTR_FLAG); - } - else{ - memcpy((&(pts.adslAturPhysEntry_pt->attainableRate)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - copy_to_user((char *)lon, (char *)pts.adslAturPhysEntry_pt, sizeof(adslAturPhysEntry)); - kfree(pts.adslAturPhysEntry_pt); - - up(&mei_sema); - break; - case GET_ADSL_ATUC_CHAN_INFO: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslAtucChanInfo_pt = (adslAtucChanInfo *)kmalloc(sizeof(adslAtucChanInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucChanInfo_pt, (char *)lon, sizeof(adslAtucChanInfo)); - if(IS_FLAG_SET((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_INTLV_DELAY_FLAG)){ - if((chantype.interleave!=1) || (chantype.fast==1)){ - CLR_FLAG((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_INTLV_DELAY_FLAG); - } - else{ - ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 3 Index 1"); -#endif - CLR_FLAG((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_INTLV_DELAY_FLAG); - } - else{ - memcpy((&(pts.adslAtucChanInfo_pt->interleaveDelay)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - } - if(IS_FLAG_SET((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_CURR_TX_RATE_FLAG)){ - ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 1 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_CURR_TX_RATE_FLAG); - } - else{ - pts.adslAtucChanInfo_pt->currTxRate = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - if(IS_FLAG_SET((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_PREV_TX_RATE_FLAG)){ - pts.adslAtucChanInfo_pt->prevTxRate = PrevTxRate.adslAtucChanPrevTxRate; - } - copy_to_user((char *)lon, (char *)pts.adslAtucChanInfo_pt, sizeof(adslAtucChanInfo)); - kfree(pts.adslAtucChanInfo_pt); - - up(&mei_sema); - break; - case GET_ADSL_ATUR_CHAN_INFO: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslAturChanInfo_pt = (adslAturChanInfo *)kmalloc(sizeof(adslAturChanInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAturChanInfo_pt, (char *)lon, sizeof(adslAturChanInfo)); - if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_INTLV_DELAY_FLAG)){ - if((chantype.interleave!=1) || (chantype.fast==1)){ - CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_INTLV_DELAY_FLAG); - } - else{ - ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 2 Index 1"); -#endif - CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_INTLV_DELAY_FLAG); - } - else{ - memcpy((&(pts.adslAturChanInfo_pt->interleaveDelay)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - } - if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CURR_TX_RATE_FLAG)){ - ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 0 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CURR_TX_RATE_FLAG); - } - else{ - pts.adslAturChanInfo_pt->currTxRate = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_PREV_TX_RATE_FLAG)){ - pts.adslAturChanInfo_pt->prevTxRate = PrevTxRate.adslAturChanPrevTxRate; - } - if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CRC_BLK_LEN_FLAG)){ - // ? no CMV to update this - CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CRC_BLK_LEN_FLAG); - } - copy_to_user((char *)lon, (char *)pts.adslAturChanInfo_pt, sizeof(adslAturChanInfo)); - kfree(pts.adslAturChanInfo_pt); - - up(&mei_sema); - break; - case GET_ADSL_ATUC_PERF_DATA: - pts.atucPerfDataEntry_pt = (atucPerfDataEntry *)kmalloc(sizeof(atucPerfDataEntry), GFP_KERNEL); - copy_from_user((char *)pts.atucPerfDataEntry_pt, (char *)lon, sizeof(atucPerfDataEntry)); - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_LOFS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfLofs=ATUC_PERF_LOFS; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_LOSS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfLoss=ATUC_PERF_LOSS; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_ESS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfESs=ATUC_PERF_ESS; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_INITS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfInits=ATUC_PERF_INITS; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_VALID_INTVLS_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==96) - break; - } - pts.atucPerfDataEntry_pt->adslAtucPerfValidIntervals=i; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_INVALID_INTVLS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfInvalidIntervals=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG)){ - do_gettimeofday(&time_now); - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinTimeElapsed=time_now.tv_sec - (current_intvl->start_time).tv_sec; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_LOFS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinLofs=current_intvl->AtucPerfLof; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_LOSS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinLoss=current_intvl->AtucPerfLos; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_ESS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinESs=current_intvl->AtucPerfEs; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_INIT_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinInits=current_intvl->AtucPerfInit; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i+=900; - } - do_gettimeofday(&time_now); - i+=time_now.tv_sec - (current_intvl->start_time).tv_sec; - if(i>=86400) - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayTimeElapsed=i-86400; - else - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayTimeElapsed=i; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_LOFS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfLof; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfLof; - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayLofs=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_LOSS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfLos; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfLos; - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayLoss=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_ESS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfEs; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfEs; - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayESs=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_INIT_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfInit; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfInit; - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayInits=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_MON_SEC_FLAG)){ - i=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - i++; - } - if(i>=96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayMoniSecs=86400; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayMoniSecs=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_LOFS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfLof; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLofs=j; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLofs=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_LOSS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfLos; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLoss=j; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLoss=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_ESS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfEs; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayESs=j; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayESs=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_INITS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfInit; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayInits=j; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayInits=0; - } - - copy_to_user((char *)lon, (char *)pts.atucPerfDataEntry_pt, sizeof(atucPerfDataEntry)); - kfree(pts.atucPerfDataEntry_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUC_PERF_DATA_EXT: //??? CMV mapping not available - pts.atucPerfDataExtEntry_pt = (atucPerfDataExtEntry *)kmalloc(sizeof(atucPerfDataExtEntry), GFP_KERNEL); - copy_from_user((char *)pts.atucPerfDataExtEntry_pt, (char *)lon, sizeof(atucPerfDataExtEntry)); - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_FASTR_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfStatFastR=ATUC_PERF_STAT_FASTR; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_FAILED_FASTR_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfStatFailedFastR=ATUC_PERF_STAT_FAILED_FASTR; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_SESL_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfStatSesL=ATUC_PERF_STAT_SESL; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_UASL_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfStatUasL=ATUC_PERF_STAT_UASL; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_FASTR_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinFastR=current_intvl->AtucPerfStatFastR; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinFailedFastR=current_intvl->AtucPerfStatFailedFastR; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_SESL_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinSesL=current_intvl->AtucPerfStatSesL; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_UASL_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinUasL=current_intvl->AtucPerfStatUasL; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_FASTR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatFastR; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfStatFastR; - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DayFastR=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatFailedFastR; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfStatFailedFastR; - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DayFailedFastR=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_SESL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatSesL; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfStatSesL; - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DaySesL=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_UASL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatUasL; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfStatUasL; - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DayUasL=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_FASTR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatFastR; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFastR=j; - else - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFastR=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatFailedFastR; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFailedFastR=j; - else - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFailedFastR=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_SESL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatSesL; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DaySesL=j; - else - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DaySesL=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_UASL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatUasL; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayUasL=j; - else - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayUasL=0; - } - copy_to_user((char *)lon, (char *)pts.atucPerfDataExtEntry_pt, sizeof(atucPerfDataExtEntry)); - kfree(pts.atucPerfDataExtEntry_pt); - break; -#endif - case GET_ADSL_ATUR_PERF_DATA: - pts.aturPerfDataEntry_pt = (aturPerfDataEntry *)kmalloc(sizeof(aturPerfDataEntry), GFP_KERNEL); - copy_from_user((char *)pts.aturPerfDataEntry_pt, (char *)lon, sizeof(aturPerfDataEntry)); - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_LOFS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfLofs=ATUR_PERF_LOFS; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_LOSS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfLoss=ATUR_PERF_LOSS; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_LPR_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfLprs=ATUR_PERF_LPR; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_ESS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfESs=ATUR_PERF_ESS; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_VALID_INTVLS_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==96) - break; - } - pts.aturPerfDataEntry_pt->adslAturPerfValidIntervals=i; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_INVALID_INTVLS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfInvalidIntervals=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG)){ - do_gettimeofday(&time_now); - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinTimeElapsed=time_now.tv_sec - (current_intvl->start_time).tv_sec; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_LOFS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinLofs=current_intvl->AturPerfLof; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_LOSS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinLoss=current_intvl->AturPerfLos; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_LPR_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinLprs=current_intvl->AturPerfLpr; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_ESS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinESs=current_intvl->AturPerfEs; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i+=900; - } - do_gettimeofday(&time_now); - i+=time_now.tv_sec - (current_intvl->start_time).tv_sec; - if(i>=86400) - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayTimeElapsed=i-86400; - else - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayTimeElapsed=i; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_LOFS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLof; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfLof; - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayLofs=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_LOSS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLos; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfLos; - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayLoss=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_LPR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLpr; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfLpr; - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayLprs=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_ESS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfEs; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfEs; - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayESs=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_MON_SEC_FLAG)){ - i=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - i++; - } - if(i>=96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayMoniSecs=86400; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayMoniSecs=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_LOFS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLof; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLofs=j; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLofs=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_LOSS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLos; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLoss=j; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLoss=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_LPR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLpr; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLprs=j; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLprs=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_ESS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfEs; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayESs=j; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayESs=0; - } - - copy_to_user((char *)lon, (char *)pts.aturPerfDataEntry_pt, sizeof(aturPerfDataEntry)); - kfree(pts.aturPerfDataEntry_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUR_PERF_DATA_EXT: - pts.aturPerfDataExtEntry_pt = (aturPerfDataExtEntry *)kmalloc(sizeof(aturPerfDataExtEntry), GFP_KERNEL); - copy_from_user((char *)pts.aturPerfDataExtEntry_pt, (char *)lon, sizeof(aturPerfDataExtEntry)); - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_STAT_SESL_FLAG)){ - pts.aturPerfDataExtEntry_pt->adslAturPerfStatSesL=ATUR_PERF_STAT_SESL; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_STAT_UASL_FLAG)){ - pts.aturPerfDataExtEntry_pt->adslAturPerfStatUasL=ATUR_PERF_STAT_UASL; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_15MIN_SESL_FLAG)){ - pts.aturPerfDataExtEntry_pt->adslAturPerfCurr15MinSesL=current_intvl->AturPerfStatSesL; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_15MIN_UASL_FLAG)){ - pts.aturPerfDataExtEntry_pt->adslAturPerfCurr15MinUasL=current_intvl->AturPerfStatUasL; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_1DAY_SESL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfStatSesL; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfStatSesL; - pts.aturPerfDataExtEntry_pt->adslAturPerfCurr1DaySesL=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_1DAY_UASL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfStatUasL; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfStatUasL; - pts.aturPerfDataExtEntry_pt->adslAturPerfCurr1DayUasL=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_PREV_1DAY_SESL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfStatSesL; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DaySesL=j; - else - pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DaySesL=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_PREV_1DAY_UASL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfStatUasL; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DayUasL=j; - else - pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DayUasL=0; - } - copy_to_user((char *)lon, (char *)pts.aturPerfDataExtEntry_pt, sizeof(aturPerfDataExtEntry)); - kfree(pts.aturPerfDataExtEntry_pt); - break; -#endif - case GET_ADSL_ATUC_INTVL_INFO: - pts.adslAtucIntvlInfo_pt = (adslAtucIntvlInfo *)kmalloc(sizeof(adslAtucIntvlInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucIntvlInfo_pt, (char *)lon, sizeof(adslAtucIntvlInfo)); - - if(pts.adslAtucIntvlInfo_pt->IntervalNumber <1){ - pts.adslAtucIntvlInfo_pt->intervalLOF = ATUC_PERF_LOFS; - pts.adslAtucIntvlInfo_pt->intervalLOS = ATUC_PERF_LOSS; - pts.adslAtucIntvlInfo_pt->intervalES = ATUC_PERF_ESS; - pts.adslAtucIntvlInfo_pt->intervalInits = ATUC_PERF_INITS; - pts.adslAtucIntvlInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAtucIntvlInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAtucIntvlInfo_pt->intervalLOF = temp_intvl->AtucPerfLof; - pts.adslAtucIntvlInfo_pt->intervalLOS = temp_intvl->AtucPerfLos; - pts.adslAtucIntvlInfo_pt->intervalES = temp_intvl->AtucPerfEs; - pts.adslAtucIntvlInfo_pt->intervalInits = temp_intvl->AtucPerfInit; - pts.adslAtucIntvlInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ - pts.adslAtucIntvlInfo_pt->intervalValidData = 0; - pts.adslAtucIntvlInfo_pt->flags = 0; - pts.adslAtucIntvlInfo_pt->intervalLOF = 0; - pts.adslAtucIntvlInfo_pt->intervalLOS = 0; - pts.adslAtucIntvlInfo_pt->intervalES = 0; - pts.adslAtucIntvlInfo_pt->intervalInits = 0; - } - } - - copy_to_user((char *)lon, (char *)pts.adslAtucIntvlInfo_pt, sizeof(adslAtucIntvlInfo)); - kfree(pts.adslAtucIntvlInfo_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUC_INTVL_EXT_INFO: - pts.adslAtucInvtlExtInfo_pt = (adslAtucInvtlExtInfo *)kmalloc(sizeof(adslAtucInvtlExtInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucInvtlExtInfo_pt, (char *)lon, sizeof(adslAtucInvtlExtInfo)); - if(pts.adslAtucInvtlExtInfo_pt->IntervalNumber <1){ - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFastR = ATUC_PERF_STAT_FASTR; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFailedFastR = ATUC_PERF_STAT_FAILED_FASTR; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalSesL = ATUC_PERF_STAT_SESL; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalUasL = ATUC_PERF_STAT_UASL; -// pts.adslAtucInvtlExtInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAtucInvtlExtInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFastR = temp_intvl->AtucPerfStatFastR; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFailedFastR = temp_intvl->AtucPerfStatFailedFastR; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalSesL = temp_intvl->AtucPerfStatSesL; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalUasL = temp_intvl->AtucPerfStatUasL; -// pts.adslAtucInvtlExtInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ -// pts.adslAtucInvtlExtInfo_pt->intervalValidData = 0; - pts.adslAtucInvtlExtInfo_pt->flags = 0; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFastR = 0; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFailedFastR = 0; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalSesL = 0; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalUasL = 0; - } - } - copy_to_user((char *)lon, (char *)pts.adslAtucInvtlExtInfo_pt, sizeof(adslAtucInvtlExtInfo)); - kfree(pts.adslAtucInvtlExtInfo_pt); - break; -#endif - case GET_ADSL_ATUR_INTVL_INFO: - pts.adslAturIntvlInfo_pt = (adslAturIntvlInfo *)kmalloc(sizeof(adslAturIntvlInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAturIntvlInfo_pt, (char *)lon, sizeof(adslAturIntvlInfo)); - - if(pts.adslAturIntvlInfo_pt->IntervalNumber <1){ - pts.adslAturIntvlInfo_pt->intervalLOF = ATUR_PERF_LOFS; - pts.adslAturIntvlInfo_pt->intervalLOS = ATUR_PERF_LOSS; - pts.adslAturIntvlInfo_pt->intervalES = ATUR_PERF_ESS; - pts.adslAturIntvlInfo_pt->intervalLPR = ATUR_PERF_LPR; - pts.adslAturIntvlInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAturIntvlInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAturIntvlInfo_pt->intervalLOF = temp_intvl->AturPerfLof; - pts.adslAturIntvlInfo_pt->intervalLOS = temp_intvl->AturPerfLos; - pts.adslAturIntvlInfo_pt->intervalES = temp_intvl->AturPerfEs; - pts.adslAturIntvlInfo_pt->intervalLPR = temp_intvl->AturPerfLpr; - pts.adslAturIntvlInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ - pts.adslAturIntvlInfo_pt->intervalValidData = 0; - pts.adslAturIntvlInfo_pt->flags = 0; - pts.adslAturIntvlInfo_pt->intervalLOF = 0; - pts.adslAturIntvlInfo_pt->intervalLOS = 0; - pts.adslAturIntvlInfo_pt->intervalES = 0; - pts.adslAturIntvlInfo_pt->intervalLPR = 0; - } - } - - copy_to_user((char *)lon, (char *)pts.adslAturIntvlInfo_pt, sizeof(adslAturIntvlInfo)); - kfree(pts.adslAturIntvlInfo_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUR_INTVL_EXT_INFO: - pts.adslAturInvtlExtInfo_pt = (adslAturInvtlExtInfo *)kmalloc(sizeof(adslAturInvtlExtInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAturInvtlExtInfo_pt, (char *)lon, sizeof(adslAturInvtlExtInfo)); - - if(pts.adslAturInvtlExtInfo_pt->IntervalNumber <1){ - pts.adslAturInvtlExtInfo_pt->adslAturIntervalSesL = ATUR_PERF_STAT_SESL; - pts.adslAturInvtlExtInfo_pt->adslAturIntervalUasL = ATUR_PERF_STAT_UASL; -// pts.adslAturInvtlExtInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAturInvtlExtInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAturInvtlExtInfo_pt->adslAturIntervalSesL = temp_intvl->AturPerfStatSesL; - pts.adslAturInvtlExtInfo_pt->adslAturIntervalUasL = temp_intvl->AturPerfStatUasL; -// pts.adslAturInvtlExtInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ -// pts.adslAturInvtlExtInfo_pt->intervalValidData = 0; - pts.adslAturInvtlExtInfo_pt->flags = 0; - pts.adslAturInvtlExtInfo_pt->adslAturIntervalSesL = 0; - pts.adslAturInvtlExtInfo_pt->adslAturIntervalUasL = 0; - } - } - - copy_to_user((char *)lon, (char *)pts.adslAturInvtlExtInfo_pt, sizeof(adslAturInvtlExtInfo)); - kfree(pts.adslAturInvtlExtInfo_pt); - break; -#endif - case GET_ADSL_ATUC_CHAN_PERF_DATA: - pts.atucChannelPerfDataEntry_pt = (atucChannelPerfDataEntry *)kmalloc(sizeof(atucChannelPerfDataEntry), GFP_KERNEL); - copy_from_user((char *)pts.atucChannelPerfDataEntry_pt, (char *)lon, sizeof(atucChannelPerfDataEntry)); - - pts.atucChannelPerfDataEntry_pt->flags = 0; - - copy_to_user((char *)lon, (char *)pts.atucChannelPerfDataEntry_pt, sizeof(atucChannelPerfDataEntry)); - kfree(pts.atucChannelPerfDataEntry_pt); - break; - case GET_ADSL_ATUR_CHAN_PERF_DATA: - pts.aturChannelPerfDataEntry_pt = (aturChannelPerfDataEntry *)kmalloc(sizeof(aturChannelPerfDataEntry), GFP_KERNEL); - copy_from_user((char *)pts.aturChannelPerfDataEntry_pt, (char *)lon, sizeof(aturChannelPerfDataEntry)); - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_RECV_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanReceivedBlks=ATUR_CHAN_RECV_BLK; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_TX_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanTransmittedBlks=ATUR_CHAN_TX_BLK; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_CORR_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanCorrectedBlks=ATUR_CHAN_CORR_BLK; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_UNCORR_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanUncorrectBlks=ATUR_CHAN_UNCORR_BLK; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_VALID_INTVL_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==96) - break; - } - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfValidIntervals=i; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_INVALID_INTVL_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfInvalidIntervals=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG)){ - do_gettimeofday(&time_now); - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinTimeElapsed=time_now.tv_sec - (current_intvl->start_time).tv_sec; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinReceivedBlks=current_intvl->AturChanPerfRxBlk; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinTransmittedBlks=current_intvl->AturChanPerfTxBlk; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinCorrectedBlks=current_intvl->AturChanPerfCorrBlk; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinUncorrectBlks=current_intvl->AturChanPerfUncorrBlk; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i+=900; - } - do_gettimeofday(&time_now); - i+=time_now.tv_sec - (current_intvl->start_time).tv_sec; - if(i>=86400) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayTimeElapsed=i-86400; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayTimeElapsed=i; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfRxBlk; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturChanPerfRxBlk; - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayReceivedBlks=j; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfTxBlk; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturChanPerfTxBlk; - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayTransmittedBlks=j; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfCorrBlk; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturChanPerfCorrBlk; - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayCorrectedBlks=j; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfUncorrBlk; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturChanPerfUncorrBlk; - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayUncorrectBlks=j; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG)){ - i=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - i++; - } - if(i>=96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayMoniSecs=86400; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayMoniSecs=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfRxBlk; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayReceivedBlks=j; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayReceivedBlks=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfTxBlk; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayTransmittedBlks=j; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayTransmittedBlks=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfCorrBlk; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayCorrectedBlks=j; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayCorrectedBlks=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfUncorrBlk; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayUncorrectBlks=j; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayUncorrectBlks=0; - } - - copy_to_user((char *)lon, (char *)pts.aturChannelPerfDataEntry_pt, sizeof(aturChannelPerfDataEntry)); - kfree(pts.aturChannelPerfDataEntry_pt); - break; - case GET_ADSL_ATUC_CHAN_INTVL_INFO: - pts.adslAtucChanIntvlInfo_pt = (adslAtucChanIntvlInfo *)kmalloc(sizeof(adslAtucChanIntvlInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucChanIntvlInfo_pt, (char *)lon, sizeof(adslAtucChanIntvlInfo)); - - pts.adslAtucChanIntvlInfo_pt->flags = 0; - - copy_to_user((char *)lon, (char *)pts.adslAtucChanIntvlInfo_pt, sizeof(adslAtucChanIntvlInfo)); - kfree(pts.adslAtucChanIntvlInfo_pt); - break; - case GET_ADSL_ATUR_CHAN_INTVL_INFO: - pts.adslAturChanIntvlInfo_pt = (adslAturChanIntvlInfo *)kmalloc(sizeof(adslAturChanIntvlInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAturChanIntvlInfo_pt, (char *)lon, sizeof(adslAturChanIntvlInfo)); - - if(pts.adslAturChanIntvlInfo_pt->IntervalNumber <1){ - pts.adslAturChanIntvlInfo_pt->chanIntervalRecvdBlks = ATUR_CHAN_RECV_BLK; - pts.adslAturChanIntvlInfo_pt->chanIntervalXmitBlks = ATUR_CHAN_TX_BLK; - pts.adslAturChanIntvlInfo_pt->chanIntervalCorrectedBlks = ATUR_CHAN_CORR_BLK; - pts.adslAturChanIntvlInfo_pt->chanIntervalUncorrectBlks = ATUR_CHAN_UNCORR_BLK; - pts.adslAturChanIntvlInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAturChanIntvlInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAturChanIntvlInfo_pt->chanIntervalRecvdBlks = temp_intvl->AturChanPerfRxBlk; - pts.adslAturChanIntvlInfo_pt->chanIntervalXmitBlks = temp_intvl->AturChanPerfTxBlk; - pts.adslAturChanIntvlInfo_pt->chanIntervalCorrectedBlks = temp_intvl->AturChanPerfCorrBlk; - pts.adslAturChanIntvlInfo_pt->chanIntervalUncorrectBlks = temp_intvl->AturChanPerfUncorrBlk; - pts.adslAturChanIntvlInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ - pts.adslAturChanIntvlInfo_pt->intervalValidData = 0; - pts.adslAturChanIntvlInfo_pt->flags = 0; - } - } - - copy_to_user((char *)lon, (char *)pts.adslAturChanIntvlInfo_pt, sizeof(adslAturChanIntvlInfo)); - kfree(pts.adslAturChanIntvlInfo_pt); - break; - case GET_ADSL_ALRM_CONF_PROF: - pts.adslLineAlarmConfProfileEntry_pt = (adslLineAlarmConfProfileEntry *)kmalloc(sizeof(adslLineAlarmConfProfileEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineAlarmConfProfileEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileEntry)); - - strncpy(pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileName, AlarmConfProfile.adslLineAlarmConfProfileName, 32); - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOFS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLofs=AlarmConfProfile.adslAtucThresh15MinLofs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOSS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLoss=AlarmConfProfile.adslAtucThresh15MinLoss; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_ESS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinESs=AlarmConfProfile.adslAtucThresh15MinESs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEUP_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateUp=AlarmConfProfile.adslAtucThreshFastRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEUP_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateUp=AlarmConfProfile.adslAtucThreshInterleaveRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEDOWN_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateDown=AlarmConfProfile.adslAtucThreshFastRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateDown=AlarmConfProfile.adslAtucThreshInterleaveRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucInitFailureTrapEnable=AlarmConfProfile.adslAtucInitFailureTrapEnable; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOFS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLofs=AlarmConfProfile.adslAturThresh15MinLofs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOSS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLoss=AlarmConfProfile.adslAturThresh15MinLoss; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LPRS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLprs=AlarmConfProfile.adslAturThresh15MinLprs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_ESS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinESs=AlarmConfProfile.adslAturThresh15MinESs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEUP_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateUp=AlarmConfProfile.adslAturThreshFastRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEUP_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateUp=AlarmConfProfile.adslAturThreshInterleaveRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEDOWN_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateDown=AlarmConfProfile.adslAturThreshFastRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateDown=AlarmConfProfile.adslAturThreshInterleaveRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileRowStatus=AlarmConfProfile.adslLineAlarmConfProfileRowStatus; - } - copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileEntry_pt, sizeof(adslLineAlarmConfProfileEntry)); - kfree(pts.adslLineAlarmConfProfileEntry_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ALRM_CONF_PROF_EXT: - pts.adslLineAlarmConfProfileExtEntry_pt = (adslLineAlarmConfProfileExtEntry *)kmalloc(sizeof(adslLineAlarmConfProfileExtEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineAlarmConfProfileExtEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileExtEntry)); - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_FAILED_FASTR_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinFailedFastR=AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_SESL_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinSesL=AlarmConfProfileExt.adslAtucThreshold15MinSesL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_UASL_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinUasL=AlarmConfProfileExt.adslAtucThreshold15MinUasL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_SESL_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinSesL=AlarmConfProfileExt.adslAturThreshold15MinSesL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_UASL_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinUasL=AlarmConfProfileExt.adslAturThreshold15MinUasL; - } - copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileExtEntry_pt, sizeof(adslLineAlarmConfProfileExtEntry)); - kfree(pts.adslLineAlarmConfProfileExtEntry_pt); - break; -#endif - case SET_ADSL_ALRM_CONF_PROF: - pts.adslLineAlarmConfProfileEntry_pt = (adslLineAlarmConfProfileEntry *)kmalloc(sizeof(adslLineAlarmConfProfileEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineAlarmConfProfileEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileEntry)); - - strncpy(AlarmConfProfile.adslLineAlarmConfProfileName, pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileName, 32); - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOFS_FLAG)){ - AlarmConfProfile.adslAtucThresh15MinLofs=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLofs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOSS_FLAG)){ - AlarmConfProfile.adslAtucThresh15MinLoss=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLoss; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_ESS_FLAG)){ - AlarmConfProfile.adslAtucThresh15MinESs=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinESs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEUP_FLAG)){ - AlarmConfProfile.adslAtucThreshFastRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEUP_FLAG)){ - AlarmConfProfile.adslAtucThreshInterleaveRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEDOWN_FLAG)){ - AlarmConfProfile.adslAtucThreshFastRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG)){ - AlarmConfProfile.adslAtucThreshInterleaveRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG)){ - AlarmConfProfile.adslAtucInitFailureTrapEnable=pts.adslLineAlarmConfProfileEntry_pt->adslAtucInitFailureTrapEnable; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOFS_FLAG)){ - AlarmConfProfile.adslAturThresh15MinLofs=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLofs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOSS_FLAG)){ - AlarmConfProfile.adslAturThresh15MinLoss=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLoss; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LPRS_FLAG)){ - AlarmConfProfile.adslAturThresh15MinLprs=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLprs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_ESS_FLAG)){ - AlarmConfProfile.adslAturThresh15MinESs=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinESs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEUP_FLAG)){ - AlarmConfProfile.adslAturThreshFastRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEUP_FLAG)){ - AlarmConfProfile.adslAturThreshInterleaveRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEDOWN_FLAG)){ - AlarmConfProfile.adslAturThreshFastRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG)){ - AlarmConfProfile.adslAturThreshInterleaveRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG)){ - AlarmConfProfile.adslLineAlarmConfProfileRowStatus=pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileRowStatus; - } - copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileEntry_pt, sizeof(adslLineAlarmConfProfileEntry)); - kfree(pts.adslLineAlarmConfProfileEntry_pt); - break; - -#ifdef AMAZON_MEI_MIB_RFC3440 - case SET_ADSL_ALRM_CONF_PROF_EXT: - pts.adslLineAlarmConfProfileExtEntry_pt = (adslLineAlarmConfProfileExtEntry *)kmalloc(sizeof(adslLineAlarmConfProfileExtEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineAlarmConfProfileExtEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileExtEntry)); - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_FAILED_FASTR_FLAG)){ - AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR=pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinFailedFastR; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_SESL_FLAG)){ - AlarmConfProfileExt.adslAtucThreshold15MinSesL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinSesL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_UASL_FLAG)){ - AlarmConfProfileExt.adslAtucThreshold15MinUasL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinUasL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_SESL_FLAG)){ - AlarmConfProfileExt.adslAturThreshold15MinSesL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinSesL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_UASL_FLAG)){ - AlarmConfProfileExt.adslAturThreshold15MinUasL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinUasL; - } - copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileExtEntry_pt, sizeof(adslLineAlarmConfProfileExtEntry)); - kfree(pts.adslLineAlarmConfProfileExtEntry_pt); - break; -#endif - - case ADSL_ATUR_TRAPS: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - trapsflag=0; - if(AlarmConfProfile.adslAtucThresh15MinLofs!=0 && current_intvl->AtucPerfLof>=AlarmConfProfile.adslAtucThresh15MinLofs) - trapsflag|=ATUC_PERF_LOFS_THRESH_FLAG; - if(AlarmConfProfile.adslAtucThresh15MinLoss!=0 && current_intvl->AtucPerfLos>=AlarmConfProfile.adslAtucThresh15MinLoss) - trapsflag|=ATUC_PERF_LOSS_THRESH_FLAG; - if(AlarmConfProfile.adslAtucThresh15MinESs!=0 && current_intvl->AtucPerfEs>=AlarmConfProfile.adslAtucThresh15MinESs) - trapsflag|=ATUC_PERF_ESS_THRESH_FLAG; - if(chantype.fast==1){ - if(AlarmConfProfile.adslAtucThreshFastRateUp!=0 || AlarmConfProfile.adslAtucThreshFastRateDown!=0){ - ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 1 Index 0"); -#endif - } - else{ - temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - if((AlarmConfProfile.adslAtucThreshFastRateUp!=0) && (temp>=PrevTxRate.adslAtucChanPrevTxRate+AlarmConfProfile.adslAtucThreshFastRateUp)){ - trapsflag|=ATUC_RATE_CHANGE_FLAG; - PrevTxRate.adslAtucChanPrevTxRate = temp; - } - if((AlarmConfProfile.adslAtucThreshFastRateDown!=0) && (temp<=PrevTxRate.adslAtucChanPrevTxRate-AlarmConfProfile.adslAtucThreshFastRateDown)){ - trapsflag|=ATUC_RATE_CHANGE_FLAG; - PrevTxRate.adslAtucChanPrevTxRate = temp; - } - } - } - } - if(chantype.interleave==1){ - if(AlarmConfProfile.adslAtucThreshInterleaveRateUp!=0 || AlarmConfProfile.adslAtucThreshInterleaveRateDown!=0){ - ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 1 Index 0"); -#endif - } - else{ - temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - if((AlarmConfProfile.adslAtucThreshInterleaveRateUp!=0) && (temp>=PrevTxRate.adslAtucChanPrevTxRate+AlarmConfProfile.adslAtucThreshInterleaveRateUp)){ - trapsflag|=ATUC_RATE_CHANGE_FLAG; - PrevTxRate.adslAtucChanPrevTxRate = temp; - } - if((AlarmConfProfile.adslAtucThreshInterleaveRateDown!=0) && (temp<=PrevTxRate.adslAtucChanPrevTxRate-AlarmConfProfile.adslAtucThreshInterleaveRateDown)){ - trapsflag|=ATUC_RATE_CHANGE_FLAG; - PrevTxRate.adslAtucChanPrevTxRate = temp; - } - } - } - } - if(AlarmConfProfile.adslAturThresh15MinLofs!=0 && current_intvl->AturPerfLof>=AlarmConfProfile.adslAturThresh15MinLofs) - trapsflag|=ATUR_PERF_LOFS_THRESH_FLAG; - if(AlarmConfProfile.adslAturThresh15MinLoss!=0 && current_intvl->AturPerfLos>=AlarmConfProfile.adslAturThresh15MinLoss) - trapsflag|=ATUR_PERF_LOSS_THRESH_FLAG; - if(AlarmConfProfile.adslAturThresh15MinLprs!=0 && current_intvl->AturPerfLpr>=AlarmConfProfile.adslAturThresh15MinLprs) - trapsflag|=ATUR_PERF_LPRS_THRESH_FLAG; - if(AlarmConfProfile.adslAturThresh15MinESs!=0 && current_intvl->AturPerfEs>=AlarmConfProfile.adslAturThresh15MinESs) - trapsflag|=ATUR_PERF_ESS_THRESH_FLAG; - if(chantype.fast==1){ - if(AlarmConfProfile.adslAturThreshFastRateUp!=0 || AlarmConfProfile.adslAturThreshFastRateDown!=0){ - ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 0 Index 0"); -#endif - } - else{ - temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - if((AlarmConfProfile.adslAturThreshFastRateUp!=0) && (temp>=PrevTxRate.adslAturChanPrevTxRate+AlarmConfProfile.adslAturThreshFastRateUp)){ - trapsflag|=ATUR_RATE_CHANGE_FLAG; - PrevTxRate.adslAturChanPrevTxRate = temp; - } - if((AlarmConfProfile.adslAturThreshFastRateDown!=0) && (temp<=PrevTxRate.adslAturChanPrevTxRate-AlarmConfProfile.adslAturThreshFastRateDown)){ - trapsflag|=ATUR_RATE_CHANGE_FLAG; - PrevTxRate.adslAturChanPrevTxRate = temp; - } - } - } - } - if(chantype.interleave==1){ - if(AlarmConfProfile.adslAturThreshInterleaveRateUp!=0 || AlarmConfProfile.adslAturThreshInterleaveRateDown!=0){ - ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 0 Index 0"); -#endif - } - else{ - temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - if((AlarmConfProfile.adslAturThreshInterleaveRateUp!=0) && (temp>=PrevTxRate.adslAturChanPrevTxRate+AlarmConfProfile.adslAturThreshInterleaveRateUp)){ - trapsflag|=ATUR_RATE_CHANGE_FLAG; - PrevTxRate.adslAturChanPrevTxRate = temp; - } - if((AlarmConfProfile.adslAturThreshInterleaveRateDown!=0) && (temp<=PrevTxRate.adslAturChanPrevTxRate-AlarmConfProfile.adslAturThreshInterleaveRateDown)){ - trapsflag|=ATUR_RATE_CHANGE_FLAG; - PrevTxRate.adslAturChanPrevTxRate = temp; - } - } - } - } - copy_to_user((char *)lon, (char *)(&trapsflag), 2); - - up(&mei_sema); - break; - -#ifdef AMAZON_MEI_MIB_RFC3440 - case ADSL_ATUR_EXT_TRAPS: - trapsflag=0; - if(AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR!=0 && current_intvl->AtucPerfStatFailedFastR>=AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR) - trapsflag|=ATUC_15MIN_FAILED_FASTR_TRAP_FLAG; - if(AlarmConfProfileExt.adslAtucThreshold15MinSesL!=0 && current_intvl->AtucPerfStatSesL>=AlarmConfProfileExt.adslAtucThreshold15MinSesL) - trapsflag|=ATUC_15MIN_SESL_TRAP_FLAG; - if(AlarmConfProfileExt.adslAtucThreshold15MinUasL!=0 && current_intvl->AtucPerfStatUasL>=AlarmConfProfileExt.adslAtucThreshold15MinUasL) - trapsflag|=ATUC_15MIN_UASL_TRAP_FLAG; - if(AlarmConfProfileExt.adslAturThreshold15MinSesL!=0 && current_intvl->AturPerfStatSesL>=AlarmConfProfileExt.adslAturThreshold15MinSesL) - trapsflag|=ATUR_15MIN_SESL_TRAP_FLAG; - if(AlarmConfProfileExt.adslAturThreshold15MinUasL!=0 && current_intvl->AturPerfStatUasL>=AlarmConfProfileExt.adslAturThreshold15MinUasL) - trapsflag|=ATUR_15MIN_UASL_TRAP_FLAG; - copy_to_user((char *)lon, (char *)(&trapsflag), 2); - break; -#endif - -// 603221:tc.chen start - case GET_ADSL_LINE_STATUS: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslLineStatusInfo_pt = (adslLineStatusInfo *)kmalloc(sizeof(adslLineStatusInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslLineStatusInfo_pt, (char *)lon, sizeof(adslLineStatusInfo)); - - if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_MODEM_STATUS_FLAG)){ - LINE_STAT_MODEM_STATUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 0 Index 0"); -#endif - pts.adslLineStatusInfo_pt->adslModemStatus = 0; - } - else{ - pts.adslLineStatusInfo_pt->adslModemStatus = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_MODE_SEL_FLAG)){ - LINE_STAT_MODE_SEL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - pts.adslLineStatusInfo_pt->adslModeSelected = 0; - } - else{ - pts.adslLineStatusInfo_pt->adslModeSelected = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_TRELLCOD_ENABLE_FLAG)){ - LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group OPTN Address 2 Index 0"); -#endif - pts.adslLineStatusInfo_pt->adslTrellisCodeEnable = 0; - } - else{ - - pts.adslLineStatusInfo_pt->adslTrellisCodeEnable = (RxMessage[4]>>13)&0x1==0x1?0:1; - } - } - - if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_LATENCY_FLAG)){ - LINE_STAT_LATENCY_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 12 Index 0"); -#endif - pts.adslLineStatusInfo_pt->adslLatency = 0; - } - else{ - pts.adslLineStatusInfo_pt->adslLatency = RxMessage[4]; - } - } - - copy_to_user((char *)lon, (char *)pts.adslLineStatusInfo_pt, sizeof(adslLineStatusInfo)); - kfree(pts.adslLineStatusInfo_pt); - - up(&mei_sema); - break; - - - case GET_ADSL_LINE_RATE: - if (showtime!=1) - return -ERESTARTSYS; - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslLineRateInfo_pt = (adslLineRateInfo *)kmalloc(sizeof(adslLineRateInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslLineRateInfo_pt, (char *)lon, sizeof(adslLineRateInfo)); - - if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_DATA_RATEDS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - if (chantype.interleave) - LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV; - else - LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group RATE Address 1 Index 0"); -#endif - pts.adslLineRateInfo_pt->adslDataRateds = 0; - } - else{ - pts.adslLineRateInfo_pt->adslDataRateds = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - }else // adsl 2/2+ - { - unsigned long Mp,Lp,Tp,Rp,Kp,Bpn,DataRate,DataRate_remain; - Mp=Lp=Tp=Rp=Kp=Bpn=DataRate=DataRate_remain=0; - //// up stream data rate - - if (chantype.interleave) - { - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 25 Index 0"); -#endif - Lp = 0; - }else - Lp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 23 Index 0"); -#endif - Rp = 0; - }else - Rp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 24 Index 0"); -#endif - Mp = 0; - }else - Mp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 26 Index 0"); -#endif - Tp = 0; - }else - Tp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 28 Index 0"); -#endif - Kp = 0; - }else - { - Kp=RxMessage[4]+ RxMessage[5]+1; - Bpn=RxMessage[4]+ RxMessage[5]; - } - }else - { - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 25 Index 1"); -#endif - Lp = 0; - }else - Lp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 23 Index 1"); -#endif - Rp = 0; - }else - Rp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 24 Index 1"); -#endif - Mp = 0; - }else - Mp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 26 Index 1"); -#endif - Tp = 0; - }else - Tp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 28 Index 2"); -#endif - Kp = 0; - }else - { - Kp=RxMessage[4]+ RxMessage[5]+1; - Bpn=RxMessage[4]+ RxMessage[5]; - } - } - DataRate=((Tp*(Bpn+1)-1)*Mp*Lp*4)/(Tp*(Kp*Mp+Rp)); - //DataRate_remain=((((Tp*(Bpn+1)-1)*Mp*Lp*4)%(Tp*(Kp*Mp+Rp)))*1000)/(Tp*(Kp*Mp+Rp)); - //pts.adslLineRateInfo_pt->adslDataRateds = DataRate * 1000 + DataRate_remain; - pts.adslLineRateInfo_pt->adslDataRateds = DataRate; - } - } - - if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_DATA_RATEUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - if (chantype.interleave) - LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV; - else - LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ - #ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group RATE Address 0 Index 0"); - #endif - pts.adslLineRateInfo_pt->adslDataRateus = 0; - } - else{ - pts.adslLineRateInfo_pt->adslDataRateus = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - }else // adsl 2/2+ - { - unsigned long Mp,Lp,Tp,Rp,Kp,Bpn,DataRate,DataRate_remain; - Mp=Lp=Tp=Rp=Kp=Bpn=DataRate=DataRate_remain=0; - //// down stream data rate - - if (chantype.interleave) - { - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 14 Index 0"); -#endif - Lp = 0; - }else - Lp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 12 Index 0"); -#endif - Rp = 0; - }else - Rp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 13 Index 0"); -#endif - Mp = 0; - }else - Mp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 15 Index 0"); -#endif - Tp = 0; - }else - Tp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 17 Index 0"); -#endif - Kp = 0; - }else - { - Kp=RxMessage[4]+ RxMessage[5]+1; - Bpn=RxMessage[4]+ RxMessage[5]; - } - }else - { - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 14 Index 1"); -#endif - Lp = 0; - }else - Lp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 12 Index 1"); -#endif - Rp = 0; - }else - Rp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 13 Index 1"); -#endif - Mp = 0; - }else - Mp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 15 Index 1"); -#endif - Tp = 0; - }else - Tp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 17 Index 2"); -#endif - Kp = 0; - }else - { - Kp=RxMessage[4]+ RxMessage[5]+1; - Bpn=RxMessage[4]+ RxMessage[5]; - } - } - DataRate=((Tp*(Bpn+1)-1)*Mp*Lp*4)/(Tp*(Kp*Mp+Rp)); - //DataRate_remain=((((Tp*(Bpn+1)-1)*Mp*Lp*4)%(Tp*(Kp*Mp+Rp)))*1000)/(Tp*(Kp*Mp+Rp)); - //pts.adslLineRateInfo_pt->adslDataRateus = DataRate * 1000 + DataRate_remain; - pts.adslLineRateInfo_pt->adslDataRateus = DataRate; - } - } - - if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_ATTNDRDS_FLAG)){ - LINE_RATE_ATTNDRDS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 4"); -#endif - pts.adslLineRateInfo_pt->adslATTNDRds = 0; - } - else{ - pts.adslLineRateInfo_pt->adslATTNDRds = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - - if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_ATTNDRUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - LINE_RATE_ATTNDRUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ - #ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 4"); - #endif - pts.adslLineRateInfo_pt->adslATTNDRus = 0; - } - else{ - pts.adslLineRateInfo_pt->adslATTNDRus = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x24; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_RATE_END; - } - pts.adslLineRateInfo_pt->adslATTNDRus = (u32)le16_to_cpu(hdlc_rx_buffer[1])<<16 | (u32)le16_to_cpu(hdlc_rx_buffer[2]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_RATE_END; - } - } - } - copy_to_user((char *)lon, (char *)pts.adslLineRateInfo_pt, sizeof(adslLineRateInfo)); - up(&mei_sema); - -GET_ADSL_LINE_RATE_END: - kfree(pts.adslLineRateInfo_pt); - break; - - case GET_ADSL_LINE_INFO: - if (showtime!=1) - return -ERESTARTSYS; - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslLineInfo_pt = (adslLineInfo *)kmalloc(sizeof(adslLineInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslLineInfo_pt, (char *)lon, sizeof(adslLineInfo)); - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_INTLV_DEPTHDS_FLAG)){ - if (chantype.interleave) - LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV; - else - LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 27 Index 0"); -#endif - pts.adslLineInfo_pt->adslInterleaveDepthds = 0; - } - else{ - pts.adslLineInfo_pt->adslInterleaveDepthds = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_INTLV_DEPTHUS_FLAG)){ - if (chantype.interleave) - LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV; - else - LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 16 Index 0"); -#endif - pts.adslLineInfo_pt->adslInterleaveDepthus = 0; - } - else{ - pts.adslLineInfo_pt->adslInterleaveDepthus = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_LATNDS_FLAG)){ - LINE_INFO_LATNDS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 1"); -#endif - pts.adslLineInfo_pt->adslLATNds = 0; - } - else{ - pts.adslLineInfo_pt->adslLATNds = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_LATNUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - LINE_INFO_LATNUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 1"); -#endif - pts.adslLineInfo_pt->adslLATNus = 0; - } - else{ - pts.adslLineInfo_pt->adslLATNus = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x21; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslLATNus = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SATNDS_FLAG)){ - LINE_INFO_SATNDS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 2"); -#endif - pts.adslLineInfo_pt->adslSATNds = 0; - } - else{ - pts.adslLineInfo_pt->adslSATNds = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SATNUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - LINE_INFO_SATNUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 2"); -#endif - pts.adslLineInfo_pt->adslSATNus = 0; - } - else{ - pts.adslLineInfo_pt->adslSATNus = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x22; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslSATNus = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SNRMNDS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV; - } - else if ((adsl_mode == 0x4000) || (adsl_mode == 0x8000) || adsl_mode_extend > 0) - { - LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV; - } - else - { - LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV; - } - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 3"); -#endif - pts.adslLineInfo_pt->adslSNRMds = 0; - } - else{ - if (adsl_mode>8 || adsl_mode_extend>0) - { - int SNRMds,SNRMds_remain; - SNRMds=RxMessage[4]; - SNRMds_remain=((SNRMds&0xff)*1000)/256; - SNRMds=(SNRMds>>8)&0xff; - if ((SNRMds_remain%100)>=50) SNRMds_remain=(SNRMds_remain/100)+1; - else SNRMds_remain=(SNRMds_remain/100); - pts.adslLineInfo_pt->adslSNRMds = SNRMds*10 + SNRMds_remain; - }else - { - pts.adslLineInfo_pt->adslSNRMds = RxMessage[4]; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SNRMNUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend == 0) - { - LINE_INFO_SNRMNUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 3"); -#endif - pts.adslLineInfo_pt->adslSNRMus = 0; - } - else{ - pts.adslLineInfo_pt->adslSNRMus = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x23; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslSNRMus = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_ACATPDS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend == 0) - { - LINE_INFO_ACATPDS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ - #ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 6"); - #endif - pts.adslLineInfo_pt->adslACATPds = 0; - } - else{ - pts.adslLineInfo_pt->adslACATPds = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x25; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslACATPds = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_ACATPUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend == 0) - { - LINE_INFO_ACATPUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 6"); -#endif - pts.adslLineInfo_pt->adslACATPus = 0; - } - else{ - pts.adslLineInfo_pt->adslACATPus = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x26; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslACATPus = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - copy_to_user((char *)lon, (char *)pts.adslLineInfo_pt, sizeof(adslLineInfo)); - up(&mei_sema); - -GET_ADSL_LINE_INFO_END: - kfree(pts.adslLineInfo_pt); - break; - - case GET_ADSL_NEAREND_STATS: - if (showtime!=1) - return -ERESTARTSYS; - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslNearEndPerfStats_pt = (adslNearEndPerfStats *)kmalloc(sizeof(adslNearEndPerfStats), GFP_KERNEL); - copy_from_user((char *)pts.adslNearEndPerfStats_pt, (char *)lon, sizeof(adslNearEndPerfStats)); - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_SUPERFRAME_FLAG)){ - NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 20 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslSuperFrames = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslSuperFrames = (u32)(RxMessage[4]); - } - NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 21 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslSuperFrames = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslSuperFrames += (((u32)(RxMessage[4]))<<16); - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOS_FLAG) || - IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOF_FLAG) || - IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LPR_FLAG) || - IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_NCD_FLAG) || - IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LCD_FLAG) ){ - NEAREND_PERF_LOS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 0 Index 0"); -#endif - RxMessage[4] = 0; - } - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOS_FLAG)){ - if( (RxMessage[4]&0x1) == 0x1) - pts.adslNearEndPerfStats_pt->adslneLOS = 1; - else - pts.adslNearEndPerfStats_pt->adslneLOS = 0; - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOF_FLAG)){ - if( (RxMessage[4]&0x2) == 0x2) - pts.adslNearEndPerfStats_pt->adslneLOF = 1; - else - pts.adslNearEndPerfStats_pt->adslneLOF = 0; - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LPR_FLAG)){ - if( (RxMessage[4]&0x4) == 0x4) - pts.adslNearEndPerfStats_pt->adslneLPR = 1; - else - pts.adslNearEndPerfStats_pt->adslneLPR = 0; - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_NCD_FLAG)){ - pts.adslNearEndPerfStats_pt->adslneNCD = (RxMessage[4]>>4)&0x3; - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LCD_FLAG)){ - pts.adslNearEndPerfStats_pt->adslneLCD = (RxMessage[4]>>6)&0x3; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_CRC_FLAG)){ - if (chantype.interleave) - NEAREND_PERF_CRC_FLAG_LP0_MAKECMV; - else - NEAREND_PERF_CRC_FLAG_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 2 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneCRC = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneCRC = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_RSCORR_FLAG)){ - if (chantype.interleave) - NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV; - else - NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 3 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneRSCorr = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneRSCorr = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_FECS_FLAG)){ - NEAREND_PERF_FECS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 6 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneFECS = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneFECS = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_ES_FLAG)){ - NEAREND_PERF_ES_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 7 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneES = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneES = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_SES_FLAG)){ - NEAREND_PERF_SES_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 8 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneSES = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneSES = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOSS_FLAG)){ - NEAREND_PERF_LOSS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 9 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneLOSS = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneLOSS = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_UAS_FLAG)){ - NEAREND_PERF_UAS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 10 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneUAS = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneUAS = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_HECERR_FLAG)){ - if (chantype.bearchannel0) - { - NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV; - }else if (chantype.bearchannel1) - { - NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV; - } - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 11 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneHECErrors = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneHECErrors = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - - copy_to_user((char *)lon, (char *)pts.adslNearEndPerfStats_pt, sizeof(adslNearEndPerfStats)); - kfree(pts.adslNearEndPerfStats_pt); - - up(&mei_sema); - break; - - case GET_ADSL_FAREND_STATS: - - if (showtime!=1) - return -ERESTARTSYS; - - if (adsl_mode>8 || adsl_mode_extend > 0) - { - do_gettimeofday(&time_now); - if( FarendData_acquire_time.tv_sec==0 || time_now.tv_sec - FarendData_acquire_time.tv_sec>=1) - { - hdlc_cmd[0]=0x105; - - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],2)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - return -ERESTARTSYS; - } - FarendStatsData.adslfeRSCorr = ((u32)le16_to_cpu(hdlc_rx_buffer[1]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[2]); - FarendStatsData.adslfeCRC = ((u32)le16_to_cpu(hdlc_rx_buffer[3]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[4]); - FarendStatsData.adslfeFECS = ((u32)le16_to_cpu(hdlc_rx_buffer[5]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[6]); - FarendStatsData.adslfeES = ((u32)le16_to_cpu(hdlc_rx_buffer[7]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[8]); - FarendStatsData.adslfeSES = ((u32)le16_to_cpu(hdlc_rx_buffer[9]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[10]); - FarendStatsData.adslfeLOSS = ((u32)le16_to_cpu(hdlc_rx_buffer[11]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[12]); - FarendStatsData.adslfeUAS = ((u32)le16_to_cpu(hdlc_rx_buffer[13]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[14]); - do_gettimeofday(&FarendData_acquire_time); - } - - } - } - - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - pts.adslFarEndPerfStats_pt = (adslFarEndPerfStats *)kmalloc(sizeof(adslFarEndPerfStats), GFP_KERNEL); - copy_from_user((char *)pts.adslFarEndPerfStats_pt, (char *)lon, sizeof(adslFarEndPerfStats)); - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOS_FLAG) || - IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOF_FLAG) || - IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LPR_FLAG) || - IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_NCD_FLAG) || - IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LCD_FLAG) ){ - FAREND_PERF_LOS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 1 Index 0"); -#endif - RxMessage[4] = 0; - } - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOS_FLAG)){ - if((RxMessage[4]&0x1) == 0x1) - pts.adslFarEndPerfStats_pt->adslfeLOS = 1; - else - pts.adslFarEndPerfStats_pt->adslfeLOS = 0; - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOF_FLAG)){ - if((RxMessage[4]&0x2) == 0x2) - pts.adslFarEndPerfStats_pt->adslfeLOF = 1; - else - pts.adslFarEndPerfStats_pt->adslfeLOF = 0; - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LPR_FLAG)){ - if((RxMessage[4]&0x4) == 0x4) - pts.adslFarEndPerfStats_pt->adslfeLPR = 1; - else - pts.adslFarEndPerfStats_pt->adslfeLPR = 0; - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_NCD_FLAG)){ - pts.adslFarEndPerfStats_pt->adslfeNCD = (RxMessage[4]>>4)&0x3; - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LCD_FLAG)){ - pts.adslFarEndPerfStats_pt->adslfeLCD = (RxMessage[4]>>6)&0x3; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_CRC_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - if (chantype.interleave) - { - FAREND_PERF_CRC_FLAG_LP0_MAKECMV; - } - else - { - FAREND_PERF_CRC_FLAG_LP1_MAKECMV; - } - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 24 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeCRC = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeCRC = RxMessage[4]; - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeCRC = FarendStatsData.adslfeCRC; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_RSCORR_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - if (chantype.interleave) - FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV; - else - FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 28 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeRSCorr = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeRSCorr = RxMessage[4]; - - } - } - else - { - pts.adslFarEndPerfStats_pt->adslfeRSCorr = FarendStatsData.adslfeRSCorr; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_FECS_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_FECS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 32 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeFECS = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeFECS = RxMessage[4]; - } - }else { - pts.adslFarEndPerfStats_pt->adslfeFECS = FarendStatsData.adslfeFECS; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_ES_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_ES_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 33 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeES = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeES = RxMessage[4]; - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeES = FarendStatsData.adslfeES; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_SES_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_SES_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 34 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeSES = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeSES = RxMessage[4]; - - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeSES = FarendStatsData.adslfeSES; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOSS_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_LOSS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeLOSS = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeLOSS = RxMessage[4]; - - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeLOSS = FarendStatsData.adslfeLOSS; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_UAS_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_UAS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 36 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeUAS = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeUAS = RxMessage[4]; - - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeUAS = FarendStatsData.adslfeUAS; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_HECERR_FLAG)){ - if (chantype.bearchannel0) - { - FAREND_PERF_HECERR_FLAG_BC0_MAKECMV; - }else if (chantype.bearchannel1) - { - FAREND_PERF_HECERR_FLAG_BC1_MAKECMV; - } - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 37 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeHECErrors = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeHECErrors = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - - copy_to_user((char *)lon, (char *)pts.adslFarEndPerfStats_pt, sizeof(adslFarEndPerfStats)); - kfree(pts.adslFarEndPerfStats_pt); - - up(&mei_sema); - - break; -// 603221:tc.chen end - case GET_ADSL_LOOP_DIAGNOSTICS_MODE: - //lon = loop_diagnostics_mode; - copy_to_user((char *)lon, (char *)&loop_diagnostics_mode, sizeof(int)); - break; -//>> SHC - case IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE: - copy_to_user((char *)lon, (char *)&loop_diagnostics_completed, sizeof(int)); - break; - -//<< end SHC - case LOOP_DIAGNOSTIC_MODE_COMPLETE: - loop_diagnostics_completed = 1; - // read adsl mode - makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - } - adsl_mode = RxMessage[4]; - - makeCMV(H2D_CMV_READ, STAT, 17, 0, 1, data); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - } - adsl_mode_extend = RxMessage[4]; - wake_up_interruptible(&wait_queue_loop_diagnostic); - break; - case SET_ADSL_LOOP_DIAGNOSTICS_MODE: - if (lon != loop_diagnostics_mode) - { - loop_diagnostics_completed = 0; - loop_diagnostics_mode = lon; - - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_REBOOT, NULL); - - } - break; - case GET_ADSL_ATUR_SUBCARRIER_STATS: - if (loop_diagnostics_completed == 0) - { - interruptible_sleep_on_timeout(&wait_queue_loop_diagnostic,300*HZ); - if (loop_diagnostics_completed==0) - { - return -ERESTARTSYS; - } - } - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslATURSubcarrierInfo_pt = (adslATURSubcarrierInfo *)kmalloc(sizeof(adslATURSubcarrierInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslATURSubcarrierInfo_pt, (char *)lon, sizeof(adslATURSubcarrierInfo)); - - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLINSC)){ - FAREND_HLINSC_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslATURSubcarrierInfo_pt->HLINSCds = 0; - } - else{ - pts.adslATURSubcarrierInfo_pt->HLINSCds = RxMessage[4]; - - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLINPS)){ - int index=0,size=12; - //printk("FAREND_HLINPS\n"); - for (index=0;index<1024;index+=size) - { - if (index+size>=1024) - size = 1024-index; - FAREND_HLINPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - memcpy(&pts.adslATURSubcarrierInfo_pt->HLINpsds[index],&RxMessage[4],size*2); -#if 0 - int msg_idx; - for(msg_idx=0;msg_idxflags)), FAREND_HLOGMT)){ - FAREND_HLOGMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslATURSubcarrierInfo_pt->HLOGMTds = 0; - } - else{ - pts.adslATURSubcarrierInfo_pt->HLOGMTds = RxMessage[4]; - - } - } - - ///////////////////////////////////////////////////////////////////////// - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLOGPS)){ - //printk("FAREND_HLOGPS\n"); - int index=0,size=12; - for (index=0;index<256;index+=size) - { - if (index+size>=256) - size = 256-index; - - FAREND_HLOGPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - if (adsl_mode < 0x4000 && adsl_mode_extend==0)//adsl2 mode - { - memcpy(&pts.adslATURSubcarrierInfo_pt->HLOGpsds[index],&RxMessage[4],size*2); - }else - { - int msg_idx=0; - for (msg_idx=0;msg_idxHLOGpsds[(index+msg_idx)*2+1] = RxMessage[4+msg_idx]; - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - } - } - } - if (adsl_mode >= 0x4000 || adsl_mode_extend >0)//adsl2+ mode - { - pts.adslATURSubcarrierInfo_pt->HLOGpsds[0] = pts.adslATURSubcarrierInfo_pt->HLOGpsds[1]; - for (index=1;index<256;index++) - { - pts.adslATURSubcarrierInfo_pt->HLOGpsds[index*2] = (pts.adslATURSubcarrierInfo_pt->HLOGpsds[(index)*2-1] + pts.adslATURSubcarrierInfo_pt->HLOGpsds[(index)*2+1] +1) >>1; - } - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_QLNMT)){ - FAREND_QLNMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslATURSubcarrierInfo_pt->QLNMTds = 0; - } - else{ - pts.adslATURSubcarrierInfo_pt->QLNMTds = RxMessage[4]; - } - } - - ///////////////////////////////////////////////////////////////////////// - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_QLNPS)){ - int index=0,size=12; - //printk("FAREND_QLNPS\n"); - for (index=0;index<128;index+=size) - { - if (index+size>=128) - size = 128-index; - FAREND_QLNPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - int msg_idx=0; - for (msg_idx=0;msg_idxQLNpsds[index],&RxMessage[4],size*2); - if (adsl_mode < 0x4000 && adsl_mode_extend==0)//adsl2 mode - { - pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - }else - { - pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*4+1] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*4+3] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - } - - - } - } - if (adsl_mode >= 0x4000 || adsl_mode_extend >0)//adsl2+ mode - { - pts.adslATURSubcarrierInfo_pt->QLNpsds[0] = pts.adslATURSubcarrierInfo_pt->QLNpsds[1]; - for (index=1;index<256;index++) - { - pts.adslATURSubcarrierInfo_pt->QLNpsds[index*2] = (pts.adslATURSubcarrierInfo_pt->QLNpsds[(index)*2-1] + pts.adslATURSubcarrierInfo_pt->QLNpsds[(index)*2+1]) >>1; - } - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_SNRMT)){ - FAREND_SNRMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslATURSubcarrierInfo_pt->SNRMTds = 0; - } - else{ - pts.adslATURSubcarrierInfo_pt->SNRMTds = RxMessage[4]; - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_SNRPS)){ - int index=0,size=12; - //printk("FAREND_SNRPS\n"); - for (index=0;index<512;index+=size) - { - if (index+size>=512) - size = 512-index; - FAREND_SNRPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - //memcpy(&pts.adslATURSubcarrierInfo_pt->SNRpsds[index],&RxMessage[4],size*2); - int msg_idx=0; - for (msg_idx=0;msg_idxSNRpsds[index+msg_idx] = (u16)(RxMessage[4+msg_idx]&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - - } - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_BITPS)){ - int index=0,size=12; - //printk("FAREND_BITPS\n"); - for (index=0;index<256;index+=size) - { - if (index+size>=256) - size = 256-index; - FAREND_BITPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - int msg_idx=0; - for (msg_idx=0;msg_idxBITpsds[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATURSubcarrierInfo_pt->BITpsds[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - //printk("index:%d ,cmv_result: %04X, %d\n",index+msg_idx,RxMessage[4+msg_idx],RxMessage[4+msg_idx]); - - } - - } - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_GAINPS)){ - int index=0,size=12; - //printk("FAREND_GAINPS\n"); - for (index=0;index<512;index+=size) - { - FAREND_GAINPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - /* - int msg_idx=0; - for (msg_idx=0;msg_idxGAINpsds[(index+msg_idx)*2] = RxMessage[4+msg_idx]&0xFF; - pts.adslATURSubcarrierInfo_pt->GAINpsds[(index+msg_idx)*2+1] = (RxMessage[4+msg_idx]>>8)&0xFF; - - } - */ - memcpy(&pts.adslATURSubcarrierInfo_pt->GAINpsds[index],&RxMessage[4],size*2); -#if 0 - int msg_idx=0; - for (msg_idx=0;msg_idxflags)), NEAREND_HLINSC)){ - NEAREND_HLINSC_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 71 Index 2"); -#endif - pts.adslATUCSubcarrierInfo_pt->HLINSCus = 0; - } - else{ - pts.adslATUCSubcarrierInfo_pt->HLINSCus = RxMessage[4]; - - } - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_HLINPS)){ - int index=0,size=12; - //printk("NEAREND_HLINPS\n"); - for (index=0;index<128;index+=size) - { - if (index+size>=128) - size = 128-index; - NEAREND_HLINPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 73 Index 0"); -#endif - } - else{ - memcpy(&pts.adslATUCSubcarrierInfo_pt->HLINpsus[index],&RxMessage[4],size*2); -#if 0 - int msg_idx; - for (msg_idx=0;msg_idxflags)), NEAREND_HLOGMT)){ - NEAREND_HLOGMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 80 Index 0"); -#endif - pts.adslATUCSubcarrierInfo_pt->HLOGMTus = 0; - } - else{ - pts.adslATUCSubcarrierInfo_pt->HLOGMTus = RxMessage[4]; - - } - } - - ///////////////////////////////////////////////////////////////////////// - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_HLOGPS)){ - int index=0,size=12; - //printk("NEAREND_HLOGPS\n"); - for (index=0;index<64;index+=size) - { - if (index+size>=64) - size = 64-index; - NEAREND_HLOGPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 75 Index 0"); -#endif - } - else{ -#if 0 - if (adsl_mode <0x4000)//adsl /adsl2 mode - { -#endif - memcpy(&pts.adslATUCSubcarrierInfo_pt->HLOGpsus[index],&RxMessage[4],size*2); -#if 0 - }else - { - int msg_idx=0; - for (msg_idx=0;msg_idxHLOGpsus[(index+msg_idx)*2+1] = RxMessage[4+msg_idx]; - pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index+msg_idx)] = RxMessage[4+msg_idx]; - } - } -#endif - } - } -#if 0 - if (adsl_mode >= 0x4000)//adsl2 mode - { - pts.adslATUCSubcarrierInfo_pt->HLOGpsus[0] = pts.adslATUCSubcarrierInfo_pt->HLOGpsus[1]; - for (index=1;index<64;index++) - { - pts.adslATUCSubcarrierInfo_pt->HLOGpsus[index*2] = (pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index)*2-1] + pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index)*2+1]) >>1; - } - } -#endif - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_QLNMT)){ - NEAREND_QLNMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 80 Index 1"); -#endif - pts.adslATUCSubcarrierInfo_pt->QLNMTus = 0; - } - else{ - pts.adslATUCSubcarrierInfo_pt->QLNMTus = RxMessage[4]; - } - } - - ///////////////////////////////////////////////////////////////////////// - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_QLNPS)){ - int index=0,size=12; - //printk("NEAREND_QLNPS\n"); - for (index=0;index<32;index+=size) - { - if (index+size>=32) - size = 32-index; - NEAREND_QLNPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 77 Index 0"); -#endif - } - else{ - int msg_idx=0; - for (msg_idx=0;msg_idxQLNpsds[index],&RxMessage[4],size*2); - if (adsl_mode == 0x200 || adsl_mode == 0x800 || adsl_mode ==0x2000 || adsl_mode ==0x4000 || (adsl_mode == 0 && (adsl_mode_extend == 0x4 || adsl_mode_extend == 0x2))//ADSL 2 Annex B(0x200)/J(0x800)/M(0x2000) //ADSL 2+ B,J,M - if (adsl_mode < 0x4000 && adsl_mode_extend==0)//adsl2 mode - { - pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*4+1] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*4+3] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - }else -#endif - { - pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - } - - - } - } -#if 0 - //if (adsl_mode <0x4000)//Annex I/J/L/M - if (adsl_mode == 0x200 || adsl_mode == 0x800 || adsl_mode ==0x2000 || adsl_mode ==0x4000 || (adsl_mode == 0 && (adsl_mode_extend == 0x4 || adsl_mode_extend == 0x2))//ADSL 2 Annex B(0x200)/J(0x800)/M(0x2000) //ADSL 2+ B,J,M - { - pts.adslATUCSubcarrierInfo_pt->QLNpsus[0] = pts.adslATUCSubcarrierInfo_pt->QLNpsus[1]; - for (index=1;index<64;index++) - { - pts.adslATUCSubcarrierInfo_pt->QLNpsus[index*2] = (pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index)*2-1] + pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index)*2+1]) >>1; - } - } -#endif - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_SNRMT)){ - NEAREND_SNRMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 80 Index 2"); -#endif - pts.adslATUCSubcarrierInfo_pt->SNRMTus = 0; - } - else{ - pts.adslATUCSubcarrierInfo_pt->SNRMTus = RxMessage[4]; - } - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_SNRPS)){ - int index=0,size=12; - //printk("NEAREND_SNRPS\n"); - for (index=0;index<64;index+=size) - { - if (index+size>=64) - size = 64-index; - NEAREND_SNRPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 78 Index 0"); -#endif - } - else{ - //memcpy(&pts.adslATUCSubcarrierInfo_pt->SNRpsus[index],&RxMessage[4],size*2); - int msg_idx=0; - for (msg_idx=0;msg_idxSNRpsus[index+msg_idx] = (u16)(RxMessage[4+msg_idx]&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - - } - } - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_BITPS)){ - int index=0,size=12; - //printk("NEAREND_BITPS\n"); - for (index=0;index<32;index+=size) - { - if (index+size>=32) - size = 32-index; - NEAREND_BITPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 22 Index 0"); -#endif - } - else{ - int msg_idx=0; - for (msg_idx=0;msg_idxBITpsus[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATUCSubcarrierInfo_pt->BITpsus[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - - } - } - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_GAINPS)){ - int index=0,size=12; - //printk("NEAREND_GAINPS\n"); - for (index=0;index<64;index+=size) - { - if (index+size>=64) - size = 64-index; - NEAREND_GAINPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 24 Index 0"); -#endif - } - else{ - /* - int msg_idx=0; - for (msg_idx=0;msg_idxGAINpsds[(index+msg_idx)*2] = RxMessage[4+msg_idx]&0xFF; - pts.adslATUCSubcarrierInfo_pt->GAINpsds[(index+msg_idx)*2+1] = (RxMessage[4+msg_idx]>>8)&0xFF; - - } - */ - memcpy(&pts.adslATUCSubcarrierInfo_pt->GAINpsus[index],&RxMessage[4],size*2); -#if 0 - int msg_idx; - for (msg_idx=0;msg_idxACTPSDus = ((int )(j*256 - temp*10*256 + k*10)) /256; - } - // DS - i=0; - j=temp=temp2=0; - NOMPSD_DS_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - i=-1; - } - else{ - j=RxMessage[4]; - } - PCB_DS_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - i=-1; - } - else{ - temp=RxMessage[4]; - } - RMSGI_DS_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - i=-1; - } - else{ - //temp2=RxMessage[4]; - k=(int16_t)RxMessage[4]; - } - if (i==0) - { - pts.adslPowerSpectralDensity_pt->ACTPSDds = ((int )(j*256 - temp*10*256 + k*10)) /256; - } - copy_to_user((char *)lon, (char *)pts.adslPowerSpectralDensity_pt, sizeof(adslPowerSpectralDensity)); - kfree(pts.adslPowerSpectralDensity_pt); - up(&mei_sema); - break; - case AMAZON_MEI_START: - showtime=0; - loop_diagnostics_completed = 0; -#ifdef ARC_READY_ACK -#ifdef LOCK_RETRY - i=0; -lock_retry: - if(down_trylock(&mei_sema)!=0) - { - reboot_lock = 1; - printk("lock fail\n"); - i++; - if (i <=5) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(10); - goto lock_retry; - }else - { - printk("Force to Reboot ADSL!\n"); - up(&mei_sema); - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1000); - sema_init(&mei_sema, 1); // semaphore initialization, mutex - } - }else - { - reboot_lock = 1; - } -#else - if(down_interruptible(&mei_sema)) //disable CMV access until ARC ready - { - return -ERESTARTSYS; - } -#endif -#endif - //CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON - if(chantype.interleave==1){ - kfree(interleave_mei_net.priv); - unregister_netdev(&interleave_mei_net); - } - else if(chantype.fast==1){ - kfree(fast_mei_net.priv); - unregister_netdev(&fast_mei_net); - } - chantype.interleave=0; - chantype.fast=0; - meiMailboxInterruptsDisable(); //disable all MEI interrupts - if(mei_arc_swap_buff == NULL){ - mei_arc_swap_buff = (u32 *)kmalloc(MAXSWAPSIZE*4, GFP_KERNEL); - if(mei_arc_swap_buff==NULL){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n malloc fail for codeswap buff"); -#endif - meierr=MEI_FAILURE; - } - } - if(meiForceRebootAdslModem() != MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n meiForceRebootAdslModem() error..."); -#endif - meierr=MEI_FAILURE; - } - interruptible_sleep_on(&wait_queue_codeswap); - // reset is called - break; - case AMAZON_MEI_MIB_DAEMON: -#ifdef IFX_SMALL_FOOTPRINT /* [ */ - return -1; -#else /* ][ !IFX_SMALL_FOOTPRINT */ - i=0; - while(1){ - if(istart_time.tv_sec>=900){ - if(current_intvl->list.next!=&interval_list){ - current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list); - do_gettimeofday(&(current_intvl->start_time)); - } - else{ - mib_ptr = list_entry(interval_list.next, amazon_mei_mib, list); - list_del(interval_list.next); - memset(mib_ptr, 0, sizeof(amazon_mei_mib)); - list_add_tail(&(mib_ptr->list), &interval_list); - if(current_intvl->list.next==&interval_list) -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nlink list error"); -#endif - current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list); - do_gettimeofday(&(current_intvl->start_time)); - } - } - - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; -/* - ATUC_PERF_LO_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 0 Index 0"); -#endif - } - else{ - if(RxMessage[4]&PLAM_LOS_FailureBit){ - current_intvl->AtucPerfLos++; - ATUC_PERF_LOSS++; - CurrStatus.adslAtucCurrStatus = 2; - } - if(RxMessage[4]&PLAM_LOF_FailureBit){ - current_intvl->AtucPerfLof++; - ATUC_PERF_LOFS++; - CurrStatus.adslAtucCurrStatus = 1; - } - if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit))) - CurrStatus.adslAtucCurrStatus = 0; - } -*/ - ATUC_PERF_ESS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 7 Index 0"); -#endif - } - else{ - temp = RxMessage[4]-mib_pread.ATUC_PERF_ESS; - if(temp>=0){ - current_intvl->AtucPerfEs+=temp; - ATUC_PERF_ESS+=temp; - mib_pread.ATUC_PERF_ESS = RxMessage[4]; - } - else{ - current_intvl->AtucPerfEs+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4]; - ATUC_PERF_ESS+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4]; - mib_pread.ATUC_PERF_ESS = RxMessage[4]; - } - } -/* - ATUR_PERF_LO_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 1 Index 0"); -#endif - } - else{ - if(RxMessage[4]&PLAM_LOS_FailureBit){ - current_intvl->AturPerfLos++; - ATUR_PERF_LOSS++; - CurrStatus.adslAturCurrStatus = 2; - } - if(RxMessage[4]&PLAM_LOF_FailureBit){ - current_intvl->AturPerfLof++; - ATUR_PERF_LOFS++; - CurrStatus.adslAturCurrStatus = 1; - } - if(RxMessage[4]&PLAM_LPR_FailureBit){ - current_intvl->AturPerfLpr++; - ATUR_PERF_LPR++; - CurrStatus.adslAturCurrStatus = 3; - } - if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit|PLAM_LPR_FailureBit))) - CurrStatus.adslAturCurrStatus = 0; - } -*/ - ATUR_PERF_ESS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 33 Index 0"); -#endif - } - else{ - temp = RxMessage[4]-mib_pread.ATUR_PERF_ESS; - if(temp>=0){ - current_intvl->AturPerfEs+=temp; - ATUR_PERF_ESS+=temp; - mib_pread.ATUR_PERF_ESS = RxMessage[4]; - } - else{ - current_intvl->AturPerfEs+=0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4]; - ATUR_PERF_ESS+= 0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4]; - mib_pread.ATUR_PERF_ESS=RxMessage[4]; - } - } - // to update rx/tx blocks - ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 20 Index 0"); -#endif - } - else{ - temp = RxMessage[4]; - } - ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 21 Index 0"); -#endif - } - else{ - temp2 = RxMessage[4]; - } - if((temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK)>=0){ - current_intvl->AturChanPerfRxBlk+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK; - ATUR_CHAN_RECV_BLK+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK; - mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16); - } - else{ - current_intvl->AturChanPerfRxBlk+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16)); - ATUR_CHAN_RECV_BLK+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16)); - mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16); - } - current_intvl->AturChanPerfTxBlk = current_intvl->AturChanPerfRxBlk; - ATUR_CHAN_TX_BLK = ATUR_CHAN_RECV_BLK; -/* - ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS) - printk("\n\nCMV fail, Group 7 Address 20 Index 0"); - else{ - if(RxMessage[4]){ - current_intvl->AturChanPerfTxBlk+=RxMessage[4]; - ATUR_CHAN_TX_BLK+=RxMessage[4]; - } - } - ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS) - printk("\n\nCMV fail, Group 7 Address 21 Index 0"); - else{ - if(RxMessage[4]){ - current_intvl->AturChanPerfTxBlk+=(int)((RxMessage[4])<<16); - ATUR_CHAN_TX_BLK+=(int)((RxMessage[4])<<16); - } - } -*/ - if(chantype.interleave == 1){ - ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 3 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_INTL; - if(temp>=0){ - current_intvl->AturChanPerfCorrBlk+=temp; - ATUR_CHAN_CORR_BLK+=temp; - mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4]; - ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4]; - mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4]; - } - } - } - else if(chantype.fast == 1){ - ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 3 Index 1"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_FAST; - if(temp>=0){ - current_intvl->AturChanPerfCorrBlk+=temp; - ATUR_CHAN_CORR_BLK+=temp; - mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4]; - ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4]; - mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4]; - } - } - } - - if(chantype.interleave == 1){ - ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 2 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL; - if(temp>=0){ - current_intvl->AturChanPerfUncorrBlk+=temp; - ATUR_CHAN_UNCORR_BLK+=temp; - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4]; - ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4]; - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4]; - } - } - } - else if(chantype.fast == 1){ - ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 2 Index 1"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST; - if(temp>=0){ - current_intvl->AturChanPerfUncorrBlk+=temp; - ATUR_CHAN_UNCORR_BLK+=temp; - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4]; - ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4]; - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4]; - } - } - } - - //RFC-3440 - -#ifdef AMAZON_MEI_MIB_RFC3440 - ATUC_PERF_STAT_FASTR_FLAG_MAKECMV; //??? - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 0 Address 0 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FASTR; - if(temp>=0){ - current_intvl->AtucPerfStatFastR+=temp; - ATUC_PERF_STAT_FASTR+=temp; - mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4]; - ATUC_PERF_STAT_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4]; - } - } - ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV; //??? - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 0 Address 0 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FAILED_FASTR; - if(temp>=0){ - current_intvl->AtucPerfStatFailedFastR+=temp; - ATUC_PERF_STAT_FAILED_FASTR+=temp; - mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatFailedFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4]; - ATUC_PERF_STAT_FAILED_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4]; - } - } - ATUC_PERF_STAT_SESL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 8 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_SESL; - if(temp>=0){ - current_intvl->AtucPerfStatSesL+=temp; - ATUC_PERF_STAT_SESL+=temp; - mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatSesL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4]; - ATUC_PERF_STAT_SESL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4]; - } - } - ATUC_PERF_STAT_UASL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 10 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_UASL; - if(temp>=0){ - current_intvl->AtucPerfStatUasL+=temp; - ATUC_PERF_STAT_UASL+=temp; - mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4]; - ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4]; - } - } - ATUR_PERF_STAT_SESL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 34 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_PERF_STAT_SESL; - if(temp>=0){ - current_intvl->AtucPerfStatUasL+=temp; - ATUC_PERF_STAT_UASL+=temp; - mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4]; - ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4]; - mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4]; - } - } - -#endif - up(&mei_sema); - - do_gettimeofday(&time_fini); - i = ((int)((time_fini.tv_sec-time_now.tv_sec)*1000)) + ((int)((time_fini.tv_usec-time_now.tv_usec)/1000)) ; //msec - }//showtime==1 - } - break; -#endif /* ] !IFX_SMALL_FOOTPRINT */ - case AMAZON_MEI_RESET: - case AMAZON_MEI_REBOOT: - case AMAZON_MEI_SHOWTIME: -/* if(mei_arc_swap_buff !=NULL){ - kfree(mei_arc_swap_buff); - mei_arc_swap_buff=NULL; - } - if(image_buffer !=NULL){ -// kfree(image_buffer); - vfree(image_buffer); - image_buffer =NULL; - } -*/ - if(clreoc_command_pkt !=NULL){ - kfree(clreoc_command_pkt); - clreoc_command_pkt =NULL; - } - for(i=0;istart_time)); - ATUC_PERF_LOFS=0; - ATUC_PERF_LOSS=0; - ATUC_PERF_ESS=0; - ATUC_PERF_INITS=0; - ATUR_PERF_LOFS=0; - ATUR_PERF_LOSS=0; - ATUR_PERF_LPR=0; - ATUR_PERF_ESS=0; - ATUR_CHAN_RECV_BLK=0; - ATUR_CHAN_TX_BLK=0; - ATUR_CHAN_CORR_BLK=0; - ATUR_CHAN_UNCORR_BLK=0; - memset((((u8 *)&AlarmConfProfile)+32), 0, 16*4); - AlarmConfProfile.adslLineAlarmConfProfileRowStatus=1; -*/ - PrevTxRate.adslAtucChanPrevTxRate=0; - PrevTxRate.adslAturChanPrevTxRate=0; - CurrStatus.adslAtucCurrStatus=0; - CurrStatus.adslAturCurrStatus=0; - - if((command==AMAZON_MEI_RESET) || (command==AMAZON_MEI_REBOOT)){ -#ifdef AMAZON_CHECK_LINK - if (adsl_link_notify){ - (*adsl_link_notify)(0); - } -#endif - showtime=0; - //CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON - // disconnect net_dev - if(chantype.interleave==1){ - kfree(interleave_mei_net.priv); - unregister_netdev(&interleave_mei_net); -// if(unregister_netdev(&interleave_mei_net)!=0) -// printk("\n unregister interleave fail"); - } - else if(chantype.fast==1){ - kfree(fast_mei_net.priv); - unregister_netdev(&fast_mei_net); -// if(unregister_netdev(&fast_mei_net)!=0) -// printk("\n unregister fast fail"); - } - chantype.interleave=0; - chantype.fast=0; -// 603221:tc.chen start - chantype.bearchannel0 = 0; - chantype.bearchannel1 = 0; - adsl_mode = 0; -// 603221:tc.chen end - - while(1){ - - makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, NULL); //maximum allowed tx message length, in bytes - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ - //printk("AdslInitStatsData.FullInitializationCount++\n"); - AdslInitStatsData.FullInitializationCount++; - //printk("AdslInitStatsData.FailedFullInitializationCount++\n"); - AdslInitStatsData.FailedFullInitializationCount++; - //printk("AdslInitStatsData.LINIT_Errors++\n"); - AdslInitStatsData.LINIT_Errors++; - }else - { - //printk("RxMessage=%X\n",RxMessage[4]); - if ( RxMessage[4]!=0x1) - { - //printk("AdslInitStatsData.FullInitializationCount++\n"); - AdslInitStatsData.FullInitializationCount++; - if ( RxMessage[4] != 0x7) - { - //printk("AdslInitStatsData.LINIT_Errors++\n"); - AdslInitStatsData.LINIT_Errors++; - //printk("AdslInitStatsData.FailedFullInitializationCount++\n"); - AdslInitStatsData.FailedFullInitializationCount++; - - } - } - } - - reboot_flag=0; - wake_up_interruptible(&wait_queue_codeswap); //wake up codeswap daemon - - interruptible_sleep_on_timeout(&wait_queue_reboot, 1*HZ); // sleep until arc ready -#ifdef ARC_READY_ACK - if(reboot_flag!=0) - break; - else - { - up(&mei_sema); - printk("\n reboot retry"); - } -#else - break; -#endif - } - } - else{ //AMAZON_MEI_SHOWTIME - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - // clreoc stuff - makeCMV(H2D_CMV_READ, INFO, 83, 0, 1, data); //maximum allowed tx message length, in bytes - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 83 Index 0"); -#endif - } - else{ - clreoc_max_tx_len = (int)RxMessage[4]; - clreoc_command_pkt = kmalloc((clreoc_max_tx_len*CLREOC_BUFF_SIZE), GFP_KERNEL); - if(clreoc_command_pkt == NULL){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("kmalloc error for clreoc_command_pkt\n\n"); -#endif - up(&mei_sema); - return -1; - } - for(i=0;ilen)>0){ - copy_to_user((char *)lon, (char*)(&(current_clreoc->len)), 4); - break; - } - else//wait for eoc data from higher layer - interruptible_sleep_on(&wait_queue_clreoc); - } - break; - case AMAZON_MEI_GET_EOC_DATA: - current_clreoc = list_entry(clreoc_list.next, amazon_clreoc_pkt, list); - if((current_clreoc->len)>0){ - copy_to_user((char*)lon, (char*)(current_clreoc->command), current_clreoc->len); - meierr=1; - list_del(clreoc_list.next); //remove and add to end of list - current_clreoc->len = 0; - list_add_tail(&(current_clreoc->list), &clreoc_list); - } - else - meierr=-1; - break; - case AMAZON_MEI_EOC_SEND: - copy_from_user((char *)(&debugrdwr), (char *)lon, sizeof(debugrdwr)); - eoc_skb = dev_alloc_skb(debugrdwr.iCount*4); - if(eoc_skb==NULL){ - printk("\n\nskb alloc fail"); - break; - } - - eoc_skb->len=debugrdwr.iCount*4; - memcpy(skb_put(eoc_skb, debugrdwr.iCount*4), (char *)debugrdwr.buffer, debugrdwr.iCount*4); - - ifx_push_eoc(eoc_skb); //pass data to higher layer - break; -#endif //#ifdef AMAZON_CLEAR_EOC - case AMAZON_MIB_LO_ATUC: - do_gettimeofday(&time_now); - if(lon&0x1){ - if((time_now.tv_sec-(mib_pflagtime.ATUC_PERF_LOSS_PTIME).tv_sec)>2){ - current_intvl->AtucPerfLos++; - ATUC_PERF_LOSS++; - CurrStatus.adslAtucCurrStatus = 2; - } - (mib_pflagtime.ATUC_PERF_LOSS_PTIME).tv_sec = time_now.tv_sec; - } - if(lon&0x2){ - if((time_now.tv_sec-(mib_pflagtime.ATUC_PERF_LOFS_PTIME).tv_sec)>2){ - current_intvl->AtucPerfLof++; - ATUC_PERF_LOFS++; - CurrStatus.adslAtucCurrStatus = 1; - } - (mib_pflagtime.ATUC_PERF_LOFS_PTIME).tv_sec = time_now.tv_sec; - } - if(!(lon&0x3)) - CurrStatus.adslAtucCurrStatus = 0; - break; - case AMAZON_MIB_LO_ATUR: - do_gettimeofday(&time_now); - if(lon&0x1){ - if((time_now.tv_sec-(mib_pflagtime.ATUR_PERF_LOSS_PTIME).tv_sec)>2){ - current_intvl->AturPerfLos++; - ATUR_PERF_LOSS++; - CurrStatus.adslAturCurrStatus = 2; - } - (mib_pflagtime.ATUR_PERF_LOSS_PTIME).tv_sec = time_now.tv_sec; - } - if(lon&0x2){ - if((time_now.tv_sec-(mib_pflagtime.ATUR_PERF_LOFS_PTIME).tv_sec)>2){ - current_intvl->AturPerfLof++; - ATUR_PERF_LOFS++; - CurrStatus.adslAturCurrStatus = 1; - } - (mib_pflagtime.ATUR_PERF_LOFS_PTIME).tv_sec = time_now.tv_sec; - } - if(lon&0x4){ - if((time_now.tv_sec-(mib_pflagtime.ATUR_PERF_LPR_PTIME).tv_sec)>2){ - current_intvl->AturPerfLpr++; - ATUR_PERF_LPR++; - CurrStatus.adslAturCurrStatus = 3; - } - (mib_pflagtime.ATUR_PERF_LPR_PTIME).tv_sec = time_now.tv_sec; - } - if(!(lon&0x7)) - CurrStatus.adslAturCurrStatus = 0; - break; - case AMAZON_MEI_DOWNLOAD: - // DMA the boot code page(s) -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n start download pages"); -#endif - for( boot_loop = 0; boot_loop < img_hdr->count; boot_loop++){ - if( img_hdr->page[boot_loop].p_size & BOOT_FLAG){ - page_size = meiGetPage( boot_loop, GET_PROG, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( page_size > 0){ - meiDMAWrite(dest_addr, mei_arc_swap_buff, page_size); - } - } - if( img_hdr->page[boot_loop].d_size & BOOT_FLAG){ - page_size = meiGetPage( boot_loop, GET_DATA, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( page_size > 0){ - meiDMAWrite( dest_addr, mei_arc_swap_buff, page_size); - } - } - } -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n pages downloaded"); -#endif - break; - //509221:tc.chen start - case AMAZON_MEI_DEBUG_MODE: - mei_debug_mode = lon; - break; - //509221:tc.chen end - } - return meierr; -} - - -////////////////////// Interrupt handler ///////////////////////////////////////////////////// -static void mei_interrupt_arcmsgav(int,void *,struct pt_regs *); -static void mei_interrupt_arcmsgav(int int1, void * void0, struct pt_regs * regs) -{ - u32 scratch; - u32 fetchpage; - u32 size; - u32 dest_addr; - u32 temp; - int i; - - meiDebugRead(ARC_MEI_MAILBOXR, &scratch, 1); - if(scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK) - { - if(showtime==1){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n Code Swap Request After ShowTime !!!"); -#endif - } - else{ -#ifdef AMAZON_MEI_DEBUG_ON -// printk("\n\n Code Swap Request"); -#endif - fetchpage = scratch & ~OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK; - size = meiGetPage( fetchpage, GET_PROG, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( size > 0) - { -#ifdef AMAZON_MEI_DEBUG_ON -// printk(" : prom page num %d",fetchpage); -#endif - meiDMAWrite( dest_addr, mei_arc_swap_buff, size); - } - - size = meiGetPage( fetchpage, GET_DATA, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( size > 0) - { -#ifdef AMAZON_MEI_DEBUG_ON -// printk(" : data page num %d",fetchpage); -#endif - meiDMAWrite( dest_addr, mei_arc_swap_buff, size); - } - } - // Notify arc that mailbox read complete - meiLongwordWrite(ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV); - - // Tell ARC Codeswap is done - meiLongwordWrite(MEI_TO_ARC_INT, MEI_TO_ARC_CS_DONE); - asm("SYNC"); - i=0; - while(i>4)==D2H_AUTONOMOUS_MODEM_READY_MSG){ //check ARC ready message - -#ifdef LOCK_RETRY - if (reboot_lock) - { - reboot_lock = 0; - up(&mei_sema); // allow cmv access - } -#else - up(&mei_sema); // allow cmv access -#endif - reboot_flag=1; -//#ifdef ADSL_LED_SUPPORT -#if 0 - led_support_check=1;//adsl led for 1.1.2.7.1.1 - adsl_led_flash();//adsl led for 1.1.2.7.1.1 -#endif - wake_up_interruptible(&wait_queue_reboot); // wait up ioctl reboot - } -#endif - } - } -// meiLongwordWrite(ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV); - mask_and_ack_amazon_irq(AMAZON_MEI_INT); - return; -} - -// 603221:tc.chen start -////////////////////////hdlc //////////////// - -// get hdlc status -static unsigned int ifx_me_hdlc_status(void) -{ - u16 CMVMSG[MSG_LENGTH]; - int ret; - - if (showtime!=1) - return -ENETRESET; - - makeCMV_local(H2D_CMV_READ, STAT, 14, 0, 1, NULL,CMVMSG); //Get HDLC status - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - return CMVMSG[4]&0x0F; -} - -int ifx_me_is_resloved(int status) -{ - u16 CMVMSG[MSG_LENGTH]; - int ret; - - if (status == ME_HDLC_MSG_QUEUED || status == ME_HDLC_MSG_SENT) - return ME_HDLC_UNRESOLVED; - if (status == ME_HDLC_IDLE) - { - makeCMV_local(H2D_CMV_READ, CNTL, 2, 0, 1, NULL,CMVMSG); //Get ME-HDLC Control - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return IFX_POP_EOC_FAIL; - } - if (CMVMSG[4]&(1<<0)) - { - return ME_HDLC_UNRESOLVED; - } - - } - return ME_HDLC_RESOLVED; -} - -int _ifx_me_hdlc_send(unsigned char *hdlc_pkt,int len,int max_length) -{ - int ret; - u16 CMVMSG[MSG_LENGTH]; - u16 data=0; - u16 pkt_len=len; - if (pkt_len > max_length) - { - printk("Exceed maximum eoc message length\n"); - return -ENOBUFS; - } - //while(pkt_len > 0) - { - makeCMV_local(H2D_CMV_WRITE, INFO, 81, 0, (pkt_len+1)/2,(u16 *)hdlc_pkt,CMVMSG); //Write clear eoc message to ARC - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - - makeCMV_local(H2D_CMV_WRITE, INFO, 83, 2, 1,&pkt_len,CMVMSG); //Update tx message length - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - - data = (1<<0); - makeCMV_local(H2D_CMV_WRITE, CNTL, 2, 0, 1,&data,CMVMSG); //Start to send - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - return 0; - } -} - -static int ifx_me_hdlc_send(unsigned char *hdlc_pkt,int hdlc_pkt_len) -{ - int hdlc_status=0; - u16 CMVMSG[MSG_LENGTH]; - int max_hdlc_tx_length=0,ret=0,retry=0; - - while(retry<10) - { - hdlc_status = ifx_me_hdlc_status(); - if (ifx_me_is_resloved(hdlc_status)==ME_HDLC_RESOLVED) // arc ready to send HDLC message - { - makeCMV_local(H2D_CMV_READ, INFO, 83, 0, 1, NULL,CMVMSG); //Get Maximum Allowed HDLC Tx Message Length - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - max_hdlc_tx_length = CMVMSG[4]; - ret = _ifx_me_hdlc_send(hdlc_pkt,hdlc_pkt_len,max_hdlc_tx_length); - return ret; - } - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(10); - } - return -EBUSY; -} - -int ifx_mei_hdlc_read(char *hdlc_pkt,int max_hdlc_pkt_len) -{ - u16 CMVMSG[MSG_LENGTH]; - int msg_read_len,ret=0,pkt_len=0,retry = 0; - - while(retry<10) - { - ret = ifx_me_hdlc_status(); - if (ret == ME_HDLC_RESP_RCVD) - { - int current_size=0; - makeCMV_local(H2D_CMV_READ, INFO, 83, 3, 1, NULL,CMVMSG); //Get EoC packet length - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - - pkt_len = CMVMSG[4]; - if (pkt_len > max_hdlc_pkt_len) - { - ret = -ENOMEM; - goto error; - } - while( current_size < pkt_len) - { - if (pkt_len - current_size >(MSG_LENGTH*2-8)) - msg_read_len = (MSG_LENGTH*2-8); - else - msg_read_len = pkt_len - (current_size); - makeCMV_local(H2D_CMV_READ, INFO, 82, 0 + (current_size/2), (msg_read_len+1)/2, NULL,CMVMSG); //Get hdlc packet - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - goto error; - } - memcpy(hdlc_pkt+current_size,&CMVMSG[4],msg_read_len); - current_size +=msg_read_len; - } - ret = current_size; - break; - }else - { - ret = -ENODATA; - } - - retry++; - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(10); - - } - return ret; -error: - - return ret; -} - -////////////////////////hdlc //////////////// -// 603221:tc.chen end - -/////////////////////// clearEoC, int ifx_pop_eoc(sk_buff * pkt) ////////// -int ifx_pop_eoc(struct sk_buff * pkt); -int ifx_pop_eoc(struct sk_buff * pkt) -{ - amazon_clreoc_pkt * current; - if(showtime!=1){ - dev_kfree_skb(pkt); - return IFX_POP_EOC_FAIL; - } - if((pkt->len)>clreoc_max_tx_len){ - dev_kfree_skb(pkt); - return IFX_POP_EOC_FAIL; - } - current = list_entry(clreoc_list.next, amazon_clreoc_pkt, list); - while(1){ - if(current->len==0){ - memcpy(current->command, pkt->data, pkt->len); - current->len=pkt->len; - break; - } - else{ - if((current->list).next==&clreoc_list){ - dev_kfree_skb(pkt); - return IFX_POP_EOC_FAIL; //buffer full - } - current = list_entry((current->list).next,amazon_clreoc_pkt, list); - } - } - wake_up_interruptible(&wait_queue_clreoc); - - dev_kfree_skb(pkt); - return IFX_POP_EOC_DONE; -} -/* this is used in circular fifo mode */ -/* -int ifx_pop_eoc(sk_buff * pkt); -int ifx_pop_eoc(sk_buff * pkt) -{ - int buff_space,i; - if(showtime!=1) - return IFX_POP_EOC_FAIL; - - if(clreoc_wr>=clreoc_rd) - buff_space = (MEI_CLREOC_BUFF_SIZE-1)-(clreoc_wr - clreoc_rd); - else - buff_space = clreoc_rd - clreoc_wr - 1; - if((pkt->len)>buff_space) - return IFX_POP_EOC_FAIL; - - if((clreoc_wr+pkt->len)>MEI_CLREOC_BUFF_SIZE){ - memcpy((clreoc+clreoc_wr), pkt->data, ((clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE+1)); - memcpy(clreoc, (pkt->data)+((clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE+1), (pkt->len)-((clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE+1)); - clreoc_wr=(clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE; - } - else{ - memcpy((clreoc+clreoc_wr), pkt->data, pkt->len); - if((clreoc_wr+pkt->len)=MEI_CLREOC_BUFF_SIZE) - clreoc_wr=0; - else - clreoc_wr+=pkt->len; - } - wake_up_interruptible(&wait_queue_clreoc); - return IFX_POP_EOC_DONE; -} -*/ - - -//////////////////////////////////////////////////////////////////////////// -//int amazon_mei_init_module (void); -//void amazon_mei_cleanup_module (void); -//int __init init_module (void); -//void __exit cleanup_module (void); - -int __init amazon_mei_init_module(void) -//int __init init_module(void) -{ - struct proc_dir_entry *entry; - int i; - -//dying gasp-start -#ifdef IFX_DYING_GASP - -//000003:fchang Start -#ifdef CONFIG_CPU_AMAZON_E - //GPIO31 :dying gasp event indication - // (1) logic high: dying gasp event is false (default) - // (2) logic low: dying gasp event is true - CLEAR_BIT((*((volatile u32 *)0xB0100B18)), 0x4); - CLEAR_BIT((*((volatile u32 *)0xB0100B1c)), 0x4); - CLEAR_BIT((*((volatile u32 *)0xB0100B20)), 0x4); - SET_BIT((*((volatile u32 *)0xB0100B24)), 0x4); - asm("SYNC"); -#else //000003:fchang End - - //GPIO31 :dying gasp event indication - // (1) logic high: dying gasp event is false (default) - // (2) logic low: dying gasp event is true - CLEAR_BIT((*((volatile u32 *)0xB0100B48)), 0x8000); - CLEAR_BIT((*((volatile u32 *)0xB0100B4C)), 0x8000); - CLEAR_BIT((*((volatile u32 *)0xB0100B50)), 0x8000); - SET_BIT((*((volatile u32 *)0xB0100B54)), 0x8000); -#if 0 -//warning-led-start -//GPIO 22 - SET_BIT ((*((volatile u32 *)0xB0100B48)), 0x40); - CLEAR_BIT((*((volatile u32 *)0xB0100B4C)), 0x40); - CLEAR_BIT((*((volatile u32 *)0xB0100B50)), 0x40); - SET_BIT((*((volatile u32 *)0xB0100B54)), 0x40); - CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //GPIO ON - printk("LED ON ON ON ON ON ON....."); -//warning-led-end -#endif - asm("SYNC"); -#endif //000003:fchang - -#endif //IFX_DYING_GASP -//dying gasp -end - - - reg_entry_t regs_temp[PROC_ITEMS] = // Items being debugged - { - /* { flag, name, description } */ - { &arcmsgav, "arcmsgav", "arc to mei message ", 0 }, - { &cmv_reply, "cmv_reply", "cmv needs reply", 0}, - { &cmv_waiting, "cmv_waiting", "waiting for cmv reply from arc", 0}, - { &indicator_count, "indicator_count", "ARC to MEI indicator count", 0}, - { &cmv_count, "cmv_count", "MEI to ARC CMVs", 0}, - { &reply_count, "reply_count", "ARC to MEI Reply", 0}, - { (int *)Recent_indicator, "Recent_indicator", "most recent indicator", 0}, - { (int *)8, "version", "version of firmware", 0}, - }; - memcpy((char *)regs, (char *)regs_temp, sizeof(regs_temp)); - - - //sema_init(&mei_sema, 0); // semaphore initialization, mutex - sema_init(&mei_sema, 1); // semaphore initialization, mutex - - init_waitqueue_head(&wait_queue_arcmsgav); // for ARCMSGAV - init_waitqueue_head(&wait_queue_codeswap); // for codeswap daemon - init_waitqueue_head(&wait_queue_mibdaemon); // for mib daemon - init_waitqueue_head(&wait_queue_reboot); // for ioctl reboot - init_waitqueue_head(&wait_queue_clreoc); // for clreoc_wr function - init_waitqueue_head(&wait_queue_loop_diagnostic); // for loop diagnostic function -#ifdef ADSL_LED_SUPPORT - init_waitqueue_head(&wait_queue_led); // adsl led for led function - init_waitqueue_head(&wait_queue_led_polling); // adsl led for led function - led_task.routine = adsl_led_flash_task; // adsl led for led function - led_poll_init(); // adsl led for led function -#endif //ADSL_LED_SUPPORT -#ifdef IFX_DYING_GASP - init_waitqueue_head(&wait_queue_dying_gasp); // IFX_DYING_GASP - lop_poll_init(); // IFX_DYING_GASP -#endif //IFX_DYING_GASP - - init_waitqueue_head(&wait_queue_uas_poll);//joelin 04/16/2005 - unavailable_seconds_poll_init();//joelin 04/16/2005 - memset(&mib_pflagtime, 0, (sizeof(mib_flags_pretime))); - - // initialize link list for intervals - mei_mib = (amazon_mei_mib *)kmalloc((sizeof(amazon_mei_mib)*INTERVAL_NUM), GFP_KERNEL); - if(mei_mib == NULL){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("kmalloc error for amazon_mei_mib\n\n"); -#endif - return -1; - } - memset(mei_mib, 0, (sizeof(amazon_mei_mib)*INTERVAL_NUM)); - INIT_LIST_HEAD(&interval_list); - for(i=0;istart_time)); - // initialize clreoc list - clreoc_pkt = (amazon_clreoc_pkt *)kmalloc((sizeof(amazon_clreoc_pkt)*CLREOC_BUFF_SIZE), GFP_KERNEL); - if(clreoc_pkt == NULL){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("kmalloc error for clreoc_pkt\n\n"); -#endif - return -1; - } - memset(clreoc_pkt, 0, (sizeof(amazon_clreoc_pkt)*CLREOC_BUFF_SIZE)); - INIT_LIST_HEAD(&clreoc_list); - for(i=0;ilow_ino; - entry->proc_fops = &proc_operations; - } else { -#ifdef AMAZON_MEI_DEBUG_ON - printk( KERN_ERR - ": can't create /proc/" MEI_DIRNAME - "/%s\n\n", regs[i].name); -#endif - return(-ENOMEM); - } - } - ///////////////////////////////// register net device //////////////////////////// - if(register_netdev(&phy_mei_net)!=0){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n Register phy Device Failed."); -#endif - return -1; - } -/* - if(register_netdev(&interleave_mei_net)!=0){ - printk("\n\n Register interleave Device Failed."); - return -1; - } - if(register_netdev(&fast_mei_net)!=0){ - printk("\n\n Register fast Device Failed."); - return -1; - } -*/ -#ifdef DFE_LOOPBACK - mei_arc_swap_buff = (u32 *)kmalloc(MAXSWAPSIZE*4, GFP_KERNEL); - if (mei_arc_swap_buff){ -#ifdef ARC_READY_ACK - if(down_interruptible(&mei_sema)) //disable CMV access until ARC ready - { - return -ERESTARTSYS; - } -#ifdef LOCK_RETRY - reboot_lock = 1; -#endif -#endif - meiForceRebootAdslModem(); - kfree(mei_arc_swap_buff); - }else{ -#ifdef AMAZON_MEI_DEBUG_ON - printk("cannot load image: no memory\n\n"); -#endif - } -#endif -#ifdef IFX_SMALL_FOOTPRINT - mib_poll_init(); -#endif - return 0; -} - -void __exit amazon_mei_cleanup_module(void) -//void __exit cleanup_module(void) -{ - int i; -#ifdef ADSL_LED_SUPPORT - stop_led_module=1; //wake up and clean led module - led_support_check=0;//joelin , clear task - showtime=0;//joelin,clear task - //CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON - firmware_support_led=0;//joelin ,clear task - wake_up_interruptible(&wait_queue_led); //wake up and clean led module - wake_up_interruptible(&wait_queue_led_polling); //wake up and clean led module -#endif - for(i=0;icomm, "kmibpoll"); - sigfillset(&tsk->blocked); - - printk("Inside mib poll loop ...\n"); - i=0; - while(1){ - if(istart_time.tv_sec>=900){ - if(current_intvl->list.next!=&interval_list){ - current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list); - do_gettimeofday(&(current_intvl->start_time)); - } - else{ - mib_ptr = list_entry(interval_list.next, amazon_mei_mib, list); - list_del(interval_list.next); - memset(mib_ptr, 0, sizeof(amazon_mei_mib)); - list_add_tail(&(mib_ptr->list), &interval_list); - if(current_intvl->list.next==&interval_list) -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nlink list error"); -#endif - current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list); - do_gettimeofday(&(current_intvl->start_time)); - } - } - - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; -/* - ATUC_PERF_LO_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 0 Index 0"); -#endif - } - else{ - if(RxMessage[4]&PLAM_LOS_FailureBit){ - current_intvl->AtucPerfLos++; - ATUC_PERF_LOSS++; - CurrStatus.adslAtucCurrStatus = 2; - } - if(RxMessage[4]&PLAM_LOF_FailureBit){ - current_intvl->AtucPerfLof++; - ATUC_PERF_LOFS++; - CurrStatus.adslAtucCurrStatus = 1; - } - if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit))) - CurrStatus.adslAtucCurrStatus = 0; - } -*/ - - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_ESS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 7 Index 0"); -#endif - } - else{ - temp = RxMessage[4]-mib_pread.ATUC_PERF_ESS; - if(temp>=0){ - current_intvl->AtucPerfEs+=temp; - ATUC_PERF_ESS+=temp; - mib_pread.ATUC_PERF_ESS = RxMessage[4]; - } - else{ - current_intvl->AtucPerfEs+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4]; - ATUC_PERF_ESS+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4]; - mib_pread.ATUC_PERF_ESS = RxMessage[4]; - } - } -/* - ATUR_PERF_LO_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 1 Index 0"); -#endif - } - else{ - if(RxMessage[4]&PLAM_LOS_FailureBit){ - current_intvl->AturPerfLos++; - ATUR_PERF_LOSS++; - CurrStatus.adslAturCurrStatus = 2; - } - if(RxMessage[4]&PLAM_LOF_FailureBit){ - current_intvl->AturPerfLof++; - ATUR_PERF_LOFS++; - CurrStatus.adslAturCurrStatus = 1; - } - if(RxMessage[4]&PLAM_LPR_FailureBit){ - current_intvl->AturPerfLpr++; - ATUR_PERF_LPR++; - CurrStatus.adslAturCurrStatus = 3; - } - if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit|PLAM_LPR_FailureBit))) - CurrStatus.adslAturCurrStatus = 0; - } -*/ - if(showtime!=1) - goto mib_poll_end; - ATUR_PERF_ESS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 33 Index 0"); -#endif - } - else{ - temp = RxMessage[4]-mib_pread.ATUR_PERF_ESS; - if(temp>=0){ - current_intvl->AturPerfEs+=temp; - ATUR_PERF_ESS+=temp; - mib_pread.ATUR_PERF_ESS = RxMessage[4]; - } - else{ - current_intvl->AturPerfEs+=0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4]; - ATUR_PERF_ESS+= 0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4]; - mib_pread.ATUR_PERF_ESS=RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - // to update rx/tx blocks - ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 20 Index 0"); -#endif - } - else{ - temp = RxMessage[4]; - } - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 21 Index 0"); -#endif - } - else{ - temp2 = RxMessage[4]; - } - if((temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK)>=0){ - current_intvl->AturChanPerfRxBlk+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK; - ATUR_CHAN_RECV_BLK+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK; - mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16); - } - else{ - current_intvl->AturChanPerfRxBlk+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16)); - ATUR_CHAN_RECV_BLK+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16)); - mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16); - } - current_intvl->AturChanPerfTxBlk = current_intvl->AturChanPerfRxBlk; - ATUR_CHAN_TX_BLK = ATUR_CHAN_RECV_BLK; -/* - ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS) - printk("\n\nCMV fail, Group 7 Address 20 Index 0"); - else{ - if(RxMessage[4]){ - current_intvl->AturChanPerfTxBlk+=RxMessage[4]; - ATUR_CHAN_TX_BLK+=RxMessage[4]; - } - } - ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS) - printk("\n\nCMV fail, Group 7 Address 21 Index 0"); - else{ - if(RxMessage[4]){ - current_intvl->AturChanPerfTxBlk+=(int)((RxMessage[4])<<16); - ATUR_CHAN_TX_BLK+=(int)((RxMessage[4])<<16); - } - } -*/ - if(chantype.interleave == 1){ - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 3 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_INTL; - if(temp>=0){ - current_intvl->AturChanPerfCorrBlk+=temp; - ATUR_CHAN_CORR_BLK+=temp; - mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4]; - ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4]; - mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4]; - } - } - } - else if(chantype.fast == 1){ - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 3 Index 1"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_FAST; - if(temp>=0){ - current_intvl->AturChanPerfCorrBlk+=temp; - ATUR_CHAN_CORR_BLK+=temp; - mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4]; - ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4]; - mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4]; - } - } - } - - if(chantype.interleave == 1){ - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 2 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL; - if(temp>=0){ - current_intvl->AturChanPerfUncorrBlk+=temp; - ATUR_CHAN_UNCORR_BLK+=temp; - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4]; - ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4]; - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4]; - } - } - } - else if(chantype.fast == 1){ - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 2 Index 1"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST; - if(temp>=0){ - current_intvl->AturChanPerfUncorrBlk+=temp; - ATUR_CHAN_UNCORR_BLK+=temp; - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4]; - ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4]; - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4]; - } - } - } - - //RFC-3440 - -#ifdef AMAZON_MEI_MIB_RFC3440 - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_STAT_FASTR_FLAG_MAKECMV; //??? - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 0 Address 0 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FASTR; - if(temp>=0){ - current_intvl->AtucPerfStatFastR+=temp; - ATUC_PERF_STAT_FASTR+=temp; - mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4]; - ATUC_PERF_STAT_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV; //??? - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 0 Address 0 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FAILED_FASTR; - if(temp>=0){ - current_intvl->AtucPerfStatFailedFastR+=temp; - ATUC_PERF_STAT_FAILED_FASTR+=temp; - mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatFailedFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4]; - ATUC_PERF_STAT_FAILED_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_STAT_SESL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 8 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_SESL; - if(temp>=0){ - current_intvl->AtucPerfStatSesL+=temp; - ATUC_PERF_STAT_SESL+=temp; - mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatSesL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4]; - ATUC_PERF_STAT_SESL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_STAT_UASL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 10 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_UASL; - if(temp>=0){ - current_intvl->AtucPerfStatUasL+=temp; - ATUC_PERF_STAT_UASL+=temp; - mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4]; - ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - ATUR_PERF_STAT_SESL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 34 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_PERF_STAT_SESL; - if(temp>=0){ - current_intvl->AtucPerfStatUasL+=temp; - ATUC_PERF_STAT_UASL+=temp; - mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4]; - ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4]; - mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4]; - } - } - -#endif -mib_poll_end: - up(&mei_sema); - - do_gettimeofday(&time_fini); - i = ((int)((time_fini.tv_sec-time_now.tv_sec)*1000)) + ((int)((time_fini.tv_usec-time_now.tv_usec)/1000)) ; //msec - }//showtime==1 - } - -} -int mib_poll_init(void) -{ - printk("Starting mib_poll...\n"); - - kernel_thread(adsl_mib_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL); - return 0; -} -#endif //IFX_SMALL_FOOTPRINT -//EXPORT_NO_SYMBOLS; - -#ifdef ADSL_LED_SUPPORT -// adsl led -start -int led_status_on=0,led_need_to_flash=0; -int led_current_flashing=0; -unsigned long led_delay=0; -static int led_poll(void *unused) -{ - stop_led_module=0; //begin polling ... - while(!stop_led_module){ - if ((!led_status_on)&&(!led_need_to_flash)) interruptible_sleep_on_timeout (&wait_queue_led_polling,1000); //10 seconds timeout for waiting wakeup -// else printk("direct running task, no waiting"); - run_task_queue(&tq_ifx_led);//joelin task -// printk("led and LOP polling...\n"); - } - return 0; -} -static int led_poll_init(void) -{ -// printk("Starting adsl led polling...\n"); - -//warning-led-start -// CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON -//warning-led-end - - kernel_thread(led_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL); - return 0; -} - -int adsl_led_flash(void) -{ - int i; - if (!firmware_support_led) return 0; //joelin version check - - if (led_status_on == 0 && led_need_to_flash == 0) - { - queue_task(&led_task, &tq_ifx_led);//joelin task - wake_up_interruptible(&wait_queue_led_polling); //wake up and clean led module -// printk("queue Task 1...\n"); //joelin test - } - led_need_to_flash=1;//asking to flash led - - return 0; -} - -int adsl_led_flash_task(void *ptr) -{ - - u16 one=1; - u16 zero=0; - u16 data=0x0600; - int kernel_use=1; - u16 CMVMSG[MSG_LENGTH]; -//adsl-led-start for >v1.1.2.7.1.1 -// printk("Task Running...\n"); //joelin test - if ((firmware_support_led==2)&&(led_support_check)) - { - led_support_check=0; - data=0x0600; - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 0, 1, &data,CMVMSG); //configure GPIO9 GPIO10 as outputs - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 2, 1, &data,CMVMSG); //enable writing to bit 9 and bit10 - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - - data=0x0a01; - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 4, 1, &data,CMVMSG); //use GPIO10 for TR68 .Enable and don't invert. - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - -#ifdef DATA_LED_ON_MODE - data=0x0903;//tecom //use GPIO9 for TR68 data led .turn on. -#else - data=0x0900; -#endif - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 5, 1, &data,CMVMSG); //use GPIO9 for TR68 data led .turn off. - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - - } - if (!showtime) {led_need_to_flash=0; return 0;} -//adsl-led-end for >v1.1.2.7.1.1 - - if (led_status_on == 0 || led_need_to_flash == 1) - { - - if (led_current_flashing==0) - { - if (firmware_support_led==1){//>1.1.2.3.1.1 - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 0, 1, &one,CMVMSG); //flash - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG); - } - else if (firmware_support_led==2){//>1.1.2.7.1.1 - data=0x0901;//flash - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 5, 1, &data,CMVMSG); //use GPIO9 for TR68 data led .flash. - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG); - - }//(firmware_support_led==2) - led_current_flashing = 1;//turn on led - } - led_status_on=1; - - do{//do nothing , waiting untill no data traffic - led_need_to_flash=0; - interruptible_sleep_on_timeout(&wait_queue_led, 25); //the time for LED Off , if no data traffic - }while(led_need_to_flash==1); - - }else if (led_status_on == 1 && led_need_to_flash==0) - { - if (led_current_flashing==1) - {//turn off led - if (firmware_support_led==1){//>1.1.2.3.1.1 - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 0, 1, &zero,CMVMSG);//off - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG); - } //>1.1.2.3.1.1 - else if (firmware_support_led==2){//>1.1.2.7.1.1 -#ifdef DATA_LED_ON_MODE - data=0x0903;//tecom //use GPIO9 for TR68 data led .turn on. -#else - data=0x0900;//off -#endif - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 5, 1, &data,CMVMSG); //use GPIO9 for TR68 data led .off. - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG); - - }//(firmware_support_led==2) - led_status_on=0; - led_current_flashing = 0; - } - } - - if (led_status_on == 1 || led_need_to_flash) - {//led flash job on going or led need to flash - queue_task(&led_task, &tq_ifx_led); //joelin task -// printk("queue Task 2...\n"); //joelin test - } - return 0; -} -//joelin adsl led-end -#else -int adsl_led_flash(void) -{ - return 0; -} -#endif //ADSL_LED_SUPPORT -#ifdef IFX_DYING_GASP -static int lop_poll(void *unused) -{ - - while(1) - { - interruptible_sleep_on_timeout(&wait_queue_dying_gasp, 1); -#ifdef CONFIG_CPU_AMAZON_E //000003:fchang - if(showtime&&((*((volatile u32 *)0xB0100B14))&0x4)==0x0) {//000003:fchang -#else //000003:fchang - if(showtime&&((*((volatile u32 *)0xB0100B44))&0x8000)==0x0) { -#endif //CONFIG_CPU_AMAZON_E - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_WRITEDEBUG, &lop_debugwr); - printk("send dying gasp..\n");} - - } - return 0; - } -static int lop_poll_init(void) -{ -// printk("Starting LOP polling...\n"); - kernel_thread(lop_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL); - return 0; -} - -#endif //IFX_DYING_GASP - -//joelin 04/16/2005-satrt -static int unavailable_seconds_poll(void *unused) -{ - while(1){ - interruptible_sleep_on_timeout (&wait_queue_uas_poll,100); //1 second timeout for waiting wakeup - if (!showtime) unavailable_seconds++; - } - return 0; -} -static int unavailable_seconds_poll_init(void) -{ - - kernel_thread(unavailable_seconds_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL); - return 0; -} - - -//joelin 04/16/2005-end -EXPORT_SYMBOL(meiDebugWrite); -EXPORT_SYMBOL(ifx_pop_eoc); - -MODULE_LICENSE("GPL"); - -module_init(amazon_mei_init_module); -module_exit(amazon_mei_cleanup_module); - diff --git a/target/linux/amazon/files/drivers/char/ifx_ssc.c b/target/linux/amazon/files/drivers/char/ifx_ssc.c deleted file mode 100644 index ea01659a94..0000000000 --- a/target/linux/amazon/files/drivers/char/ifx_ssc.c +++ /dev/null @@ -1,2121 +0,0 @@ -/************************************************** - * - * drivers/ifx/serial/ifx_ssc.c - * - * Driver for IFX_SSC serial ports - * - * Copyright (C) 2004 Infineon Technologies AG - * Author Michael Schoenenborn (IFX COM TI BT) - * - */ -#define IFX_SSC_DRV_VERSION "0.2.1" -/* - ************************************************** - * - * This driver was originally based on the INCA-IP driver, but due to - * fundamental conceptual drawbacks there has been changed a lot. - * - * Based on INCA-IP driver Copyright (c) 2003 Gary Jennejohn - * Based on the VxWorks drivers Copyright (c) 2002, Infineon Technologies. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -// ### TO DO: general issues: -// - power management -// - interrupt handling (direct/indirect) -// - pin/mux-handling (just overall concept due to project dependency) -// - multiple instances capability -// - slave functionality - -/* - * Include section - */ -#ifndef EXPORT_SYMTAB -#define EXPORT_SYMTAB -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -//#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#ifdef SSC_FRAME_INT_ENABLE -#undef SSC_FRAME_INT_ENABLE -#endif - -#define not_yet - -#define SPI_VINETIC - -/* - * Deal with CONFIG_MODVERSIONS - */ -#if CONFIG_MODVERSIONS==1 -# include -#endif - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Michael Schoenenborn"); -MODULE_DESCRIPTION("IFX SSC driver"); -MODULE_SUPPORTED_DEVICE("ifx_ssc"); -MODULE_PARM(maj, "i"); -MODULE_PARM_DESC(maj, "Major device number"); - -/* allow the user to set the major device number */ -static int maj = 0; - - -/* - * This is the per-channel data structure containing pointers, flags - * and variables for the port. This driver supports a maximum of PORT_CNT. - * isp is allocated in ifx_ssc_init() based on the chip version. - */ -static struct ifx_ssc_port *isp; - -/* prototypes for fops */ -static ssize_t ifx_ssc_read(struct file *, char *, size_t, loff_t *); -static ssize_t ifx_ssc_write(struct file *, const char *, size_t, loff_t *); -//static unsigned int ifx_ssc_poll(struct file *, struct poll_table_struct *); -int ifx_ssc_ioctl(struct inode *, struct file *, unsigned int, unsigned long); -int ifx_ssc_open(struct inode *, struct file *); -int ifx_ssc_close(struct inode *, struct file *); - -/* other forward declarations */ -static unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info); -static void ifx_ssc_rx_int(int, void *, struct pt_regs *); -static void ifx_ssc_tx_int(int, void *, struct pt_regs *); -static void ifx_ssc_err_int(int, void *, struct pt_regs *); -#ifdef SSC_FRAME_INT_ENABLE -static void ifx_ssc_frm_int(int, void *, struct pt_regs *); -#endif -static void tx_int(struct ifx_ssc_port *); -static int ifx_ssc1_read_proc(char *, char **, off_t, int, int *, void *); -static void ifx_gpio_init(void); -/************************************************************************ - * Function declaration - ************************************************************************/ -//interrupt.c -extern unsigned int amazon_get_fpi_hz(void); -extern void disable_amazon_irq(unsigned int irq_nr); -extern void enable_amazon_irq(unsigned int irq_nr); -extern void mask_and_ack_amazon_irq(unsigned int irq_nr); - - -/*****************************************************************/ -typedef struct { - int (*request)(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, - const char * devname, - void *dev_id); - void (*free)(unsigned int irq, void *dev_id); - void (*enable)(unsigned int irq); - void (*disable)(unsigned int irq); - void (*clear)(unsigned int irq); -} ifx_int_wrapper_t; - -static ifx_int_wrapper_t ifx_int_wrapper = { - request: request_irq, // IM action: enable int - free: free_irq, // IM action: disable int - enable: enable_amazon_irq, - disable: disable_amazon_irq, - clear: mask_and_ack_amazon_irq, - //end: -}; - -/* Fops-struct */ -static struct file_operations ifx_ssc_fops = { - owner: THIS_MODULE, - read: ifx_ssc_read, /* read */ - write: ifx_ssc_write, /* write */ -// poll: ifx_ssc_poll, /* poll */ - ioctl: ifx_ssc_ioctl, /* ioctl */ - open: ifx_ssc_open, /* open */ - release: ifx_ssc_close, /* release */ -}; - - -static inline unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info) -{ // ATTENTION: This function assumes that the CLC register is set with the - // appropriate value for RMC. - unsigned int rmc; - - rmc = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_CLC) & - IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET; - if (rmc == 0){ - printk("ifx_ssc_get_kernel_clk rmc==0 \n"); - return (0); - } - return (amazon_get_fpi_hz() / rmc); -} - -#ifndef not_yet -#ifdef IFX_SSC_INT_USE_BH -/* - * This routine is used by the interrupt handler to schedule - * processing in the software interrupt portion of the driver - * (also known as the "bottom half"). This can be called any - * number of times for any channel without harm. - */ -static inline void -ifx_ssc_sched_event(struct ifx_ssc_port *info, int event) -{ - info->event |= 1 << event; /* remember what kind of event and who */ - queue_task(&info->tqueue, &tq_cyclades); /* it belongs to */ - mark_bh(CYCLADES_BH); /* then trigger event */ -} /* ifx_ssc_sched_event */ - - -/* - * This routine is used to handle the "bottom half" processing for the - * serial driver, known also the "software interrupt" processing. - * This processing is done at the kernel interrupt level, after the - * cy#/_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This - * is where time-consuming activities which can not be done in the - * interrupt driver proper are done; the interrupt driver schedules - * them using ifx_ssc_sched_event(), and they get done here. - * - * This is done through one level of indirection--the task queue. - * When a hardware interrupt service routine wants service by the - * driver's bottom half, it enqueues the appropriate tq_struct (one - * per port) to the tq_cyclades work queue and sets a request flag - * via mark_bh for processing that queue. When the time is right, - * do_ifx_ssc_bh is called (because of the mark_bh) and it requests - * that the work queue be processed. - * - * Although this may seem unwieldy, it gives the system a way to - * pass an argument (in this case the pointer to the ifx_ssc_port - * structure) to the bottom half of the driver. Previous kernels - * had to poll every port to see if that port needed servicing. - */ -static void -do_ifx_ssc_bh(void) -{ - run_task_queue(&tq_cyclades); -} /* do_ifx_ssc_bh */ - -static void -do_softint(void *private_) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *) private_; - - if (test_and_clear_bit(Cy_EVENT_HANGUP, &info->event)) { - wake_up_interruptible(&info->open_wait); - info->flags &= ~(ASYNC_NORMAL_ACTIVE| - ASYNC_CALLOUT_ACTIVE); - } - if (test_and_clear_bit(Cy_EVENT_OPEN_WAKEUP, &info->event)) { - wake_up_interruptible(&info->open_wait); - } - if (test_and_clear_bit(Cy_EVENT_DELTA_WAKEUP, &info->event)) { - wake_up_interruptible(&info->delta_msr_wait); - } - if (test_and_clear_bit(Cy_EVENT_WRITE_WAKEUP, &info->event)) { - wake_up_interruptible(&tty->write_wait); - } -#ifdef Z_WAKE - if (test_and_clear_bit(Cy_EVENT_SHUTDOWN_WAKEUP, &info->event)) { - wake_up_interruptible(&info->shutdown_wait); - } -#endif -} /* do_softint */ -#endif /* IFX_SSC_INT_USE_BH */ -#endif // not_yet - -inline static void -rx_int(struct ifx_ssc_port *info) -{ - int fifo_fill_lev, bytes_in_buf, i; - unsigned long tmp_val; - unsigned long *tmp_ptr; - unsigned int rx_valid_cnt; - /* number of words waiting in the RX FIFO */ - fifo_fill_lev = (READ_PERIPHERAL_REGISTER(info->mapbase + - IFX_SSC_FSTAT) & - IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> - IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET; - // Note: There are always 32 bits in a fifo-entry except for the last - // word of a contigous transfer block and except for not in rx-only - // mode and CON.ENBV set. But for this case it should be a convention - // in software which helps: - // In tx or rx/tx mode all transfers from the buffer to the FIFO are - // 32-bit wide, except for the last three bytes, which could be a - // combination of 16- and 8-bit access. - // => The whole block is received as 32-bit words as a contigous stream, - // even if there was a gap in tx which has the fifo run out of data! - // Just the last fifo entry *may* be partially filled (0, 1, 2 or 3 bytes)! - - /* free space in the RX buffer */ - bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr; - // transfer with 32 bits per entry - while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) { - tmp_ptr = (unsigned long *)info->rxbuf_ptr; - *tmp_ptr = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RB); - info->rxbuf_ptr += 4; - info->stats.rxBytes += 4; - fifo_fill_lev --; - bytes_in_buf -= 4; - } // while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) - // now do the rest as mentioned in STATE.RXBV - while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) { - rx_valid_cnt = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & - IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> - IFX_SSC_STATE_RX_BYTE_VALID_OFFSET; - if (rx_valid_cnt == 0) break; - if (rx_valid_cnt > bytes_in_buf) { - // ### TO DO: warning message: not block aligned data, other data - // in this entry will be lost - rx_valid_cnt = bytes_in_buf; - } - tmp_val = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RB); - - for (i=0; irxbuf_ptr = (tmp_val >> ( 8 * (rx_valid_cnt - i-1))) & 0xff; -/* - *info->rxbuf_ptr = tmp_val & 0xff; - tmp_val >>= 8; -*/ - bytes_in_buf--; - - - info->rxbuf_ptr++; - } - info->stats.rxBytes += rx_valid_cnt; - } // while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) - - // check if transfer is complete - if (info->rxbuf_ptr >= info->rxbuf_end) { - ifx_int_wrapper.disable(info->rxirq); - /* wakeup any processes waiting in read() */ - wake_up_interruptible(&info->rwait); - /* and in poll() */ - //wake_up_interruptible(&info->pwait); - } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && - (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) == 0)) { - // if buffer not filled completely and rx request done initiate new transfer -/* - if (info->rxbuf_end - info->rxbuf_ptr < 65536) -*/ - if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE) - WRITE_PERIPHERAL_REGISTER((info->rxbuf_end - info->rxbuf_ptr) << - IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - else - WRITE_PERIPHERAL_REGISTER(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - } -} // rx_int - -inline static void -tx_int(struct ifx_ssc_port *info) -{ - - int fifo_space, fill, i; - fifo_space = ((READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_ID) & - IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) - - ((READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_FSTAT) & - IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> - IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET); - - if (fifo_space == 0) - return; - - fill = info->txbuf_end - info->txbuf_ptr; - - if (fill > fifo_space * 4) - fill = fifo_space * 4; - - for (i = 0; i < fill / 4; i++) { - // at first 32 bit access - WRITE_PERIPHERAL_REGISTER(*(UINT32 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB); - info->txbuf_ptr += 4; - } - - fifo_space -= fill / 4; - info->stats.txBytes += fill & ~0x3; - fill &= 0x3; - if ((fifo_space > 0) & (fill > 1)) { - // trailing 16 bit access - WRITE_PERIPHERAL_REGISTER_16(*(UINT16 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB); - info->txbuf_ptr += 2; - info->stats.txBytes += 2; - fifo_space --; -/* added by bingtao */ - fill -=2; - } - if ((fifo_space > 0) & (fill > 0)) { - // trailing 8 bit access - WRITE_PERIPHERAL_REGISTER_8(*(UINT8 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB); - info->txbuf_ptr ++; - info->stats.txBytes ++; -/* - fifo_space --; -*/ - } - - // check if transmission complete - if (info->txbuf_ptr >= info->txbuf_end) { - ifx_int_wrapper.disable(info->txirq); - kfree(info->txbuf); - info->txbuf = NULL; - /* wake up any process waiting in poll() */ - //wake_up_interruptible(&info->pwait); - } - -} // tx_int - -static void -ifx_ssc_rx_int(int irq, void *dev_id, struct pt_regs *regs) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id; - //WRITE_PERIPHERAL_REGISTER(IFX_SSC_R_BIT, info->mapbase + IFX_SSC_IRN_CR); - rx_int(info); -} - -static void -ifx_ssc_tx_int(int irq, void *dev_id, struct pt_regs *regs) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id; - //WRITE_PERIPHERAL_REGISTER(IFX_SSC_T_BIT, info->mapbase + IFX_SSC_IRN_CR); - tx_int(info); -} - -static void -ifx_ssc_err_int(int irq, void *dev_id, struct pt_regs *regs) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id; - unsigned int state; - unsigned int write_back = 0; - unsigned long flags; - - - local_irq_save(flags); - state = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE); - - if ((state & IFX_SSC_STATE_RX_UFL) != 0) { - info->stats.rxUnErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR; - } - if ((state & IFX_SSC_STATE_RX_OFL) != 0) { - info->stats.rxOvErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR; - } - if ((state & IFX_SSC_STATE_TX_OFL) != 0) { - info->stats.txOvErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR; - } - if ((state & IFX_SSC_STATE_TX_UFL) != 0) { - info->stats.txUnErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR; - } -// if ((state & IFX_SSC_STATE_ABORT_ERR) != 0) { -// info->stats.abortErr++; -// write_back |= IFX_SSC_WHBSTATE_CLR_ABORT_ERROR; -// } - if ((state & IFX_SSC_STATE_MODE_ERR) != 0) { - info->stats.modeErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR; - } - - if (write_back) - WRITE_PERIPHERAL_REGISTER(write_back, - info->mapbase + IFX_SSC_WHBSTATE); - - local_irq_restore(flags); -} - -#ifdef SSC_FRAME_INT_ENABLE -static void -ifx_ssc_frm_int(int irq, void *dev_id, struct pt_regs *regs) -{ - // ### TO DO: wake up framing wait-queue in conjunction with batch execution -} -#endif - -static void -ifx_ssc_abort(struct ifx_ssc_port *info) -{ - unsigned long flags; - bool enabled; - - local_irq_save(flags); - - // disable all int's - ifx_int_wrapper.disable(info->rxirq); - ifx_int_wrapper.disable(info->txirq); - ifx_int_wrapper.disable(info->errirq); -/* - ifx_int_wrapper.disable(info->frmirq); -*/ - local_irq_restore(flags); - - // disable SSC (also aborts a receive request!) - // ### TO DO: Perhaps it's better to abort after the receiption of a - // complete word. The disable cuts the transmission immediatly and - // releases the chip selects. This could result in unpredictable - // behavior of connected external devices! - enabled = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_IS_ENABLED) != 0; - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - - // flush fifos - WRITE_PERIPHERAL_REGISTER(IFX_SSC_XFCON_FIFO_FLUSH, - info->mapbase + IFX_SSC_TXFCON); - WRITE_PERIPHERAL_REGISTER(IFX_SSC_XFCON_FIFO_FLUSH, - info->mapbase + IFX_SSC_RXFCON); - - // free txbuf - if (info->txbuf != NULL) { - kfree(info->txbuf); - info->txbuf = NULL; - } - - // wakeup read process - if (info->rxbuf != NULL) - wake_up_interruptible(&info->rwait); - - // clear pending int's - ifx_int_wrapper.clear(info->rxirq); - ifx_int_wrapper.clear(info->txirq); - ifx_int_wrapper.clear(info->errirq); -/* - ifx_int_wrapper.clear(info->frmirq); -*/ - - // clear error flags - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, - info->mapbase + IFX_SSC_WHBSTATE); - - //printk("IFX SSC%d: Transmission aborted\n", info->port_nr); - // enable SSC - if (enabled) - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - -} // ifx_ssc_abort - - -/* - * This routine is called whenever a port is opened. It enforces - * exclusive opening of a port and enables interrupts, etc. - */ -int -ifx_ssc_open(struct inode *inode, struct file * filp) -{ - struct ifx_ssc_port *info; - int line; - int from_kernel = 0; - - if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) { - from_kernel = 1; - line = (int)inode; - } - else { - line = MINOR(filp->f_dentry->d_inode->i_rdev); - filp->f_op = &ifx_ssc_fops; - } - - /* don't open more minor devices than we can support */ - if (line < 0 || line >= PORT_CNT) - return -ENXIO; - - info = &isp[line]; - - /* exclusive open */ - if (info->port_is_open != 0) - return -EBUSY; - info->port_is_open++; - - ifx_int_wrapper.disable(info->rxirq); - ifx_int_wrapper.disable(info->txirq); - ifx_int_wrapper.disable(info->errirq); -/* - ifx_int_wrapper.disable(info->frmirq); -*/ - - /* Flush and enable TX/RX FIFO */ - WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_TXFIFO_FL << - IFX_SSC_XFCON_ITL_OFFSET) | - IFX_SSC_XFCON_FIFO_FLUSH | - IFX_SSC_XFCON_FIFO_ENABLE, - info->mapbase + IFX_SSC_TXFCON); - WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_RXFIFO_FL << - IFX_SSC_XFCON_ITL_OFFSET) | - IFX_SSC_XFCON_FIFO_FLUSH | - IFX_SSC_XFCON_FIFO_ENABLE, - info->mapbase + IFX_SSC_RXFCON); - - - /* logically flush the software FIFOs */ - info->rxbuf_ptr = 0; - info->txbuf_ptr = 0; - - /* clear all error bits */ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, - info->mapbase + IFX_SSC_WHBSTATE); - - // clear pending interrupts - ifx_int_wrapper.clear(info->rxirq); - ifx_int_wrapper.clear(info->txirq); - ifx_int_wrapper.clear(info->errirq); -/* - ifx_int_wrapper.clear(info->frmirq); -*/ - - // enable SSC - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - MOD_INC_USE_COUNT; - - return 0; -} /* ifx_ssc_open */ -EXPORT_SYMBOL(ifx_ssc_open); - -/* - * This routine is called when a particular device is closed. - */ -int -ifx_ssc_close(struct inode *inode, struct file *filp) -{ - struct ifx_ssc_port *info; - int idx; - - if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) - idx = (int)inode; - else - idx = MINOR(filp->f_dentry->d_inode->i_rdev); - - if (idx < 0 || idx >= PORT_CNT) - return -ENXIO; - - info = &isp[idx]; - if (!info) - return -ENXIO; - - // disable SSC - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - // call abort function to disable int's, flush fifos... - ifx_ssc_abort(info); - - info->port_is_open --; - MOD_DEC_USE_COUNT; - - return 0; -} /* ifx_ssc_close */ -EXPORT_SYMBOL(ifx_ssc_close); - -/* added by bingtao */ -/* helper routine to handle reads from the kernel or user-space */ -/* info->rxbuf : never kfree and contains valid data */ -/* should be points to NULL after copying data !!! */ -static ssize_t -ifx_ssc_read_helper_poll(struct ifx_ssc_port *info, char *buf, size_t len, - int from_kernel) -{ - ssize_t ret_val; - unsigned long flags; - - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - return -EFAULT; - local_irq_save(flags); - info->rxbuf_ptr = info->rxbuf; - info->rxbuf_end = info->rxbuf + len; - local_irq_restore(flags); -/* Vinetic driver always works in IFX_SSC_MODE_RXTX */ -/* TXRX in poll mode */ - while (info->rxbuf_ptr < info->rxbuf_end){ -/* This is the key point, if you don't check this condition - kfree (NULL) will happen - because tx only need write into FIFO, it's much fast than rx - So when rx still waiting , tx already finish and release buf -*/ - if (info->txbuf_ptr < info->txbuf_end) { - tx_int(info); - } - - rx_int(info); - }; - - ret_val = info->rxbuf_ptr - info->rxbuf; - return (ret_val); -} // ifx_ssc_read_helper_poll - -/* helper routine to handle reads from the kernel or user-space */ -/* info->rx_buf : never kfree and contains valid data */ -/* should be points to NULL after copying data !!! */ -static ssize_t -ifx_ssc_read_helper(struct ifx_ssc_port *info, char *buf, size_t len, - int from_kernel) -{ - ssize_t ret_val; - unsigned long flags; - DECLARE_WAITQUEUE(wait, current); - - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - return -EFAULT; - local_irq_save(flags); - info->rxbuf_ptr = info->rxbuf; - info->rxbuf_end = info->rxbuf + len; - if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) { - if ((info->txbuf == NULL) || - (info->txbuf != info->txbuf_ptr) || - (info->txbuf_end != len + info->txbuf)) { - local_irq_restore(flags); - printk("IFX SSC - %s: write must be called before calling " - "read in combined RX/TX!\n", __FUNCTION__); - return -EFAULT; - } - local_irq_restore(flags); - /* should enable tx, right?*/ - tx_int(info); - if (info->txbuf_ptr < info->txbuf_end){ - ifx_int_wrapper.enable(info->txirq); - } - - ifx_int_wrapper.enable(info->rxirq); - } else { // rx mode - local_irq_restore(flags); - if (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) & - IFX_SSC_RXCNT_TODO_MASK) - return -EBUSY; - ifx_int_wrapper.enable(info->rxirq); - // rx request limited to ' bytes -/* - if (len < 65536) -*/ - if (len < IFX_SSC_RXREQ_BLOCK_SIZE) - WRITE_PERIPHERAL_REGISTER(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - else - WRITE_PERIPHERAL_REGISTER(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - } - - __add_wait_queue(&info->rwait, &wait); - set_current_state(TASK_INTERRUPTIBLE); - // wakeup done in rx_int - - do { - local_irq_save(flags); - if (info->rxbuf_ptr >= info->rxbuf_end) - break; - local_irq_restore(flags); - -// if (filp->f_flags & O_NONBLOCK) -// { -// N = -EAGAIN; -// goto out; -// } - if (signal_pending(current)) { - ret_val = -ERESTARTSYS; - goto out; - } - schedule(); - } while (1); - - ret_val = info->rxbuf_ptr - info->rxbuf; // should be equal to len - local_irq_restore(flags); - - out: - current->state = TASK_RUNNING; - __remove_wait_queue(&info->rwait, &wait); - return (ret_val); -} // ifx_ssc_read_helper - - -#if 0 -/* helper routine to handle reads from the kernel or user-space */ -/* appropriate in interrupt context */ -static ssize_t -ifx_ssc_read_helper(struct ifx_ssc_port *info, char *buf, size_t len, - int from_kernel) -{ - ssize_t ret_val; - unsigned long flags; - DECLARE_WAITQUEUE(wait, current); - - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - return -EFAULT; - local_irq_save(flags); - info->rxbuf_ptr = info->rxbuf; - info->rxbuf_end = info->rxbuf + len; - if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) { - if ((info->txbuf == NULL) || - (info->txbuf != info->txbuf_ptr) || - (info->txbuf_end != len + info->txbuf)) { - local_irq_restore(flags); - printk("IFX SSC - %s: write must be called before calling " - "read in combined RX/TX!\n", __FUNCTION__); - return -EFAULT; - } - local_irq_restore(flags); - /* should enable tx, right?*/ - tx_int(info); - if (!in_irq()){ - if (info->txbuf_ptr < info->txbuf_end){ - ifx_int_wrapper.enable(info->txirq); - } - ifx_int_wrapper.enable(info->rxirq); - } - } else { // rx mode - local_irq_restore(flags); - if (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) & - IFX_SSC_RXCNT_TODO_MASK) - return -EBUSY; - if (!in_irq()){ - ifx_int_wrapper.enable(info->rxirq); - } - - if (len < IFX_SSC_RXREQ_BLOCK_SIZE) - WRITE_PERIPHERAL_REGISTER(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - else - WRITE_PERIPHERAL_REGISTER(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - } - if (in_irq()){ - do { - rx_int(info); - if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) { - tx_int(info); - } - - if (info->rxbuf_ptr >= info->rxbuf_end) - break; - } while (1); - ret_val = info->rxbuf_ptr - info->rxbuf; - }else{ - __add_wait_queue(&info->rwait, &wait); - set_current_state(TASK_INTERRUPTIBLE); - // wakeup done in rx_int - - do { - local_irq_save(flags); - if (info->rxbuf_ptr >= info->rxbuf_end) - break; - local_irq_restore(flags); - - if (signal_pending(current)) { - ret_val = -ERESTARTSYS; - goto out; - } - schedule(); - } while (1); - - ret_val = info->rxbuf_ptr - info->rxbuf; // should be equal to len - local_irq_restore(flags); - - out: - current->state = TASK_RUNNING; - __remove_wait_queue(&info->rwait, &wait); - } - return (ret_val); -} // ifx_ssc_read_helper -#endif - -/* helper routine to handle writes to the kernel or user-space */ -/* info->txbuf has two cases: - * 1) return value < 0 (-EFAULT), not touched at all - * 2) kfree and points to NULL in interrupt routine (but maybe later ) - */ -static ssize_t -ifx_ssc_write_helper(struct ifx_ssc_port *info, const char *buf, - size_t len, int from_kernel) -{ - // check if in tx or tx/rx mode - if (info->opts.modeRxTx == IFX_SSC_MODE_RX) - return -EFAULT; - - info->txbuf_ptr = info->txbuf; - info->txbuf_end = len + info->txbuf; - /* start the transmission (not in rx/tx, see read helper) */ - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) { - tx_int(info); - if (info->txbuf_ptr < info->txbuf_end){ - ifx_int_wrapper.enable(info->txirq); - } - } - //local_irq_restore(flags); - return len; -} - -/* - * kernel interfaces for read and write. - * The caller must set port to: n for SSC with n=m-1 (e.g. n=0 for SSC1) - */ -ssize_t -ifx_ssc_kread(int port, char *kbuf, size_t len) -{ - struct ifx_ssc_port *info; - ssize_t ret_val; - - if (port < 0 || port >= PORT_CNT) - return -ENXIO; - - if (len == 0) - return 0; - - info = &isp[port]; - - // check if reception in progress - if (info->rxbuf != NULL){ - printk("SSC device busy\n"); - return -EBUSY; - } - - info->rxbuf = kbuf; - if (info->rxbuf == NULL){ - printk("SSC device error\n"); - return -EINVAL; - } - -/* changed by bingtao */ - /* change by TaiCheng */ - //if (!in_irq()){ - if (0){ - ret_val = ifx_ssc_read_helper(info, kbuf, len, 1); - }else{ - ret_val = ifx_ssc_read_helper_poll(info, kbuf, len, 1); - }; - info->rxbuf = NULL; - - // ### TO DO: perhaps warn if ret_val != len - ifx_int_wrapper.disable(info->rxirq); - - return (ret_val); -} // ifx_ssc_kread -EXPORT_SYMBOL(ifx_ssc_kread); - -ssize_t -ifx_ssc_kwrite(int port, const char *kbuf, size_t len) -{ - struct ifx_ssc_port *info; - ssize_t ret_val; - - if (port < 0 || port >= PORT_CNT) - return -ENXIO; - - if (len == 0) - return 0; - - info = &isp[port]; - - // check if transmission in progress - if (info->txbuf != NULL) - return -EBUSY; - info->txbuf = (char *)kbuf; - - ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 1); - if (ret_val < 0){ - info->txbuf = NULL; - } - return ret_val; -} -EXPORT_SYMBOL(ifx_ssc_kwrite); - - -/* - * user interfaces to read and write - */ -static ssize_t -ifx_ssc_read(struct file *filp, char *ubuf, size_t len, loff_t *off) -{ - ssize_t ret_val; - int idx; - struct ifx_ssc_port *info; - -/* - if (len == 0) - return (0); -*/ - idx = MINOR(filp->f_dentry->d_inode->i_rdev); - info = &isp[idx]; - - // check if reception in progress - if (info->rxbuf != NULL) - return -EBUSY; - - info->rxbuf = kmalloc(len+ 3, GFP_KERNEL); - if (info->rxbuf == NULL) - return -ENOMEM; - - ret_val = ifx_ssc_read_helper(info, info->rxbuf, len, 0); - // ### TO DO: perhaps warn if ret_val != len - if (copy_to_user((void*)ubuf, info->rxbuf, ret_val) != 0) - ret_val = -EFAULT; - - ifx_int_wrapper.disable(info->rxirq); - - kfree(info->rxbuf); - info->rxbuf = NULL; - return (ret_val); -} // ifx_ssc_read - -/* - * As many bytes as we have free space for are copied from the user - * into txbuf and the actual byte count is returned. The transmission is - * always kicked off by calling the appropriate TX routine. - */ -static ssize_t -ifx_ssc_write(struct file *filp, const char *ubuf, size_t len, loff_t *off) -{ - int idx; - struct ifx_ssc_port *info; - int ret_val; - - if (len == 0) - return (0); - - idx = MINOR(filp->f_dentry->d_inode->i_rdev); - info = &isp[idx]; - - // check if transmission in progress - if (info->txbuf != NULL) - return -EBUSY; - - info->txbuf = kmalloc(len+ 3, GFP_KERNEL); - if (info->txbuf == NULL) - return -ENOMEM; - - ret_val = copy_from_user(info->txbuf, ubuf, len); - if (ret_val == 0) - ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 0); - else - ret_val = -EFAULT; - if (ret_val < 0) { - kfree(info->txbuf); // otherwise will be done in ISR - info->txbuf = NULL; - } - return (ret_val); -} /* ifx_ssc_write */ - - -/* - * ------------------------------------------------------------ - * ifx_ssc_ioctl() and friends - * ------------------------------------------------------------ - */ - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_frm_status_get - LONG-NAME : framing status get - PURPOSE : Get the actual status of the framing. - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : pointer to a structure ifx_ssc_frm_status which holds busy and - count values. - - REMARKS : Returns a register value independent of framing is enabled or - not! Changes structure inside of info, so the return value isn't - needed at all, but could be used for simple access. ------------------------------------------------------------------------------*/ -static struct ifx_ssc_frm_status * -ifx_ssc_frm_status_get(struct ifx_ssc_port *info) -{ - unsigned long tmp; - - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFSTAT); - info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0; - info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0; - info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) - >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET; - info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) - >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET; - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFCON); - info->frm_status.EnIntAfterData = - (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0; - info->frm_status.EnIntAfterPause = - (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0; - return (&info->frm_status); -} // ifx_ssc_frm_status_get - - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_frm_control_get - LONG-NAME : framing control get - PURPOSE : Get the actual control values of the framing. - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : pointer to a structure ifx_ssc_frm_opts which holds control bits - and count reload values. - - REMARKS : Changes structure inside of info, so the return value isn't - needed at all, but could be used for simple access. ------------------------------------------------------------------------------*/ -static struct ifx_ssc_frm_opts * -ifx_ssc_frm_control_get(struct ifx_ssc_port *info) -{ - unsigned long tmp; - - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFCON); - info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0; - info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) - >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET; - info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) - >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET; - info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) - >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET; - info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) - >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET; - info->frm_opts.StopAfterPause = - (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0; - return (&info->frm_opts); -} // ifx_ssc_frm_control_get - - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_frm_control_set - LONG-NAME : framing control set - PURPOSE : Set the actual control values of the framing. - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : pointer to a structure ifx_ssc_frm_opts which holds control bits - and count reload values. - - REMARKS : ------------------------------------------------------------------------------*/ -static int -ifx_ssc_frm_control_set(struct ifx_ssc_port *info) -{ - unsigned long tmp; - - // check parameters - if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX) || - (info->frm_opts.DataLength < 1) || - (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX) || - (info->frm_opts.PauseLength < 1) || - ((info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> - IFX_SSC_SFCON_PAUSE_DATA_OFFSET)) != 0 ) || - ((info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> - IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)) != 0 )) - return -EINVAL; - - // read interrupt bits (they're not changed here) - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFCON) & - (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | - IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE); - - // set all values with respect to it's bit position (for data and pause - // length set N-1) - tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET; - tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET; - tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET; - tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET; - tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE; - tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE; - - WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_SFCON); - - return 0; -} // ifx_ssc_frm_control_set - - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_rxtx_mode_set - LONG-NAME : rxtx mode set - PURPOSE : Set the transmission mode. - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : Returns error code - - REMARKS : Assumes that SSC not used (SSC disabled, device not opened yet - or just closed) ------------------------------------------------------------------------------*/ -static int -ifx_ssc_rxtx_mode_set(struct ifx_ssc_port *info, unsigned int val) -{ - unsigned long tmp; - - // check parameters - if (!(info) || (val & ~(IFX_SSC_MODE_MASK))) - return -EINVAL; - /*check BUSY and RXCNT*/ - if ( READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_BUSY - ||READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK) - return -EBUSY; - // modify - tmp = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_CON) & - ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val); - WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_CON); - info->opts.modeRxTx = val; -/* - printk(KERN_DEBUG "IFX SSC%d: Setting mode to %s%s\n", - info->port_nr, - ((val & IFX_SSC_CON_RX_OFF) == 0) ? "rx ":"", - ((val & IFX_SSC_CON_TX_OFF) == 0) ? "tx":""); -*/ - return 0; -} // ifx_ssc_rxtx_mode_set - -void ifx_gpio_init(void) -{ - u32 temp; -/* set gpio pin p0.10(SPI_DIN) p0.11(SPI_DOUT) p0.12(SPI_CLK) p0.13(SPI_CS2) direction */ - temp = *(AMAZON_GPIO_P0_DIR) ; - temp &= 0xFFFFFBFF; - temp |= 0x3800; - *(AMAZON_GPIO_P0_DIR) = temp; -/* set port 0 alternate select register 0 */ - temp = *(AMAZON_GPIO_P0_ALTSEL0) ; - temp &= 0xFFFFC3FF; - temp |= 0x00001c00; - *(AMAZON_GPIO_P0_ALTSEL0) = temp; - -/* set port 0 alternate select register 1 */ - temp = *(AMAZON_GPIO_P0_ALTSEL1) ; - temp &= 0xFFFFC3FF; - temp |= 0x00002000; - *(AMAZON_GPIO_P0_ALTSEL1) = temp; - -/* set port 0 open drain mode register */ - temp = *(AMAZON_GPIO_P0_OD); - temp |= 0x00003800; /* set output pin normal mode */ - *(AMAZON_GPIO_P0_OD)= temp; -} - -/* - * This routine intializes the SSC appropriately depending - * on slave/master and full-/half-duplex mode. - * It assumes that the SSC is disabled and the fifo's and buffers - * are flushes later on. - */ -static int -ifx_ssc_sethwopts(struct ifx_ssc_port *info) -{ - unsigned long flags, bits; - struct ifx_ssc_hwopts *opts = &info->opts; - - /* sanity checks */ - if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH) || - (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH)) { - printk("%s: sanity check failed\n", __FUNCTION__); - return -EINVAL; - } - bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET; - bits |= IFX_SSC_CON_ENABLE_BYTE_VALID; -// if (opts->abortErrDetect) -// bits |= IFX_SSC_CON_ABORT_ERR_CHECK; - if (opts->rxOvErrDetect) - bits |= IFX_SSC_CON_RX_OFL_CHECK; - if (opts->rxUndErrDetect) - bits |= IFX_SSC_CON_RX_UFL_CHECK; - if (opts->txOvErrDetect) - bits |= IFX_SSC_CON_TX_OFL_CHECK; - if (opts->txUndErrDetect) - bits |= IFX_SSC_CON_TX_UFL_CHECK; - if (opts->loopBack) - bits |= IFX_SSC_CON_LOOPBACK_MODE; - if (opts->echoMode) - bits |= IFX_SSC_CON_ECHO_MODE_ON; - if (opts->headingControl) - bits |= IFX_SSC_CON_MSB_FIRST; - if (opts->clockPhase) - bits |= IFX_SSC_CON_LATCH_THEN_SHIFT; - if (opts->clockPolarity) - bits |= IFX_SSC_CON_CLOCK_FALL; - switch (opts->modeRxTx) { - case IFX_SSC_MODE_TX: - bits |= IFX_SSC_CON_RX_OFF; - break; - case IFX_SSC_MODE_RX: - bits |= IFX_SSC_CON_TX_OFF; - break; - } // switch (opts->modeRxT) - local_irq_save(flags); - WRITE_PERIPHERAL_REGISTER(bits, info->mapbase + IFX_SSC_CON); - WRITE_PERIPHERAL_REGISTER((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) | - (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), - info->mapbase + IFX_SSC_GPOCON); - //master mode - if (opts->masterSelect){ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_MASTER_SELECT,info->mapbase + IFX_SSC_WHBSTATE); - }else{ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT,info->mapbase + IFX_SSC_WHBSTATE); - } - // init serial framing - WRITE_PERIPHERAL_REGISTER(0, info->mapbase + IFX_SSC_SFCON); - /* set up the port pins */ - //check for general requirements to switch (external) pad/pin characteristics - ifx_gpio_init(); - local_irq_restore(flags); - - return 0; -} // ifx_ssc_sethwopts - -static int -ifx_ssc_set_baud(struct ifx_ssc_port *info, unsigned int baud) -{ - unsigned int ifx_ssc_clock; - unsigned int br; - unsigned long flags; - bool enabled; - - ifx_ssc_clock = ifx_ssc_get_kernel_clk(info); - if (ifx_ssc_clock ==0) - return -EINVAL; - - local_irq_save(flags); - /* have to disable the SSC to set the baudrate */ - enabled = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_IS_ENABLED) != 0; - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - // compute divider - br = ((ifx_ssc_clock >> 1)/baud) - 1; - asm("SYNC"); - if (br > 0xffff || - ((br == 0) && - ((READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & - IFX_SSC_STATE_IS_MASTER) == 0))){ - local_irq_restore(flags); - printk("%s: illegal baudrate %u\n", __FUNCTION__, baud); - return -EINVAL; - } - WRITE_PERIPHERAL_REGISTER(br, info->mapbase + IFX_SSC_BR); - if (enabled) - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - local_irq_restore(flags); - return 0; -} // ifx_ssc_set_baud - -static int -ifx_ssc_hwinit(struct ifx_ssc_port *info) -{ - unsigned long flags; - bool enabled; - - /* have to disable the SSC */ - enabled = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_IS_ENABLED) != 0; - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - if (ifx_ssc_sethwopts(info) < 0) - { - printk("%s: setting the hardware options failed\n", - __FUNCTION__); - return -EINVAL; - } - - if (ifx_ssc_set_baud(info, info->baud) < 0) { - printk("%s: setting the baud rate failed\n", __FUNCTION__); - return -EINVAL; - } - local_irq_save(flags); - /* TX FIFO */ - WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_TXFIFO_FL << - IFX_SSC_XFCON_ITL_OFFSET) | - IFX_SSC_XFCON_FIFO_ENABLE, - info->mapbase + IFX_SSC_TXFCON); - /* RX FIFO */ - WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_RXFIFO_FL << - IFX_SSC_XFCON_ITL_OFFSET) | - IFX_SSC_XFCON_FIFO_ENABLE, - info->mapbase + IFX_SSC_RXFCON); - local_irq_restore(flags); - if (enabled) - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - return 0; -} // ifx_ssc_hwinit - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_batch_exec - LONG-NAME : - PURPOSE : - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : Returns error code - - REMARKS : ------------------------------------------------------------------------------*/ -static int -ifx_ssc_batch_exec(struct ifx_ssc_port *info, struct ifx_ssc_batch_list *batch_anchor) -{ - // ### TO DO: implement user space batch execution - // first, copy the whole linked list from user to kernel space - // save some hardware options - // execute list - // restore hardware options if selected - return -EFAULT; -} // ifx_ssc_batch_exec - - -/* - * This routine allows the driver to implement device- - * specific ioctl's. If the ioctl number passed in cmd is - * not recognized by the driver, it should return ENOIOCTLCMD. - */ -int -ifx_ssc_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long data) -{ - struct ifx_ssc_port *info; - int line, ret_val = 0; - unsigned long flags; - unsigned long tmp; - int from_kernel = 0; - - if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) - { - from_kernel = 1; - line = (int)inode; - } - else - line = MINOR(filp->f_dentry->d_inode->i_rdev); - - /* don't use more minor devices than we can support */ - if (line < 0 || line >= PORT_CNT) - return -ENXIO; - - info = &isp[line]; - - switch (cmd) { - case IFX_SSC_STATS_READ: - /* data must be a pointer to a struct ifx_ssc_statistics */ - if (from_kernel) - memcpy((void *)data, (void *)&info->stats, - sizeof(struct ifx_ssc_statistics)); - else - if (copy_to_user((void *)data, - (void *)&info->stats, - sizeof(struct ifx_ssc_statistics))) - ret_val = -EFAULT; - break; - case IFX_SSC_STATS_RESET: - /* just resets the statistics counters */ - memset((void *)&info->stats, 0, sizeof(struct ifx_ssc_statistics)); - break; - case IFX_SSC_BAUD_SET: - /* if the buffers are not empty then the port is */ - /* busy and we shouldn't change things on-the-fly! */ - if (!info->txbuf || !info->rxbuf || - (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_BUSY)) { - ret_val = -EBUSY; - break; - } - /* misuse flags */ - if (from_kernel) - flags = *((unsigned long *)data); - else - if (copy_from_user((void *)&flags, - (void *)data, sizeof(flags))) - { - ret_val = -EFAULT; - break; - } - if (flags == 0) - { - ret_val = -EINVAL; - break; - } - if (ifx_ssc_set_baud(info, flags) < 0) - { - ret_val = -EINVAL; - break; - } - info->baud = flags; - break; - case IFX_SSC_BAUD_GET: - if (from_kernel) - *((unsigned int *)data) = info->baud; - else - if (copy_to_user((void *)data, - (void *)&info->baud, - sizeof(unsigned long))) - ret_val = -EFAULT; - break; - case IFX_SSC_RXTX_MODE_SET: - if (from_kernel) - tmp = *((unsigned long *)data); - else - if (copy_from_user((void *)&tmp, - (void *)data, sizeof(tmp))) { - ret_val = -EFAULT; - break; - } - ret_val = ifx_ssc_rxtx_mode_set(info, tmp); - break; - case IFX_SSC_RXTX_MODE_GET: - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_CON) & - (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)); - if (from_kernel) - *((unsigned int *)data) = tmp; - else - if (copy_to_user((void *)data, - (void *)&tmp, - sizeof(tmp))) - ret_val = -EFAULT; - break; - - case IFX_SSC_ABORT: - ifx_ssc_abort(info); - break; - - case IFX_SSC_GPO_OUT_SET: - if (from_kernel) - tmp = *((unsigned long *)data); - else - if (copy_from_user((void *)&tmp, - (void *)data, sizeof(tmp))) { - ret_val = -EFAULT; - break; - } - if (tmp > IFX_SSC_MAX_GPO_OUT) - ret_val = -EINVAL; - else - WRITE_PERIPHERAL_REGISTER - (1<<(tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS), - info->mapbase + IFX_SSC_WHBGPOSTAT); - break; - case IFX_SSC_GPO_OUT_CLR: - if (from_kernel) - tmp = *((unsigned long *)data); - else - if (copy_from_user((void *)&tmp, - (void *)data, sizeof(tmp))) { - ret_val = -EFAULT; - break; - } - if (tmp > IFX_SSC_MAX_GPO_OUT) - ret_val = -EINVAL; - else { - WRITE_PERIPHERAL_REGISTER - (1<<(tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS), - info->mapbase + IFX_SSC_WHBGPOSTAT); - } - break; - case IFX_SSC_GPO_OUT_GET: - tmp = READ_PERIPHERAL_REGISTER - (info->mapbase + IFX_SSC_GPOSTAT); - if (from_kernel) - *((unsigned int *)data) = tmp; - else - if (copy_to_user((void *)data, - (void *)&tmp, - sizeof(tmp))) - ret_val = -EFAULT; - break; - case IFX_SSC_FRM_STATUS_GET: - ifx_ssc_frm_status_get(info); - if (from_kernel) - memcpy((void *)data, (void *)&info->frm_status, - sizeof(struct ifx_ssc_frm_status)); - else - if (copy_to_user((void *)data, - (void *)&info->frm_status, - sizeof(struct ifx_ssc_frm_status))) - ret_val = -EFAULT; - break; - case IFX_SSC_FRM_CONTROL_GET: - ifx_ssc_frm_control_get(info); - if (from_kernel) - memcpy((void *)data, (void *)&info->frm_opts, - sizeof(struct ifx_ssc_frm_opts)); - else - if (copy_to_user((void *)data, - (void *)&info->frm_opts, - sizeof(struct ifx_ssc_frm_opts))) - ret_val = -EFAULT; - break; - case IFX_SSC_FRM_CONTROL_SET: - if (from_kernel) - memcpy((void *)&info->frm_opts, (void *)data, - sizeof(struct ifx_ssc_frm_opts)); - else - if (copy_to_user((void *)&info->frm_opts, - (void *)data, - sizeof(struct ifx_ssc_frm_opts))){ - ret_val = -EFAULT; - break; - } - ret_val = ifx_ssc_frm_control_set(info); - break; - case IFX_SSC_HWOPTS_SET: - /* data must be a pointer to a struct ifx_ssc_hwopts */ - /* if the buffers are not empty then the port is */ - /* busy and we shouldn't change things on-the-fly! */ - if (!info->txbuf || !info->rxbuf || - (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_BUSY)) { - ret_val = -EBUSY; - break; - } - if (from_kernel) - memcpy((void *)&info->opts, (void *)data, - sizeof(struct ifx_ssc_hwopts)); - else - if (copy_from_user((void *)&info->opts, - (void *)data, - sizeof(struct ifx_ssc_hwopts))) - { - ret_val = -EFAULT; - break; - } - if (ifx_ssc_hwinit(info) < 0) - { - ret_val = -EIO; - } - break; - case IFX_SSC_HWOPTS_GET: - /* data must be a pointer to a struct ifx_ssc_hwopts */ - if (from_kernel) - memcpy((void *)data, (void *)&info->opts, - sizeof(struct ifx_ssc_hwopts)); - else - if (copy_to_user((void *)data, - (void *)&info->opts, - sizeof(struct ifx_ssc_hwopts))) - ret_val = -EFAULT; - break; - default: - ret_val = -ENOIOCTLCMD; - } - - return ret_val; -} /* ifx_ssc_ioctl */ -EXPORT_SYMBOL(ifx_ssc_ioctl); - -///* the poll routine */ -//static unsigned int -//ifx_ssc_poll(struct file *filp, struct poll_table_struct *pts) -//{ -// int unit = MINOR(filp->f_dentry->d_inode->i_rdev); -// struct ifx_ssc_port *info; -// unsigned int mask = 0; -// int spc; -// -// info = &isp[unit]; -// -// /* add event to the wait queues */ -// /* DO NOT FORGET TO DO A WAKEUP ON THESE !!!! */ -// poll_wait(filp, &info->pwait, pts); -// -// /* are there bytes in the RX SW-FIFO? */ -// if (info->rxrp != info->rxwp) -// mask |= POLLIN | POLLRDNORM; -// -// /* free space in the TX SW-FIFO */ -// spc = info->txrp - info->txwp - 1; -// if (spc < 0) -// spc += TX_BUFSIZE; -//#ifdef IFX_SSC_USEDMA -// /* writing always works, except in the DMA case when all descriptors */ -// /* are used up */ -// if (unit == 1 && info->dma_freecnt == 0) -// spc = 0; -//#endif -// if (spc > 0) -// mask |= POLLOUT | POLLWRNORM; -// -// return (mask); -//} - -static int -ifx_ssc1_read_proc(char *page, char **start, off_t offset, int count, int *eof, void *data) -{ - int off = 0; - unsigned long flags; - - /* don't want any interrupts here */ - save_flags(flags); - cli(); - - - /* print statistics */ - off += sprintf(page+off, "Statistics for Infineon Synchronous Serial Controller SSC1\n"); - off += sprintf(page+off, "RX overflow errors %d\n", isp[0].stats.rxOvErr); - off += sprintf(page+off, "RX underflow errors %d\n", isp[0].stats.rxUnErr); - off += sprintf(page+off, "TX overflow errors %d\n", isp[0].stats.txOvErr); - off += sprintf(page+off, "TX underflow errors %d\n", isp[0].stats.txUnErr); - off += sprintf(page+off, "Abort errors %d\n", isp[0].stats.abortErr); - off += sprintf(page+off, "Mode errors %d\n", isp[0].stats.modeErr); - off += sprintf(page+off, "RX Bytes %d\n", isp[0].stats.rxBytes); - off += sprintf(page+off, "TX Bytes %d\n", isp[0].stats.txBytes); - - restore_flags (flags); /* XXXXX */ - *eof = 1; - return (off); -} - - -/* - * This routine prints out the appropriate serial driver version number - */ -static inline void -show_version(void) -{ -#if 0 - printk("Infineon Technologies Synchronous Serial Controller (SSC) driver\n" - " version %s - built %s %s\n", IFX_SSC_DRV_VERSION, __DATE__, __TIME__); -#endif -} /* show_version */ - - -/* - * Due to the fact that a port can be dynamically switched between slave - * and master mode using an IOCTL the hardware is not initialized here, - * but in ifx_ssc_hwinit() as a result of an IOCTL. - */ -int __init -ifx_ssc_init(void) -{ - struct ifx_ssc_port *info; - int i, nbytes; - unsigned long flags; - int ret_val; - - // ### TO DO: dynamic port count evaluation due to pin multiplexing - - ret_val = -ENOMEM; - nbytes = PORT_CNT * sizeof(struct ifx_ssc_port); - isp = (struct ifx_ssc_port *)kmalloc(nbytes, GFP_KERNEL); - if (isp == NULL) - { - printk("%s: no memory for isp\n", __FUNCTION__); - return (ret_val); - } - memset(isp, 0, nbytes); - - show_version(); - - /* register the device */ - ret_val = -ENXIO; -/* - i = maj; -*/ - if ((i = register_chrdev(maj, "ssc", &ifx_ssc_fops)) < 0) - { - printk("Unable to register major %d for the Infineon SSC\n", maj); - if (maj == 0){ - goto errout; - } - else{ - maj = 0; - if ((i = register_chrdev(maj, "ssc", &ifx_ssc_fops)) < 0) - { - printk("Unable to register major %d for the Infineon SSC\n", maj); - goto errout; - } - } - } - if (maj == 0) maj = i; - //printk("registered major %d for Infineon SSC\n", maj); - - /* set default values in ifx_ssc_port */ - for (i = 0; i < PORT_CNT; i++) { - info = &isp[i]; - info->port_nr = i; - /* default values for the HwOpts */ - info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT; - info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT; - info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT; - info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT; - info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT; - info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK; - info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE; - info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA; - info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY; - info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE; - info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL; - info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH; - info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX; - info->opts.gpoCs = IFX_SSC_DEF_GPO_CS; - info->opts.gpoInv = IFX_SSC_DEF_GPO_INV; - info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE; - info->baud = IFX_SSC_DEF_BAUDRATE; - info->rxbuf = NULL; - info->txbuf = NULL; - /* values specific to SSC1 */ - if (i == 0) { - info->mapbase = AMAZON_SSC_BASE_ADD_0; - // ### TO DO: power management - - // setting interrupt vectors - info->txirq = IFX_SSC_TIR; - info->rxirq = IFX_SSC_RIR; - info->errirq = IFX_SSC_EIR; -/* - info->frmirq = IFX_SSC_FIR; -*/ - } - /* activate SSC */ - /* CLC.DISS = 0 */ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC); - -// ### TO DO: multiple instances - - init_waitqueue_head(&info->rwait); - //init_waitqueue_head(&info->pwait); - - local_irq_save(flags); - - // init serial framing register - WRITE_PERIPHERAL_REGISTER(IFX_SSC_DEF_SFCON, info->mapbase + IFX_SSC_SFCON); - - /* try to get the interrupts */ - // ### TO DO: interrupt handling with multiple instances - ret_val = ifx_int_wrapper.request(info->txirq, ifx_ssc_tx_int, - 0, "ifx_ssc_tx", info); - if (ret_val){ - printk("%s: unable to get irq %d\n", __FUNCTION__, - info->txirq); - local_irq_restore(flags); - goto errout; - } - ret_val = ifx_int_wrapper.request(info->rxirq, ifx_ssc_rx_int, - 0, "ifx_ssc_rx", info); - if (ret_val){ - printk("%s: unable to get irq %d\n", __FUNCTION__, - info->rxirq); - local_irq_restore(flags); - goto irqerr; - } - ret_val = ifx_int_wrapper.request(info->errirq, ifx_ssc_err_int, - 0, "ifx_ssc_err", info); - if (ret_val){ - printk("%s: unable to get irq %d\n", __FUNCTION__, - info->errirq); - local_irq_restore(flags); - goto irqerr; - } -/* - ret_val = ifx_int_wrapper.request(info->frmirq, ifx_ssc_frm_int, - 0, "ifx_ssc_frm", info); - if (ret_val){ - printk("%s: unable to get irq %d\n", __FUNCTION__, - info->frmirq); - local_irq_restore(flags); - goto irqerr; - } - -*/ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_DEF_IRNEN, info->mapbase + IFX_SSC_IRN_EN); - - local_irq_restore(flags); - } // for (i = 0; i < PORT_CNT; i++) - - /* init the SSCs with default values */ - for (i = 0; i < PORT_CNT; i++) - { - info = &isp[i]; - if (ifx_ssc_hwinit(info) < 0) - { - printk("%s: hardware init failed for port %d\n", - __FUNCTION__, i); - goto irqerr; - } - } - - /* register /proc read handler */ - // ### TO DO: multiple instances - /* for SSC1, which is always present */ - create_proc_read_entry("driver/ssc1", 0, NULL, ifx_ssc1_read_proc, NULL); - return 0; - -irqerr: - // ### TO DO: multiple instances - ifx_int_wrapper.free(isp[0].txirq,&isp[0]); - ifx_int_wrapper.free(isp[0].rxirq,&isp[0]); - ifx_int_wrapper.free(isp[0].errirq,&isp[0]); -/* - ifx_int_wrapper.free(isp[0].frmirq, &isp[0]); -*/ -errout: - /* free up any allocated memory in the error case */ - kfree(isp); - return (ret_val); -} /* ifx_ssc_init */ - - -void -ifx_ssc_cleanup_module(void) -{ - int i; - - /* free up any allocated memory */ - for (i = 0; i < PORT_CNT; i++) - { - /* disable the SSC */ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE,isp[i].mapbase + IFX_SSC_WHBSTATE); - /* free the interrupts */ - ifx_int_wrapper.free(isp[i].txirq, &isp[i]); - ifx_int_wrapper.free(isp[i].rxirq, &isp[i]); - ifx_int_wrapper.free(isp[i].errirq, &isp[i]); -/* - ifx_int_wrapper.free(isp[i].frmirq, &isp[i]); - - if (isp[i].rxbuf != NULL) - kfree(isp[i].rxbuf); - if (isp[i].txbuf != NULL) - kfree(isp[i].txbuf); -*/ - } - kfree(isp); - /* unregister the device */ - if (unregister_chrdev(maj, "ssc")) - { - printk("Unable to unregister major %d for the SSC\n", maj); - } - /* delete /proc read handler */ - remove_proc_entry("driver/ssc1", NULL); - remove_proc_entry("driver/ssc2", NULL); -} /* ifx_ssc_cleanup_module */ - -module_exit(ifx_ssc_cleanup_module); - -/* Module entry-points */ -module_init(ifx_ssc_init); - -#ifndef MODULE -static int __init -ifx_ssc_set_maj(char *str) -{ - maj = simple_strtol(str, NULL, 0); - return 1; -} -__setup("ssc_maj=", ifx_ssc_set_maj); -#endif /* !MODULE */ - -#define AMAZON_SSC_EMSG(fmt,arg...) printk("%s: "fmt,__FUNCTION__, ##arg) -/* Brief: chip select enable - */ -inline int amazon_ssc_cs_low(u32 pin) -{ - int ret=0; - if ((ret=ifx_ssc_ioctl((struct inode *)0, NULL,IFX_SSC_GPO_OUT_CLR, (unsigned long)&pin))){ - AMAZON_SSC_EMSG("clear CS %d fails\n",pin); - } - wmb(); - return ret; -} -EXPORT_SYMBOL(amazon_ssc_cs_low); -/* Brief: chip select disable - */ -inline int amazon_ssc_cs_high(u32 pin) -{ - int ret=0; - if ((ret=ifx_ssc_ioctl((struct inode *)0, NULL,IFX_SSC_GPO_OUT_SET, (unsigned long)&pin))){ - AMAZON_SSC_EMSG("set CS %d fails\n", pin); - } - wmb(); - return ret; -} -EXPORT_SYMBOL(amazon_ssc_cs_high); -/* Brief: one SSC session - * Parameter: - * tx_buf - * tx_len - * rx_buf - * rx_len - * session_mode: IFX_SSC_MODE_RXTX or IFX_SSC_MODE_TX - * Return: >=0 number of bytes received (if rx_buf != 0) or transmitted - * <0 error code - * Description: - * 0. copy data to internal buffer - * 1. Write command - * 2a. If SSC_SESSION_MODE_TXONLY, read tx_len data - * 2b. If not Read back (tx_len + rx_len) data - * 3. copy internal buffer to rx buf if necessary - */ -static int ssc_session(char * tx_buf, u32 tx_len, char * rx_buf, u32 rx_len) -{ - int ret=0; - - char * ssc_tx_buf=NULL; - char * ssc_rx_buf=NULL; - -// volatile char ssc_tx_buf[128]={0}; -// volatile char ssc_rx_buf[128]={0}; - - int eff_size=0; - u8 mode=0; - - if (tx_buf == NULL && tx_len ==0 && rx_buf == NULL && rx_len == 0){ - AMAZON_SSC_EMSG("invalid parameters\n"); - ret=-EINVAL; - goto ssc_session_exit; - }else if (tx_buf == NULL || tx_len == 0){ - if (rx_buf != NULL && rx_len != 0){ - mode = IFX_SSC_MODE_RX; - }else{ - AMAZON_SSC_EMSG("invalid parameters\n"); - ret=-EINVAL; - goto ssc_session_exit; - } - }else if (rx_buf == NULL || rx_len ==0){ - if (tx_buf != NULL && tx_len != 0){ - mode = IFX_SSC_MODE_TX; - }else{ - AMAZON_SSC_EMSG("invalid parameters\n"); - ret=-EINVAL; - goto ssc_session_exit; - } - }else{ - mode = IFX_SSC_MODE_RXTX; - } - - if (mode == IFX_SSC_MODE_RXTX){ - eff_size = tx_len + rx_len; - }else if (mode == IFX_SSC_MODE_RX){ - eff_size = rx_len; - }else{ - eff_size = tx_len; - } - - //4 bytes alignment, required by driver - /* change by TaiCheng */ - //if (in_irq()){ - if (1){ - ssc_tx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_ATOMIC); - ssc_rx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_ATOMIC); - }else{ - ssc_tx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_KERNEL); - ssc_rx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_KERNEL); - } - if (ssc_tx_buf == NULL || ssc_rx_buf == NULL){ - AMAZON_SSC_EMSG("no memory for size of %d\n", eff_size); - ret = -ENOMEM; - goto ssc_session_exit; - } - memset((void*)ssc_tx_buf, 0, eff_size); - memset((void*)ssc_rx_buf, 0, eff_size); - - if (tx_len>0){ - memcpy(ssc_tx_buf, tx_buf, tx_len); - } - - ret=ifx_ssc_kwrite(0, ssc_tx_buf, eff_size); - - if (ret > 0) { - ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite - } - - if ( ret != eff_size ){ - AMAZON_SSC_EMSG("ifx_ssc_write return %d\n",ret); - goto ssc_session_exit; - } - ret=ifx_ssc_kread(0, ssc_rx_buf,eff_size); - if ( ret != eff_size ){ - AMAZON_SSC_EMSG("ifx_ssc_read return %d\n",ret); - goto ssc_session_exit; - } - - memcpy(rx_buf, ssc_rx_buf+tx_len, rx_len); - - if (mode == IFX_SSC_MODE_TX) { - ret = tx_len; - }else{ - ret = rx_len; - } -ssc_session_exit: - - if (ssc_tx_buf != NULL) kfree(ssc_tx_buf); - if (ssc_rx_buf != NULL) kfree(ssc_rx_buf); - - if (ret<0) { - printk("ssc session fails\n"); - } - return ret; -} -/* Brief: TX-RX session - * Parameter: - * tx_buf - * tx_len - * rx_buf - * rx_len - * Return: >=0 number of bytes received - * <0 error code - * Description: - * 1. TX session - * 2. RX session - */ -int amazon_ssc_txrx(char * tx_buf, u32 tx_len, char * rx_buf, u32 rx_len) -{ - return ssc_session(tx_buf,tx_len,rx_buf,rx_len); -} -EXPORT_SYMBOL(amazon_ssc_txrx); -/* Brief: TX only session - * Parameter: - * tx_buf - * tx_len - * Return: >=0 number of bytes transmitted - * <0 error code - */ -int amazon_ssc_tx(char * tx_buf, u32 tx_len) -{ - return ssc_session(tx_buf,tx_len,NULL,0); -} -EXPORT_SYMBOL(amazon_ssc_tx); -/* Brief: RX only session - * Parameter: - * rx_buf - * rx_len - * Return: >=0 number of bytes received - * <0 error code - */ -int amazon_ssc_rx(char * rx_buf, u32 rx_len) -{ - return ssc_session(NULL,0,rx_buf,rx_len); -} -EXPORT_SYMBOL(amazon_ssc_rx); - diff --git a/target/linux/amazon/files/drivers/char/watchdog/amazon_wdt.c b/target/linux/amazon/files/drivers/char/watchdog/amazon_wdt.c deleted file mode 100644 index 3c58d2fea8..0000000000 --- a/target/linux/amazon/files/drivers/char/watchdog/amazon_wdt.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright 2004 Wu Qi Ming - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DRV_NAME "AMAZON WDT:" - -#undef AMAZON_WDT_DEBUG - -extern unsigned int amazon_get_fpi_hz(void); -static int amazon_wdt_isopen = 0; - -#ifdef AMAZON_WDT_DEBUG -static struct proc_dir_entry* amazon_wdt_dir; -#endif - -int wdt_enable(int timeout) -{ - u32 hard_psw, ffpi; - int reload_value, divider = 1; - - ffpi = amazon_get_fpi_hz(); - - reload_value = 65536 - timeout * ffpi / 256; - - if (reload_value < 0) { - divider = 0; - reload_value = 65536 - timeout * ffpi / 16384; - } - - if (reload_value < 0){ - printk(KERN_INFO DRV_NAME "timeout too large %d\n", timeout); - return -EINVAL; - } - - printk(KERN_INFO DRV_NAME "timeout:%d reload_value: %8x\n", timeout, reload_value); - - hard_psw = (amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) + - (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0; - amazon_writel(hard_psw, AMAZON_WDT_CON0); - wmb(); - - amazon_writel((hard_psw & 0xff00) + (reload_value << 16) + 0xf2, AMAZON_WDT_CON0); - wmb(); - - amazon_writel(divider << 2, AMAZON_WDT_CON1); - wmb(); - - hard_psw = (amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) + - (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0; - amazon_writel(hard_psw, AMAZON_WDT_CON0); - wmb(); - - amazon_writel_masked(AMAZON_WDT_CON0, 0xff, 0xf3); - wmb(); - return 0; -} - -void wdt_disable(void) -{ - u32 hard_psw = 0; - - hard_psw = (amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) + - (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0; - amazon_writel(hard_psw, AMAZON_WDT_CON0); - wmb(); - - amazon_writel_masked(AMAZON_WDT_CON0, 0xff, 0xf2); - wmb(); - - amazon_writel_masked(AMAZON_WDT_CON1, 0x8, 0x8); - wmb(); - - hard_psw=(amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) + - (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0; - amazon_writel(hard_psw, AMAZON_WDT_CON0); - wmb(); - - amazon_writel_masked(AMAZON_WDT_CON0, 0xff, 0xf3); - wmb(); - - return; -} - -static int wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -{ - int result=0; - static int timeout=-1; - - switch(cmd){ - case AMAZON_WDT_IOC_START: - printk(KERN_INFO DRV_NAME "enable watch dog timer!\n"); - if (copy_from_user((void*)&timeout, (void*)arg, sizeof (int))) { - printk(KERN_INFO DRV_NAME "invalid argument\n"); - result=-EINVAL; - } else if ((result = wdt_enable(timeout)) < 0) { - timeout = -1; - } - break; - - case AMAZON_WDT_IOC_STOP: - printk(KERN_INFO DRV_NAME "disable watch dog timer\n"); - timeout = -1; - wdt_disable(); - break; - - case AMAZON_WDT_IOC_PING: - if (timeout < 0) { - result = -EIO; - } else { - result = wdt_enable(timeout); - } - break; - - default: - result=-EINVAL; - break; - } - return result; -} - -static ssize_t wdt_read(struct file *file, char *buf, size_t count, loff_t *offset) -{ - return 0; -} - -static ssize_t wdt_write(struct file *file, const char *buf, size_t count, loff_t *offset) -{ - return count; -} - -static int wdt_open(struct inode *inode, struct file *file) -{ - if (amazon_wdt_isopen == 1) - return -EBUSY; - - amazon_wdt_isopen = 1; - printk(KERN_INFO DRV_NAME "opened\n"); - return 0; -} - -static int wdt_release(struct inode *inode, struct file *file) -{ - amazon_wdt_isopen = 0; - printk(KERN_INFO DRV_NAME "closed\n"); - return 0; -} - -#ifdef AMAZON_WDT_DEBUG -int wdt_register_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int len=0; - len+=sprintf(buf+len,"NMISR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_NMISR)); - len+=sprintf(buf+len,"RST_REQ: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_RST_REQ)); - len+=sprintf(buf+len,"RST_SR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_RST_SR)); - len+=sprintf(buf+len,"WDT_CON0: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_CON0)); - len+=sprintf(buf+len,"WDT_CON1: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_CON1)); - len+=sprintf(buf+len,"WDT_SR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_SR)); - *eof = 1; - return len; -} -#endif - -static struct file_operations wdt_fops = { - read: wdt_read, - write: wdt_write, - ioctl: wdt_ioctl, - open: wdt_open, - release: wdt_release, -}; - -int __init amazon_wdt_init_module(void) -{ - int result = result = register_chrdev(0, "watchdog", &wdt_fops); - - if (result < 0) { - printk(KERN_INFO DRV_NAME "cannot register device\n"); - return result; - } - -#ifdef AMAZON_WDT_DEBUG - amazon_wdt_dir=proc_mkdir("amazon_wdt",NULL); - create_proc_read_entry("wdt_register", 0, amazon_wdt_dir, - wdt_register_proc_read, NULL); -#endif - - amazon_wdt_isopen=0; - printk(KERN_INFO DRV_NAME "driver loaded but inactive"); - return 0; -} - -void amazon_wdt_cleanup_module(void) -{ - unregister_chrdev(0, "watchdog"); -#ifdef AMAZON_WDT_DEBUG - remove_proc_entry("wdt_register", amazon_wdt_dir); - remove_proc_entry("amazon_wdt", NULL); -#endif - printk(KERN_INFO DRV_NAME "unregistered"); - return; -} - -MODULE_LICENSE ("GPL"); -MODULE_AUTHOR("Infineon / John Crispin "); -MODULE_DESCRIPTION("AMAZON WDT driver"); - -module_init(amazon_wdt_init_module); -module_exit(amazon_wdt_cleanup_module); - diff --git a/target/linux/amazon/files/drivers/mtd/maps/amazon.c b/target/linux/amazon/files/drivers/mtd/maps/amazon.c deleted file mode 100644 index 3e7dc4f583..0000000000 --- a/target/linux/amazon/files/drivers/mtd/maps/amazon.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Handle mapping of the flash memory access routines - * on Amazon based devices. - * - * Copyright(C) 2004 peng.liu@infineon.com - * - * This code is GPLed - * - */ -// 000005:fchang 2005/6/2 Modified by Bingtao to double check if the EBU is enabled/disabled -// 506231:tc.chen 2005/06/23 increase firmware partition size form 192KB to 256KB -// 050701:linmars 2005/07/01 fix flash size wrong alignment after increase firmware partition -// 165001:henryhsu 2005/8/18 Remove the support for Intel flash because of 2.1 not enough rootfs partition size -// 165001:henryhsu 2005/9/7 Rolback to support INtel flash -// 509071:tc.chen 2005/09/07 Reduced flash writing time -// 511046:linmars 2005/11/04 change bootloader size from 128 into 64 -// 511241:linmars 2005/11/24 merge TaiChen's IRM patch - -// copyright 2005 infineon - -// copyright 2007 john crispin -// copyright 2007 felix fietkau - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define AMAZON_PCI_ARB_CTL_ALT 0xb100205c -#define AMAZON_MTD_REG32( addr ) (*(volatile u32 *)(addr)) - - -static struct map_info amazon_map = { - .name = "AMAZON_FLASH", - .bankwidth = 2, - .size = 0x400000, -}; - -static map_word amazon_read16(struct map_info * map, unsigned long ofs) -{ - map_word temp; - ofs ^= 2; - temp.x[0] = *((__u16 *) (map->virt + ofs)); - return temp; -} - -static void amazon_write16(struct map_info *map, map_word d, unsigned long adr) -{ - adr ^= 2; - *((__u16 *) (map->virt + adr)) = d.x[0]; -} - -void amazon_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) -{ - u8 *p; - u8 *to_8; - ssize_t l = len; - from = (unsigned long) (from + map->virt); - p = (u8 *) from; - to_8 = (u8 *) to; - while(len--){ - *to_8++ = *p++; - } -} - -void amazon_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) -{ - u8 *p = (u8*) from; - u8 *to_8; - to += (unsigned long) map->virt; - to_8 = (u8*)to; - while(len--){ - *p++ = *to_8++; - } -} - -#define UBOOT_SIZE 0x40000 - -static struct mtd_partition amazon_partitions[3] = { - { - name:"U-Boot", /* U-Boot firmware */ - offset:0x00000000, - size:UBOOT_SIZE , /* 128k */ - }, - { - name:"kernel", /* firmware */ - offset:UBOOT_SIZE, - size:0x00100000, /* 192K */ - }, - { - name:"rootfs", /* default partition */ - offset:0x00200000, - size:0x00200000, - }, -}; - - -unsigned long flash_start = 0x13000000; -unsigned long flash_size = 0x800000; -unsigned long uImage_size = 0x10000d; - -int find_uImage_size(unsigned long start_offset){ - unsigned long temp; - - printk("trying to find uImage and its size\n"); - amazon_copy_from(&amazon_map, &temp, start_offset + 12, 4); - printk("kernel size is %d \n", temp + 0x40); - return temp + 0x40; -} - -int __init init_amazon_mtd(void) -{ - int ret = 0; - struct mtd_info *mymtd = NULL; - struct mtd_partition *parts = NULL; - - *AMAZON_EBU_BUSCON0 = 0x1d7ff; - - amazon_map.read = amazon_read16; - amazon_map.write = amazon_write16; - amazon_map.copy_from = amazon_copy_from; - amazon_map.copy_to = amazon_copy_to; - - amazon_map.phys = flash_start; - amazon_map.virt = ioremap_nocache(flash_start, flash_size); - - if (!amazon_map.virt) { - printk(KERN_WARNING "Failed to ioremap!\n"); - return -EIO; - } - - mymtd = (struct mtd_info *) do_map_probe("cfi_probe", &amazon_map); - if (!mymtd) { - iounmap(amazon_map.virt); - printk("probing failed\n"); - return -ENXIO; - } - - mymtd->owner = THIS_MODULE; - parts = &amazon_partitions[0]; - amazon_partitions[2].offset = UBOOT_SIZE + find_uImage_size(amazon_partitions[1].offset); - amazon_partitions[1].size = mymtd->size - amazon_partitions[1].offset - (2 * mymtd->erasesize); - amazon_partitions[2].size = mymtd->size - amazon_partitions[2].offset - (2 * mymtd->erasesize); - add_mtd_partitions(mymtd, parts, 3); - return 0; -} - -static void __exit cleanup_amazon_mtd(void) -{ - /* FIXME! */ -} - -module_init(init_amazon_mtd); -module_exit(cleanup_amazon_mtd); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("john crispin blogic@openwrt.org"); -MODULE_DESCRIPTION("MTD map driver for AMAZON boards"); diff --git a/target/linux/amazon/files/drivers/net/amazon_sw.c b/target/linux/amazon/files/drivers/net/amazon_sw.c deleted file mode 100644 index d19db6e36d..0000000000 --- a/target/linux/amazon/files/drivers/net/amazon_sw.c +++ /dev/null @@ -1,876 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - */ -//----------------------------------------------------------------------- -/* - * Description: - * Driver for Infineon Amazon 3 port switch - */ -//----------------------------------------------------------------------- -/* Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com] - * Created: 7-April-2004 - */ -//----------------------------------------------------------------------- -/* History - * Changed on: Jun 28, 2004 - * Changed by: peng.liu@infineon.com - * Reason: add hardware flow control (HFC) (CONFIG_NET_HW_FLOWCONTROL) - * - * Changed on: Apr 6, 2005 - * Changed by: mars.lin@infineon.com - * Reason : supoort port identification - */ - - -// copyright 2004-2005 infineon.com - -// copyright 2007 john crispin -// copyright 2007 felix fietkau - - -// TODO -// port vlan code from bcrm target... the tawainese code was scrapped due to crappyness -// check all the mmi reg settings and possibly document them better -// verify the ethtool code -// remove the while(1) stuff -// further clean up and rework ... but it works for now -// check the mode[]=bridge stuff -// verify that the ethaddr can be set from u-boot - - -#ifndef __KERNEL__ -#define __KERNEL__ -#endif - - -#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -#define MODVERSIONS -#endif - -#if defined(MODVERSIONS) && !defined(__GENKSYMS__) -#include -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -// how many mii ports are there ? -#define AMAZON_SW_INT_NO 2 - -#define ETHERNET_PACKET_DMA_BUFFER_SIZE 1536 - -/***************************************** Module Parameters *************************************/ -char mode[] = "bridge"; -module_param_array(mode, charp, NULL, 0); - -static int timeout = 1 * HZ; -module_param(timeout, int, 0); - -int switch_init(struct net_device *dev); -void switch_tx_timeout(struct net_device *dev); - -struct net_device switch_devs[2] = { - {init:switch_init,}, - {init:switch_init,} -}; - -int add_mac_table_entry(u64 entry_value) -{ - int i; - u32 data1, data2; - - AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) = ~7; - - for (i = 0; i < 32; i++) { - AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0x80000000 | 0x20 | i; - while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {}; - data1 = AMAZON_SW_REG32(AMAZON_SW_DATA1); - data2 = AMAZON_SW_REG32(AMAZON_SW_DATA2); - if ((data1 & (0x00700000)) != 0x00700000) - continue; - AMAZON_SW_REG32(AMAZON_SW_DATA1) = (u32) (entry_value >> 32); - AMAZON_SW_REG32(AMAZON_SW_DATA2) = (u32) entry_value & 0xffffffff; - AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0xc0000020 | i; - while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {}; - break; - } - AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) |= 7; - if (i >= 32) - return -1; - return OK; -} - -u64 read_mac_table_entry(int index) -{ - u32 data1, data2; - u64 value; - AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0x80000000 | 0x20 | index; - while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {}; - data1 = AMAZON_SW_REG32(AMAZON_SW_DATA1) & 0xffffff; - data2 = AMAZON_SW_REG32(AMAZON_SW_DATA2); - value = (u64) data1 << 32 | (u64) data2; - return value; -} - -int write_mac_table_entry(int index, u64 value) -{ - u32 data1, data2; - data1 = (u32) (value >> 32); - data2 = (u32) value & 0xffffffff; - AMAZON_SW_REG32(AMAZON_SW_DATA1) = data1; - AMAZON_SW_REG32(AMAZON_SW_DATA2) = data2; - AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0xc0000020 | index; - while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {}; - return OK; -} - -u32 get_mdio_reg(int phy_addr, int reg_num) -{ - u32 value; - AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = (3 << 30) | ((phy_addr & 0x1f) << 21) | ((reg_num & 0x1f) << 16); - while (AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & (1 << 31)) {}; - value = AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & 0xffff; - return value; -} - -int set_mdio_reg(int phy_addr, int reg_num, u32 value) -{ - AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = (2 << 30) | ((phy_addr & 0x1f) << 21) | ((reg_num & 0x1f) << 16) | (value & 0xffff); - while (AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & (1 << 31)) {}; - return OK; -} - -int auto_negotiate(int phy_addr) -{ - u32 value = 0; - value = get_mdio_reg(phy_addr, MDIO_BASE_CONTROL_REG); - set_mdio_reg(phy_addr, MDIO_BASE_CONTROL_REG, (value | RESTART_AUTO_NEGOTIATION | AUTO_NEGOTIATION_ENABLE | PHY_RESET)); - return OK; -} - -/* - In this version of switch driver, we split the dma channels for the switch. - 2 for port0 and 2 for port1. So that we can do internal bridging if necessary. - In switch mode, packets coming in from port0 or port1 is able to do Destination - address lookup. Packets coming from port0 with destination address of port1 should - not go to pmac again. The switch hardware should be able to do the switch in the hard - ware level. Packets coming from the pmac should not do the DA look up in that the - desination is already known for the kernel. It only needs to go to the correct NIC to - find its way out. - */ -int amazon_sw_chip_init(void) -{ - u32 tmp1; - int i = 0; - - /* Aging tick select: 5mins */ - tmp1 = 0xa0; - if (strcmp(mode, "bridge") == 0) { - // bridge mode, set militarised mode to 1, no learning! - tmp1 |= 0xC00; - } else { - // enable learning for P0 and P1, - tmp1 |= 3; - } - - /* unknown broadcast/multicast/unicast to all ports */ - AMAZON_SW_REG32(AMAZON_SW_UN_DEST) = 0x1ff; - - AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) = tmp1; - - /* OCS:1 set OCS bit, split the two NIC in rx direction EDL:1 (enable DA lookup) */ -#if defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT) || defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT_MODULE) - AMAZON_SW_REG32(AMAZON_SW_P2_PCTL) = 0x700; -#else - AMAZON_SW_REG32(AMAZON_SW_P2_PCTL) = 0x401; -#endif - - /* EPC: 1 split the two NIC in tx direction CRC is generated */ - AMAZON_SW_REG32(AMAZON_SW_P2_CTL) = 0x6; - - // for bi-directional - AMAZON_SW_REG32(AMAZON_SW_P0_WM) = 0x14141412; - AMAZON_SW_REG32(AMAZON_SW_P1_WM) = 0x14141412; - AMAZON_SW_REG32(AMAZON_SW_P2_WM) = 0x28282826; - AMAZON_SW_REG32(AMAZON_SW_GBL_WM) = 0x0; - - AMAZON_SW_REG32(AMAZON_CGU_PLL0SR) = (AMAZON_SW_REG32(AMAZON_CGU_PLL0SR)) | 0x58000000; - // clock for PHY - AMAZON_SW_REG32(AMAZON_CGU_IFCCR) = (AMAZON_SW_REG32(AMAZON_CGU_IFCCR)) | 0x80000004; - // enable power for PHY - AMAZON_SW_REG32(AMAZON_PMU_PWDCR) = (AMAZON_SW_REG32(AMAZON_PMU_PWDCR)) | AMAZON_PMU_PWDCR_EPHY; - // set reverse MII, enable MDIO statemachine - AMAZON_SW_REG32(AMAZON_SW_MDIO_CFG) = 0x800027bf; - while (1) - if (((AMAZON_SW_REG32(AMAZON_SW_MDIO_CFG)) & 0x80000000) == 0) - break; - AMAZON_SW_REG32(AMAZON_SW_EPHY) = 0xff; - - // auto negotiation - AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = 0x83e08000; - auto_negotiate(0x1f); - - /* enable all ports */ - AMAZON_SW_REG32(AMAZON_SW_PS_CTL) = 0x7; - for (i = 0; i < 32; i++) - write_mac_table_entry(i, 1 << 50); - return 0; -} - -static unsigned char my_ethaddr[MAX_ADDR_LEN]; -/* need to get the ether addr from u-boot */ -static int __init ethaddr_setup(char *line) -{ - char *ep; - int i; - - memset(my_ethaddr, 0, MAX_ADDR_LEN); - for (i = 0; i < 6; i++) { - my_ethaddr[i] = line ? simple_strtoul(line, &ep, 16) : 0; - if (line) - line = (*ep) ? ep + 1 : ep; - } - printk("mac address %2x-%2x-%2x-%2x-%2x-%2x \n", my_ethaddr[0], my_ethaddr[1], my_ethaddr[2], my_ethaddr[3], my_ethaddr[4], my_ethaddr[5]); - return 0; -} - -__setup("ethaddr=", ethaddr_setup); - -static void open_rx_dma(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; - struct dma_device_info *dma_dev = priv->dma_device; - int i; - - for (i = 0; i < dma_dev->num_rx_chan; i++) - dma_dev->rx_chan[i].control = 1; - dma_device_update_rx(dma_dev); -} - -#ifdef CONFIG_NET_HW_FLOWCONTROL -static void close_rx_dma(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; - struct dma_device_info *dma_dev = priv->dma_device; - int i; - - for (i = 0; i < dma_dev->num_rx_chan; i++) - dma_dev->rx_chan[i].control = 0; - dma_device_update_rx(dma_dev); -} - -void amazon_xon(struct net_device *dev) -{ - unsigned long flag; - local_irq_save(flag); - open_rx_dma(dev); - local_irq_restore(flag); -} -#endif - -int switch_open(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; - if (!strcmp(dev->name, "eth1")) { - priv->mdio_phy_addr = PHY0_ADDR; - } - open_rx_dma(dev); - -#ifdef CONFIG_NET_HW_FLOWCONTROL - if ((priv->fc_bit = netdev_register_fc(dev, amazon_xon)) == 0) { - printk("Hardware Flow Control register fails\n"); - } -#endif - - netif_start_queue(dev); - return OK; -} - -int switch_release(struct net_device *dev) -{ - int i; - struct switch_priv *priv = (struct switch_priv *) dev->priv; - struct dma_device_info *dma_dev = priv->dma_device; - - for (i = 0; i < dma_dev->num_tx_chan; i++) - dma_dev->tx_chan[i].control = 0; - for (i = 0; i < dma_dev->num_rx_chan; i++) - dma_dev->rx_chan[i].control = 0; - - dma_device_update(dma_dev); - -#ifdef CONFIG_NET_HW_FLOWCONTROL - if (priv->fc_bit) { - netdev_unregister_fc(priv->fc_bit); - } -#endif - netif_stop_queue(dev); - - return OK; -} - - -void switch_rx(struct net_device *dev, int len, struct sk_buff *skb) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; -#ifdef CONFIG_NET_HW_FLOWCONTROL - int mit_sel = 0; -#endif - skb->dev = dev; - skb->protocol = eth_type_trans(skb, dev); - -#ifdef CONFIG_NET_HW_FLOWCONTROL - mit_sel = netif_rx(skb); - switch (mit_sel) { - case NET_RX_SUCCESS: - case NET_RX_CN_LOW: - case NET_RX_CN_MOD: - break; - case NET_RX_CN_HIGH: - break; - case NET_RX_DROP: - if ((priv->fc_bit) - && (!test_and_set_bit(priv->fc_bit, &netdev_fc_xoff))) { - close_rx_dma(dev); - } - break; - } -#else - netif_rx(skb); -#endif - priv->stats.rx_packets++; - priv->stats.rx_bytes += len; - return; -} - -int asmlinkage switch_hw_tx(char *buf, int len, struct net_device *dev) -{ - struct switch_priv *priv = dev->priv; - struct dma_device_info *dma_dev = priv->dma_device; - - dma_dev->current_tx_chan = 0; - return dma_device_write(dma_dev, buf, len, priv->skb); -} - -int asmlinkage switch_tx(struct sk_buff *skb, struct net_device *dev) -{ - int len; - char *data; - struct switch_priv *priv = (struct switch_priv *) dev->priv; - - len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; - data = skb->data; - priv->skb = skb; - dev->trans_start = jiffies; - - if (switch_hw_tx(data, len, dev) != len) { - dev_kfree_skb_any(skb); - return OK; - } - - priv->stats.tx_packets++; - priv->stats.tx_bytes += len; - return OK; -} - -void switch_tx_timeout(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; - priv->stats.tx_errors++; - netif_wake_queue(dev); - return; -} - -void negotiate(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; - unsigned short data = get_mdio_reg(priv->mdio_phy_addr, MDIO_ADVERTISMENT_REG); - - data &= ~(MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD); - - switch (priv->current_speed_selection) { - case 10: - if (priv->current_duplex == full) - data |= MDIO_ADVERT_10_FD; - else if (priv->current_duplex == half) - data |= MDIO_ADVERT_10_HD; - else - data |= MDIO_ADVERT_10_HD | MDIO_ADVERT_10_FD; - break; - - case 100: - if (priv->current_duplex == full) - data |= MDIO_ADVERT_100_FD; - else if (priv->current_duplex == half) - data |= MDIO_ADVERT_100_HD; - else - data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD; - break; - - case 0: /* Auto */ - if (priv->current_duplex == full) - data |= MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD; - else if (priv->current_duplex == half) - data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_10_HD; - else - data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD; - break; - - default: /* assume autoneg speed and duplex */ - data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD; - } - - set_mdio_reg(priv->mdio_phy_addr, MDIO_ADVERTISMENT_REG, data); - - /* Renegotiate with link partner */ - - data = get_mdio_reg(priv->mdio_phy_addr, MDIO_BASE_CONTROL_REG); - data |= MDIO_BC_NEGOTIATE; - - set_mdio_reg(priv->mdio_phy_addr, MDIO_BASE_CONTROL_REG, data); - -} - - -void set_duplex(struct net_device *dev, enum duplex new_duplex) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; - if (new_duplex != priv->current_duplex) { - priv->current_duplex = new_duplex; - negotiate(dev); - } -} - -void set_speed(struct net_device *dev, unsigned long speed) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; - priv->current_speed_selection = speed; - negotiate(dev); -} - -static int switch_ethtool_ioctl(struct net_device *dev, struct ifreq *ifr) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; - struct ethtool_cmd ecmd; - - if (copy_from_user(&ecmd, ifr->ifr_data, sizeof(ecmd))) - return -EFAULT; - - switch (ecmd.cmd) { - case ETHTOOL_GSET: - memset((void *) &ecmd, 0, sizeof(ecmd)); - ecmd.supported = SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full; - ecmd.port = PORT_TP; - ecmd.transceiver = XCVR_EXTERNAL; - ecmd.phy_address = priv->mdio_phy_addr; - - ecmd.speed = priv->current_speed; - - ecmd.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; - - ecmd.advertising = ADVERTISED_TP; - if (priv->current_duplex == autoneg && priv->current_speed_selection == 0) - ecmd.advertising |= ADVERTISED_Autoneg; - else { - ecmd.advertising |= ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | - ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; - if (priv->current_speed_selection == 10) - ecmd.advertising &= ~(ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full); - else if (priv->current_speed_selection == 100) - ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full); - if (priv->current_duplex == half) - ecmd.advertising &= ~(ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Full); - else if (priv->current_duplex == full) - ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_100baseT_Half); - } - ecmd.autoneg = AUTONEG_ENABLE; - if (copy_to_user(ifr->ifr_data, &ecmd, sizeof(ecmd))) - return -EFAULT; - break; - - case ETHTOOL_SSET: - if (!capable(CAP_NET_ADMIN)) { - return -EPERM; - } - if (ecmd.autoneg == AUTONEG_ENABLE) { - set_duplex(dev, autoneg); - set_speed(dev, 0); - } else { - set_duplex(dev, ecmd.duplex == DUPLEX_HALF ? half : full); - set_speed(dev, ecmd.speed == SPEED_10 ? 10 : 100); - } - break; - - case ETHTOOL_GDRVINFO: - { - struct ethtool_drvinfo info; - memset((void *) &info, 0, sizeof(info)); - strncpy(info.driver, "AMAZONE", sizeof(info.driver) - 1); - strncpy(info.fw_version, "N/A", sizeof(info.fw_version) - 1); - strncpy(info.bus_info, "N/A", sizeof(info.bus_info) - 1); - info.regdump_len = 0; - info.eedump_len = 0; - info.testinfo_len = 0; - if (copy_to_user(ifr->ifr_data, &info, sizeof(info))) - return -EFAULT; - } - break; - case ETHTOOL_NWAY_RST: - if (priv->current_duplex == autoneg && priv->current_speed_selection == 0) - negotiate(dev); - break; - default: - return -EOPNOTSUPP; - break; - } - return 0; -} - - - -int mac_table_tools_ioctl(struct net_device *dev, struct mac_table_req *req) -{ - int cmd; - int i; - cmd = req->cmd; - switch (cmd) { - case RESET_MAC_TABLE: - for (i = 0; i < 32; i++) { - write_mac_table_entry(i, 0); - } - break; - case READ_MAC_ENTRY: - req->entry_value = read_mac_table_entry(req->index); - break; - case WRITE_MAC_ENTRY: - write_mac_table_entry(req->index, req->entry_value); - break; - case ADD_MAC_ENTRY: - add_mac_table_entry(req->entry_value); - break; - default: - return -EINVAL; - } - - return 0; -} - - -/* - the ioctl for the switch driver is developed in the conventional way - the control type falls into some basic categories, among them, the - SIOCETHTOOL is the traditional eth interface. VLAN_TOOLS and - MAC_TABLE_TOOLS are designed specifically for amazon chip. User - should be aware of the data structures used in these interfaces. -*/ -int switch_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -{ - struct data_req *switch_data_req = (struct data_req *) ifr->ifr_data; - struct mac_table_req *switch_mac_table_req; - switch (cmd) { - case SIOCETHTOOL: - switch_ethtool_ioctl(dev, ifr); - break; - case SIOCGMIIPHY: /* Get PHY address */ - break; - case SIOCGMIIREG: /* Read MII register */ - break; - case SIOCSMIIREG: /* Write MII register */ - break; - case SET_ETH_SPEED_10: /* 10 Mbps */ - break; - case SET_ETH_SPEED_100: /* 100 Mbps */ - break; - case SET_ETH_SPEED_AUTO: /* Auto negotiate speed */ - break; - case SET_ETH_DUPLEX_HALF: /* Half duplex. */ - break; - case SET_ETH_DUPLEX_FULL: /* Full duplex. */ - break; - case SET_ETH_DUPLEX_AUTO: /* Autonegotiate duplex */ - break; - case SET_ETH_REG: - AMAZON_SW_REG32(switch_data_req->index) = switch_data_req->value; - break; - case MAC_TABLE_TOOLS: - switch_mac_table_req = (struct mac_table_req *) ifr->ifr_data; - mac_table_tools_ioctl(dev, switch_mac_table_req); - break; - default: - return -EINVAL; - } - - return 0; -} - -struct net_device_stats *switch_stats(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) dev->priv; - return &priv->stats; -} - -int switch_change_mtu(struct net_device *dev, int new_mtu) -{ - if (new_mtu >= 1516) - new_mtu = 1516; - dev->mtu = new_mtu; - return 0; -} - -int switch_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev) -{ - u8 *buf = NULL; - int len = 0; - struct sk_buff *skb = NULL; - - len = dma_device_read(dma_dev, &buf, (void **) &skb); - - if (len >= 0x600) { - printk("packet too large %d\n", len); - goto switch_hw_receive_err_exit; - } - - /* remove CRC */ - len -= 4; - if (skb == NULL) { - printk("cannot restore pointer\n"); - goto switch_hw_receive_err_exit; - } - if (len > (skb->end - skb->tail)) { - printk("BUG, len:%d end:%p tail:%p\n", (len + 4), skb->end, skb->tail); - goto switch_hw_receive_err_exit; - } - skb_put(skb, len); - skb->dev = dev; - switch_rx(dev, len, skb); - return OK; - - switch_hw_receive_err_exit: - if (skb) - dev_kfree_skb_any(skb); - return -EIO; -} - -int dma_intr_handler(struct dma_device_info *dma_dev, int status) -{ - struct net_device *dev; - - dev = switch_devs + (u32) dma_dev->priv; - switch (status) { - case RCV_INT: - switch_hw_receive(dev, dma_dev); - break; - case TX_BUF_FULL_INT: - netif_stop_queue(dev); - break; - case TRANSMIT_CPT_INT: - netif_wake_queue(dev); - break; - } - return OK; -} - -/* reserve 2 bytes in front of data pointer*/ -u8 *dma_buffer_alloc(int len, int *byte_offset, void **opt) -{ - u8 *buffer = NULL; - struct sk_buff *skb = NULL; - skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE); - if (skb == NULL) { - return NULL; - } - buffer = (u8 *) (skb->data); - skb_reserve(skb, 2); - *(int *) opt = (int) skb; - *byte_offset = 2; - return buffer; -} - -int dma_buffer_free(u8 * dataptr, void *opt) -{ - struct sk_buff *skb = NULL; - if (opt == NULL) { - kfree(dataptr); - } else { - skb = (struct sk_buff *) opt; - dev_kfree_skb_any(skb); - } - return OK; -} - -int init_dma_device(_dma_device_info * dma_dev) -{ - int i; - int num_tx_chan, num_rx_chan; - if (strcmp(dma_dev->device_name, "switch1") == 0) { - num_tx_chan = 1; - num_rx_chan = 2; - dma_dev->priv = (void *) 0; - } else { - num_tx_chan = 1; - num_rx_chan = 2; - dma_dev->priv = (void *) 1; - } - - dma_dev->weight = 1; - dma_dev->num_tx_chan = num_tx_chan; - dma_dev->num_rx_chan = num_rx_chan; - dma_dev->ack = 1; - dma_dev->tx_burst_len = 4; - dma_dev->rx_burst_len = 4; - for (i = 0; i < dma_dev->num_tx_chan; i++) { - dma_dev->tx_chan[i].weight = QOS_DEFAULT_WGT; - dma_dev->tx_chan[i].desc_num = 10; - dma_dev->tx_chan[i].packet_size = 0; - dma_dev->tx_chan[i].control = 0; - } - for (i = 0; i < num_rx_chan; i++) { - dma_dev->rx_chan[i].weight = QOS_DEFAULT_WGT; - dma_dev->rx_chan[i].desc_num = 10; - dma_dev->rx_chan[i].packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE; - dma_dev->rx_chan[i].control = 0; - } - dma_dev->intr_handler = dma_intr_handler; - dma_dev->buffer_alloc = dma_buffer_alloc; - dma_dev->buffer_free = dma_buffer_free; - return 0; -} - -int switch_set_mac_address(struct net_device *dev, void *p) -{ - struct sockaddr *addr = p; - memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); - return OK; -} - - -int switch_init(struct net_device *dev) -{ - u64 retval = 0; - int i; - int result; - struct switch_priv *priv; - ether_setup(dev); /* assign some of the fields */ - printk("%s up using ", dev->name); - dev->open = switch_open; - dev->stop = switch_release; - dev->hard_start_xmit = switch_tx; - dev->do_ioctl = switch_ioctl; - dev->get_stats = switch_stats; - dev->change_mtu = switch_change_mtu; - dev->set_mac_address = switch_set_mac_address; - dev->tx_timeout = switch_tx_timeout; - dev->watchdog_timeo = timeout; - - SET_MODULE_OWNER(dev); - - dev->priv = kmalloc(sizeof(struct switch_priv), GFP_KERNEL); - if (dev->priv == NULL) - return -ENOMEM; - memset(dev->priv, 0, sizeof(struct switch_priv)); - priv = dev->priv; - priv->dma_device = (struct dma_device_info *) kmalloc(sizeof(struct dma_device_info), GFP_KERNEL); - if ((dev - switch_devs) == 0) { - sprintf(priv->dma_device->device_name, "switch1"); - } else if ((dev - switch_devs) == 1) { - sprintf(priv->dma_device->device_name, "switch2"); - } - printk("\"%s\"\n", priv->dma_device->device_name); - init_dma_device(priv->dma_device); - result = dma_device_register(priv->dma_device); - - /* read the mac address from the mac table and put them into the mac table. */ - for (i = 0; i < 6; i++) { - retval += my_ethaddr[i]; - } - /* ethaddr not set in u-boot ? */ - if (retval == 0) { - dev->dev_addr[0] = 0x00; - dev->dev_addr[1] = 0x20; - dev->dev_addr[2] = 0xda; - dev->dev_addr[3] = 0x86; - dev->dev_addr[4] = 0x23; - dev->dev_addr[5] = 0x74 + (unsigned char) (dev - switch_devs); - } else { - for (i = 0; i < 6; i++) { - dev->dev_addr[i] = my_ethaddr[i]; - } - dev->dev_addr[5] += +(unsigned char) (dev - switch_devs); - } - return OK; -} - -int switch_init_module(void) -{ - int i = 0, result, device_present = 0; - - for (i = 0; i < AMAZON_SW_INT_NO; i++) { - sprintf(switch_devs[i].name, "eth%d", i); - - if ((result = register_netdev(switch_devs + i))) - printk("error %i registering device \"%s\"\n", result, switch_devs[i].name); - else - device_present++; - } - amazon_sw_chip_init(); - return device_present ? 0 : -ENODEV; -} - -void switch_cleanup(void) -{ - int i; - struct switch_priv *priv; - for (i = 0; i < AMAZON_SW_INT_NO; i++) { - priv = switch_devs[i].priv; - if (priv->dma_device) { - dma_device_unregister(priv->dma_device); - kfree(priv->dma_device); - } - kfree(switch_devs[i].priv); - unregister_netdev(switch_devs + i); - } - return; -} - -module_init(switch_init_module); -module_exit(switch_cleanup); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Wu Qi Ming"); diff --git a/target/linux/amazon/files/drivers/serial/amazon_asc.c b/target/linux/amazon/files/drivers/serial/amazon_asc.c deleted file mode 100644 index 7c17cb0f4a..0000000000 --- a/target/linux/amazon/files/drivers/serial/amazon_asc.c +++ /dev/null @@ -1,685 +0,0 @@ -/* - * Driver for AMAZONASC serial ports - * - * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. - * Based on drivers/serial/serial_s3c2400.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright (C) 2004 Infineon IFAP DC COM CPE - * Copyright (C) 2007 Felix Fietkau - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define PORT_AMAZONASC 111 - -#include - -#define UART_NR 1 - -#define UART_DUMMY_UER_RX 1 - -#define SERIAL_AMAZONASC_MAJOR TTY_MAJOR -#define CALLOUT_AMAZONASC_MAJOR TTYAUX_MAJOR -#define SERIAL_AMAZONASC_MINOR 64 -#define SERIAL_AMAZONASC_NR UART_NR - -static void amazonasc_tx_chars(struct uart_port *port); -extern void prom_printf(const char * fmt, ...); -static struct uart_port amazonasc_ports[UART_NR]; -static struct uart_driver amazonasc_reg; -static unsigned int uartclk = 0; -extern unsigned int amazon_get_fpi_hz(void); - -static void amazonasc_stop_tx(struct uart_port *port) -{ - /* fifo underrun shuts up after firing once */ - return; -} - -static void amazonasc_start_tx(struct uart_port *port) -{ - unsigned long flags; - - local_irq_save(flags); - amazonasc_tx_chars(port); - local_irq_restore(flags); - - return; -} - -static void amazonasc_stop_rx(struct uart_port *port) -{ - /* clear the RX enable bit */ - amazon_writel(ASCWHBCON_CLRREN, AMAZON_ASC_WHBCON); -} - -static void amazonasc_enable_ms(struct uart_port *port) -{ - /* no modem signals */ - return; -} - -static void -amazonasc_rx_chars(struct uart_port *port) -{ - struct tty_struct *tty = port->info->tty; - unsigned int ch = 0, rsr = 0, fifocnt; - - fifocnt = amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; - while (fifocnt--) - { - u8 flag = TTY_NORMAL; - ch = amazon_readl(AMAZON_ASC_RBUF); - rsr = (amazon_readl(AMAZON_ASC_CON) & ASCCON_ANY) | UART_DUMMY_UER_RX; - tty_flip_buffer_push(tty); - port->icount.rx++; - - /* - * Note that the error handling code is - * out of the main execution path - */ - if (rsr & ASCCON_ANY) { - if (rsr & ASCCON_PE) { - port->icount.parity++; - amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE, ASCWHBCON_CLRPE); - } else if (rsr & ASCCON_FE) { - port->icount.frame++; - amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE, ASCWHBCON_CLRFE); - } - if (rsr & ASCCON_OE) { - port->icount.overrun++; - amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE, ASCWHBCON_CLROE); - } - - rsr &= port->read_status_mask; - - if (rsr & ASCCON_PE) - flag = TTY_PARITY; - else if (rsr & ASCCON_FE) - flag = TTY_FRAME; - } - - if ((rsr & port->ignore_status_mask) == 0) - tty_insert_flip_char(tty, ch, flag); - - if (rsr & ASCCON_OE) - /* - * Overrun is special, since it's reported - * immediately, and doesn't affect the current - * character - */ - tty_insert_flip_char(tty, 0, TTY_OVERRUN); - } - if (ch != 0) - tty_flip_buffer_push(tty); - - return; -} - - -static void amazonasc_tx_chars(struct uart_port *port) -{ - struct circ_buf *xmit = &port->info->xmit; - - if (uart_tx_stopped(port)) { - amazonasc_stop_tx(port); - return; - } - - while (((amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) - >> ASCFSTAT_TXFFLOFF) != AMAZONASC_TXFIFO_FULL) - { - if (port->x_char) { - amazon_writel(port->x_char, AMAZON_ASC_TBUF); - port->icount.tx++; - port->x_char = 0; - continue; - } - - if (uart_circ_empty(xmit)) - break; - - amazon_writel(xmit->buf[xmit->tail], AMAZON_ASC_TBUF); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); - port->icount.tx++; - } - - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(port); -} - -static irqreturn_t amazonasc_tx_int(int irq, void *port) -{ - amazon_writel(ASC_IRNCR_TIR, AMAZON_ASC_IRNCR1); - amazonasc_start_tx(port); - - /* clear any pending interrupts */ - amazon_writel_masked(AMAZON_ASC_WHBCON, - (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE), - (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE)); - - return IRQ_HANDLED; -} - -static irqreturn_t amazonasc_er_int(int irq, void *port) -{ - /* clear any pending interrupts */ - amazon_writel_masked(AMAZON_ASC_WHBCON, - (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE), - (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE)); - - return IRQ_HANDLED; -} - -static irqreturn_t amazonasc_rx_int(int irq, void *port) -{ - amazon_writel(ASC_IRNCR_RIR, AMAZON_ASC_IRNCR1); - amazonasc_rx_chars((struct uart_port *) port); - return IRQ_HANDLED; -} - -static u_int amazonasc_tx_empty(struct uart_port *port) -{ - int status; - - /* - * FSTAT tells exactly how many bytes are in the FIFO. - * The question is whether we really need to wait for all - * 16 bytes to be transmitted before reporting that the - * transmitter is empty. - */ - status = amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; - return status ? 0 : TIOCSER_TEMT; -} - -static u_int amazonasc_get_mctrl(struct uart_port *port) -{ - /* no modem control signals - the readme says to pretend all are set */ - return TIOCM_CTS|TIOCM_CAR|TIOCM_DSR; -} - -static void amazonasc_set_mctrl(struct uart_port *port, u_int mctrl) -{ - /* no modem control - just return */ - return; -} - -static void amazonasc_break_ctl(struct uart_port *port, int break_state) -{ - /* no way to send a break */ - return; -} - -static int amazonasc_startup(struct uart_port *port) -{ - unsigned int con = 0; - unsigned long flags; - int retval; - - /* this assumes: CON.BRS = CON.FDE = 0 */ - if (uartclk == 0) - uartclk = amazon_get_fpi_hz(); - - amazonasc_ports[0].uartclk = uartclk; - - local_irq_save(flags); - - /* this setup was probably already done in u-boot */ - /* ASC and GPIO Port 1 bits 3 and 4 share the same pins - * P1.3 (RX) in, Alternate 10 - * P1.4 (TX) in, Alternate 10 - */ - amazon_writel_masked(AMAZON_GPIO_P1_DIR, 0x18, 0x10); //P1.4 output, P1.3 input - amazon_writel_masked(AMAZON_GPIO_P1_ALTSEL0, 0x18, 0x18); //ALTSETL0 11 - amazon_writel_masked(AMAZON_GPIO_P1_ALTSEL1, 0x18, 0); //ALTSETL1 00 - amazon_writel_masked(AMAZON_GPIO_P1_OD, 0x18, 0x10); - - /* set up the CLC */ - amazon_writel_masked(AMAZON_ASC_CLC, AMAZON_ASC_CLC_DISS, 0); - amazon_writel_masked(AMAZON_ASC_CLC, ASCCLC_RMCMASK, 1 << ASCCLC_RMCOFFSET); - - /* asynchronous mode */ - con = ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_OEN | ASCCON_PEN; - - /* choose the line - there's only one */ - amazon_writel(0, AMAZON_ASC_PISEL); - amazon_writel(((AMAZONASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, - AMAZON_ASC_TXFCON); - amazon_writel(((AMAZONASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, - AMAZON_ASC_RXFCON); - wmb(); - - amazon_writel_masked(AMAZON_ASC_CON, con, con); - - retval = request_irq(AMAZONASC_RIR, amazonasc_rx_int, 0, "asc_rx", port); - if (retval){ - printk("failed to request amazonasc_rx_int\n"); - return retval; - } - retval = request_irq(AMAZONASC_TIR, amazonasc_tx_int, 0, "asc_tx", port); - if (retval){ - printk("failed to request amazonasc_tx_int\n"); - goto err1; - } - - retval = request_irq(AMAZONASC_EIR, amazonasc_er_int, 0, "asc_er", port); - if (retval){ - printk("failed to request amazonasc_er_int\n"); - goto err2; - } - - local_irq_restore(flags); - return 0; - -err2: - free_irq(AMAZONASC_TIR, port); - -err1: - free_irq(AMAZONASC_RIR, port); - local_irq_restore(flags); - return retval; -} - -static void amazonasc_shutdown(struct uart_port *port) -{ - free_irq(AMAZONASC_RIR, port); - free_irq(AMAZONASC_TIR, port); - free_irq(AMAZONASC_EIR, port); - /* - * disable the baudrate generator to disable the ASC - */ - amazon_writel(0, AMAZON_ASC_CON); - - /* flush and then disable the fifos */ - amazon_writel_masked(AMAZON_ASC_RXFCON, ASCRXFCON_RXFFLU, ASCRXFCON_RXFFLU); - amazon_writel_masked(AMAZON_ASC_RXFCON, ASCRXFCON_RXFEN, 0); - amazon_writel_masked(AMAZON_ASC_TXFCON, ASCTXFCON_TXFFLU, ASCTXFCON_TXFFLU); - amazon_writel_masked(AMAZON_ASC_TXFCON, ASCTXFCON_TXFEN, 0); -} - -static void amazonasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old) -{ - unsigned int cflag; - unsigned int iflag; - unsigned int baud, quot; - unsigned int con = 0; - unsigned long flags; - - cflag = new->c_cflag; - iflag = new->c_iflag; - - /* byte size and parity */ - switch (cflag & CSIZE) { - /* 7 bits are always with parity */ - case CS7: con = ASCCON_M_7ASYNCPAR; break; - /* the ASC only suports 7 and 8 bits */ - case CS5: - case CS6: - default: - if (cflag & PARENB) - con = ASCCON_M_8ASYNCPAR; - else - con = ASCCON_M_8ASYNC; - break; - } - if (cflag & CSTOPB) - con |= ASCCON_STP; - if (cflag & PARENB) { - if (!(cflag & PARODD)) - con &= ~ASCCON_ODD; - else - con |= ASCCON_ODD; - } - - port->read_status_mask = ASCCON_OE; - if (iflag & INPCK) - port->read_status_mask |= ASCCON_FE | ASCCON_PE; - - port->ignore_status_mask = 0; - if (iflag & IGNPAR) - port->ignore_status_mask |= ASCCON_FE | ASCCON_PE; - - if (iflag & IGNBRK) { - /* - * If we're ignoring parity and break indicators, - * ignore overruns too (for real raw support). - */ - if (iflag & IGNPAR) - port->ignore_status_mask |= ASCCON_OE; - } - - /* - * Ignore all characters if CREAD is not set. - */ - if ((cflag & CREAD) == 0) - port->ignore_status_mask |= UART_DUMMY_UER_RX; - - /* set error signals - framing, parity and overrun */ - con |= ASCCON_FEN; - con |= ASCCON_OEN; - con |= ASCCON_PEN; - /* enable the receiver */ - con |= ASCCON_REN; - - /* block the IRQs */ - local_irq_save(flags); - - /* set up CON */ - amazon_writel(con, AMAZON_ASC_CON); - - /* Set baud rate - take a divider of 2 into account */ - baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16); - quot = uart_get_divisor(port, baud); - quot = quot/2 - 1; - - /* the next 3 probably already happened when we set CON above */ - /* disable the baudrate generator */ - amazon_writel_masked(AMAZON_ASC_CON, ASCCON_R, 0); - /* make sure the fractional divider is off */ - amazon_writel_masked(AMAZON_ASC_CON, ASCCON_FDE, 0); - /* set up to use divisor of 2 */ - amazon_writel_masked(AMAZON_ASC_CON, ASCCON_BRS, 0); - /* now we can write the new baudrate into the register */ - amazon_writel(quot, AMAZON_ASC_BTR); - /* turn the baudrate generator back on */ - amazon_writel_masked(AMAZON_ASC_CON, ASCCON_R, ASCCON_R); - - local_irq_restore(flags); -} - -static const char *amazonasc_type(struct uart_port *port) -{ - return port->type == PORT_AMAZONASC ? "AMAZONASC" : NULL; -} - -/* - * Release the memory region(s) being used by 'port' - */ -static void amazonasc_release_port(struct uart_port *port) -{ - return; -} - -/* - * Request the memory region(s) being used by 'port' - */ -static int amazonasc_request_port(struct uart_port *port) -{ - return 0; -} - -/* - * Configure/autoconfigure the port. - */ -static void amazonasc_config_port(struct uart_port *port, int flags) -{ - if (flags & UART_CONFIG_TYPE) { - port->type = PORT_AMAZONASC; - amazonasc_request_port(port); - } -} - -/* - * verify the new serial_struct (for TIOCSSERIAL). - */ -static int amazonasc_verify_port(struct uart_port *port, struct serial_struct *ser) -{ - int ret = 0; - if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMAZONASC) - ret = -EINVAL; - if (ser->irq < 0 || ser->irq >= NR_IRQS) - ret = -EINVAL; - if (ser->baud_base < 9600) - ret = -EINVAL; - return ret; -} - -static struct uart_ops amazonasc_pops = { - .tx_empty = amazonasc_tx_empty, - .set_mctrl = amazonasc_set_mctrl, - .get_mctrl = amazonasc_get_mctrl, - .stop_tx = amazonasc_stop_tx, - .start_tx = amazonasc_start_tx, - .stop_rx = amazonasc_stop_rx, - .enable_ms = amazonasc_enable_ms, - .break_ctl = amazonasc_break_ctl, - .startup = amazonasc_startup, - .shutdown = amazonasc_shutdown, - .set_termios = amazonasc_set_termios, - .type = amazonasc_type, - .release_port = amazonasc_release_port, - .request_port = amazonasc_request_port, - .config_port = amazonasc_config_port, - .verify_port = amazonasc_verify_port, -}; - -static struct uart_port amazonasc_ports[UART_NR] = { - { - membase: (void *)AMAZON_ASC, - mapbase: AMAZON_ASC, - iotype: SERIAL_IO_MEM, - irq: AMAZONASC_RIR, /* RIR */ - uartclk: 0, /* filled in dynamically */ - fifosize: 16, - unused: { AMAZONASC_TIR, AMAZONASC_EIR}, /* xmit/error/xmit-buffer-empty IRQ */ - type: PORT_AMAZONASC, - ops: &amazonasc_pops, - flags: ASYNC_BOOT_AUTOCONF, - }, -}; - -static void amazonasc_console_write(struct console *co, const char *s, u_int count) -{ - int i, fifocnt; - unsigned long flags; - local_irq_save(flags); - for (i = 0; i < count;) - { - /* wait until the FIFO is not full */ - do - { - fifocnt = (amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) - >> ASCFSTAT_TXFFLOFF; - } while (fifocnt == AMAZONASC_TXFIFO_FULL); - if (s[i] == '\0') - { - break; - } - if (s[i] == '\n') - { - amazon_writel('\r', AMAZON_ASC_TBUF); - do - { - fifocnt = (amazon_readl(AMAZON_ASC_FSTAT) & - ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF; - } while (fifocnt == AMAZONASC_TXFIFO_FULL); - } - amazon_writel(s[i], AMAZON_ASC_TBUF); - i++; - } - - local_irq_restore(flags); -} - -static void __init -amazonasc_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits) -{ - u_int lcr_h; - - lcr_h = amazon_readl(AMAZON_ASC_CON); - /* do this only if the ASC is turned on */ - if (lcr_h & ASCCON_R) { - u_int quot, div, fdiv, frac; - - *parity = 'n'; - if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNCPAR || - (lcr_h & ASCCON_MODEMASK) == ASCCON_M_8ASYNCPAR) { - if (lcr_h & ASCCON_ODD) - *parity = 'o'; - else - *parity = 'e'; - } - - if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNCPAR) - *bits = 7; - else - *bits = 8; - - quot = amazon_readl(AMAZON_ASC_BTR) + 1; - - /* this gets hairy if the fractional divider is used */ - if (lcr_h & ASCCON_FDE) - { - div = 1; - fdiv = amazon_readl(AMAZON_ASC_FDV); - if (fdiv == 0) - fdiv = 512; - frac = 512; - } - else - { - div = lcr_h & ASCCON_BRS ? 3 : 2; - fdiv = frac = 1; - } - /* - * This doesn't work exactly because we use integer - * math to calculate baud which results in rounding - * errors when we try to go from quot -> baud !! - * Try to make this work for both the fractional divider - * and the simple divider. Also try to avoid rounding - * errors using integer math. - */ - - *baud = frac * (port->uartclk / (div * 512 * 16 * quot)); - if (*baud > 1100 && *baud < 2400) - *baud = 1200; - if (*baud > 2300 && *baud < 4800) - *baud = 2400; - if (*baud > 4700 && *baud < 9600) - *baud = 4800; - if (*baud > 9500 && *baud < 19200) - *baud = 9600; - if (*baud > 19000 && *baud < 38400) - *baud = 19200; - if (*baud > 38400 && *baud < 57600) - *baud = 38400; - if (*baud > 57600 && *baud < 115200) - *baud = 57600; - if (*baud > 115200 && *baud < 230400) - *baud = 115200; - } -} - -static int __init amazonasc_console_setup(struct console *co, char *options) -{ - struct uart_port *port; - int baud = 115200; - int bits = 8; - int parity = 'n'; - int flow = 'n'; - - /* this assumes: CON.BRS = CON.FDE = 0 */ - if (uartclk == 0) - uartclk = amazon_get_fpi_hz(); - co->index = 0; - port = &amazonasc_ports[0]; - amazonasc_ports[0].uartclk = uartclk; - amazonasc_ports[0].type = PORT_AMAZONASC; - - if (options){ - uart_parse_options(options, &baud, &parity, &bits, &flow); - } - - return uart_set_options(port, co, baud, parity, bits, flow); -} - -static struct uart_driver amazonasc_reg; -static struct console amazonasc_console = { - name: "ttyS", - write: amazonasc_console_write, - device: uart_console_device, - setup: amazonasc_console_setup, - flags: CON_PRINTBUFFER, - index: -1, - data: &amazonasc_reg, -}; - -static int __init amazonasc_console_init(void) -{ - register_console(&amazonasc_console); - return 0; -} -console_initcall(amazonasc_console_init); - -static struct uart_driver amazonasc_reg = { - .owner = THIS_MODULE, - .driver_name = "serial", - .dev_name = "ttyS", - .major = TTY_MAJOR, - .minor = 64, - .nr = UART_NR, - .cons = &amazonasc_console, -}; - -static int __init amazonasc_init(void) -{ - unsigned char res; - uart_register_driver(&amazonasc_reg); - res = uart_add_one_port(&amazonasc_reg, &amazonasc_ports[0]); - return res; -} - -static void __exit amazonasc_exit(void) -{ - uart_unregister_driver(&amazonasc_reg); -} - -module_init(amazonasc_init); -module_exit(amazonasc_exit); - -MODULE_AUTHOR("Gary Jennejohn, Felix Fietkau, John Crispin"); -MODULE_DESCRIPTION("MIPS AMAZONASC serial port driver"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/amazon/files/include/asm-mips/amazon/adm6996.h b/target/linux/amazon/files/include/asm-mips/amazon/adm6996.h deleted file mode 100644 index 77cf4b131d..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/adm6996.h +++ /dev/null @@ -1,232 +0,0 @@ -/****************************************************************************** - Copyright (c) 2004, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. - ****************************************************************************** - Module : ifx_swdrv.h - Date : 2004-09-01 - Description : JoeLin - Remarks: - - *****************************************************************************/ - -#ifndef _ADM_6996_MODULE_H_ -#define _ADM_6996_MODULE_H_ - -#include - -#define ifx_printf(x) printk x - -/* command codes */ -#define ADM_SW_SMI_READ 0x02 -#define ADM_SW_SMI_WRITE 0x01 -#define ADM_SW_SMI_START 0x01 - -#define ADM_SW_EEPROM_WRITE 0x01 -#define ADM_SW_EEPROM_WRITE_ENABLE 0x03 -#define ADM_SW_EEPROM_WRITE_DISABLE 0x00 -#define EEPROM_TYPE 8 /* for 93C66 */ - -/* bit masks */ -#define ADM_SW_BIT_MASK_1 0x00000001 -#define ADM_SW_BIT_MASK_2 0x00000002 -#define ADM_SW_BIT_MASK_4 0x00000008 -#define ADM_SW_BIT_MASK_10 0x00000200 -#define ADM_SW_BIT_MASK_16 0x00008000 -#define ADM_SW_BIT_MASK_32 0x80000000 - -/* delay timers */ -#define ADM_SW_MDC_DOWN_DELAY 5 -#define ADM_SW_MDC_UP_DELAY 5 -#define ADM_SW_CS_DELAY 5 - -/* MDIO modes */ -#define ADM_SW_MDIO_OUTPUT 1 -#define ADM_SW_MDIO_INPUT 0 - -#define ADM_SW_MAX_PORT_NUM 5 -#define ADM_SW_MAX_VLAN_NUM 15 - -/* registers */ -#define ADM_SW_PORT0_CONF 0x1 -#define ADM_SW_PORT1_CONF 0x3 -#define ADM_SW_PORT2_CONF 0x5 -#define ADM_SW_PORT3_CONF 0x7 -#define ADM_SW_PORT4_CONF 0x8 -#define ADM_SW_PORT5_CONF 0x9 -#define ADM_SW_VLAN_MODE 0x11 -#define ADM_SW_MAC_LOCK 0x12 -#define ADM_SW_VLAN0_CONF 0x13 -#define ADM_SW_PORT0_PVID 0x28 -#define ADM_SW_PORT1_PVID 0x29 -#define ADM_SW_PORT2_PVID 0x2a -#define ADM_SW_PORT34_PVID 0x2b -#define ADM_SW_PORT5_PVID 0x2c -#define ADM_SW_PHY_RESET 0x2f -#define ADM_SW_MISC_CONF 0x30 -#define ADM_SW_BNDWDH_CTL0 0x31 -#define ADM_SW_BNDWDH_CTL1 0x32 -#define ADM_SW_BNDWDH_CTL_ENA 0x33 - -/* port modes */ -#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */ -#define ADM_SW_PORT_AN 0x2 /* auto negotiation */ -#define ADM_SW_PORT_100M 0x4 /* 100M */ -#define ADM_SW_PORT_FULL 0x8 /* full duplex */ -#define ADM_SW_PORT_TAG 0x10 /* output tag on */ -#define ADM_SW_PORT_DISABLE 0x20 /* disable port */ -#define ADM_SW_PORT_TOS 0x40 /* TOS first */ -#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */ -#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */ -#define ADM_SW_PORT_PVID_SHIFT 10 -#define ADM_SW_PORT_PVID_BITS 4 - -/* VLAN */ -#define ADM_SW_VLAN_PORT0 0x1 -#define ADM_SW_VLAN_PORT1 0x2 -#define ADM_SW_VLAN_PORT2 0x10 -#define ADM_SW_VLAN_PORT3 0x40 -#define ADM_SW_VLAN_PORT4 0x80 -#define ADM_SW_VLAN_PORT5 0x100 - - -/* GPIO 012 enabled, output mode */ -#define GPIO_ENABLEBITS 0x000700f8 - -/* - define AMAZON GPIO port to ADM6996 EEPROM interface - MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction - MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only - MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only - EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */ - -#define GPIO_MDIO 1 //P1.0 -#define GPIO_MDC 2 //P1.1 -#define GPIO_MDCS 4 //P1.2 - -//joelin #define GPIO_MDIO 0 -//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */ -//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */ - - -#define MDIO_INPUT 0x00000001 -#define MDIO_OUTPUT_EN 0x00010000 - - -/* type definitions */ -typedef unsigned char U8; -typedef unsigned short U16; -typedef unsigned int U32; - -typedef struct _REGRW_ -{ - unsigned int addr; - unsigned int value; - unsigned int mode; -}REGRW, *PREGRW; - -//joelin adm6996i -typedef struct _MACENTRY_ -{ - unsigned char mac_addr[6]; - unsigned long fid:4; - unsigned long portmap:6; - union { - unsigned long age_timer:9; - unsigned long info_ctrl:9; - } ctrl; - unsigned long occupy:1; - unsigned long info_type:1; - unsigned long bad:1; - unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error - - }MACENTRY, *PMACENTRY; -typedef struct _PROTOCOLFILTER_ -{ - int protocol_filter_num;//[0~7] - int ip_p; //Value Compared with Protocol in IP Heade[7:0] - char action:2;//Action for protocol Filter . -//00 = Protocol Portmap is Default Output Ports. -//01 = Protocol Portmap is 6'b0. -//10 = Protocol Portmap is the CPU port if the incoming port -//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port. - }PROTOCOLFILTER, *PPROTOCOLFILTER; - -//joelin adm6996i - -/* Santosh: for IGMP proxy/snooping */ - -//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac); -//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter); - - -/* IOCTL keys */ -#define KEY_IOCTL_ADM_REGRW 0x01 -#define KEY_IOCTL_ADM_SW_REGRW 0x02 -#define KEY_IOCTL_ADM_SW_PORTSTS 0x03 -#define KEY_IOCTL_ADM_SW_INIT 0x04 -//for adm6996i-start -#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05 -#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06 -#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07 -#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08 -#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09 -#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a -#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b - -//adm6996i #define KEY_IOCTL_MAX_KEY 0x05 -#define KEY_IOCTL_MAX_KEY 0x0c -//for adm6996i-end -/* IOCTL MAGIC */ -#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k') - -/* IOCTL parameters */ -#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW) -#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW) -#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL) -#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL) - - -//6996i-stat -#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY) -#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY) -#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY) -#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY) -#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER) -#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER) -#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER) - -//6996i-end - - -#define REG_READ 0x0 -#define REG_WRITE 0x1 - -/* undefine symbol */ -#define AMAZON_SW_REG(reg) *((volatile U32*)(reg)) -//#define GPIO0_INPUT_MASK 0 -//#define GPIO_conf0_REG 0x12345678 -//#define GPIO_SET_HI -//#define GPIO_SET_LOW - -#endif -/* _ADM_6996_MODULE_H_ */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon.h deleted file mode 100644 index d28bb418f1..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon.h +++ /dev/null @@ -1,1440 +0,0 @@ -#ifndef AMAZON_H -#define AMAZON_H -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - -#define amazon_readl(a) readl(((u32*)(a))) -#define amazon_writel(a,b) writel(a, ((u32*)(b))) -#define amazon_writel_masked(a,b,c) writel((readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a))) - -/* check ADSL link status */ -#define AMAZON_CHECK_LINK - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ - -#define AMAZON_WDT (KSEG1+0x10100900) -/***********************************************************************/ - -/***Reset Request Register***/ -#define AMAZON_RST_REQ ((volatile u32*)(AMAZON_WDT+ 0x0010)) -#define AMAZON_RST_REQ_PLL (1 << 31) -#define AMAZON_RST_REQ_PCI_CORE (1 << 13) -#define AMAZON_RST_REQ_TPE (1 << 12) -#define AMAZON_RST_REQ_AFE (1 << 11) -#define AMAZON_RST_REQ_DMA (1 << 9) -#define AMAZON_RST_REQ_SWITCH (1 << 8) -#define AMAZON_RST_REQ_DFE (1 << 7) -#define AMAZON_RST_REQ_PHY (1 << 5) -#define AMAZON_RST_REQ_PCI (1 << 4) -#define AMAZON_RST_REQ_FPI (1 << 2) -#define AMAZON_RST_REQ_CPU (1 << 1) -#define AMAZON_RST_REQ_HRST (1 << 0) -#define AMAZON_RST_ALL (AMAZON_RST_REQ_PLL \ - |AMAZON_RST_REQ_PCI_CORE \ - |AMAZON_RST_REQ_TPE \ - |AMAZON_RST_REQ_AFE \ - |AMAZON_RST_REQ_DMA \ - |AMAZON_RST_REQ_SWITCH \ - |AMAZON_RST_REQ_DFE \ - |AMAZON_RST_REQ_PHY \ - |AMAZON_RST_REQ_PCI \ - |AMAZON_RST_REQ_FPI \ - |AMAZON_RST_REQ_CPU \ - |AMAZON_RST_REQ_HRST) - -/***Reset Status Register Power On***/ -#define AMAZON_RST_SR ((volatile u32*)(AMAZON_WDT+ 0x0014)) - -/***Watchdog Timer Control Register 0***/ -#define AMAZON_WDT_CON0 ((volatile u32*)(AMAZON_WDT+ 0x0020)) - -/***Watchdog Timer Control Register 1***/ -#define AMAZON_WDT_CON1 ((volatile u32*)(AMAZON_WDT+ 0x0024)) -#define AMAZON_WDT_CON1_WDTDR (1 << 3) -#define AMAZON_WDT_CON1_WDTIR (1 << 2) - -/***Watchdog Timer Status Register***/ -#define AMAZON_WDT_SR ((volatile u32*)(AMAZON_WDT+ 0x0028)) -#define AMAZON_WDT_SR_WDTTIM(value) (((( 1 << 16) - 1) & (value)) << 16) -#define AMAZON_WDT_SR_WDTPR (1 << 5) -#define AMAZON_WDT_SR_WDTTO (1 << 4) -#define AMAZON_WDT_SR_WDTDS (1 << 3) -#define AMAZON_WDT_SR_WDTIS (1 << 2) -#define AMAZON_WDT_SR_WDTOE (1 << 1) -#define AMAZON_WDT_SR_WDTAE (1 << 0) - -/***NMI Status Register***/ -#define AMAZON_WDT_NMISR ((volatile u32*)(AMAZON_WDT+ 0x002C)) -#define AMAZON_WDT_NMISR_NMIWDT (1 << 2) -#define AMAZON_WDT_NMISR_NMIPLL (1 << 1) -#define AMAZON_WDT_NMISR_NMIEXT (1 << 0) - -#define AMAZON_WDT_RST_MON ((volatile u32*)(AMAZON_WDT+ 0x0030)) - -/***********************************************************************/ -/* Module : MCD register address and bits */ -/***********************************************************************/ -#define AMAZON_MCD (KSEG1+0x1F106000) - -/***Manufacturer Identification Register***/ -#define AMAZON_MCD_MANID ((volatile u32*)(AMAZON_MCD+ 0x0024)) -#define AMAZON_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ -#define AMAZON_MCD_CHIPID ((volatile u32*)(AMAZON_MCD+ 0x0028)) -#define AMAZON_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define AMAZON_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define AMAZON_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define AMAZON_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define AMAZON_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -#define AMAZON_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) - -#define AMAZON_CHIPID_STANDARD 0x00EB -#define AMAZON_CHIPID_YANGTSE 0x00ED - -/***Redesign Tracing Identification Register***/ -#define AMAZON_MCD_RTID ((volatile u32*)(AMAZON_MCD+ 0x002C)) -#define AMAZON_MCD_RTID_LC (1 << 15) -#define AMAZON_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define AMAZON_CGU (KSEG1+0x1F103000) -/***********************************************************************/ - -/***CGU Clock Divider Select Register***/ -#define AMAZON_CGU_DIV (AMAZON_CGU + 0x0000) -/***CGU PLL0 Status Register***/ -#define AMAZON_CGU_PLL0SR (AMAZON_CGU + 0x0004) -/***CGU PLL1 Status Register***/ -#define AMAZON_CGU_PLL1SR (AMAZON_CGU + 0x0008) -/***CGU Interface Clock Control Register***/ -#define AMAZON_CGU_IFCCR (AMAZON_CGU + 0x000c) -/***CGU Oscillator Control Register***/ -#define AMAZON_CGU_OSCCR (AMAZON_CGU + 0x0010) -/***CGU Memory Clock Delay Register***/ -#define AMAZON_CGU_MCDEL (AMAZON_CGU + 0x0014) -/***CGU CPU Clock Reduction Register***/ -#define AMAZON_CGU_CPUCRD (AMAZON_CGU + 0x0018) -/***CGU Test Register**/ -#define AMAZON_CGU_TST (AMAZON_CGU + 0x003c) - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ - -#define AMAZON_PMU AMAZON_CGU -/***********************************************************************/ - - -/***PMU Power Down Control Register***/ -#define AMAZON_PMU_PWDCR ((volatile u32*)(AMAZON_PMU+ 0x001c)) -#define AMAZON_PMU_PWDCR_TPE (1 << 13) -#define AMAZON_PMU_PWDCR_PLL (1 << 12) -#define AMAZON_PMU_PWDCR_XTAL (1 << 11) -#define AMAZON_PMU_PWDCR_EBU (1 << 10) -#define AMAZON_PMU_PWDCR_DFE (1 << 9) -#define AMAZON_PMU_PWDCR_SPI (1 << 8) -#define AMAZON_PMU_PWDCR_UART (1 << 7) -#define AMAZON_PMU_PWDCR_GPT (1 << 6) -#define AMAZON_PMU_PWDCR_DMA (1 << 5) -#define AMAZON_PMU_PWDCR_PCI (1 << 4) -#define AMAZON_PMU_PWDCR_SW (1 << 3) -#define AMAZON_PMU_PWDCR_IOR (1 << 2) -#define AMAZON_PMU_PWDCR_FPI (1 << 1) -#define AMAZON_PMU_PWDCR_EPHY (1 << 0) - -/***PMU Status Register***/ -#define AMAZON_PMU_SR ((volatile u32*)(AMAZON_PMU+ 0x0020)) -#define AMAZON_PMU_SR_TPE (1 << 13) -#define AMAZON_PMU_SR_PLL (1 << 12) -#define AMAZON_PMU_SR_XTAL (1 << 11) -#define AMAZON_PMU_SR_EBU (1 << 10) -#define AMAZON_PMU_SR_DFE (1 << 9) -#define AMAZON_PMU_SR_SPI (1 << 8) -#define AMAZON_PMU_SR_UART (1 << 7) -#define AMAZON_PMU_SR_GPT (1 << 6) -#define AMAZON_PMU_SR_DMA (1 << 5) -#define AMAZON_PMU_SR_PCI (1 << 4) -#define AMAZON_PMU_SR_SW (1 << 3) -#define AMAZON_PMU_SR_IOR (1 << 2) -#define AMAZON_PMU_SR_FPI (1 << 1) -#define AMAZON_PMU_SR_EPHY (1 << 0) - -/***********************************************************************/ -/* Module : BCU register address and bits */ -/***********************************************************************/ - -#define AMAZON_BCU (KSEG1+0x10100000) -/***********************************************************************/ - - -/***BCU Control Register (0010H)***/ -#define AMAZON_BCU_CON ((volatile u32*)(AMAZON_BCU+ 0x0010)) -#define AMAZON_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) -#define AMAZON_BCU_CON_SPE (1 << 19) -#define AMAZON_BCU_CON_PSE (1 << 18) -#define AMAZON_BCU_CON_DBG (1 << 16) -#define AMAZON_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***BCU Error Control Capture Register (0020H)***/ -#define AMAZON_BCU_ECON ((volatile u32*)(AMAZON_BCU+ 0x0020)) -#define AMAZON_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) -#define AMAZON_BCU_ECON_RDN (1 << 23) -#define AMAZON_BCU_ECON_WRN (1 << 22) -#define AMAZON_BCU_ECON_SVM (1 << 21) -#define AMAZON_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) -#define AMAZON_BCU_ECON_ABT (1 << 18) -#define AMAZON_BCU_ECON_RDY (1 << 17) -#define AMAZON_BCU_ECON_TOUT (1 << 16) -#define AMAZON_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) -#define AMAZON_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ -#define AMAZON_BCU_EADD ((volatile u32*)(AMAZON_BCU+ 0x0024)) -#define AMAZON_BCU_EADD_FPIADR - -/***BCU Error Data Capture Register (0028H)***/ -#define AMAZON_BCU_EDAT ((volatile u32*)(AMAZON_BCU+ 0x0028)) -#define AMAZON_BCU_EDAT_FPIDAT - -/***********************************************************************/ -/* Module : Switch register address and bits */ -/***********************************************************************/ - -#define AMAZON_SWITCH (KSEG1+0x10106000) -/***********************************************************************/ -#define AMAZON_SW_UN_DEST AMAZON_SWITCH+0x00 /*Unknown destination register*/ -#define AMAZON_SW_VLAN_CTRL AMAZON_SWITCH+0x04 /*VLAN control register*/ -#define AMAZON_SW_PS_CTL AMAZON_SWITCH+0x08 /*port status control register*/ -#define AMAZON_SW_COS_CTL AMAZON_SWITCH+0x0c /*Cos control register*/ -#define AMAZON_SW_VLAN_COS AMAZON_SWITCH+0x10 /*VLAN priority cos mapping register*/ -#define AMAZON_SW_DSCP_COS3 AMAZON_SWITCH+0x14 /*DSCP cos mapping register3*/ -#define AMAZON_SW_DSCP_COS2 AMAZON_SWITCH+0x18 /*DSCP cos mapping register2*/ -#define AMAZON_SW_DSCP_COS1 AMAZON_SWITCH+0x1c /*DSCP cos mapping register1*/ -#define AMAZON_SW_DSCP_COS0 AMAZON_SWITCH+0x20 /*DSCP cos mapping register*/ -#define AMAZON_SW_ARL_CTL AMAZON_SWITCH+0x24 /*ARL control register*/ -#define AMAZON_SW_PKT_LEN AMAZON_SWITCH+0x28 /*packet length register*/ -#define AMAZON_SW_CPU_ACTL AMAZON_SWITCH+0x2c /*CPU control register1*/ -#define AMAZON_SW_DATA1 AMAZON_SWITCH+0x30 /*CPU access control register1*/ -#define AMAZON_SW_DATA2 AMAZON_SWITCH+0x34 /*CPU access control register2*/ -#define AMAZON_SW_P2_PCTL AMAZON_SWITCH+0x38 /*Port2 control register*/ -#define AMAZON_SW_P0_TX_CTL AMAZON_SWITCH+0x3c /*port0 TX control register*/ -#define AMAZON_SW_P1_TX_CTL AMAZON_SWITCH+0x40 /*port 1 TX control register*/ -#define AMAZON_SW_P0_WM AMAZON_SWITCH+0x44 /*port 0 watermark control register*/ -#define AMAZON_SW_P1_WM AMAZON_SWITCH+0x48 /*port 1 watermark control register*/ -#define AMAZON_SW_P2_WM AMAZON_SWITCH+0x4c /*port 2 watermark control register*/ -#define AMAZON_SW_GBL_WM AMAZON_SWITCH+0x50 /*Global watermark register*/ -#define AMAZON_SW_PM_CTL AMAZON_SWITCH+0x54 /*PM control register*/ -#define AMAZON_SW_P2_CTL AMAZON_SWITCH+0x58 /*PMAC control register*/ -#define AMAZON_SW_P2_TX_IPG AMAZON_SWITCH+0x5c /*port2 TX IPG control register*/ -#define AMAZON_SW_P2_RX_IPG AMAZON_SWITCH+0x60 /*prot2 RX IPG control register*/ -#define AMAZON_SW_MDIO_ACC AMAZON_SWITCH+0x64 /*MDIO access register*/ -#define AMAZON_SW_EPHY AMAZON_SWITCH+0x68 /*Ethernet PHY register*/ -#define AMAZON_SW_MDIO_CFG AMAZON_SWITCH+0x6c /*MDIO configuration register*/ -#define AMAZON_SW_P0_RCV_DROP_CNT AMAZON_SWITCH+0x70 /*port0 receive drop counter */ -#define AMAZON_SW_P0_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x74 /*port0 receive frame error conter*/ -#define AMAZON_SW_P0_TX_COLL_CNT AMAZON_SWITCH+0x78 /*port0 transmit collision counter*/ -#define AMAZON_SW_P0_TX_DROP_CNT AMAZON_SWITCH+0x7c /*port1 transmit drop counter*/ -#define AMAZON_SW_P1_RCV_DROP_CNT AMAZON_SWITCH+0x80 /*port1 receive drop counter*/ -#define AMAZON_SW_P1_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x84 /*port1 receive error counter*/ -#define AMAZON_SW_P1_TX_COLL_CNT AMAZON_SWITCH+0x88 /*port1 transmit collision counter*/ -#define AMAZON_SW_P1_TX_DROP_CNT AMAZON_SWITCH+0x8c /*port1 transmit drop counter*/ - - - -/***********************************************************************/ -/* Module : SSC register address and bits */ -/***********************************************************************/ -#define AMAZON_SSC_BASE_ADD_0 (KSEG1+0x10100800) - -/*165001:henryhsu:20050603:Source add by Bing Tao*/ - -/*configuration/Status Registers in Bus Clock Domain*/ -#define AMAZON_SSC_CLC ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0000)) -#define AMAZON_SSC_ID ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0008)) -#define AMAZON_SSC_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0010)) -#define AMAZON_SSC_STATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0014)) -#define AMAZON_SSC_WHBSTATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0018)) -#define AMAZON_SSC_TB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0020)) -#define AMAZON_SSC_RB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0024)) -#define AMAZON_SSC_FSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0038)) - -/*Configuration/Status Registers in Kernel Clock Domain*/ -#define AMAZON_SSC_PISEL ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0004)) -#define AMAZON_SSC_RXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0030)) -#define AMAZON_SSC_TXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0034)) -#define AMAZON_SSC_BR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0040)) -#define AMAZON_SSC_BRSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0044)) -#define AMAZON_SSC_SFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0060)) -#define AMAZON_SSC_SFSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0064)) -#define AMAZON_SSC_GPOCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0070)) -#define AMAZON_SSC_GPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0074)) -#define AMAZON_SSC_WHBGPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0078)) -#define AMAZON_SSC_RXREQ ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0080)) -#define AMAZON_SSC_RXCNT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0084)) - -/*DMA Registers in Bus Clock Domain*/ -#define AMAZON_SSC_DMA_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00ec)) - -/*interrupt Node Registers in Bus Clock Domain*/ -#define AMAZON_SSC_IRNEN ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F4)) -#define AMAZON_SSC_IRNICR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00FC)) -#define AMAZON_SSC_IRNCR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F8)) - -/*165001*/ - -/***********************************************************************/ - - - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define AMAZON_EBU (KSEG1+0x10105300) -/***********************************************************************/ - - -/***EBU Clock Control Register***/ -#define AMAZON_EBU_CLC ((volatile u32*)(AMAZON_EBU+ 0x0000)) -#define AMAZON_EBU_CLC_DISS (1 << 1) -#define AMAZON_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ -#define AMAZON_EBU_CON ((volatile u32*)(AMAZON_EBU+ 0x0010)) -#define AMAZON_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) -#define AMAZON_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) -#define AMAZON_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) -#define AMAZON_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) -#define AMAZON_EBU_CON_ARBSYNC (1 << 5) -#define AMAZON_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define AMAZON_EBU_ADDSEL0 ((volatile u32*)(AMAZON_EBU+ 0x0020)) -#define AMAZON_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -#define AMAZON_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_EBU_ADDSEL0_MIRRORE (1 << 1) -#define AMAZON_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ -#define AMAZON_EBU_ADDSEL1 ((volatile u32*)(AMAZON_EBU+ 0x0024)) -#define AMAZON_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -#define AMAZON_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_EBU_ADDSEL1_MIRRORE (1 << 1) -#define AMAZON_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ -#define AMAZON_EBU_ADDSEL2 ((volatile u32*)(AMAZON_EBU+ 0x0028)) -#define AMAZON_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -#define AMAZON_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_EBU_ADDSEL2_MIRRORE (1 << 1) -#define AMAZON_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define AMAZON_EBU_BUSCON0 ((volatile u32*)(AMAZON_EBU+ 0x0060)) -#define AMAZON_EBU_BUSCON0_WRDIS (1 << 31) -#define AMAZON_EBU_BUSCON0_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -#define AMAZON_EBU_BUSCON0_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -#define AMAZON_EBU_BUSCON0_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -#define AMAZON_EBU_BUSCON0_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -#define AMAZON_EBU_BUSCON0_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -#define AMAZON_EBU_BUSCON0_WAITINV (1 << 19) -#define AMAZON_EBU_BUSCON0_SETUP (1 << 18) -#define AMAZON_EBU_BUSCON0_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -#define AMAZON_EBU_BUSCON0_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -#define AMAZON_EBU_BUSCON0_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -#define AMAZON_EBU_BUSCON0_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -#define AMAZON_EBU_BUSCON0_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -#define AMAZON_EBU_BUSCON0_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define AMAZON_EBU_BUSCON1 ((volatile u32*)(AMAZON_EBU+ 0x0064)) -#define AMAZON_EBU_BUSCON1_WRDIS (1 << 31) -#define AMAZON_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -#define AMAZON_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -#define AMAZON_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -#define AMAZON_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -#define AMAZON_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -#define AMAZON_EBU_BUSCON1_WAITINV (1 << 19) -#define AMAZON_EBU_BUSCON1_SETUP (1 << 18) -#define AMAZON_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -#define AMAZON_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -#define AMAZON_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -#define AMAZON_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -#define AMAZON_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -#define AMAZON_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define AMAZON_EBU_BUSCON2 ((volatile u32*)(AMAZON_EBU+ 0x0068)) -#define AMAZON_EBU_BUSCON2_WRDIS (1 << 31) -#define AMAZON_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -#define AMAZON_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -#define AMAZON_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -#define AMAZON_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -#define AMAZON_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -#define AMAZON_EBU_BUSCON2_WAITINV (1 << 19) -#define AMAZON_EBU_BUSCON2_SETUP (1 << 18) -#define AMAZON_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -#define AMAZON_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -#define AMAZON_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -#define AMAZON_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -#define AMAZON_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -#define AMAZON_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ - -#define AMAZON_SDRAM (KSEG1+0x1F800000) -/***********************************************************************/ - - -/***MC Access Error Cause Register***/ -#define AMAZON_SDRAM_MC_ERRCAUSE ((volatile u32*)(AMAZON_SDRAM+ 0x0010)) -#define AMAZON_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -#define AMAZON_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -#define AMAZON_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ -#define AMAZON_SDRAM_MC_ERRADDR ((volatile u32*)(AMAZON_SDRAM+ 0x0020)) -#define AMAZON_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ -#define AMAZON_SDRAM_MC_IOGP ((volatile u32*)(AMAZON_SDRAM+ 0x0100)) -#define AMAZON_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) -#define AMAZON_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) -#define AMAZON_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) -#define AMAZON_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) -#define AMAZON_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) -#define AMAZON_SDRAM_MC_IOGP_CPS (1 << 11) -#define AMAZON_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) -#define AMAZON_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ -#define AMAZON_SDRAM_MC_SELFRFSH ((volatile u32*)(AMAZON_SDRAM+ 0x01A0)) -#define AMAZON_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -#define AMAZON_SDRAM_MC_SELFRFSH_PWD (1 << 0) -#define AMAZON_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ -#define AMAZON_SDRAM_MC_CTRLENA ((volatile u32*)(AMAZON_SDRAM+ 0x0110)) -#define AMAZON_SDRAM_MC_CTRLENA_ENA (1 << 0) -#define AMAZON_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ -#define AMAZON_SDRAM_MC_MRSCODE ((volatile u32*)(AMAZON_SDRAM+ 0x0120)) -#define AMAZON_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) -#define AMAZON_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) -#define AMAZON_SDRAM_MC_MRSCODE_WT (1 << 3) -#define AMAZON_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ -#define AMAZON_SDRAM_MC_CFGDW ((volatile u32*)(AMAZON_SDRAM+ 0x0130)) -#define AMAZON_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ -#define AMAZON_SDRAM_MC_CFGPB0 ((volatile u32*)(AMAZON_SDRAM+ 0x140)) -#define AMAZON_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) -#define AMAZON_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) -#define AMAZON_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ -#define AMAZON_SDRAM_MC_LATENCY ((volatile u32*)(AMAZON_SDRAM+ 0x0180)) -#define AMAZON_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) -#define AMAZON_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) -#define AMAZON_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) -#define AMAZON_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ -#define AMAZON_SDRAM_MC_TREFRESH ((volatile u32*)(AMAZON_SDRAM+ 0x0190)) -#define AMAZON_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) - -/***********************************************************************/ -/* Module : GPTU register address and bits */ -/***********************************************************************/ - -#define AMAZON_GPTU (KSEG1+0x10100A00) -/***********************************************************************/ - - -/***GPT Clock Control Register***/ -#define AMAZON_GPTU_CLC ((volatile u32*)(AMAZON_GPTU+ 0x0000)) -#define AMAZON_GPTU_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -#define AMAZON_GPTU_CLC_DISS (1 << 1) -#define AMAZON_GPTU_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ -#define AMAZON_GPTU_T3CON ((volatile u32*)(AMAZON_GPTU+ 0x0014)) -#define AMAZON_GPTU_T3CON_T3RDIR (1 << 15) -#define AMAZON_GPTU_T3CON_T3CHDIR (1 << 14) -#define AMAZON_GPTU_T3CON_T3EDGE (1 << 13) -#define AMAZON_GPTU_T3CON_BPS1(value) (((( 1 << 2) - 1) & (value)) << 11) -#define AMAZON_GPTU_T3CON_T3OTL (1 << 10) -#define AMAZON_GPTU_T3CON_T3UD (1 << 7) -#define AMAZON_GPTU_T3CON_T3R (1 << 6) -#define AMAZON_GPTU_T3CON_T3M(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T3CON_T3I(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register -If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define AMAZON_GPTU_WHBT3CON ((volatile u32*)(AMAZON_GPTU+ 0x004C)) -#define AMAZON_GPTU_WHBT3CON_SETT3CHDIR (1 << 15) -#define AMAZON_GPTU_WHBT3CON_CLRT3CHDIR (1 << 14) -#define AMAZON_GPTU_WHBT3CON_SETT3EDGE (1 << 13) -#define AMAZON_GPTU_WHBT3CON_CLRT3EDGE (1 << 12) -#define AMAZON_GPTU_WHBT3CON_SETT3OTL (1 << 11) -#define AMAZON_GPTU_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ -#define AMAZON_GPTU_T2CON ((volatile u32*)(AMAZON_GPTU+ 0x0010)) -#define AMAZON_GPTU_T2CON_TxRDIR (1 << 15) -#define AMAZON_GPTU_T2CON_TxCHDIR (1 << 14) -#define AMAZON_GPTU_T2CON_TxEDGE (1 << 13) -#define AMAZON_GPTU_T2CON_TxIRDIS (1 << 12) -#define AMAZON_GPTU_T2CON_TxRC (1 << 9) -#define AMAZON_GPTU_T2CON_TxUD (1 << 7) -#define AMAZON_GPTU_T2CON_TxR (1 << 6) -#define AMAZON_GPTU_T2CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T2CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ -#define AMAZON_GPTU_T4CON ((volatile u32*)(AMAZON_GPTU+ 0x0018)) -#define AMAZON_GPTU_T4CON_TxRDIR (1 << 15) -#define AMAZON_GPTU_T4CON_TxCHDIR (1 << 14) -#define AMAZON_GPTU_T4CON_TxEDGE (1 << 13) -#define AMAZON_GPTU_T4CON_TxIRDIS (1 << 12) -#define AMAZON_GPTU_T4CON_TxRC (1 << 9) -#define AMAZON_GPTU_T4CON_TxUD (1 << 7) -#define AMAZON_GPTU_T4CON_TxR (1 << 6) -#define AMAZON_GPTU_T4CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T4CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 2 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define AMAZON_GPTU_WHBT2CON ((volatile u32*)(AMAZON_GPTU+ 0x0048)) -#define AMAZON_GPTU_WHBT2CON_SETTxCHDIR (1 << 15) -#define AMAZON_GPTU_WHBT2CON_CLRTxCHDIR (1 << 14) -#define AMAZON_GPTU_WHBT2CON_SETTxEDGE (1 << 13) -#define AMAZON_GPTU_WHBT2CON_CLRTxEDGE (1 << 12) - -/***GPT Write HW Modified Timer 4 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define AMAZON_GPTU_WHBT4CON ((volatile u32*)(AMAZON_GPTU+ 0x0050)) -#define AMAZON_GPTU_WHBT4CON_SETTxCHDIR (1 << 15) -#define AMAZON_GPTU_WHBT4CON_CLRTxCHDIR (1 << 14) -#define AMAZON_GPTU_WHBT4CON_SETTxEDGE (1 << 13) -#define AMAZON_GPTU_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ -#define AMAZON_GPTU_CAPREL ((volatile u32*)(AMAZON_GPTU+ 0x0030)) -#define AMAZON_GPTU_CAPREL_CAPREL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ -#define AMAZON_GPTU_T2 ((volatile u32*)(AMAZON_GPTU+ 0x0034)) -#define AMAZON_GPTU_T2_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ -#define AMAZON_GPTU_T3 ((volatile u32*)(AMAZON_GPTU+ 0x0038)) -#define AMAZON_GPTU_T3_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ -#define AMAZON_GPTU_T4 ((volatile u32*)(AMAZON_GPTU+ 0x003C)) -#define AMAZON_GPTU_T4_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ -#define AMAZON_GPTU_T5 ((volatile u32*)(AMAZON_GPTU+ 0x0040)) -#define AMAZON_GPTU_T5_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ -#define AMAZON_GPTU_T6 ((volatile u32*)(AMAZON_GPTU+ 0x0044)) -#define AMAZON_GPTU_T6_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ -#define AMAZON_GPTU_T6CON ((volatile u32*)(AMAZON_GPTU+ 0x0020)) -#define AMAZON_GPTU_T6CON_T6SR (1 << 15) -#define AMAZON_GPTU_T6CON_T6CLR (1 << 14) -#define AMAZON_GPTU_T6CON_BPS2(value) (((( 1 << 2) - 1) & (value)) << 11) -#define AMAZON_GPTU_T6CON_T6OTL (1 << 10) -#define AMAZON_GPTU_T6CON_T6UD (1 << 7) -#define AMAZON_GPTU_T6CON_T6R (1 << 6) -#define AMAZON_GPTU_T6CON_T6M(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T6CON_T6I(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 6 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define AMAZON_GPTU_WHBT6CON ((volatile u32*)(AMAZON_GPTU+ 0x0054)) -#define AMAZON_GPTU_WHBT6CON_SETT6OTL (1 << 11) -#define AMAZON_GPTU_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ -#define AMAZON_GPTU_T5CON ((volatile u32*)(AMAZON_GPTU+ 0x001C)) -#define AMAZON_GPTU_T5CON_T5SC (1 << 15) -#define AMAZON_GPTU_T5CON_T5CLR (1 << 14) -#define AMAZON_GPTU_T5CON_CI(value) (((( 1 << 2) - 1) & (value)) << 12) -#define AMAZON_GPTU_T5CON_T5CC (1 << 11) -#define AMAZON_GPTU_T5CON_CT3 (1 << 10) -#define AMAZON_GPTU_T5CON_T5RC (1 << 9) -#define AMAZON_GPTU_T5CON_T5UDE (1 << 8) -#define AMAZON_GPTU_T5CON_T5UD (1 << 7) -#define AMAZON_GPTU_T5CON_T5R (1 << 6) -#define AMAZON_GPTU_T5CON_T5M(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T5CON_T5I(value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : ASC register address and bits */ -/***********************************************************************/ - -#define AMAZON_ASC (KSEG1+0x10100400) -/***********************************************************************/ - - -/***ASC Port Input Select Register***/ -#define AMAZON_ASC_PISEL (AMAZON_ASC+ 0x0004) -#define AMAZON_ASC_PISEL_RIS (1 << 0) - -/***ASC Control Register***/ -#define AMAZON_ASC_CON (AMAZON_ASC+ 0x0010) -#define AMAZON_ASC_CON_R (1 << 15) -#define AMAZON_ASC_CON_LB (1 << 14) -#define AMAZON_ASC_CON_BRS (1 << 13) -#define AMAZON_ASC_CON_ODD (1 << 12) -#define AMAZON_ASC_CON_FDE (1 << 11) -#define AMAZON_ASC_CON_OE (1 << 10) -#define AMAZON_ASC_CON_FE (1 << 9) -#define AMAZON_ASC_CON_PE (1 << 8) -#define AMAZON_ASC_CON_OEN (1 << 7) -#define AMAZON_ASC_CON_FEN (1 << 6) -#define AMAZON_ASC_CON_PENRXDI (1 << 5) -#define AMAZON_ASC_CON_REN (1 << 4) -#define AMAZON_ASC_CON_STP (1 << 3) -#define AMAZON_ASC_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***ASC Write Hardware Modified Control Register***/ -#define AMAZON_ASC_WHBCON (AMAZON_ASC+ 0x0050) -#define AMAZON_ASC_WHBCON_SETOE (1 << 13) -#define AMAZON_ASC_WHBCON_SETFE (1 << 12) -#define AMAZON_ASC_WHBCON_SETPE (1 << 11) -#define AMAZON_ASC_WHBCON_CLROE (1 << 10) -#define AMAZON_ASC_WHBCON_CLRFE (1 << 9) -#define AMAZON_ASC_WHBCON_CLRPE (1 << 8) -#define AMAZON_ASC_WHBCON_SETREN (1 << 5) -#define AMAZON_ASC_WHBCON_CLRREN (1 << 4) - -/***ASC Baudrate Timer/Reload Register***/ -#define AMAZON_ASC_BTR (AMAZON_ASC+ 0x0014) -#define AMAZON_ASC_BTR_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) - -/***ASC Fractional Divider Register***/ -#define AMAZON_ASC_FDV (AMAZON_ASC+ 0x0018) -#define AMAZON_ASC_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC IrDA Pulse Mode/Width Register***/ -#define AMAZON_ASC_PMW (AMAZON_ASC+ 0x001C) -#define AMAZON_ASC_PMW_IRPW (1 << 8) -#define AMAZON_ASC_PMW_PW_VALUE(value) (((( 1 << 8) - 1) & (value)) << 0) - -/***ASC Transmit Buffer Register***/ -#define AMAZON_ASC_TBUF (AMAZON_ASC+ 0x0020) -#define AMAZON_ASC_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Receive Buffer Register***/ -#define AMAZON_ASC_RBUF (AMAZON_ASC+ 0x0024) -#define AMAZON_ASC_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Autobaud Control Register***/ -#define AMAZON_ASC_ABCON (AMAZON_ASC+ 0x0030) -#define AMAZON_ASC_ABCON_RXINV (1 << 11) -#define AMAZON_ASC_ABCON_TXINV (1 << 10) -#define AMAZON_ASC_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) -#define AMAZON_ASC_ABCON_FCDETEN (1 << 4) -#define AMAZON_ASC_ABCON_ABDETEN (1 << 3) -#define AMAZON_ASC_ABCON_ABSTEN (1 << 2) -#define AMAZON_ASC_ABCON_AUREN (1 << 1) -#define AMAZON_ASC_ABCON_ABEN (1 << 0) - -/***Receive FIFO Control Register***/ -#define AMAZON_ASC_RXFCON (AMAZON_ASC+ 0x0040) -#define AMAZON_ASC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define AMAZON_ASC_RXFCON_RXTMEN (1 << 2) -#define AMAZON_ASC_RXFCON_RXFFLU (1 << 1) -#define AMAZON_ASC_RXFCON_RXFEN (1 << 0) - -/***Transmit FIFO Control Register***/ -#define AMAZON_ASC_TXFCON (AMAZON_ASC+ 0x0044) -#define AMAZON_ASC_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define AMAZON_ASC_TXFCON_TXTMEN (1 << 2) -#define AMAZON_ASC_TXFCON_TXFFLU (1 << 1) -#define AMAZON_ASC_TXFCON_TXFEN (1 << 0) - -/***FIFO Status Register***/ -#define AMAZON_ASC_FSTAT (AMAZON_ASC+ 0x0048) -#define AMAZON_ASC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define AMAZON_ASC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) - -/***ASC Write HW Modified Autobaud Control Register***/ -#define AMAZON_ASC_WHBABCON (AMAZON_ASC+ 0x0054) -#define AMAZON_ASC_WHBABCON_SETABEN (1 << 1) -#define AMAZON_ASC_WHBABCON_CLRABEN (1 << 0) - -/***ASC Autobaud Status Register***/ -#define AMAZON_ASC_ABSTAT (AMAZON_ASC+ 0x0034) -#define AMAZON_ASC_ABSTAT_DETWAIT (1 << 4) -#define AMAZON_ASC_ABSTAT_SCCDET (1 << 3) -#define AMAZON_ASC_ABSTAT_SCSDET (1 << 2) -#define AMAZON_ASC_ABSTAT_FCCDET (1 << 1) -#define AMAZON_ASC_ABSTAT_FCSDET (1 << 0) - -/***ASC Write HW Modified Autobaud Status Register***/ -#define AMAZON_ASC_WHBABSTAT (AMAZON_ASC+ 0x0058) -#define AMAZON_ASC_WHBABSTAT_SETDETWAIT (1 << 9) -#define AMAZON_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) -#define AMAZON_ASC_WHBABSTAT_SETSCCDET (1 << 7) -#define AMAZON_ASC_WHBABSTAT_CLRSCCDET (1 << 6) -#define AMAZON_ASC_WHBABSTAT_SETSCSDET (1 << 5) -#define AMAZON_ASC_WHBABSTAT_CLRSCSDET (1 << 4) -#define AMAZON_ASC_WHBABSTAT_SETFCCDET (1 << 3) -#define AMAZON_ASC_WHBABSTAT_CLRFCCDET (1 << 2) -#define AMAZON_ASC_WHBABSTAT_SETFCSDET (1 << 1) -#define AMAZON_ASC_WHBABSTAT_CLRFCSDET (1 << 0) - -/***ASC Clock Control Register***/ -#define AMAZON_ASC_CLC (AMAZON_ASC+ 0x0000) -#define AMAZON_ASC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -#define AMAZON_ASC_CLC_DISS (1 << 1) -#define AMAZON_ASC_CLC_DISR (1 << 0) - -/***ASC IRNCR0 **/ -#define AMAZON_ASC_IRNCR0 (AMAZON_ASC+ 0x00FC) -/***ASC IRNCR1 **/ -#define AMAZON_ASC_IRNCR1 (AMAZON_ASC+ 0x00F8) -#define ASC_IRNCR_TIR 0x1 -#define ASC_IRNCR_RIR 0x2 -#define ASC_IRNCR_EIR 0x4 -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define AMAZON_DMA (KSEG1+0x10103000) -/***********************************************************************/ -#define AMAZON_DMA_CH_ON AMAZON_DMA+0x28 -#define AMAZON_DMA_CH_RST AMAZON_DMA+0x2c -#define AMAZON_DMA_CH0_ISR AMAZON_DMA+0x30 -#define AMAZON_DMA_CH1_ISR AMAZON_DMA+0x34 -#define AMAZON_DMA_CH2_ISR AMAZON_DMA+0x38 -#define AMAZON_DMA_CH3_ISR AMAZON_DMA+0x3c -#define AMAZON_DMA_CH4_ISR AMAZON_DMA+0x40 -#define AMAZON_DMA_CH5_ISR AMAZON_DMA+0x44 -#define AMAZON_DMA_CH6_ISR AMAZON_DMA+0x48 -#define AMAZON_DMA_CH7_ISR AMAZON_DMA+0x4c -#define AMAZON_DMA_CH8_ISR AMAZON_DMA+0x50 -#define AMAZON_DMA_CH9_ISR AMAZON_DMA+0x54 -#define AMAZON_DMA_CH10_ISR AMAZON_DMA+0x58 -#define AMAZON_DMA_CH11_ISR AMAZON_DMA+0x5c -#define AMAZON_DMA_CH0_MSK AMAZON_DMA+0x60 -#define AMAZON_DMA_CH1_MSK AMAZON_DMA+0x64 -#define AMAZON_DMA_CH2_MSK AMAZON_DMA+0x68 -#define AMAZON_DMA_CH3_MSK AMAZON_DMA+0x6c -#define AMAZON_DMA_CH4_MSK AMAZON_DMA+0x70 -#define AMAZON_DMA_CH5_MSK AMAZON_DMA+0x74 -#define AMAZON_DMA_CH6_MSK AMAZON_DMA+0x78 -#define AMAZON_DMA_CH7_MSK AMAZON_DMA+0x7c -#define AMAZON_DMA_CH8_MSK AMAZON_DMA+0x80 -#define AMAZON_DMA_CH9_MSK AMAZON_DMA+0x84 -#define AMAZON_DMA_CH10_MSK AMAZON_DMA+0x88 -#define AMAZON_DMA_CH11_MSK AMAZON_DMA+0x8c -#define AMAZON_DMA_Desc_BA AMAZON_DMA+0x90 -#define AMAZON_DMA_CH0_DES_LEN AMAZON_DMA+0x94 -#define AMAZON_DMA_CH1_DES_LEN AMAZON_DMA+0x98 -#define AMAZON_DMA_CH2_DES_LEN AMAZON_DMA+0x9c -#define AMAZON_DMA_CH3_DES_LEN AMAZON_DMA+0xa0 -#define AMAZON_DMA_CH4_DES_LEN AMAZON_DMA+0xa4 -#define AMAZON_DMA_CH5_DES_LEN AMAZON_DMA+0xa8 -#define AMAZON_DMA_CH6_DES_LEN AMAZON_DMA+0xac -#define AMAZON_DMA_CH7_DES_LEN AMAZON_DMA+0xb0 -#define AMAZON_DMA_CH8_DES_LEN AMAZON_DMA+0xb4 -#define AMAZON_DMA_CH9_DES_LEN AMAZON_DMA+0xb8 -#define AMAZON_DMA_CH10_DES_LEN AMAZON_DMA+0xbc -#define AMAZON_DMA_CH11_DES_LEN AMAZON_DMA+0xc0 -#define AMAZON_DMA_CH1_DES_OFST AMAZON_DMA+0xc4 -#define AMAZON_DMA_CH2_DES_OFST AMAZON_DMA+0xc8 -#define AMAZON_DMA_CH3_DES_OFST AMAZON_DMA+0xcc -#define AMAZON_DMA_CH4_DES_OFST AMAZON_DMA+0xd0 -#define AMAZON_DMA_CH5_DES_OFST AMAZON_DMA+0xd4 -#define AMAZON_DMA_CH6_DES_OFST AMAZON_DMA+0xd8 -#define AMAZON_DMA_CH7_DES_OFST AMAZON_DMA+0xdc -#define AMAZON_DMA_CH8_DES_OFST AMAZON_DMA+0xe0 -#define AMAZON_DMA_CH9_DES_OFST AMAZON_DMA+0xe4 -#define AMAZON_DMA_CH10_DES_OFST AMAZON_DMA+0xe8 -#define AMAZON_DMA_CH11_DES_OFST AMAZON_DMA+0xec -#define AMAZON_DMA_SW_BL AMAZON_DMA+0xf0 -#define AMAZON_DMA_TPE_BL AMAZON_DMA+0xf4 -#define AMAZON_DMA_DPlus2FPI_BL AMAZON_DMA+0xf8 -#define AMAZON_DMA_GRX_BUF_LEN AMAZON_DMA+0xfc -#define AMAZON_DMA_DMA_ECON_REG AMAZON_DMA+0x100 -#define AMAZON_DMA_POLLING_REG AMAZON_DMA+0x104 -#define AMAZON_DMA_CH_WGT AMAZON_DMA+0x108 -#define AMAZON_DMA_TX_WGT AMAZON_DMA+0x10c -#define AMAZON_DMA_DPLus2FPI_CLASS AMAZON_DMA+0x110 -#define AMAZON_DMA_COMB_ISR AMAZON_DMA+0x114 - -//channel reset -#define SWITCH1_RST_MASK 0x83 /* Switch1 channel mask */ -#define SWITCH2_RST_MASK 0x10C /* Switch1 channel mask */ -#define TPE_RST_MASK 0x630 /* TPE channel mask */ -#define DPlus2FPI_RST_MASK 0x840 /* DPlusFPI channel mask */ - -//ISR -#define DMA_ISR_RDERR 0x20 -#define DMA_ISR_CMDCPT 0x10 -#define DMA_ISR_CPT 0x8 -#define DMA_ISR_DURR 0x4 -#define DMA_ISR_EOP 0x2 -#define DMA_DESC_BYTEOFF_SHIFT 23 - -#define DMA_POLLING_ENABLE 0x80000000 -#define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/ - -/***********************************************************************/ -/* Module : Debug register address and bits */ -/***********************************************************************/ - -#define AMAZON_DEBUG (KSEG1+0x1F106000) -/***********************************************************************/ - - -/***MCD Break System Control Register***/ -#define AMAZON_DEBUG_MCD_BSCR ((volatile u32*)(AMAZON_DEBUG+ 0x0000)) - -/***PMC Performance Counter Control Register0***/ -#define AMAZON_DEBUG_PMC_PCCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0010)) - -/***PMC Performance Counter Control Register1***/ -#define AMAZON_DEBUG_PMC_PCCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0014)) - -/***PMC Performance Counter Register0***/ -#define AMAZON_DEBUG_PMC_PCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0018)) - -/*165001:henryhsu:20050603:Source modified by Bing Tao*/ - -/***PMC Performance Counter Register1***/ -//#define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0020)) -#define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x001c)) - -/*165001*/ - - - -/***MCD Suspend Mode Control Register***/ -#define AMAZON_DEBUG_MCD_SMCR ((volatile u32*)(AMAZON_DEBUG+ 0x0024)) - -/***********************************************************************/ -/* Module : GPIO register address and bits */ -/***********************************************************************/ - -#define AMAZON_GPIO (KSEG1+0x10100B00) -/***********************************************************************/ - - -/***Port 0 Data Output Register (0010H)***/ -#define AMAZON_GPIO_P0_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0010)) - -/***Port 1 Data Output Register (0040H)***/ -#define AMAZON_GPIO_P1_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0040)) - -/***Port 0 Data Input Register (0014H)***/ -#define AMAZON_GPIO_P0_IN ((volatile u32*)(AMAZON_GPIO+ 0x0014)) - -/***Port 1 Data Input Register (0044H)***/ -#define AMAZON_GPIO_P1_IN ((volatile u32*)(AMAZON_GPIO+ 0x0044)) - -/***Port 0 Direction Register (0018H)***/ -#define AMAZON_GPIO_P0_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0018)) - -/***Port 1 Direction Register (0048H)***/ -#define AMAZON_GPIO_P1_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0048)) - -/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -#define AMAZON_GPIO_P0_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x001C)) - -/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -#define AMAZON_GPIO_P1_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x004C)) - -/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -#define AMAZON_GPIO_P0_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0020)) - -/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -#define AMAZON_GPIO_P1_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0050)) - -/***Port 0 Open Drain Control Register (0024H)***/ -#define AMAZON_GPIO_P0_OD ((volatile u32*)(AMAZON_GPIO+ 0x0024)) - -/***Port 1 Open Drain Control Register (0054H)***/ -#define AMAZON_GPIO_P1_OD ((volatile u32*)(AMAZON_GPIO+ 0x0054)) - -/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -#define AMAZON_GPIO_P0_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0028)) - -/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -#define AMAZON_GPIO_P1_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0058)) - -/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -#define AMAZON_GPIO_P0_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x002C)) - -/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -#define AMAZON_GPIO_P1_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x005C)) - -/***Port 0 Pull Up Device Enable Register (0030 H)***/ -#define AMAZON_GPIO_P0_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0030)) - -/***Port 1 Pull Up Device Enable Register (0060 H)***/ -#define AMAZON_GPIO_P1_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0060)) - -/***********************************************************************/ -/* Module : BIU register address and bits */ -/***********************************************************************/ - -#define AMAZON_BIU (KSEG1+0x1FA80000) -/***********************************************************************/ - - -/***BIU Identification Register***/ -#define AMAZON_BIU_ID ((volatile u32*)(AMAZON_BIU+ 0x0000)) -#define AMAZON_BIU_ID_ARCH (1 << 16) -#define AMAZON_BIU_ID_ID(value) (((( 1 << 8) - 1) & (value)) << 8) -#define AMAZON_BIU_ID_REV(value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ -#define AMAZON_BIU_ERRCAUSE ((volatile u32*)(AMAZON_BIU+ 0x0100)) -#define AMAZON_BIU_ERRCAUSE_ERR (1 << 31) -#define AMAZON_BIU_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -#define AMAZON_BIU_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ -#define AMAZON_BIU_ERRADDR ((volatile u32*)(AMAZON_BIU+ 0x0108)) -#define AMAZON_BIU_ERRADDR_ADDR - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define AMAZON_ICU (KSEG1+0x1F101000) -/***********************************************************************/ - -/***IM0 Interrupt Status Register***/ -#define AMAZON_ICU_IM0_ISR (AMAZON_ICU + 0x0010) -#define AMAZON_ICU_IM1_ISR (AMAZON_ICU + 0x0020) -#define AMAZON_ICU_IM2_ISR (AMAZON_ICU + 0x0030) -#define AMAZON_ICU_IM3_ISR (AMAZON_ICU + 0x0040) -#define AMAZON_ICU_IM4_ISR (AMAZON_ICU + 0x0050) - -/***IM0 Interrupt Enable Register***/ -#define AMAZON_ICU_IM0_IER (AMAZON_ICU + 0x0014) -#define AMAZON_ICU_IM1_IER (AMAZON_ICU + 0x0024) -#define AMAZON_ICU_IM2_IER (AMAZON_ICU + 0x0034) -#define AMAZON_ICU_IM3_IER (AMAZON_ICU + 0x0044) -#define AMAZON_ICU_IM4_IER (AMAZON_ICU + 0x0054) - -/***IM0 Interrupt Output Status Register***/ -#define AMAZON_ICU_IM0_IOSR (AMAZON_ICU + 0x0018) -#define AMAZON_ICU_IM1_IOSR (AMAZON_ICU + 0x0028) -#define AMAZON_ICU_IM2_IOSR (AMAZON_ICU + 0x0038) -#define AMAZON_ICU_IM3_IOSR (AMAZON_ICU + 0x0048) -#define AMAZON_ICU_IM4_IOSR (AMAZON_ICU + 0x0058) - -/***IM0 Interrupt Request Set Register***/ -#define AMAZON_ICU_IM0_IRSR (AMAZON_ICU + 0x001c) -#define AMAZON_ICU_IM1_IRSR (AMAZON_ICU + 0x002c) -#define AMAZON_ICU_IM2_IRSR (AMAZON_ICU + 0x003c) -#define AMAZON_ICU_IM3_IRSR (AMAZON_ICU + 0x004c) -#define AMAZON_ICU_IM4_IRSR (AMAZON_ICU + 0x005c) - -/***Interrupt Vector Value Register***/ -#define AMAZON_ICU_IM_VEC (AMAZON_ICU + 0x0060) - -/***Interrupt Vector Value Mask***/ -#define AMAZON_ICU_IM0_VEC_MASK 0x0000001f -#define AMAZON_ICU_IM1_VEC_MASK 0x000003e0 -#define AMAZON_ICU_IM2_VEC_MASK 0x00007c00 -#define AMAZON_ICU_IM3_VEC_MASK 0x000f8000 -#define AMAZON_ICU_IM4_VEC_MASK 0x01f00000 - -/***DMA Interrupt Mask Value***/ -#define AMAZON_DMA_H_MASK 0x00000fff - -/***External Interrupt Control Register***/ -#define AMAZON_ICU_EXTINTCR (AMAZON_ICU + 0x0000) -#define AMAZON_ICU_IRNICR (AMAZON_ICU + 0x0004) -#define AMAZON_ICU_IRNCR (AMAZON_ICU + 0x0008) -#define AMAZON_ICU_IRNEN (AMAZON_ICU + 0x000c) - -/***********************************************************************/ -/* Module : PCI/Card-BUS/PC-Card register address and bits */ -/***********************************************************************/ - -#define AMAZON_PCI (KSEG1+0x10105400) -#define AMAZON_PCI_CFG_BASE (KSEG1+0x11000000) -#define AMAZON_PCI_MEM_BASE (KSEG1+0x12000000) - -#define CLOCK_CONTROL AMAZON_PCI + 0x00000000 -#define ARB_CTRL_bit 1 -#define IDENTIFICATION AMAZON_PCI + 0x00000004 -#define SOFTRESET AMAZON_PCI + 0x00000010 -#define PCI_FPI_ERROR_ADDRESS AMAZON_PCI + 0x00000014 -#define FPI_PCI_ERROR_ADDRESS AMAZON_PCI + 0x00000018 -#define FPI_ERROR_TAG AMAZON_PCI + 0x0000001c -#define IRR AMAZON_PCI + 0x00000020 -#define IRA_IR AMAZON_PCI + 0x00000024 -#define IRM AMAZON_PCI + 0x00000028 -#define DMA_COMPLETE_BIT 0 -#define PCI_POWER_CHANGE_BIT 16 -#define PCI_MASTER0_BROKEN_INT_BIT 24 -#define PCI_MASTER1_BROKEN_INT_BIT 25 -#define PCI_MASTER2_BROKEN_INT_BIT 26 -#define EOI AMAZON_PCI + 0x0000002c -#define PCI_MODE AMAZON_PCI + 0x00000030 -#define PCI_MODE_cfgok_bit 24 -#define DEVICE_VENDOR_ID AMAZON_PCI + 0x00000034 -#define SUBSYSTEM_VENDOR_ID AMAZON_PCI + 0x00000038 -#define POWER_MANAGEMENT AMAZON_PCI + 0x0000003c -#define CLASS_CODE1 AMAZON_PCI + 0x00000040 -#define BAR11_MASK AMAZON_PCI + 0x00000044 -#define BAR12_MASK AMAZON_PCI + 0x00000048 -#define BAR13_MASK AMAZON_PCI + 0x0000004c -#define BAR14_MASK AMAZON_PCI + 0x00000050 -#define BAR15_MASK AMAZON_PCI + 0x00000054 -#define BAR16_MASK AMAZON_PCI + 0x00000058 -#define CARDBUS_CIS_POINTER1 AMAZON_PCI + 0x0000005c -#define SUBSYSTEM_ID1 AMAZON_PCI + 0x00000060 -#define PCI_ADDRESS_MAP_11 AMAZON_PCI + 0x00000064 -#define PCI_ADDRESS_MAP_12 AMAZON_PCI + 0x00000068 -#define PCI_ADDRESS_MAP_13 AMAZON_PCI + 0x0000006c -#define PCI_ADDRESS_MAP_14 AMAZON_PCI + 0x00000070 -#define PCI_ADDRESS_MAP_15 AMAZON_PCI + 0x00000074 -#define PCI_ADDRESS_MAP_16 AMAZON_PCI + 0x00000078 -#define FPI_SEGMENT_ENABLE AMAZON_PCI + 0x0000007c -#define CLASS_CODE2 AMAZON_PCI + 0x00000080 -#define BAR21_MASK AMAZON_PCI + 0x00000084 -#define BAR22_MASK AMAZON_PCI + 0x00000088 -#define BAR23_MASK AMAZON_PCI + 0x0000008c -#define BAR24_MASK AMAZON_PCI + 0x00000090 -#define BAR25_MASK AMAZON_PCI + 0x00000094 -#define BAR26_MASK AMAZON_PCI + 0x00000098 -#define CARDBUS_CIS_POINTER2 AMAZON_PCI + 0x0000009c -#define SUBSYSTEM_ID2 AMAZON_PCI + 0x000000a0 -#define PCI_ADDRESS_MAP_21 AMAZON_PCI + 0x000000a4 -#define PCI_ADDRESS_MAP_22 AMAZON_PCI + 0x000000a8 -#define PCI_ADDRESS_MAP_23 AMAZON_PCI + 0x000000ac -#define PCI_ADDRESS_MAP_24 AMAZON_PCI + 0x000000b0 -#define PCI_ADDRESS_MAP_25 AMAZON_PCI + 0x000000b4 -#define PCI_ADDRESS_MAP_26 AMAZON_PCI + 0x000000b8 -#define FPI_ADDRESS_MASK11LOW AMAZON_PCI + 0x000000bc -#define FPI_ADDRESS_MAP_0 AMAZON_PCI + 0x000000c0 -#define FPI_ADDRESS_MAP_1 AMAZON_PCI + 0x000000c4 -#define FPI_ADDRESS_MAP_2 AMAZON_PCI + 0x000000c8 -#define FPI_ADDRESS_MAP_3 AMAZON_PCI + 0x000000cc -#define FPI_ADDRESS_MAP_4 AMAZON_PCI + 0x000000d0 -#define FPI_ADDRESS_MAP_5 AMAZON_PCI + 0x000000d4 -#define FPI_ADDRESS_MAP_6 AMAZON_PCI + 0x000000d8 -#define FPI_ADDRESS_MAP_7 AMAZON_PCI + 0x000000dc -#define FPI_ADDRESS_MAP_11LOW AMAZON_PCI + 0x000000e0 -#define FPI_ADDRESS_MAP_11HIGH AMAZON_PCI + 0x000000e4 -#define FPI_BURST_LENGTH AMAZON_PCI + 0x000000e8 -#define SET_PCI_SERR AMAZON_PCI + 0x000000ec -#define DMA_FPI_START_ADDR AMAZON_PCI + 0x000000f0 -#define DMA_PCI_START_ADDR AMAZON_PCI + 0x000000f4 -#define DMA_TRANSFER_COUNT AMAZON_PCI + 0x000000f8 -#define DMA_CONTROL_STATUS AMAZON_PCI + 0x000000fc - -#define EXT_PCI1_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x0800 -#define EXT_PCI2_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1000 -#define EXT_PCI3_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1800 -#define EXT_PCI4_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2000 -#define EXT_PCI5_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2800 -#define EXT_PCI6_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3000 -#define EXT_PCI7_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3800 -#define EXT_PCI8_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4000 -#define EXT_PCI9_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4800 -#define EXT_PCI10_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5000 -#define EXT_PCI11_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5800 -#define EXT_PCI12_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6000 -#define EXT_PCI13_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6800 -#define EXT_PCI14_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7000 -#define EXT_PCI15_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7800 -#define EXT_CARDBUS_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0XF000 -#define EXT_PCI_BAR1_ADDR 0x10 -#define EXT_PCI_BAR2_ADDR 0x14 -#define EXT_PCI_BAR3_ADDR 0x18 -#define EXT_PCI_BAR4_ADDR 0x1C -#define EXT_PCI_BAR5_ADDR 0x20 -#define EXT_PCI_BAR6_ADDR 0x24 - -#define DEVICE_ID_VECDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x0 -#define STATUS_COMMAND_ADDR AMAZON_PCI_CFG_BASE + 0x4 -#define BUS_MASTER_ENABLE_BIT 2 -#define MEM_SPACE_ENABLE_BIT 1 -#define CLASS_CODE_REVISION_ADDR AMAZON_PCI_CFG_BASE + 0x8 -#define BIST_HEADER_TYPE_LATENCY_CAHCE_ADDR AMAZON_PCI_CFG_BASE + 0xC -#define BAR1_ADDR AMAZON_PCI_CFG_BASE + 0x10 -#define BAR2_ADDR AMAZON_PCI_CFG_BASE + 0x14 -#define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18 -#define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C -#define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18 -#define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C -#define BAR5_ADDR AMAZON_PCI_CFG_BASE + 0x20 -#define BAR6_ADDR AMAZON_PCI_CFG_BASE + 0x24 -#define CARDBUS_CIS_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x28 -#define SUBSYSTEM_ID_VENDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x2C -#define EXPANSION_ROM_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x30 -#define CAPABILITIES_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x34 -#define RESERVED_0x38 AMAZON_PCI_CFG_BASE + 0x38 -#define MAX_LAT_MIN_GNT_INT_PIN_LINE_ADDR AMAZON_PCI_CFG_BASE + 0x3C -#define POWER_MNGT_NEXT_POINTER_CAP_ID_ADDR AMAZON_PCI_CFG_BASE + 0x40 -#define POWER_MANAGEMENT_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x44 -#define RESERVED_0x48 AMAZON_PCI_CFG_BASE + 0x48 -#define RESERVED_0x4C AMAZON_PCI_CFG_BASE + 0x4C -#define ERROR_ADDR_PCI_FPI_ADDR AMAZON_PCI_CFG_BASE + 0x50 -#define ERROR_ADdR_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x54 -#define ERROR_TAG_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x58 -#define PCI_ARB_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x5C -#define INTERNAL_ARB_ENABLE_BIT 0 -#define ARB_SCHEME_BIT 1 -#define PCI_MASTER0_PRIOR_2BITS 2 -#define PCI_MASTER1_PRIOR_2BITS 4 -#define PCI_MASTER2_PRIOR_2BITS 6 -#define PCI_MASTER0_REQ_MASK_2BITS 8 -#define PCI_MASTER1_REQ_MASK_2BITS 10 -#define PCI_MASTER2_REQ_MASK_2BITS 12 -#define PCI_MASTER0_GNT_MASK_2BITS 14 -#define PCI_MASTER1_GNT_MASK_2BITS 16 -#define PCI_MASTER2_GNT_MASK_2BITS 18 -#define FPI_PCI_INT_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x60 -#define FPI_PCI_INT_ACK_ADDR AMAZON_PCI_CFG_BASE + 0x64 -#define FPI_PCI_INT_MASK_ADDR AMAZON_PCI_CFG_BASE + 0x68 -#define CARDBUS_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x6C -#define CARDBUS_CFRAME_ENABLE 0 - -#define CLOCK_CONTROL_default 0x00000000 -#define CLOCK_CONTROL_mask 0x00000003 - -#define IDENTIFICATION_default 0x0011C002 -#define IDENTIFICATION_mask 0x00000000 - -#define SOFTRESET_default 0x00000000 -// SOFTRESET bit 0 is writable but will be reset to 0 after software reset is over -#define SOFTRESET_mask 0x00000000 - -#define PCI_FPI_ERROR_ADDRESS_default 0xFFFFFFFF -#define PCI_FPI_ERROR_ADDRESS_mask 0x00000000 - -#define FPI_PCI_ERROR_ADDRESS_default 0xFFFFFFFF -#define FPI_PCI_ERROR_ADDRESS_mask 0x00000000 - -#define FPI_ERROR_TAG_default 0x0000000F -#define FPI_ERROR_TAG_mask 0x00000000 - -#define IRR_default 0x00000000 -#define IRR_mask 0x07013b2F - -#define IRA_IR_default 0x00000000 -#define IRA_IR_mask 0x07013b2F - -#define IRM_default 0x00000000 -#define IRM_mask 0xFFFFFFFF - -#define EOI_default 0x00000000 -#define EOI_mask 0x00000000 - -#define PCI_MODE_default 0x01000103 -#define PCI_MODE_mask 0x1107070F - -#define DEVICE_VENDOR_ID_default 0x000C15D1 -#define DEVICE_VENDOR_ID_mask 0xFFFFFFFF - -#define SUBSYSTEM_VENDOR_ID_default 0x000015D1 -#define SUBSYSTEM_VENDOR_ID_mask 0x0000FFFF - -#define POWER_MANAGEMENT_default 0x0000001B -#define POWER_MANAGEMENT_mask 0x0000001F - -#define CLASS_CODE1_default 0x00028000 -#define CLASS_CODE1_mask 0x00FFFFFF - -#define BAR11_MASK_default 0x0FF00008 -#define BAR11_MASK_mask 0x8FF00008 - -#define BAR12_MASK_default 0x80001800 -#define BAR12_MASK_mask 0x80001F08 - -#define BAR13_MASK_default 0x8FF00008 -#define BAR13_MASK_mask 0x8FF00008 - -#define BAR14_MASK_default 0x8F000000 -#define BAR14_MASK_mask 0x8FFFFF08 - -#define BAR15_MASK_default 0x80000000 -#define BAR15_MASK_mask 0x8FFFFF08 - -#define BAR16_MASK_default 0x80000001 -// bit 0 and bit 3 is mutually exclusive -#define BAR16_MASK_mask 0x8FFFFFF9 - -#define CARDBUS_CIS_POINTER1_default 0x00000000 -#define CARDBUS_CIS_POINTER1_mask 0x03FFFFFF - -#define SUBSYSTEM_ID1_default 0x0000000C -#define SUBSYSTEM_ID1_mask 0x0000FFFF - -#define PCI_ADDRESS_MAP_11_default 0x18000000 -#define PCI_ADDRESS_MAP_11_mask 0x7FFFFFF1 - -#define PCI_ADDRESS_MAP_12_default 0x18100000 -#define PCI_ADDRESS_MAP_12_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_13_default 0x18200000 -#define PCI_ADDRESS_MAP_13_mask 0x7FF00001 - -#define PCI_ADDRESS_MAP_14_default 0x70000000 -#define PCI_ADDRESS_MAP_14_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_15_default 0x00000001 -#define PCI_ADDRESS_MAP_15_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_16_default 0x60000000 -#define PCI_ADDRESS_MAP_16_mask 0x7FF00001 - -#define FPI_SEGMENT_ENABLE_default 0x000003FF -#define FPI_SEGMENT_ENABLE_mask 0x000003FF - -#define CLASS_CODE2_default 0x00FF0000 -#define CLASS_CODE2_mask 0x00FFFFFF - -#define BAR21_MASK_default 0x80000008 -#define BAR21_MASK_mask 0x8FFFFFF8 - -#define BAR22_MASK_default 0x80000008 -#define BAR22_MASK_mask 0x80001F08 - -#define BAR23_MASK_default 0x80000008 -#define BAR23_MASK_mask 0x8FF00008 - -#define BAR24_MASK_default 0x8FE00000 -#define BAR24_MASK_mask 0x8FFFFF08 - -#define BAR25_MASK_default 0x8FFFF000 -#define BAR25_MASK_mask 0x8FFFFF08 - -#define BAR26_MASK_default 0x8FFFFFE1 -#define BAR26_MASK_mask 0x8FFFFFF1 - -#define CARDBUS_CIS_POINTER2_default 0x00000000 -#define CARDBUS_CIS_POINTER2_mask 0x03FFFFFF - -#define SUBSYSTEM_ID2_default 0x0000000C -#define SUBSYSTEM_ID2_mask 0x0000FFFF - -#define PCI_ADDRESS_MAP_21_default 0x3FE00000 -#define PCI_ADDRESS_MAP_21_mask 0x7FFFFFF1 - -#define PCI_ADDRESS_MAP_22_default 0x68000000 -#define PCI_ADDRESS_MAP_22_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_23_default 0x20000000 -#define PCI_ADDRESS_MAP_23_mask 0x7FF00001 - -#define PCI_ADDRESS_MAP_24_default 0x70000001 -#define PCI_ADDRESS_MAP_24_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_25_default 0x78000001 -#define PCI_ADDRESS_MAP_25_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_26_default 0x20000000 -#define PCI_ADDRESS_MAP_26_mask 0x7FF00001 - -#define FPI_ADDRESS_MASK11LOW_default 0x00000000 -#define FPI_ADDRESS_MASK11LOW_mask 0x00070000 - -#define FPI_ADDRESS_MAP_0_default 0x00000000 -#define FPI_ADDRESS_MAP_0_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_1_default 0x10000000 -#define FPI_ADDRESS_MAP_1_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_2_default 0x20000000 -#define FPI_ADDRESS_MAP_2_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_3_default 0x30000000 -#define FPI_ADDRESS_MAP_3_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_4_default 0x40000000 -#define FPI_ADDRESS_MAP_4_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_5_default 0x50000000 -#define FPI_ADDRESS_MAP_5_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_6_default 0x60000000 -#define FPI_ADDRESS_MAP_6_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_7_default 0x70000000 -#define FPI_ADDRESS_MAP_7_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_11LOW_default 0xB0000000 -#define FPI_ADDRESS_MAP_11LOW_mask 0xFFFF0000 - -#define FPI_ADDRESS_MAP_11HIGH_default 0xB8000000 -#define FPI_ADDRESS_MAP_11HIGH_mask 0xFFF80000 - -#define FPI_BURST_LENGTH_default 0x00000000 -#define FPI_BURST_LENGTH_mask 0x00000303 - -#define SET_PCI_SERR_default 0x00000000 -#define SET_PCI_SERR_mask 0x00000000 - -#define DMA_FPI_START_ADDRESS_default 0x00000000 -#define DMA_FPI_START_ADDRESS_mask 0xFFFFFFFF - -#define DMA_PCI_START_ADDRESS_default 0x00000000 -#define DMA_PCI_START_ADDRESS_mask 0xFFFFFFFF - -#define DMA_TRANSFER_COUNT_default 0x00000000 -#define DMA_TRANSFER_COUNT_mask 0x0000FFFF - -#define DMA_CONTROL_STATUS_default 0x00000000 -#define DMA_CONTROL_STATUS_mask 0x00000000 // bit 0,1 is writable - -/***********************************************************************/ -#undef IKOS_MINI_BOOT //don't run a full booting -#ifdef CONFIG_USE_IKOS -#define CONFIG_USE_VENUS //Faster, 10M CPU and 192k baudrate -#ifdef CONFIG_USE_VENUS -#define IKOS_CPU_SPEED 10000000 -#else -#define IKOS_CPU_SPEED 180000 //IKOS is slow -#endif -#endif //CONFIG_USE_IKOS - -/* 165001:henryhsu:20050603:Source Modify form Bing Tao */ - -#if defined(CONFIG_NET_WIRELESS_SPURS) || defined(CONFIG_NET_WIRELESS_SPURS_MODULE) -#define EBU_PCI_SOFTWARE_ARBITOR -#endif - -#define AMAZON_B11 -#ifdef AMAZON_B11 -#define SWITCH_BUF_FPI_ADDR (0x10110000) -#define SWITCH_BUF_ADDR (KSEG1+SWITCH_BUF_FPI_ADDR) -#define SWITCH_BUF_SIZE (0x2800) -#define AMAZON_B11_CBM_QD_ADDR (SWITCH_BUF_ADDR+0x0) -#define AMAZON_B11_BOND_CELL_ADDR (SWITCH_BUF_ADDR+0x000) -#endif -#define AMAZON_REFERENCE_BOARD -//for AMAZON ATM bonding application -#ifdef AMAZON_REFERENCE_BOARD -#define GPIO_DETECT_LOW -#else -#undef GPIO_DETECT_LOW -#endif - -/* 165001 */ - -#undef AMAZON_IKOS_DEBUG_MSG -#undef AMAZON_INT_DEBUG_MSG -#undef AMAZON_ATM_DEBUG_MSG -#undef AMAZON_DMA_DEBUG_MSG -#undef AMAZON_SW_DEBUG_MSG -#undef AMAZON_WDT_DEBUG_MSG -#undef AMAZON_MTD_DEBUG_MSG -#undef AMAZON_SSC_DEBUG_MSG -#undef AMAZON_MEI_DEBUG_MSG - -#ifdef AMAZON_IKOS_DEBUG_MSG -#define AMAZON_IKOS_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args) -#else -#define AMAZON_IKOS_DMSG(fmt,args...) -#endif - -#ifdef AMAZON_WDT_DEBUG_MSG -#define AMAZON_WDT_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_WDT_DMSG(fm,args...) -#endif - -#ifdef AMAZON_SSC_DEBUG_MSG -#define AMAZON_SSC_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_SSC_DMSG(fm,args...) -#endif - -#ifdef AMAZON_DMA_DEBUG_MSG -#define AMAZON_DMA_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_DMA_DMSG(fm,args...) -#endif - -#ifdef AMAZON_ATM_DEBUG_MSG -#define AMAZON_TPE_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) -#else //not AMAZON_ATM_DEBUG -#define AMAZON_TPE_DMSG(fmt, args...) -#endif //AMAZON_ATM_DEBUG - -#ifdef AMAZON_SW_DEBUG_MSG -#define AMAZON_SW_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_SW_DMSG(fmt,args...) -#endif - -#ifdef AMAZON_MTD_DEBUG_MSG -#define AMAZON_MTD_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_MTD_DMSG(fmt,args...) -#endif - -#ifdef AMAZON_INT_DEBUG_MSG -#define AMAZON_INT_DMSG(x...) printk(x) -#else -#define AMAZON_INT_DMSG(x...) -#endif - -#ifdef AMAZON_MEI_DEBUG_MSG -#define AMAZON_MEI_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args) -#else -#define AMAZON_MEI_DMSG(fmt,args...) -#endif - -#endif //AMAZON_H diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_dma.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_dma.h deleted file mode 100644 index 63ab5924e5..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_dma.h +++ /dev/null @@ -1,148 +0,0 @@ -#ifndef AMAZON_DMA_H -#define AMAZON_DMA_H - -#define RCV_INT 1 -#define TX_BUF_FULL_INT 2 -#define TRANSMIT_CPT_INT 4 - -#define QOS_DEFAULT_WGT 0x7fffffffUL; - - -enum attr_t{ - TX=0, - RX=1, - RESERVED=2, - DEFAULT=3, - -}; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -typedef struct rx_desc{ - u32 data_length:16; - volatile u32 reserved:7; - volatile u32 byte_offset:2; - volatile u32 Burst_length_offset:3; - volatile u32 EoP:1; - volatile u32 Res:1; - volatile u32 C:1; - volatile u32 OWN:1; - volatile u32 Data_Pointer; - /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/ -}_rx_desc; - - -typedef struct tx_desc{ - volatile u32 data_length:16; - volatile u32 reserved1:7; - volatile u32 byte_offset:5; - volatile u32 EoP:1; - volatile u32 SoP:1; - volatile u32 C:1; - volatile u32 OWN:1; - volatile u32 Data_Pointer;//fix me:should be 28 bits here -}_tx_desc; -#else //BIG -typedef struct rx_desc{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 SoP :1; - volatile u32 EoP :1; - volatile u32 Burst_length_offset :3; - volatile u32 byte_offset :2; - volatile u32 reserve :7; - volatile u32 data_length :16; - }field; - - volatile u32 word; - }status; - - volatile u32 Data_Pointer; -}_rx_desc; - - -typedef struct tx_desc{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 SoP :1; - volatile u32 EoP :1; - volatile u32 byte_offset :5; - volatile u32 reserved :7; - volatile u32 data_length :16; - }field; - - volatile u32 word; - }status; - - volatile u32 Data_Pointer; -}_tx_desc; - -#endif //ENDIAN - -struct dma_channel_info{ - /*filled by driver, optional*/ - enum attr_t attr;/*TX or RX*/ - int weight; - int desc_num; - int packet_size; - int control;/*on or off*/ - - int desc_base; - int status; -}; - -typedef struct dma_channel_info _dma_channel_info; - -struct dma_device_info{ - /*variables*/ - /*filled by driver, compulsary*/ - char device_name[15]; - enum attr_t attr;/*default or else*/ - int tx_burst_len; - int rx_burst_len; - - int logic_rx_chan_base; - int logic_tx_chan_base; - u8 on_ch_bit; - /*filled by driver, optional*/ - int weight; - int current_tx_chan; - int current_rx_chan; - int num_tx_chan; - int num_rx_chan; - struct dma_channel_info tx_chan[2]; - struct dma_channel_info rx_chan[4]; - - /*functions, optional*/ - u8* (*buffer_alloc)(int len,int* offset, void** opt); - int (*buffer_free)(u8* dataptr, void* opt); - int (*intr_handler)(struct dma_device_info* info, int status); - /*set by device, clear by dma*/ - int ack; - void * priv; /* used by peripheral driver only */ -}; -typedef struct dma_device_info _dma_device_info; - -int dma_device_register(struct dma_device_info* info); - -int dma_device_unregister(struct dma_device_info* info); - -int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt); - -int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt); - -int dma_device_update(struct dma_device_info* info); - -void dma_device_update_rx(struct dma_device_info* dma_dev); - -void dma_device_update_tx(struct dma_device_info* dma_dev); - -void register_handler_sim(int (*handler)(int)); -#endif /* AMAZON_DMA_H */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei.h deleted file mode 100644 index 6ac8ab310b..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei.h +++ /dev/null @@ -1,220 +0,0 @@ -#ifndef _AMAZON_MEI_H -#define _AMAZON_MEI_H -///////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#include "amazon_mei_app.h" - -#define AMAZON_MEI_DEBUG_ON -#define AMAZON_MEI_CMV_EXTRA - -#define AMAZON_MEI_MAJOR 106 - -/* -** Define where in ME Processor's memory map the Stratify chip lives -*/ -#define MEI_SPACE_ACCESS 0xB0100C00 - -#define MAXSWAPSIZE 8 * 1024 //8k *(32bits) -//#define AMAZON_ADSL_IMAGESIZE 16*1024 // 16k * (32bits) - - -// Mailboxes -#define MSG_LENGTH 16 // x16 bits -#define YES_REPLY 1 -#define NO_REPLY 0 - -#define CMV_TIMEOUT 100 //jiffies -#define MIB_INTERVAL 10000 //msec - -/*** Bit definitions ***/ - -#define FALSE 0 -#define TRUE 1 -#define BIT0 1<<0 -#define BIT1 1<<1 -#define BIT2 1<<2 -#define BIT3 1<<3 -#define BIT4 1<<4 -#define BIT5 1<<5 -#define BIT6 1<<6 -#define BIT7 1<<7 -#define BIT8 1<<8 -#define BIT9 1<<9 -#define BIT10 1<<10 -#define BIT11 1<<11 -#define BIT12 1<<12 -#define BIT13 1<<13 -#define BIT14 1<<14 -#define BIT15 1<<15 -#define BIT16 1<<16 -#define BIT17 1<<17 -#define BIT18 1<<18 -#define BIT19 1<<19 -#define BIT20 1<<20 -#define BIT21 1<<21 -#define BIT22 1<<22 -#define BIT23 1<<23 -#define BIT24 1<<24 -#define BIT25 1<<25 -#define BIT26 1<<26 -#define BIT27 1<<27 -#define BIT28 1<<28 -#define BIT29 1<<29 -#define BIT30 1<<30 -#define BIT31 1<<31 - - -/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ -#define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS) -#define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS) -#define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS) -#define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS) -#define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS) -#define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS) -#define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS) -#define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS) -#define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS) -#define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS) -#define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS) - - -// MEI_TO_ARC_INTERRUPT Register definitions -#define MEI_TO_ARC_INT1 BIT3 -#define MEI_TO_ARC_INT0 BIT2 -#define MEI_TO_ARC_CS_DONE BIT1 -#define MEI_TO_ARC_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT Register definitions -#define ARC_TO_MEI_INT1 BIT8 -#define ARC_TO_MEI_INT0 BIT7 -#define ARC_TO_MEI_CS_REQ BIT6 -#define ARC_TO_MEI_DBG_DONE BIT5 -#define ARC_TO_MEI_MSGACK BIT4 -#define ARC_TO_MEI_NO_ACCESS BIT3 -#define ARC_TO_MEI_CHECK_AAITX BIT2 -#define ARC_TO_MEI_CHECK_AAIRX BIT1 -#define ARC_TO_MEI_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT_MASK Register definitions -#define GP_INT1_EN BIT8 -#define GP_INT0_EN BIT7 -#define CS_REQ_EN BIT6 -#define DBG_DONE_EN BIT5 -#define MSGACK_EN BIT4 -#define NO_ACC_EN BIT3 -#define AAITX_EN BIT2 -#define AAIRX_EN BIT1 -#define MSGAV_EN BIT0 - -// MEI_CONTROL Register definitions -#define INT_LEVEL BIT2 -#define SOFT_RESET BIT1 -#define HOST_MSTR BIT0 - -// MEI_DEBUG_DECODE Register definitions -#define MEI_DEBUG_DEC_MASK (0x3) -#define MEI_DEBUG_DEC_AUX_MASK (0x0) -#define MEI_DEBUG_DEC_DMP1_MASK (0x1) -#define MEI_DEBUG_DEC_DMP2_MASK (0x2) -#define MEI_DEBUG_DEC_CORE_MASK (0x3) - - -// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate -// page swap requests. -#define MEI_TO_ARC_MAILBOX (0x15FC0) -#define MEI_TO_ARC_MAILBOXR (0x15FEC) -#define ARC_TO_MEI_MAILBOX (0x15F90) -#define ARC_MEI_MAILBOXR (0x15FBC) - -// Codeswap request messages are indicated by setting BIT31 -#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000) - -/* -** Swap page header -*/ -// Page must be loaded at boot time if size field has BIT31 set -#define BOOT_FLAG (BIT31) -#define BOOT_FLAG_MASK ~BOOT_FLAG - -// Swap page header describes size in 32-bit words, load location, and image offset -// for program and/or data segments -typedef struct _arc_swp_page_hdr -{ - u32 p_offset; // Offset bytes of progseg from beginning of image - u32 p_dest; // Destination addr of progseg on processor - u32 p_size; // Size in 32-bitwords of program segment - u32 d_offset; // Offset bytes of dataseg from beginning of image - u32 d_dest; // Destination addr of dataseg on processor - u32 d_size; // Size in 32-bitwords of data segment -}ARC_SWP_PAGE_HDR; - - -/* -** Swap image header -*/ -#define GET_PROG 0 // Flag used for program mem segment -#define GET_DATA 1 // Flag used for data mem segment - -// Image header contains size of image, checksum for image, and count of -// page headers. Following that are 'count' page headers followed by -// the code and/or data segments to be loaded -typedef struct _arc_img_hdr -{ - u32 size; // Size of binary image in bytes - u32 checksum; // Checksum for image - u32 count; // Count of swp pages in image - ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy -}ARC_IMG_HDR; - - - -/* -** Native size for the Stratiphy interface is 32-bits. All reads and writes -** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or -** byte data. Read routines are provided. Write routines are probably a bad idea, as the -** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle -** could very well have unintended results. -*/ -MEI_ERROR meiCMV(u16 *, int); // first arg is CMV to ARC, second to indicate whether need reply - -void meiLongwordWrite(u32 ul_address, u32 ul_data); -void meiLongwordRead(u32 ul_address, u32 *pul_data); - - -MEI_ERROR meiDMAWrite(u32 destaddr, u32 *databuff, u32 databuffsize); -MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize); - -MEI_ERROR meiDMARead(u32 srcaddr, u32 *databuff, u32 databuffsize); -MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize); - -void meiPollForDbgDone(void); - -void meiMailboxInterruptsDisable(void); -void meiMailboxInterruptsEnable(void); - -MEI_ERROR meiMailboxWrite(u16 *msgsrcbuffer, u16 msgsize); -MEI_ERROR meiMailboxRead(u16 *msgdestbuffer, u16 msgsize); - -int meiGetPage( u32 Page, u32 data, u32 MaxSize, u32 *Buffer, u32 *Dest); - -MEI_ERROR meiHaltArc(void); -MEI_ERROR meiRunArc(void); - -MEI_ERROR meiDownloadBootCode(void); - -MEI_ERROR meiForceRebootAdslModem(void); - -void makeCMV(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data); - -#endif - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app.h deleted file mode 100644 index 89700d9d76..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app.h +++ /dev/null @@ -1,54 +0,0 @@ -//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl - -#ifndef _AMAZON_MEI_APP_H -#define _AMAZON_MEI_APP_H - -///////////////////////////////////////////////////////////////////////////////////////////////////// - - // ioctl control -#define AMAZON_MEI_START 300 -#define AMAZON_MEI_REPLY 301 -#define AMAZON_MEI_NOREPLY 302 - -#define AMAZON_MEI_RESET 303 -#define AMAZON_MEI_REBOOT 304 -#define AMAZON_MEI_HALT 305 -#define AMAZON_MEI_CMV_WINHOST 306 -#define AMAZON_MEI_CMV_READ 307 -#define AMAZON_MEI_CMV_WRITE 308 -#define AMAZON_MEI_MIB_DAEMON 309 -#define AMAZON_MEI_SHOWTIME 310 -#define AMAZON_MEI_REMOTE 311 -#define AMAZON_MEI_READDEBUG 312 -#define AMAZON_MEI_WRITEDEBUG 313 -#define AMAZON_MEI_LOP 314 - -#define AMAZON_MEI_PCM_SETUP 315 -#define AMAZON_MEI_PCM_START_TIMER 316 -#define AMAZON_MEI_PCM_STOP_TIMER 317 -#define AMAZON_MEI_PCM_CHECK 318 -#define AMAZON_MEI_GET_EOC_LEN 319 -#define AMAZON_MEI_GET_EOC_DATA 320 -#define AMAZON_MEI_PCM_GETDATA 321 -#define AMAZON_MEI_PCM_GPIO 322 -#define AMAZON_MEI_EOC_SEND 323 -//MIB -#define AMAZON_MIB_LO_ATUC 324 -#define AMAZON_MIB_LO_ATUR 325 -#define AMAZON_MEI_DOWNLOAD 326 - -#define AMAZON_MEI_DEBUG_MODE 327 //509221:tc.chen -#define LOOP_DIAGNOSTIC_MODE_COMPLETE 328 - - -/*** Enums ***/ -typedef enum mei_error -{ - MEI_SUCCESS = 0, - MEI_FAILURE = -1, - MEI_MAILBOX_FULL = -2, - MEI_MAILBOX_EMPTY = -3, - MEI_MAILBOX_TIMEOUT = -4, -}MEI_ERROR; - -#endif diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app_ioctl.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app_ioctl.h deleted file mode 100644 index d98f60b171..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app_ioctl.h +++ /dev/null @@ -1,1169 +0,0 @@ -// 603221:tc.chen 2006/03/21 added APIs to support the WEB related parameters for ADSL Statistics - -#ifndef __AMAZON_MEI_APP_IOCTL_H -#define __AMAZON_MEI_APP_IOCTL_H - -#ifdef __KERNEL__ -#include "amazon_mei_ioctl.h" -#endif - -/* Interface Name */ -//#define INTERFACE_NAME - -/* adslLineTable constants */ -#define GET_ADSL_LINE_CODE 1 - -/* adslAtucPhysTable constants */ -#define GET_ADSL_ATUC_PHY 4 - -/* adslAturPhysTable constants */ -#define GET_ADSL_ATUR_PHY 10 - -/* adslAtucChanTable constants */ -#define GET_ADSL_ATUC_CHAN_INFO 15 - -/* adslAturChanTable constants */ -#define GET_ADSL_ATUR_CHAN_INFO 18 - -/* adslAtucPerfDataTable constants */ -#define GET_ADSL_ATUC_PERF_DATA 21 - -/* adslAturPerfDataTable constants */ -#define GET_ADSL_ATUR_PERF_DATA 40 - -/* adslAtucIntervalTable constants */ -#define GET_ADSL_ATUC_INTVL_INFO 60 - -/* adslAturIntervalTable constants */ -#define GET_ADSL_ATUR_INTVL_INFO 65 - -/* adslAtucChanPerfDataTable constants */ -#define GET_ADSL_ATUC_CHAN_PERF_DATA 70 - -/* adslAturChanPerfDataTable constants */ -#define GET_ADSL_ATUR_CHAN_PERF_DATA 90 - -/* adslAtucChanIntervalTable constants */ -#define GET_ADSL_ATUC_CHAN_INTVL_INFO 110 - -/* adslAturChanIntervalTable constants */ -#define GET_ADSL_ATUR_CHAN_INTVL_INFO 115 - -/* adslLineAlarmConfProfileTable constants */ -#define GET_ADSL_ALRM_CONF_PROF 120 -#define SET_ADSL_ALRM_CONF_PROF 121 - -/* adslAturTrap constants */ -#define ADSL_ATUR_TRAPS 135 - -////////////////// RFC-3440 ////////////// - -#ifdef AMAZON_MEI_MIB_RFC3440 -/* adslLineExtTable */ -#define GET_ADSL_ATUC_LINE_EXT 201 -#define SET_ADSL_ATUC_LINE_EXT 203 - -/* adslAtucPerfDateExtTable */ -#define GET_ADSL_ATUC_PERF_DATA_EXT 205 - -/* adslAtucIntervalExtTable */ -#define GET_ADSL_ATUC_INTVL_EXT_INFO 221 - -/* adslAturPerfDataExtTable */ -#define GET_ADSL_ATUR_PERF_DATA_EXT 225 - -/* adslAturIntervalExtTable */ -#define GET_ADSL_ATUR_INTVL_EXT_INFO 233 - -/* adslAlarmConfProfileExtTable */ -#define GET_ADSL_ALRM_CONF_PROF_EXT 235 -#define SET_ADSL_ALRM_CONF_PROF_EXT 236 - -/* adslAturExtTrap */ -#define ADSL_ATUR_EXT_TRAPS 240 - -#endif - -// 603221:tc.chen start -/* The following constants are added to support the WEB related ADSL Statistics */ - -/* adslLineStatus constants */ -#define GET_ADSL_LINE_STATUS 245 - -/* adslLineRate constants */ -#define GET_ADSL_LINE_RATE 250 - -/* adslLineInformation constants */ -#define GET_ADSL_LINE_INFO 255 - -/* adslNearEndPerformanceStats constants */ -#define GET_ADSL_NEAREND_STATS 270 - -/* adslFarEndPerformanceStats constants */ -#define GET_ADSL_FAREND_STATS 290 - -// 603221:tc.chen end - -/* Loop diagnostics mode of the ADSL line related constants */ -#define GET_ADSL_LOOP_DIAGNOSTICS_MODE 295 -#define SET_ADSL_LOOP_DIAGNOSTICS_MODE 296 -#define IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE 299 - -/* Sub-carrier related parameters */ -#define GET_ADSL_ATUC_SUBCARRIER_STATS 297 -#define GET_ADSL_ATUR_SUBCARRIER_STATS 298 -#define GET_ADSL_LINE_INIT_STATS 150 -#define GET_ADSL_POWER_SPECTRAL_DENSITY 151 - - -/////////////////////////////////////////////////////////// -// makeCMV(Opcode, Group, Address, Index, Size, Data) - -/* adslLineCode Flags */ -#define LINE_CODE_FLAG 0x1 /* BIT 0th position */ - -/* adslAtucPhysTable Flags */ -#define ATUC_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 57, 0, 12, data) -#define ATUC_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 57, 12, 4, data) - -#define ATUC_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */ -#define ATUC_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 64, 0, 4, data) - -#define ATUC_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */ -#define ATUC_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 58, 0, 8, data) - -#define ATUC_CURR_STAT_FLAG 0x8 /* BIT 3 */ - -#define ATUC_CURR_OUT_PWR_FLAG 0x10 /* BIT 4 */ -#define ATUC_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 5, 1, data) - -#define ATUC_CURR_ATTR_FLAG 0x20 /* BIT 5 */ -#define ATUC_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 0, 2, data) - - -/* adslAturPhysTable Flags */ -#define ATUR_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */ -#define ATUR_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 62, 0, 12, data) -#define ATUR_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 62, 12, 4, data) - -#define ATUR_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */ -#define ATUR_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 65, 0, 4, data) - -#define ATUR_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */ -#define ATUR_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 61, 0, 8, data) - -#define ATUR_SNRMGN_FLAG 0x8 -#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 1, data) - -#define ATUR_ATTN_FLAG 0x10 -#define ATUR_ATTN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data) - -#define ATUR_CURR_STAT_FLAG 0x20 /* BIT 3 */ - -#define ATUR_CURR_OUT_PWR_FLAG 0x40 /* BIT 4 */ -#define ATUR_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 5, 1, data) - -#define ATUR_CURR_ATTR_FLAG 0x80 /* BIT 5 */ -#define ATUR_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 0, 2, data) - -/* adslAtucChanTable Flags */ -#define ATUC_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */ -#define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 1, 1, data) - -#define ATUC_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */ -#define ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data) - -#define ATUC_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */ - -/* adslAturChanTable Flags */ -#define ATUR_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */ -#define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 2, 1, 1, data) - -#define ATUR_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */ -#define ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data) - -#define ATUR_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */ - -#define ATUR_CHAN_CRC_BLK_LEN_FLAG 0x8 /* BIT 3 */ - -/* adslAtucPerfDataTable Flags */ -#define ATUC_PERF_LOFS_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PERF_LOSS_FLAG 0x2 /* BIT 1 */ -#define ATUC_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data) -#define ATUC_PERF_ESS_FLAG 0x4 /* BIT 2 */ -#define ATUC_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data) -#define ATUC_PERF_INITS_FLAG 0x8 /* BIT 3 */ -#define ATUC_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */ -#define ATUC_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */ -#define ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUC_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */ -#define ATUC_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */ -#define ATUC_PERF_CURR_15MIN_ESS_FLAG 0x200 /* BIT 9 */ -#define ATUC_PERF_CURR_15MIN_INIT_FLAG 0x400 /* BIT 10 */ -#define ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ -#define ATUC_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */ -#define ATUC_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */ -#define ATUC_PERF_CURR_1DAY_ESS_FLAG 0x4000 /* BIT 14 */ -#define ATUC_PERF_CURR_1DAY_INIT_FLAG 0x8000 /* BIT 15 */ -#define ATUC_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUC_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */ -#define ATUC_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */ -#define ATUC_PERF_PREV_1DAY_ESS_FLAG 0x80000 /* BIT 19 */ -#define ATUC_PERF_PREV_1DAY_INITS_FLAG 0x100000 /* BIT 20 */ - -/* adslAturPerfDataTable Flags */ -#define ATUR_PERF_LOFS_FLAG 0x1 /* BIT 0th position */ -#define ATUR_PERF_LOSS_FLAG 0x2 /* BIT 1 */ -#define ATUR_PERF_LPR_FLAG 0x4 /* BIT 2 */ -#define ATUR_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data) -#define ATUR_PERF_ESS_FLAG 0x8 /* BIT 3 */ -#define ATUR_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data) -#define ATUR_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */ -#define ATUR_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */ -#define ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUR_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */ -#define ATUR_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */ -#define ATUR_PERF_CURR_15MIN_LPR_FLAG 0x200 /* BIT 9 */ -#define ATUR_PERF_CURR_15MIN_ESS_FLAG 0x400 /* BIT 10 */ -#define ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ -#define ATUR_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */ -#define ATUR_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */ -#define ATUR_PERF_CURR_1DAY_LPR_FLAG 0x4000 /* BIT 14 */ -#define ATUR_PERF_CURR_1DAY_ESS_FLAG 0x8000 /* BIT 15 */ -#define ATUR_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUR_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */ -#define ATUR_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */ -#define ATUR_PERF_PREV_1DAY_LPR_FLAG 0x80000 /* BIT 19 */ -#define ATUR_PERF_PREV_1DAY_ESS_FLAG 0x100000 /* BIT 20 */ - -/* adslAtucIntervalTable Flags */ -#define ATUC_INTVL_LOF_FLAG 0x1 /* BIT 0th position */ -#define ATUC_INTVL_LOS_FLAG 0x2 /* BIT 1 */ -#define ATUC_INTVL_ESS_FLAG 0x4 /* BIT 2 */ -#define ATUC_INTVL_INIT_FLAG 0x8 /* BIT 3 */ -#define ATUC_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */ - -/* adslAturIntervalTable Flags */ -#define ATUR_INTVL_LOF_FLAG 0x1 /* BIT 0th position */ -#define ATUR_INTVL_LOS_FLAG 0x2 /* BIT 1 */ -#define ATUR_INTVL_LPR_FLAG 0x4 /* BIT 2 */ -#define ATUR_INTVL_ESS_FLAG 0x8 /* BIT 3 */ -#define ATUR_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */ - -/* adslAtucChanPerfDataTable Flags */ -#define ATUC_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */ -#define ATUC_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */ -#define ATUC_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */ -#define ATUC_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */ -#define ATUC_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */ -#define ATUC_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */ -#define ATUC_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUC_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */ -#define ATUC_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */ -#define ATUC_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */ -#define ATUC_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */ -#define ATUC_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11*/ -#define ATUC_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */ -#define ATUC_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */ -#define ATUC_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */ -#define ATUC_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */ -#define ATUC_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUC_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */ -#define ATUC_CHAN_PERF_PREV_1DAY_TX_BLK_FLAG 0x40000 /* BIT 18 */ -#define ATUC_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */ -#define ATUC_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */ - - -/* adslAturChanPerfDataTable Flags */ -#define ATUR_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */ -#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data) -#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data) -#define ATUR_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */ -#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data) -#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data) -#define ATUR_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */ -#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data) -#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data) -#define ATUR_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */ -#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data) -#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data) -#define ATUR_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */ -#define ATUR_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */ -#define ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */ -#define ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */ -#define ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */ -#define ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */ -#define ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ -#define ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */ -#define ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */ -#define ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */ -#define ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */ -#define ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */ -#define ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG 0x40000 /* BIT 18 */ -#define ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */ -#define ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */ - -/* adslAtucChanIntervalTable Flags */ -#define ATUC_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th position */ -#define ATUC_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */ -#define ATUC_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */ -#define ATUC_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */ -#define ATUC_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */ -#define ATUC_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */ - -/* adslAturChanIntervalTable Flags */ -#define ATUR_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th Position */ -#define ATUR_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */ -#define ATUR_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */ -#define ATUR_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */ -#define ATUR_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */ -#define ATUR_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */ - -/* adslLineAlarmConfProfileTable Flags */ -#define ATUC_THRESH_15MIN_LOFS_FLAG 0x01 /* BIT 0th position */ -#define ATUC_THRESH_15MIN_LOSS_FLAG 0x02 /* BIT 1 */ -#define ATUC_THRESH_15MIN_ESS_FLAG 0x04 /* BIT 2 */ -#define ATUC_THRESH_FAST_RATEUP_FLAG 0x08 /* BIT 3 */ -#define ATUC_THRESH_INTERLEAVE_RATEUP_FLAG 0x10 /* BIT 4 */ -#define ATUC_THRESH_FAST_RATEDOWN_FLAG 0x20 /* BIT 5 */ -#define ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x40 /* BIT 6 */ -#define ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG 0x80 /* BIT 7 */ -#define ATUR_THRESH_15MIN_LOFS_FLAG 0x100 /* BIT 8 */ -#define ATUR_THRESH_15MIN_LOSS_FLAG 0x200 /* BIT 9 */ -#define ATUR_THRESH_15MIN_LPRS_FLAG 0x400 /* BIT 10 */ -#define ATUR_THRESH_15MIN_ESS_FLAG 0x800 /* BIT 11 */ -#define ATUR_THRESH_FAST_RATEUP_FLAG 0x1000 /* BIT 12 */ -#define ATUR_THRESH_INTERLEAVE_RATEUP_FLAG 0x2000 /* BIT 13 */ -#define ATUR_THRESH_FAST_RATEDOWN_FLAG 0x4000 /* BIT 14 */ -#define ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x8000 /* BIT 15 */ -#define LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG 0x10000 /* BIT 16 */ - - -/* adslAturTraps Flags */ -#define ATUC_PERF_LOFS_THRESH_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PERF_LOSS_THRESH_FLAG 0x2 /* BIT 1 */ -#define ATUC_PERF_ESS_THRESH_FLAG 0x4 /* BIT 2 */ -#define ATUC_RATE_CHANGE_FLAG 0x8 /* BIT 3 */ -#define ATUR_PERF_LOFS_THRESH_FLAG 0x10 /* BIT 4 */ -#define ATUR_PERF_LOSS_THRESH_FLAG 0x20 /* BIT 5 */ -#define ATUR_PERF_LPRS_THRESH_FLAG 0x40 /* BIT 6 */ -#define ATUR_PERF_ESS_THRESH_FLAG 0x80 /* BIT 7 */ -#define ATUR_RATE_CHANGE_FLAG 0x100 /* BIT 8 */ - -//RFC- 3440 FLAG DEFINITIONS - -#ifdef AMAZON_MEI_MIB_RFC3440 -/* adslLineExtTable flags */ -#define ATUC_LINE_TRANS_CAP_FLAG 0x1 /* BIT 0th position */ -#define ATUC_LINE_TRANS_CAP_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data) -#define ATUC_LINE_TRANS_CONFIG_FLAG 0x2 /* BIT 1 */ -#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data) -#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR makeCMV(H2D_CMV_WRITE,INFO, 67, 0, 1, data) -#define ATUC_LINE_TRANS_ACTUAL_FLAG 0x4 /* BIT 2 */ -#define ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 1, 0, 1, data) -#define LINE_GLITE_POWER_STATE_FLAG 0x8 /* BIT 3 */ -#define LINE_GLITE_POWER_STATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 0, 0, 1, data) - -/* adslAtucPerfDataExtTable flags */ -#define ATUC_PERF_STAT_FASTR_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PERF_STAT_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data) -#define ATUC_PERF_STAT_FAILED_FASTR_FLAG 0x2 /* BIT 1 */ -#define ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data) -#define ATUC_PERF_STAT_SESL_FLAG 0X4 /* BIT 2 */ -#define ATUC_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data) -#define ATUC_PERF_STAT_UASL_FLAG 0X8 /* BIT 3 */ -#define ATUC_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data) -#define ATUC_PERF_CURR_15MIN_FASTR_FLAG 0X10 /* BIT 4 */ -#define ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG 0X20 /* BIT 5 */ -#define ATUC_PERF_CURR_15MIN_SESL_FLAG 0X40 /* BIT 6 */ -#define ATUC_PERF_CURR_15MIN_UASL_FLAG 0X80 /* BIT 7 */ -#define ATUC_PERF_CURR_1DAY_FASTR_FLAG 0X100 /* BIT 8 */ -#define ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG 0X200 /* BIT 9 */ -#define ATUC_PERF_CURR_1DAY_SESL_FLAG 0X400 /* BIT 10 */ -#define ATUC_PERF_CURR_1DAY_UASL_FLAG 0X800 /* BIT 11 */ -#define ATUC_PERF_PREV_1DAY_FASTR_FLAG 0X1000 /* BIT 12 */ -#define ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG 0X2000 /* BIT 13 */ -#define ATUC_PERF_PREV_1DAY_SESL_FLAG 0X4000 /* BIT 14 */ -#define ATUC_PERF_PREV_1DAY_UASL_FLAG 0X8000 /* BIT 15 */ - -/* adslAturPerfDataExtTable */ -#define ATUR_PERF_STAT_SESL_FLAG 0X1 /* BIT 0th position */ -#define ATUR_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data) -#define ATUR_PERF_STAT_UASL_FLAG 0X2 /* BIT 1 */ -#define ATUR_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data) -#define ATUR_PERF_CURR_15MIN_SESL_FLAG 0X4 /* BIT 2 */ -#define ATUR_PERF_CURR_15MIN_UASL_FLAG 0X8 /* BIT 3 */ -#define ATUR_PERF_CURR_1DAY_SESL_FLAG 0X10 /* BIT 4 */ -#define ATUR_PERF_CURR_1DAY_UASL_FLAG 0X20 /* BIT 5 */ -#define ATUR_PERF_PREV_1DAY_SESL_FLAG 0X40 /* BIT 6 */ -#define ATUR_PERF_PREV_1DAY_UASL_FLAG 0X80 /* BIT 7 */ - -/* adslAutcIntervalExtTable flags */ -#define ATUC_INTERVAL_FASTR_FLAG 0x1 /* Bit 0 */ -#define ATUC_INTERVAL_FAILED_FASTR_FLAG 0x2 /* Bit 1 */ -#define ATUC_INTERVAL_SESL_FLAG 0x4 /* Bit 2 */ -#define ATUC_INTERVAL_UASL_FLAG 0x8 /* Bit 3 */ - -/* adslAturIntervalExtTable */ -#define ATUR_INTERVAL_SESL_FLAG 0X1 /* BIT 0th position */ -#define ATUR_INTERVAL_UASL_FLAG 0X2 /* BIT 1 */ - -/* adslAlarmConfProfileExtTable */ -#define ATUC_THRESH_15MIN_FAILED_FASTR_FLAG 0X1/* BIT 0th position */ -#define ATUC_THRESH_15MIN_SESL_FLAG 0X2 /* BIT 1 */ -#define ATUC_THRESH_15MIN_UASL_FLAG 0X4 /* BIT 2 */ -#define ATUR_THRESH_15MIN_SESL_FLAG 0X8 /* BIT 3 */ -#define ATUR_THRESH_15MIN_UASL_FLAG 0X10 /* BIT 4 */ - -/* adslAturExtTraps */ -#define ATUC_15MIN_FAILED_FASTR_TRAP_FLAG 0X1 /* BIT 0th position */ -#define ATUC_15MIN_SESL_TRAP_FLAG 0X2 /* BIT 1 */ -#define ATUC_15MIN_UASL_TRAP_FLAG 0X4 /* BIT 2 */ -#define ATUR_15MIN_SESL_TRAP_FLAG 0X8 /* BIT 3 */ -#define ATUR_15MIN_UASL_TRAP_FLAG 0X10 /* BIT 4 */ - -// 603221:tc.chen start -/* adslLineStatus Flags */ -#define LINE_STAT_MODEM_STATUS_FLAG 0x1 /* BIT 0th position */ -#define LINE_STAT_MODEM_STATUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data) -#define LINE_STAT_MODE_SEL_FLAG 0x2 /* BIT 1 */ -#define LINE_STAT_MODE_SEL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data) -#define LINE_STAT_TRELLCOD_ENABLE_FLAG 0x4 /* BIT 2 */ -#define LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, OPTN, 2, 0, 1, data) -#define LINE_STAT_LATENCY_FLAG 0x8 /* BIT 3 */ -#define LINE_STAT_LATENCY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 12, 0, 1, data) - -/* adslLineRate Flags */ -#define LINE_RATE_DATA_RATEDS_FLAG 0x1 /* BIT 0th position */ -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 2, 2, data) - - -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 0, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 0, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 0, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 0, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 0, 2, data) - -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 1, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 1, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 1, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 1, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 2, 2, data) - -#define LINE_RATE_DATA_RATEUS_FLAG 0x2 /* BIT 1 */ -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 2, 2, data) - - -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 0, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 0, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 0, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 0, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 0, 2, data) - -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 1, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 1, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 1, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 1, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 2, 2, data) - -#define LINE_RATE_ATTNDRDS_FLAG 0x4 /* BIT 2 */ -#define LINE_RATE_ATTNDRDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 2, data) - -#define LINE_RATE_ATTNDRUS_FLAG 0x8 /* BIT 3 */ -#define LINE_RATE_ATTNDRUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 4, 2, data) - -/* adslLineInformation Flags */ -#define LINE_INFO_INTLV_DEPTHDS_FLAG 0x1 /* BIT 0th position */ -#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 0, 1, data) -#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 1, 1, data) -#define LINE_INFO_INTLV_DEPTHUS_FLAG 0x2 /* BIT 1 */ -#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 0, 1, data) -#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 1, 1, data) -#define LINE_INFO_LATNDS_FLAG 0x4 /* BIT 2 */ -#define LINE_INFO_LATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 1, 1, data) -#define LINE_INFO_LATNUS_FLAG 0x8 /* BIT 3 */ -#define LINE_INFO_LATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 1, 1, data) -#define LINE_INFO_SATNDS_FLAG 0x10 /* BIT 4 */ -#define LINE_INFO_SATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data) -#define LINE_INFO_SATNUS_FLAG 0x20 /* BIT 5 */ -#define LINE_INFO_SATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 2, 1, data) -#define LINE_INFO_SNRMNDS_FLAG 0x40 /* BIT 6 */ -#define LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 3, 1, data) -#define LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 0, 1, data) -#define LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 46, 0, 1, data) -#define LINE_INFO_SNRMNUS_FLAG 0x80 /* BIT 7 */ -#define LINE_INFO_SNRMNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 3, 1, data) -#define LINE_INFO_ACATPDS_FLAG 0x100 /* BIT 8 */ -#define LINE_INFO_ACATPDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 6, 1, data) -#define LINE_INFO_ACATPUS_FLAG 0x200 /* BIT 9 */ -#define LINE_INFO_ACATPUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 6, 1, data) - -/* adslNearEndPerformanceStats Flags */ -#define NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data) -#define NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data) -#define NEAREND_PERF_SUPERFRAME_FLAG 0x1 /* BIT 0th position */ -#define NEAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data) -#define NEAREND_PERF_LOS_FLAG 0x2 /* BIT 1 */ -#define NEAREND_PERF_LOF_FLAG 0x4 /* BIT 2 */ -#define NEAREND_PERF_LPR_FLAG 0x8 /* BIT 3 */ -#define NEAREND_PERF_NCD_FLAG 0x10 /* BIT 4 */ -#define NEAREND_PERF_LCD_FLAG 0x20 /* BIT 5 */ -#define NEAREND_PERF_CRC_FLAG 0x40 /* BIT 6 */ -#define NEAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data) -#define NEAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data) -#define NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data) -#define NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data) -#define NEAREND_PERF_RSCORR_FLAG 0x80 /* BIT 7 */ -#define NEAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 6, 0, 1, data) -#define NEAREND_PERF_FECS_FLAG 0x100 /* BIT 8 */ -#define NEAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data) -#define NEAREND_PERF_ES_FLAG 0x200 /* BIT 9 */ -#define NEAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data) -#define NEAREND_PERF_SES_FLAG 0x400 /* BIT 10 */ -#define NEAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 9, 0, 1, data) -#define NEAREND_PERF_LOSS_FLAG 0x800 /* BIT 11 */ -#define NEAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data) -#define NEAREND_PERF_UAS_FLAG 0x1000 /* BIT 12 */ -#define NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 0, 2, data) -#define NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 2, 2, data) -#define NEAREND_PERF_HECERR_FLAG 0x2000 /* BIT 13 */ - -/* adslFarEndPerformanceStats Flags */ -#define FAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data) -#define FAREND_PERF_LOS_FLAG 0x1 /* BIT 0th position */ -#define FAREND_PERF_LOF_FLAG 0x2 /* BIT 1 */ -#define FAREND_PERF_LPR_FLAG 0x4 /* BIT 2 */ -#define FAREND_PERF_NCD_FLAG 0x8 /* BIT 3 */ -#define FAREND_PERF_LCD_FLAG 0x10 /* BIT 4 */ -#define FAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 0, 1, data) -#define FAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 1, 1, data) -#define FAREND_PERF_CRC_FLAG 0x20 /* BIT 5 */ -#define FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 0, 1, data) -#define FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 1, 1, data) -#define FAREND_PERF_RSCORR_FLAG 0x40 /* BIT 6 */ -#define FAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 32, 0, 1, data) -#define FAREND_PERF_FECS_FLAG 0x80 /* BIT 7 */ -#define FAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data) -#define FAREND_PERF_ES_FLAG 0x100 /* BIT 8 */ -#define FAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data) -#define FAREND_PERF_SES_FLAG 0x200 /* BIT 9 */ -#define FAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 35, 0, 1, data) -#define FAREND_PERF_LOSS_FLAG 0x400 /* BIT 10 */ -#define FAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data) -#define FAREND_PERF_UAS_FLAG 0x800 /* BIT 11 */ -#define FAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 0, 2, data) -#define FAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 2, 2, data) -#define FAREND_PERF_HECERR_FLAG 0x1000 /* BIT 12 */ -// 603221:tc.chen end -/* TR-69 related additional parameters - defines */ -/* Defines for struct adslATURSubcarrierInfo */ -#define NEAREND_HLINSC 0x1 -#define NEAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 71, 2, 1, data) -#define NEAREND_HLINPS 0x2 -#define NEAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 73, idx, size, data) -#define NEAREND_HLOGMT 0x4 -#define NEAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 0, 1, data) -#define NEAREND_HLOGPS 0x8 -#define NEAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 75, idx, size, data) -#define NEAREND_QLNMT 0x10 -#define NEAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 1, 1, data) -#define NEAREND_QLNPS 0x20 -#define NEAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 77, idx, size, data) -#define NEAREND_SNRMT 0x40 -#define NEAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 2, 1, data) -#define NEAREND_SNRPS 0x80 -#define NEAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 78, idx, size, data) -#define NEAREND_BITPS 0x100 -#define NEAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 22, idx, size, data) -#define NEAREND_GAINPS 0x200 -#define NEAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 24, idx, size, data) - -/* Defines for struct adslATUCSubcarrierInfo */ -#define FAREND_HLINSC 0x1 -#define FAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 70, 0, 1, data) -#define FAREND_HLINPS 0x2 -#define FAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 72, idx, size, data) -#define FAREND_HLOGMT 0x4 -#define FAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 0, 1, data) -#define FAREND_HLOGPS 0x8 -#define FAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 74, idx, size, data) -#define FAREND_QLNMT 0x10 -#define FAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 1, 1, data) -#define FAREND_QLNPS 0x20 -#define FAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 76, idx, size, data) -#define FAREND_SNRMT 0x40 -#define FAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 2, 1, data) -#define FAREND_SNRPS 0x80 -#define FAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 10, idx, size, data) -#define FAREND_BITPS 0x100 -#define FAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 23, idx, size, data) -#define FAREND_GAINPS 0x200 -#define FAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 25, idx, size, data) - - -// GET_ADSL_POWER_SPECTRAL_DENSITY -#define NOMPSD_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 0, 1, data) -#define NOMPSD_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 1, 1, data) -#define PCB_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 6, 1, data) -#define PCB_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 7, 1, data) -#define RMSGI_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 10, 1, data) -#define RMSGI_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 11, 1, data) - - -#endif -/////////////////////////////////////////////////Macro Definitions ? FLAG Setting & Testing - -#define SET_FLAG(flags, flag_val) ((*flags) = ((*flags) | flag_val)) -// -- This macro sets the flags with the flag_val. Here flags is passed as a pointer - -#define IS_FLAG_SET(flags, test_flag) (((*flags) & (test_flag)) == (test_flag)? test_flag:0) -// -- This macro verifies whether test_flag has been set in flags. Here flags is passed as a pointer - - -#define CLR_FLAG(flags, flag_bit) ((*flags) = (*flags) & (~flag_bit)) -// -- This macro resets the specified flag_bit in the flags. Here flags is passed as a pointer - - -////////////////////////////////////////////////DATA STRUCTURES ORGANIZATION - -//Here are the data structures used for accessing mib parameters. The ioctl call includes the third parameter as a void pointer. This parameter has to be type-casted in the driver code to the corresponding structure depending upon the command type. For Ex: consider the ioctl used to get the adslLineCode type, ioctl(fd,GET_ADSL_LINE_CODE,void *struct_adslLineTableEntry). In the driver code we check on the type of the command, i.e GET_ADSL_LINE_CODE and type-cast the void pointer to struct adslLineTableEntry type. - // -#define u32 unsigned int -#define u16 unsigned short -#define s16 short -#define u8 unsigned char - - -typedef u32 AdslPerfTimeElapsed; -typedef u32 AdslPerfPrevDayCount; -typedef u32 PerfCurrentCount; -typedef u32 PerfIntervalCount; -typedef u32 AdslPerfCurrDayCount; - - -//ioctl(int fd, GET_ADSL_LINE_CODE, void *struct_adslLineTableEntry) - -typedef struct adslLineTableEntry { - int ifIndex; - int adslLineCode; - u8 flags; -} adslLineTableEntry; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct adslLineExtTableEntry { - int ifIndex; - u16 adslLineTransAtucCap; - u16 adslLineTransAtucConfig; - u16 adslLineTransAtucActual; - int adslLineGlitePowerState; - u32 flags; -}adslLineExtTableEntry; -#endif -//ioctl(int fd, GET_ADSL_ATUC_PHY, void *struct_adslAtucPhysEntry) - -typedef struct adslVendorId { - u16 country_code; - u_char provider_id[4]; /* Ascii characters */ - u_char revision_info[2]; -}adslVendorId; - - -typedef struct adslAtucPhysEntry { - int ifIndex; - char serial_no[32]; - union { - char vendor_id[16]; - adslVendorId vendor_info; - } vendor_id; - - char version_no[16]; - u32 status; - int outputPwr; - u32 attainableRate; - u8 flags; -} adslAtucPhysEntry; - - -//ioctl(int fd, GET_ADSL_ATUR_PHY, void *struct_adslAturPhysEntry) - -typedef struct adslAturPhysEntry { - int ifIndex; - char serial_no[32]; - union { - char vendor_id[16]; - adslVendorId vendor_info; - } vendor_id; - char version_no[16]; - int SnrMgn; - u32 Attn; - u32 status; - int outputPwr; - u32 attainableRate; - u8 flags; -} adslAturPhysEntry; - - -//ioctl(int fd, GET_ADSL_ATUC_CHAN_INFO, void *struct_adslAtucChanInfo) - -typedef struct adslAtucChanInfo { - int ifIndex; - u32 interleaveDelay; - u32 currTxRate; - u32 prevTxRate; - u8 flags; -} adslAtucChanInfo; - - -//ioctl(int fd, GET_ADSL_ATUR_CHAN_INFO, void *struct_adslAturChanInfo) - -typedef struct adslAturChanInfo { - int ifIndex; - u32 interleaveDelay; - u32 currTxRate; - u32 prevTxRate; - u32 crcBlkLen; - u8 flags; -} adslAturChanInfo; - - -//ioctl(int fd, GET_ADSL_ATUC_PERF_DATA, void *struct_atucPerfDataEntry) - -typedef struct atucPerfDataEntry -{ - int ifIndex; - u32 adslAtucPerfLofs; - u32 adslAtucPerfLoss; - u32 adslAtucPerfESs; - u32 adslAtucPerfInits; - int adslAtucPerfValidIntervals; - int adslAtucPerfInvalidIntervals; - AdslPerfTimeElapsed adslAtucPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAtucPerfCurr15MinLofs; - PerfCurrentCount adslAtucPerfCurr15MinLoss; - PerfCurrentCount adslAtucPerfCurr15MinESs; - PerfCurrentCount adslAtucPerfCurr15MinInits; - AdslPerfTimeElapsed adslAtucPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAtucPerfCurr1DayLofs; - AdslPerfCurrDayCount adslAtucPerfCurr1DayLoss; - AdslPerfCurrDayCount adslAtucPerfCurr1DayESs; - AdslPerfCurrDayCount adslAtucPerfCurr1DayInits; - int adslAtucPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAtucPerfPrev1DayLofs; - AdslPerfPrevDayCount adslAtucPerfPrev1DayLoss; - AdslPerfPrevDayCount adslAtucPerfPrev1DayESs; - AdslPerfPrevDayCount adslAtucPerfPrev1DayInits; - u32 flags; -} atucPerfDataEntry; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct atucPerfDataExtEntry - { - int ifIndex; - u32 adslAtucPerfStatFastR; - u32 adslAtucPerfStatFailedFastR; - u32 adslAtucPerfStatSesL; - u32 adslAtucPerfStatUasL; - u32 adslAtucPerfCurr15MinFastR; - u32 adslAtucPerfCurr15MinFailedFastR; - u32 adslAtucPerfCurr15MinSesL; - u32 adslAtucPerfCurr15MinUasL; - u32 adslAtucPerfCurr1DayFastR; - u32 adslAtucPerfCurr1DayFailedFastR; - u32 adslAtucPerfCurr1DaySesL; - u32 adslAtucPerfCurr1DayUasL; - u32 adslAtucPerfPrev1DayFastR; - u32 adslAtucPerfPrev1DayFailedFastR; - u32 adslAtucPerfPrev1DaySesL; - u32 adslAtucPerfPrev1DayUasL; - u32 flags; -} atucPerfDataExtEntry; - -#endif -//ioctl(int fd, GET_ADSL_ATUR_PERF_DATA, void *struct_aturPerfDataEntry) - -typedef struct aturPerfDataEntry -{ - int ifIndex; - u32 adslAturPerfLofs; - u32 adslAturPerfLoss; - u32 adslAturPerfLprs; - u32 adslAturPerfESs; - int adslAturPerfValidIntervals; - int adslAturPerfInvalidIntervals; - AdslPerfTimeElapsed adslAturPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAturPerfCurr15MinLofs; - PerfCurrentCount adslAturPerfCurr15MinLoss; - PerfCurrentCount adslAturPerfCurr15MinLprs; - PerfCurrentCount adslAturPerfCurr15MinESs; - AdslPerfTimeElapsed adslAturPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAturPerfCurr1DayLofs; - AdslPerfCurrDayCount adslAturPerfCurr1DayLoss; - AdslPerfCurrDayCount adslAturPerfCurr1DayLprs; - AdslPerfCurrDayCount adslAturPerfCurr1DayESs; - int adslAturPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAturPerfPrev1DayLofs; - AdslPerfPrevDayCount adslAturPerfPrev1DayLoss; - AdslPerfPrevDayCount adslAturPerfPrev1DayLprs; - AdslPerfPrevDayCount adslAturPerfPrev1DayESs; - u32 flags; -} aturPerfDataEntry; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct aturPerfDataExtEntry - { - int ifIndex; - u32 adslAturPerfStatSesL; - u32 adslAturPerfStatUasL; - u32 adslAturPerfCurr15MinSesL; - u32 adslAturPerfCurr15MinUasL; - u32 adslAturPerfCurr1DaySesL; - u32 adslAturPerfCurr1DayUasL; - u32 adslAturPerfPrev1DaySesL; - u32 adslAturPerfPrev1DayUasL; - u32 flags; -} aturPerfDataExtEntry; -#endif -//ioctl(int fd, GET_ADSL_ATUC_INTVL_INFO, void *struct_adslAtucInvtInfo) - -typedef struct adslAtucIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount intervalLOF; - PerfIntervalCount intervalLOS; - PerfIntervalCount intervalES; - PerfIntervalCount intervalInits; - int intervalValidData; - u8 flags; -} adslAtucIntvlInfo; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct adslAtucInvtlExtInfo - { - int ifIndex; - int IntervalNumber; - u32 adslAtucIntervalFastR; - u32 adslAtucIntervalFailedFastR; - u32 adslAtucIntervalSesL; - u32 adslAtucIntervalUasL; - u32 flags; -} adslAtucInvtlExtInfo; -#endif -//ioctl(int fd, GET_ADSL_ATUR_INTVL_INFO, void *struct_adslAturInvtlInfo) - -typedef struct adslAturIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount intervalLOF; - PerfIntervalCount intervalLOS; - PerfIntervalCount intervalLPR; - PerfIntervalCount intervalES; - int intervalValidData; - u8 flags; -} adslAturIntvlInfo; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct adslAturInvtlExtInfo - { - int ifIndex; - int IntervalNumber; - u32 adslAturIntervalSesL; - u32 adslAturIntervalUasL; - u32 flags; -} adslAturInvtlExtInfo; -#endif -//ioctl(int fd, GET_ADSL_ATUC_CHAN_PERF_DATA, void *struct_atucChannelPerfDataEntry) - -typedef struct atucChannelPerfDataEntry -{ - int ifIndex; - u32 adslAtucChanReceivedBlks; - u32 adslAtucChanTransmittedBlks; - u32 adslAtucChanCorrectedBlks; - u32 adslAtucChanUncorrectBlks; - int adslAtucChanPerfValidIntervals; - int adslAtucChanPerfInvalidIntervals; - AdslPerfTimeElapsed adslAtucChanPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAtucChanPerfCurr15MinReceivedBlks; - PerfCurrentCount adslAtucChanPerfCurr15MinTransmittedBlks; - PerfCurrentCount adslAtucChanPerfCurr15MinCorrectedBlks; - PerfCurrentCount adslAtucChanPerfCurr15MinUncorrectBlks; - AdslPerfTimeElapsed adslAtucChanPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayReceivedBlks; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayTransmittedBlks; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayCorrectedBlks; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayUncorrectBlks; - int adslAtucChanPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayReceivedBlks; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayTransmittedBlks; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayCorrectedBlks; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayUncorrectBlks; - u32 flags; -}atucChannelPerfDataEntry; - - -//ioctl(int fd, GET_ADSL_ATUR_CHAN_PERF_DATA, void *struct_aturChannelPerfDataEntry) - -typedef struct aturChannelPerfDataEntry -{ - int ifIndex; - u32 adslAturChanReceivedBlks; - u32 adslAturChanTransmittedBlks; - u32 adslAturChanCorrectedBlks; - u32 adslAturChanUncorrectBlks; - int adslAturChanPerfValidIntervals; - int adslAturChanPerfInvalidIntervals; - AdslPerfTimeElapsed adslAturChanPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAturChanPerfCurr15MinReceivedBlks; - PerfCurrentCount adslAturChanPerfCurr15MinTransmittedBlks; - PerfCurrentCount adslAturChanPerfCurr15MinCorrectedBlks; - PerfCurrentCount adslAturChanPerfCurr15MinUncorrectBlks; - AdslPerfTimeElapsed adslAturChanPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayReceivedBlks; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayTransmittedBlks; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayCorrectedBlks; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayUncorrectBlks; - int adslAturChanPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayReceivedBlks; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayTransmittedBlks; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayCorrectedBlks; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayUncorrectBlks; - u32 flags; -} aturChannelPerfDataEntry; - - -//ioctl(int fd, GET_ADSL_ATUC_CHAN_INTVL_INFO, void *struct_adslAtucChanIntvlInfo) - -typedef struct adslAtucChanIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount chanIntervalRecvdBlks; - PerfIntervalCount chanIntervalXmitBlks; - PerfIntervalCount chanIntervalCorrectedBlks; - PerfIntervalCount chanIntervalUncorrectBlks; - int intervalValidData; - u8 flags; -} adslAtucChanIntvlInfo; - - -//ioctl(int fd, GET_ADSL_ATUR_CHAN_INTVL_INFO, void *struct_adslAturChanIntvlInfo) - -typedef struct adslAturChanIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount chanIntervalRecvdBlks; - PerfIntervalCount chanIntervalXmitBlks; - PerfIntervalCount chanIntervalCorrectedBlks; - PerfIntervalCount chanIntervalUncorrectBlks; - int intervalValidData; - u8 flags; -} adslAturChanIntvlInfo; - - -//ioctl(int fd, GET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry) -//ioctl(int fd, SET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry) - -typedef struct adslLineAlarmConfProfileEntry - { - unsigned char adslLineAlarmConfProfileName[32]; - int adslAtucThresh15MinLofs; - int adslAtucThresh15MinLoss; - int adslAtucThresh15MinESs; - u32 adslAtucThreshFastRateUp; - u32 adslAtucThreshInterleaveRateUp; - u32 adslAtucThreshFastRateDown; - u32 adslAtucThreshInterleaveRateDown; - int adslAtucInitFailureTrapEnable; - int adslAturThresh15MinLofs; - int adslAturThresh15MinLoss; - int adslAturThresh15MinLprs; - int adslAturThresh15MinESs; - u32 adslAturThreshFastRateUp; - u32 adslAturThreshInterleaveRateUp; - u32 adslAturThreshFastRateDown; - u32 adslAturThreshInterleaveRateDown; - int adslLineAlarmConfProfileRowStatus; - u32 flags; -} adslLineAlarmConfProfileEntry; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct adslLineAlarmConfProfileExtEntry - { - u8 adslLineAlarmConfProfileExtName[32]; - u32 adslAtucThreshold15MinFailedFastR; - u32 adslAtucThreshold15MinSesL; - u32 adslAtucThreshold15MinUasL; - u32 adslAturThreshold15MinSesL; - u32 adslAturThreshold15MinUasL; - u32 flags; -} adslLineAlarmConfProfileExtEntry; -#endif -//TRAPS - -// 603221:tc.chen start -/* The following Data Sturctures are added to support the WEB related parameters for ADSL Statistics */ -typedef struct adslLineStatus - { - int adslModemStatus; - u32 adslModeSelected; - int adslAtucThresh15MinESs; - int adslTrellisCodeEnable; - int adslLatency; - u8 flags; - } adslLineStatusInfo; - -typedef struct adslLineRate - { - u32 adslDataRateds; - u32 adslDataRateus; - u32 adslATTNDRds; - u32 adslATTNDRus; - u8 flags; - } adslLineRateInfo; - -typedef struct adslLineInfo - { - u32 adslInterleaveDepthds; - u32 adslInterleaveDepthus; - u32 adslLATNds; - u32 adslLATNus; - u32 adslSATNds; - u32 adslSATNus; - int adslSNRMds; - int adslSNRMus; - int adslACATPds; - int adslACATPus; - u32 flags; - } adslLineInfo; - -typedef struct adslNearEndPerfStats - { - u32 adslSuperFrames; - u32 adslneLOS; - u32 adslneLOF; - u32 adslneLPR; - u32 adslneNCD; - u32 adslneLCD; - u32 adslneCRC; - u32 adslneRSCorr; - u32 adslneFECS; - u32 adslneES; - u32 adslneSES; - u32 adslneLOSS; - u32 adslneUAS; - u32 adslneHECErrors; - u32 flags; - } adslNearEndPerfStats; - -typedef struct adslFarEndPerfStats - { - u32 adslfeLOS; - u32 adslfeLOF; - u32 adslfeLPR; - u32 adslfeNCD; - u32 adslfeLCD; - u32 adslfeCRC; - u32 adslfeRSCorr; - u32 adslfeFECS; - u32 adslfeES; - u32 adslfeSES; - u32 adslfeLOSS; - u32 adslfeUAS; - u32 adslfeHECErrors; - u32 flags; - } adslFarEndPerfStats; -// 603221:tc.chen end - -/* The number of tones (and hence indexes) is dependent on the ADSL mode - G.992.1, G.992.2, G.992.3, * G.992.4 and G.992.5 */ -typedef struct adslATURSubcarrierInfo { - int ifindex; - u16 HLINSCds; - u16 HLINpsds[1024];/* Even index = real part; Odd Index - = imaginary part for each tone */ - u16 HLOGMTds; - u16 HLOGpsds[512]; - u16 QLNMTds; - u16 QLNpsds[512]; - u16 SNRMTds; - u16 SNRpsds[512]; - u16 BITpsds[512]; - u16 GAINpsds[512]; - u16 flags; -}adslATURSubcarrierInfo; - -typedef struct adslATUCSubcarrierInfo { - int ifindex; - u16 HLINSCus; - u16 HLINpsus[128];/* Even index = real part; Odd Index - = imaginary part for each tone */ - u16 HLOGMTus; - u16 HLOGpsus[64]; - u16 QLNMTus; - u16 QLNpsus[64]; - u16 SNRMTus; - u16 SNRpsus[64]; - u16 BITpsus[64]; - u16 GAINpsus[64]; - u16 flags; -}adslATUCSubcarrierInfo; - -#ifndef u_int16 -#define u_int16 u16 -#endif - -typedef struct adslInitStats { - u_int16 FullInitializationCount; - u_int16 FailedFullInitializationCount; - u_int16 LINIT_Errors; - u_int16 Init_Timeouts; -}adslInitStats; - -typedef struct adslPowerSpectralDensity { - int ACTPSDds; - int ACTPSDus; -}adslPowerSpectralDensity; - - -//ioctl(int fd, ADSL_ATUR_TRAPS, void *uint16_flags) -typedef union structpts { - adslLineTableEntry * adslLineTableEntry_pt; - adslAtucPhysEntry * adslAtucPhysEntry_pt; - adslAturPhysEntry * adslAturPhysEntry_pt; - adslAtucChanInfo * adslAtucChanInfo_pt; - adslAturChanInfo * adslAturChanInfo_pt; - atucPerfDataEntry * atucPerfDataEntry_pt; - aturPerfDataEntry * aturPerfDataEntry_pt; - adslAtucIntvlInfo * adslAtucIntvlInfo_pt; - adslAturIntvlInfo * adslAturIntvlInfo_pt; - atucChannelPerfDataEntry * atucChannelPerfDataEntry_pt; - aturChannelPerfDataEntry * aturChannelPerfDataEntry_pt; - adslAtucChanIntvlInfo * adslAtucChanIntvlInfo_pt; - adslAturChanIntvlInfo * adslAturChanIntvlInfo_pt; - adslLineAlarmConfProfileEntry * adslLineAlarmConfProfileEntry_pt; - // RFC 3440 - - #ifdef AMAZON_MEI_MIB_RFC3440 - adslLineExtTableEntry * adslLineExtTableEntry_pt; - atucPerfDataExtEntry * atucPerfDataExtEntry_pt; - adslAtucInvtlExtInfo * adslAtucInvtlExtInfo_pt; - aturPerfDataExtEntry * aturPerfDataExtEntry_pt; - adslAturInvtlExtInfo * adslAturInvtlExtInfo_pt; - adslLineAlarmConfProfileExtEntry * adslLineAlarmConfProfileExtEntry_pt; - #endif -// 603221:tc.chen start - adslLineStatusInfo * adslLineStatusInfo_pt; - adslLineRateInfo * adslLineRateInfo_pt; - adslLineInfo * adslLineInfo_pt; - adslNearEndPerfStats * adslNearEndPerfStats_pt; - adslFarEndPerfStats * adslFarEndPerfStats_pt; -// 603221:tc.chen end - adslATUCSubcarrierInfo * adslATUCSubcarrierInfo_pt; - adslATURSubcarrierInfo * adslATURSubcarrierInfo_pt; - adslPowerSpectralDensity * adslPowerSpectralDensity_pt; -}structpts; - -#endif /* ] __AMAZON_MEI_APP_IOCTL_H */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_ioctl.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_ioctl.h deleted file mode 100644 index 02a150eac4..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_ioctl.h +++ /dev/null @@ -1,757 +0,0 @@ -//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl -#ifndef _AMAZON_MEI_IOCTL_H -#define _AMAZON_MEI_IOCTL_H - -///////////////////////////////////////////////////////////////////////////////////////////////////// -#define PCM_BUFF_SIZE 1024 //bytes -// interrupt numbers - -#ifndef _AMAZON_ADSL_APP - -typedef struct pcm_data_struct{ - u16 S; - u16 temp; - u16 LSW; - u16 MSW; - u16 len; - u16 rdindex; - u16 wrindex; - u16 flow; - - int finish; - u8 buff[PCM_BUFF_SIZE]; - int point; -}pcm_data_struct; - -typedef struct amazon_clreoc_pkt{ - struct list_head list; - u8 * command; //point to clreoc command data - int len; //command length -}amazon_clreoc_pkt; - -// Number of intervals -#define INTERVAL_NUM 192 //two days -typedef struct amazon_mei_mib{ - struct list_head list; - struct timeval start_time; //start of current interval - - int AtucPerfLof; - int AtucPerfLos; - int AtucPerfEs; - int AtucPerfInit; - - int AturPerfLof; - int AturPerfLos; - int AturPerfLpr; - int AturPerfEs; - - int AturChanPerfRxBlk; - int AturChanPerfTxBlk; - int AturChanPerfCorrBlk; - int AturChanPerfUncorrBlk; - - //RFC-3440 - int AtucPerfStatFastR; - int AtucPerfStatFailedFastR; - int AtucPerfStatSesL; - int AtucPerfStatUasL; - int AturPerfStatSesL; - int AturPerfStatUasL; -}amazon_mei_mib; - -typedef struct adslChanPrevTxRate{ - u32 adslAtucChanPrevTxRate; - u32 adslAturChanPrevTxRate; -}adslChanPrevTxRate; - -typedef struct adslPhysCurrStatus{ - u32 adslAtucCurrStatus; - u32 adslAturCurrStatus; -}adslPhysCurrStatus; - -typedef struct ChanType{ - int interleave; - int fast; -// 603221:tc.chen start - int bearchannel0; - int bearchannel1; -// 603221:tc.chen end -}ChanType; - -typedef struct mib_previous_read{ - u16 ATUC_PERF_ESS; - u16 ATUR_PERF_ESS; - u32 ATUR_CHAN_RECV_BLK; - u16 ATUR_CHAN_CORR_BLK_INTL; - u16 ATUR_CHAN_CORR_BLK_FAST; - u16 ATUR_CHAN_UNCORR_BLK_INTL; - u16 ATUR_CHAN_UNCORR_BLK_FAST; - u16 ATUC_PERF_STAT_FASTR; - u16 ATUC_PERF_STAT_FAILED_FASTR; - u16 ATUC_PERF_STAT_SESL; - u16 ATUC_PERF_STAT_UASL; - u16 ATUR_PERF_STAT_SESL; -}mib_previous_read; - -typedef struct mib_flags_pretime{ - struct timeval ATUC_PERF_LOSS_PTIME; - struct timeval ATUC_PERF_LOFS_PTIME; - struct timeval ATUR_PERF_LOSS_PTIME; - struct timeval ATUR_PERF_LOFS_PTIME; - struct timeval ATUR_PERF_LPR_PTIME; -}mib_flags_pretime; - - // cmv message structures -#define MP_PAYLOAD_SIZE 12 -typedef struct mpmessage{ - u16 iFunction; - u16 iGroup; - u16 iAddress; - u16 iIndex; - u16 iPayload[MP_PAYLOAD_SIZE]; -}MPMessage; -#endif - - -typedef struct meireg{ - u32 iAddress; - u32 iData; -}meireg; - -#define MEIDEBUG_BUFFER_SIZES 50 -typedef struct meidebug{ - u32 iAddress; - u32 iCount; - u32 buffer[MEIDEBUG_BUFFER_SIZES]; -}meidebug; - -//============================================================================== -// Group definitions -//============================================================================== -#define OPTN 5 -#define CNFG 8 -#define CNTL 1 -#define STAT 2 -#define RATE 6 -#define PLAM 7 -#define INFO 3 -#define TEST 4 -//============================================================================== -// Opcode definitions -//============================================================================== -#define H2D_CMV_READ 0x00 -#define H2D_CMV_WRITE 0x04 -#define H2D_CMV_INDICATE_REPLY 0x10 -#define H2D_ERROR_OPCODE_UNKNOWN 0x20 -#define H2D_ERROR_CMV_UNKNOWN 0x30 - -#define D2H_CMV_READ_REPLY 0x01 -#define D2H_CMV_WRITE_REPLY 0x05 -#define D2H_CMV_INDICATE 0x11 -#define D2H_ERROR_OPCODE_UNKNOWN 0x21 -#define D2H_ERROR_CMV_UNKNOWN 0x31 -#define D2H_ERROR_CMV_READ_NOT_AVAILABLE 0x41 -#define D2H_ERROR_CMV_WRITE_ONLY 0x51 -#define D2H_ERROR_CMV_READ_ONLY 0x61 - -#define H2D_DEBUG_READ_DM 0x02 -#define H2D_DEBUG_READ_PM 0x06 -#define H2D_DEBUG_WRITE_DM 0x0a -#define H2D_DEBUG_WRITE_PM 0x0e - -#define D2H_DEBUG_READ_DM_REPLY 0x03 -#define D2H_DEBUG_READ_FM_REPLY 0x07 -#define D2H_DEBUG_WRITE_DM_REPLY 0x0b -#define D2H_DEBUG_WRITE_FM_REPLY 0x0f -#define D2H_ERROR_ADDR_UNKNOWN 0x33 - -#define D2H_AUTONOMOUS_MODEM_READY_MSG 0xf1 -//============================================================================== -// INFO register address field definitions -//============================================================================== - -#define INFO_TxState 0 -#define INFO_RxState 1 -#define INFO_TxNextState 2 -#define INFO_RxNextState 3 -#define INFO_TxStateJumpFrom 4 -#define INFO_RxStateJumpFrom 5 - -#define INFO_ReverbSnrBuf 8 -#define INFO_ReverbEchoSnrBuf 9 -#define INFO_MedleySnrBuf 10 -#define INFO_RxShowtimeSnrBuf 11 -#define INFO_DECdelay 12 -#define INFO_DECExponent 13 -#define INFO_DECTaps 14 -#define INFO_AECdelay 15 -#define INFO_AECExponent 16 -#define INFO_AECTaps 17 -#define INFO_TDQExponent 18 -#define INFO_TDQTaps 19 -#define INFO_FDQExponent 20 -#define INFO_FDQTaps 21 -#define INFO_USBat 22 -#define INFO_DSBat 23 -#define INFO_USFineGains 24 -#define INFO_DSFineGains 25 -#define INFO_BitloadFirstChannel 26 -#define INFO_BitloadLastChannel 27 -#define INFO_PollEOCData 28 // CO specific -#define INFO_CSNRMargin 29 // CO specific -#define INFO_RCMsgs1 30 -#define INFO_RMsgs1 31 -#define INFO_RMsgRA 32 -#define INFO_RCMsgRA 33 -#define INFO_RMsg2 34 -#define INFO_RCMsg2 35 -#define INFO_BitLoadOK 36 -#define INFO_RCRates1 37 -#define INFO_RRates1Tab 38 -#define INFO_RMsgs1Tab 39 -#define INFO_RMsgRATab 40 -#define INFO_RRatesRA 41 -#define INFO_RCRatesRA 42 -#define INFO_RRates2 43 -#define INFO_RCRates2 44 -#define INFO_PackedRMsg2 45 -#define INFO_RxBitSwapFlag 46 -#define INFO_TxBitSwapFlag 47 -#define INFO_ShowtimeSNRUpdateCount 48 -#define INFO_ShowtimeFDQUpdateCount 49 -#define INFO_ShowtimeDECUpdateCount 50 -#define INFO_CopyRxBuffer 51 -#define INFO_RxToneBuf 52 -#define INFO_TxToneBuf 53 -#define INFO_Version 54 -#define INFO_TimeStamp 55 -#define INFO_feVendorID 56 -#define INFO_feSerialNum 57 -#define INFO_feVersionNum 58 -#define INFO_BulkMemory 59 //Points to start of bulk memory -#define INFO_neVendorID 60 -#define INFO_neVersionNum 61 -#define INFO_neSerialNum 62 - -//============================================================================== -// RATE register address field definitions -//============================================================================== - - -#define RATE_UsRate 0 -#define RATE_DsRate 1 - - -//============================================================================== -// PLAM (Physical Layer Management) register address field definitions -// (See G997.1 for reference) -//============================================================================== - - - // /// - // Failure Flags /// - // /// - -#define PLAM_NearEndFailureFlags 0 -#define PLAM_FarEndFailureFlags 1 - - // /// - // Near End Failure Flags Bit Definitions /// - // /// - -// ADSL Failures /// -#define PLAM_LOS_FailureBit 0x0001 -#define PLAM_LOF_FailureBit 0x0002 -#define PLAM_LPR_FailureBit 0x0004 -#define PLAM_RFI_FailureBit 0x0008 - -// ATM Failures /// -#define PLAM_NCD_LP0_FailureBit 0x0010 -#define PLAM_NCD_LP1_FailureBit 0x0020 -#define PLAM_LCD_LP0_FailureBit 0x0040 -#define PLAM_LCD_LP1_FailureBit 0x0080 - -#define PLAM_NCD_BC0_FailureBit 0x0100 -#define PLAM_NCD_BC1_FailureBit 0x0200 -#define PLAM_LCD_BC0_FailureBit 0x0400 -#define PLAM_LCD_BC1_FailureBit 0x0800 - // /// - // Performance Counts /// - // /// - -#define PLAM_NearEndCrcCnt 2 -#define PLAM_CorrectedRSErrors 3 - -#define PLAM_NearEndECSCnt 6 -#define PLAM_NearEndESCnt 7 -#define PLAM_NearEndSESCnt 8 -#define PLAM_NearEndLOSSCnt 9 -#define PLAM_NearEndUASLCnt 10 - -#define PLAM_NearEndHECErrCnt 11 - -#define PLAM_NearEndHECTotCnt 16 -#define PLAM_NearEndCellTotCnt 18 -#define PLAM_NearEndSfCntLSW 20 -#define PLAM_NearEndSfCntMSW 21 - -#define PLAM_FarEndFebeCnt 24 - -#define PLAM_FarEndFecCnt 28 - -#define PLAM_FarEndFECSCnt 32 -#define PLAM_FarEndESCnt 33 -#define PLAM_FarEndSESCnt 34 -#define PLAM_FarEndLOSSCnt 35 -#define PLAM_FarEndUASLCnt 36 - -#define PLAM_FarEndHECErrCnt 37 - -#define PLAM_FarEndHECTotCnt 41 - -#define PLAM_FarEndCellTotCnt 43 - -#define PLAM_LineAttn 45 -#define PLAM_SNRMargin 46 - - -//============================================================================== -// CNTL register address and bit field definitions -//============================================================================== - - -#define CNTL_ModemControl 0 - -#define CNTL_ModemReset 0x0 -#define CNTL_ModemStart 0x2 - - -//============================================================================== -// STAT register address and bit field definitions -//============================================================================== - -#define STAT_MacroState 0 -#define STAT_Mode 1 -#define STAT_DMTFramingMode 2 -#define STAT_SleepState 3 -#define STAT_Misc 4 -#define STAT_FailureState 5 - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // STAT_OLRStatus provides status of OLR - //16-bit STAT_OLRStatus_DS - // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted - // [3:2]: Reserved - // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA) - // [7:6]: Reserved - // [10:8]: >0=Request. 0=not. For DS, # of request transmissions/retransmissions (3 bits). - // [11]: 1=Receive Response, 0=not - // [15:12]: Reserved - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /// -#define STAT_OLRStatus_DS 6 - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // STAT_OLRStatus provides status of OLR - // 16-bit STAT_OLRStatus_US CMV - // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted - // [3:2]: Reserved - // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA) - // [7:6]: Reserved - // [8]: 1=Request Received. 0=not. - // [10:9]: Reserved - // [11]: 1=Response Sent, 0=not - // [15:12]: Reserved - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/// -#define STAT_OLRStatus_US 7 - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // STAT_PMStatus provides status of PM - // 16-bit STAT_PMStatus CMV - // [1:0] : PM Status 00=IDLE, 01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted - // [2] : 0=ATU_R initiated PM; 1 = ATU_C initiated PM - // [3]: Reserved - // [5:4]: PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim) - // [7:6]: Reserved - // [10:8]: >0=Request. 0=not. # of request transmissions/retransmissions (3 bits). - // [11]: 1=Response, 0=not - // [15:12]: Reserved - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /// -#define STAT_PMStatus 8 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError - // [3:0]: OLR/PM response reason code - // [7:4]: OLR/PM Internal error code - // [15:8]: OLR/PM Reserved for future - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /// -#define STAT_OLRError_DS 9 -#define STAT_OLRError_US 10 -#define STAT_PMError 11 - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_MacroState -// MacroState reflects the high level state of the modem - -#define STAT_InitState 0x0000 -#define STAT_ReadyState 0x0001 -#define STAT_FailState 0x0002 -#define STAT_IdleState 0x0003 -#define STAT_QuietState 0x0004 -#define STAT_GhsState 0x0005 -#define STAT_FullInitState 0x0006 -#define STAT_ShowTimeState 0x0007 -#define STAT_FastRetrainState 0x0008 -#define STAT_LoopDiagMode 0x0009 -#define STAT_ShortInit 0x000A // Bis short initialization /// - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_Mode -// ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use -// G.Hs or some other mechanism to negotiate the specific mode of operation. -// The OPTN_modeControl CMV is used to select a set of desired modes. -// The STAT_Mode CMV indicates which mode was actually selected. - -#define STAT_ConfigMode_T1413 0x0001 -#define STAT_ConfigMode_G992_2_AB 0x0002 -#define STAT_ConfigMode_G992_1_A 0x0004 -#define STAT_ConfigMode_G992_1_B 0x0008 -#define STAT_ConfigMode_G992_1_C 0x0010 -#define STAT_ConfigMode_G992_2_C 0x0020 - -#define STAT_ConfigMode_G992_3_A 0x0100 -#define STAT_ConfigMode_G992_3_B 0x0200 -#define STAT_ConfigMode_G992_3_I 0x0400 -#define STAT_ConfigMode_G992_3_J 0x0800 -#define STAT_ConfigMode_G992_3_L 0x1000 - -#define STAT_ConfigMode_G992_4_A 0x2000 -#define STAT_ConfigMode_G992_4_I 0x4000 - -#define STAT_ConfigMode_G992_5 0x8000 - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_DMTFramingMode -// FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode -// status is not applicable in BIS mode and its value is undefined -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define STAT_FramingModeMask 0x0003 - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_Misc -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define STAT_OverlappedSpectrum 0x0008 -#define STAT_TCM 0x0010 -#define STAT_TDQ_at_1104 0x0020 -#define STAT_T1413_Signal_Detected 0x0040 -#define STAT_AnnexL_US_Mask1_PSD 0x1000 //indicate we actually selected G992.3 AnnexL US PSD mask1 -#define STAT_AnnexL_US_Mask2_PSD 0x2000 //indicate we actually selected G992.3 AnnexL US PSD mask2 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_FailureState -// when the MacroSTate indicates the fail state, FailureState provides a failure code -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -#define E_CODE_NO_ERROR 0 -#define E_CODE_BAT_TX 1 // TX BAT table is incorrect */ -#define E_CODE_BAT_RX 2 // RX BAT table is incorrect */ -#define E_CODE_PROFILE 3 // profile is not selected in fast retrain */ -#define E_CODE_TX_AOC_FIFO_OVERFLOW 4 -#define E_CODE_TRUNCATE_FR 5 //Fast Retrain truncated due to no stored profiles*/ -#define E_CODE_BITLOAD 6 // bit loading fails */ -#define E_CODE_ST_ERROR 7 // showtime CRC error */ -#define E_CODE_RESERVED 8 // using parameters reserved by the ITU-T */ -#define E_CODE_C_TONES 9 // detected C_TONES */ -#define E_CODE_CODESWAP_ERR 10 // codeswap not finished in time */ -#define E_CODE_FIFO_OVERFLOW 11 // we have run out of fifo space */ -#define E_CODE_C_BG_DECODE_ERR 12 // error in decoding C-BG message */ -#define E_CODE_C_RATES2_DECODE_ERR 13 // error in decoding C-MSGS2 and C-RATES2 */ -#define E_CODE_RCMedleyRx_C_SEGUE2_Failure 14 // Timeout after RCMedleyRx waiting for C_SEGUE2 */ -#define E_CODE_RReverbRATx_C_SEGUE2_Failure 15 // Timeout after RReverbRATx waiting for C_SEGUE2 */ -#define E_CODE_RReverb3Tx_C_SEGUE1_Failure 16 // Timeout after RReverb3Tx waiting for C_SEGUE1 */ -#define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR 17 // Received CRC not equal to computed CRC */ -#define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR 18 // Received CRC not equal to computed CRC */ -#define E_CODE_RReverb5Tx_C_SEGUE2_Failure 19 // Timeout after RReverb5Tx waiting for C_SEGUE2 */ -#define E_CODE_RReverb6Tx_C_SEGUE3_Failure 20 // Timeout after RReverb6Tx waiting for C_SEGUE3 */ -#define E_CODE_RSegue5Tx_C_SEGUE3_Failure 21 // Timeout after RSegue5Tx waiting for C_SEGUE3 */ -#define E_CODE_RCReverb5Rx_C_SEGUE_Failure 22 // Timeout after RCReverb5Rx waiting for C_SEGUE */ -#define E_CODE_RCReverbRARx_C_SEGUE2_Failure 23 // Timeout after RCReverbRARx waiting for C_SEGUE2 */ -#define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR 24 // Received CRC not equal to computed CRC */ -#define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR 25 // Received CRC not equal to computed CRC */ -#define E_CODE_RCCRC3Rx_DECOD_ERR 26 // Received CRC not equal to computed CRC */ -#define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT 27 // DEC Path Delay timeout */ -#define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT 28 // DEC Training timeout */ -#define E_CODE_RCReverb3Rx_C_SEGUE1_Failure 29 // Timeout after RCReverb3Rx waiting for C_SEGUE1 */ -#define E_CODE_RCReverb2Rx_SignalEnd_Failure 30 // Timeout waiting for the end of RCReverb2Rx signal */ -#define E_CODE_RQuiet2_SignalEnd_Failure 31 // Timeout waiting for the end of RQuiet2 signal */ -#define E_CODE_RCReverbFR1Rx_Failure 32 // Timeout waiting for the end of RCReverbFR1Rx signal */ -#define E_CODE_RCPilotFR1Rx_SignalEnd_Failure 33 // Timeout waiting for the end of RCPilotFR1Rx signal */ -#define E_CODE_RCReverbFR2Rx_C_Segue_Failure 34 // Timeout after RCReverbFR2Rx waiting for C_SEGUE */ -#define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT 35 // Timeout waiting for the end of RCReverbFR5Rx signal */ -#define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure 36 // Timeout after RCReverbFR6Rx waiting for C_SEGUE */ -#define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure 37 // Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */ -#define E_CODE_RCReverbFR8Rx_No_PROFILE 38 // Timeout since no profile was selected */ -#define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT 39 // Timeout waiting for the end of RCReverbFR8Rx signal */ -#define E_CODE_RCCRCFR1_DECOD_ERR 40 // Received CRC not equal to computed CRC */ -#define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT 41 // Timeout waiting for the end of RCRecovRx signal */ -#define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT 42 // Timeout after RSegueFR5Tx waiting for C_SEGUE2 */ -#define E_CODE_RRecovTx_SignalEnd_TIMEOUT 43 // Timeout waiting for the end of RRecovTx signal */ -#define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure 44 // Timeout after RCMedleyFRRx waiting for C_SEGUE2 */ -#define E_CODE_CONFIGURATION_PARAMETERS_ERROR 45 // one of the configuration parameters do not meet the standard */ -#define E_CODE_BAD_MEM_ACCESS 46 -#define E_CODE_BAD_INSTRUCTION_ACCESS 47 -#define E_CODE_TX_EOC_FIFO_OVERFLOW 48 -#define E_CODE_RX_EOC_FIFO_OVERFLOW 49 -#define E_CODE_GHS_CD_FLAG_TIME_OUT 50 // Timeout when transmitting Flag in handshake cleardown */ - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//STAT_OLRStatus: -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define STAT_OLRPM_IDLE 0x0000 -#define STAT_OLRPM_IN_PROGRESS 0x0001 -#define STAT_OLRPM_COMPLETE 0x0002 -#define STAT_OLRPM_ABORTED 0x0003 -#define STAT_OLRPM_RESPONSE 0x0800 - -#define STAT_OLR_BITSWAP 0x0010 -#define STAT_OLR_DRR 0x0020 -#define STAT_OLR_SRA 0x0030 - -//STAT_PMStatus_US: -#define STAT_PM_CO_REQ 0x0004 -#define STAT_PM_SIMPLE_REQ 0x0010 -#define STAT_PM_L2_REQ 0x0020 -#define STAT_PM_L2_TRIM_REQ 0x0030 - -// STAT_OLRError_DS, STAT_OLRError_US -//4 bit response reason code: -#define RESP_BUSY 0x01 -#define RESP_INVALID_PARAMETERS 0x02 -#define RESP_NOT_ENABLED 0x03 -#define RESP_NOT_SUPPORTED 0x04 - -//4 bit internal error code (common for OLR and PM) -#define REQ_INVALID_BiGi 0x10 -#define REQ_INVALID_Lp 0x20 -#define REQ_INVALID_Bpn 0x30 -#define REQ_INVALID_FRAMING_CONSTRAINT 0x40 -#define REQ_NOT_IN_L0_STATE 0x50 -#define REQ_NOT_IN_L2_STATE 0x60 -#define REQ_INVALID_PCB 0x70 -#define REQ_VIOLATES_MARGIN 0x80 - -//STAT_PMError -//4 bit response reason code: -#define RESP_STATE_NOT_DESIRED 0x03 -#define RESP_INFEASIBLE_PARAMETERS 0x04 - - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN register address and bit field definitions -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_ModeControl 0 -#define OPTN_DMTLnkCtl 1 -// Reserved 2 -#define OPTN_GhsControl 3 -// Reserved 4 -#define OPTN_PwrManControl 5 -#define OPTN_AnnexControl 6 -#define OPTN_ModeControl1 7 -// Reserved 8 -#define OPTN_StateMachineCtrl 9 -// Reserved 10 -// Reserved 11 -#define OPTN_BisLinkControl 12 -#define OPTN_ATMAddrConfig 13 -#define OPTN_ATMNumCellConfig 14 - -// Mode control defines the allowable operating modes of an ADSL link. In general, a modem may /// -// use G.Hs or some other mechanism to negotiate the specific mode of operation. /// -// The OPTN_ModeControl CMV is used to select a set of desired modes /// -// The STAT_ModeControl CMV indicates which mode was actually selected /// - -// OPTN_ModeControl -#define OPTN_ConfigMode_T1413 0x0001 -#define OPTN_ConfigMode_G992_2_AB 0x0002 -#define OPTN_ConfigMode_G992_1_A 0x0004 -#define OPTN_ConfigMode_G992_1_B 0x0008 -#define OPTN_ConfigMode_G992_1_C 0x0010 -#define OPTN_ConfigMode_G992_2_C 0x0020 - -#define OPTN_ConfigMode_G992_3_A 0x0100 -#define OPTN_ConfigMode_G992_3_B 0x0200 -#define OPTN_ConfigMode_G992_3_I 0x0400 -#define OPTN_ConfigMode_G992_3_J 0x0800 -#define OPTN_ConfigMode_G992_3_L 0x1000 - -#define OPTN_ConfigMode_G992_4_A 0x2000 -#define OPTN_ConfigMode_G992_4_I 0x4000 - -#define OPTN_ConfigMode_G992_5 0x8000 - -// OPTN_PwrManControl -#define OPTN_PwrManWakeUpGhs 0x1 -#define OPTN_PwrManWakeUpFR 0x2 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_DMT Link Control -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define OPTN_DMT_DualLatency_Dis 0x200 -#define OPTN_DMT_S_Dis 0x100 -#define OPTN_DMT_FRAMINGMODE 0x1 -#define OPTN_DMT_FRAMINGMODE_MASK 0x7 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_BIS Link Control -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define OPTN_BisLinkContrl_LineProbeDis 0x1 -#define OPTN_BisLinkContrl_DSBlackBitsEn 0x2 -#define OPTN_BisLinkContrl_DiagnosticModeEn 0x4 -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_GhsControl -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// -// for OPTN_GhsControl, we will assign 16bit word as follows -// bit 0~3: set the control over which start(initial) message CPE will send: -// -// BIT: 2 1 0 -// 0 0 1 CLR -// 0 1 0 MR -// 0 1 1 MS -// 1 0 0 MP -// -// // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange -// BIT: 5 4 -// 0 1 MS -// 1 0 MR -// 1 1 MP -// -// // bit 15: RT initiated G.hs sample sessions one through eight. Session one is default. -// BIT: 15 -// 1 means session one -// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_GHS_ST_GHS 0x8000 -#define OPTN_GHS_INIT_MASK 0x000F -#define OPTN_GHS_RESP_MASK 0x00F0 - -#define OPTN_RTInitTxMsg_CLR 0x0001 -#define OPTN_RTInitTxMsg_MR 0x0002 -#define OPTN_RTInitTxMsg_MS 0x0003 -#define OPTN_RTInitTxMsg_MP 0x0004 - -#define OPTN_RTRespTxMsg_MS 0x0010 -#define OPTN_RTRespTxMsg_MR 0x0020 -#define OPTN_RTRespTxMsg_MP 0x0030 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_AnnexControl -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -// G.992.3 Annex A/L1/L2 US PSD Mask preferred - -#define OPTN_G992_3_AnnexA_PreferredModeMask 0x3000 -#define OPTN_G992_3_AnnexA_PreferredModeA 0x0000 // default AnnexA PSD mask /// -#define OPTN_G992_3_AnnexA_PreferredModeL1 0x1000 // AnnexL wide spectrum upstream PSD mask /// -#define OPTN_G992_3_AnnexA_PreferredModeL2 0x2000 // AnnexL narrow spectrum upstream PSD mask /// - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//OPTN_ATMAddrConfig -// Bits 4:0 are Utopia address for BC1 -// Bits 9:5 are Utopia address for BC0 -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_UTPADDR_BC1 0x001F -#define OPTN_UTPADDR_BC0 0x03E0 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//OPTN_ATMNumCellConfig -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_BC1_NUM_CELL_PAGES 0x000F // Bits 0:3 /// -#define OPTN_BC0_NUM_CELL_PAGES 0x00F0 // Bits 4:7 /// - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// CNFG register address field /// -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -/////////////////////////////////////////// -// these cmvs are used by bis handshake /// -/////////////////////////////////////////// - -// Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t) -#define CNFG_TPS_TC_DS0 0 -#define CNFG_TPS_TC_DS1 1 -#define CNFG_TPS_TC_US0 2 -#define CNFG_TPS_TC_US1 3 - -#define CNFG_HDLC_Overhead_Requirements 4 - -// Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t) -#define CNFG_PMS_TC_DS0 5 -#define CNFG_PMS_TC_DS1 6 -#define CNFG_PMS_TC_US0 7 -#define CNFG_PMS_TC_US1 8 - -// CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t) -#define CNFG_PMD_PARAMETERS 9 - -//////////////////////////////////////////////////////////// -// these cmvs are used by bis training and showtime code /// -//////////////////////////////////////////////////////////// - -//////////////// -// Tx Config /// -//////////////// -#define CNFG_tx_Cnfg_Nbc 10 -#define CNFG_tx_Cnfg_Nlp 11 -#define CNFG_tx_Cnfg_Rp 12 -#define CNFG_tx_Cnfg_Mp 13 -#define CNFG_tx_Cnfg_Lp 14 -#define CNFG_tx_Cnfg_Tp 15 -#define CNFG_tx_Cnfg_Dp 16 -#define CNFG_tx_Cnfg_Bpn 17 -#define CNFG_tx_Cnfg_FramingMode 18 -#define CNFG_tx_Cnfg_MSGLp 19 -#define CNFG_tx_Cnfg_MSGc 20 - - -//////////////// -// Rx Config /// -//////////////// -#define CNFG_rx_Cnfg_Nbc 21 -#define CNFG_rx_Cnfg_Nlp 22 -#define CNFG_rx_Cnfg_Rp 23 -#define CNFG_rx_Cnfg_Mp 24 -#define CNFG_rx_Cnfg_Lp 25 -#define CNFG_rx_Cnfg_Tp 26 -#define CNFG_rx_Cnfg_Dp 27 -#define CNFG_rx_Cnfg_Bpn 28 -#define CNFG_rx_Cnfg_FramingMode 29 -#define CNFG_rx_Cnfg_MSGLp 30 -#define CNFG_rx_Cnfg_MSGc 31 - -#define CNFG_tx_Cnfg_BCnToLPp 32 -#define CNFG_rx_Cnfg_BCnToLPp 33 - - - -#endif - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_sw.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_sw.h deleted file mode 100644 index 3b73b53892..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_sw.h +++ /dev/null @@ -1,176 +0,0 @@ -#ifndef AMAZON_SW_H -#define AMAZON_SW_H -#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE -#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 -#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 -#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 -#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 -#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 -#define SET_ETH_REG SIOCDEVPRIVATE+6 -#define VLAN_TOOLS SIOCDEVPRIVATE+7 -#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8 - - -/*===mac table commands==*/ -#define RESET_MAC_TABLE 0 -#define READ_MAC_ENTRY 1 -#define WRITE_MAC_ENTRY 2 -#define ADD_MAC_ENTRY 3 - -/*====vlan commands===*/ - -#define CHANGE_VLAN_CTRL 0 -#define READ_VLAN_ENTRY 1 -#define UPDATE_VLAN_ENTRY 2 -#define CLEAR_VLAN_ENTRY 3 -#define RESET_VLAN_TABLE 4 -#define ADD_VLAN_ENTRY 5 - -/* -** MDIO constants. -*/ - -#define MDIO_BASE_STATUS_REG 0x1 -#define MDIO_BASE_CONTROL_REG 0x0 -#define MDIO_PHY_ID_HIGH_REG 0x2 -#define MDIO_PHY_ID_LOW_REG 0x3 -#define MDIO_BC_NEGOTIATE 0x0200 -#define MDIO_BC_FULL_DUPLEX_MASK 0x0100 -#define MDIO_BC_AUTO_NEG_MASK 0x1000 -#define MDIO_BC_SPEED_SELECT_MASK 0x2000 -#define MDIO_STATUS_100_FD 0x4000 -#define MDIO_STATUS_100_HD 0x2000 -#define MDIO_STATUS_10_FD 0x1000 -#define MDIO_STATUS_10_HD 0x0800 -#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800 -#define MDIO_ADVERTISMENT_REG 0x4 -#define MDIO_ADVERT_100_FD 0x100 -#define MDIO_ADVERT_100_HD 0x080 -#define MDIO_ADVERT_10_FD 0x040 -#define MDIO_ADVERT_10_HD 0x020 -#define MDIO_LINK_UP_MASK 0x4 -#define MDIO_START 0x1 -#define MDIO_READ 0x2 -#define MDIO_WRITE 0x1 -#define MDIO_PREAMBLE 0xfffffffful - -#define PHY_RESET 0x8000 -#define AUTO_NEGOTIATION_ENABLE 0X1000 -#define AUTO_NEGOTIATION_COMPLETE 0x20 -#define RESTART_AUTO_NEGOTIATION 0X200 - - -#define PHY0_ADDR 0 -#define PHY1_ADDR 1 -#define P1M 0 - -#define AMAZON_SW_REG32(reg_num) *((volatile u32*)(reg_num)) - -#define OK 0; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -typedef struct mac_table_entry{ - u64 mac_address:48; - u64 p0:1; - u64 p1:1; - u64 p2:1; - u64 cr:1; - u64 ma_st:3; - u64 res:9; -}_mac_table_entry; - -typedef struct IFX_Switch_VLanTableEntry{ - u32 vlan_id:12; - u32 mp0:1; - u32 mp1:1; - u32 mp2:1; - u32 v:1; - u32 res:16; -}_IFX_Switch_VLanTableEntry; - -typedef struct mac_table_req{ - int cmd; - int index; - u32 data; - u64 entry_value; -}_mac_table_req; - -#else //not CONFIG_CPU_LITTLE_ENDIAN -typedef struct mac_table_entry{ - u64 mac_address:48; - u64 p0:1; - u64 p1:1; - u64 p2:1; - u64 cr:1; - u64 ma_st:3; - u64 res:9; -}_mac_table_entry; - -typedef struct IFX_Switch_VLanTableEntry{ - u32 vlan_id:12; - u32 mp0:1; - u32 mp1:1; - u32 mp2:1; - u32 v:1; - u32 res:16; -}_IFX_Switch_VLanTableEntry; - - -typedef struct mac_table_req{ - int cmd; - int index; - u32 data; - u64 entry_value; -}_mac_table_req; - -#endif //CONFIG_CPU_LITTLE_ENDIAN - - - -typedef struct vlan_req{ - int cmd; - int index; - u32 data; - u32 entry_value; -}_vlan_req; - -typedef struct data_req{ - int index; - u32 value; -}_data_req; - -enum duplex -{ - half, - full, - autoneg -}; - -struct switch_priv { - struct net_device_stats stats; - int rx_packetlen; - u8 *rx_packetdata; - int rx_status; - int tx_packetlen; -#ifdef CONFIG_NET_HW_FLOWCONTROL - int fc_bit; -#endif //CONFIG_NET_HW_FLOWCONTROL - u8 *tx_packetdata; - int tx_status; - struct dma_device_info *dma_device; - struct sk_buff *skb; - spinlock_t lock; - int mdio_phy_addr; - int current_speed; - int current_speed_selection; - int rx_queue_len; - int full_duplex; - enum duplex current_duplex; -}; - -#endif //AMAZON_SW_H - - - - - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_tpe.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_tpe.h deleted file mode 100644 index a64e6f9f80..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_tpe.h +++ /dev/null @@ -1,258 +0,0 @@ -#ifndef AMAZON_TPE_H -#define AMAZON_TPE_H -#include -#include -#include -#include - -#ifdef CONFIG_IFX_ATM_MIB -/* For ATM-MIB lists */ -#include -#endif -#include - -/* CBM Queue arranagement - * Q0: free cells pool - * Q1~ Q15: upstream queues - * Q16: QAM downstream - * Q17~Q31: downstream queues - */ -#define AMAZON_ATM_MAX_QUEUE_NUM 32 -#define AMAZON_ATM_PORT_NUM 2 -#define AMAZON_ATM_FREE_CELLS 4000 -#define AMAZON_ATM_MAX_VCC_NUM (AMAZON_ATM_MAX_QUEUE_NUM/2 - 1) -#define AMAZON_AAL0_SDU (ATM_AAL0_SDU+4) //one more word for status -#define CBM_RX_OFFSET 16 //offset from the same q for tx -#define AMAZON_ATM_OAM_Q_ID 16 -#define AMAZON_ATM_RM_Q_ID 16 -#define AMAZON_ATM_OTHER_Q_ID 16 -#define CBM_DEFAULT_Q_OFFSET 1 -#define HTUTIMEOUT 0xffff//timeoutofhtutocbm -#define QSB_WFQ_NONUBR_MAX 0x3f00 -#define QSB_WFQ_UBR_BYPASS 0x3fff -#define QSB_TP_TS_MAX 65472 -#define QSB_TAUS_MAX 64512 -#define QSB_GCR_MIN 18 -#define HTU_RAM_ACCESS_MAX 1024//maxium time for HTU RAM access - -#define SWIE_LOCK 1 -#define PROC_ATM 1 -#define PROC_MIB 2 -#define PROC_VCC 3 -#define PROC_AAL5 4 -#define PROC_CBM 5 -#define PROC_HTU 6 -#define PROC_QSB 7 -#define PROC_SWIE 8 - -/***************** internal data structure ********************/ -typedef int (*push_back_t)(struct atm_vcc *vcc,struct sk_buff *skb,int err) ; -/* Device private data */ -typedef struct{ - u8 padding_byte; - u32 tx_max_sdu; - u32 rx_max_sdu; - u32 cnt_cpy; //no. of packets that need a copy due to alignment -}amazon_aal5_dev_t; - -typedef struct{ - u32 max_q_off; //maxium queues used in real scenario - u32 nrt_thr; - u32 clp0_thr; - u32 clp1_thr; - u32 free_cell_cnt; -#ifdef CONFIG_USE_VENUS - u8 * qd_addr_free; //to work around a bug, bit15 of QDOFF address should be 1 -#endif - u8 * qd_addr; - u8 * mem_addr; - u8 allocated; -}amazon_cbm_dev_t; - -typedef struct{ - -}amazon_htu_dev_t; - -typedef struct{ - u32 tau; //cell delay variation due to concurrency(?) - u32 tstepc; //time step, all legal values are 1,2,4 - u32 sbl; //scheduler burse length (for PHY) -}amazon_qsb_dev_t; - -typedef struct{ - u32 qid; //QID of the current extraction queue - struct semaphore in_sem; // Software-Insertion semaphore - volatile long lock; //lock that avoids race contions between SWIN and SWEX - wait_queue_head_t sleep; //wait queue for SWIE and SWEX - u32 sw; //status word -}amazon_swie_dev_t; - -//AAL5 MIB Counter -typedef struct{ - u32 tx,rx; //number AAL5 CPCS PDU from/to higher-layer - u32 tx_err,rx_err; //ifInErrors and ifOutErros - u32 tx_drop,rx_drop; //discarded received packets due to mm shortage - u32 htu_unp; //number of unknown received cells - u32 rx_cnt_h; //number of octets received, high 32 bits - u32 rx_cnt_l; //number of octets received, low 32 bits - u32 tx_cnt_h; //number of octets transmitted, high 32 bits - u32 tx_cnt_l; //number of octets transmitted, low 32 bits - u32 tx_ppd; //number of cells for AAL5 upstream PPD discards - u64 rx_cells; //number of cells for downstream - u64 tx_cells; //number of cells for upstream - u32 rx_err_cells; //number of cells dropped due to uncorrectable HEC errors -}amazon_mib_counter_t; - - - -typedef enum {QS_PKT,QS_LEN,QS_ERR,QS_HW_DROP,QS_SW_DROP,QS_MAX} qs_t; -//queue statics no. of packet received / sent -//queue statics no. of bytes received / sent -//queue statics no. of packets with error -//queue statics no. of packets dropped by hw -//queue statics no. of packets dropped by sw - -typedef struct{ - push_back_t push; //call back function - struct atm_vcc * vcc; //opened vcc - struct timeval access_time; //time when last F4/F5 user cells arrive - int free; //whether this queue is occupied, 0: occupied, 1: free - u32 aal5VccCrcErrors; //MIB counter - u32 aal5VccOverSizedSDUs; //MIB counter - -#if defined(AMAZON_ATM_DEBUG) || defined (CONFIG_IFX_ATM_MIB) - u32 qs[QS_MAX]; -#endif -}amazon_atm_queue_t; - - -typedef struct{ - int enable; //enable / disable - u32 max_conn; //maximum number of connections per port - u32 tx_max_cr; //Remaining cellrate for this device for tx direction - u32 tx_rem_cr; //Remaining cellrate for this device for tx direction - u32 tx_cur_cr; //Current cellrate for this device for tx direction -}amazon_atm_port_t; - -typedef struct{ - amazon_aal5_dev_t aal5; - amazon_cbm_dev_t cbm; - amazon_htu_dev_t htu; - amazon_qsb_dev_t qsb; - amazon_swie_dev_t swie; - amazon_mib_counter_t mib_counter; - amazon_atm_queue_t queues[AMAZON_ATM_MAX_QUEUE_NUM]; - amazon_atm_port_t ports[AMAZON_ATM_PORT_NUM]; - atomic_t dma_tx_free_0;//TX_CH0 has availabe descriptors -} amazon_atm_dev_t; - -struct oam_last_activity{ - u8 vpi; //vpi for this connection - u16 vci; //vci for t his connection - struct timeval stamp; //time when last F4/F5 user cells arrive - struct oam_last_activity * next;//for link list purpose -}; - -typedef union{ -#ifdef CONFIG_CPU_LITTLE_ENDIAN - struct{ - u32 tprs :16; - u32 twfq :14; - u32 vbr :1; - u32 reserved :1; - }bit; - u32 w0; -#else - struct{ - u32 reserved :1; - u32 vbr :1; - u32 twfq :14; - u32 tprs :16; - }bit; - u32 w0; -#endif - -}qsb_qptl_t; - -typedef union{ -#ifdef CONFIG_CPU_LITTLE_ENDIAN - struct{ - u32 ts :16; - u32 taus :16; - }bit; - u32 w0; -#else - struct{ - u32 taus :16; - u32 ts :16; - }bit; - u32 w0; -#endif -}qsb_qvpt_t; - - - -struct amazon_atm_cell_header { -#ifdef CONFIG_CPU_LITTLE_ENDIAN - struct{ - u32 clp :1; // Cell Loss Priority - u32 pti :3; // Payload Type Identifier - u32 vci :16; // Virtual Channel Identifier - u32 vpi :8; // Vitual Path Identifier - u32 gfc :4; // Generic Flow Control - }bit; -#else - struct{ - u32 gfc :4; // Generic Flow Control - u32 vpi :8; // Vitual Path Identifier - u32 vci :16; // Virtual Channel Identifier - u32 pti :3; // Payload Type Identifier - u32 clp :1; // Cell Loss Priority - }bit; -#endif -}; - - -/************************ Function Declarations **************************/ -amazon_atm_dev_t * amazon_atm_create(void); -int amazon_atm_open(struct atm_vcc *vcc,push_back_t); -int amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb); -int amazon_atm_send_oam(struct atm_vcc *vcc,void *cell, int flags); -void amazon_atm_close(struct atm_vcc *vcc); -void amazon_atm_cleanup(void); -const struct oam_last_activity* get_oam_time_stamp(void); - -//mib-related -int amazon_atm_cell_mib(atm_cell_ifEntry_t * to,u32 itf); -int amazon_atm_aal5_mib(atm_aal5_ifEntry_t * to); -int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t * to); -int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to); - -#define AMAZON_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data); wmb();} while (0) -#define AMAZON_READ_REGISTER_L(addr) (*((volatile u32*)(addr))) -/******************************* ioctl stuff****************************************/ -#define NUM(dev) (MINOR(dev) & 0xf) -/* - * Ioctl definitions - */ -/* Use 'o' as magic number */ -#define AMAZON_ATM_IOC_MAGIC 'o' -/* MIB_CELL: get atm cell level mib counter - * MIB_AAL5: get aal5 mib counter - * MIB_VCC: get vcc mib counter - */ -typedef struct{ - int vpi; - int vci; - atm_aal5_vcc_t mib_vcc; -}atm_aal5_vcc_x_t; -#define AMAZON_ATM_MIB_CELL _IOWR(AMAZON_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) -#define AMAZON_ATM_MIB_AAL5 _IOWR(AMAZON_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) -#define AMAZON_ATM_MIB_VCC _IOWR(AMAZON_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) -#define AMAZON_ATM_IOC_MAXNR 3 - -//sockopt -#define SO_AMAZON_ATM_MIB_VCC __SO_ENCODE(SOL_ATM,5,atm_aal5_vcc_t) - -#endif // AMAZON_TPE_H - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_wdt.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_wdt.h deleted file mode 100644 index 775dabccfb..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_wdt.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef AMAZON_WDT_H -#define AMAZON_WDT_H -#ifdef __KERNEL__ -typedef struct wdt_dev{ - char name[16]; - int major; - int minor; - - int full; - char buff[10]; -}wdt_dev; -#define AMAZON_WDT_REG32(addr) (*((volatile u32*)(addr))) -#endif //__KERNEL__ - -//AMAZON_WDT_IOC_START: start the WDT timer (must provide a initial timeout value) -//AMAZON_WDT_IOC_STOP: stop the WDT -//AMAZON_WDT_IOC_PING: reload the timer to initial value (must happend after a AMAZON_WDT_IOC_START) -#define AMAZON_WDT_IOC_MAGIC 0xc0 -#define AMAZON_WDT_IOC_START _IOW( AMAZON_WDT_IOC_MAGIC,0, int) -#define AMAZON_WDT_IOC_STOP _IO( AMAZON_WDT_IOC_MAGIC,1) -#define AMAZON_WDT_IOC_PING _IO( AMAZON_WDT_IOC_MAGIC,2) - -#endif //AMAZON_WDT_H diff --git a/target/linux/amazon/files/include/asm-mips/amazon/atm_defines.h b/target/linux/amazon/files/include/asm-mips/amazon/atm_defines.h deleted file mode 100644 index 8adda20051..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/atm_defines.h +++ /dev/null @@ -1,540 +0,0 @@ -#ifndef ATM_DEFINES_H -#define ATM_DEFINES_H - -//Registers Base Address -#define IO_BASE_ADDR 0xA0000000 -#define AAL5_BASE_ADDRESS 0x10104400+IO_BASE_ADDR -#define CBM_BASE_ADDRESS 0x10104000+IO_BASE_ADDR -#define HTU_BASE_ADDRESS 0x10105100+IO_BASE_ADDR -#define QSB_BASE_ADDRESS 0x10105000+IO_BASE_ADDR -#define SWIE_BASE_ADDRESS 0x10105200+IO_BASE_ADDR - -//AAL5 Registers -#define AAL5_SISR0_ADDR AAL5_BASE_ADDRESS+0x20 -#define AAL5_SIMR0_ADDR AAL5_BASE_ADDRESS+0x24 -#define AAL5_SISR1_ADDR AAL5_BASE_ADDRESS+0x28 -#define AAL5_SIMR1_ADDR AAL5_BASE_ADDRESS+0x2C -#define AAL5_SMFL_ADDR AAL5_BASE_ADDRESS+0x30 -#define AAL5_SATMHD_ADDR AAL5_BASE_ADDRESS+0x34 -#define AAL5_SCON_ADDR AAL5_BASE_ADDRESS+0x38 -#define AAL5_SCMD_ADDR AAL5_BASE_ADDRESS+0x3C -#define AAL5_RISR0_ADDR AAL5_BASE_ADDRESS+0x40 -#define AAL5_RIMR0_ADDR AAL5_BASE_ADDRESS+0x44 -#define AAL5_RISR1_ADDR AAL5_BASE_ADDRESS+0x48 -#define AAL5_RIMR1_ADDR AAL5_BASE_ADDRESS+0x4C -#define AAL5_RMFL_ADDR AAL5_BASE_ADDRESS+0x50 -#define AAL5_RINTINF0_ADDR AAL5_BASE_ADDRESS+0x54 -#define AAL5_RINTINF1_ADDR AAL5_BASE_ADDRESS+0x58 -#define AAL5_RES5C_ADDR AAL5_BASE_ADDRESS+0x5C -#define AAL5_RIOL_ADDR AAL5_BASE_ADDRESS+0x60 -#define AAL5_RIOM_ADDR AAL5_BASE_ADDRESS+0x64 -#define AAL5_SOOL_ADDR AAL5_BASE_ADDRESS+0x68 -#define AAL5_SOOM_ADDR AAL5_BASE_ADDRESS+0x6C -#define AAL5_RES70_ADDR AAL5_BASE_ADDRESS+0x70 -#define AAL5_RES74_ADDR AAL5_BASE_ADDRESS+0x74 -#define AAL5_RES78_ADDR AAL5_BASE_ADDRESS+0x78 -#define AAL5_RES7C_ADDR AAL5_BASE_ADDRESS+0x7C -#define AAL5_RES80_ADDR AAL5_BASE_ADDRESS+0x80 -#define AAL5_RES84_ADDR AAL5_BASE_ADDRESS+0x84 -#define AAL5_RES88_ADDR AAL5_BASE_ADDRESS+0x88 -#define AAL5_RES8C_ADDR AAL5_BASE_ADDRESS+0x8C -#define AAL5_RES90_ADDR AAL5_BASE_ADDRESS+0x90 -#define AAL5_RES94_ADDR AAL5_BASE_ADDRESS+0x94 -#define AAL5_RES98_ADDR AAL5_BASE_ADDRESS+0x98 -#define AAL5_RES9C_ADDR AAL5_BASE_ADDRESS+0x9C -#define AAL5_RESA0_ADDR AAL5_BASE_ADDRESS+0xA0 -#define AAL5_RESA4_ADDR AAL5_BASE_ADDRESS+0xA4 -#define AAL5_RESA8_ADDR AAL5_BASE_ADDRESS+0xA8 -#define AAL5_RESAC_ADDR AAL5_BASE_ADDRESS+0xAC -#define AAL5_RESB0_ADDR AAL5_BASE_ADDRESS+0xB0 -#define AAL5_RESB4_ADDR AAL5_BASE_ADDRESS+0xB4 -#define AAL5_RESB8_ADDR AAL5_BASE_ADDRESS+0xB8 -#define AAL5_RESBC_ADDR AAL5_BASE_ADDRESS+0xBC -#define AAL5_RESC0_ADDR AAL5_BASE_ADDRESS+0xC0 -#define AAL5_RESC4_ADDR AAL5_BASE_ADDRESS+0xC4 -#define AAL5_RESC8_ADDR AAL5_BASE_ADDRESS+0xC8 -#define AAL5_RESCC_ADDR AAL5_BASE_ADDRESS+0xCC -#define AAL5_RESD0_ADDR AAL5_BASE_ADDRESS+0xD0 -#define AAL5_RESD4_ADDR AAL5_BASE_ADDRESS+0xD4 -#define AAL5_RESD8_ADDR AAL5_BASE_ADDRESS+0xD8 -#define AAL5_RESDC_ADDR AAL5_BASE_ADDRESS+0xDC -#define AAL5_RESE0_ADDR AAL5_BASE_ADDRESS+0xE0 -#define AAL5_RESE4_ADDR AAL5_BASE_ADDRESS+0xE4 -#define AAL5_RESE8_ADDR AAL5_BASE_ADDRESS+0xE8 -#define AAL5_RESEC_ADDR AAL5_BASE_ADDRESS+0xEC -#define AAL5_SSRC0_ADDR AAL5_BASE_ADDRESS+0xF0 -#define AAL5_SSRC1_ADDR AAL5_BASE_ADDRESS+0xF4 -#define AAL5_RSRC0_ADDR AAL5_BASE_ADDRESS+0xF8 -#define AAL5_RSRC1_ADDR AAL5_BASE_ADDRESS+0xFC - -#define AAL5S_ISR_QID_MASK 0xFF000000 -#define AAL5S_ISR_SAB 0x00000100 -#define AAL5S_ISR_SE 0x00000080 -#define AAL5S_ISR_MFLE 0x00000040 -#define AAL5S_ISR_SBE0 0x00000020 -#define AAL5S_ISR_SEG0 0x00000010 -#define AAL5S_ISR_TAB 0x00000004 - -#define AAL5_SIMR_MASK 0x000001c7 -#define AAL5_SIMR_SAB 0x00000100 -#define AAL5_SIMR_SE 0x00000080 -#define AAL5_SIMR_MFLE 0x00000040 -#define AAL5_SIMR_TAB 0x00000004 -#define AAL5_SIMR_SBE0 0x00000002 -#define AAL5_SIMR_SEG0 0x00000001 - -#define AAL5_SCMD_SEQCOUNT_MASK 0x0000ff00 -#define AAL5_SCMD_MODE_POLL 0x00000008 -#define AAL5_SCMD_MODE_COUNT 0x00000000 -#define AAL5_SCMD_AS 0x00000004 -#define AAL5_SCMD_SS 0x00000002 -#define AAL5_SCMD_AR 0x00000001 - -#define AAL5R_ISR_CID_MASK 0xFF000000//ConnectionID -#define AAL5R_ISR_DBC_MASK 0x00FF0000//DiscardedByteCounter -#define AAL5R_ISR_END 0x00002000//End -#define AAL5R_ISR_ICID 0x00001000//InvalidConnectionID -#define AAL5R_ISR_CLP 0x00000800//CellLossPriority -#define AAL5R_ISR_CGST 0x00000400//Congestion -#define AAL5R_ISR_UUE 0x00000200//CPCSUUError -#define AAL5R_ISR_CPIE 0x00000100//CPIError -#define AAL5R_ISR_FE 0x00000080//FrameEnd -#define AAL5R_ISR_MFLE 0x00000040//MaximumFrameLengthExceeded -#define AAL5R_ISR_DBCE 0x00000020//DiscardedByteCounterExceeded -#define AAL5R_ISR_CRC 0x00000010//CRCError -#define AAL5R_ISR_ILEN 0x00000008//InvalidLength -#define AAL5R_ISR_RAB 0x00000004//ReceiveAbort - -#define AAL5_RIMR1_MASK 0x00003ffc -#define AAL5_RIMR1_END 0x00002000//End -#define AAL5_RIMR1_ICID 0x00001000//InvalidConnectionID -#define AAL5_RIMR1_CLP 0x00000800//CellLossPriority -#define AAL5_RIMR1_CGST 0x00000400//Congestion -#define AAL5_RIMR1_UUE 0x00000200//CPCSUUError -#define AAL5_RIMR1_CPIE 0x00000100//CPIError -#define AAL5_RIMR1_FE 0x00000080//FrameEnd -#define AAL5_RIMR1_MFLE 0x00000040//MaximumFrameLengthExceeded -#define AAL5_RIMR1_DBCE 0x00000020//DiscardedByteCounterExceeded -#define AAL5_RIMR1_CRC 0x00000010//CRCError -#define AAL5_RIMR1_ILEN 0x00000008//InvalidLength -#define AAL5_RIMR1_RAB 0x00000004//ReceiveAbort - -//AAL5 Reassambly Errors -#define AAL5_STW1_MASK 0x33//Error mask -#define AAL5_STW0_MASK 0x5c//Error mask -#define AAL5_STW0_BE 0x3//padding bytes mask -#define AAL5_STW1_CBM 0x20//Transfer from CBM to A5R abnormally ended -#define AAL5_STW1_CH 0x10//Invalid Channel number error -#define AAL5_STW1_CLP 0x8//CLP value of cells in packet is 1 -#define AAL5_STW1_CG 0x4//Cell in packet expired congestion -#define AAL5_STW1_UU 0x2//CPCS-UU value error -#define AAL5_STW1_CPI 0x1//CPI value error -#define AAL5_STW0_FE 0x80//Frame end -#define AAL5_STW0_MFL 0x40//Maximum frame length error -#define AAL5_STW0_CRC 0x10//CRC error -#define AAL5_STW0_IL 0x8//Invalid length -#define AAL5_STW0_RA 0x4//Received abort - - - -//CBM Registers -#define CBM_NRTTHR_ADDR CBM_BASE_ADDRESS+0x10//NonRealTimeThreshold -#define CBM_CLP0THR_ADDR CBM_BASE_ADDRESS+0x14//CLP0Threshold -#define CBM_CLP1THR_ADDR CBM_BASE_ADDRESS+0x18//CLP1Threshold -#define CBM_QDOFF_ADDR CBM_BASE_ADDRESS+0x1C//QueueDescriptorOffset -#define CBM_CFG_ADDR CBM_BASE_ADDRESS+0x20//Configuration -#define CBM_HWEXPAR0_ADDR CBM_BASE_ADDRESS+0x24//HWExtractParameter0 -#define CBM_RES28_ADDR CBM_BASE_ADDRESS+0x28 -#define CBM_WMSTAT0_ADDR CBM_BASE_ADDRESS+0x2C -#define CBM_HWEXCMD_ADDR CBM_BASE_ADDRESS+0x30//HWExtractCommand0 -#define CBM_RES34_ADDR CBM_BASE_ADDRESS+0x34 -#define CBM_HWEXSTAT0_ADDR CBM_BASE_ADDRESS+0x38//HWExtractStatus0 -#define CBM_RES3C_ADDR CBM_BASE_ADDRESS+0x3C -#define CBM_RES40_ADDR CBM_BASE_ADDRESS+0x40 -#define CBM_CNT_ADDR CBM_BASE_ADDRESS+0x44//CellCount -#define CBM_RES48_ADDR CBM_BASE_ADDRESS+0x48 -#define CBM_LFR_ADDR CBM_BASE_ADDRESS+0x4C//PointertolastCellinfreeCellQueue -#define CBM_FFR_ADDR CBM_BASE_ADDRESS+0x50//PointertofirstCellinfreeCellQueue -#define CBM_RES54_ADDR CBM_BASE_ADDRESS+0x54 -#define CBM_RES58_ADDR CBM_BASE_ADDRESS+0x58 -#define CBM_RES5C_ADDR CBM_BASE_ADDRESS+0x5C -#define CBM_RES60_ADDR CBM_BASE_ADDRESS+0x60 -#define CBM_RES64_ADDR CBM_BASE_ADDRESS+0x64 -#define CBM_RES68_ADDR CBM_BASE_ADDRESS+0x68 -#define CBM_RES6C_ADDR CBM_BASE_ADDRESS+0x6C -#define CBM_RES70_ADDR CBM_BASE_ADDRESS+0x70 -#define CBM_RES74_ADDR CBM_BASE_ADDRESS+0x74 -#define CBM_RES78_ADDR CBM_BASE_ADDRESS+0x78 -#define CBM_RES7C_ADDR CBM_BASE_ADDRESS+0x7C -#define CBM_RES80_ADDR CBM_BASE_ADDRESS+0x80 -#define CBM_RES84_ADDR CBM_BASE_ADDRESS+0x84 -#define CBM_RES88_ADDR CBM_BASE_ADDRESS+0x88 -#define CBM_RES8C_ADDR CBM_BASE_ADDRESS+0x8C -#define CBM_RES90_ADDR CBM_BASE_ADDRESS+0x90 -#define CBM_RES94_ADDR CBM_BASE_ADDRESS+0x94 -#define CBM_RES98_ADDR CBM_BASE_ADDRESS+0x98 -#define CBM_RES9C_ADDR CBM_BASE_ADDRESS+0x9C -#define CBM_RESA0_ADDR CBM_BASE_ADDRESS+0xA0 -#define CBM_RESA4_ADDR CBM_BASE_ADDRESS+0xA4 -#define CBM_RESA8_ADDR CBM_BASE_ADDRESS+0xA8 -#define CBM_RESAC_ADDR CBM_BASE_ADDRESS+0xAC -#define CBM_RESB0_ADDR CBM_BASE_ADDRESS+0xB0 -#define CBM_RESB4_ADDR CBM_BASE_ADDRESS+0xB4 -#define CBM_RESB8_ADDR CBM_BASE_ADDRESS+0xB8 -#define CBM_RESBC_ADDR CBM_BASE_ADDRESS+0xBC -#define CBM_INTINF0_ADDR CBM_BASE_ADDRESS+0xC0//InterruptInfo0 -#define CBM_INTCMD_ADDR CBM_BASE_ADDRESS+0xC4//InterruptCommand0 -#define CBM_IMR0_ADDR CBM_BASE_ADDRESS+0xC8//InterruptMask -#define CBM_SRC0_ADDR CBM_BASE_ADDRESS+0xCC//ServiceRequestControl -#define CBM_RESD0_ADDR CBM_BASE_ADDRESS+0xD0 -#define CBM_RESD4_ADDR CBM_BASE_ADDRESS+0xD4 -#define CBM_RESD8_ADDR CBM_BASE_ADDRESS+0xD8 -#define CBM_RESDC_ADDR CBM_BASE_ADDRESS+0xDC -#define CBM_RESE0_ADDR CBM_BASE_ADDRESS+0xE0 -#define CBM_AAL5IDIS_ADDR CBM_BASE_ADDRESS+0xE4//MIB-No.EPDdiscardedpacketsupstream -#define CBM_AAL5ODIS_ADDR CBM_BASE_ADDRESS+0xE8//MIB-No.PPDdiscardedpacketsupstream -#define CBM_RESEC_ADDR CBM_BASE_ADDRESS+0xEC -#define CBM_RESF0_ADDR CBM_BASE_ADDRESS+0xF0 -#define CBM_RESF4_ADDR CBM_BASE_ADDRESS+0xF4 -#define CBM_RESF8_ADDR CBM_BASE_ADDRESS+0xF8 -#define CBM_RESFC_ADDR CBM_BASE_ADDRESS+0xFC - -//CBMCFG -#define CBM_CFG_INTLCK0EN 0x00000008 -#define CBM_CFG_INT0HLT 0x00000004 -#define CBM_CFG_START 0x00000001 - -#define CBM_HWEXPAR_PN_A5 0x00002000 -#define CBM_HWEXPAR_PN_CM 0x00000000 -#define CBM_HWEXPAR_SUBADD_PORTMASK 0x00000070 -#define CBM_HWEXPAR_SUBADD_ADU 0x00000000 -#define CBM_HWEXPAR_SUBADD_AAL2 0x00000080 -#define CBM_HWEXPAR_SUBADD_SWIE 0x00000100 - -#define CBM_HWEXCMD_SFE2 0x00000100 -#define CBM_HWEXCMD_FE2 0x00000080 -#define CBM_HWEXCMD_SCE2 0x00000040 -#define CBM_HWEXCMD_SFE1 0x00000020 -#define CBM_HWEXCMD_FE1 0x00000010 -#define CBM_HWEXCMD_SCE1 0x00000008 -#define CBM_HWEXCMD_SFE0 0x00000004 -#define CBM_HWEXCMD_FE0 0x00000002 -#define CBM_HWEXCMD_SCE0 0x00000001 - -#define CBM_INTINF0_QID_MASK 0xFF000000 -#define CBM_INTINF0_ORIGIN_MASK 0x00F00000 -#define CBM_INTINF0_EF 0x00004000 -#define CBM_INTINF0_ACA 0x00002000 -#define CBM_INTINF0_ERR 0x00001000 -#define CBM_INTINF0_DISC 0x00000800 -#define CBM_INTINF0_QSBV 0x00000400 -#define CBM_INTINF0_Q0E 0x00000200 -#define CBM_INTINF0_Q0I 0x00000100 -#define CBM_INTINF0_RDE 0x00000080 -#define CBM_INTINF0_OPF 0x00000040 -#define CBM_INTINF0_NFCA 0x00000020 -#define CBM_INTINF0_CLP1TR 0x00000010 -#define CBM_INTINF0_CLP0TR 0x00000008 -#define CBM_INTINF0_NRTTR 0x00000004 -#define CBM_INTINF0_QFD 0x00000002 -#define CBM_INTINF0_QTR 0x00000001 -#define CBM_INTINF0_QID_SHIFT 24 -//CBM QD Word 3 -#define CBM_QD_W3_QOS_0 0x00000000 -#define CBM_QD_W3_QOS_1 0x40000000 -#define CBM_QD_W3_QOS_2 0x80000000 -#define CBM_QD_W3_QOS_3 0xc0000000 - -#define CBM_QD_W3_DIR_UP 0x20000000 -#define CBM_QD_W3_DIR_DOWN 0x00000000 - -#define CBM_QD_W3_CLPt 0x10000000 -#define CBM_QD_W3_RT 0x08000000 -#define CBM_QD_W3_AAL5 0x04000000 - -#define CBM_QD_W3_INT_NOINT 0x00000000 -#define CBM_QD_W3_INT_ACA 0x01000000 -#define CBM_QD_W3_INT_EOF 0x02000000 -#define CBM_QD_W3_INT_BOTH 0x03000000 - -#define CBM_QD_W3_THRESHOLD_MASK 0x00ff0000 -#define CBM_QD_W3_WM_EN 0x00000010 -#define CBM_QD_W3_HCR 0x00000008 -#define CBM_QD_W3_SBID_MASK 0x00000001 - -#define CBM_QD_W3_THRESHOLD_SHIFT 16 - -//WATER MARK STATUS -#define CBM_WM_NRT_MASK 0x00040000 -#define CBM_WM_CLP0_MASK 0x00020000 -#define CBM_WM_CLP1_MASK 0x00010000 - -//CBMNRTTHR, CBMCLP0THR, CBMCLP0THR -#define CBM_NRT_WM_NONE 0x00000000//no water mark -#define CBM_WM_3_1 0x00010000//3/4 to set, 1/4 to release -#define CBM_WM_3_2 0x00020000//3/4 to set, 2/4 to release -#define CBM_WM_2_1 0x00030000//2/4 to set, 1/4 to release -#define CBM_THR_MASK 0x0000FFFF - -#define CBM_IMR_MASK 0x0000fbff -#define CBM_IMR_reserved 0xFFFF0400 -#define CBM_IMR_RFULL 0x00008000//EndofFrame -#define CBM_IMR_EF 0x00004000//EndofFrame -#define CBM_IMR_ACA 0x00002000//AnyCellArrived -#define CBM_IMR_ERR 0x00001000//FPI Error -#define CBM_IMR_DISC 0x00000800//Discard -#define CBM_IMR_reserved1 0x00000400//reserved -#define CBM_IMR_Q0E 0x00000200//Queue0Extract -#define CBM_IMR_Q0I 0x00000100//Queue0Insert -#define CBM_IMR_RDE 0x00000080//ReadEmptyQueue -#define CBM_IMR_OPF 0x00000040//OncePerFrame -#define CBM_IMR_NFCA 0x00000020//NoFreeCellAvailable -#define CBM_IMR_CLP1TR 0x00000010//CLP1ThresholdReached -#define CBM_IMR_CLP0TR 0x00000008//CLP0ThresholdReached -#define CBM_IMR_NRTTR 0x00000004//NonRealTimeThresholdReached -#define CBM_IMR_QFD 0x00000002//QueueFrameDiscard -#define CBM_IMR_QTR 0x00000001//QueueThresholdReached - -#define CBM_EXSTAT_FB 0x00000010 -#define CBM_EXSTAT_SCB 0x00000008 -#define CBM_EXSTAT_Q0 0x00000004 -#define CBM_EXSTAT_RDE 0x00000002 -#define CBM_EXSTAT_QV 0x00000001 - -//HTU Registers -#define HTU_RX0_ADDR HTU_BASE_ADDRESS+0x10 -#define HTU_RX1_ADDR HTU_BASE_ADDRESS+0x14 -#define HTU_RES18_ADDR HTU_BASE_ADDRESS+0x18 -#define HTU_RES1C_ADDR HTU_BASE_ADDRESS+0x1C -#define HTU_RES20_ADDR HTU_BASE_ADDRESS+0x20 -#define HTU_RES24_ADDR HTU_BASE_ADDRESS+0x24 -#define HTU_RES28_ADDR HTU_BASE_ADDRESS+0x28 -#define HTU_RES2C_ADDR HTU_BASE_ADDRESS+0x2C -#define HTU_PCF0PAT_ADDR HTU_BASE_ADDRESS+0x30 -#define HTU_PCF1PAT_ADDR HTU_BASE_ADDRESS+0x34 -#define HTU_RES38_ADDR HTU_BASE_ADDRESS+0x38 -#define HTU_RES3C_ADDR HTU_BASE_ADDRESS+0x3C -#define HTU_RES40_ADDR HTU_BASE_ADDRESS+0x40 -#define HTU_RES44_ADDR HTU_BASE_ADDRESS+0x44 -#define HTU_RES48_ADDR HTU_BASE_ADDRESS+0x48 -#define HTU_RES4C_ADDR HTU_BASE_ADDRESS+0x4C -#define HTU_PCF0MASK_ADDR HTU_BASE_ADDRESS+0x50 -#define HTU_PCF1MASK_ADDR HTU_BASE_ADDRESS+0x54 -#define HTU_RES58_ADDR HTU_BASE_ADDRESS+0x58 -#define HTU_RES5C_ADDR HTU_BASE_ADDRESS+0x5C -#define HTU_RES60_ADDR HTU_BASE_ADDRESS+0x60 -#define HTU_RES64_ADDR HTU_BASE_ADDRESS+0x64 -#define HTU_RES68_ADDR HTU_BASE_ADDRESS+0x68 -#define HTU_RES6C_ADDR HTU_BASE_ADDRESS+0x6C -#define HTU_TIMEOUT_ADDR HTU_BASE_ADDRESS+0x70 -#define HTU_DESTOAM_ADDR HTU_BASE_ADDRESS+0x74 -#define HTU_DESTRM_ADDR HTU_BASE_ADDRESS+0x78 -#define HTU_DESTOTHER_ADDR HTU_BASE_ADDRESS+0x7C -#define HTU_CFG_ADDR HTU_BASE_ADDRESS+0x80 -#define HTU_RES84_ADDR HTU_BASE_ADDRESS+0x84 -#define HTU_RES88_ADDR HTU_BASE_ADDRESS+0x88 -#define HTU_RES8C_ADDR HTU_BASE_ADDRESS+0x8C -#define HTU_INFNOENTRY_ADDR HTU_BASE_ADDRESS+0x90 -#define HTU_INFTIMEOUT_ADDR HTU_BASE_ADDRESS+0x94 -#define HTU_RES98_STAT HTU_BASE_ADDRESS+0x98 -#define HTU_RES9C_ADDR HTU_BASE_ADDRESS+0x9C -#define HTU_MIBCIUP HTU_BASE_ADDRESS+0xA0//MIB Counter In Unknown Protoc Register -#define HTU_CNTTIMEOUT_ADDR HTU_BASE_ADDRESS+0xA4 -#define HTU_RESA8_ADDR HTU_BASE_ADDRESS+0xA8 -#define HTU_RESAC_ADDR HTU_BASE_ADDRESS+0xAC -#define HTU_RAMADDR_ADDR HTU_BASE_ADDRESS+0xB0 -#define HTU_RAMCMD_ADDR HTU_BASE_ADDRESS+0xB4 -#define HTU_RAMSTAT_ADDR HTU_BASE_ADDRESS+0xB8 -#define HTU_RESBC_ADDR HTU_BASE_ADDRESS+0xBC -#define HTU_RAMDAT1_ADDR HTU_BASE_ADDRESS+0xC0 -#define HTU_RAMDAT2_ADDR HTU_BASE_ADDRESS+0xC4 -#define HTU_RESCC_ADDR HTU_BASE_ADDRESS+0xCC -#define HTU_RESD0_ADDR HTU_BASE_ADDRESS+0xD0 -#define HTU_RESD4_ADDR HTU_BASE_ADDRESS+0xD4 -#define HTU_RESD8_ADDR HTU_BASE_ADDRESS+0xD8 -#define HTU_RESDC_ADDR HTU_BASE_ADDRESS+0xDC -#define HTU_RESE0_ADDR HTU_BASE_ADDRESS+0xE0 -#define HTU_RESE4_ADDR HTU_BASE_ADDRESS+0xE4 -#define HTU_IMR0_ADDR HTU_BASE_ADDRESS+0xE8 -#define HTU_RESEC_ADDR HTU_BASE_ADDRESS+0xEC -#define HTU_ISR0_ADDR HTU_BASE_ADDRESS+0xF0 -#define HTU_RESF4_ADDR HTU_BASE_ADDRESS+0xF4 -#define HTU_SRC0_ADDR HTU_BASE_ADDRESS+0xF8 -#define HTU_RESFC_ADDR HTU_BASE_ADDRESS+0xFC - -//HTU_CFG -#define HTU_CFG_START 0x00000001 - -#define HTU_RAMCMD_RMW 0x00000004 -#define HTU_RAMCMD_RD 0x00000002 -#define HTU_RAMCMD_WR 0x00000001 - -#define HTU_RAMDAT1_VCON 0x00000080//validconnection -#define HTU_RAMDAT1_VCT 0x00000040//vcivalueistransparent -#define HTU_RAMDAT1_QIDS 0x00000020//qid selects a cell in cbm -#define HTU_RAMDAT1_VCI3 0x00000010//vci3->oamqueue -#define HTU_RAMDAT1_VCI4 0x00000008//vci4->oamqueue -#define HTU_RAMDAT1_VCI6 0x00000004//vci6->rmqueue -#define HTU_RAMDAT1_PTI4 0x00000002//pti4->oamqueue -#define HTU_RAMDAT1_PTI5 0x00000001//pti5->oamqueue - -#define HTU_RAMDAT2_PTI6 0x00000800 -#define HTU_RAMDAT2_PTI7 0x00000400 -#define HTU_RAMDAT2_F4U 0x00000200 -#define HTU_RAMDAT2_F5U 0x00000100 -#define HTU_RAMDAT2_QID_MASK 0x000000ff - -#define HTU_ISR_NE 0x00000001 -#define HTU_ISR_TORD 0x00000002 -#define HTU_ISR_IT 0x00000008 -#define HTU_ISR_OTOC 0x00000010 -#define HTU_ISR_ONEC 0x00000020 -#define HTU_ISR_PNE 0x00000040 -#define HTU_ISR_PT 0x00000080 -#define HTU_ISR_MASK 0x000000ff - - -//QSB Registers -#define QSB_BIP0_ADDR QSB_BASE_ADDRESS+0x00 -#define QSB_BIP1_ADDR QSB_BASE_ADDRESS+0x04 -#define QSB_BIP2_ADDR QSB_BASE_ADDRESS+0x08 -#define QSB_BIP3_ADDR QSB_BASE_ADDRESS+0x0C -#define QSB_RSVP_ADDR QSB_BASE_ADDRESS+0x10 -#define QSB_TNOW_ADDR QSB_BASE_ADDRESS+0x14 -#define QSB_TNOWCYC_ADDR QSB_BASE_ADDRESS+0x18 -#define QSB_TAU_ADDR QSB_BASE_ADDRESS+0x1C -#define QSB_L1BRS_ADDR QSB_BASE_ADDRESS+0x20 -#define QSB_SBL_ADDR QSB_BASE_ADDRESS+0x24 -#define QSB_CONFIG_ADDR QSB_BASE_ADDRESS+0x28 -#define QSB_RTM_ADDR QSB_BASE_ADDRESS+0x2C -#define QSB_RTD_ADDR QSB_BASE_ADDRESS+0x30 -#define QSB_RAMAC_ADDR QSB_BASE_ADDRESS+0x34 -#define QSB_ISR_ADDR QSB_BASE_ADDRESS+0x38 -#define QSB_IMR_ADDR QSB_BASE_ADDRESS+0x3C -#define QSB_SRC_ADDR QSB_BASE_ADDRESS+0x40 - -#define QSB_TABLESEL_QVPT 8 -#define QSB_TABLESEL_QPT 1 -#define QSB_TABLESEL_SCT 2 -#define QSB_TABLESEL_SPT 3 -#define QSB_TABLESEL_CALENDARWFQ 4/*notusedbyFW*/ -#define QSB_TABLESEL_L2WFQ 5/*notusedbyFW*/ -#define QSB_TABLESEL_CALENDARRS 6/*notusedbyFW*/ -#define QSB_TABLESEL_L2BITMAPRS 7/*notusedbyFW*/ -#define QSB_TABLESEL_SHIFT 24 -#define QSB_TWFQ_MASK 0x3FFF0000 -#define QSB_TPRS_MASK 0x0000FFFF -#define QSB_SBID_MASK 0xF -#define QSB_TWFQ_SHIFT 16 -#define QSB_SCDRATE_MASK 0x00007FFF -#define QSB_SBVALID_MASK 0x80000000 - -#define QSB_ISR_WFQLE 0x00000001 -#define QSB_ISR_WFQBE 0x00000002 -#define QSB_ISR_RSLE 0x00000004 -#define QSB_ISR_RSBE 0x00000008 -#define QSB_ISR_MUXOV 0x00000010 -#define QSB_ISR_CDVOV 0x00000020 -#define QSB_ISR_PARAMI 0x00000040 -#define QSB_ISR_SLOSS 0x00000080 -#define QSB_ISR_IIPS 0x00000100 - -#define QSB_IMR_WFQLE 0x00000001 -#define QSB_IMR_WFQBE 0x00000002 -#define QSB_IMR_RSLE 0x00000004 -#define QSB_IMR_RSBE 0x00000008 -#define QSB_IMR_MUXOV 0x00000010 -#define QSB_IMR_CDVOV 0x00000020 -#define QSB_IMR_PARAMI 0x00000040 -#define QSB_IMR_SLOSS 0x00000080 -#define QSB_IMR_IIPS 0x00000100 - -#define QSB_READ 0x0 -#define QSB_WRITE 0x80000000 -#define QSB_READ_ALL 0xFFFFFFFF - -#if 1 //some bug with QSB access mask -#define QSB_QPT_SET_MASK 0x0 -#define QSB_QVPT_SET_MASK 0x0 -#define QSB_SET_SCT_MASK 0x0 -#define QSB_SET_SPT_MASK 0x0 -#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF -#else //some bug with QSB access mask -#define QSB_QPT_SET_MASK 0x80000000 -#define QSB_QVPT_SET_MASK 0x0 -#define QSB_SET_SCT_MASK 0xFFFFFFE0 -#define QSB_SET_SPT_MASK 0x7FF8C000 -#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF -#endif //some bug with QSB access mask - -#define QSB_SPT_SBVALID 0x80000000 - -#define QSB_RAMAC_REG_LOW 0x0 -#define QSB_RAMAC_REG_HIGH 0x00010000 - -#define SRC_SRE_ENABLE 0x1000 -#define SRC_CLRR 0x4000 //request clear bit - - - -//SWIE Registers -#define SWIE_IQID_ADDR SWIE_BASE_ADDRESS+0x0c//SWIEInsertQueueDescriptor -#define SWIE_ICMD_ADDR SWIE_BASE_ADDRESS+0x10//SWIEInsertCommand -#define SWIE_ISTAT_ADDR SWIE_BASE_ADDRESS+0x14//SWIEInsertStatus -#define SWIE_ESTAT_ADDR SWIE_BASE_ADDRESS+0x18//SWIEExtractStatus -#define SWIE_ISRC_ADDR SWIE_BASE_ADDRESS+0x74//SWIEInsertServiceRequestControl -#define SWIE_ESRC_ADDR SWIE_BASE_ADDRESS+0x78//SWIEExtractServiceRequestControl -#define SWIE_ICELL_ADDR SWIE_BASE_ADDRESS+0x80//SWIEInsertCell(0x80-0xb4) -#define SWIE_ECELL_ADDR SWIE_BASE_ADDRESS+0xc0//SWIEExtractCell(0xc0-0xf4) - -#define SWIE_ISTAT_DONE 0x1 -#define SWIE_ESTAT_DONE 0x1 -#define SWIE_ICMD_START 0x00000001//Startcommandforinsertion -#define SWIE_CBM_SCE0 CBM_HWEXCMD_SCE0//CBMcommandforSingle-Cell-Extract -#define SWIE_CBM_PID_SUBADDR 0x00001000//CBMPortIDandSubAddressforUTOPIA - -//Extracted cell format -//52bytes AAL0 PDU + "Input cell additional data"(14bits) -#define SWIE_ADDITION_DATA_MASK 0x7fff -#define SWIE_EPORT_MASK 0x7000//Source ID (000 AUB0, 001 AUB1) -#define SWIE_EF4USER_MASK 0x800 -#define SWIE_EF5USER_MASK 0x400 -#define SWIE_EOAM_MASK 0x200 -#define SWIE_EAUU_MASK 0x100 -#define SWIE_EVCI3_MASK 0x80 -#define SWIE_EVCI4_MASK 0x40 -#define SWIE_EVCI6_MASK 0x20 -#define SWIE_EPTI4_MASK 0x10 -#define SWIE_EPTI5_MASK 0x8 -#define SWIE_EPTI6_MASK 0x4 -#define SWIE_EPTI7_MASK 0x2 -#define SWIE_ECRC10ERROR_MASK 0x1 - -#define CBM_CELL_SIZE 0x40 -#define CBM_QD_SIZE 0x10 -#define AAL5R_TRAILER_LEN 12 -#define AAL5S_INBOUND_HEADER 8 - -//constants -//TODO: to be finalized by system guys -//DMA QOS defined by ATM QoS Service type -#define DMA_RX_CH0 0 -#define DMA_RX_CH1 1 -#define DMA_TX_CH0 0 -#define DMA_TX_CH1 1 -#define CBR_DMA_QOS CBM_QD_W3_QOS_0 -#define VBR_RT_DMA_QOS CBM_QD_W3_QOS_0 -#define VBR_NRT_DMA_QOS CBM_QD_W3_QOS_0 -#define UBR_PLUS_DMA_QOS CBM_QD_W3_QOS_0 -#define UBR_DMA_QOS CBM_QD_W3_QOS_0 - -#define SRC_TOS_MIPS 0 -#define AAL5R_SRPN 0x00000006//a5rneedshigherprioritythanDR -#define AAL5S_SRPN 0x00000005 -#define CBM_MIPS_SRPN 0x00000004 -#define QSB_SRPN 0x00000023 -#define HTU_SRPN1 0x00000022 -#define HTU_SRPN0 0x00000021 - -#endif //ATM_DEFINES_H - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/atm_mib.h b/target/linux/amazon/files/include/asm-mips/amazon/atm_mib.h deleted file mode 100644 index f863342580..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/atm_mib.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef AMAZON_ATM_MIB_H -#define AMAZON_ATM_MIB_H - -#ifdef CONFIG_IFX_ATM_MIB -#include -#ifdef __KERNEL__ -#include -#endif -#endif /* CONFIG_IFX_ATM_MIB */ - -#ifndef __KERNEL__ -#include -typedef unsigned int __u32; -#endif - -typedef struct{ - __u32 ifHCInOctets_h; - __u32 ifHCInOctets_l; - __u32 ifHCOutOctets_h; - __u32 ifHCOutOctets_l; - __u32 ifInErrors; - __u32 ifInUnknownProtos; - __u32 ifOutErrors; -}atm_cell_ifEntry_t; - -typedef struct{ - __u32 ifHCInOctets_h; - __u32 ifHCInOctets_l; - __u32 ifHCOutOctets_h; - __u32 ifHCOutOctets_l; - __u32 ifInUcastPkts; - __u32 ifOutUcastPkts; - __u32 ifInErrors; - __u32 ifInDiscards; - __u32 ifOutErros; - __u32 ifOutDiscards; -}atm_aal5_ifEntry_t; - -typedef struct{ - __u32 aal5VccCrcErrors; - __u32 aal5VccSarTimeOuts;//no timer support yet - __u32 aal5VccOverSizedSDUs; -}atm_aal5_vcc_t; - -#if defined(CONFIG_IFX_ATM_MIB) || defined(IFX_CONFIG_SNMP_ATM_MIB) -/* ATM-MIB data structures */ -typedef struct atmIfConfEntry { - int ifIndex; - int atmInterfaceMaxVpcs; - int atmInterfaceMaxVccs; - int atmInterfaceConfVpcs; - int atmInterfaceConfVccs; - int atmInterfaceMaxActiveVpiBits; - int atmInterfaceMaxActiveVciBits; - int atmInterfaceIlmiVpi; - int atmInterfaceIlmiVci; - int atmInterfaceAddressType; - char atmInterfaceAdminAddress[40]; - unsigned long atmInterfaceMyNeighborIpAddress; - char atmInterfaceMyNeighborIfName[20]; - int atmInterfaceCurrentMaxVpiBits; - int atmInterfaceCurrentMaxVciBits; - char atmInterfaceSubscrAddress[40]; - int flags; -}atmIfConfEntry; - -typedef struct atmTrafficDescParamEntry { - /* Following three parameters are used to update VCC QoS values */ - int ifIndex; - short atmVclvpi; - int atmVclvci; - - unsigned int atmTrafficParamIndex; - unsigned char traffic_class; - int max_pcr; - /* Subramani: Added min_pcr */ - int min_pcr; - int cdv; - int scr; - int mbs; - int atmTrafficRowStatus; - int atmTrafficFrameDiscard; - struct list_head vpivci_head; - struct list_head list; -}atmTrafficDescParamEntry; - - -typedef struct atmVclEntry { - int ifIndex; - short atmVclvpi; - int atmVclvci; - char vpivci[20]; - int atmVclAdminStatus; - int atmVclOperStatus; - unsigned long atmVclLastChange; - struct atmTrafficDescParamEntry *atmVclRxTrafficPtr; - struct atmTrafficDescParamEntry *atmVclTxTrafficPtr; - unsigned char atmVccAalType; - unsigned int atmVccAal5TxSduSize; - unsigned int atmVccAal5RxSduSize; - int atmVccAal5Encap; - int atmVclRowStatus; - int atmVclCastType; - int atmVclConnKind; - struct list_head list; - int flags; -}atmVclEntry; - - -typedef union union_atmptrs { - struct atmIfConfEntry *atmIfConfEntry_ptr; - struct atmTrafficDescParamEntry *atmTrafficDescParamEntry_ptr; - struct atmVclEntry *atmVclEntry_ptr; -}union_atmptrs; - -/* ATM Character device major number */ -#define ATM_MEI_MAJOR 107 - -/* Protocol Constants */ -#define IFX_PROTO_RAW 0 -#define IFX_PROTO_BR2684 1 -#define IFX_PROTO_PPPOATM 2 -#define IFX_PROTO_CLIP 3 - -/* IOCTL Command Set for ATM-MIB */ -#define GET_ATM_IF_CONF_DATA 0x0AB0 -#define SET_ATM_IF_CONF_DATA 0x0AB1 - -#define SET_ATM_QOS_DATA 0x0BC0 - -#define GET_ATM_VCL_DATA 0x0CD0 -#define SET_ATM_VCL_DATA 0x0CD1 - -#define FIND_VCC_IN_KERNEL 0x0DE0 - -/* User defined flags for VCL Table */ -#define ATMVCCAAL5CPCSTRANSMITSDUSIZE 9 -#define ATMVCCAAL5CPCSRECEIVESDUSIZE 10 - -#endif /* CONFIG_IFX_ATM_MIB || IFX_CONFIG_SNMP_ATM_MIB */ - -#endif //AMAZON_ATM_MIB_H diff --git a/target/linux/amazon/files/include/asm-mips/amazon/ifx_peripheral_definitions.h b/target/linux/amazon/files/include/asm-mips/amazon/ifx_peripheral_definitions.h deleted file mode 100644 index 65f14e405f..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/ifx_peripheral_definitions.h +++ /dev/null @@ -1,96 +0,0 @@ -//************************************************************************* -//* Summary of definitions which are used in each peripheral * -//************************************************************************* - -#ifndef peripheral_definitions_h -#define peripheral_definitions_h - -typedef unsigned char UINT8; -typedef signed char INT8; -typedef unsigned short UINT16; -typedef signed short INT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef signed long long INT64; - -#define REG8( addr ) (*(volatile UINT8 *) (addr)) -#define REG16( addr ) (*(volatile UINT16 *)(addr)) -#define REG32( addr ) (*(volatile UINT32 *)(addr)) -#define REG64( addr ) (*(volatile UINT64 *)(addr)) - -/* define routine to set FPI access in Supervisor Mode */ -#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01 -/* Supervisor mode ends, following functions will be done in User mode */ -#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00 -/* Supervisor mode ends, following functions will be done in User mode */ -#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG) -/* Supervisor mode ends, following functions will be done in User mode */ -#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm -/* enable all Interrupts in IIU */ -//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask -///* get all high priority interrupt bits in IIU */ -//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED) -///* signal ends of interrupt to IIU */ -//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit -///* force IIU interrupt register */ -//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data -///* get all bits of interrupt register */ -//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR) -/* insert a NOP instruction */ -#define NOP _nop() -/* CPU goes to power down mode until interrupt occurs */ -#define IFX_CPU_SLEEP _sleep() -/* enable all interrupts to CPU */ -#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int() -/* get all low priority interrupt bits in peripheral */ -#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg) -/* clear low priority interrupt bit in peripheral */ -#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit -/* write FPI bus */ -#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data -#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data -#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data -/* read FPI bus */ -#define READ_FPI_BYTE(addr) REG8(addr) -#define READ_FPI_16BIT(addr) REG16(addr) -#define READ_FPI_32BIT(addr) REG32(addr) -/* write peripheral register */ -#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data -#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data -#else //not CONFIG_CPU_LITTLE_ENDIAN -#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data -#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data -#endif //CONFIG_CPU_LITTLE_ENDIAN - -/* read peripheral register */ -#define READ_PERIPHERAL_REGISTER(addr) REG32(addr) - -/* read/modify(or)/write peripheral register */ -#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data -/* read/modify(and)/write peripheral register */ -#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data - -/* CPU-independent mnemonic constants */ -/* CLC register bits */ -#define IFX_CLC_ENABLE 0x00000000 -#define IFX_CLC_DISABLE 0x00000001 -#define IFX_CLC_DISABLE_STATUS 0x00000002 -#define IFX_CLC_SUSPEND_ENABLE 0x00000004 -#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008 -#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010 -#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020 -#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00 -#define IFX_CLC_RUN_DIVIDER_OFFSET 8 -#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000 -#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16 -#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000 -#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24 - -/* number of cycles to wait for interrupt service routine to be called */ -#define WAIT_CYCLES 50 - -#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc.h b/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc.h deleted file mode 100644 index e5d73ad4ec..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * ifx_ssc.h defines some data sructures used in ifx_ssc.c - * - * Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT) - * - * - */ - -#ifndef __IFX_SSC_H -#define __IFX_SSC_H -#ifdef __KERNEL__ -#include -#endif //__KERNEL__ - -#define PORT_CNT 1 // assume default value - -/* symbolic constants to be used in SSC routines */ - -// ### TO DO: bad performance -#define IFX_SSC_TXFIFO_ITL 1 -#define IFX_SSC_RXFIFO_ITL 1 - - - -struct ifx_ssc_statistics{ - unsigned int abortErr; /* abort error */ - unsigned int modeErr; /* master/slave mode error */ - unsigned int txOvErr; /* TX Overflow error */ - unsigned int txUnErr; /* TX Underrun error */ - unsigned int rxOvErr; /* RX Overflow error */ - unsigned int rxUnErr; /* RX Underrun error */ - unsigned int rxBytes; - unsigned int txBytes; -}; - - -struct ifx_ssc_hwopts { - unsigned int AbortErrDetect :1; /* Abort Error detection (in slave mode) */ - unsigned int rxOvErrDetect :1; /* Receive Overflow Error detection */ - unsigned int rxUndErrDetect :1; /* Receive Underflow Error detection */ - unsigned int txOvErrDetect :1; /* Transmit Overflow Error detection */ - unsigned int txUndErrDetect :1; /* Transmit Underflow Error detection */ - unsigned int echoMode :1; /* Echo mode */ - unsigned int loopBack :1; /* Loopback mode */ - unsigned int idleValue :1; /* Idle value */ - unsigned int clockPolarity :1; /* Idle clock is high or low */ - unsigned int clockPhase :1; /* Tx on trailing or leading edge*/ - unsigned int headingControl :1; /* LSB first or MSB first */ - unsigned int dataWidth :6; /* from 2 up to 32 bits */ - unsigned int masterSelect :1; /* Master or Slave mode */ - unsigned int modeRxTx :2; /* rx/tx mode */ - unsigned int gpoCs :8; /* choose outputs to use for chip select */ - unsigned int gpoInv :8; /* invert GPO outputs */ -}; - - -struct ifx_ssc_frm_opts { - bool FrameEnable; // SFCON.SFEN - unsigned int DataLength; // SFCON.DLEN - unsigned int PauseLength; // SFCON.PLEN - unsigned int IdleData; // SFCON.IDAT - unsigned int IdleClock; // SFCON.ICLK - bool StopAfterPause; // SFCON.STOP -}; - -struct ifx_ssc_frm_status { - bool DataBusy; // SFSTAT.DBSY - bool PauseBusy; // SFSTAT.PBSY - unsigned int DataCount; // SFSTAT.DCNT - unsigned int PauseCount; // SFSTAT.PCNT - bool EnIntAfterData; // SFCON.IBEN - bool EnIntAfterPause;// SFCON.IAEN -}; - -typedef struct { - char *buf; - size_t len; -} ifx_ssc_buf_item_t; - - -// data structures for batch execution -typedef union { - struct { - bool save_options; - } init; - ifx_ssc_buf_item_t read; - ifx_ssc_buf_item_t write; - ifx_ssc_buf_item_t rd_wr; - unsigned int set_baudrate; - struct ifx_ssc_frm_opts set_frm; - unsigned int set_gpo; - struct ifx_ssc_hwopts set_hwopts; -}ifx_ssc_batch_cmd_param; - -struct ifx_ssc_batch_list { - unsigned int cmd; - ifx_ssc_batch_cmd_param cmd_param; - struct ifx_ssc_batch_list *next; -}; - -#ifdef __KERNEL__ -#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE) - - -struct ifx_ssc_port{ - unsigned long mapbase; - struct ifx_ssc_hwopts opts; - struct ifx_ssc_statistics stats; - struct ifx_ssc_frm_status frm_status; - struct ifx_ssc_frm_opts frm_opts; - /* wait queue for ifx_ssc_read() */ - wait_queue_head_t rwait, pwait; - int port_nr; - char port_is_open; /* exclusive open - boolean */ -// int no_of_bits; /* number of _valid_ bits */ -// int elem_size; /* shift for element (no of bytes)*/ - /* buffer and pointers to the read/write position */ - char *rxbuf; /* buffer for RX */ - char *rxbuf_end; /* buffer end pointer for RX */ - volatile char *rxbuf_ptr; /* buffer write pointer for RX */ - char *txbuf; /* buffer for TX */ - char *txbuf_end; /* buffer end pointer for TX */ - volatile char *txbuf_ptr; /* buffer read pointer for TX */ - unsigned int baud; - /* each channel has its own interrupts */ - /* (transmit/receive/error/frame) */ - unsigned int txirq, rxirq, errirq, frmirq; -}; -/* default values for SSC configuration */ -// values of CON -#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */ -#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */ -#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */ -#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */ -#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */ -#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */ -#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */ -#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */ -#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST -#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX -// other values -#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */ -#define IFX_SSC_DEF_BAUDRATE 1000000 -#define IFX_SSC_DEF_RMC 0x10 - -#define IFX_SSC_DEF_TXFIFO_FL 8 -#define IFX_SSC_DEF_RXFIFO_FL 1 - -#if 1 //TODO -#define IFX_SSC_DEF_GPO_CS 2 /* no chip select */ -#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */ -#else -#error "what is ur Chip Select???" -#endif -#define IFX_SSC_DEF_SFCON 0 /* no serial framing */ -#if 0 -#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ - IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT -#endif -#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ - IFX_SSC_R_BIT | IFX_SSC_E_BIT -#endif /* __KERNEL__ */ - -// batch execution commands -#define IFX_SSC_BATCH_CMD_INIT 1 -#define IFX_SSC_BATCH_CMD_READ 2 -#define IFX_SSC_BATCH_CMD_WRITE 3 -#define IFX_SSC_BATCH_CMD_RD_WR 4 -#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5 -#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6 -#define IFX_SSC_BATCH_CMD_SET_FRM 7 -#define IFX_SSC_BATCH_CMD_SET_GPO 8 -#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9 -//#define IFX_SSC_BATCH_CMD_ -//#define IFX_SSC_BATCH_CMD_ -#define IFX_SSC_BATCH_CMD_END_EXEC 0 - -/* Macros to configure SSC hardware */ -/* headingControl: */ -#define IFX_SSC_LSB_FIRST 0 -#define IFX_SSC_MSB_FIRST 1 -/* dataWidth: */ -#define IFX_SSC_MIN_DATA_WIDTH 2 -#define IFX_SSC_MAX_DATA_WIDTH 32 -/* master/slave mode select */ -#define IFX_SSC_MASTER_MODE 1 -#define IFX_SSC_SLAVE_MODE 0 -/* rx/tx mode */ -// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h -#define IFX_SSC_MODE_RXTX 0 -#define IFX_SSC_MODE_RX 1 -#define IFX_SSC_MODE_TX 2 -#define IFX_SSC_MODE_OFF 3 -#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX - -/* GPO values */ -#define IFX_SSC_MAX_GPO_OUT 7 - -#define IFX_SSC_RXREQ_BLOCK_SIZE 32768 - -/***********************/ -/* defines for ioctl's */ -/***********************/ -#define IFX_SSC_IOCTL_MAGIC 'S' -/* read out the statistics */ -#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics) -/* clear the statistics */ -#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2) -/* set the baudrate */ -#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int) -/* get the current baudrate */ -#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int) -/* set hardware options */ -#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts) -/* get the current hardware options */ -#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts) -/* set transmission mode */ -#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int) -/* get the current transmission mode */ -#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int) -/* abort transmission */ -#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9) -#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9) - -/* set general purpose outputs */ -#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int) -/* clear general purpose outputs */ -#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int) -/* get general purpose outputs */ -#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int) - -/*** serial framing ***/ -/* get status of serial framing */ -#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status) -/* get counter reload values and control bits */ -#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts) -/* set counter reload values and control bits */ -#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts) - - -/*** batch execution ***/ -/* do batch execution */ -#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list) - - -#ifdef __KERNEL__ -// routines from ifx_ssc.c -// ### TO DO -/* kernel interface for read and write */ -ssize_t ifx_ssc_kread(int, char *, size_t); -ssize_t ifx_ssc_kwrite(int, const char *, size_t); - -#ifdef CONFIG_IFX_VP_KERNEL_TEST -void ifx_ssc_tc(void); -#endif // CONFIG_IFX_VP_KERNEL_TEST - -#endif //__KERNEL__ -#endif // __IFX_SSC_H - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc_defines.h b/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc_defines.h deleted file mode 100644 index 46157dcbd6..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc_defines.h +++ /dev/null @@ -1,552 +0,0 @@ -#ifndef IFX_SSC_DEFINES_H -#define IFX_SSC_DEFINES_H - -#include "ifx_peripheral_definitions.h" - -/* maximum SSC FIFO size */ -#define IFX_SSC_MAX_FIFO_SIZE 32 - -/* register map of SSC */ - -/* address of the Clock Control Register of the SSC */ -#define IFX_SSC_CLC 0x00000000 -/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0 - bit 1 is hardware modified*/ -#define IFX_SSC_CLC_readmask 0x00FFFFEF -#define IFX_SSC_CLC_writemask 0x00FFFF3D -#define IFX_SSC_CLC_hwmask 0x00000002 -#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask) - -/* address of Port Input Select Register of the SSC */ -#define IFX_SSC_PISEL 0x00000004 -/* IFX_SSC_PISEL register is significant in lowest three bits only */ -#define IFX_SSC_PISEL_readmask 0x00000007 -#define IFX_SSC_PISEL_writemask 0x00000007 -#define IFX_SSC_PISEL_hwmask 0x00000000 -#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask) - -/* address of Identification Register of the SSC */ -#define IFX_SSC_ID 0x00000008 -/* IFX_SSC_ID register is significant in no bit */ -#define IFX_SSC_ID_readmask 0x0000FF3F -#define IFX_SSC_ID_writemask 0x00000000 -#define IFX_SSC_ID_hwmask 0x00000000 -#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask) - -/* address of the Control Register of the SSC */ -#define IFX_SSC_CON 0x00000010 -/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */ -#define IFX_SSC_CON_readmask 0x01DF1FFF -#define IFX_SSC_CON_writemask 0x01DF1FFF -#define IFX_SSC_CON_hwmask 0x00000000 -#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask) - - -/* address of the Status Register of the SSC */ -#define IFX_SSC_STATE 0x00000014 -/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0 - all bits except 1:0 are hardware modified */ -#define IFX_SSC_STATE_readmask 0x771F3F87 -#define IFX_SSC_STATE_writemask 0x00000000 -#define IFX_SSC_STATE_hwmask 0x771F3F84 -#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask) - -/* address of the Write Hardware Modified Control Register Bits of the SSC */ -#define IFX_SSC_WHBSTATE 0x00000018 -/* IFX_SSC_WHBSTATE register is write only */ -#define IFX_SSC_WHBSTATE_readmask 0x00000000 -#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF -#define IFX_SSC_WHBSTATE_hwmask 0x00000000 -#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask) - -/* address of the Baudrate Timer Reload Register of the SSC */ -#define IFX_SSC_BR 0x00000040 -/* IFX_SSC_BR register is significant in bit 15 downto 0*/ -#define IFX_SSC_BR_readmask 0x0000FFFF -#define IFX_SSC_BR_writemask 0x0000FFFF -#define IFX_SSC_BR_hwmask 0x00000000 -#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask) - -/* address of the Baudrate Timer Status Register of the SSC */ -#define IFX_SSC_BRSTAT 0x00000044 -/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/ -#define IFX_SSC_BRSTAT_readmask 0x0000FFFF -#define IFX_SSC_BRSTAT_writemask 0x00000000 -#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF -#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask) - -/* address of the Transmitter Buffer Register of the SSC */ -#define IFX_SSC_TB 0x00000020 -/* IFX_SSC_TB register is significant in bit 31 downto 0*/ -#define IFX_SSC_TB_readmask 0xFFFFFFFF -#define IFX_SSC_TB_writemask 0xFFFFFFFF -#define IFX_SSC_TB_hwmask 0x00000000 -#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask) - -/* address of the Reciver Buffer Register of the SSC */ -#define IFX_SSC_RB 0x00000024 -/* IFX_SSC_RB register is significant in no bits*/ -#define IFX_SSC_RB_readmask 0xFFFFFFFF -#define IFX_SSC_RB_writemask 0x00000000 -#define IFX_SSC_RB_hwmask 0xFFFFFFFF -#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask) - -/* address of the Receive FIFO Control Register of the SSC */ -#define IFX_SSC_RXFCON 0x00000030 -/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ -#define IFX_SSC_RXFCON_readmask 0x00003F03 -#define IFX_SSC_RXFCON_writemask 0x00003F03 -#define IFX_SSC_RXFCON_hwmask 0x00000000 -#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask) - -/* address of the Transmit FIFO Control Register of the SSC */ -#define IFX_SSC_TXFCON 0x00000034 -/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ -#define IFX_SSC_TXFCON_readmask 0x00003F03 -#define IFX_SSC_TXFCON_writemask 0x00003F03 -#define IFX_SSC_TXFCON_hwmask 0x00000000 -#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask) - -/* address of the FIFO Status Register of the SSC */ -#define IFX_SSC_FSTAT 0x00000038 -/* IFX_SSC_FSTAT register is significant in no bit*/ -#define IFX_SSC_FSTAT_readmask 0x00003F3F -#define IFX_SSC_FSTAT_writemask 0x00000000 -#define IFX_SSC_FSTAT_hwmask 0x00003F3F -#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask) - -/* address of the Data Frame Control register of the SSC */ -#define IFX_SSC_SFCON 0x00000060 -#define IFX_SSC_SFCON_readmask 0xFFDFFFFD -#define IFX_SSC_SFCON_writemask 0xFFDFFFFD -#define IFX_SSC_SFCON_hwmask 0x00000000 -#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask) - -/* address of the Data Frame Status register of the SSC */ -#define IFX_SSC_SFSTAT 0x00000064 -#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3 -#define IFX_SSC_SFSTAT_writemask 0x00000000 -#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3 -#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask) - -/* address of the General Purpose Output Control register of the SSC */ -#define IFX_SSC_GPOCON 0x00000070 -#define IFX_SSC_GPOCON_readmask 0x0000FFFF -#define IFX_SSC_GPOCON_writemask 0x0000FFFF -#define IFX_SSC_GPOCON_hwmask 0x00000000 -#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask) - -/* address of the General Purpose Output Status register of the SSC */ -#define IFX_SSC_GPOSTAT 0x00000074 -#define IFX_SSC_GPOSTAT_readmask 0x000000FF -#define IFX_SSC_GPOSTAT_writemask 0x00000000 -#define IFX_SSC_GPOSTAT_hwmask 0x00000000 -#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask) - -/* address of the Force GPO Status register of the SSC */ -#define IFX_SSC_WHBGPOSTAT 0x00000078 -#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000 -#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF -#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000 -#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask) - -/* address of the Receive Request Register of the SSC */ -#define IFX_SSC_RXREQ 0x00000080 -#define IFX_SSC_RXREQ_readmask 0x0000FFFF -#define IFX_SSC_RXREQ_writemask 0x0000FFFF -#define IFX_SSC_RXREQ_hwmask 0x00000000 -#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask) - -/* address of the Receive Count Register of the SSC */ -#define IFX_SSC_RXCNT 0x00000084 -#define IFX_SSC_RXCNT_readmask 0x0000FFFF -#define IFX_SSC_RXCNT_writemask 0x00000000 -#define IFX_SSC_RXCNT_hwmask 0x0000FFFF -#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask) - -/* address of the DMA Configuration Register of the SSC */ -#define IFX_SSC_DMACON 0x000000EC -#define IFX_SSC_DMACON_readmask 0x0000FFFF -#define IFX_SSC_DMACON_writemask 0x00000000 -#define IFX_SSC_DMACON_hwmask 0x0000FFFF -#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask) - -//------------------------------------------------------ -// interrupt register for enabling interrupts, mask register of irq_reg -#define IFX_SSC_IRN_EN 0xF4 -// read/write -#define IFX_SSC_IRN_EN_readmask 0x0000000F -#define IFX_SSC_IRN_EN_writemask 0x0000000F -#define IFX_SSC_IRN_EN_hwmask 0x00000000 -#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask) - -// interrupt register for accessing interrupts -#define IFX_SSC_IRN_CR 0xF8 -// read/write -#define IFX_SSC_IRN_CR_readmask 0x0000000F -#define IFX_SSC_IRN_CR_writemask 0x0000000F -#define IFX_SSC_IRN_CR_hwmask 0x0000000F -#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask) - -// interrupt register for stimulating interrupts -#define IFX_SSC_IRN_ICR 0xFC -// read/write -#define IFX_SSC_IRN_ICR_readmask 0x0000000F -#define IFX_SSC_IRN_ICR_writemask 0x0000000F -#define IFX_SSC_IRN_ICR_hwmask 0x00000000 -#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask) - -//--------------------------------------------------------------------- -// Number of IRQs and bitposition of IRQ -#define IFX_SSC_NUM_IRQ 4 -#define IFX_SSC_T_BIT 0x00000001 -#define IFX_SSC_R_BIT 0x00000002 -#define IFX_SSC_E_BIT 0x00000004 -#define IFX_SSC_F_BIT 0x00000008 - -/* bit masks for SSC registers */ - -/* ID register */ -#define IFX_SSC_PERID_REV_MASK 0x0000001F -#define IFX_SSC_PERID_CFG_MASK 0x00000020 -#define IFX_SSC_PERID_ID_MASK 0x0000FF00 -#define IFX_SSC_PERID_REV_OFFSET 0 -#define IFX_SSC_PERID_CFG_OFFSET 5 -#define IFX_SSC_PERID_ID_OFFSET 8 -#define IFX_SSC_PERID_ID 0x45 -#define IFX_SSC_PERID_DMA_ON 0x00000020 -#define IFX_SSC_PERID_RXFS_MASK 0x003F0000 -#define IFX_SSC_PERID_RXFS_OFFSET 16 -#define IFX_SSC_PERID_TXFS_MASK 0x3F000000 -#define IFX_SSC_PERID_TXFS_OFFSET 24 - -/* PISEL register */ -#define IFX_SSC_PISEL_MASTER_IN_A 0x0000 -#define IFX_SSC_PISEL_MASTER_IN_B 0x0001 -#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000 -#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002 -#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000 -#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004 - - -/* IFX_SSC_CON register */ -#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000 -#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000 -#define IFX_SSC_CON_IDLE_HIGH 0x00800000 -#define IFX_SSC_CON_IDLE_LOW 0x00000000 -#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000 -#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000 -#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16 -#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000 -#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK) - -#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000 -#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000 - -#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000 -#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000 -#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800 -#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000 -#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400 -#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000 -#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200 -#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000 -#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100 -#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000 -#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00 -#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000 - -#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080 -#define IFX_SSC_CON_NO_LOOPBACK 0x00000000 -#define IFX_SSC_CON_HALF_DUPLEX 0x00000080 -#define IFX_SSC_CON_FULL_DUPLEX 0x00000000 -#define IFX_SSC_CON_CLOCK_FALL 0x00000040 -#define IFX_SSC_CON_CLOCK_RISE 0x00000000 -#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000 -#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020 -#define IFX_SSC_CON_MSB_FIRST 0x00000010 -#define IFX_SSC_CON_LSB_FIRST 0x00000000 -#define IFX_SSC_CON_ENABLE_CSB 0x00000008 -#define IFX_SSC_CON_DISABLE_CSB 0x00000000 -#define IFX_SSC_CON_INVERT_CSB 0x00000004 -#define IFX_SSC_CON_TRUE_CSB 0x00000000 -#define IFX_SSC_CON_RX_OFF 0x00000002 -#define IFX_SSC_CON_RX_ON 0x00000000 -#define IFX_SSC_CON_TX_OFF 0x00000001 -#define IFX_SSC_CON_TX_ON 0x00000000 - - -/* IFX_SSC_STATE register */ -#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28 -#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000 -#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET) -#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24 -#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000 -#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET) -#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16 -#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000 -#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1) -#define IFX_SSC_STATE_BUSY 0x00002000 -#define IFX_SSC_STATE_RX_UFL 0x00001000 -#define IFX_SSC_STATE_TX_UFL 0x00000800 -#define IFX_SSC_STATE_ABORT_ERR 0x00000400 -#define IFX_SSC_STATE_RX_OFL 0x00000200 -#define IFX_SSC_STATE_TX_OFL 0x00000100 -#define IFX_SSC_STATE_MODE_ERR 0x00000080 -#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004 -#define IFX_SSC_STATE_IS_MASTER 0x00000002 -#define IFX_SSC_STATE_IS_ENABLED 0x00000001 - -/* WHBSTATE register */ -#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001 -#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001 -#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001 - -#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002 -#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002 -#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002 - -#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004 -#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004 - -#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008 -#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008 - -#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010 -#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020 - -#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040 -#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080 - -#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100 -#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200 -#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400 -#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800 -#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000 -#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000 -#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000 -#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000 -#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50 -#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0 - -/* BR register */ -#define IFX_SSC_BR_BAUDRATE_OFFSET 0 -#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF - -/* BR_STAT register */ -#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0 -#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF - -/* TB register */ -#define IFX_SSC_TB_DATA_OFFSET 0 -#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF - -/* RB register */ -#define IFX_SSC_RB_DATA_OFFSET 0 -#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF - - -/* RXFCON and TXFCON registers */ -#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000 -#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001 -#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002 -#define IFX_SSC_XFCON_ITL_MASK 0x00003F00 -#define IFX_SSC_XFCON_ITL_OFFSET 8 - -/* FSTAT register */ -#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0 -#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F -#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8 -#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00 - -/* GPOCON register */ -#define IFX_SSC_GPOCON_INVOUT0_POS 0 -#define IFX_SSC_GPOCON_INV_OUT0 0x00000001 -#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000 -#define IFX_SSC_GPOCON_INVOUT1_POS 1 -#define IFX_SSC_GPOCON_INV_OUT1 0x00000002 -#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000 -#define IFX_SSC_GPOCON_INVOUT2_POS 2 -#define IFX_SSC_GPOCON_INV_OUT2 0x00000003 -#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000 -#define IFX_SSC_GPOCON_INVOUT3_POS 3 -#define IFX_SSC_GPOCON_INV_OUT3 0x00000008 -#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000 -#define IFX_SSC_GPOCON_INVOUT4_POS 4 -#define IFX_SSC_GPOCON_INV_OUT4 0x00000010 -#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000 -#define IFX_SSC_GPOCON_INVOUT5_POS 5 -#define IFX_SSC_GPOCON_INV_OUT5 0x00000020 -#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000 -#define IFX_SSC_GPOCON_INVOUT6_POS 6 -#define IFX_SSC_GPOCON_INV_OUT6 0x00000040 -#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000 -#define IFX_SSC_GPOCON_INVOUT7_POS 7 -#define IFX_SSC_GPOCON_INV_OUT7 0x00000080 -#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000 -#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF -#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000 - -#define IFX_SSC_GPOCON_ISCSB0_POS 8 -#define IFX_SSC_GPOCON_IS_CSB0 0x00000100 -#define IFX_SSC_GPOCON_IS_GPO0 0x00000000 -#define IFX_SSC_GPOCON_ISCSB1_POS 9 -#define IFX_SSC_GPOCON_IS_CSB1 0x00000200 -#define IFX_SSC_GPOCON_IS_GPO1 0x00000000 -#define IFX_SSC_GPOCON_ISCSB2_POS 10 -#define IFX_SSC_GPOCON_IS_CSB2 0x00000400 -#define IFX_SSC_GPOCON_IS_GPO2 0x00000000 -#define IFX_SSC_GPOCON_ISCSB3_POS 11 -#define IFX_SSC_GPOCON_IS_CSB3 0x00000800 -#define IFX_SSC_GPOCON_IS_GPO3 0x00000000 -#define IFX_SSC_GPOCON_ISCSB4_POS 12 -#define IFX_SSC_GPOCON_IS_CSB4 0x00001000 -#define IFX_SSC_GPOCON_IS_GPO4 0x00000000 -#define IFX_SSC_GPOCON_ISCSB5_POS 13 -#define IFX_SSC_GPOCON_IS_CSB5 0x00002000 -#define IFX_SSC_GPOCON_IS_GPO5 0x00000000 -#define IFX_SSC_GPOCON_ISCSB6_POS 14 -#define IFX_SSC_GPOCON_IS_CSB6 0x00004000 -#define IFX_SSC_GPOCON_IS_GPO6 0x00000000 -#define IFX_SSC_GPOCON_ISCSB7_POS 15 -#define IFX_SSC_GPOCON_IS_CSB7 0x00008000 -#define IFX_SSC_GPOCON_IS_GPO7 0x00000000 -#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00 -#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000 - -/* GPOSTAT register */ -#define IFX_SSC_GPOSTAT_OUT0 0x00000001 -#define IFX_SSC_GPOSTAT_OUT1 0x00000002 -#define IFX_SSC_GPOSTAT_OUT2 0x00000004 -#define IFX_SSC_GPOSTAT_OUT3 0x00000008 -#define IFX_SSC_GPOSTAT_OUT4 0x00000010 -#define IFX_SSC_GPOSTAT_OUT5 0x00000020 -#define IFX_SSC_GPOSTAT_OUT6 0x00000040 -#define IFX_SSC_GPOSTAT_OUT7 0x00000080 -#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF - -/* WHBGPOSTAT register */ -#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001 -#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002 -#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004 -#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008 -#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010 -#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020 -#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040 -#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF - -#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0 -#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1 -#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2 -#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3 -#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4 -#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5 -#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6 -#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7 - - -#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8 -#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100 -#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9 -#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200 -#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10 -#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400 -#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11 -#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800 -#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12 -#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000 -#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13 -#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000 -#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14 -#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000 -#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15 -#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000 -#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00 - -/* SFCON register */ -#define IFX_SSC_SFCON_SF_ENABLE 0x00000001 -#define IFX_SSC_SFCON_SF_DISABLE 0x00000000 -#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004 -#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000 -#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008 -#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000 -#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0 -#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4 -#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000 -#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16 -#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000 -#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000 -#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18 -#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000 -#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000 -#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000 -#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000 -#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22 -#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096 -#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024 - -#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET) -#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) -#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK) -#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) - -/* SFSTAT register */ -#define IFX_SSC_SFSTAT_IN_DATA 0x00000001 -#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002 -#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0 -#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4 -#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000 -#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20 - -#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET) -#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET) - -/* RXREQ register */ -#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF -#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0 - -/* RXCNT register */ -#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF -#define IFX_SSC_RXCNT_TODO_OFFSET 0 - -/* DMACON register */ -#define IFX_SSC_DMACON_RXON 0x00000001 -#define IFX_SSC_DMACON_RXOFF 0x00000000 -#define IFX_SSC_DMACON_TXON 0x00000002 -#define IFX_SSC_DMACON_TXOFF 0x00000000 -#define IFX_SSC_DMACON_DMAON 0x00000003 -#define IFX_SSC_DMACON_DMAOFF 0x00000000 -#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C -#define IFX_SSC_DMACON_CLASS_OFFSET 2 - -/* register access macros */ -#define ifx_ssc_fstat_received_words(status) (status & 0x003F) -#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8) - -#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE)) -#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON)) -#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON)) -#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE)) -#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB)) -#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB)) -#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT)) -#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR)) - -#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET) -#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) - -#endif diff --git a/target/linux/amazon/files/include/asm-mips/amazon/irq.h b/target/linux/amazon/files/include/asm-mips/amazon/irq.h deleted file mode 100644 index c575dd64b2..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/irq.h +++ /dev/null @@ -1,200 +0,0 @@ -/* irq.h - AMAZON interrupts */ - -#ifndef __AMAZON_IRQ -#define __AMAZON_IRQ - -/************************************************************************ - * Interrupt information -*************************************************************************/ - -/* these vectors are to handle the interrupts from the internal AMAZON - interrupt controller. THe INT_NUM values are really just indices into - an array and are set up so that we can use the INT_NUM as a shift - to calculate a mask value. */ -#define INT_NUM_IRQ0 8 -#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) -#define INT_NUM_IM0_IRL1 (INT_NUM_IRQ0 + 1) -#define INT_NUM_IM0_IRL2 (INT_NUM_IRQ0 + 2) -#define INT_NUM_IM0_IRL3 (INT_NUM_IRQ0 + 3) -#define INT_NUM_IM0_IRL4 (INT_NUM_IRQ0 + 4) -#define INT_NUM_IM0_IRL5 (INT_NUM_IRQ0 + 5) -#define INT_NUM_IM0_IRL6 (INT_NUM_IRQ0 + 6) -#define INT_NUM_IM0_IRL7 (INT_NUM_IRQ0 + 7) -#define INT_NUM_IM0_IRL8 (INT_NUM_IRQ0 + 8) -#define INT_NUM_IM0_IRL9 (INT_NUM_IRQ0 + 9) -#define INT_NUM_IM0_IRL10 (INT_NUM_IRQ0 + 10) -#define INT_NUM_IM0_IRL11 (INT_NUM_IRQ0 + 11) -#define INT_NUM_IM0_IRL12 (INT_NUM_IRQ0 + 12) -#define INT_NUM_IM0_IRL13 (INT_NUM_IRQ0 + 13) -#define INT_NUM_IM0_IRL14 (INT_NUM_IRQ0 + 14) -#define INT_NUM_IM0_IRL15 (INT_NUM_IRQ0 + 15) -#define INT_NUM_IM0_IRL16 (INT_NUM_IRQ0 + 16) -#define INT_NUM_IM0_IRL17 (INT_NUM_IRQ0 + 17) -#define INT_NUM_IM0_IRL18 (INT_NUM_IRQ0 + 18) -#define INT_NUM_IM0_IRL19 (INT_NUM_IRQ0 + 19) -#define INT_NUM_IM0_IRL20 (INT_NUM_IRQ0 + 20) -#define INT_NUM_IM0_IRL21 (INT_NUM_IRQ0 + 21) -#define INT_NUM_IM0_IRL22 (INT_NUM_IRQ0 + 22) -#define INT_NUM_IM0_IRL23 (INT_NUM_IRQ0 + 23) -#define INT_NUM_IM0_IRL24 (INT_NUM_IRQ0 + 24) -#define INT_NUM_IM0_IRL25 (INT_NUM_IRQ0 + 25) -#define INT_NUM_IM0_IRL26 (INT_NUM_IRQ0 + 26) -#define INT_NUM_IM0_IRL27 (INT_NUM_IRQ0 + 27) -#define INT_NUM_IM0_IRL28 (INT_NUM_IRQ0 + 28) -#define INT_NUM_IM0_IRL29 (INT_NUM_IRQ0 + 29) -#define INT_NUM_IM0_IRL30 (INT_NUM_IRQ0 + 30) -#define INT_NUM_IM0_IRL31 (INT_NUM_IRQ0 + 31) - -#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) -#define INT_NUM_IM1_IRL1 (INT_NUM_IM1_IRL0 + 1) -#define INT_NUM_IM1_IRL2 (INT_NUM_IM1_IRL0 + 2) -#define INT_NUM_IM1_IRL3 (INT_NUM_IM1_IRL0 + 3) -#define INT_NUM_IM1_IRL4 (INT_NUM_IM1_IRL0 + 4) -#define INT_NUM_IM1_IRL5 (INT_NUM_IM1_IRL0 + 5) -#define INT_NUM_IM1_IRL6 (INT_NUM_IM1_IRL0 + 6) -#define INT_NUM_IM1_IRL7 (INT_NUM_IM1_IRL0 + 7) -#define INT_NUM_IM1_IRL8 (INT_NUM_IM1_IRL0 + 8) -#define INT_NUM_IM1_IRL9 (INT_NUM_IM1_IRL0 + 9) -#define INT_NUM_IM1_IRL10 (INT_NUM_IM1_IRL0 + 10) -#define INT_NUM_IM1_IRL11 (INT_NUM_IM1_IRL0 + 11) -#define INT_NUM_IM1_IRL12 (INT_NUM_IM1_IRL0 + 12) -#define INT_NUM_IM1_IRL13 (INT_NUM_IM1_IRL0 + 13) -#define INT_NUM_IM1_IRL14 (INT_NUM_IM1_IRL0 + 14) -#define INT_NUM_IM1_IRL15 (INT_NUM_IM1_IRL0 + 15) -#define INT_NUM_IM1_IRL16 (INT_NUM_IM1_IRL0 + 16) -#define INT_NUM_IM1_IRL17 (INT_NUM_IM1_IRL0 + 17) -#define INT_NUM_IM1_IRL18 (INT_NUM_IM1_IRL0 + 18) -#define INT_NUM_IM1_IRL19 (INT_NUM_IM1_IRL0 + 19) -#define INT_NUM_IM1_IRL20 (INT_NUM_IM1_IRL0 + 20) -#define INT_NUM_IM1_IRL21 (INT_NUM_IM1_IRL0 + 21) -#define INT_NUM_IM1_IRL22 (INT_NUM_IM1_IRL0 + 22) -#define INT_NUM_IM1_IRL23 (INT_NUM_IM1_IRL0 + 23) -#define INT_NUM_IM1_IRL24 (INT_NUM_IM1_IRL0 + 24) -#define INT_NUM_IM1_IRL25 (INT_NUM_IM1_IRL0 + 25) -#define INT_NUM_IM1_IRL26 (INT_NUM_IM1_IRL0 + 26) -#define INT_NUM_IM1_IRL27 (INT_NUM_IM1_IRL0 + 27) -#define INT_NUM_IM1_IRL28 (INT_NUM_IM1_IRL0 + 28) -#define INT_NUM_IM1_IRL29 (INT_NUM_IM1_IRL0 + 29) -#define INT_NUM_IM1_IRL30 (INT_NUM_IM1_IRL0 + 30) -#define INT_NUM_IM1_IRL31 (INT_NUM_IM1_IRL0 + 31) - -#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) -#define INT_NUM_IM2_IRL1 (INT_NUM_IM2_IRL0 + 1) -#define INT_NUM_IM2_IRL2 (INT_NUM_IM2_IRL0 + 2) -#define INT_NUM_IM2_IRL3 (INT_NUM_IM2_IRL0 + 3) -#define INT_NUM_IM2_IRL4 (INT_NUM_IM2_IRL0 + 4) -#define INT_NUM_IM2_IRL5 (INT_NUM_IM2_IRL0 + 5) -#define INT_NUM_IM2_IRL6 (INT_NUM_IM2_IRL0 + 6) -#define INT_NUM_IM2_IRL7 (INT_NUM_IM2_IRL0 + 7) -#define INT_NUM_IM2_IRL8 (INT_NUM_IM2_IRL0 + 8) -#define INT_NUM_IM2_IRL9 (INT_NUM_IM2_IRL0 + 9) -#define INT_NUM_IM2_IRL10 (INT_NUM_IM2_IRL0 + 10) -#define INT_NUM_IM2_IRL11 (INT_NUM_IM2_IRL0 + 11) -#define INT_NUM_IM2_IRL12 (INT_NUM_IM2_IRL0 + 12) -#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13) -#define INT_NUM_IM2_IRL14 (INT_NUM_IM2_IRL0 + 14) -#define INT_NUM_IM2_IRL15 (INT_NUM_IM2_IRL0 + 15) -#define INT_NUM_IM2_IRL16 (INT_NUM_IM2_IRL0 + 16) -#define INT_NUM_IM2_IRL17 (INT_NUM_IM2_IRL0 + 17) -#define INT_NUM_IM2_IRL18 (INT_NUM_IM2_IRL0 + 18) -#define INT_NUM_IM2_IRL19 (INT_NUM_IM2_IRL0 + 19) -#define INT_NUM_IM2_IRL20 (INT_NUM_IM2_IRL0 + 20) -#define INT_NUM_IM2_IRL21 (INT_NUM_IM2_IRL0 + 21) -#define INT_NUM_IM2_IRL22 (INT_NUM_IM2_IRL0 + 22) -#define INT_NUM_IM2_IRL23 (INT_NUM_IM2_IRL0 + 23) -#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) -#define INT_NUM_IM2_IRL25 (INT_NUM_IM2_IRL0 + 25) -#define INT_NUM_IM2_IRL26 (INT_NUM_IM2_IRL0 + 26) -#define INT_NUM_IM2_IRL27 (INT_NUM_IM2_IRL0 + 27) -#define INT_NUM_IM2_IRL28 (INT_NUM_IM2_IRL0 + 28) -#define INT_NUM_IM2_IRL29 (INT_NUM_IM2_IRL0 + 29) -#define INT_NUM_IM2_IRL30 (INT_NUM_IM2_IRL0 + 30) -#define INT_NUM_IM2_IRL31 (INT_NUM_IM2_IRL0 + 31) - -#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) -#define INT_NUM_IM3_IRL1 (INT_NUM_IM3_IRL0 + 1) -#define INT_NUM_IM3_IRL2 (INT_NUM_IM3_IRL0 + 2) -#define INT_NUM_IM3_IRL3 (INT_NUM_IM3_IRL0 + 3) -#define INT_NUM_IM3_IRL4 (INT_NUM_IM3_IRL0 + 4) -#define INT_NUM_IM3_IRL5 (INT_NUM_IM3_IRL0 + 5) -#define INT_NUM_IM3_IRL6 (INT_NUM_IM3_IRL0 + 6) -#define INT_NUM_IM3_IRL7 (INT_NUM_IM3_IRL0 + 7) -#define INT_NUM_IM3_IRL8 (INT_NUM_IM3_IRL0 + 8) -#define INT_NUM_IM3_IRL9 (INT_NUM_IM3_IRL0 + 9) -#define INT_NUM_IM3_IRL10 (INT_NUM_IM3_IRL0 + 10) -#define INT_NUM_IM3_IRL11 (INT_NUM_IM3_IRL0 + 11) -#define INT_NUM_IM3_IRL12 (INT_NUM_IM3_IRL0 + 12) -#define INT_NUM_IM3_IRL13 (INT_NUM_IM3_IRL0 + 13) -#define INT_NUM_IM3_IRL14 (INT_NUM_IM3_IRL0 + 14) -#define INT_NUM_IM3_IRL15 (INT_NUM_IM3_IRL0 + 15) -#define INT_NUM_IM3_IRL16 (INT_NUM_IM3_IRL0 + 16) -#define INT_NUM_IM3_IRL17 (INT_NUM_IM3_IRL0 + 17) -#define INT_NUM_IM3_IRL18 (INT_NUM_IM3_IRL0 + 18) -#define INT_NUM_IM3_IRL19 (INT_NUM_IM3_IRL0 + 19) -#define INT_NUM_IM3_IRL20 (INT_NUM_IM3_IRL0 + 20) -#define INT_NUM_IM3_IRL21 (INT_NUM_IM3_IRL0 + 21) -#define INT_NUM_IM3_IRL22 (INT_NUM_IM3_IRL0 + 22) -#define INT_NUM_IM3_IRL23 (INT_NUM_IM3_IRL0 + 23) -#define INT_NUM_IM3_IRL24 (INT_NUM_IM3_IRL0 + 24) -#define INT_NUM_IM3_IRL25 (INT_NUM_IM3_IRL0 + 25) -#define INT_NUM_IM3_IRL26 (INT_NUM_IM3_IRL0 + 26) -#define INT_NUM_IM3_IRL27 (INT_NUM_IM3_IRL0 + 27) -#define INT_NUM_IM3_IRL28 (INT_NUM_IM3_IRL0 + 28) -#define INT_NUM_IM3_IRL29 (INT_NUM_IM3_IRL0 + 29) -#define INT_NUM_IM3_IRL30 (INT_NUM_IM3_IRL0 + 30) -#define INT_NUM_IM3_IRL31 (INT_NUM_IM3_IRL0 + 31) - -#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) -#define INT_NUM_IM4_IRL1 (INT_NUM_IM4_IRL0 + 1) -#define INT_NUM_IM4_IRL2 (INT_NUM_IM4_IRL0 + 2) -#define INT_NUM_IM4_IRL3 (INT_NUM_IM4_IRL0 + 3) -#define INT_NUM_IM4_IRL4 (INT_NUM_IM4_IRL0 + 4) -#define INT_NUM_IM4_IRL5 (INT_NUM_IM4_IRL0 + 5) -#define INT_NUM_IM4_IRL6 (INT_NUM_IM4_IRL0 + 6) -#define INT_NUM_IM4_IRL7 (INT_NUM_IM4_IRL0 + 7) -#define INT_NUM_IM4_IRL8 (INT_NUM_IM4_IRL0 + 8) -#define INT_NUM_IM4_IRL9 (INT_NUM_IM4_IRL0 + 9) -#define INT_NUM_IM4_IRL10 (INT_NUM_IM4_IRL0 + 10) -#define INT_NUM_IM4_IRL11 (INT_NUM_IM4_IRL0 + 11) -#define INT_NUM_IM4_IRL12 (INT_NUM_IM4_IRL0 + 12) -#define INT_NUM_IM4_IRL13 (INT_NUM_IM4_IRL0 + 13) -#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) -#define INT_NUM_IM4_IRL15 (INT_NUM_IM4_IRL0 + 15) -#define INT_NUM_IM4_IRL16 (INT_NUM_IM4_IRL0 + 16) -#define INT_NUM_IM4_IRL17 (INT_NUM_IM4_IRL0 + 17) -#define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18) -#define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19) -#define INT_NUM_IM4_IRL20 (INT_NUM_IM4_IRL0 + 20) -#define INT_NUM_IM4_IRL21 (INT_NUM_IM4_IRL0 + 21) -#define INT_NUM_IM4_IRL22 (INT_NUM_IM4_IRL0 + 22) -#define INT_NUM_IM4_IRL23 (INT_NUM_IM4_IRL0 + 23) -#define INT_NUM_IM4_IRL24 (INT_NUM_IM4_IRL0 + 24) -#define INT_NUM_IM4_IRL25 (INT_NUM_IM4_IRL0 + 25) -#define INT_NUM_IM4_IRL26 (INT_NUM_IM4_IRL0 + 26) -#define INT_NUM_IM4_IRL27 (INT_NUM_IM4_IRL0 + 27) -#define INT_NUM_IM4_IRL28 (INT_NUM_IM4_IRL0 + 28) -#define INT_NUM_IM4_IRL29 (INT_NUM_IM4_IRL0 + 29) -#define INT_NUM_IM4_IRL30 (INT_NUM_IM4_IRL0 + 30) -#define INT_NUM_IM4_IRL31 (INT_NUM_IM4_IRL0 + 31) - -/****** Interrupt Assigments ***********/ -#define AMAZON_DMA_INT INT_NUM_IM0_IRL0 -#define IFX_SSC_TIR INT_NUM_IM0_IRL29 -#define IFX_SSC_RIR INT_NUM_IM0_IRL30 -#define IFX_SSC_EIR INT_NUM_IM0_IRL31 - -#define AMAZON_MEI_INT INT_NUM_IM2_IRL8 - -#define AMAZONASC_TIR INT_NUM_IM4_IRL15/* TX interrupt */ -#define AMAZONASC_RIR INT_NUM_IM4_IRL16/* RX interrupt */ -#define AMAZONASC_EIR INT_NUM_IM4_IRL17/* ERROR interrupt */ - -#define AMAZON_TIMER6_INT INT_NUM_IM1_IRL23 - -#define AMAZON_SWIE_INT INT_NUM_IM3_IRL8 -#define AMAZON_CBM_INT INT_NUM_IM3_IRL9 -#define AMAZON_AAL5_INT INT_NUM_IM3_IRL10 -#define AMAZON_HTU_INT INT_NUM_IM3_IRL11 -#define AMAZON_QSB_INT INT_NUM_IM3_IRL12 -#define MIPS_CPU_TIMER_IRQ 7 -#endif /* __AMAZON_IRQ */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/model.h b/target/linux/amazon/files/include/asm-mips/amazon/model.h deleted file mode 100644 index 4e43ab5f19..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/model.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef AMAZON_MODEL_H -#define AMAZON_MODEL_H -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ -#define BOARD_SYSTEM_TYPE "AMAZON" -#define SYSTEM_MODEL_NAME "Amazon Gateway Package 3.2 Version" -#endif diff --git a/target/linux/amazon/files/include/asm-mips/amazon/port.h b/target/linux/amazon/files/include/asm-mips/amazon/port.h deleted file mode 100644 index 21825794c5..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/port.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * port.h - * - * Global Amazon port driver header file - * - */ - -/* Modification history */ -/* 21Jun2004 btxu Generate from Inca_IP project */ - - -#ifndef PORT_H -#define PORT_H - -struct amazon_port_ioctl_parm { - int port; - int pin; - int value; -}; -#define AMAZON_PORT_IOC_MAGIC 0xbf -#define AMAZON_PORT_IOCOD _IOW( AMAZON_PORT_IOC_MAGIC,0,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCPUDSEL _IOW( AMAZON_PORT_IOC_MAGIC,1,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCPUDEN _IOW( AMAZON_PORT_IOC_MAGIC,2,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCSTOFF _IOW( AMAZON_PORT_IOC_MAGIC,3,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCDIR _IOW( AMAZON_PORT_IOC_MAGIC,4,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCOUTPUT _IOW( AMAZON_PORT_IOC_MAGIC,5,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCINPUT _IOWR(AMAZON_PORT_IOC_MAGIC,6,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCALTSEL0 _IOW( AMAZON_PORT_IOC_MAGIC,7,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCALTSEL1 _IOW( AMAZON_PORT_IOC_MAGIC,8,struct amazon_port_ioctl_parm) - -int amazon_port_reserve_pin(int port, int pin, int module_id); -int amazon_port_free_pin(int port, int pin, int module_id); -int amazon_port_set_open_drain(int port, int pin, int module_id); -int amazon_port_clear_open_drain(int port, int pin, int module_id); -int amazon_port_set_pudsel(int port, int pin, int module_id); -int amazon_port_clear_pudsel(int port, int pin, int module_id); -int amazon_port_set_puden(int port, int pin, int module_id); -int amazon_port_clear_puden(int port, int pin, int module_id); -int amazon_port_set_stoff(int port, int pin, int module_id); -int amazon_port_clear_stoff(int port, int pin, int module_id); -int amazon_port_set_dir_out(int port, int pin, int module_id); -int amazon_port_set_dir_in(int port, int pin, int module_id); -int amazon_port_set_output(int port, int pin, int module_id); -int amazon_port_clear_output(int port, int pin, int module_id); -int amazon_port_get_input(int port, int pin, int module_id); - -int amazon_port_set_altsel0(int port, int pin, int module_id); -int amazon_port_clear_altsel0(int port, int pin, int module_id); -int amazon_port_set_altsel1(int port, int pin, int module_id); -int amazon_port_clear_altsel1(int port, int pin, int module_id); - - -#endif /* PORT_H */ - - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/serial.h b/target/linux/amazon/files/include/asm-mips/amazon/serial.h deleted file mode 100644 index 3ff3efc28d..0000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/serial.h +++ /dev/null @@ -1,146 +0,0 @@ -/* incaAscSio.h - (AMAZON) ASC UART tty driver header */ - -#ifndef __AMAZON_ASC_H -#define __AMAZON_ASC_H - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -/* use fractional divider for baudrate settings */ -#define AMAZONASC_USE_FDV - -#ifdef AMAZONASC_USE_FDV - #define AMAZONASC_FDV_LOW_BAUDRATE 71 -#ifdef CONFIG_USE_IKOS - #define AMAZONASC_FDV_HIGH_BAUDRATE 443 -#else - #define AMAZONASC_FDV_HIGH_BAUDRATE 498 -#endif //CONFIG_USE_IKOS -#endif /*AMAZONASC_USE_FDV*/ - - -#define AMAZONASC_TXFIFO_FL 1 -#define AMAZONASC_RXFIFO_FL 1 -#define AMAZONASC_TXFIFO_FULL 16 - -/* interrupt lines masks for the ASC device interrupts*/ -/* change these macroses if it's necessary */ -#define AMAZONASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */ - -#define AMAZONASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */ -#define AMAZONASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */ -#define AMAZONASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */ -#define AMAZONASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/ - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0007 - #define ASCCON_M_8SYNC 0x0 - #define ASCCON_M_8ASYNC 0x1 - #define ASCCON_M_8IRDAASYNC 0x2 - #define ASCCON_M_7ASYNCPAR 0x3 - #define ASCCON_M_9ASYNC 0x4 - #define ASCCON_M_8WAKEUPASYNC 0x5 - #define ASCCON_M_8ASYNCPAR 0x7 -#define ASCCON_STP 0x0008 -#define ASCCON_REN 0x0010 -#define ASCCON_PEN 0x0020 -#define ASCCON_FEN 0x0040 -#define ASCCON_OEN 0x0080 -#define ASCCON_PE 0x0100 -#define ASCCON_FE 0x0200 -#define ASCCON_OE 0x0400 -#define ASCCON_FDE 0x0800 -#define ASCCON_ODD 0x1000 -#define ASCCON_BRS 0x2000 -#define ASCCON_LB 0x4000 -#define ASCCON_R 0x8000 -#define ASCCON_ANY (ASCCON_PE|ASCCON_FE|ASCCON_OE) - -/* WHBCON register's bits and bitfields */ -#define ASCWHBCON_CLRREN 0x0010 -#define ASCWHBCON_SETREN 0x0020 -#define ASCWHBCON_CLRPE 0x0100 -#define ASCWHBCON_CLRFE 0x0200 -#define ASCWHBCON_CLROE 0x0400 -#define ASCWHBCON_SETPE 0x0800 -#define ASCWHBCON_SETFE 0x1000 -#define ASCWHBCON_SETOE 0x2000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 -#define ASCABCON_EMMASK 0x0300 - #define ASCABCON_EMOFF 8 - #define ASCABCON_EM_DISAB 0x0 - #define ASCABCON_EM_DURAB 0x1 - #define ASCABCON_EM_ALWAYS 0x2 -#define ASCABCON_TXINV 0x0400 -#define ASCABCON_RXINV 0x0800 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_SETABEN 0x0001 -#define ASCWHBABCON_CLRABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_SETSCCDET 0x0040 -#define ASCWHBABSTAT_CLRSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXTMEN 0x0004 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXTMEN 0x0004 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -#endif /* __AMAZON_ASC_H */ - diff --git a/target/linux/amazon/files/include/asm-mips/mach-amazon/irq.h b/target/linux/amazon/files/include/asm-mips/mach-amazon/irq.h deleted file mode 100644 index e72b7d5c11..0000000000 --- a/target/linux/amazon/files/include/asm-mips/mach-amazon/irq.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __AMAZON_IRQ_H -#define __AMAZON_IRQ_H - -#define NR_IRQS 256 -#include_next - -#endif diff --git a/target/linux/amazon/files/include/asm-mips/mach-amazon/mangle-port.h b/target/linux/amazon/files/include/asm-mips/mach-amazon/mangle-port.h deleted file mode 100644 index 9aefebbe63..0000000000 --- a/target/linux/amazon/files/include/asm-mips/mach-amazon/mangle-port.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H -#define __ASM_MACH_GENERIC_MANGLE_PORT_H - -#define __swizzle_addr_b(port) (port) -#define __swizzle_addr_w(port) ((port) ^ 2) -#define __swizzle_addr_l(port) (port) -#define __swizzle_addr_q(port) (port) - -/* - * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; - * less sane hardware forces software to fiddle with this... - * - * Regardless, if the host bus endianness mismatches that of PCI/ISA, then - * you can't have the numerical value of data and byte addresses within - * multibyte quantities both preserved at the same time. Hence two - * variations of functions: non-prefixed ones that preserve the value - * and prefixed ones that preserve byte addresses. The latters are - * typically used for moving raw data between a peripheral and memory (cf. - * string I/O functions), hence the "__mem_" prefix. - */ -#if defined(CONFIG_SWAP_IO_SPACE) - -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) le16_to_cpu(x) -# define __mem_ioswabw(a,x) (x) -# define ioswabl(a,x) le32_to_cpu(x) -# define __mem_ioswabl(a,x) (x) -# define ioswabq(a,x) le64_to_cpu(x) -# define __mem_ioswabq(a,x) (x) - -#else - -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) - -#endif - -#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */ diff --git a/target/linux/amazon/image/Makefile b/target/linux/amazon/image/Makefile deleted file mode 100644 index 6946f89adc..0000000000 --- a/target/linux/amazon/image/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Image/BuildKernel - $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.lzma - mkimage -A mips -O linux -T kernel -C lzma -a 0x80002000 -e \ - 0x80002000 \ - -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ - -d $(KDIR)/vmlinux.lzma $(KDIR)/uImage - - cp $(KDIR)/uImage $(BIN_DIR)/openwrt-$(BOARD)-uImage -endef - -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(BIN_DIR)/openwrt-$(BOARD)-$(1).image) -endef - -define Image/Build - cat $(KDIR)/uImage $(KDIR)/root.$(1) > $(BIN_DIR)/openwrt-$(BOARD)-$(1).image - $(call Image/Build/$(1),$(1)) -endef - - -$(eval $(call BuildImage)) diff --git a/target/linux/amazon/patches/017-wdt-driver.patch b/target/linux/amazon/patches/017-wdt-driver.patch deleted file mode 100644 index fa52fcb861..0000000000 --- a/target/linux/amazon/patches/017-wdt-driver.patch +++ /dev/null @@ -1,12 +0,0 @@ -Index: linux-2.6.21.7/drivers/char/watchdog/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/char/watchdog/Makefile -+++ linux-2.6.21.7/drivers/char/watchdog/Makefile -@@ -74,6 +74,7 @@ obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o - # MIPS Architecture - obj-$(CONFIG_INDYDOG) += indydog.o - obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o -+obj-$(CONFIG_AMAZON_WDT) += amazon_wdt.o - - # S390 Architecture - diff --git a/target/linux/amazon/patches/100-board.patch b/target/linux/amazon/patches/100-board.patch deleted file mode 100644 index 0293b04b57..0000000000 --- a/target/linux/amazon/patches/100-board.patch +++ /dev/null @@ -1,65 +0,0 @@ -Index: linux-2.6.21.7/arch/mips/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/arch/mips/Kconfig -+++ linux-2.6.21.7/arch/mips/Kconfig -@@ -159,6 +159,17 @@ config BASLER_EXCITE_PROTOTYPE - note that a kernel built with this option selected will not be - able to run on normal units. - -+config AMAZON -+ bool "Amazon support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select HAVE_STD_PC_SERIAL_PORT -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_HAS_EARLY_PRINTK -+ - config MIPS_COBALT - bool "Cobalt Server" - select DMA_NONCOHERENT -@@ -823,6 +834,7 @@ config TOSHIBA_RBTX4938 - - endchoice - -+source "arch/mips/amazon/Kconfig" - source "arch/mips/ddb5xxx/Kconfig" - source "arch/mips/gt64120/ev64120/Kconfig" - source "arch/mips/jazz/Kconfig" -Index: linux-2.6.21.7/arch/mips/Makefile -=================================================================== ---- linux-2.6.21.7.orig/arch/mips/Makefile -+++ linux-2.6.21.7/arch/mips/Makefile -@@ -267,6 +267,13 @@ libs-$(CONFIG_MIPS_XXS1500) += arch/mips - load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 - - # -+# Infineon AMAZON -+# -+core-$(CONFIG_AMAZON) += arch/mips/amazon/ -+cflags-$(CONFIG_AMAZON) += -Iinclude/asm-mips/mach-amazon -+load-$(CONFIG_AMAZON) += 0xffffffff80002000 -+ -+# - # Cobalt Server - # - core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ -Index: linux-2.6.21.7/include/asm-mips/bootinfo.h -=================================================================== ---- linux-2.6.21.7.orig/include/asm-mips/bootinfo.h -+++ linux-2.6.21.7/include/asm-mips/bootinfo.h -@@ -213,6 +213,12 @@ - #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ - #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ - -+/* -+ * Valid machtype for group ATHEROS -+ */ -+#define MACH_GROUP_INFINEON 27 -+#define MACH_INFINEON_AMAZON 0 -+ - #define CL_SIZE COMMAND_LINE_SIZE - - const char *get_system_type(void); diff --git a/target/linux/amazon/patches/110-char_drivers.patch b/target/linux/amazon/patches/110-char_drivers.patch deleted file mode 100644 index dd08498998..0000000000 --- a/target/linux/amazon/patches/110-char_drivers.patch +++ /dev/null @@ -1,12 +0,0 @@ -Index: linux-2.6.21.7/drivers/char/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/char/Makefile -+++ linux-2.6.21.7/drivers/char/Makefile -@@ -103,6 +103,7 @@ obj-$(CONFIG_IPMI_HANDLER) += ipmi/ - - obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o - obj-$(CONFIG_TCG_TPM) += tpm/ -+obj-$(CONFIG_AMAZONE_WDT) += amazone_wdt.o - - # Files generated that shall be removed upon make clean - clean-files := consolemap_deftbl.c defkeymap.c diff --git a/target/linux/amazon/patches/130-mtd_drivers.patch b/target/linux/amazon/patches/130-mtd_drivers.patch deleted file mode 100644 index 59735e4294..0000000000 --- a/target/linux/amazon/patches/130-mtd_drivers.patch +++ /dev/null @@ -1,9 +0,0 @@ -Index: linux-2.6.21.7/drivers/mtd/maps/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/mtd/maps/Makefile -+++ linux-2.6.21.7/drivers/mtd/maps/Makefile -@@ -72,3 +72,4 @@ obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o - obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o - obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o - obj-$(CONFIG_MTD_TQM834x) += tqm834x.o -+obj-$(CONFIG_AMAZON_MTD) += amazon.o diff --git a/target/linux/amazon/patches/140-net_drivers.patch b/target/linux/amazon/patches/140-net_drivers.patch deleted file mode 100644 index 1f010e5551..0000000000 --- a/target/linux/amazon/patches/140-net_drivers.patch +++ /dev/null @@ -1,10 +0,0 @@ -Index: linux-2.6.21.7/drivers/net/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/Makefile -+++ linux-2.6.21.7/drivers/net/Makefile -@@ -219,3 +219,5 @@ obj-$(CONFIG_NETCONSOLE) += netconsole.o - obj-$(CONFIG_FS_ENET) += fs_enet/ - - obj-$(CONFIG_NETXEN_NIC) += netxen/ -+ -+obj-$(CONFIG_AMAZON_NET_SW) += amazon_sw.o diff --git a/target/linux/amazon/patches/150-serial_driver.patch b/target/linux/amazon/patches/150-serial_driver.patch deleted file mode 100644 index 45bb8f4824..0000000000 --- a/target/linux/amazon/patches/150-serial_driver.patch +++ /dev/null @@ -1,12 +0,0 @@ -Index: linux-2.6.21.7/drivers/serial/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/serial/Makefile -+++ linux-2.6.21.7/drivers/serial/Makefile -@@ -5,6 +5,7 @@ - # - - obj-$(CONFIG_SERIAL_CORE) += serial_core.o -+obj-$(CONFIG_AMAZON_ASC_UART) += amazon_asc.o - obj-$(CONFIG_SERIAL_21285) += 21285.o - obj-$(CONFIG_SERIAL_8250) += 8250.o - obj-$(CONFIG_SERIAL_8250_PNP) += 8250_pnp.o diff --git a/target/linux/amazon/patches/160-cfi-swap.patch b/target/linux/amazon/patches/160-cfi-swap.patch deleted file mode 100644 index f9305fd88b..0000000000 --- a/target/linux/amazon/patches/160-cfi-swap.patch +++ /dev/null @@ -1,15 +0,0 @@ -Index: linux-2.6.21.7/drivers/mtd/chips/cfi_cmdset_0002.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/mtd/chips/cfi_cmdset_0002.c -+++ linux-2.6.21.7/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -1007,7 +1007,9 @@ static int __xipram do_write_oneword(str - int ret = 0; - map_word oldd; - int retry_cnt = 0; -- -+#ifdef CONFIG_AMAZON -+ adr ^= 2; -+#endif - adr += chip->start; - - spin_lock(chip->mutex); diff --git a/target/linux/brcm63xx/Makefile b/target/linux/brcm63xx/Makefile deleted file mode 100644 index 7005d0163e..0000000000 --- a/target/linux/brcm63xx/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=mips -BOARD:=brcm63xx -BOARDNAME:=Broadcom BCM963xx -FEATURES:=squashfs jffs2 broken usb atm -LINUX_VERSION:=2.6.25.17 - -include $(INCLUDE_DIR)/target.mk - -define Target/Description - Build firmware images for Broadcom based xDSL/routers - (e.g. Inventel Livebox, Siemens SE515) -endef - -$(eval $(call BuildTarget)) diff --git a/target/linux/brcm63xx/config-2.6.24 b/target/linux/brcm63xx/config-2.6.24 deleted file mode 100644 index 92c4a4f0a5..0000000000 --- a/target/linux/brcm63xx/config-2.6.24 +++ /dev/null @@ -1,299 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -# CONFIG_8139TOO is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_POPULATES_NODE_MAP=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ATM_DRIVERS=y -CONFIG_AUDIT=y -CONFIG_AUDIT_GENERIC=y -CONFIG_BASE_SMALL=0 -# CONFIG_BCM47XX is not set -CONFIG_BCM963XX=y -CONFIG_BINFMT_MISC=m -CONFIG_BITREVERSE=y -CONFIG_BLK_DEV_IO_TRACE=y -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_BSD_DISKLABEL is not set -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CICADA_PHY=m -# CONFIG_CIFS is not set -# CONFIG_CLS_U32_MARK is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_LOONGSON2 is not set -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR1=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -CONFIG_CRAMFS=y -CONFIG_DAVICOM_PHY=m -CONFIG_DEBUG_FS=y -CONFIG_DEFAULT_BIC=y -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_DEFAULT_TCP_CONG="bic" -# CONFIG_DEFAULT_VEGAS is not set -CONFIG_DEVPORT=y -# CONFIG_DM9000 is not set -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DUMMY=m -CONFIG_ELF_CORE=y -CONFIG_EQUALIZER=m -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_EXT3_FS_XATTR=y -# CONFIG_FIXED_PHY is not set -CONFIG_FS_MBCACHE=m -CONFIG_FS_POSIX_ACL=y -CONFIG_FUSE_FS=m -CONFIG_FW_LOADER=m -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -# CONFIG_HAMRADIO is not set -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -CONFIG_HZ=250 -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_I2C is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IDE is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_RAW is not set -# CONFIG_IP6_NF_TARGET_HL is not set -# CONFIG_IP6_NF_TARGET_LOG is not set -CONFIG_IPV6_PRIVACY=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_IP_SCTP=m -CONFIG_IRQ_CPU=y -# CONFIG_ISDN is not set -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_KMOD=y -CONFIG_LBD=y -# CONFIG_LEDS_ALIX is not set -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set -# CONFIG_LEMOTE_FULONG is not set -# CONFIG_LLC2 is not set -CONFIG_LXT_PHY=m -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MARVELL_PHY=m -# CONFIG_MDIO_BITBANG is not set -CONFIG_MII=m -# CONFIG_MINIX_FS is not set -CONFIG_MIPS=y -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -CONFIG_MTD_BCM963XX=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_BE_BYTE_SWAP=y -# CONFIG_MTD_CFI_GEOMETRY is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_NOSWAP is not set -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_DEBUG_VERBOSE=3 -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_ONENAND is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NET_VENDOR_3COM is not set -CONFIG_NLS=y -CONFIG_NLS_ASCII=m -# CONFIG_NO_IOPORT is not set -# CONFIG_PAGE_SIZE_16KB is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_64KB is not set -# CONFIG_PAGE_SIZE_8KB is not set -CONFIG_PCCARD=m -CONFIG_PCCARD_NONSTATIC=m -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PHYLIB=m -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -CONFIG_POSIX_MQUEUE=y -CONFIG_QSEMI_PHY=m -CONFIG_RELAY=y -# CONFIG_RTC is not set -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_WAIT_SCAN=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -CONFIG_SCTP_HMAC_MD5=y -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIO=m -CONFIG_SERIO_I8042=m -CONFIG_SERIO_LIBPS2=m -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_RAW is not set -CONFIG_SERIO_SERPORT=m -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -CONFIG_SHAPER=m -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -CONFIG_SLABINFO=y -# CONFIG_SMSC_PHY is not set -# CONFIG_SOUND is not set -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_SQUASHFS_EMBEDDED=y -CONFIG_SQUASHFS_VMALLOC=y -CONFIG_SSB_POSSIBLE=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -# CONFIG_TC35815 is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_TCP_CONG_HSTCP is not set -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_LP is not set -# CONFIG_TCP_CONG_SCALABLE is not set -CONFIG_TCP_CONG_VEGAS=m -# CONFIG_TCP_CONG_VENO is not set -CONFIG_TICK_ONESHOT=y -CONFIG_TIPC=m -# CONFIG_TIPC_ADVANCED is not set -# CONFIG_TIPC_DEBUG is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_TRAD_SIGNALS=y -CONFIG_USB=m -# CONFIG_USB_EHCI_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_UHCI_HCD is not set -# CONFIG_USER_NS is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIA_RHINE is not set -CONFIG_VLAN_8021Q=m -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WAN_ROUTER=m -# CONFIG_WATCHDOG is not set -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/brcm63xx/config-2.6.25 b/target/linux/brcm63xx/config-2.6.25 deleted file mode 100644 index c3efcb8741..0000000000 --- a/target/linux/brcm63xx/config-2.6.25 +++ /dev/null @@ -1,318 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -# CONFIG_8139TOO is not set -# CONFIG_ADM6996_PHY is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_POPULATES_NODE_MAP=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ATM_DRIVERS=y -CONFIG_AUDIT=y -CONFIG_AUDIT_GENERIC=y -CONFIG_BASE_SMALL=0 -# CONFIG_BCM47XX is not set -CONFIG_BCM963XX=y -CONFIG_BINFMT_MISC=m -CONFIG_BITREVERSE=y -CONFIG_BLK_DEV_IO_TRACE=y -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_BSD_DISKLABEL is not set -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CEVT_R4K=y -CONFIG_CICADA_PHY=m -# CONFIG_CIFS is not set -CONFIG_CLASSIC_RCU=y -# CONFIG_CLS_U32_MARK is not set -CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd console=ttyS0,115200" -# CONFIG_CONFIGFS_FS is not set -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_LOONGSON2 is not set -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR1=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -CONFIG_CRAMFS=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CSRC_R4K=y -CONFIG_DAVICOM_PHY=m -CONFIG_DEBUG_FS=y -CONFIG_DEFAULT_BIC=y -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_DEFAULT_TCP_CONG="bic" -# CONFIG_DEFAULT_VEGAS is not set -CONFIG_DEVPORT=y -# CONFIG_DM9000 is not set -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DUMMY=m -# CONFIG_E1000E_ENABLED is not set -CONFIG_ELF_CORE=y -CONFIG_EQUALIZER=m -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_EXT3_FS_XATTR=y -CONFIG_FS_MBCACHE=m -CONFIG_FS_POSIX_ACL=y -CONFIG_FUSE_FS=m -CONFIG_FW_LOADER=m -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -# CONFIG_HAMRADIO is not set -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_IDE=y -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -CONFIG_HZ=250 -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_I2C is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IDE is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_RAW is not set -# CONFIG_IP6_NF_TARGET_HL is not set -# CONFIG_IP6_NF_TARGET_LOG is not set -CONFIG_IPV6_PRIVACY=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_IP_SCTP=m -CONFIG_IRQ_CPU=y -# CONFIG_ISDN is not set -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_KMOD=y -CONFIG_LBD=y -# CONFIG_LEDS_ALIX is not set -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set -# CONFIG_LEMOTE_FULONG is not set -# CONFIG_LLC2 is not set -CONFIG_LXT_PHY=m -CONFIG_LZO_COMPRESS=m -CONFIG_LZO_DECOMPRESS=m -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MARVELL_PHY=m -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MEMSTICK is not set -CONFIG_MII=m -# CONFIG_MINIX_FS is not set -CONFIG_MIPS=y -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -CONFIG_MTD_BCM963XX=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_BE_BYTE_SWAP=y -# CONFIG_MTD_CFI_GEOMETRY is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_NOSWAP is not set -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_CONCAT=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_ONENAND is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MVSWITCH_PHY is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NET_VENDOR_3COM is not set -CONFIG_NLS=y -CONFIG_NLS_ASCII=m -# CONFIG_NO_IOPORT is not set -# CONFIG_PAGE_SIZE_16KB is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_64KB is not set -# CONFIG_PAGE_SIZE_8KB is not set -CONFIG_PCCARD=m -CONFIG_PCCARD_NONSTATIC=m -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PHYLIB=m -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -CONFIG_POSIX_MQUEUE=y -CONFIG_QSEMI_PHY=m -# CONFIG_R6040 is not set -# CONFIG_REALTEK_PHY is not set -CONFIG_RELAY=y -# CONFIG_RTC is not set -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_WAIT_SCAN=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -CONFIG_SCTP_HMAC_MD5=y -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIO=m -CONFIG_SERIO_I8042=m -CONFIG_SERIO_LIBPS2=m -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_RAW is not set -CONFIG_SERIO_SERPORT=m -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -CONFIG_SLABINFO=y -# CONFIG_SMSC_PHY is not set -# CONFIG_SOUND is not set -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_SQUASHFS_EMBEDDED=y -CONFIG_SQUASHFS_VMALLOC=y -CONFIG_SSB_POSSIBLE=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -# CONFIG_TC35815 is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_TCP_CONG_HSTCP is not set -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_LP is not set -# CONFIG_TCP_CONG_SCALABLE is not set -CONFIG_TCP_CONG_VEGAS=m -# CONFIG_TCP_CONG_VENO is not set -# CONFIG_THERMAL is not set -CONFIG_TICK_ONESHOT=y -CONFIG_TIPC=m -# CONFIG_TIPC_ADVANCED is not set -# CONFIG_TIPC_DEBUG is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_TRAD_SIGNALS=y -CONFIG_USB=m -# CONFIG_USB_EHCI_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_SERIAL_CH341 is not set -CONFIG_USB_SUPPORT=y -# CONFIG_USB_UHCI_HCD is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIA_RHINE is not set -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_VLAN_8021Q=m -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WAN_ROUTER=m -# CONFIG_WATCHDOG is not set -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/brcm63xx/files/arch/mips/bcm963xx/Makefile b/target/linux/brcm63xx/files/arch/mips/bcm963xx/Makefile deleted file mode 100644 index a9d1e55979..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/bcm963xx/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile for the Broadcom BCM963xx SoC specific parts of the kernel -# -# Copyright (C) 2004 Broadcom Corporation -# -obj-y := irq.o prom.o setup.o time.o ser_init.o int-handler.o info.o wdt.o - -SRCBASE := $(TOPDIR) -EXTRA_CFLAGS += -I$(SRCBASE)/include diff --git a/target/linux/brcm63xx/files/arch/mips/bcm963xx/info.c b/target/linux/brcm63xx/files/arch/mips/bcm963xx/info.c deleted file mode 100644 index d50b601e22..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/bcm963xx/info.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * $Id$ - * - * Copyright (C) 2007 OpenWrt.org - * Copyright (C) 2007 Gabor Juhos - * Copyright (C) 2007 Florian Fainelli - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static char *boot_loader_names[BOOT_LOADER_LAST+1] = { - [BOOT_LOADER_UNKNOWN] = "Unknown", - [BOOT_LOADER_CFE] = "CFE", - [BOOT_LOADER_REDBOOT] = "RedBoot", - [BOOT_LOADER_CFE2] = "CFEv2" -}; - -/* boot loaders specific definitions */ -#define CFE_EPTSEAL 0x43464531 /* CFE1 is the magic number to recognize CFE from other bootloaders */ - -int boot_loader_type; -/* - * Boot loader detection routines - */ -static int __init detect_cfe(void) -{ - /* - * This method only works, when we are booted directly from the CFE. - */ - uint32_t cfe_handle = (uint32_t) fw_arg0; - uint32_t cfe_a1_val = (uint32_t) fw_arg1; - uint32_t cfe_entry = (uint32_t) fw_arg2; - uint32_t cfe_seal = (uint32_t) fw_arg3; - - /* Check for CFE by finding the CFE magic number */ - if (cfe_seal != CFE_EPTSEAL) - /* We are not booted from CFE */ - return 0; - - /* cfe_a1_val must be 0, because only one CPU present in the ADM5120 SoC */ - if (cfe_a1_val != 0) - return 0; - - /* The cfe_handle, and the cfe_entry must be kernel mode addresses */ - if ((cfe_handle < KSEG0) || (cfe_entry < KSEG0)) - return 0; - - return 1; -} - -static int __init detect_redboot(void) -{ - /* On Inventel Livebox, the boot loader is passed as a command line argument, check for it */ - if (!strncmp(arcs_cmdline, "boot_loader=RedBoot", 19)) - return 1; - return 0; -} - -void __init detect_bootloader(void) -{ - if (detect_cfe()) { - boot_loader_type = BOOT_LOADER_CFE; - } - - if (detect_redboot()) { - boot_loader_type = BOOT_LOADER_REDBOOT; - } - else { - /* Some devices are using CFE, but it is not detected as is */ - boot_loader_type = BOOT_LOADER_CFE2; - } - printk("Boot loader is : %s\n", boot_loader_names[boot_loader_type]); -} - -void __init detect_board(void) -{ - switch (boot_loader_type) - { - case BOOT_LOADER_CFE: - break; - case BOOT_LOADER_REDBOOT: - break; - default: - break; - } -} - -EXPORT_SYMBOL(boot_loader_type); diff --git a/target/linux/brcm63xx/files/arch/mips/bcm963xx/int-handler.S b/target/linux/brcm63xx/files/arch/mips/bcm963xx/int-handler.S deleted file mode 100644 index a7a9c9d20c..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/bcm963xx/int-handler.S +++ /dev/null @@ -1,59 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -/* - * Generic interrupt handler for Broadcom MIPS boards - */ - -#include - -#include -#include -#include -#include - -/* - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 Combined hardware interrupt (hw0) - * 3 Hardware - * 4 Hardware - * 5 Hardware - * 6 Hardware - * 7 R4k timer - */ - - .text - .set noreorder - .set noat - .align 5 - NESTED(brcmIRQ, PT_SIZE, sp) - SAVE_ALL - CLI - .set noreorder - .set at - - jal plat_irq_dispatch - move a0, sp - - j ret_from_irq - nop - - END(brcmIRQ) diff --git a/target/linux/brcm63xx/files/arch/mips/bcm963xx/irq.c b/target/linux/brcm63xx/files/arch/mips/bcm963xx/irq.c deleted file mode 100644 index 62a848bd7d..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/bcm963xx/irq.c +++ /dev/null @@ -1,259 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -/* - * Interrupt control functions for Broadcom 963xx MIPS boards - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include <6348_map_part.h> -#include <6348_intr.h> -#include -#include - -static void irq_dispatch_int(void) -{ - unsigned int pendingIrqs; - static unsigned int irqBit; - static unsigned int isrNumber = 31; - - pendingIrqs = PERF->IrqStatus & PERF->IrqMask; - if (!pendingIrqs) { - return; - } - - while (1) { - irqBit <<= 1; - isrNumber++; - if (isrNumber == 32) { - isrNumber = 0; - irqBit = 0x1; - } - if (pendingIrqs & irqBit) { - PERF->IrqMask &= ~irqBit; // mask - do_IRQ(isrNumber + INTERNAL_ISR_TABLE_OFFSET); - break; - } - } -} - -static void irq_dispatch_ext(uint32 irq) -{ - if (!(PERF->ExtIrqCfg & (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)))) { - printk("**** Ext IRQ mask. Should not dispatch ****\n"); - } - /* disable and clear interrupt in the controller */ - PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT)); - PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); - do_IRQ(irq); -} - - -//extern void brcm_timer_interrupt(struct pt_regs *regs); - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long cause; - - cause = read_c0_status() & read_c0_cause() & ST0_IM; - if (cause & CAUSEF_IP7) - do_IRQ(7); - else if (cause & CAUSEF_IP2) - irq_dispatch_int(); - else if (cause & CAUSEF_IP3) - irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_0); - else if (cause & CAUSEF_IP4) - irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_1); - else if (cause & CAUSEF_IP5) - irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_2); - else if (cause & CAUSEF_IP6) { - irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_3); - local_irq_disable(); - } -} - - -void enable_brcm_irq(unsigned int irq) -{ - unsigned long flags; - - local_irq_save(flags); - if( irq >= INTERNAL_ISR_TABLE_OFFSET ) { - PERF->IrqMask |= (1 << (irq - INTERNAL_ISR_TABLE_OFFSET)); - } - else if (irq >= INTERRUPT_ID_EXTERNAL_0 && irq <= INTERRUPT_ID_EXTERNAL_3) { - /* enable and clear interrupt in the controller */ - PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT)); - PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); - } - local_irq_restore(flags); -} - -void disable_brcm_irq(unsigned int irq) -{ - unsigned long flags; - - local_irq_save(flags); - if( irq >= INTERNAL_ISR_TABLE_OFFSET ) { - PERF->IrqMask &= ~(1 << (irq - INTERNAL_ISR_TABLE_OFFSET)); - } - else if (irq >= INTERRUPT_ID_EXTERNAL_0 && irq <= INTERRUPT_ID_EXTERNAL_3) { - /* disable interrupt in the controller */ - PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); - } - local_irq_restore(flags); -} - -void ack_brcm_irq(unsigned int irq) -{ - /* Already done in brcm_irq_dispatch */ -} - -unsigned int startup_brcm_irq(unsigned int irq) -{ - enable_brcm_irq(irq); - - return 0; /* never anything pending */ -} - -unsigned int startup_brcm_none(unsigned int irq) -{ - return 0; -} - -void end_brcm_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_brcm_irq(irq); -} - -void end_brcm_none(unsigned int irq) -{ -} - -static struct hw_interrupt_type brcm_irq_type = { - .typename = "MIPS", - .startup = startup_brcm_irq, - .shutdown = disable_brcm_irq, - .enable = enable_brcm_irq, - .disable = disable_brcm_irq, - .ack = ack_brcm_irq, - .end = end_brcm_irq, - .set_affinity = NULL -}; - -static struct hw_interrupt_type brcm_irq_no_end_type = { - .typename = "MIPS", - .startup = startup_brcm_none, - .shutdown = disable_brcm_irq, - .enable = enable_brcm_irq, - .disable = disable_brcm_irq, - .ack = ack_brcm_irq, - .end = end_brcm_none, - .set_affinity = NULL -}; - -void __init arch_init_irq(void) -{ - int i; - - clear_c0_status(ST0_BEV); - change_c0_status(ST0_IM, (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)); - - for (i = 0; i < NR_IRQS; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &brcm_irq_type; - } -} - -int request_external_irq(unsigned int irq, - FN_HANDLER handler, - unsigned long irqflags, - const char * devname, - void *dev_id) -{ - unsigned long flags; - - local_irq_save(flags); - - PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT)); // Clear - PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); // Mask - PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_INSENS_SHFT)); // Edge insesnsitive - PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_LEVEL_SHFT)); // Level triggered - PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_SENSE_SHFT)); // Low level - - local_irq_restore(flags); - - return( request_irq(irq, handler, irqflags, devname, dev_id) ); -} - -/* VxWorks compatibility function(s). */ - -unsigned int BcmHalMapInterrupt(FN_HANDLER pfunc, unsigned int param, - unsigned int interruptId) -{ - int nRet = -1; - char *devname; - - devname = kmalloc(16, GFP_KERNEL); - if (devname) - sprintf( devname, "brcm_%d", interruptId ); - - /* Set the IRQ description to not automatically enable the interrupt at - * the end of an ISR. The driver that handles the interrupt must - * explicitly call BcmHalInterruptEnable or enable_brcm_irq. This behavior - * is consistent with interrupt handling on VxWorks. - */ - irq_desc[interruptId].chip = &brcm_irq_no_end_type; - - if( interruptId >= INTERNAL_ISR_TABLE_OFFSET ) - { - printk("BcmHalMapInterrupt : internal IRQ\n"); - nRet = request_irq( interruptId, pfunc, IRQF_DISABLED, devname, (void *) param ); - } - else if (interruptId >= INTERRUPT_ID_EXTERNAL_0 && interruptId <= INTERRUPT_ID_EXTERNAL_3) - { - printk("BcmHalMapInterrupt : external IRQ\n"); - nRet = request_external_irq( interruptId, pfunc, IRQF_DISABLED, devname, (void *) param ); - } - - return( nRet ); -} - - -EXPORT_SYMBOL(enable_brcm_irq); -EXPORT_SYMBOL(disable_brcm_irq); -EXPORT_SYMBOL(request_external_irq); -EXPORT_SYMBOL(BcmHalMapInterrupt); - diff --git a/target/linux/brcm63xx/files/arch/mips/bcm963xx/prom.c b/target/linux/brcm63xx/files/arch/mips/bcm963xx/prom.c deleted file mode 100644 index 5ebadc6679..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/bcm963xx/prom.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - Copyright 2004 Broadcom Corp. All Rights Reserved. - Copyright 2007 OpenWrt,org, Florian Fainelli - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -*/ -/* - * prom.c: PROM library initialization code. - * - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "../cfe/cfe_private.h" - -extern void __init detect_bootloader(void); -extern void serial_init(void); -extern int boot_loader_type; - -#define MACH_BCM MACH_BCM96348 - -const char *get_system_type(void) -{ - return "Broadcom BCM963xx"; -} - -void __init prom_init(void) -{ - serial_init(); - - printk("%s prom init\n", get_system_type() ); - - PERF->IrqMask = 0; - - /* Detect the bootloader */ - detect_bootloader(); - - /* Register 16MB RAM minus the ADSL SDRAM by default */ - add_memory_region(0, (0x01000000 - ADSL_SDRAM_IMAGE_SIZE), BOOT_MEM_RAM); - -} - -void __init prom_free_prom_memory(void) -{ - /* We do not have any memory to free */ -} diff --git a/target/linux/brcm63xx/files/arch/mips/bcm963xx/ser_init.c b/target/linux/brcm63xx/files/arch/mips/bcm963xx/ser_init.c deleted file mode 100644 index bb745aec6e..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/bcm963xx/ser_init.c +++ /dev/null @@ -1,181 +0,0 @@ -/* -<:copyright-gpl - Copyright 2004 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -/* - * Broadcom bcm63xx serial port initialization, also prepare for printk - * by registering with console_init - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include <6348_map_part.h> -#include - -#define SER63XX_DEFAULT_BAUD 115200 -#define BD_BCM63XX_TIMER_CLOCK_INPUT (FPERIPH) -#define stUart ((volatile Uart * const) UART_BASE) - -// Transmit interrupts -#define TXINT (TXFIFOEMT | TXUNDERR | TXOVFERR) -// Receive interrupts -#define RXINT (RXFIFONE | RXOVFERR) - -/* -------------------------------------------------------------------------- - Name: serial_init - Purpose: Initalize the UART --------------------------------------------------------------------------- */ -void __init serial_init(void) -{ - u32 tmpVal = SER63XX_DEFAULT_BAUD; - ULONG clockFreqHz; - -#if defined(CONFIG_BCM96345) - // Make sure clock is ticking - PERF->blkEnables |= UART_CLK_EN; -#endif - - /* Dissable channel's receiver and transmitter. */ - stUart->control &= ~(BRGEN|TXEN|RXEN); - - /*--------------------------------------------------------------------*/ - /* Write the table value to the clock select register. */ - /* DPullen - this is the equation to use: */ - /* value = clockFreqHz / baud / 32-1; */ - /* (snmod) Actually you should also take into account any necessary */ - /* rounding. Divide by 16, look at lsb, if 0, divide by 2 */ - /* and subtract 1. If 1, just divide by 2 */ - /*--------------------------------------------------------------------*/ - clockFreqHz = BD_BCM63XX_TIMER_CLOCK_INPUT; - tmpVal = (clockFreqHz / tmpVal) / 16; - if( tmpVal & 0x01 ) - tmpVal /= 2; //Rounding up, so sub is already accounted for - else - tmpVal = (tmpVal / 2) - 1; // Rounding down so we must sub 1 - stUart->baudword = tmpVal; - - /* Finally, re-enable the transmitter and receiver. */ - stUart->control |= (BRGEN|TXEN|RXEN); - - stUart->config = (BITS8SYM | ONESTOP); - // Set the FIFO interrupt depth ... stUart->fifocfg = 0xAA; - stUart->fifoctl = RSTTXFIFOS | RSTRXFIFOS; - stUart->intMask = 0; - stUart->intMask = RXINT | TXINT; -} - - -/* prom_putc() - * Output a character to the UART - */ -void prom_putc(char c) -{ - /* Wait for Tx uffer to empty */ - while (! (READ16(stUart->intStatus) & TXFIFOEMT)); - /* Send character */ - stUart->Data = c; -} - -/* prom_puts() - * Write a string to the UART - */ -void prom_puts(const char *s) -{ - while (*s) { - if (*s == '\n') { - prom_putc('\r'); - } - prom_putc(*s++); - } -} - - -/* prom_getc_nowait() - * Returns a character from the UART - * Returns -1 if no characters available or corrupted - */ -int prom_getc_nowait(void) -{ - uint16 uStatus; - int cData = -1; - - uStatus = READ16(stUart->intStatus); - - if (uStatus & RXFIFONE) { /* Do we have a character? */ - cData = READ16(stUart->Data) & 0xff; /* Read character */ - if (uStatus & (RXFRAMERR | RXPARERR)) { /* If we got an error, throw it away */ - cData = -1; - } - } - - return cData; -} - -/* prom_getc() - * Returns a charcter from the serial port - * Will block until it receives a valid character -*/ -char prom_getc(void) -{ - int cData = -1; - - /* Loop until we get a valid character */ - while(cData == -1) { - cData = prom_getc_nowait(); - } - return (char) cData; -} - -/* prom_testc() - * Returns 0 if no characters available - */ -int prom_testc(void) -{ - uint16 uStatus; - - uStatus = READ16(stUart->intStatus); - - return (uStatus & RXFIFONE); -} - -#if defined (CONFIG_REMOTE_DEBUG) -/* Prevent other code from writing to the serial port */ -void _putc(char c) { } -void _puts(const char *ptr) { } -#else -/* Low level outputs call prom routines */ -void _putc(char c) { - prom_putc(c); -} -void _puts(const char *ptr) { - prom_puts(ptr); -} -#endif diff --git a/target/linux/brcm63xx/files/arch/mips/bcm963xx/setup.c b/target/linux/brcm63xx/files/arch/mips/bcm963xx/setup.c deleted file mode 100644 index 58472783f4..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/bcm963xx/setup.c +++ /dev/null @@ -1,472 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -/* - * Generic setup routines for Broadcom 963xx MIPS boards - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void brcm_time_init(void); -extern int boot_loader_type; - -#include -#include -#include -#include <6348_map_part.h> -#include - -static volatile MpiRegisters * mpi = (MpiRegisters *)(MPI_BASE); - -/* This function should be in a board specific directory. For now, - * assume that all boards that include this file use a Broadcom chip - * with a soft reset bit in the PLL control register. - */ -static void brcm_machine_restart(char *command) -{ - const unsigned long ulSoftReset = 0x00000001; - unsigned long *pulPllCtrl = (unsigned long *) 0xfffe0008; - *pulPllCtrl |= ulSoftReset; -} - -static void brcm_machine_halt(void) -{ - printk("System halted\n"); - while (1); -} - -static void mpi_SetLocalPciConfigReg(uint32 reg, uint32 value) -{ - /* write index then value */ - mpi->pcicfgcntrl = PCI_CFG_REG_WRITE_EN + reg;; - mpi->pcicfgdata = value; -} - -static uint32 mpi_GetLocalPciConfigReg(uint32 reg) -{ - /* write index then get value */ - mpi->pcicfgcntrl = PCI_CFG_REG_WRITE_EN + reg;; - return mpi->pcicfgdata; -} - -/* - * mpi_ResetPcCard: Set/Reset the PcCard - */ -static void mpi_ResetPcCard(int cardtype, BOOL bReset) -{ - if (cardtype == MPI_CARDTYPE_NONE) { - return; - } - - if (cardtype == MPI_CARDTYPE_CARDBUS) { - bReset = ! bReset; - } - - if (bReset) { - mpi->pcmcia_cntl1 = (mpi->pcmcia_cntl1 & ~PCCARD_CARD_RESET); - } else { - mpi->pcmcia_cntl1 = (mpi->pcmcia_cntl1 | PCCARD_CARD_RESET); - } -} - -/* - * mpi_ConfigCs: Configure an MPI/EBI chip select - */ -static void mpi_ConfigCs(uint32 cs, uint32 base, uint32 size, uint32 flags) -{ - mpi->cs[cs].base = ((base & 0x1FFFFFFF) | size); - mpi->cs[cs].config = flags; -} - -/* - * mpi_InitPcmciaSpace - */ -static void mpi_InitPcmciaSpace(void) -{ - // ChipSelect 4 controls PCMCIA Memory accesses - mpi_ConfigCs(PCMCIA_COMMON_BASE, pcmciaMem, EBI_SIZE_1M, (EBI_WORD_WIDE|EBI_ENABLE)); - // ChipSelect 5 controls PCMCIA Attribute accesses - mpi_ConfigCs(PCMCIA_ATTRIBUTE_BASE, pcmciaAttr, EBI_SIZE_1M, (EBI_WORD_WIDE|EBI_ENABLE)); - // ChipSelect 6 controls PCMCIA I/O accesses - mpi_ConfigCs(PCMCIA_IO_BASE, pcmciaIo, EBI_SIZE_64K, (EBI_WORD_WIDE|EBI_ENABLE)); - - mpi->pcmcia_cntl2 = ((PCMCIA_ATTR_ACTIVE << RW_ACTIVE_CNT_BIT) | - (PCMCIA_ATTR_INACTIVE << INACTIVE_CNT_BIT) | - (PCMCIA_ATTR_CE_SETUP << CE_SETUP_CNT_BIT) | - (PCMCIA_ATTR_CE_HOLD << CE_HOLD_CNT_BIT)); - - mpi->pcmcia_cntl2 |= (PCMCIA_HALFWORD_EN | PCMCIA_BYTESWAP_DIS); -} - -/* - * cardtype_vcc_detect: PC Card's card detect and voltage sense connection - * - * CD1#/ CD2#/ VS1#/ VS2#/ Card Initial Vcc - * CCD1# CCD2# CVS1 CVS2 Type - * - * GND GND open open 16-bit 5 vdc - * - * GND GND GND open 16-bit 3.3 vdc - * - * GND GND open GND 16-bit x.x vdc - * - * GND GND GND GND 16-bit 3.3 & x.x vdc - * - *==================================================================== - * - * CVS1 GND CCD1# open CardBus 3.3 vdc - * - * GND CVS2 open CCD2# CardBus x.x vdc - * - * GND CVS1 CCD2# open CardBus y.y vdc - * - * GND CVS2 GND CCD2# CardBus 3.3 & x.x vdc - * - * CVS2 GND open CCD1# CardBus x.x & y.y vdc - * - * GND CVS1 CCD2# open CardBus 3.3, x.x & y.y vdc - * - */ -static int cardtype_vcc_detect(void) -{ - uint32 data32; - int cardtype; - - cardtype = MPI_CARDTYPE_NONE; - mpi->pcmcia_cntl1 = 0x0000A000; // Turn on the output enables and drive - // the CVS pins to 0. - data32 = mpi->pcmcia_cntl1; - switch (data32 & 0x00000003) // Test CD1# and CD2#, see if card is plugged in. - { - case 0x00000003: // No Card is in the slot. - printk("mpi: No Card is in the PCMCIA slot\n"); - break; - - case 0x00000002: // Partial insertion, No CD2#. - printk("mpi: Card in the PCMCIA slot partial insertion, no CD2 signal\n"); - break; - - case 0x00000001: // Partial insertion, No CD1#. - printk("mpi: Card in the PCMCIA slot partial insertion, no CD1 signal\n"); - break; - - case 0x00000000: - mpi->pcmcia_cntl1 = 0x0000A0C0; // Turn off the CVS output enables and - // float the CVS pins. - mdelay(1); - data32 = mpi->pcmcia_cntl1; - // Read the Register. - switch (data32 & 0x0000000C) // See what is on the CVS pins. - { - case 0x00000000: // CVS1 and CVS2 are tied to ground, only 1 option. - printk("mpi: Detected 3.3 & x.x 16-bit PCMCIA card\n"); - cardtype = MPI_CARDTYPE_PCMCIA; - break; - - case 0x00000004: // CVS1 is open or tied to CCD1/CCD2 and CVS2 is tied to ground. - // 2 valid voltage options. - switch (data32 & 0x00000003) // Test the values of CCD1 and CCD2. - { - case 0x00000003: // CCD1 and CCD2 are tied to 1 of the CVS pins. - // This is not a valid combination. - printk("mpi: Unknown card plugged into slot\n"); - break; - - case 0x00000002: // CCD2 is tied to either CVS1 or CVS2. - mpi->pcmcia_cntl1 = 0x0000A080; // Drive CVS1 to a 0. - mdelay(1); - data32 = mpi->pcmcia_cntl1; - if (data32 & 0x00000002) { // CCD2 is tied to CVS2, not valid. - printk("mpi: Unknown card plugged into slot\n"); - } else { // CCD2 is tied to CVS1. - printk("mpi: Detected 3.3, x.x and y.y Cardbus card\n"); - cardtype = MPI_CARDTYPE_CARDBUS; - } - break; - - case 0x00000001: // CCD1 is tied to either CVS1 or CVS2. - // This is not a valid combination. - printk("mpi: Unknown card plugged into slot\n"); - break; - - case 0x00000000: // CCD1 and CCD2 are tied to ground. - printk("mpi: Detected x.x vdc 16-bit PCMCIA card\n"); - cardtype = MPI_CARDTYPE_PCMCIA; - break; - } - break; - - case 0x00000008: // CVS2 is open or tied to CCD1/CCD2 and CVS1 is tied to ground. - // 2 valid voltage options. - switch (data32 & 0x00000003) // Test the values of CCD1 and CCD2. - { - case 0x00000003: // CCD1 and CCD2 are tied to 1 of the CVS pins. - // This is not a valid combination. - printk("mpi: Unknown card plugged into slot\n"); - break; - - case 0x00000002: // CCD2 is tied to either CVS1 or CVS2. - mpi->pcmcia_cntl1 = 0x0000A040; // Drive CVS2 to a 0. - mdelay(1); - data32 = mpi->pcmcia_cntl1; - if (data32 & 0x00000002) { // CCD2 is tied to CVS1, not valid. - printk("mpi: Unknown card plugged into slot\n"); - } else {// CCD2 is tied to CVS2. - printk("mpi: Detected 3.3 and x.x Cardbus card\n"); - cardtype = MPI_CARDTYPE_CARDBUS; - } - break; - - case 0x00000001: // CCD1 is tied to either CVS1 or CVS2. - // This is not a valid combination. - printk("mpi: Unknown card plugged into slot\n"); - break; - - case 0x00000000: // CCD1 and CCD2 are tied to ground. - cardtype = MPI_CARDTYPE_PCMCIA; - printk("mpi: Detected 3.3 vdc 16-bit PCMCIA card\n"); - break; - } - break; - - case 0x0000000C: // CVS1 and CVS2 are open or tied to CCD1/CCD2. - // 5 valid voltage options. - - switch (data32 & 0x00000003) // Test the values of CCD1 and CCD2. - { - case 0x00000003: // CCD1 and CCD2 are tied to 1 of the CVS pins. - // This is not a valid combination. - printk("mpi: Unknown card plugged into slot\n"); - break; - - case 0x00000002: // CCD2 is tied to either CVS1 or CVS2. - // CCD1 is tied to ground. - mpi->pcmcia_cntl1 = 0x0000A040; // Drive CVS2 to a 0. - mdelay(1); - data32 = mpi->pcmcia_cntl1; - if (data32 & 0x00000002) { // CCD2 is tied to CVS1. - printk("mpi: Detected y.y vdc Cardbus card\n"); - } else { // CCD2 is tied to CVS2. - printk("mpi: Detected x.x vdc Cardbus card\n"); - } - cardtype = MPI_CARDTYPE_CARDBUS; - break; - - case 0x00000001: // CCD1 is tied to either CVS1 or CVS2. - // CCD2 is tied to ground. - - mpi->pcmcia_cntl1 = 0x0000A040; // Drive CVS2 to a 0. - mdelay(1); - data32 = mpi->pcmcia_cntl1; - if (data32 & 0x00000001) {// CCD1 is tied to CVS1. - printk("mpi: Detected 3.3 vdc Cardbus card\n"); - } else { // CCD1 is tied to CVS2. - printk("mpi: Detected x.x and y.y Cardbus card\n"); - } - cardtype = MPI_CARDTYPE_CARDBUS; - break; - - case 0x00000000: // CCD1 and CCD2 are tied to ground. - cardtype = MPI_CARDTYPE_PCMCIA; - printk("mpi: Detected 5 vdc 16-bit PCMCIA card\n"); - break; - } - break; - - default: - printk("mpi: Unknown card plugged into slot\n"); - break; - - } - } - return cardtype; -} - -/* - * mpi_DetectPcCard: Detect the plugged in PC-Card - * Return: < 0 => Unknown card detected - * 0 => No card detected - * 1 => 16-bit card detected - * 2 => 32-bit CardBus card detected - */ -static int mpi_DetectPcCard(void) -{ - int cardtype; - - cardtype = cardtype_vcc_detect(); - switch(cardtype) { - case MPI_CARDTYPE_PCMCIA: - mpi->pcmcia_cntl1 &= ~0x0000e000; // disable enable bits - //mpi->pcmcia_cntl1 = (mpi->pcmcia_cntl1 & ~PCCARD_CARD_RESET); - mpi->pcmcia_cntl1 |= (PCMCIA_ENABLE | PCMCIA_GPIO_ENABLE); - mpi_InitPcmciaSpace(); - mpi_ResetPcCard(cardtype, FALSE); - // Hold card in reset for 10ms - mdelay(10); - mpi_ResetPcCard(cardtype, TRUE); - // Let card come out of reset - mdelay(100); - break; - case MPI_CARDTYPE_CARDBUS: - // 8 => CardBus Enable - // 1 => PCI Slot Number - // C => Float VS1 & VS2 - mpi->pcmcia_cntl1 = (mpi->pcmcia_cntl1 & 0xFFFF0000) | - CARDBUS_ENABLE | - (CARDBUS_SLOT << 8)| - VS2_OEN | - VS1_OEN; - /* access to this memory window will be to/from CardBus */ - mpi->l2pmremap1 |= CARDBUS_MEM; - - // Need to reset the Cardbus Card. There's no CardManager to do this, - // and we need to be ready for PCI configuration. - mpi_ResetPcCard(cardtype, FALSE); - // Hold card in reset for 10ms - mdelay(10); - mpi_ResetPcCard(cardtype, TRUE); - // Let card come out of reset - mdelay(100); - break; - default: - break; - } - return cardtype; -} - -static int mpi_init(void) -{ - unsigned long data; - unsigned int chipid, chiprev, sdramsize; - - printk("Broadcom BCM963xx MPI\n"); - chipid = (PERF->RevID & 0xFFFF0000) >> 16; - chiprev = (PERF->RevID & 0xFF); - - if (boot_loader_type == BOOT_LOADER_CFE) - sdramsize = boot_mem_map.map[0].size; - else - sdramsize = 0x01000000; - /* - * Init the pci interface - */ - data = GPIO->GPIOMode; // GPIO mode register - data |= GROUP2_PCI | GROUP1_MII_PCCARD; // PCI internal arbiter + Cardbus - GPIO->GPIOMode = data; // PCI internal arbiter - - /* - * In the BCM6348 CardBus support is defaulted to Slot 0 - * because there is no external IDSEL for CardBus. To disable - * the CardBus and allow a standard PCI card in Slot 0 - * set the cbus_idsel field to 0x1f. - */ - /* - uData = mpi->pcmcia_cntl1; - uData |= CARDBUS_IDSEL; - mpi->pcmcia_cntl1 = uData; - */ - // Setup PCI I/O Window range. Give 64K to PCI I/O - mpi->l2piorange = ~(BCM_PCI_IO_SIZE_64KB-1); - // UBUS to PCI I/O base address - mpi->l2piobase = BCM_PCI_IO_BASE & BCM_PCI_ADDR_MASK; - // UBUS to PCI I/O Window remap - mpi->l2pioremap = (BCM_PCI_IO_BASE | MEM_WINDOW_EN); - - // enable PCI related GPIO pins and data swap between system and PCI bus - mpi->locbuscntrl = (EN_PCI_GPIO | DIR_U2P_NOSWAP); - - /* Enable 6348 BusMaster and Memory access mode */ - data = mpi_GetLocalPciConfigReg(PCI_COMMAND); - data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - mpi_SetLocalPciConfigReg(PCI_COMMAND, data); - - /* Configure two 16 MByte PCI to System memory regions. */ - /* These memory regions are used when PCI device is a bus master */ - /* Accesses to the SDRAM from PCI bus will be "byte swapped" for this region */ - mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_3, BCM_HOST_MEM_SPACE1); - mpi->sp0remap = 0x0; - - /* Accesses to the SDRAM from PCI bus will not be "byte swapped" for this region */ - mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_4, BCM_HOST_MEM_SPACE2); - mpi->sp1remap = 0x0; - mpi->pcimodesel |= (PCI_BAR2_NOSWAP | 0x40); - - if ((chipid == 0x6348) && (chiprev == 0xb0)) { - mpi->sp0range = ~(sdramsize-1); - mpi->sp1range = ~(sdramsize-1); - } - /* - * Change 6348 PCI Cfg Reg. offset 0x40 to PCI memory read retry count infinity - * by set 0 in bit 8~15. This resolve read Bcm4306 srom return 0xffff in - * first read. - */ - data = mpi_GetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER); - data &= ~BRCM_PCI_CONFIG_TIMER_RETRY_MASK; - data |= 0x00000080; - mpi_SetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER, data); - - /* enable pci interrupt */ - mpi->locintstat |= (EXT_PCI_INT << 16); - - mpi_DetectPcCard(); - - ioport_resource.start = BCM_PCI_IO_BASE; - ioport_resource.end = BCM_PCI_IO_BASE + BCM_PCI_IO_SIZE_64KB; - -#if defined(CONFIG_USB) - PERF->blkEnables |= USBH_CLK_EN; - mdelay(100); - *USBH_NON_OHCI = NON_OHCI_BYTE_SWAP; -#endif - - return 0; -} - -void __init plat_mem_setup(void) -{ - _machine_restart = brcm_machine_restart; - _machine_halt = brcm_machine_halt; - pm_power_off = brcm_machine_halt; - - //board_time_init = brcm_time_init; - - /* mpi initialization */ - mpi_init(); -} diff --git a/target/linux/brcm63xx/files/arch/mips/bcm963xx/time.c b/target/linux/brcm63xx/files/arch/mips/bcm963xx/time.c deleted file mode 100644 index fa0fa71a7f..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/bcm963xx/time.c +++ /dev/null @@ -1,118 +0,0 @@ -/* -<:copyright-gpl - Copyright 2004 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -/* - * Setup time for Broadcom 963xx MIPS boards - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include <6348_map_part.h> -#include <6348_intr.h> -#include -#include - -static unsigned long r4k_offset; /* Amount to increment compare reg each time */ -static unsigned long r4k_cur; /* What counter should be at next timer irq */ - -/* ********************************************************************* - * calculateCpuSpeed() - * Calculate the BCM6348 CPU speed by reading the PLL strap register - * and applying the following formula: - * cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) - * Input parameters: - * none - * Return value: - * none - ********************************************************************* */ - -static inline unsigned long __init calculateCpuSpeed(void) -{ - u32 pllStrap = PERF->PllStrap; - int n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT; - int n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT; - int m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT; - - return (16 * (n1 + 1) * (n2 + 2) / (m1cpu + 1)) * 1000000; -} - - -static inline unsigned long __init cal_r4koff(void) -{ - mips_hpt_frequency = calculateCpuSpeed() / 2; - return (mips_hpt_frequency / HZ); -} - - -/* - * There are a lot of conceptually broken versions of the MIPS timer interrupt - * handler floating around. This one is rather different, but the algorithm - * is provably more robust. - */ -#if 0 -irqreturn_t brcm_timer_interrupt(struct pt_regs *regs) -{ - int irq = MIPS_TIMER_INT; - - irq_enter(); - kstat_this_cpu.irqs[irq]++; - - timer_interrupt(irq, regs); - irq_exit(); - return IRQ_HANDLED; -} -#endif - -void __init plat_time_init(void) -{ - unsigned int est_freq, flags; - local_irq_save(flags); - - printk("calculating r4koff... "); - r4k_offset = cal_r4koff(); - printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset); - - est_freq = 2 * r4k_offset * HZ; - est_freq += 5000; /* round */ - est_freq -= est_freq % 10000; - printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000, - (est_freq % 1000000) * 100 / 1000000); - local_irq_restore(flags); -} - -#if 0 -void __init plat_timer_setup(struct irqaction *irq) -{ - r4k_cur = (read_c0_count() + r4k_offset); - write_c0_compare(r4k_cur); - set_c0_status(IE_IRQ5); -} -#endif diff --git a/target/linux/brcm63xx/files/arch/mips/bcm963xx/wdt.c b/target/linux/brcm63xx/files/arch/mips/bcm963xx/wdt.c deleted file mode 100644 index 0ea36a67f0..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/bcm963xx/wdt.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Watchdog driver for the BCM963xx devices - * - * Copyright (C) 2007 OpenWrt.org - * Florian Fainelli - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -typedef struct bcm963xx_timer { - unsigned short unused0; - unsigned char timer_mask; -#define TIMER0EN 0x01 -#define TIMER1EN 0x02 -#define TIMER2EN 0x04 - unsigned char timer_ints; -#define TIMER0 0x01 -#define TIMER1 0x02 -#define TIMER2 0x04 -#define WATCHDOG 0x08 - unsigned long timer_ctl0; - unsigned long timer_ctl1; - unsigned long timer_ctl2; -#define TIMERENABLE 0x80000000 -#define RSTCNTCLR 0x40000000 - unsigned long timer_cnt0; - unsigned long timer_cnt1; - unsigned long timer_cnt2; - unsigned long wdt_def_count; - - /* Write 0xff00 0x00ff to Start timer - * Write 0xee00 0x00ee to Stop and re-load default count - * Read from this register returns current watch dog count - */ - unsigned long wdt_ctl; - - /* Number of 40-MHz ticks for WD Reset pulse to last */ - unsigned long wdt_rst_count; -} bcm963xx_timer; - -static struct bcm963xx_wdt_device { - struct completion stop; - volatile int running; - struct timer_list timer; - volatile int queue; - int default_ticks; - unsigned long inuse; -} bcm963xx_wdt_device; - -static int ticks = 1000; - -#define WDT_BASE 0xfffe0200 -#define WDT ((volatile bcm963xx_timer * const) WDT_BASE) - -#define BCM963XX_INTERVAL (HZ/10+1) - -static void bcm963xx_wdt_trigger(unsigned long unused) -{ - if (bcm963xx_wdt_device.running) - ticks--; - - /* Load the default ticking value into the reset counter register */ - WDT->wdt_rst_count = bcm963xx_wdt_device.default_ticks; - - if (bcm963xx_wdt_device.queue && ticks) { - bcm963xx_wdt_device.timer.expires = jiffies + BCM963XX_INTERVAL; - add_timer(&bcm963xx_wdt_device.timer); - } - else { - complete(&bcm963xx_wdt_device.stop); - } -} - -static void bcm963xx_wdt_reset(void) -{ - ticks = bcm963xx_wdt_device.default_ticks; - /* Also reload default count */ - WDT->wdt_def_count = ticks; - WDT->wdt_ctl = 0xee00; - WDT->wdt_ctl = 0x00ee; -} - -static void bcm963xx_wdt_start(void) -{ - if (!bcm963xx_wdt_device.queue) { - bcm963xx_wdt_device.queue; - /* Enable the watchdog by writing 0xff00 ,then 0x00ff to the control register */ - WDT->wdt_ctl = 0xff00; - WDT->wdt_ctl = 0x00ff; - bcm963xx_wdt_device.timer.expires = jiffies + BCM963XX_INTERVAL; - add_timer(&bcm963xx_wdt_device.timer); - } - bcm963xx_wdt_device.running++; -} - -static int bcm963xx_wdt_stop(void) -{ - if (bcm963xx_wdt_device.running) - bcm963xx_wdt_device.running = 0; - - ticks = bcm963xx_wdt_device.default_ticks; - - /* Stop the watchdog by writing 0xee00 then 0x00ee to the control register */ - WDT->wdt_ctl = 0xee00; - WDT->wdt_ctl = 0x00ee; - - return -EIO; -} - -static int bcm963xx_wdt_open(struct inode *inode, struct file *file) -{ - if (test_and_set_bit(0, &bcm963xx_wdt_device.inuse)) - return -EBUSY; - return nonseekable_open(inode, file); -} - -static int bcm963xx_wdt_release(struct inode *inode, struct file *file) -{ - clear_bit(0, &bcm963xx_wdt_device.inuse); - return 0; -} - -static int bcm963xx_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) -{ - void __user *argp = (void __user *)arg; - unsigned int value; - - static struct watchdog_info ident = { - .options = WDIOF_CARDRESET, - .identity = "BCM963xx WDT", - }; - - switch (cmd) { - case WDIOC_KEEPALIVE: - bcm963xx_wdt_reset(); - break; - case WDIOC_GETSTATUS: - /* Reading from the control register will return the current value */ - value = WDT->wdt_ctl; - if ( copy_to_user(argp, &value, sizeof(int)) ) - return -EFAULT; - break; - case WDIOC_GETSUPPORT: - if ( copy_to_user(argp, &ident, sizeof(ident)) ) - return -EFAULT; - break; - case WDIOC_SETOPTIONS: - if ( copy_from_user(&value, argp, sizeof(int)) ) - return -EFAULT; - switch(value) { - case WDIOS_ENABLECARD: - bcm963xx_wdt_start(); - break; - case WDIOS_DISABLECARD: - bcm963xx_wdt_stop(); - break; - default: - return -EINVAL; - } - break; - default: - return -ENOTTY; - } - return 0; -} - -static int bcm963xx_wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) -{ - if (!count) - return -EIO; - bcm963xx_wdt_reset(); - return count; -} - -static const struct file_operations bcm963xx_wdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = bcm963xx_wdt_write, - .ioctl = bcm963xx_wdt_ioctl, - .open = bcm963xx_wdt_open, - .release = bcm963xx_wdt_release, -}; - -static struct miscdevice bcm963xx_wdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &bcm963xx_wdt_fops, -}; - -static void __exit bcm963xx_wdt_exit(void) -{ - if (bcm963xx_wdt_device.queue ){ - bcm963xx_wdt_device.queue = 0; - wait_for_completion(&bcm963xx_wdt_device.stop); - } - misc_deregister(&bcm963xx_wdt_miscdev); -} - -static int __init bcm963xx_wdt_init(void) -{ - int ret = 0; - - printk("Broadcom BCM963xx Watchdog timer\n"); - - ret = misc_register(&bcm963xx_wdt_miscdev); - if (ret) { - printk(KERN_CRIT "Cannot register miscdev on minor=%d (err=%d)\n", WATCHDOG_MINOR, ret); - return ret; - } - init_completion(&bcm963xx_wdt_device.stop); - bcm963xx_wdt_device.queue = 0; - - clear_bit(0, &bcm963xx_wdt_device.inuse); - - init_timer(&bcm963xx_wdt_device.timer); - bcm963xx_wdt_device.timer.function = bcm963xx_wdt_trigger; - bcm963xx_wdt_device.timer.data = 0; - - bcm963xx_wdt_device.default_ticks = ticks; - return ret; -} - - -module_init(bcm963xx_wdt_init); -module_exit(bcm963xx_wdt_exit); - -MODULE_AUTHOR("Florian Fainelli "); -MODULE_DESCRIPTION("Broadcom BCM963xx Watchdog driver"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm63xx/files/arch/mips/cfe/Makefile b/target/linux/brcm63xx/files/arch/mips/cfe/Makefile deleted file mode 100644 index d9f046adf3..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/cfe/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Broadcom Common Firmware Environment support -# - -obj-y += cfe.o diff --git a/target/linux/brcm63xx/files/arch/mips/cfe/cfe.c b/target/linux/brcm63xx/files/arch/mips/cfe/cfe.c deleted file mode 100644 index 6d16111e1c..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/cfe/cfe.c +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Broadcom Common Firmware Environment (CFE) support - * - * Copyright 2000, 2001, 2002 - * Broadcom Corporation. All rights reserved. - * - * Copyright (C) 2006 Michael Buesch - * - * Original Authors: Mitch Lichtenberg, Chris Demetriou - * - * This software is furnished under license and may be used and copied only - * in accordance with the following terms and conditions. Subject to these - * conditions, you may download, copy, install, use, modify and distribute - * modified or unmodified copies of this software in source and/or binary - * form. No title or ownership is transferred hereby. - * - * 1) Any source code used, modified or distributed must reproduce and - * retain this copyright notice and list of conditions as they appear in - * the source file. - * - * 2) No right is granted to use any trade name, trademark, or logo of - * Broadcom Corporation. The "Broadcom Corporation" name may not be - * used to endorse or promote products derived from this software - * without the prior written permission of Broadcom Corporation. - * - * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE - * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE - * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "cfe_private.h" - - -static cfe_uint_t cfe_handle; -static int (*cfe_trampoline)(long handle, long iocb); - - -#include - -void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1, - unsigned long fwarg2, unsigned long fwarg3) -{ - if (fwarg3 == 0x80300000) { - /* WRT54G workaround */ - fwarg3 = CFE_EPTSEAL; - fwarg2 = 0xBFC00500; - } - if (fwarg3 != CFE_EPTSEAL) { - /* We are not booted from CFE */ - return; - } - if (fwarg1 == 0) { - /* We are on the boot CPU */ - cfe_handle = (cfe_uint_t)fwarg0; - cfe_trampoline = CFE_TO_PTR(fwarg2); - } -} - -int cfe_vprintk(const char *fmt, va_list args) -{ - static char buffer[1024]; - static DEFINE_SPINLOCK(lock); - static const char pfx[] = "CFE-console: "; - static const size_t pfx_len = sizeof(pfx) - 1; - unsigned long flags; - int len, cnt, pos; - int handle; - int res; - - if (!cfe_present()) - return -ENODEV; - - spin_lock_irqsave(&lock, flags); - handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); - if (CFE_ISERR(handle)) { - len = -EIO; - goto out; - } - strcpy(buffer, pfx); - len = vscnprintf(buffer + pfx_len, - sizeof(buffer) - pfx_len - 2, - fmt, args); - len += pfx_len; - /* The CFE console requires CR-LF line-ends. - * Add a CR, if we only terminate lines with a LF. - * This does only fix CR-LF at the end of the string. - * So for multiple lines, use multiple cfe_vprintk calls. - */ - if (len > 1 && - buffer[len - 1] == '\n' && buffer[len - 2] != '\r') { - buffer[len - 1] = '\r'; - buffer[len] = '\n'; - len += 1; - } - cnt = len; - pos = 0; - while (cnt > 0) { - res = cfe_write(handle, buffer + pos, len - pos); - if (CFE_ISERR(res)) { - len = -EIO; - goto out; - } - cnt -= res; - pos += res; - } -out: - spin_unlock_irqrestore(&lock, flags); - - return len; -} - -int cfe_printk(const char *fmt, ...) -{ - va_list args; - int res; - - va_start(args, fmt); - res = cfe_vprintk(fmt, args); - va_end(args); - - return res; -} - -static int cfe_iocb_dispatch(struct cfe_iocb *iocb) -{ - if (!cfe_present()) - return CFE_ERR_UNSUPPORTED; - return cfe_trampoline((long)cfe_handle, (long)iocb); -} - -int cfe_present(void) -{ - return (cfe_trampoline != NULL); -} - -int cfe_close(int handle) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_DEV_CLOSE; - iocb.handle = handle; - - err = cfe_iocb_dispatch(&iocb); - - return (CFE_ISERR(err)) ? err : iocb.status; -} - -int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_FW_CPUCTL; - iocb.psize = sizeof(struct cfe_iocb_cpuctl); - iocb.cpuctl.number = cpu; - iocb.cpuctl.command = CFE_CPU_CMD_START; - iocb.cpuctl.gp = gp; - iocb.cpuctl.sp = sp; - iocb.cpuctl.a1 = a1; - iocb.cpuctl.start_addr = (long)fn; - - err = cfe_iocb_dispatch(&iocb); - - return (CFE_ISERR(err)) ? err : iocb.status; -} - -int cfe_cpu_stop(int cpu) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_FW_CPUCTL; - iocb.psize = sizeof(struct cfe_iocb_cpuctl); - iocb.cpuctl.number = cpu; - iocb.cpuctl.command = CFE_CPU_CMD_STOP; - - err = cfe_iocb_dispatch(&iocb); - - return (CFE_ISERR(err)) ? err : iocb.status; -} - -int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_ENV_ENUM; - iocb.psize = sizeof(struct cfe_iocb_envbuf); - iocb.envbuf.index = idx; - iocb.envbuf.name = PTR_TO_CFE(name); - iocb.envbuf.name_len = namelen; - iocb.envbuf.val = PTR_TO_CFE(val); - iocb.envbuf.val_len = vallen; - - err = cfe_iocb_dispatch(&iocb); - - return (CFE_ISERR(err)) ? err : iocb.status; -} - -int cfe_enumdev(int idx, char *name, int namelen) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - - iocb.fcode = CFE_CMD_DEV_ENUM; - iocb.psize = sizeof(struct cfe_iocb_envbuf); - iocb.envbuf.index = idx; - iocb.envbuf.name = PTR_TO_CFE(name); - iocb.envbuf.name_len = namelen; - - err = cfe_iocb_dispatch(&iocb); - - return (CFE_ISERR(err)) ? err : iocb.status; -} - -int cfe_enummem(int idx, int flags, u64 *start, u64 *length, - u64 *type) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - - iocb.fcode = CFE_CMD_FW_MEMENUM; - iocb.flags = flags; - iocb.psize = sizeof(struct cfe_iocb_meminfo); - iocb.meminfo.index = idx; - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (!CFE_ISERR(iocb.status)) { - *start = iocb.meminfo.addr; - *length = iocb.meminfo.size; - *type = iocb.meminfo.type; - } - - return iocb.status; -} - -int cfe_exit(int warm, int status) -{ - struct cfe_iocb iocb; - int err; - -printk("CFE REBOOT\n"); - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_FW_RESTART; - if (warm) - iocb.flags = CFE_FLG_WARMSTART; - iocb.psize = sizeof(struct cfe_iocb_exitstat); - iocb.exitstat.status = status; - -printk("CALL\n"); - err = cfe_iocb_dispatch(&iocb); -printk("DONE\n"); - - return (CFE_ISERR(err)) ? err : iocb.status; -} - -int cfe_flushcache(int flags) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_FW_FLUSHCACHE; - iocb.flags = flags; - - err = cfe_iocb_dispatch(&iocb); - - return (CFE_ISERR(err)) ? err : iocb.status; -} - -int cfe_getdevinfo(char *name) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_DEV_GETINFO; - iocb.psize = sizeof(struct cfe_iocb_buf); - iocb.buffer.ptr = PTR_TO_CFE(name); - iocb.buffer.length = strlen(name); - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (CFE_ISERR(iocb.status)) - return iocb.status; - - return iocb.buffer.devflags; -} - -int cfe_getenv(char *name, char *dest, int destlen) -{ - struct cfe_iocb iocb; - int err; - - dest[0] = '\0'; - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_ENV_GET; - iocb.psize = sizeof(struct cfe_iocb_envbuf); - iocb.envbuf.name = PTR_TO_CFE(name); - iocb.envbuf.name_len = strlen(name); - iocb.envbuf.val = PTR_TO_CFE(dest); - iocb.envbuf.val_len = destlen; - - err = cfe_iocb_dispatch(&iocb); - - return (CFE_ISERR(err)) ? err : iocb.status; -} - -int cfe_getfwinfo(struct cfe_fwinfo *info) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_FW_GETINFO; - iocb.psize = sizeof(struct cfe_iocb_fwinfo); - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (CFE_ISERR(iocb.status)) - return err; - - info->version = iocb.fwinfo.version; - info->totalmem = iocb.fwinfo.totalmem; - info->flags = iocb.fwinfo.flags; - info->boardid = iocb.fwinfo.boardid; - info->bootarea_va = iocb.fwinfo.bootarea_va; - info->bootarea_pa = iocb.fwinfo.bootarea_pa; - info->bootarea_size = iocb.fwinfo.bootarea_size; - - return iocb.status; -} - -int cfe_getstdhandle(int handletype) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_DEV_GETHANDLE; - iocb.flags = handletype; - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (CFE_ISERR(iocb.status)) - return iocb.status; - - return iocb.handle; -} - -int cfe_getticks(s64 *ticks) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_FW_GETTIME; - iocb.psize = sizeof(struct cfe_iocb_time); - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (!CFE_ISERR(iocb.status)) - *ticks = iocb.time.ticks; - - return iocb.status; -} - -int cfe_inpstat(int handle) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_DEV_INPSTAT; - iocb.handle = handle; - iocb.psize = sizeof(struct cfe_iocb_inpstat); - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (CFE_ISERR(iocb.status)) - return iocb.status; - - return iocb.inpstat.status; -} - -int cfe_ioctl(int handle, unsigned int ioctlnum, - unsigned char *buffer, int length, - int *retlen, u64 offset) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_DEV_IOCTL; - iocb.handle = handle; - iocb.psize = sizeof(struct cfe_iocb_buf); - iocb.buffer.offset = offset; - iocb.buffer.ioctlcmd = ioctlnum; - iocb.buffer.ptr = PTR_TO_CFE(buffer); - iocb.buffer.length = length; - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (CFE_ISERR(iocb.status)) - return iocb.status; - if (retlen) - *retlen = iocb.buffer.retlen; - - return iocb.status; -} - -int cfe_open(char *name) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_DEV_OPEN; - iocb.psize = sizeof(struct cfe_iocb_buf); - iocb.buffer.ptr = PTR_TO_CFE(name); - iocb.buffer.length = strlen(name); - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (CFE_ISERR(iocb.status)) - return iocb.status; - - return iocb.handle; -} - -int cfe_read(int handle, unsigned char *buffer, int length) -{ - return cfe_readblk(handle, 0, buffer, length); -} - -int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_DEV_READ; - iocb.handle = handle; - iocb.psize = sizeof(struct cfe_iocb_buf); - iocb.buffer.offset = offset; - iocb.buffer.ptr = PTR_TO_CFE(buffer); - iocb.buffer.length = length; - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (CFE_ISERR(iocb.status)) - return iocb.status; - - return iocb.buffer.retlen; -} - -int cfe_setenv(char *name, char *val) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_ENV_SET; - iocb.psize = sizeof(struct cfe_iocb_envbuf); - iocb.envbuf.name = PTR_TO_CFE(name); - iocb.envbuf.name_len = strlen(name); - iocb.envbuf.val = PTR_TO_CFE(val); - iocb.envbuf.val_len = strlen(val); - - err = cfe_iocb_dispatch(&iocb); - - return (CFE_ISERR(err)) ? err : iocb.status; -} - -int cfe_write(int handle, unsigned char *buffer, int length) -{ - return cfe_writeblk(handle, 0, buffer, length); -} - -int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length) -{ - struct cfe_iocb iocb; - int err; - - memset(&iocb, 0, sizeof(iocb)); - iocb.fcode = CFE_CMD_DEV_WRITE; - iocb.handle = handle; - iocb.psize = sizeof(struct cfe_iocb_buf); - iocb.buffer.offset = offset; - iocb.buffer.ptr = PTR_TO_CFE(buffer); - iocb.buffer.length = length; - - err = cfe_iocb_dispatch(&iocb); - if (CFE_ISERR(err)) - return err; - if (CFE_ISERR(iocb.status)) - return iocb.status; - - return iocb.buffer.retlen; -} diff --git a/target/linux/brcm63xx/files/arch/mips/cfe/cfe_private.h b/target/linux/brcm63xx/files/arch/mips/cfe/cfe_private.h deleted file mode 100644 index 0a604d3bbd..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/cfe/cfe_private.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Broadcom Common Firmware Environment (CFE) support - * - * Copyright 2000, 2001, 2002 - * Broadcom Corporation. All rights reserved. - * - * Copyright (C) 2006 Michael Buesch - * - * Original Authors: Mitch Lichtenberg, Chris Demetriou - * - * This software is furnished under license and may be used and copied only - * in accordance with the following terms and conditions. Subject to these - * conditions, you may download, copy, install, use, modify and distribute - * modified or unmodified copies of this software in source and/or binary - * form. No title or ownership is transferred hereby. - * - * 1) Any source code used, modified or distributed must reproduce and - * retain this copyright notice and list of conditions as they appear in - * the source file. - * - * 2) No right is granted to use any trade name, trademark, or logo of - * Broadcom Corporation. The "Broadcom Corporation" name may not be - * used to endorse or promote products derived from this software - * without the prior written permission of Broadcom Corporation. - * - * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE - * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE - * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef LINUX_CFE_PRIVATE_H_ -#define LINUX_CFE_PRIVATE_H_ - -#ifndef __ASSEMBLY__ - -/* Seal indicating CFE's presence, passed to the kernel. */ -#define CFE_EPTSEAL 0x43464531 - -#define CFE_CMD_FW_GETINFO 0 -#define CFE_CMD_FW_RESTART 1 -#define CFE_CMD_FW_BOOT 2 -#define CFE_CMD_FW_CPUCTL 3 -#define CFE_CMD_FW_GETTIME 4 -#define CFE_CMD_FW_MEMENUM 5 -#define CFE_CMD_FW_FLUSHCACHE 6 - -#define CFE_CMD_DEV_GETHANDLE 9 -#define CFE_CMD_DEV_ENUM 10 -#define CFE_CMD_DEV_OPEN 11 -#define CFE_CMD_DEV_INPSTAT 12 -#define CFE_CMD_DEV_READ 13 -#define CFE_CMD_DEV_WRITE 14 -#define CFE_CMD_DEV_IOCTL 15 -#define CFE_CMD_DEV_CLOSE 16 -#define CFE_CMD_DEV_GETINFO 17 - -#define CFE_CMD_ENV_ENUM 20 -#define CFE_CMD_ENV_GET 22 -#define CFE_CMD_ENV_SET 23 -#define CFE_CMD_ENV_DEL 24 - -#define CFE_CMD_MAX 32 - -#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */ - -typedef u64 cfe_uint_t; -typedef s64 cfe_int_t; -typedef s64 cfe_ptr_t; - -/* Cast a pointer from native to CFE-API pointer and back */ -#define CFE_TO_PTR(p) ((void *)(unsigned long)(p)) -#define PTR_TO_CFE(p) ((cfe_ptr_t)(unsigned long)(p)) - -struct cfe_iocb_buf { - cfe_uint_t offset; /* offset on device (bytes) */ - cfe_ptr_t ptr; /* pointer to a buffer */ - cfe_uint_t length; /* length of this buffer */ - cfe_uint_t retlen; /* returned length (for read ops) */ - union { - cfe_uint_t ioctlcmd; /* IOCTL command (used only for IOCTLs) */ - cfe_uint_t devflags; /* Returned device info flags */ - }; -}; - -struct cfe_iocb_inpstat { - cfe_uint_t status; /* 1 means input available */ -}; - -struct cfe_iocb_envbuf { - cfe_int_t index; /* 0-based enumeration index */ - cfe_ptr_t name; /* name string buffer */ - cfe_int_t name_len; /* size of name buffer */ - cfe_ptr_t val; /* value string buffer */ - cfe_int_t val_len; /* size of value string buffer */ -}; - -struct cfe_iocb_cpuctl { - cfe_uint_t number; /* cpu number to control */ - cfe_uint_t command; /* command to issue to CPU */ - cfe_uint_t start_addr; /* CPU start address */ - cfe_uint_t gp; /* starting GP value */ - cfe_uint_t sp; /* starting SP value */ - cfe_uint_t a1; /* starting A1 value */ -}; - -struct cfe_iocb_time { - cfe_int_t ticks; /* current time in ticks */ -}; - -struct cfe_iocb_exitstat { - cfe_int_t status; -}; - -struct cfe_iocb_meminfo { - cfe_int_t index; /* 0-based enumeration index */ - cfe_int_t type; /* type of memory block */ - cfe_uint_t addr; /* physical start address */ - cfe_uint_t size; /* block size */ -}; - -struct cfe_iocb_fwinfo { - cfe_int_t version; /* major, minor, eco version */ - cfe_int_t totalmem; /* total installed mem */ - cfe_int_t flags; /* various flags */ - cfe_int_t boardid; /* board ID */ - cfe_int_t bootarea_va; /* VA of boot area */ - cfe_int_t bootarea_pa; /* PA of boot area */ - cfe_int_t bootarea_size; /* size of boot area */ - cfe_int_t reserved1; - cfe_int_t reserved2; - cfe_int_t reserved3; -}; - -/* CFE I/O Control Block */ -struct cfe_iocb { - cfe_uint_t fcode; /* IOCB function code */ - cfe_int_t status; /* return status */ - cfe_int_t handle; /* file/device handle */ - cfe_uint_t flags; /* flags for this IOCB */ - cfe_uint_t psize; /* size of parameter list */ - union { - struct cfe_iocb_buf buffer; /* buffer parameters */ - struct cfe_iocb_inpstat inpstat; /* input status parameters */ - struct cfe_iocb_envbuf envbuf; /* environment function parameters */ - struct cfe_iocb_cpuctl cpuctl; /* CPU control parameters */ - struct cfe_iocb_time time; /* timer parameters */ - struct cfe_iocb_meminfo meminfo; /* memory arena info parameters */ - struct cfe_iocb_fwinfo fwinfo; /* firmware information */ - struct cfe_iocb_exitstat exitstat; /* Exit Status */ - }; -}; - - -#include - -void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1, - unsigned long fwarg2, unsigned long fwarg3); - -#else /* __ASSEMBLY__ */ - - .macro cfe_early_init -#ifdef CONFIG_CFE - jal cfe_setup -#endif - .endm - -#endif /* __ASSEMBLY__ */ -#endif /* LINUX_CFE_PRIVATE_H_ */ diff --git a/target/linux/brcm63xx/files/arch/mips/pci/fixup-bcm96348.c b/target/linux/brcm63xx/files/arch/mips/pci/fixup-bcm96348.c deleted file mode 100644 index e3703a94c2..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/pci/fixup-bcm96348.c +++ /dev/null @@ -1,95 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -#include -#include -#include - -#include -#include -#include -#include <6348_intr.h> -#include <6348_map_part.h> - -static volatile MpiRegisters * mpi = (MpiRegisters *)(MPI_BASE); - -static char irq_tab_bcm96348[] __initdata = { - [0] = INTERRUPT_ID_MPI, - [1] = INTERRUPT_ID_MPI, -#if defined(CONFIG_USB) - [USB_HOST_SLOT] = INTERRUPT_ID_USBH -#endif -}; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_tab_bcm96348[slot]; -} - -static void bcm96348_fixup(struct pci_dev *dev) -{ - uint32 memaddr; - uint32 size; - - memaddr = pci_resource_start(dev, 0); - size = pci_resource_len(dev, 0); - - switch (PCI_SLOT(dev->devfn)) { - case 0: - // UBUS to PCI address range - // Memory Window 1. Mask determines which bits are decoded. - mpi->l2pmrange1 = ~(size-1); - // UBUS to PCI Memory base address. This is akin to the ChipSelect base - // register. - mpi->l2pmbase1 = memaddr & BCM_PCI_ADDR_MASK; - // UBUS to PCI Remap Address. Replaces the masked address bits in the - // range register with this setting. - // Also, enable direct I/O and direct Memory accesses - mpi->l2pmremap1 = (memaddr | MEM_WINDOW_EN); - break; - - case 1: - // Memory Window 2 - mpi->l2pmrange2 = ~(size-1); - // UBUS to PCI Memory base address. - mpi->l2pmbase2 = memaddr & BCM_PCI_ADDR_MASK; - // UBUS to PCI Remap Address - mpi->l2pmremap2 = (memaddr | MEM_WINDOW_EN); - break; - -#if defined(CONFIG_USB) - case USB_HOST_SLOT: - dev->resource[0].start = USB_HOST_BASE; - dev->resource[0].end = USB_HOST_BASE+USB_BAR0_MEM_SIZE-1; - break; -#endif - } -} - -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_ANY_ID, - bcm96348_fixup); - -/*struct pci_fixup pcibios_fixups[] = { - { PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID, bcm96348_fixup }, - {0} -};*/ diff --git a/target/linux/brcm63xx/files/arch/mips/pci/ops-bcm96348.c b/target/linux/brcm63xx/files/arch/mips/pci/ops-bcm96348.c deleted file mode 100644 index ee1647121e..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/pci/ops-bcm96348.c +++ /dev/null @@ -1,278 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -#include -#include -#include -#include -#include - -#include -#include -#include <6348_intr.h> -#include <6348_map_part.h> -#include - -#include - -#if defined(CONFIG_USB) -#if 0 -#define DPRINT(x...) printk(x) -#else -#define DPRINT(x...) -#endif - -static int -pci63xx_int_read(unsigned int devfn, int where, u32 * value, int size); -static int -pci63xx_int_write(unsigned int devfn, int where, u32 * value, int size); - -static bool usb_mem_size_rd = FALSE; -static uint32 usb_mem_base = 0; -static uint32 usb_cfg_space_cmd_reg = 0; -#endif -static bool pci_mem_size_rd = FALSE; - -static volatile MpiRegisters * mpi = (MpiRegisters *)(MPI_BASE); - -static void mpi_SetupPciConfigAccess(uint32 addr) -{ - mpi->l2pcfgctl = (DIR_CFG_SEL | DIR_CFG_USEREG | addr) & ~CONFIG_TYPE; -} - -static void mpi_ClearPciConfigAccess(void) -{ - mpi->l2pcfgctl = 0x00000000; -} - -#if defined(CONFIG_USB) -/* -------------------------------------------------------------------------- - Name: pci63xx_int_write -Abstract: PCI Config write on internal device(s) - -------------------------------------------------------------------------- */ -static int -pci63xx_int_write(unsigned int devfn, int where, u32 * value, int size) -{ - if (PCI_SLOT(devfn) != USB_HOST_SLOT) { - return PCIBIOS_SUCCESSFUL; - } - - switch (size) { - case 1: - DPRINT("W => Slot: %d Where: %2X Len: %d Data: %02X\n", - PCI_SLOT(devfn), where, size, *value); - break; - case 2: - DPRINT("W => Slot: %d Where: %2X Len: %d Data: %04X\n", - PCI_SLOT(devfn), where, size, *value); - switch (where) { - case PCI_COMMAND: - usb_cfg_space_cmd_reg = *value; - break; - default: - break; - } - break; - case 4: - DPRINT("W => Slot: %d Where: %2X Len: %d Data: %08lX\n", - PCI_SLOT(devfn), where, size, *value); - switch (where) { - case PCI_BASE_ADDRESS_0: - if (*value == 0xffffffff) { - usb_mem_size_rd = TRUE; - } else { - usb_mem_base = *value; - } - break; - default: - break; - } - break; - default: - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -/* -------------------------------------------------------------------------- - Name: pci63xx_int_read -Abstract: PCI Config read on internal device(s) - -------------------------------------------------------------------------- */ -static int -pci63xx_int_read(unsigned int devfn, int where, u32 * value, int size) -{ - uint32 retValue = 0xFFFFFFFF; - - if (PCI_SLOT(devfn) != USB_HOST_SLOT) { - return PCIBIOS_SUCCESSFUL; - } - - // For now, this is specific to the USB Host controller. We can - // make it more general if we have to... - // Emulate PCI Config accesses - switch (where) { - case PCI_VENDOR_ID: - case PCI_DEVICE_ID: - retValue = PCI_VENDOR_ID_BROADCOM | 0x63000000; - break; - case PCI_COMMAND: - case PCI_STATUS: - retValue = (0x0006 << 16) | usb_cfg_space_cmd_reg; - break; - case PCI_CLASS_REVISION: - case PCI_CLASS_DEVICE: - retValue = (PCI_CLASS_SERIAL_USB << 16) | (0x10 << 8) | 0x01; - break; - case PCI_BASE_ADDRESS_0: - if (usb_mem_size_rd) { - retValue = USB_BAR0_MEM_SIZE; - } else { - if (usb_mem_base != 0) - retValue = usb_mem_base; - else - retValue = USB_HOST_BASE; - } - usb_mem_size_rd = FALSE; - break; - case PCI_CACHE_LINE_SIZE: - case PCI_LATENCY_TIMER: - retValue = 0; - break; - case PCI_HEADER_TYPE: - retValue = PCI_HEADER_TYPE_NORMAL; - break; - case PCI_SUBSYSTEM_VENDOR_ID: - retValue = PCI_VENDOR_ID_BROADCOM; - break; - case PCI_SUBSYSTEM_ID: - retValue = 0x6300; - break; - case PCI_INTERRUPT_LINE: - retValue = INTERRUPT_ID_USBH; - break; - default: - break; - } - - switch (size) { - case 1: - *value = (retValue >> ((where & 3) << 3)) & 0xff; - DPRINT("R <= Slot: %d Where: %2X Len: %d Data: %02X\n", - PCI_SLOT(devfn), where, size, *value); - break; - case 2: - *value = (retValue >> ((where & 3) << 3)) & 0xffff; - DPRINT("R <= Slot: %d Where: %2X Len: %d Data: %04X\n", - PCI_SLOT(devfn), where, size, *value); - break; - case 4: - *value = retValue; - DPRINT("R <= Slot: %d Where: %2X Len: %d Data: %08lX\n", - PCI_SLOT(devfn), where, size, *value); - break; - default: - break; - } - - return PCIBIOS_SUCCESSFUL; -} -#endif - -static int bcm96348_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - volatile unsigned char *ioBase = (unsigned char *)(mpi->l2piobase | KSEG1); - uint32 data; - -#if defined(CONFIG_USB) - if (PCI_SLOT(devfn) == USB_HOST_SLOT) - return pci63xx_int_read(devfn, where, val, size); -#endif - - mpi_SetupPciConfigAccess(BCM_PCI_CFG(PCI_SLOT(devfn), PCI_FUNC(devfn), where)); - data = *(uint32 *)ioBase; - switch(size) { - case 1: - *val = (data >> ((where & 3) << 3)) & 0xff; - break; - case 2: - *val = (data >> ((where & 3) << 3)) & 0xffff; - break; - case 4: - *val = data; - /* Special case for reading PCI device range */ - if ((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_5)) { - if (pci_mem_size_rd) { - /* bcm6348 PCI memory window minimum size is 64K */ - *val &= PCI_SIZE_64K; - } - } - break; - default: - break; - } - pci_mem_size_rd = FALSE; - mpi_ClearPciConfigAccess(); - - return PCIBIOS_SUCCESSFUL; -} - -static int bcm96348_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - volatile unsigned char *ioBase = (unsigned char *)(mpi->l2piobase | KSEG1); - uint32 data; - -#if defined(CONFIG_USB) - if (PCI_SLOT(devfn) == USB_HOST_SLOT) - return pci63xx_int_write(devfn, where, &val, size); -#endif - mpi_SetupPciConfigAccess(BCM_PCI_CFG(PCI_SLOT(devfn), PCI_FUNC(devfn), where)); - data = *(uint32 *)ioBase; - switch(size) { - case 1: - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - break; - case 2: - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - break; - case 4: - data = val; - /* Special case for reading PCI device range */ - if ((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_5)) { - if (val == 0xffffffff) - pci_mem_size_rd = TRUE; - } - break; - default: - break; - } - *(uint32 *)ioBase = data; - udelay(500); - mpi_ClearPciConfigAccess(); - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops bcm96348_pci_ops = { - .read = bcm96348_pcibios_read, - .write = bcm96348_pcibios_write -}; diff --git a/target/linux/brcm63xx/files/arch/mips/pci/pci-bcm96348.c b/target/linux/brcm63xx/files/arch/mips/pci/pci-bcm96348.c deleted file mode 100644 index bea3b7ba08..0000000000 --- a/target/linux/brcm63xx/files/arch/mips/pci/pci-bcm96348.c +++ /dev/null @@ -1,62 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -#include -#include -#include -#include - -#include - -static struct resource bcm_pci_io_resource = { - .name = "bcm96348 pci IO space", - .start = BCM_PCI_IO_BASE, - .end = BCM_PCI_IO_BASE + BCM_PCI_IO_SIZE_64KB - 1, - .flags = IORESOURCE_IO -}; - -static struct resource bcm_pci_mem_resource = { - .name = "bcm96348 pci memory space", - .start = BCM_PCI_MEM_BASE, - .end = BCM_PCI_MEM_BASE + BCM_PCI_MEM_SIZE_16MB - 1, - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops bcm96348_pci_ops; - -struct pci_controller bcm96348_controller = { - .pci_ops = &bcm96348_pci_ops, - .io_resource = &bcm_pci_io_resource, - .mem_resource = &bcm_pci_mem_resource, -}; - -static __init int bcm96348_pci_init(void) -{ - /* Avoid ISA compat ranges. */ - PCIBIOS_MIN_IO = 0x00000000; - PCIBIOS_MIN_MEM = 0x00000000; - - /* Set I/O resource limits. */ - ioport_resource.end = 0x1fffffff; - iomem_resource.end = 0xffffffff; - - register_pci_controller(&bcm96348_controller); - return 0; -} - -arch_initcall(bcm96348_pci_init); diff --git a/target/linux/brcm63xx/files/drivers/mtd/maps/bcm963xx-flash.c b/target/linux/brcm63xx/files/drivers/mtd/maps/bcm963xx-flash.c deleted file mode 100644 index c4c4526b49..0000000000 --- a/target/linux/brcm63xx/files/drivers/mtd/maps/bcm963xx-flash.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * $Id$ - * Copyright (C) 2006 Florian Fainelli - * Mike Albon - * Copyright (C) $Date$ $Author$ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is the BCM963xx flash map driver, in its actual state it only supports BCM96348 devices - * this driver is able to manage both bootloader we found on these boards : CFE and RedBoot - * - * RedBoot : - * - this bootloader allows us to parse partitions and therefore deduce the MTD partition table - * - * CFE : - * - CFE partitionning can be detected as for BCM947xx devices - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define WINDOW_ADDR 0x1FC00000 /* Real address of the flash */ -#define WINDOW_SIZE 0x400000 /* Size of flash */ -#define BUSWIDTH 2 /* Buswidth */ -#define EXTENDED_SIZE 0xBFC00000 /* Extended flash address */ -#define IMAGE_LEN 10 /* Length of Length Field */ -#define ADDRESS_LEN 12 /* Length of Address field */ -#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y)) - -extern int boot_loader_type; /* For RedBoot / CFE detection */ -extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts, unsigned long fis_origin); -static struct mtd_partition *parsed_parts; - -static void __exit bcm963xx_mtd_cleanup(void); - -static struct mtd_info *bcm963xx_mtd_info; - -static struct map_info bcm963xx_map = { - .name = "bcm963xx", - .size = WINDOW_SIZE, - .bankwidth = BUSWIDTH, - .phys = WINDOW_ADDR, -}; - - -int parse_cfe_partitions( struct mtd_info *master, struct mtd_partition **pparts) -{ - int nrparts = 2, curpart = 0; // CFE and NVRAM always present. - struct bcm963xx_cfe_map { - unsigned char tagVersion[4]; // Version of the image tag - unsigned char sig_1[20]; // Company Line 1 - unsigned char sig_2[14]; // Company Line 2 - unsigned char chipid[6]; // Chip this image is for - unsigned char boardid[16]; // Board name - unsigned char bigEndian[2]; // Map endianness -- 1 BE 0 LE - unsigned char totalLength[IMAGE_LEN]; //Total length of image - unsigned char cfeAddress[ADDRESS_LEN]; // Address in memory of CFE - unsigned char cfeLength[IMAGE_LEN]; // Size of CFE - unsigned char rootAddress[ADDRESS_LEN]; // Address in memory of rootfs - unsigned char rootLength[IMAGE_LEN]; // Size of rootfs - unsigned char kernelAddress[ADDRESS_LEN]; // Address in memory of kernel - unsigned char kernelLength[IMAGE_LEN]; // Size of kernel - unsigned char dualImage[2]; // Unused at present - unsigned char inactiveFlag[2]; // Unused at present - unsigned char reserved1[74]; // Reserved area not in use - unsigned char imageCRC[4]; // CRC32 of images - unsigned char reserved2[16]; // Unused at present - unsigned char headerCRC[4]; // CRC32 of header excluding tagVersion - unsigned char reserved3[16]; // Unused at present - } *buf; - struct mtd_partition *parts; - int ret; - size_t retlen; - unsigned int rootfsaddr, kerneladdr, spareaddr; - unsigned int rootfslen, kernellen, sparelen, totallen; - int namelen = 0; - int i; - // Allocate memory for buffer - buf = vmalloc(sizeof(struct bcm963xx_cfe_map)); - - if (!buf) - return -ENOMEM; - - // Get the tag - ret = master->read(master,master->erasesize,sizeof(struct bcm963xx_cfe_map), &retlen, (void *)buf); - if (retlen != sizeof(struct bcm963xx_cfe_map)){ - vfree(buf); - return -EIO; - }; - printk("bcm963xx: CFE boot tag found with version %s and board type %s.\n",buf->tagVersion,buf->boardid); - // Get the values and calculate - sscanf(buf->rootAddress,"%u", &rootfsaddr); - rootfsaddr = rootfsaddr - EXTENDED_SIZE; - sscanf(buf->rootLength, "%u", &rootfslen); - sscanf(buf->kernelAddress, "%u", &kerneladdr); - kerneladdr = kerneladdr - EXTENDED_SIZE; - sscanf(buf->kernelLength, "%u", &kernellen); - sscanf(buf->totalLength, "%u", &totallen); - spareaddr = ROUNDUP(totallen,master->erasesize) + master->erasesize; - sparelen = master->size - spareaddr - master->erasesize; - // Determine number of partitions - namelen = 8; - if (rootfslen > 0){ - nrparts++; - namelen =+ 6; - }; - if (kernellen > 0){ - nrparts++; - namelen =+ 6; - }; - if (sparelen > 0){ - nrparts++; - namelen =+ 6; - }; - // Ask kernel for more memory. - parts = kmalloc(sizeof(*parts)*nrparts+10*nrparts, GFP_KERNEL); - if (!parts){ - vfree(buf); - return -ENOMEM; - }; - memset(parts,0,sizeof(*parts)*nrparts+10*nrparts); - // Start building partition list - parts[curpart].name = "CFE"; - parts[curpart].offset = 0; - parts[curpart].size = master->erasesize; - curpart++; - if (kernellen > 0){ - parts[curpart].name = "Kernel"; - parts[curpart].offset = kerneladdr; - parts[curpart].size = kernellen; - curpart++; - }; - if (rootfslen > 0){ - parts[curpart].name = "Rootfs"; - parts[curpart].offset = rootfsaddr; - parts[curpart].size = rootfslen; - curpart++; - }; - if (sparelen > 0){ - parts[curpart].name = "OpenWrt"; - parts[curpart].offset = spareaddr; - parts[curpart].size = sparelen; - curpart++; - }; - parts[curpart].name = "NVRAM"; - parts[curpart].offset = master->size - master->erasesize; - parts[curpart].size = master->erasesize; - for (i = 0; i < nrparts; i++) { - printk("bcm963xx: Partition %d is %s offset %x and length %x\n", i, parts[i].name, parts[i].offset, parts[i].size); - } - *pparts = parts; - vfree(buf); - return nrparts; -}; - -static struct mtd_partition bcm963xx_parts[] = { - { name: "bootloader", size: 0, offset: 0, mask_flags: MTD_WRITEABLE }, - { name: "rootfs", size: 0, offset: 0}, - { name: "jffs2", size: 5 * 0x10000, offset: 57*0x10000} -}; - -static int bcm963xx_parts_size = sizeof(bcm963xx_parts) / sizeof(bcm963xx_parts[0]); - -static int bcm963xx_detect_cfe(struct mtd_info *master) -{ - int idoffset = 0x4e0; - static char idstring[8] = "CFE1CFE1"; - char buf[8]; - int ret; - size_t retlen; - - ret = master->read(master, idoffset, 8, &retlen, (void *)buf); - printk("bcm963xx: Read Signature value of %s\n", buf); - return strcmp(idstring,buf); -} - -static int __init bcm963xx_mtd_init(void) -{ - printk("bcm963xx: 0x%08x at 0x%08x\n", WINDOW_SIZE, WINDOW_ADDR); - bcm963xx_map.virt = ioremap(WINDOW_ADDR, WINDOW_SIZE); - - if (!bcm963xx_map.virt) { - printk("bcm963xx: Failed to ioremap\n"); - return -EIO; - } - - simple_map_init(&bcm963xx_map); - - bcm963xx_mtd_info = do_map_probe("cfi_probe", &bcm963xx_map); - - if (bcm963xx_mtd_info) { - bcm963xx_mtd_info->owner = THIS_MODULE; - - //if (boot_loader_type == BOOT_CFE) - if (bcm963xx_detect_cfe(bcm963xx_mtd_info) == 0) - { - int parsed_nr_parts = 0; - char * part_type; - printk("bcm963xx: CFE bootloader detected\n"); - //add_mtd_device(bcm963xx_mtd_info); - //add_mtd_partitions(bcm963xx_mtd_info, bcm963xx_parts, bcm963xx_parts_size); - if (parsed_nr_parts == 0) { - int ret = parse_cfe_partitions(bcm963xx_mtd_info, &parsed_parts); - if (ret > 0) { - part_type = "CFE"; - parsed_nr_parts = ret; - } - } - add_mtd_partitions(bcm963xx_mtd_info, parsed_parts, parsed_nr_parts); - return 0; - } - else - { - int parsed_nr_parts = 0; - char * part_type; - - if (bcm963xx_mtd_info->size > 0x00400000) { - printk("Support for extended flash memory size : 0x%08X ; ONLY 64MBIT SUPPORT\n", bcm963xx_mtd_info->size); - bcm963xx_map.virt = (unsigned long)(EXTENDED_SIZE); - } - -#ifdef CONFIG_MTD_REDBOOT_PARTS - if (parsed_nr_parts == 0) { - int ret = parse_redboot_partitions(bcm963xx_mtd_info, &parsed_parts, 0); - if (ret > 0) { - part_type = "RedBoot"; - parsed_nr_parts = ret; - } - } -#endif - add_mtd_partitions(bcm963xx_mtd_info, parsed_parts, parsed_nr_parts); - - return 0; - } - } - iounmap(bcm963xx_map.virt); - return -ENXIO; -} - -static void __exit bcm963xx_mtd_cleanup(void) -{ - if (bcm963xx_mtd_info) { - del_mtd_partitions(bcm963xx_mtd_info); - map_destroy(bcm963xx_mtd_info); - } - - if (bcm963xx_map.virt) { - iounmap(bcm963xx_map.virt); - bcm963xx_map.virt = 0; - } -} - -module_init(bcm963xx_mtd_init); -module_exit(bcm963xx_mtd_cleanup); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Florian Fainelli Mike Albon "); diff --git a/target/linux/brcm63xx/files/drivers/serial/bcm63xx_cons.c b/target/linux/brcm63xx/files/drivers/serial/bcm63xx_cons.c deleted file mode 100644 index 8fff16dd9c..0000000000 --- a/target/linux/brcm63xx/files/drivers/serial/bcm63xx_cons.c +++ /dev/null @@ -1,1041 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -/* Description: Serial port driver for the BCM963XX. */ - -#define CARDNAME "bcm963xx_serial driver" -#define VERSION "2.0" -#define VER_STR CARDNAME " v" VERSION "\n" - - -#include -#include -#include -#include -#include -#include -#include - -/* for definition of struct console */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include <6348_map_part.h> -#include <6348_intr.h> - -static DEFINE_SPINLOCK(bcm963xx_serial_lock); - -extern void _putc(char); -extern void _puts(const char *); - -typedef struct bcm_serial { - volatile Uart *port; - int type; - int flags; - int irq; - int baud_base; - int blocked_open; - unsigned short close_delay; - unsigned short closing_wait; - unsigned short line; /* port/line number */ - unsigned short cflags; /* line configuration flag */ - unsigned short x_char; /* xon/xoff character */ - unsigned short read_status_mask; /* mask for read condition */ - unsigned short ignore_status_mask; /* mask for ignore condition */ - unsigned long event; /* mask used in BH */ - int xmit_head; /* Position of the head */ - int xmit_tail; /* Position of the tail */ - int xmit_cnt; /* Count of the chars in the buffer */ - int count; /* indicates how many times it has been opened */ - int magic; - - struct async_icount icount; /* keep track of things ... */ - struct tty_struct *tty; /* tty associated */ - struct ktermios normal_termios; - - wait_queue_head_t open_wait; - wait_queue_head_t close_wait; - - long session; /* Session of opening process */ - long pgrp; /* pgrp of opening process */ - - unsigned char is_initialized; -} Context; - - -/*---------------------------------------------------------------------*/ -/* Define bits in the Interrupt Enable register */ -/*---------------------------------------------------------------------*/ -/* Enable receive interrupt */ -#define RXINT (RXFIFONE|RXOVFERR) - -/* Enable transmit interrupt */ -#define TXINT (TXFIFOEMT|TXUNDERR|TXOVFERR) - -/* Enable receiver line status interrupt */ -#define LSINT (RXBRK|RXPARERR|RXFRAMERR) - -#define BCM_NUM_UARTS 1 - -#define BD_BCM63XX_TIMER_CLOCK_INPUT (FPERIPH) - - -static struct bcm_serial multi[BCM_NUM_UARTS]; -static struct bcm_serial *lines[BCM_NUM_UARTS]; -static struct tty_driver *serial_driver; -static struct ktermios *serial_termios[BCM_NUM_UARTS]; -static struct ktermios *serial_termios_locked[BCM_NUM_UARTS]; - - -static void bcm_stop(struct tty_struct *tty); -static void bcm_start(struct tty_struct *tty); -static inline void receive_chars(struct bcm_serial *info); -static int startup(struct bcm_serial *info); -static void shutdown(struct bcm_serial *info); -static void change_speed(volatile Uart * pUart, tcflag_t cFlag); -static void bcm63xx_cons_flush_chars(struct tty_struct *tty); -static int bcm63xx_cons_write(struct tty_struct *tty, - const unsigned char *buf, int count); -static int bcm63xx_cons_write_room(struct tty_struct *tty); -static int bcm_chars_in_buffer(struct tty_struct *tty); -static void bcm_flush_buffer(struct tty_struct *tty); -static void bcm_throttle(struct tty_struct *tty); -static void bcm_unthrottle(struct tty_struct *tty); -static void bcm_send_xchar(struct tty_struct *tty, char ch); -static int get_serial_info(struct bcm_serial *info, - struct serial_struct *retinfo); -static int set_serial_info(struct bcm_serial *info, - struct serial_struct *new_info); -static int get_lsr_info(struct bcm_serial *info, unsigned int *value); -static void send_break(struct bcm_serial *info, int duration); -static int bcm_ioctl(struct tty_struct *tty, struct file *file, - unsigned int cmd, unsigned long arg); -static void bcm_set_termios(struct tty_struct *tty, - struct ktermios *old_termios); -static void bcm63xx_cons_close(struct tty_struct *tty, struct file *filp); -static void bcm_hangup(struct tty_struct *tty); -static int block_til_ready(struct tty_struct *tty, struct file *filp, - struct bcm_serial *info); -static int bcm63xx_cons_open(struct tty_struct *tty, struct file *filp); -static int __init bcm63xx_serialinit(void); - - -/* - * ------------------------------------------------------------ - * rs_stop () and rs_start () - * - * These routines are called before setting or resetting - * tty->stopped. They enable or disable transmitter interrupts, - * as necessary. - * ------------------------------------------------------------ - */ -static void bcm_stop(struct tty_struct *tty) -{ -} - -static void bcm_start(struct tty_struct *tty) -{ - _puts(CARDNAME " Start\n"); -} - -/* - * ------------------------------------------------------------ - * receive_char () - * - * This routine deals with inputs from any lines. - * ------------------------------------------------------------ - */ -static inline void receive_chars(struct bcm_serial *info) -{ - struct tty_struct *tty = 0; - struct async_icount *icount; - int ignore = 0; - unsigned short status, tmp; - UCHAR ch = 0; - while ((status = info->port->intStatus) & RXINT) { - char flag_char = TTY_NORMAL; - - if (status & RXFIFONE) - ch = info->port->Data; // Read the character - tty = info->tty; /* now tty points to the proper dev */ - icount = &info->icount; - if (!tty) - break; - if (!tty_buffer_request_room(tty, 1)) - break; - icount->rx++; - if (status & RXBRK) { - flag_char = TTY_BREAK; - icount->brk++; - } - // keep track of the statistics - if (status & (RXFRAMERR | RXPARERR | RXOVFERR)) { - if (status & RXPARERR) /* parity error */ - icount->parity++; - else if (status & RXFRAMERR) /* frame error */ - icount->frame++; - if (status & RXOVFERR) { - // Overflow. Reset the RX FIFO - info->port->fifoctl |= RSTRXFIFOS; - icount->overrun++; - } - // check to see if we should ignore the character - // and mask off conditions that should be ignored - if (status & info->ignore_status_mask) { - if (++ignore > 100) - break; - goto ignore_char; - } - // Mask off the error conditions we want to ignore - tmp = status & info->read_status_mask; - if (tmp & RXPARERR) { - flag_char = TTY_PARITY; - } else if (tmp & RXFRAMERR) { - flag_char = TTY_FRAME; - } - if (tmp & RXOVFERR) { - tty_insert_flip_char(tty, ch, flag_char); - ch = 0; - flag_char = TTY_OVERRUN; - if (!tty_buffer_request_room(tty, 1)) - break; - } - } - tty_insert_flip_char(tty, ch, flag_char); - } - ignore_char:; - tty_flip_buffer_push(tty); - tty_schedule_flip(tty); - -} - - -/* - * ------------------------------------------------------------ - * bcm_interrupt () - * - * this is the main interrupt routine for the chip. - * It deals with the multiple ports. - * ------------------------------------------------------------ - */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) -static irqreturn_t bcm_interrupt(int irq, void *dev) -#else -static void bcm_interrupt(int irq, void *dev, struct pt_regs *regs) -#endif -{ - struct bcm_serial *info = lines[0]; - UINT16 intStat; - - /* get pending interrupt flags from UART */ - - /* Mask with only the serial interrupts that are enabled */ - intStat = info->port->intStatus & info->port->intMask; - while (intStat) { - if (intStat & RXINT) - receive_chars(info); - else if (intStat & TXINT) - info->port->intStatus = TXINT; - else /* don't know what it was, so let's mask it */ - info->port->intMask &= ~intStat; - - intStat = info->port->intStatus & info->port->intMask; - } - - // Clear the interrupt - enable_brcm_irq(INTERRUPT_ID_UART); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) - return IRQ_HANDLED; -#endif -} - -/* - * ------------------------------------------------------------------- - * startup () - * - * various initialization tasks - * ------------------------------------------------------------------- - */ -static int startup(struct bcm_serial *info) -{ - // Port is already started... - return 0; -} - -/* - * ------------------------------------------------------------------- - * shutdown () - * - * This routine will shutdown a serial port; interrupts are disabled, and - * DTR is dropped if the hangup on close termio flag is on. - * ------------------------------------------------------------------- - */ -static void shutdown(struct bcm_serial *info) -{ - unsigned long flags; - if (!info->is_initialized) - return; - - spin_lock_irqsave(&bcm963xx_serial_lock, flags); - - info->port->control &= ~(BRGEN | TXEN | RXEN); - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - info->is_initialized = 0; - - spin_unlock_irqrestore(&bcm963xx_serial_lock, flags); -} - -/* - * ------------------------------------------------------------------- - * change_speed () - * - * Set the baud rate, character size, parity and stop bits. - * ------------------------------------------------------------------- - */ -static void change_speed(volatile Uart * pUart, tcflag_t cFlag) -{ - unsigned long ulFlags, ulBaud, ulClockFreqHz, ulTmp; - - spin_lock_irqsave(&bcm963xx_serial_lock, ulFlags); - switch (cFlag & (CBAUD | CBAUDEX)) { - case B115200: - ulBaud = 115200; - break; - case B57600: - ulBaud = 57600; - break; - case B38400: - ulBaud = 38400; - break; - case B19200: - ulBaud = 19200; - break; - case B9600: - ulBaud = 9600; - break; - case B4800: - ulBaud = 4800; - break; - case B2400: - ulBaud = 2400; - break; - case B1800: - ulBaud = 1800; - break; - case B1200: - ulBaud = 1200; - break; - case B600: - ulBaud = 600; - break; - case B300: - ulBaud = 300; - break; - case B200: - ulBaud = 200; - break; - case B150: - ulBaud = 150; - break; - case B134: - ulBaud = 134; - break; - case B110: - ulBaud = 110; - break; - case B75: - ulBaud = 75; - break; - case B50: - ulBaud = 50; - break; - default: - ulBaud = 115200; - break; - } - - /* Calculate buad rate. */ - ulClockFreqHz = BD_BCM63XX_TIMER_CLOCK_INPUT; - ulTmp = (ulClockFreqHz / ulBaud) / 16; - if (ulTmp & 0x01) - ulTmp /= 2; /* Rounding up, so sub is already accounted for */ - else - ulTmp = (ulTmp / 2) - 1; /* Rounding down so we must sub 1 */ - pUart->baudword = ulTmp; - - /* Set character size, stop bits and parity. */ - switch (cFlag & CSIZE) { - case CS5: - ulTmp = BITS5SYM; /* select transmit 5 bit data size */ - break; - case CS6: - ulTmp = BITS6SYM; /* select transmit 6 bit data size */ - break; - case CS7: - ulTmp = BITS7SYM; /* select transmit 7 bit data size */ - break; - default: - ulTmp = BITS8SYM; /* select transmit 8 bit data size */ - break; - } - if (cFlag & CSTOPB) - ulTmp |= TWOSTOP; /* select 2 stop bits */ - else - ulTmp |= ONESTOP; /* select one stop bit */ - - /* Write these values into the config reg. */ - pUart->config = ulTmp; - pUart->control &= - ~(RXPARITYEN | TXPARITYEN | RXPARITYEVEN | TXPARITYEVEN); - switch (cFlag & (PARENB | PARODD)) { - case PARENB | PARODD: - pUart->control |= RXPARITYEN | TXPARITYEN; - break; - case PARENB: - pUart->control |= - RXPARITYEN | TXPARITYEN | RXPARITYEVEN | TXPARITYEVEN; - break; - default: - pUart->control |= 0; - break; - } - - /* Reset and flush uart */ - pUart->fifoctl = RSTTXFIFOS | RSTRXFIFOS; - spin_unlock_irqrestore(&bcm963xx_serial_lock, ulFlags); -} - - -/* - * ------------------------------------------------------------------- - * bcm_flush_char () - * - * Nothing to flush. Polled I/O is used. - * ------------------------------------------------------------------- - */ -static void bcm63xx_cons_flush_chars(struct tty_struct *tty) -{ -} - - -/* - * ------------------------------------------------------------------- - * bcm63xx_cons_write () - * - * Main output routine using polled I/O. - * ------------------------------------------------------------------- - */ -static int bcm63xx_cons_write(struct tty_struct *tty, - const unsigned char *buf, int count) -{ - int c; - - for (c = 0; c < count; c++) - _putc(buf[c]); - return count; -} - -/* - * ------------------------------------------------------------------- - * bcm63xx_cons_write_room () - * - * Compute the amount of space available for writing. - * ------------------------------------------------------------------- - */ -static int bcm63xx_cons_write_room(struct tty_struct *tty) -{ - /* Pick a number. Any number. Polled I/O is used. */ - return 1024; -} - -/* - * ------------------------------------------------------------------- - * bcm_chars_in_buffer () - * - * compute the amount of char left to be transmitted - * ------------------------------------------------------------------- - */ -static int bcm_chars_in_buffer(struct tty_struct *tty) -{ - return 0; -} - -/* - * ------------------------------------------------------------------- - * bcm_flush_buffer () - * - * Empty the output buffer - * ------------------------------------------------------------------- - */ -static void bcm_flush_buffer(struct tty_struct *tty) -{ - tty_wakeup(tty); -} - -/* - * ------------------------------------------------------------ - * bcm_throttle () and bcm_unthrottle () - * - * This routine is called by the upper-layer tty layer to signal that - * incoming characters should be throttled (or not). - * ------------------------------------------------------------ - */ -static void bcm_throttle(struct tty_struct *tty) -{ - struct bcm_serial *info = (struct bcm_serial *) tty->driver_data; - if (I_IXOFF(tty)) - info->x_char = STOP_CHAR(tty); -} - -static void bcm_unthrottle(struct tty_struct *tty) -{ - struct bcm_serial *info = (struct bcm_serial *) tty->driver_data; - if (I_IXOFF(tty)) { - if (info->x_char) - info->x_char = 0; - else - info->x_char = START_CHAR(tty); - } -} - -static void bcm_send_xchar(struct tty_struct *tty, char ch) -{ - struct bcm_serial *info = (struct bcm_serial *) tty->driver_data; - info->x_char = ch; - if (ch) - bcm_start(info->tty); -} - -/* - * ------------------------------------------------------------ - * rs_ioctl () and friends - * ------------------------------------------------------------ - */ -static int get_serial_info(struct bcm_serial *info, - struct serial_struct *retinfo) -{ - struct serial_struct tmp; - - if (!retinfo) - return -EFAULT; - - memset(&tmp, 0, sizeof(tmp)); - tmp.type = info->type; - tmp.line = info->line; - tmp.port = (int) info->port; - tmp.irq = info->irq; - tmp.flags = 0; - tmp.baud_base = info->baud_base; - tmp.close_delay = info->close_delay; - tmp.closing_wait = info->closing_wait; - - return copy_to_user(retinfo, &tmp, sizeof(*retinfo)); -} - -static int set_serial_info(struct bcm_serial *info, - struct serial_struct *new_info) -{ - struct serial_struct new_serial; - struct bcm_serial old_info; - int retval = 0; - - if (!new_info) - return -EFAULT; - - copy_from_user(&new_serial, new_info, sizeof(new_serial)); - old_info = *info; - - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - - - if (info->count > 1) - return -EBUSY; - - /* OK, past this point, all the error checking has been done. - * At this point, we start making changes..... - */ - info->baud_base = new_serial.baud_base; - info->type = new_serial.type; - info->close_delay = new_serial.close_delay; - info->closing_wait = new_serial.closing_wait; - retval = startup(info); - return retval; -} - -/* - * get_lsr_info - get line status register info - * - * Purpose: Let user call ioctl() to get info when the UART physically - * is emptied. On bus types like RS485, the transmitter must - * release the bus after transmitting. This must be done when - * the transmit shift register is empty, not be done when the - * transmit holding register is empty. This functionality - * allows an RS485 driver to be written in user space. - */ -static int get_lsr_info(struct bcm_serial *info, unsigned int *value) -{ - return (0); -} - -/* - * This routine sends a break character out the serial port. - */ -static void send_break(struct bcm_serial *info, int duration) -{ - unsigned long flags; - - if (!info->port) - return; - - current->state = TASK_INTERRUPTIBLE; - - /*save_flags (flags); - cli(); */ - spin_lock_irqsave(&bcm963xx_serial_lock, flags); - - info->port->control |= XMITBREAK; - schedule_timeout(duration); - info->port->control &= ~XMITBREAK; - - spin_unlock_irqrestore(&bcm963xx_serial_lock, flags); - //restore_flags (flags); -} - -static int bcm_ioctl(struct tty_struct *tty, struct file *file, - unsigned int cmd, unsigned long arg) -{ - int error; - struct bcm_serial *info = (struct bcm_serial *) tty->driver_data; - int retval; - - if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && - (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) && - (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) { - if (tty->flags & (1 << TTY_IO_ERROR)) - return -EIO; - } - switch (cmd) { - - case TCSBRK: /* SVID version: non-zero arg --> no break */ - retval = tty_check_change(tty); - if (retval) - return retval; - tty_wait_until_sent(tty, 0); - if (!arg) - send_break(info, HZ / 4); /* 1/4 second */ - return 0; - - case TCSBRKP: /* support for POSIX tcsendbreak() */ - retval = tty_check_change(tty); - if (retval) - return retval; - tty_wait_until_sent(tty, 0); - send_break(info, arg ? arg * (HZ / 10) : HZ / 4); - return 0; - - case TIOCGSOFTCAR: - error = - access_ok(VERIFY_WRITE, (void *) arg, sizeof(long)); - if (!error) - return -EFAULT; - else { - put_user(C_CLOCAL(tty) ? 1 : 0, - (unsigned long *) arg); - return 0; - } - - case TIOCSSOFTCAR: - error = get_user(arg, (unsigned long *) arg); - if (error) - return error; - tty->termios->c_cflag = - ((tty->termios-> - c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0)); - return 0; - - case TIOCGSERIAL: - error = - access_ok(VERIFY_WRITE, (void *) arg, - sizeof(struct serial_struct)); - if (!error) - return -EFAULT; - else - return get_serial_info(info, - (struct serial_struct *) - arg); - - case TIOCSSERIAL: - return set_serial_info(info, (struct serial_struct *) arg); - - case TIOCSERGETLSR: /* Get line status register */ - error = - access_ok(VERIFY_WRITE, (void *) arg, - sizeof(unsigned int)); - if (!error) - return -EFAULT; - else - return get_lsr_info(info, (unsigned int *) arg); - - case TIOCSERGSTRUCT: - error = - access_ok(VERIFY_WRITE, (void *) arg, - sizeof(struct bcm_serial)); - if (!error) - return -EFAULT; - else { - copy_to_user((struct bcm_serial *) arg, info, - sizeof(struct bcm_serial)); - return 0; - } - - default: - return -ENOIOCTLCMD; - } - return 0; -} - -static void bcm_set_termios(struct tty_struct *tty, - struct ktermios *old_termios) -{ - struct bcm_serial *info = (struct bcm_serial *) tty->driver_data; - - if (tty->termios->c_cflag != old_termios->c_cflag) - change_speed(info->port, tty->termios->c_cflag); -} - -/* - * ------------------------------------------------------------ - * bcm63xx_cons_close() - * - * This routine is called when the serial port gets closed. First, we - * wait for the last remaining data to be sent. Then, we turn off - * the transmit enable and receive enable flags. - * ------------------------------------------------------------ - */ -static void bcm63xx_cons_close(struct tty_struct *tty, struct file *filp) -{ - struct bcm_serial *info = (struct bcm_serial *) tty->driver_data; - unsigned long flags; - - if (!info) - return; - - /*save_flags (flags); - cli(); */ - spin_lock_irqsave(&bcm963xx_serial_lock, flags); - - if (tty_hung_up_p(filp)) { - spin_unlock_irqrestore(&bcm963xx_serial_lock, flags); - //restore_flags (flags); - return; - } - - if ((tty->count == 1) && (info->count != 1)) { - - /* Uh, oh. tty->count is 1, which means that the tty - * structure will be freed. Info->count should always - * be one in these conditions. If it's greater than - * one, we've got real problems, since it means the - * serial port won't be shutdown. - */ - printk - ("bcm63xx_cons_close: bad serial port count; tty->count is 1, " - "info->count is %d\n", info->count); - info->count = 1; - } - - if (--info->count < 0) { - printk("ds_close: bad serial port count for ttys%d: %d\n", - info->line, info->count); - info->count = 0; - } - - if (info->count) { - //restore_flags (flags); - spin_unlock_irqrestore(&bcm963xx_serial_lock, flags); - return; - } - - /* Now we wait for the transmit buffer to clear; and we notify - * the line discipline to only process XON/XOFF characters. - */ - tty->closing = 1; - - /* At this point we stop accepting input. To do this, we - * disable the receive line status interrupts. - */ - shutdown(info); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) - if (tty->driver->flush_buffer) - tty->driver->flush_buffer(tty); -#else - if (tty->driver.flush_buffer) - tty->driver.flush_buffer(tty); -#endif - if (tty->ldisc.flush_buffer) - tty->ldisc.flush_buffer(tty); - - tty->closing = 0; - info->event = 0; - info->tty = 0; - if (tty->ldisc.num != tty_ldisc_get(N_TTY)->num) { - if (tty->ldisc.close) - (tty->ldisc.close) (tty); - tty->ldisc = *tty_ldisc_get(N_TTY); - tty->termios->c_line = N_TTY; - if (tty->ldisc.open) - (tty->ldisc.open) (tty); - } - if (info->blocked_open) { - if (info->close_delay) { - current->state = TASK_INTERRUPTIBLE; - schedule_timeout(info->close_delay); - } - wake_up_interruptible(&info->open_wait); - } - wake_up_interruptible(&info->close_wait); - - //restore_flags (flags); - spin_unlock_irqrestore(&bcm963xx_serial_lock, flags); -} - -/* - * bcm_hangup () --- called by tty_hangup() when a hangup is signaled. - */ -static void bcm_hangup(struct tty_struct *tty) -{ - - struct bcm_serial *info = (struct bcm_serial *) tty->driver_data; - - shutdown(info); - info->event = 0; - info->count = 0; - info->tty = 0; - wake_up_interruptible(&info->open_wait); -} - -/* - * ------------------------------------------------------------ - * rs_open() and friends - * ------------------------------------------------------------ - */ -static int block_til_ready(struct tty_struct *tty, struct file *filp, - struct bcm_serial *info) -{ - return 0; -} - -/* - * This routine is called whenever a serial port is opened. It - * enables interrupts for a serial port. It also performs the - * serial-specific initialization for the tty structure. - */ -static int bcm63xx_cons_open(struct tty_struct *tty, struct file *filp) -{ - struct bcm_serial *info; - int retval, line; - - // Make sure we're only opening on of the ports we support -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) - line = MINOR(tty->driver->cdev.dev) - tty->driver->minor_start; -#else - line = MINOR(tty->device) - tty->driver.minor_start; -#endif - - if ((line < 0) || (line >= BCM_NUM_UARTS)) - return -ENODEV; - - info = lines[line]; - - tty->low_latency = 1; - info->port->intMask = 0; /* Clear any pending interrupts */ - info->port->intMask = RXINT; /* Enable RX */ - - info->count++; - tty->driver_data = info; - info->tty = tty; - enable_brcm_irq(INTERRUPT_ID_UART); - - // Start up serial port - retval = startup(info); - if (retval) - return retval; - - retval = block_til_ready(tty, filp, info); - if (retval) - return retval; - - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) - info->pgrp = task_pgrp(current); -#else - info->session = current->session; - info->pgrp = current->pgrp; -#endif - - return 0; -} - - -static struct tty_operations rs_ops = { - .open = bcm63xx_cons_open, - .close = bcm63xx_cons_close, - .write = bcm63xx_cons_write, - .flush_chars = bcm63xx_cons_flush_chars, - .write_room = bcm63xx_cons_write_room, - .chars_in_buffer = bcm_chars_in_buffer, - .flush_buffer = bcm_flush_buffer, - .ioctl = bcm_ioctl, - .throttle = bcm_throttle, - .unthrottle = bcm_unthrottle, - .send_xchar = bcm_send_xchar, - .set_termios = bcm_set_termios, - .stop = bcm_stop, - .start = bcm_start, - .hangup = bcm_hangup, -}; - -/* -------------------------------------------------------------------------- - Name: bcm63xx_serialinit - Purpose: Initialize our BCM63xx serial driver --------------------------------------------------------------------------- */ -static int __init bcm63xx_serialinit(void) -{ - int i, flags; - struct bcm_serial *info; - - // Print the driver version information - printk(VER_STR); - serial_driver = alloc_tty_driver(BCM_NUM_UARTS); - if (!serial_driver) - return -ENOMEM; - - serial_driver->owner = THIS_MODULE; - serial_driver->name = "ttyS"; - serial_driver->major = TTY_MAJOR; - serial_driver->minor_start = 64; - serial_driver->num = 1; - serial_driver->type = TTY_DRIVER_TYPE_SERIAL; - serial_driver->subtype = SERIAL_TYPE_NORMAL; - serial_driver->init_termios = tty_std_termios; - serial_driver->init_termios.c_cflag = B115200 | CS8 | CREAD | HUPCL | CLOCAL; - serial_driver->flags = TTY_DRIVER_REAL_RAW; - - serial_driver->termios = serial_termios; - serial_driver->termios_locked = serial_termios_locked; - - tty_set_operations(serial_driver, &rs_ops); - - if (tty_register_driver(serial_driver)) - panic("Couldn't register serial driver\n"); - - //save_flags(flags); cli(); - spin_lock_irqsave(&bcm963xx_serial_lock, flags); - - for (i = 0; i < 1; i++) { - info = &multi[i]; - lines[i] = info; - info->magic = SERIAL_MAGIC; - info->port = (Uart *) ((char *) UART_BASE + (i * 0x20)); - info->tty = 0; - info->irq = (2 - i) + 8; - info->line = i; - info->close_delay = 50; - info->closing_wait = 3000; - info->x_char = 0; - info->event = 0; - info->count = 0; - info->blocked_open = 0; - info->normal_termios = serial_driver->init_termios; - init_waitqueue_head(&info->open_wait); - init_waitqueue_head(&info->close_wait); - - /* If we are pointing to address zero then punt - not correctly - * set up in setup.c to handle this. - */ - if (!info->port) - return 0; - BcmHalMapInterrupt(bcm_interrupt, 0, INTERRUPT_ID_UART); - } - - /* order matters here... the trick is that flags - * is updated... in request_irq - to immediatedly obliterate - * it is unwise. - */ - spin_unlock_irqrestore(&bcm963xx_serial_lock, flags); - return 0; -} - -module_init(bcm63xx_serialinit); - -/* -------------------------------------------------------------------------- - Name: bcm_console_print - Purpose: bcm_console_print is registered for printk. - The console_lock must be held when we get here. --------------------------------------------------------------------------- */ -static void bcm_console_print(struct console *cons, const char *str, - unsigned int count) -{ - unsigned int i; - //_puts(str); - for (i = 0; i < count; i++, str++) { - _putc(*str); - if (*str == 10) { - _putc(13); - } - } -} - -static struct tty_driver *bcm_console_device(struct console *c, int *index) -{ - *index = c->index; - return serial_driver; -} - -static int __init bcm_console_setup(struct console *co, char *options) -{ - return 0; -} - -static struct console bcm_sercons = { - .name = "ttyS", - .write = bcm_console_print, - .device = bcm_console_device, - .setup = bcm_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -static int __init bcm63xx_console_init(void) -{ - register_console(&bcm_sercons); - return 0; -} - -console_initcall(bcm63xx_console_init); diff --git a/target/linux/brcm63xx/files/include/asm-mips/cfe.h b/target/linux/brcm63xx/files/include/asm-mips/cfe.h deleted file mode 100644 index 47c3f5613d..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/cfe.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Broadcom Common Firmware Environment (CFE) support - * - * Copyright 2000, 2001, 2002 - * Broadcom Corporation. All rights reserved. - * - * Copyright (C) 2006 Michael Buesch - * - * Original Authors: Mitch Lichtenberg, Chris Demetriou - * - * This software is furnished under license and may be used and copied only - * in accordance with the following terms and conditions. Subject to these - * conditions, you may download, copy, install, use, modify and distribute - * modified or unmodified copies of this software in source and/or binary - * form. No title or ownership is transferred hereby. - * - * 1) Any source code used, modified or distributed must reproduce and - * retain this copyright notice and list of conditions as they appear in - * the source file. - * - * 2) No right is granted to use any trade name, trademark, or logo of - * Broadcom Corporation. The "Broadcom Corporation" name may not be - * used to endorse or promote products derived from this software - * without the prior written permission of Broadcom Corporation. - * - * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE - * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE - * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef LINUX_CFE_API_H_ -#define LINUX_CFE_API_H_ - -#include - - -#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ -#define CFE_MI_AVAILABLE 1 /* memory is available */ - -#define CFE_FLG_WARMSTART 0x00000001 -#define CFE_FLG_FULL_ARENA 0x00000001 -#define CFE_FLG_ENV_PERMANENT 0x00000001 - -#define CFE_CPU_CMD_START 1 -#define CFE_CPU_CMD_STOP 0 - -#define CFE_STDHANDLE_CONSOLE 0 - -#define CFE_DEV_NETWORK 1 -#define CFE_DEV_DISK 2 -#define CFE_DEV_FLASH 3 -#define CFE_DEV_SERIAL 4 -#define CFE_DEV_CPU 5 -#define CFE_DEV_NVRAM 6 -#define CFE_DEV_CLOCK 7 -#define CFE_DEV_OTHER 8 -#define CFE_DEV_MASK 0x0F - -#define CFE_CACHE_FLUSH_D 1 -#define CFE_CACHE_INVAL_I 2 -#define CFE_CACHE_INVAL_D 4 -#define CFE_CACHE_INVAL_L2 8 - -#define CFE_FWI_64BIT 0x00000001 -#define CFE_FWI_32BIT 0x00000002 -#define CFE_FWI_RELOC 0x00000004 -#define CFE_FWI_UNCACHED 0x00000008 -#define CFE_FWI_MULTICPU 0x00000010 -#define CFE_FWI_FUNCSIM 0x00000020 -#define CFE_FWI_RTLSIM 0x00000040 - -struct cfe_fwinfo { - s64 version; /* major, minor, eco version */ - s64 totalmem; /* total installed mem */ - s64 flags; /* various flags */ - s64 boardid; /* board ID */ - s64 bootarea_va; /* VA of boot area */ - s64 bootarea_pa; /* PA of boot area */ - s64 bootarea_size; /* size of boot area */ -}; - - -/* The public CFE API */ - -int cfe_present(void); /* Check if we booted from CFE. Returns bool */ - -int cfe_getticks(s64 *ticks); -int cfe_close(int handle); -int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1); -int cfe_cpu_stop(int cpu); -int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen); -int cfe_enumdev(int idx, char *name, int namelen); -int cfe_enummem(int idx, int flags, u64 *start, u64 *length, - u64 *type); -int cfe_exit(int warm, int status); -int cfe_flushcache(int flags); -int cfe_getdevinfo(char *name); -int cfe_getenv(char *name, char *dest, int destlen); -int cfe_getfwinfo(struct cfe_fwinfo *info); -int cfe_getstdhandle(int handletype); -int cfe_inpstat(int handle); -int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, - int length, int *retlen, u64 offset); -int cfe_open(char *name); -int cfe_read(int handle, unsigned char *buffer, int length); -int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length); -int cfe_setenv(char *name, char *val); -int cfe_write(int handle, unsigned char *buffer, int length); -int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, - int length); - - -/* High level API */ - -/* Print some information to CFE's console (most likely serial line) */ -int cfe_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2))); -int cfe_vprintk(const char *fmt, va_list args); - - - -/* Error codes returned by the low API functions */ - -#define CFE_ISERR(errcode) (errcode < 0) - -#define CFE_OK 0 -#define CFE_ERR -1 /* generic error */ -#define CFE_ERR_INV_COMMAND -2 -#define CFE_ERR_EOF -3 -#define CFE_ERR_IOERR -4 -#define CFE_ERR_NOMEM -5 -#define CFE_ERR_DEVNOTFOUND -6 -#define CFE_ERR_DEVOPEN -7 -#define CFE_ERR_INV_PARAM -8 -#define CFE_ERR_ENVNOTFOUND -9 -#define CFE_ERR_ENVREADONLY -10 - -#define CFE_ERR_NOTELF -11 -#define CFE_ERR_NOT32BIT -12 -#define CFE_ERR_WRONGENDIAN -13 -#define CFE_ERR_BADELFVERS -14 -#define CFE_ERR_NOTMIPS -15 -#define CFE_ERR_BADELFFMT -16 -#define CFE_ERR_BADADDR -17 - -#define CFE_ERR_FILENOTFOUND -18 -#define CFE_ERR_UNSUPPORTED -19 - -#define CFE_ERR_HOSTUNKNOWN -20 - -#define CFE_ERR_TIMEOUT -21 - -#define CFE_ERR_PROTOCOLERR -22 - -#define CFE_ERR_NETDOWN -23 -#define CFE_ERR_NONAMESERVER -24 - -#define CFE_ERR_NOHANDLES -25 -#define CFE_ERR_ALREADYBOUND -26 - -#define CFE_ERR_CANNOTSET -27 -#define CFE_ERR_NOMORE -28 -#define CFE_ERR_BADFILESYS -29 -#define CFE_ERR_FSNOTAVAIL -30 - -#define CFE_ERR_INVBOOTBLOCK -31 -#define CFE_ERR_WRONGDEVTYPE -32 -#define CFE_ERR_BBCHECKSUM -33 -#define CFE_ERR_BOOTPROGCHKSUM -34 - -#define CFE_ERR_LDRNOTAVAIL -35 - -#define CFE_ERR_NOTREADY -36 - -#define CFE_ERR_GETMEM -37 -#define CFE_ERR_SETMEM -38 - -#define CFE_ERR_NOTCONN -39 -#define CFE_ERR_ADDRINUSE -40 - - -#endif /* LINUX_CFE_API_H_ */ diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6338_intr.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6338_intr.h deleted file mode 100644 index 3a6e00a2ae..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6338_intr.h +++ /dev/null @@ -1,64 +0,0 @@ -/* -<:copyright-gpl - Copyright 2003 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -#ifndef __6338_INTR_H -#define __6338_INTR_H - -/*=====================================================================*/ -/* BCM6338 External Interrupt Level Assignments */ -/*=====================================================================*/ -#define INTERRUPT_ID_EXTERNAL_0 3 -#define INTERRUPT_ID_EXTERNAL_1 4 -#define INTERRUPT_ID_EXTERNAL_2 5 -#define INTERRUPT_ID_EXTERNAL_3 6 - -/*=====================================================================*/ -/* BCM6338 Timer Interrupt Level Assignments */ -/*=====================================================================*/ -#define MIPS_TIMER_INT 7 - -/*=====================================================================*/ -/* Peripheral ISR Table Offset */ -/*=====================================================================*/ -#define INTERNAL_ISR_TABLE_OFFSET 8 - -/*=====================================================================*/ -/* Logical Peripheral Interrupt IDs */ -/*=====================================================================*/ - -#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0) -#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1) -#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2) -#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 4) -#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 5) -#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 6) -#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 7) -#define INTERRUPT_ID_EMAC1 (INTERNAL_ISR_TABLE_OFFSET + 8) -#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 9) -#define INTERRUPT_ID_SDRAM (INTERNAL_ISR_TABLE_OFFSET + 10) -#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 11) -#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 12) -#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 13) -#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 14) -#define INTERRUPT_ID_EMAC1_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 15) -#define INTERRUPT_ID_EMAC1_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 16) -#define INTERRUPT_ID_SDIO (INTERNAL_ISR_TABLE_OFFSET + 17) - -#endif /* __BCM6338_H */ - diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6338_map_part.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6338_map_part.h deleted file mode 100644 index 70bf807342..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6338_map_part.h +++ /dev/null @@ -1,334 +0,0 @@ -/* -<:copyright-gpl - Copyright 2004 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -#ifndef __BCM6338_MAP_H -#define __BCM6338_MAP_H - -#include "bcmtypes.h" - -#define PERF_BASE 0xfffe0000 -#define TIMR_BASE 0xfffe0200 -#define UART_BASE 0xfffe0300 -#define GPIO_BASE 0xfffe0400 -#define SPI_BASE 0xfffe0c00 - -typedef struct PerfControl { - uint32 RevID; - uint16 testControl; - uint16 blkEnables; -#define EMAC_CLK_EN 0x0010 -#define USBS_CLK_EN 0x0010 -#define SAR_CLK_EN 0x0020 - -#define SPI_CLK_EN 0x0200 - - uint32 pll_control; -#define SOFT_RESET 0x00000001 - - uint32 IrqMask; - uint32 IrqStatus; - - uint32 ExtIrqCfg; -#define EI_SENSE_SHFT 0 -#define EI_STATUS_SHFT 5 -#define EI_CLEAR_SHFT 10 -#define EI_MASK_SHFT 15 -#define EI_INSENS_SHFT 20 -#define EI_LEVEL_SHFT 25 - - uint32 unused[4]; /* (18) */ - uint32 BlockSoftReset; /* (28) */ -#define BSR_SPI 0x00000001 -#define BSR_EMAC 0x00000004 -#define BSR_USBH 0x00000008 -#define BSR_USBS 0x00000010 -#define BSR_ADSL 0x00000020 -#define BSR_DMAMEM 0x00000040 -#define BSR_SAR 0x00000080 -#define BSR_ACLC 0x00000100 -#define BSR_ADSL_MIPS_PLL 0x00000400 -#define BSR_ALL_BLOCKS \ - (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \ - BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL) -} PerfControl; - -#define PERF ((volatile PerfControl * const) PERF_BASE) - - -typedef struct Timer { - uint16 unused0; - byte TimerMask; -#define TIMER0EN 0x01 -#define TIMER1EN 0x02 -#define TIMER2EN 0x04 - byte TimerInts; -#define TIMER0 0x01 -#define TIMER1 0x02 -#define TIMER2 0x04 -#define WATCHDOG 0x08 - uint32 TimerCtl0; - uint32 TimerCtl1; - uint32 TimerCtl2; -#define TIMERENABLE 0x80000000 -#define RSTCNTCLR 0x40000000 - uint32 TimerCnt0; - uint32 TimerCnt1; - uint32 TimerCnt2; - uint32 WatchDogDefCount; - - /* Write 0xff00 0x00ff to Start timer - * Write 0xee00 0x00ee to Stop and re-load default count - * Read from this register returns current watch dog count - */ - uint32 WatchDogCtl; - - /* Number of 40-MHz ticks for WD Reset pulse to last */ - uint32 WDResetCount; -} Timer; - -#define TIMER ((volatile Timer * const) TIMR_BASE) -typedef struct UartChannel { - byte unused0; - byte control; -#define BRGEN 0x80 /* Control register bit defs */ -#define TXEN 0x40 -#define RXEN 0x20 -#define LOOPBK 0x10 -#define TXPARITYEN 0x08 -#define TXPARITYEVEN 0x04 -#define RXPARITYEN 0x02 -#define RXPARITYEVEN 0x01 - - byte config; -#define XMITBREAK 0x40 -#define BITS5SYM 0x00 -#define BITS6SYM 0x10 -#define BITS7SYM 0x20 -#define BITS8SYM 0x30 -#define ONESTOP 0x07 -#define TWOSTOP 0x0f - /* 4-LSBS represent STOP bits/char - * in 1/8 bit-time intervals. Zero - * represents 1/8 stop bit interval. - * Fifteen represents 2 stop bits. - */ - byte fifoctl; -#define RSTTXFIFOS 0x80 -#define RSTRXFIFOS 0x40 - /* 5-bit TimeoutCnt is in low bits of this register. - * This count represents the number of characters - * idle times before setting receive Irq when below threshold - */ - uint32 baudword; - /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate - */ - - byte txf_levl; /* Read-only fifo depth */ - byte rxf_levl; /* Read-only fifo depth */ - byte fifocfg; /* Upper 4-bits are TxThresh, Lower are - * RxThreshold. Irq can be asserted - * when rx fifo> thresh, txfifo -*/ - -#ifndef __6345_INTR_H -#define __6345_INTR_H - - -/*=====================================================================*/ -/* BCM6345 External Interrupt Level Assignments */ -/*=====================================================================*/ -#define INTERRUPT_ID_EXTERNAL_0 3 -#define INTERRUPT_ID_EXTERNAL_1 4 -#define INTERRUPT_ID_EXTERNAL_2 5 -#define INTERRUPT_ID_EXTERNAL_3 6 - -/*=====================================================================*/ -/* BCM6345 Timer Interrupt Level Assignments */ -/*=====================================================================*/ -#define MIPS_TIMER_INT 7 - -/*=====================================================================*/ -/* Peripheral ISR Table Offset */ -/*=====================================================================*/ -#define INTERNAL_ISR_TABLE_OFFSET 8 -#define DMA_ISR_TABLE_OFFSET (INTERNAL_ISR_TABLE_OFFSET + 13) - -/*=====================================================================*/ -/* Logical Peripheral Interrupt IDs */ -/*=====================================================================*/ - -/* Internal peripheral interrupt IDs */ -#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0) -#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2) -#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 3) -#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 4) -#define INTERRUPT_ID_USB (INTERNAL_ISR_TABLE_OFFSET + 5) -#define INTERRUPT_ID_EMAC (INTERNAL_ISR_TABLE_OFFSET + 8) -#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 12) - -/* DMA channel interrupt IDs */ -#define INTERRUPT_ID_EMAC_RX_CHAN (DMA_ISR_TABLE_OFFSET + EMAC_RX_CHAN) -#define INTERRUPT_ID_EMAC_TX_CHAN (DMA_ISR_TABLE_OFFSET + EMAC_TX_CHAN) -#define INTERRUPT_ID_EBI_RX_CHAN (DMA_ISR_TABLE_OFFSET + EBI_RX_CHAN) -#define INTERRUPT_ID_EBI_TX_CHAN (DMA_ISR_TABLE_OFFSET + EBI_TX_CHAN) -#define INTERRUPT_ID_RESERVED_RX_CHAN (DMA_ISR_TABLE_OFFSET + RESERVED_RX_CHAN) -#define INTERRUPT_ID_RESERVED_TX_CHAN (DMA_ISR_TABLE_OFFSET + RESERVED_TX_CHAN) -#define INTERRUPT_ID_USB_BULK_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_BULK_RX_CHAN) -#define INTERRUPT_ID_USB_BULK_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_BULK_TX_CHAN) -#define INTERRUPT_ID_USB_CNTL_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_CNTL_RX_CHAN) -#define INTERRUPT_ID_USB_CNTL_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_CNTL_TX_CHAN) -#define INTERRUPT_ID_USB_ISO_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_ISO_RX_CHAN) -#define INTERRUPT_ID_USB_ISO_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_ISO_TX_CHAN) - - -#endif /* __BCM6345_H */ - diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6345_map_part.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6345_map_part.h deleted file mode 100644 index 78e59a4399..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6345_map_part.h +++ /dev/null @@ -1,163 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -#ifndef __BCM6345_MAP_H -#define __BCM6345_MAP_H - - -#include "bcmtypes.h" -#include "6345_intr.h" - -typedef struct IntControl { - uint32 RevID; - uint16 testControl; - uint16 blkEnables; -#define USB_CLK_EN 0x0100 -#define EMAC_CLK_EN 0x0080 -#define UART_CLK_EN 0x0008 -#define CPU_CLK_EN 0x0001 - - uint32 pll_control; -#define SOFT_RESET 0x00000001 - - uint32 IrqMask; - uint32 IrqStatus; - - uint32 ExtIrqCfg; -#define EI_SENSE_SHFT 0 -#define EI_STATUS_SHFT 4 -#define EI_CLEAR_SHFT 8 -#define EI_MASK_SHFT 12 -#define EI_INSENS_SHFT 16 -#define EI_LEVEL_SHFT 20 -} IntControl; - -#define INTC_BASE 0xfffe0000 -#define PERF ((volatile IntControl * const) INTC_BASE) - -#define TIMR_BASE 0xfffe0200 -typedef struct Timer { - uint16 unused0; - byte TimerMask; -#define TIMER0EN 0x01 -#define TIMER1EN 0x02 -#define TIMER2EN 0x04 - byte TimerInts; -#define TIMER0 0x01 -#define TIMER1 0x02 -#define TIMER2 0x04 -#define WATCHDOG 0x08 - uint32 TimerCtl0; - uint32 TimerCtl1; - uint32 TimerCtl2; -#define TIMERENABLE 0x80000000 -#define RSTCNTCLR 0x40000000 - uint32 TimerCnt0; - uint32 TimerCnt1; - uint32 TimerCnt2; - uint32 WatchDogDefCount; - - /* Write 0xff00 0x00ff to Start timer - * Write 0xee00 0x00ee to Stop and re-load default count - * Read from this register returns current watch dog count - */ - uint32 WatchDogCtl; - - /* Number of 40-MHz ticks for WD Reset pulse to last */ - uint32 WDResetCount; -} Timer; - -#define TIMER ((volatile Timer * const) TIMR_BASE) - -typedef struct UartChannel { - byte unused0; - byte control; -#define BRGEN 0x80 /* Control register bit defs */ -#define TXEN 0x40 -#define RXEN 0x20 -#define TXPARITYEN 0x08 -#define TXPARITYEVEN 0x04 -#define RXPARITYEN 0x02 -#define RXPARITYEVEN 0x01 - byte config; -#define BITS5SYM 0x00 -#define BITS6SYM 0x10 -#define BITS7SYM 0x20 -#define BITS8SYM 0x30 -#define XMITBREAK 0x40 -#define ONESTOP 0x07 -#define TWOSTOP 0x0f - - byte fifoctl; -#define RSTTXFIFOS 0x80 -#define RSTRXFIFOS 0x40 - uint32 baudword; - - byte txf_levl; - byte rxf_levl; - byte fifocfg; - byte prog_out; - - byte unused1; - byte DeltaIPEdgeNoSense; - byte DeltaIPConfig_Mask; - byte DeltaIP_SyncIP; - uint16 intMask; - uint16 intStatus; -#define TXUNDERR 0x0002 -#define TXOVFERR 0x0004 -#define TXFIFOEMT 0x0020 -#define RXOVFERR 0x0080 -#define RXFIFONE 0x0800 -#define RXFRAMERR 0x1000 -#define RXPARERR 0x2000 -#define RXBRK 0x4000 - - uint16 unused2; - uint16 Data; - uint32 unused3; - uint32 unused4; -} Uart; - -#define UART_BASE 0xfffe0300 -#define UART ((volatile Uart * const) UART_BASE) - -typedef struct GpioControl { - uint16 unused0; - byte unused1; - byte TBusSel; - - uint16 unused2; - uint16 GPIODir; - byte unused3; - byte Leds; - uint16 GPIOio; - - uint32 UartCtl; -} GpioControl; - -#define GPIO_BASE 0xfffe0400 -#define GPIO ((volatile GpioControl * const) GPIO_BASE) - -#define GPIO_NUM_MAX_BITS_MASK 0x0f -#define GPIO_NUM_TO_MASK(X) (1 << ((X) & GPIO_NUM_MAX_BITS_MASK)) - - -#endif - diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6348_intr.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6348_intr.h deleted file mode 100644 index da3ee9fc34..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6348_intr.h +++ /dev/null @@ -1,74 +0,0 @@ -/* -<:copyright-gpl - Copyright 2003 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -#ifndef __6348_INTR_H -#define __6348_INTR_H - - -/*=====================================================================*/ -/* BCM6348 External Interrupt Level Assignments */ -/*=====================================================================*/ -#define INTERRUPT_ID_EXTERNAL_0 3 -#define INTERRUPT_ID_EXTERNAL_1 4 -#define INTERRUPT_ID_EXTERNAL_2 5 -#define INTERRUPT_ID_EXTERNAL_3 6 - -/*=====================================================================*/ -/* BCM6348 Timer Interrupt Level Assignments */ -/*=====================================================================*/ -#define MIPS_TIMER_INT 7 - -/*=====================================================================*/ -/* Peripheral ISR Table Offset */ -/*=====================================================================*/ -#define INTERNAL_ISR_TABLE_OFFSET 8 - -/*=====================================================================*/ -/* Logical Peripheral Interrupt IDs */ -/*=====================================================================*/ - -#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0) -#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1) -#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2) -#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 4) -#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 5) -#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 6) -#define INTERRUPT_ID_EMAC2 (INTERNAL_ISR_TABLE_OFFSET + 7) -#define INTERRUPT_ID_EMAC1 (INTERNAL_ISR_TABLE_OFFSET + 8) -#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 9) -#define INTERRUPT_ID_M2M (INTERNAL_ISR_TABLE_OFFSET + 10) -#define INTERRUPT_ID_ACLC (INTERNAL_ISR_TABLE_OFFSET + 11) -#define INTERRUPT_ID_USBH (INTERNAL_ISR_TABLE_OFFSET + 12) -#define INTERRUPT_ID_SDRAM (INTERNAL_ISR_TABLE_OFFSET + 13) -#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 14) -#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 15) -#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 16) -#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 17) -#define INTERRUPT_ID_USB_ISO_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 18) -#define INTERRUPT_ID_USB_ISO_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 19) -#define INTERRUPT_ID_EMAC1_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 20) -#define INTERRUPT_ID_EMAC1_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 21) -#define INTERRUPT_ID_EMAC2_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 22) -#define INTERRUPT_ID_EMAC2_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 23) -#define INTERRUPT_ID_MPI (INTERNAL_ISR_TABLE_OFFSET + 24) -#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 25) - - -#endif /* __BCM6348_H */ - diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6348_map_part.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6348_map_part.h deleted file mode 100644 index 199ef9e15e..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6348_map_part.h +++ /dev/null @@ -1,500 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -#ifndef __BCM6348_MAP_H -#define __BCM6348_MAP_H - -#include "bcmtypes.h" - -#define PERF_BASE 0xfffe0000 -#define TIMR_BASE 0xfffe0200 -#define UART_BASE 0xfffe0300 -#define GPIO_BASE 0xfffe0400 -#define MPI_BASE 0xfffe2000 /* MPI control registers */ -#define USB_HOST_BASE 0xfffe1b00 /* USB host registers */ -#define USB_HOST_NON_OHCI 0xfffe1c00 /* USB host non-OHCI registers */ - -typedef struct PerfControl { - uint32 RevID; - uint16 testControl; - uint16 blkEnables; -#define EMAC_CLK_EN 0x0010 -#define SAR_CLK_EN 0x0020 -#define USBS_CLK_EN 0x0040 -#define USBH_CLK_EN 0x0100 - - uint32 pll_control; -#define SOFT_RESET 0x00000001 - - uint32 IrqMask; - uint32 IrqStatus; - - uint32 ExtIrqCfg; -#define EI_SENSE_SHFT 0 -#define EI_STATUS_SHFT 5 -#define EI_CLEAR_SHFT 10 -#define EI_MASK_SHFT 15 -#define EI_INSENS_SHFT 20 -#define EI_LEVEL_SHFT 25 - - uint32 unused[4]; /* (18) */ - uint32 BlockSoftReset; /* (28) */ -#define BSR_SPI 0x00000001 -#define BSR_EMAC 0x00000004 -#define BSR_USBH 0x00000008 -#define BSR_USBS 0x00000010 -#define BSR_ADSL 0x00000020 -#define BSR_DMAMEM 0x00000040 -#define BSR_SAR 0x00000080 -#define BSR_ACLC 0x00000100 -#define BSR_ADSL_MIPS_PLL 0x00000400 -#define BSR_ALL_BLOCKS \ - (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \ - BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL) - uint32 unused2[2]; /* (2c) */ - uint32 PllStrap; /* (34) */ -#define PLL_N1_SHFT 20 -#define PLL_N1_MASK (7< thresh, txfifo= 32) ? (1 << ((X-32) & GPIO_NUM_MAX_BITS_MASK_HIGH)) : (0) ) - - -/* -** External Bus Interface -*/ -typedef struct EbiChipSelect { - uint32 base; /* base address in upper 24 bits */ -#define EBI_SIZE_8K 0 -#define EBI_SIZE_16K 1 -#define EBI_SIZE_32K 2 -#define EBI_SIZE_64K 3 -#define EBI_SIZE_128K 4 -#define EBI_SIZE_256K 5 -#define EBI_SIZE_512K 6 -#define EBI_SIZE_1M 7 -#define EBI_SIZE_2M 8 -#define EBI_SIZE_4M 9 -#define EBI_SIZE_8M 10 -#define EBI_SIZE_16M 11 -#define EBI_SIZE_32M 12 -#define EBI_SIZE_64M 13 -#define EBI_SIZE_128M 14 -#define EBI_SIZE_256M 15 - uint32 config; -#define EBI_ENABLE 0x00000001 /* .. enable this range */ -#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */ -#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */ -#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */ -#define EBI_WREN 0x00000020 /* enable posted writes */ -#define EBI_POLARITY 0x00000040 /* .. set to invert something, - ** don't know what yet */ -#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */ -#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */ -#define EBI_FIFO 0x00000200 /* .. use fifo */ -#define EBI_RE 0x00000400 /* .. Reverse Endian */ -} EbiChipSelect; - -typedef struct MpiRegisters { - EbiChipSelect cs[7]; /* size chip select configuration */ -#define EBI_CS0_BASE 0 -#define EBI_CS1_BASE 1 -#define EBI_CS2_BASE 2 -#define EBI_CS3_BASE 3 -#define PCMCIA_COMMON_BASE 4 -#define PCMCIA_ATTRIBUTE_BASE 5 -#define PCMCIA_IO_BASE 6 - uint32 unused0[2]; /* reserved */ - uint32 ebi_control; /* ebi control */ - uint32 unused1[4]; /* reserved */ -#define EBI_ACCESS_TIMEOUT 0x000007FF - uint32 pcmcia_cntl1; /* pcmcia control 1 */ -#define PCCARD_CARD_RESET 0x00040000 -#define CARDBUS_ENABLE 0x00008000 -#define PCMCIA_ENABLE 0x00004000 -#define PCMCIA_GPIO_ENABLE 0x00002000 -#define CARDBUS_IDSEL 0x00001F00 -#define VS2_OEN 0x00000080 -#define VS1_OEN 0x00000040 -#define VS2_OUT 0x00000020 -#define VS1_OUT 0x00000010 -#define VS2_IN 0x00000008 -#define VS1_IN 0x00000004 -#define CD2_IN 0x00000002 -#define CD1_IN 0x00000001 -#define VS_MASK 0x0000000C -#define CD_MASK 0x00000003 - uint32 unused2; /* reserved */ - uint32 pcmcia_cntl2; /* pcmcia control 2 */ -#define PCMCIA_BYTESWAP_DIS 0x00000002 -#define PCMCIA_HALFWORD_EN 0x00000001 -#define RW_ACTIVE_CNT_BIT 2 -#define INACTIVE_CNT_BIT 8 -#define CE_SETUP_CNT_BIT 16 -#define CE_HOLD_CNT_BIT 24 - uint32 unused3[40]; /* reserved */ - - uint32 sp0range; /* PCI to internal system bus address space */ - uint32 sp0remap; - uint32 sp0cfg; - uint32 sp1range; - uint32 sp1remap; - uint32 sp1cfg; - - uint32 EndianCfg; - - uint32 l2pcfgctl; /* internal system bus to PCI IO/Cfg control */ -#define DIR_CFG_SEL 0x80000000 /* change from PCI I/O access to PCI config access */ -#define DIR_CFG_USEREG 0x40000000 /* use this register info for PCI configuration access */ -#define DEVICE_NUMBER 0x00007C00 /* device number for the PCI configuration access */ -#define FUNC_NUMBER 0x00000300 /* function number for the PCI configuration access */ -#define REG_NUMBER 0x000000FC /* register number for the PCI configuration access */ -#define CONFIG_TYPE 0x00000003 /* configuration type for the PCI configuration access */ - - uint32 l2pmrange1; /* internal system bus to PCI memory space */ -#define PCI_SIZE_64K 0xFFFF0000 -#define PCI_SIZE_128K 0xFFFE0000 -#define PCI_SIZE_256K 0xFFFC0000 -#define PCI_SIZE_512K 0xFFF80000 -#define PCI_SIZE_1M 0xFFF00000 -#define PCI_SIZE_2M 0xFFE00000 -#define PCI_SIZE_4M 0xFFC00000 -#define PCI_SIZE_8M 0xFF800000 -#define PCI_SIZE_16M 0xFF000000 -#define PCI_SIZE_32M 0xFE000000 - uint32 l2pmbase1; /* kseg0 or kseg1 address & 0x1FFFFFFF */ - uint32 l2pmremap1; -#define CARDBUS_MEM 0x00000004 -#define MEM_WINDOW_EN 0x00000001 - uint32 l2pmrange2; - uint32 l2pmbase2; - uint32 l2pmremap2; - uint32 l2piorange; /* internal system bus to PCI I/O space */ - uint32 l2piobase; - uint32 l2pioremap; - - uint32 pcimodesel; -#define PCI2_INT_BUS_RD_PREFECH 0x000000F0 -#define PCI_BAR2_NOSWAP 0x00000002 /* BAR at offset 0x20 */ -#define PCI_BAR1_NOSWAP 0x00000001 /* BAR at affset 0x1c */ - - uint32 pciintstat; /* PCI interrupt mask/status */ -#define MAILBOX1_SENT 0x08 -#define MAILBOX0_SENT 0x04 -#define MAILBOX1_MSG_RCV 0x02 -#define MAILBOX0_MSG_RCV 0x01 - uint32 locbuscntrl; /* internal system bus control */ -#define DIR_U2P_NOSWAP 0x00000002 -#define EN_PCI_GPIO 0x00000001 - uint32 locintstat; /* internal system bus interrupt mask/status */ -#define CSERR 0x0200 -#define SERR 0x0100 -#define EXT_PCI_INT 0x0080 -#define DIR_FAILED 0x0040 -#define DIR_COMPLETE 0x0020 -#define PCI_CFG 0x0010 - uint32 unused5[7]; - - uint32 mailbox0; - uint32 mailbox1; - - uint32 pcicfgcntrl; /* internal system bus PCI configuration control */ -#define PCI_CFG_REG_WRITE_EN 0x00000080 -#define PCI_CFG_ADDR 0x0000003C - uint32 pcicfgdata; /* internal system bus PCI configuration data */ - - uint32 locch2ctl; /* PCI to interrnal system bus DMA (downstream) local control */ -#define MPI_DMA_HALT 0x00000008 /* idle after finish current memory burst */ -#define MPI_DMA_PKT_HALT 0x00000004 /* idle after an EOP flag is detected */ -#define MPI_DMA_STALL 0x00000002 /* idle after an EOP flag is detected */ -#define MPI_DMA_ENABLE 0x00000001 /* set to enable channel */ - uint32 locch2intStat; -#define MPI_DMA_NO_DESC 0x00000004 /* no valid descriptors */ -#define MPI_DMA_DONE 0x00000002 /* packet xfer complete */ -#define MPI_DMA_BUFF_DONE 0x00000001 /* buffer done */ - uint32 locch2intMask; - uint32 unused6; - uint32 locch2descaddr; - uint32 locch2status1; -#define LOCAL_DESC_STATE 0xE0000000 -#define PCI_DESC_STATE 0x1C000000 -#define BYTE_DONE 0x03FFC000 -#define RING_ADDR 0x00003FFF - uint32 locch2status2; -#define BUFPTR_OFFSET 0x1FFF0000 -#define PCI_MASTER_STATE 0x000000C0 -#define LOC_MASTER_STATE 0x00000038 -#define CONTROL_STATE 0x00000007 - uint32 unused7; - - uint32 locch1Ctl; /*internal system bus to PCI DMA (upstream) local control */ -#define DMA_U2P_LE 0x00000200 /* local bus is little endian */ -#define DMA_U2P_NOSWAP 0x00000100 /* lccal bus is little endian but no data swapped */ - uint32 locch1intstat; - uint32 locch1intmask; - uint32 unused8; - uint32 locch1descaddr; - uint32 locch1status1; - uint32 locch1status2; - uint32 unused9; - - uint32 pcich1ctl; /* internal system bus to PCI DMA PCI control */ - uint32 pcich1intstat; - uint32 pcich1intmask; - uint32 pcich1descaddr; - uint32 pcich1status1; - uint32 pcich1status2; - - uint32 pcich2Ctl; /* PCI to internal system bus DMA PCI control */ - uint32 pcich2intstat; - uint32 pcich2intmask; - uint32 pcich2descaddr; - uint32 pcich2status1; - uint32 pcich2status2; - - uint32 perm_id; /* permanent device and vendor id */ - uint32 perm_rev; /* permanent revision id */ -} MpiRegisters; - -#define MPI ((volatile MpiRegisters * const) MPI_BASE) - -/* PCI configuration address space start offset 0x40 */ -#define BRCM_PCI_CONFIG_TIMER 0x40 -#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK 0x0000FF00 -#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK 0x000000FF - -/* USB host non-Open HCI register, USB_HOST_NON_OHCI, bit definitions. */ -#define NON_OHCI_ENABLE_PORT1 0x00000001 /* Use USB port 1 for host, not dev */ -#define NON_OHCI_BYTE_SWAP 0x00000008 /* Swap USB host registers */ - -#define USBH_NON_OHCI ((volatile unsigned long * const) USB_HOST_NON_OHCI) - -#endif - diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmTag.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmTag.h deleted file mode 100644 index e902e96aa3..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmTag.h +++ /dev/null @@ -1,153 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -//************************************************************************************** -// File Name : bcmTag.h -// -// Description: add tag with validation system to the firmware image file to be uploaded -// via http -// -// Created : 02/28/2002 seanl -//************************************************************************************** - -#ifndef _BCMTAG_H_ -#define _BCMTAG_H_ - - -#define BCM_SIG_1 "Broadcom Corporation" -#define BCM_SIG_2 "ver. 2.0" // was "firmware version 2.0" now it is split 6 char out for chip id. - -#define BCM_TAG_VER "6" -#define BCM_TAG_VER_LAST "26" - -// file tag (head) structure all is in clear text except validationTokens (crc, md5, sha1, etc). Total: 128 unsigned chars -#define TAG_LEN 256 -#define TAG_VER_LEN 4 -#define SIG_LEN 20 -#define SIG_LEN_2 14 // Original second SIG = 20 is now devided into 14 for SIG_LEN_2 and 6 for CHIP_ID -#define CHIP_ID_LEN 6 -#define IMAGE_LEN 10 -#define ADDRESS_LEN 12 -#define FLAG_LEN 2 -#define TOKEN_LEN 20 -#define BOARD_ID_LEN 16 -#define RESERVED_LEN (TAG_LEN - TAG_VER_LEN - SIG_LEN - SIG_LEN_2 - CHIP_ID_LEN - BOARD_ID_LEN - \ - (4*IMAGE_LEN) - (3*ADDRESS_LEN) - (3*FLAG_LEN) - (2*TOKEN_LEN)) - - -// TAG for downloadable image (kernel plus file system) -typedef struct _FILE_TAG -{ - unsigned char tagVersion[TAG_VER_LEN]; // tag version. Will be 2 here. - unsigned char signiture_1[SIG_LEN]; // text line for company info - unsigned char signiture_2[SIG_LEN_2]; // additional info (can be version number) - unsigned char chipId[CHIP_ID_LEN]; // chip id - unsigned char boardId[BOARD_ID_LEN]; // board id - unsigned char bigEndian[FLAG_LEN]; // if = 1 - big, = 0 - little endia of the host - unsigned char totalImageLen[IMAGE_LEN]; // the sum of all the following length - unsigned char cfeAddress[ADDRESS_LEN]; // if non zero, cfe starting address - unsigned char cfeLen[IMAGE_LEN]; // if non zero, cfe size in clear ASCII text. - unsigned char rootfsAddress[ADDRESS_LEN]; // if non zero, filesystem starting address - unsigned char rootfsLen[IMAGE_LEN]; // if non zero, filesystem size in clear ASCII text. - unsigned char kernelAddress[ADDRESS_LEN]; // if non zero, kernel starting address - unsigned char kernelLen[IMAGE_LEN]; // if non zero, kernel size in clear ASCII text. - unsigned char dualImage[FLAG_LEN]; // if 1, dual image - unsigned char inactiveLen[FLAG_LEN]; // if 1, the image is INACTIVE; if 0, active - unsigned char reserved[RESERVED_LEN]; // reserved for later use - unsigned char imageValidationToken[TOKEN_LEN];// image validation token - can be crc, md5, sha; for - // now will be 4 unsigned char crc - unsigned char tagValidationToken[TOKEN_LEN]; // validation token for tag(from signiture_1 to end of // mageValidationToken) -} FILE_TAG, *PFILE_TAG; - -#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */ -#define CRC_LEN 4 - -// only included if for bcmTag.exe program -#ifdef BCMTAG_EXE_USE - -static unsigned long Crc32_table[256] = { - 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, - 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, - 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, - 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, - 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, - 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, - 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, - 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, - 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, - 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, - 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, - 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, - 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, - 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F, - 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, - 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, - 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, - 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, - 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, - 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, - 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, - 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, - 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, - 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, - 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, - 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, - 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, - 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, - 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, - 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, - 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, - 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, - 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, - 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, - 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, - 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, - 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, - 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, - 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, - 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, - 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, - 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, - 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, - 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, - 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, - 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, - 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, - 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, - 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, - 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, - 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, - 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, - 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, - 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, - 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, - 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, - 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, - 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, - 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, - 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, - 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, - 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, - 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, - 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D -}; -#endif // BCMTAG_USE - - -#endif // _BCMTAG_H_ - diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcm_intr.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcm_intr.h deleted file mode 100644 index 8c56840f42..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcm_intr.h +++ /dev/null @@ -1,59 +0,0 @@ -/* -<:copyright-gpl - Copyright 2003 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -#ifndef __BCM_INTR_H -#define __BCM_INTR_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(CONFIG_BCM96338) -#include <6338_intr.h> -#endif -#if defined(CONFIG_BCM96345) -#include <6345_intr.h> -#endif -#if defined(CONFIG_BCM96348) -#include <6348_intr.h> -#endif - -/* defines */ -struct pt_regs; -typedef int (*FN_HANDLER) (int, void *); - -/* prototypes */ -extern void enable_brcm_irq(unsigned int irq); -extern void disable_brcm_irq(unsigned int irq); -extern int request_external_irq(unsigned int irq, - FN_HANDLER handler, unsigned long irqflags, - const char * devname, void *dev_id); -extern unsigned int BcmHalMapInterrupt(FN_HANDLER isr, unsigned int param, - unsigned int interruptId); -extern void dump_intr_regs(void); - -/* compatibility definitions */ -#define BcmHalInterruptEnable(irq) enable_brcm_irq( irq ) -#define BcmHalInterruptDisable(irq) disable_brcm_irq( irq ) - -#ifdef __cplusplus - } -#endif - -#endif diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcm_map_part.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcm_map_part.h deleted file mode 100644 index ccfe965dc3..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcm_map_part.h +++ /dev/null @@ -1,34 +0,0 @@ -/* -<:copyright-gpl - Copyright 2004 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -#ifndef __BCM_MAP_PART_H -#define __BCM_MAP_PART_H - -#if defined(CONFIG_BCM96338) -#include <6338_map_part.h> -#endif -#if defined(CONFIG_BCM96345) -#include <6345_map_part.h> -#endif -#if defined(CONFIG_BCM96348) -#include <6348_map_part.h> -#endif - -#endif - diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmpci.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmpci.h deleted file mode 100644 index cecbd995a4..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmpci.h +++ /dev/null @@ -1,87 +0,0 @@ -/* -<:copyright-gpl - Copyright 2004 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -// -// bcmpci.h - bcm96348 PCI, Cardbus, and PCMCIA definition -// -#ifndef BCMPCI_H -#define BCMPCI_H - -/* Memory window in internal system bus address space */ -#define BCM_PCI_MEM_BASE 0x08000000 -/* IO window in internal system bus address space */ -#define BCM_PCI_IO_BASE 0x0C000000 - -#define BCM_PCI_ADDR_MASK 0x1fffffff - -/* Memory window size (range) */ -#define BCM_PCI_MEM_SIZE_16MB 0x01000000 -/* IO window size (range) */ -#define BCM_PCI_IO_SIZE_64KB 0x00010000 - -/* PCI Configuration and I/O space acesss */ -#define BCM_PCI_CFG(d, f, o) ( (d << 11) | (f << 8) | (o/4 << 2) ) - -/* fake USB PCI slot */ -#define USB_HOST_SLOT 9 -#define USB_BAR0_MEM_SIZE 0x0800 - -#define BCM_HOST_MEM_SPACE1 0x10000000 -#define BCM_HOST_MEM_SPACE2 0x00000000 - -/* - * EBI bus clock is 33MHz and share with PCI bus - * each clock cycle is 30ns. - */ -/* attribute memory access wait cnt for 4306 */ -#define PCMCIA_ATTR_CE_HOLD 3 // data hold time 70ns -#define PCMCIA_ATTR_CE_SETUP 3 // data setup time 50ns -#define PCMCIA_ATTR_INACTIVE 6 // time between read/write cycles 180ns. For the total cycle time 600ns (cnt1+cnt2+cnt3+cnt4) -#define PCMCIA_ATTR_ACTIVE 10 // OE/WE pulse width 300ns - -/* common memory access wait cnt for 4306 */ -#define PCMCIA_MEM_CE_HOLD 1 // data hold time 30ns -#define PCMCIA_MEM_CE_SETUP 1 // data setup time 30ns -#define PCMCIA_MEM_INACTIVE 2 // time between read/write cycles 40ns. For the total cycle time 250ns (cnt1+cnt2+cnt3+cnt4) -#define PCMCIA_MEM_ACTIVE 5 // OE/WE pulse width 150ns - -#define PCCARD_VCC_MASK 0x00070000 // Mask Reset also -#define PCCARD_VCC_33V 0x00010000 -#define PCCARD_VCC_50V 0x00020000 - -typedef enum { - MPI_CARDTYPE_NONE, // No Card in slot - MPI_CARDTYPE_PCMCIA, // 16-bit PCMCIA card in slot - MPI_CARDTYPE_CARDBUS, // 32-bit CardBus card in slot -} CardType; - -#define CARDBUS_SLOT 0 // Slot 0 is default for CardBus - -#define pcmciaAttrOffset 0x00200000 -#define pcmciaMemOffset 0x00000000 -// Needs to be right above PCI I/O space. Give 0x8000 (32K) to PCMCIA. -#define pcmciaIoOffset (BCM_PCI_IO_BASE + 0x80000) -// Base Address is that mapped into the MPI ChipSelect registers. -// UBUS bridge MemoryWindow 0 outputs a 0x00 for the base. -#define pcmciaBase 0xbf000000 -#define pcmciaAttr (pcmciaAttrOffset | pcmciaBase) -#define pcmciaMem (pcmciaMemOffset | pcmciaBase) -#define pcmciaIo (pcmciaIoOffset | pcmciaBase) - -#endif diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmtypes.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmtypes.h deleted file mode 100644 index 43aebc9c06..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmtypes.h +++ /dev/null @@ -1,160 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ - -// -// bcmtypes.h - misc useful typedefs -// -#ifndef BCMTYPES_H -#define BCMTYPES_H - -// These are also defined in typedefs.h in the application area, so I need to -// protect against re-definition. - -#ifndef _TYPEDEFS_H_ -typedef unsigned char uint8; -typedef unsigned short uint16; -typedef unsigned long uint32; -typedef signed char int8; -typedef signed short int16; -typedef signed long int32; -#endif - -typedef unsigned char byte; -// typedef unsigned long sem_t; - -typedef unsigned long HANDLE,*PULONG,DWORD,*PDWORD; -typedef signed long LONG,*PLONG; - -typedef unsigned int *PUINT; -typedef signed int INT; - -typedef unsigned short *PUSHORT; -typedef signed short SHORT,*PSHORT; -typedef unsigned short WORD,*PWORD; - -typedef unsigned char *PUCHAR; -typedef signed char *PCHAR; - -typedef void *PVOID; - -typedef unsigned char BOOLEAN, *PBOOL, *PBOOLEAN; - -typedef unsigned char BYTE,*PBYTE; - -//#ifndef __GNUC__ -//The following has been defined in Vxworks internally: vxTypesOld.h -//redefine under vxworks will cause error -typedef signed int *PINT; - -typedef signed char INT8; -typedef signed short INT16; -typedef signed long INT32; - -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned long UINT32; - -typedef unsigned char UCHAR; -typedef unsigned short USHORT; -typedef unsigned int UINT; -typedef unsigned long ULONG; - -typedef void VOID; -typedef unsigned char BOOL; - -//#endif /* __GNUC__ */ - - -// These are also defined in typedefs.h in the application area, so I need to -// protect against re-definition. -#ifndef TYPEDEFS_H - -// Maximum and minimum values for a signed 16 bit integer. -#define MAX_INT16 32767 -#define MIN_INT16 -32768 - -// Useful for true/false return values. This uses the -// Taligent notation (k for constant). -typedef enum -{ - kFalse = 0, - kTrue = 1 -} Bool; - -#endif - -/* macros to protect against unaligned accesses */ - -#if 0 -/* first arg is an address, second is a value */ -#define PUT16( a, d ) { \ - *((byte *)a) = (byte)((d)>>8); \ - *(((byte *)a)+1) = (byte)(d); \ -} - -#define PUT32( a, d ) { \ - *((byte *)a) = (byte)((d)>>24); \ - *(((byte *)a)+1) = (byte)((d)>>16); \ - *(((byte *)a)+2) = (byte)((d)>>8); \ - *(((byte *)a)+3) = (byte)(d); \ -} - -/* first arg is an address, returns a value */ -#define GET16( a ) ( \ - (*((byte *)a) << 8) | \ - (*(((byte *)a)+1)) \ -) - -#define GET32( a ) ( \ - (*((byte *)a) << 24) | \ - (*(((byte *)a)+1) << 16) | \ - (*(((byte *)a)+2) << 8) | \ - (*(((byte *)a)+3)) \ -) -#endif - -#ifndef YES -#define YES 1 -#endif - -#ifndef NO -#define NO 0 -#endif - -#ifndef IN -#define IN -#endif - -#ifndef OUT -#define OUT -#endif - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#define READ32(addr) (*(volatile UINT32 *)((ULONG)&addr)) -#define READ16(addr) (*(volatile UINT16 *)((ULONG)&addr)) -#define READ8(addr) (*(volatile UINT8 *)((ULONG)&addr)) - -#endif diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/board.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/board.h deleted file mode 100644 index e674cb10d7..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/board.h +++ /dev/null @@ -1,373 +0,0 @@ -/* -<:copyright-gpl - Copyright 2002 Broadcom Corp. All Rights Reserved. - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as - published by the Free Software Foundation. - - This program is distributed in the hope it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -:> -*/ -/***********************************************************************/ -/* */ -/* MODULE: board.h */ -/* DATE: 97/02/18 */ -/* PURPOSE: Board specific information. This module should include */ -/* all base device addresses and board specific macros. */ -/* */ -/***********************************************************************/ -#ifndef _BOARD_H -#define _BOARD_H - -/*****************************************************************************/ -/* Misc board definitions */ -/*****************************************************************************/ - -#define DYING_GASP_API - -/*****************************************************************************/ -/* Physical Memory Map */ -/*****************************************************************************/ - -#define PHYS_DRAM_BASE 0x00000000 /* Dynamic RAM Base */ -#define PHYS_FLASH_BASE 0x1FC00000 /* Flash Memory */ - -/*****************************************************************************/ -/* Note that the addresses above are physical addresses and that programs */ -/* have to use converted addresses defined below: */ -/*****************************************************************************/ -#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */ -#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */ -#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */ - -/*****************************************************************************/ -/* Select the PLL value to get the desired CPU clock frequency. */ -/* */ -/* */ -/*****************************************************************************/ -#define FPERIPH 50000000 - -#define ONEK 1024 -#define BLK64K (64*ONEK) -#define FLASH45_BLKS_BOOT_ROM 1 -#define FLASH45_LENGTH_BOOT_ROM (FLASH45_BLKS_BOOT_ROM * BLK64K) -#define FLASH_RESERVED_AT_END (64*ONEK) /*reserved for PSI, scratch pad*/ - -/*****************************************************************************/ -/* Note that the addresses above are physical addresses and that programs */ -/* have to use converted addresses defined below: */ -/*****************************************************************************/ -#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */ -#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */ -#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */ - -/*****************************************************************************/ -/* Select the PLL value to get the desired CPU clock frequency. */ -/* */ -/* */ -/*****************************************************************************/ -#define FPERIPH 50000000 - -#define SDRAM_TYPE_ADDRESS_OFFSET 16 -#define NVRAM_DATA_OFFSET 0x0580 -#define NVRAM_DATA_ID 0x0f1e2d3c -#define BOARD_SDRAM_TYPE *(unsigned long *) \ - (FLASH_BASE + SDRAM_TYPE_ADDRESS_OFFSET) - -#define ONEK 1024 -#define BLK64K (64*ONEK) - -// nvram and psi flash definitions for 45 -#define FLASH45_LENGTH_NVRAM ONEK // 1k nvram -#define NVRAM_PSI_DEFAULT 24 // default psi in K byes - -/*****************************************************************************/ -/* NVRAM Offset and definition */ -/*****************************************************************************/ - -#define NVRAM_VERSION_NUMBER 2 -#define NVRAM_VERSION_NUMBER_ADDRESS 0 - -#define NVRAM_BOOTLINE_LEN 256 -#define NVRAM_BOARD_ID_STRING_LEN 16 -#define NVRAM_MAC_ADDRESS_LEN 6 -#define NVRAM_MAC_COUNT_MAX 32 - -/*****************************************************************************/ -/* Misc Offsets */ -/*****************************************************************************/ - -#define CFE_VERSION_OFFSET 0x0570 -#define CFE_VERSION_MARK_SIZE 5 -#define CFE_VERSION_SIZE 5 - -typedef struct -{ - unsigned long ulVersion; - char szBootline[NVRAM_BOOTLINE_LEN]; - char szBoardId[NVRAM_BOARD_ID_STRING_LEN]; - unsigned long ulReserved1[2]; - unsigned long ulNumMacAddrs; - unsigned char ucaBaseMacAddr[NVRAM_MAC_ADDRESS_LEN]; - char chReserved[2]; - unsigned long ulCheckSum; -} NVRAM_DATA, *PNVRAM_DATA; - - -/*****************************************************************************/ -/* board ioctl calls for flash, led and some other utilities */ -/*****************************************************************************/ - - -/* Defines. for board driver */ -#define BOARD_IOCTL_MAGIC 'B' -#define BOARD_DRV_MAJOR 206 - -#define MAC_ADDRESS_ANY (unsigned long) -1 - -#define BOARD_IOCTL_FLASH_INIT \ - _IOWR(BOARD_IOCTL_MAGIC, 0, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_FLASH_WRITE \ - _IOWR(BOARD_IOCTL_MAGIC, 1, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_FLASH_READ \ - _IOWR(BOARD_IOCTL_MAGIC, 2, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_NR_PAGES \ - _IOWR(BOARD_IOCTL_MAGIC, 3, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_DUMP_ADDR \ - _IOWR(BOARD_IOCTL_MAGIC, 4, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_SET_MEMORY \ - _IOWR(BOARD_IOCTL_MAGIC, 5, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_MIPS_SOFT_RESET \ - _IOWR(BOARD_IOCTL_MAGIC, 6, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_LED_CTRL \ - _IOWR(BOARD_IOCTL_MAGIC, 7, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_ID \ - _IOWR(BOARD_IOCTL_MAGIC, 8, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_MAC_ADDRESS \ - _IOWR(BOARD_IOCTL_MAGIC, 9, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_RELEASE_MAC_ADDRESS \ - _IOWR(BOARD_IOCTL_MAGIC, 10, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_PSI_SIZE \ - _IOWR(BOARD_IOCTL_MAGIC, 11, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_SDRAM_SIZE \ - _IOWR(BOARD_IOCTL_MAGIC, 12, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_SET_MONITOR_FD \ - _IOWR(BOARD_IOCTL_MAGIC, 13, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_WAKEUP_MONITOR_TASK \ - _IOWR(BOARD_IOCTL_MAGIC, 14, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_BOOTLINE \ - _IOWR(BOARD_IOCTL_MAGIC, 15, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_SET_BOOTLINE \ - _IOWR(BOARD_IOCTL_MAGIC, 16, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_BASE_MAC_ADDRESS \ - _IOWR(BOARD_IOCTL_MAGIC, 17, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_CHIP_ID \ - _IOWR(BOARD_IOCTL_MAGIC, 18, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_NUM_ENET \ - _IOWR(BOARD_IOCTL_MAGIC, 19, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_CFE_VER \ - _IOWR(BOARD_IOCTL_MAGIC, 20, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_ENET_CFG \ - _IOWR(BOARD_IOCTL_MAGIC, 21, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_WLAN_ANT_INUSE \ - _IOWR(BOARD_IOCTL_MAGIC, 22, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_SET_TRIGGER_EVENT \ - _IOWR(BOARD_IOCTL_MAGIC, 23, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_GET_TRIGGER_EVENT \ - _IOWR(BOARD_IOCTL_MAGIC, 24, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_UNSET_TRIGGER_EVENT \ - _IOWR(BOARD_IOCTL_MAGIC, 25, BOARD_IOCTL_PARMS) - -#define BOARD_IOCTL_SET_SES_LED \ - _IOWR(BOARD_IOCTL_MAGIC, 26, BOARD_IOCTL_PARMS) - -//<>JUNHON, 2004/09/15 - -// for the action in BOARD_IOCTL_PARMS for flash operation -typedef enum -{ - PERSISTENT, - NVRAM, - BCM_IMAGE_CFE, - BCM_IMAGE_FS, - BCM_IMAGE_KERNEL, - BCM_IMAGE_WHOLE, - SCRATCH_PAD, - FLASH_SIZE, -} BOARD_IOCTL_ACTION; - - -typedef struct boardIoctParms -{ - char *string; - char *buf; - int strLen; - int offset; - BOARD_IOCTL_ACTION action; /* flash read/write: nvram, persistent, bcm image */ - int result; -} BOARD_IOCTL_PARMS; - - -// LED defines -typedef enum -{ - kLedAdsl, - kLedWireless, - kLedUsb, - kLedHpna, - kLedWanData, - kLedPPP, - kLedVoip, - kLedSes, - kLedLan, - kLedSelfTest, - kLedEnd, // NOTE: Insert the new led name before this one. Alway stay at the end. -} BOARD_LED_NAME; - -typedef enum -{ - kLedStateOff, /* turn led off */ - kLedStateOn, /* turn led on */ - kLedStateFail, /* turn led on red */ - kLedStateBlinkOnce, /* blink once, ~100ms and ignore the same call during the 100ms period */ - kLedStateSlowBlinkContinues, /* slow blink continues at ~600ms interval */ - kLedStateFastBlinkContinues, /* fast blink continues at ~200ms interval */ -} BOARD_LED_STATE; - - -// virtual and physical map pair defined in board.c -typedef struct ledmappair -{ - BOARD_LED_NAME ledName; // virtual led name - BOARD_LED_STATE ledInitState; // initial led state when the board boots. - unsigned short ledMask; // physical GPIO pin mask - unsigned short ledActiveLow; // reset bit to turn on LED - unsigned short ledMaskFail; // physical GPIO pin mask for state failure - unsigned short ledActiveLowFail;// reset bit to turn on LED -} LED_MAP_PAIR, *PLED_MAP_PAIR; - -typedef void (*HANDLE_LED_FUNC)(BOARD_LED_NAME ledName, BOARD_LED_STATE ledState); - -/* Flash storage address information that is determined by the flash driver. */ -typedef struct flashaddrinfo -{ - int flash_persistent_start_blk; - int flash_persistent_number_blk; - int flash_persistent_length; - unsigned long flash_persistent_blk_offset; - int flash_scratch_pad_start_blk; // start before psi (SP_BUF_LEN) - int flash_scratch_pad_number_blk; - int flash_scratch_pad_length; - unsigned long flash_scratch_pad_blk_offset; - int flash_nvram_start_blk; - int flash_nvram_number_blk; - int flash_nvram_length; - unsigned long flash_nvram_blk_offset; -} FLASH_ADDR_INFO, *PFLASH_ADDR_INFO; - -// scratch pad defines -/* SP - Persisten Scratch Pad format: - sp header : 32 bytes - tokenId-1 : 8 bytes - tokenId-1 len : 4 bytes - tokenId-1 data - .... - tokenId-n : 8 bytes - tokenId-n len : 4 bytes - tokenId-n data -*/ - -#define MAGIC_NUM_LEN 8 -#define MAGIC_NUMBER "gOGoBrCm" -#define TOKEN_NAME_LEN 16 -#define SP_VERSION 1 -#define SP_MAX_LEN 8 * 1024 // 8k buf before psi -#define SP_RESERVERD 16 - -typedef struct _SP_HEADER -{ - char SPMagicNum[MAGIC_NUM_LEN]; // 8 bytes of magic number - int SPVersion; // version number - int SPUsedLen; // used sp len - char SPReserved[SP_RESERVERD]; // reservied, total 32 bytes -} SP_HEADER, *PSP_HEADER; - -typedef struct _TOKEN_DEF -{ - char tokenName[TOKEN_NAME_LEN]; - int tokenLen; -} SP_TOKEN, *PSP_TOKEN; - - -/*****************************************************************************/ -/* Function Prototypes */ -/*****************************************************************************/ -#if !defined(__ASM_ASM_H) -void dumpaddr( unsigned char *pAddr, int nLen ); - -int kerSysNvRamGet(char *string, int strLen, int offset); -int kerSysNvRamSet(char *string, int strLen, int offset); -int kerSysPersistentGet(char *string, int strLen, int offset); -int kerSysPersistentSet(char *string, int strLen, int offset); -int kerSysScratchPadGet(char *tokName, char *tokBuf, int tokLen); -int kerSysScratchPadSet(char *tokName, char *tokBuf, int tokLen); -int kerSysBcmImageSet( int flash_start_addr, char *string, int size); -int kerSysGetMacAddress( unsigned char *pucaAddr, unsigned long ulId ); -int kerSysReleaseMacAddress( unsigned char *pucaAddr ); -int kerSysGetSdramSize( void ); -void kerSysGetBootline(char *string, int strLen); -void kerSysSetBootline(char *string, int strLen); -void kerSysMipsSoftReset(void); -void kerSysLedCtrl(BOARD_LED_NAME, BOARD_LED_STATE); -void kerSysLedRegisterHwHandler( BOARD_LED_NAME, HANDLE_LED_FUNC, int ); -int kerSysFlashSizeGet(void); -void kerSysRegisterDyingGaspHandler(char *devname, void *cbfn, void *context); -void kerSysDeregisterDyingGaspHandler(char *devname); -void kerSysWakeupMonitorTask( void ); -#endif - -#define BOOT_CFE 0 -#define BOOT_REDBOOT 1 - -extern int boot_loader_type; - -#endif /* _BOARD_H */ - diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bootloaders.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bootloaders.h deleted file mode 100644 index e169bb00c0..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bootloaders.h +++ /dev/null @@ -1,7 +0,0 @@ -#define ADSL_SDRAM_IMAGE_SIZE (384*1024) - -#define BOOT_LOADER_UNKNOWN 0 -#define BOOT_LOADER_CFE 1 -#define BOOT_LOADER_REDBOOT 2 -#define BOOT_LOADER_CFE2 3 -#define BOOT_LOADER_LAST 3 diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/cpu-feature-overrides.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/cpu-feature-overrides.h deleted file mode 100644 index ea9b3587ad..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/cpu-feature-overrides.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H - -#define cpu_has_tlb 1 -#define cpu_has_4kex 4 -#define cpu_has_4ktlb 8 -#define cpu_has_fpu 0 -#define cpu_has_32fpr 0 -#define cpu_has_counter 0x40 -#define cpu_has_watch 0 -#define cpu_has_mips16 0 -#define cpu_has_divec 0x200 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 0x40000 -#define cpu_has_mcheck 0x2000 -#define cpu_has_ejtag 0x4000 -#define cpu_has_llsc 0x10000 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 0 -#define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 - -#define cpu_has_subset_pcaches 0 - -#define cpu_dcache_line_size() 16 -#define cpu_icache_line_size() 16 -#define cpu_scache_line_size() 0 - -#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/war.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/war.h deleted file mode 100644 index 0f09a31e67..0000000000 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MACH_BCM963XX_WAR_H -#define __ASM_MIPS_MACH_BCM963XX_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_BCM963XX_WAR_H */ diff --git a/target/linux/brcm63xx/files/include/linux/atmrt2684.h b/target/linux/brcm63xx/files/include/linux/atmrt2684.h deleted file mode 100644 index f138c643a2..0000000000 --- a/target/linux/brcm63xx/files/include/linux/atmrt2684.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef _LINUX_ATMRT2684_H -#define _LINUX_ATMRT2684_H - -#include -#include /* For IFNAMSIZ */ - -#define RT2684_ENCAPS_NULL (0) /* VC-mux */ -#define RT2684_ENCAPS_LLC (1) -#define RT2684_ENCAPS_AUTODETECT (2) /* Unsuported */ - -/* - * This is for the ATM_NEWBACKENDIF call - these are like socket families: - * the first element of the structure is the backend number and the rest - * is per-backend specific - */ -struct atm_newif_rt2684 { - atm_backend_t backend_num; /* ATM_BACKEND_RT2684 */ - char ifname[IFNAMSIZ]; -}; - -/* - * This structure is used to specify a rt2684 interface - either by a - * positive integer (returned by ATM_NEWBACKENDIF) or the interfaces name - */ -#define RT2684_FIND_BYNOTHING (0) -#define RT2684_FIND_BYNUM (1) -#define RT2684_FIND_BYIFNAME (2) -struct rt2684_if_spec { - int method; /* RT2684_FIND_* */ - union { - char ifname[IFNAMSIZ]; - int devnum; - } spec; -}; - -/* - * This is for the ATM_SETBACKEND call - these are like socket families: - * the first element of the structure is the backend number and the rest - * is per-backend specific - */ -struct atm_backend_rt2684 { - atm_backend_t backend_num; /* ATM_BACKEND_RT2684 */ - struct rt2684_if_spec ifspec; - unsigned char encaps; /* RT2684_ENCAPS_* */ -}; - - -#endif /* _LINUX_ATMRT2684_H */ diff --git a/target/linux/brcm63xx/image/Makefile b/target/linux/brcm63xx/image/Makefile deleted file mode 100644 index 47c1df730d..0000000000 --- a/target/linux/brcm63xx/image/Makefile +++ /dev/null @@ -1,78 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -LOADADDR = 0x80010000 # RAM start + 16M -KERNEL_ENTRY = $(LOADADDR) # Newer kernels add a jmp to the kernel_entry at the start of the binary -RAMSIZE = 0x01000000 # 64MB - -LOADER_MAKEOPTS= \ - KDIR=$(KDIR) \ - LOADADDR=$(LOADADDR) \ - KERNEL_ENTRY=$(KERNEL_ENTRY) \ - RAMSIZE=$(RAMSIZE) - -define trxalign/jffs2-128k --a 0x20000 -endef -define trxalign/jffs2-64k --a 0x10000 -endef -define trxalign/squashfs --a 1024 -endef - -define Image/Build/CFE - # Generate the tagged image - $(STAGING_DIR_HOST)/bin/imagetag -i $(KDIR)/vmlinux.lzma.cfe -f $(KDIR)/root.$(1) \ - -o $(BIN_DIR)/openwrt-$(2)-$(1)-cfe.bin \ - -b $(2) -c $(3) -e $(LOADADDR) -l $(LOADADDR) -# -b $(2) -c $(3) -e $(KERNEL_ENTRY) -l $(LOADADDR) - - $(call prepare_generic_squashfs,$(BIN_DIR)/openwrt-$(2)-$(1)-cfe.bin) -endef - -define Build/Clean - $(MAKE) -C lzma-loader clean -endef - -define Image/Prepare - # Standard LZMA kernel - cat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma - - # CFE is a LZMA nazi! It took me hours to find out the parameters! - # Also I think lzma has a bug cause it generates different output depending on - # if you use stdin / stdout or not. Use files instead of stdio here, cause - # otherwise CFE will complain and not boot the image. - $(STAGING_DIR_HOST)/bin/lzma e -d22 -fb64 -a1 $(KDIR)/vmlinux $(KDIR)/vmlinux.lzma.tmp - - # Strip out the length, CFE doesn't like this - dd if=$(KDIR)/vmlinux.lzma.tmp of=$(KDIR)/vmlinux.lzma.cfe bs=5 count=1 - dd if=$(KDIR)/vmlinux.lzma.tmp of=$(KDIR)/vmlinux.lzma.cfe ibs=13 obs=5 skip=1 seek=1 conv=notrunc - rm -f $(KDIR)/vmlinux.lzma.tmp - - # Build the LZMA loader - rm -f $(KDIR)/loader.gz - $(MAKE) -C lzma-loader \ - BUILD_DIR="$(KDIR)" \ - TARGET="$(KDIR)" \ - clean install - - echo -ne "\\x00" >> $(KDIR)/loader.gz - rm -f $(KDIR)/fs_mark - touch $(KDIR)/fs_mark - $(call prepare_generic_squashfs,$(KDIR)/fs_mark) - -endef - -define Image/Build - $(STAGING_DIR_HOST)/bin/trx -o $(BIN_DIR)/openwrt-$(BOARD)-$(1).trx -f $(KDIR)/loader.gz -f $(KDIR)/vmlinux.lzma $(call trxalign/$(1)) -f $(KDIR)/root.$(1) - $(call Image/Build/CFE,$(1),96345GW2,6345) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/brcm63xx/image/lzma-loader/Makefile b/target/linux/brcm63xx/image/lzma-loader/Makefile deleted file mode 100644 index b56cbaab0f..0000000000 --- a/target/linux/brcm63xx/image/lzma-loader/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -# $Id$ - -include $(TOPDIR)/rules.mk - -PKG_NAME := lzma-loader -PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME) - -$(PKG_BUILD_DIR)/.prepared: - mkdir $(PKG_BUILD_DIR) - $(CP) ./src/* $(PKG_BUILD_DIR)/ - touch $@ - -$(PKG_BUILD_DIR)/loader.gz: $(PKG_BUILD_DIR)/.prepared - $(MAKE) -C $(PKG_BUILD_DIR) CC="$(TARGET_CC)" \ - LD="$(TARGET_CROSS)ld" CROSS_COMPILE="$(TARGET_CROSS)" - -download: -prepare: $(PKG_BUILD_DIR)/.prepared -compile: $(PKG_BUILD_DIR)/loader.gz -install: - -ifneq ($(TARGET),) -install: compile - $(CP) $(PKG_BUILD_DIR)/loader.gz $(PKG_BUILD_DIR)/loader.elf $(TARGET)/ -endif - -clean: - rm -rf $(PKG_BUILD_DIR) diff --git a/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.c b/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.c deleted file mode 100644 index 951700bddf..0000000000 --- a/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.c +++ /dev/null @@ -1,663 +0,0 @@ -/* - LzmaDecode.c - LZMA Decoder - - LZMA SDK 4.05 Copyright (c) 1999-2004 Igor Pavlov (2004-08-25) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#include "LzmaDecode.h" - -#ifndef Byte -#define Byte unsigned char -#endif - -#define kNumTopBits 24 -#define kTopValue ((UInt32)1 << kNumTopBits) - -#define kNumBitModelTotalBits 11 -#define kBitModelTotal (1 << kNumBitModelTotalBits) -#define kNumMoveBits 5 - -typedef struct _CRangeDecoder -{ - Byte *Buffer; - Byte *BufferLim; - UInt32 Range; - UInt32 Code; - #ifdef _LZMA_IN_CB - ILzmaInCallback *InCallback; - int Result; - #endif - int ExtraBytes; -} CRangeDecoder; - -Byte RangeDecoderReadByte(CRangeDecoder *rd) -{ - if (rd->Buffer == rd->BufferLim) - { - #ifdef _LZMA_IN_CB - UInt32 size; - rd->Result = rd->InCallback->Read(rd->InCallback, &rd->Buffer, &size); - rd->BufferLim = rd->Buffer + size; - if (size == 0) - #endif - { - rd->ExtraBytes = 1; - return 0xFF; - } - } - return (*rd->Buffer++); -} - -/* #define ReadByte (*rd->Buffer++) */ -#define ReadByte (RangeDecoderReadByte(rd)) - -void RangeDecoderInit(CRangeDecoder *rd, - #ifdef _LZMA_IN_CB - ILzmaInCallback *inCallback - #else - Byte *stream, UInt32 bufferSize - #endif - ) -{ - int i; - #ifdef _LZMA_IN_CB - rd->InCallback = inCallback; - rd->Buffer = rd->BufferLim = 0; - #else - rd->Buffer = stream; - rd->BufferLim = stream + bufferSize; - #endif - rd->ExtraBytes = 0; - rd->Code = 0; - rd->Range = (0xFFFFFFFF); - for(i = 0; i < 5; i++) - rd->Code = (rd->Code << 8) | ReadByte; -} - -#define RC_INIT_VAR UInt32 range = rd->Range; UInt32 code = rd->Code; -#define RC_FLUSH_VAR rd->Range = range; rd->Code = code; -#define RC_NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | ReadByte; } - -UInt32 RangeDecoderDecodeDirectBits(CRangeDecoder *rd, int numTotalBits) -{ - RC_INIT_VAR - UInt32 result = 0; - int i; - for (i = numTotalBits; i > 0; i--) - { - /* UInt32 t; */ - range >>= 1; - - result <<= 1; - if (code >= range) - { - code -= range; - result |= 1; - } - /* - t = (code - range) >> 31; - t &= 1; - code -= range & (t - 1); - result = (result + result) | (1 - t); - */ - RC_NORMALIZE - } - RC_FLUSH_VAR - return result; -} - -int RangeDecoderBitDecode(CProb *prob, CRangeDecoder *rd) -{ - UInt32 bound = (rd->Range >> kNumBitModelTotalBits) * *prob; - if (rd->Code < bound) - { - rd->Range = bound; - *prob += (kBitModelTotal - *prob) >> kNumMoveBits; - if (rd->Range < kTopValue) - { - rd->Code = (rd->Code << 8) | ReadByte; - rd->Range <<= 8; - } - return 0; - } - else - { - rd->Range -= bound; - rd->Code -= bound; - *prob -= (*prob) >> kNumMoveBits; - if (rd->Range < kTopValue) - { - rd->Code = (rd->Code << 8) | ReadByte; - rd->Range <<= 8; - } - return 1; - } -} - -#define RC_GET_BIT2(prob, mi, A0, A1) \ - UInt32 bound = (range >> kNumBitModelTotalBits) * *prob; \ - if (code < bound) \ - { A0; range = bound; *prob += (kBitModelTotal - *prob) >> kNumMoveBits; mi <<= 1; } \ - else \ - { A1; range -= bound; code -= bound; *prob -= (*prob) >> kNumMoveBits; mi = (mi + mi) + 1; } \ - RC_NORMALIZE - -#define RC_GET_BIT(prob, mi) RC_GET_BIT2(prob, mi, ; , ;) - -int RangeDecoderBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder *rd) -{ - int mi = 1; - int i; - #ifdef _LZMA_LOC_OPT - RC_INIT_VAR - #endif - for(i = numLevels; i > 0; i--) - { - #ifdef _LZMA_LOC_OPT - CProb *prob = probs + mi; - RC_GET_BIT(prob, mi) - #else - mi = (mi + mi) + RangeDecoderBitDecode(probs + mi, rd); - #endif - } - #ifdef _LZMA_LOC_OPT - RC_FLUSH_VAR - #endif - return mi - (1 << numLevels); -} - -int RangeDecoderReverseBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder *rd) -{ - int mi = 1; - int i; - int symbol = 0; - #ifdef _LZMA_LOC_OPT - RC_INIT_VAR - #endif - for(i = 0; i < numLevels; i++) - { - #ifdef _LZMA_LOC_OPT - CProb *prob = probs + mi; - RC_GET_BIT2(prob, mi, ; , symbol |= (1 << i)) - #else - int bit = RangeDecoderBitDecode(probs + mi, rd); - mi = mi + mi + bit; - symbol |= (bit << i); - #endif - } - #ifdef _LZMA_LOC_OPT - RC_FLUSH_VAR - #endif - return symbol; -} - -Byte LzmaLiteralDecode(CProb *probs, CRangeDecoder *rd) -{ - int symbol = 1; - #ifdef _LZMA_LOC_OPT - RC_INIT_VAR - #endif - do - { - #ifdef _LZMA_LOC_OPT - CProb *prob = probs + symbol; - RC_GET_BIT(prob, symbol) - #else - symbol = (symbol + symbol) | RangeDecoderBitDecode(probs + symbol, rd); - #endif - } - while (symbol < 0x100); - #ifdef _LZMA_LOC_OPT - RC_FLUSH_VAR - #endif - return symbol; -} - -Byte LzmaLiteralDecodeMatch(CProb *probs, CRangeDecoder *rd, Byte matchByte) -{ - int symbol = 1; - #ifdef _LZMA_LOC_OPT - RC_INIT_VAR - #endif - do - { - int bit; - int matchBit = (matchByte >> 7) & 1; - matchByte <<= 1; - #ifdef _LZMA_LOC_OPT - { - CProb *prob = probs + ((1 + matchBit) << 8) + symbol; - RC_GET_BIT2(prob, symbol, bit = 0, bit = 1) - } - #else - bit = RangeDecoderBitDecode(probs + ((1 + matchBit) << 8) + symbol, rd); - symbol = (symbol << 1) | bit; - #endif - if (matchBit != bit) - { - while (symbol < 0x100) - { - #ifdef _LZMA_LOC_OPT - CProb *prob = probs + symbol; - RC_GET_BIT(prob, symbol) - #else - symbol = (symbol + symbol) | RangeDecoderBitDecode(probs + symbol, rd); - #endif - } - break; - } - } - while (symbol < 0x100); - #ifdef _LZMA_LOC_OPT - RC_FLUSH_VAR - #endif - return symbol; -} - -#define kNumPosBitsMax 4 -#define kNumPosStatesMax (1 << kNumPosBitsMax) - -#define kLenNumLowBits 3 -#define kLenNumLowSymbols (1 << kLenNumLowBits) -#define kLenNumMidBits 3 -#define kLenNumMidSymbols (1 << kLenNumMidBits) -#define kLenNumHighBits 8 -#define kLenNumHighSymbols (1 << kLenNumHighBits) - -#define LenChoice 0 -#define LenChoice2 (LenChoice + 1) -#define LenLow (LenChoice2 + 1) -#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) -#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) - -int LzmaLenDecode(CProb *p, CRangeDecoder *rd, int posState) -{ - if(RangeDecoderBitDecode(p + LenChoice, rd) == 0) - return RangeDecoderBitTreeDecode(p + LenLow + - (posState << kLenNumLowBits), kLenNumLowBits, rd); - if(RangeDecoderBitDecode(p + LenChoice2, rd) == 0) - return kLenNumLowSymbols + RangeDecoderBitTreeDecode(p + LenMid + - (posState << kLenNumMidBits), kLenNumMidBits, rd); - return kLenNumLowSymbols + kLenNumMidSymbols + - RangeDecoderBitTreeDecode(p + LenHigh, kLenNumHighBits, rd); -} - -#define kNumStates 12 - -#define kStartPosModelIndex 4 -#define kEndPosModelIndex 14 -#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) - -#define kNumPosSlotBits 6 -#define kNumLenToPosStates 4 - -#define kNumAlignBits 4 -#define kAlignTableSize (1 << kNumAlignBits) - -#define kMatchMinLen 2 - -#define IsMatch 0 -#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) -#define IsRepG0 (IsRep + kNumStates) -#define IsRepG1 (IsRepG0 + kNumStates) -#define IsRepG2 (IsRepG1 + kNumStates) -#define IsRep0Long (IsRepG2 + kNumStates) -#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) -#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) -#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) -#define LenCoder (Align + kAlignTableSize) -#define RepLenCoder (LenCoder + kNumLenProbs) -#define Literal (RepLenCoder + kNumLenProbs) - -#if Literal != LZMA_BASE_SIZE -StopCompilingDueBUG -#endif - -#ifdef _LZMA_OUT_READ - -typedef struct _LzmaVarState -{ - CRangeDecoder RangeDecoder; - Byte *Dictionary; - UInt32 DictionarySize; - UInt32 DictionaryPos; - UInt32 GlobalPos; - UInt32 Reps[4]; - int lc; - int lp; - int pb; - int State; - int PreviousIsMatch; - int RemainLen; -} LzmaVarState; - -int LzmaDecoderInit( - unsigned char *buffer, UInt32 bufferSize, - int lc, int lp, int pb, - unsigned char *dictionary, UInt32 dictionarySize, - #ifdef _LZMA_IN_CB - ILzmaInCallback *inCallback - #else - unsigned char *inStream, UInt32 inSize - #endif - ) -{ - LzmaVarState *vs = (LzmaVarState *)buffer; - CProb *p = (CProb *)(buffer + sizeof(LzmaVarState)); - UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + lp)); - UInt32 i; - if (bufferSize < numProbs * sizeof(CProb) + sizeof(LzmaVarState)) - return LZMA_RESULT_NOT_ENOUGH_MEM; - vs->Dictionary = dictionary; - vs->DictionarySize = dictionarySize; - vs->DictionaryPos = 0; - vs->GlobalPos = 0; - vs->Reps[0] = vs->Reps[1] = vs->Reps[2] = vs->Reps[3] = 1; - vs->lc = lc; - vs->lp = lp; - vs->pb = pb; - vs->State = 0; - vs->PreviousIsMatch = 0; - vs->RemainLen = 0; - dictionary[dictionarySize - 1] = 0; - for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - RangeDecoderInit(&vs->RangeDecoder, - #ifdef _LZMA_IN_CB - inCallback - #else - inStream, inSize - #endif - ); - return LZMA_RESULT_OK; -} - -int LzmaDecode(unsigned char *buffer, - unsigned char *outStream, UInt32 outSize, - UInt32 *outSizeProcessed) -{ - LzmaVarState *vs = (LzmaVarState *)buffer; - CProb *p = (CProb *)(buffer + sizeof(LzmaVarState)); - CRangeDecoder rd = vs->RangeDecoder; - int state = vs->State; - int previousIsMatch = vs->PreviousIsMatch; - Byte previousByte; - UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; - UInt32 nowPos = 0; - UInt32 posStateMask = (1 << (vs->pb)) - 1; - UInt32 literalPosMask = (1 << (vs->lp)) - 1; - int lc = vs->lc; - int len = vs->RemainLen; - UInt32 globalPos = vs->GlobalPos; - - Byte *dictionary = vs->Dictionary; - UInt32 dictionarySize = vs->DictionarySize; - UInt32 dictionaryPos = vs->DictionaryPos; - - if (len == -1) - { - *outSizeProcessed = 0; - return LZMA_RESULT_OK; - } - - while(len > 0 && nowPos < outSize) - { - UInt32 pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - len--; - } - if (dictionaryPos == 0) - previousByte = dictionary[dictionarySize - 1]; - else - previousByte = dictionary[dictionaryPos - 1]; -#else - -int LzmaDecode( - Byte *buffer, UInt32 bufferSize, - int lc, int lp, int pb, - #ifdef _LZMA_IN_CB - ILzmaInCallback *inCallback, - #else - unsigned char *inStream, UInt32 inSize, - #endif - unsigned char *outStream, UInt32 outSize, - UInt32 *outSizeProcessed) -{ - UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + lp)); - CProb *p = (CProb *)buffer; - CRangeDecoder rd; - UInt32 i; - int state = 0; - int previousIsMatch = 0; - Byte previousByte = 0; - UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; - UInt32 nowPos = 0; - UInt32 posStateMask = (1 << pb) - 1; - UInt32 literalPosMask = (1 << lp) - 1; - int len = 0; - if (bufferSize < numProbs * sizeof(CProb)) - return LZMA_RESULT_NOT_ENOUGH_MEM; - for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - RangeDecoderInit(&rd, - #ifdef _LZMA_IN_CB - inCallback - #else - inStream, inSize - #endif - ); -#endif - - *outSizeProcessed = 0; - while(nowPos < outSize) - { - int posState = (int)( - (nowPos - #ifdef _LZMA_OUT_READ - + globalPos - #endif - ) - & posStateMask); - #ifdef _LZMA_IN_CB - if (rd.Result != LZMA_RESULT_OK) - return rd.Result; - #endif - if (rd.ExtraBytes != 0) - return LZMA_RESULT_DATA_ERROR; - if (RangeDecoderBitDecode(p + IsMatch + (state << kNumPosBitsMax) + posState, &rd) == 0) - { - CProb *probs = p + Literal + (LZMA_LIT_SIZE * - ((( - (nowPos - #ifdef _LZMA_OUT_READ - + globalPos - #endif - ) - & literalPosMask) << lc) + (previousByte >> (8 - lc)))); - - if (state < 4) state = 0; - else if (state < 10) state -= 3; - else state -= 6; - if (previousIsMatch) - { - Byte matchByte; - #ifdef _LZMA_OUT_READ - UInt32 pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - matchByte = dictionary[pos]; - #else - matchByte = outStream[nowPos - rep0]; - #endif - previousByte = LzmaLiteralDecodeMatch(probs, &rd, matchByte); - previousIsMatch = 0; - } - else - previousByte = LzmaLiteralDecode(probs, &rd); - outStream[nowPos++] = previousByte; - #ifdef _LZMA_OUT_READ - dictionary[dictionaryPos] = previousByte; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - #endif - } - else - { - previousIsMatch = 1; - if (RangeDecoderBitDecode(p + IsRep + state, &rd) == 1) - { - if (RangeDecoderBitDecode(p + IsRepG0 + state, &rd) == 0) - { - if (RangeDecoderBitDecode(p + IsRep0Long + (state << kNumPosBitsMax) + posState, &rd) == 0) - { - #ifdef _LZMA_OUT_READ - UInt32 pos; - #endif - if ( - (nowPos - #ifdef _LZMA_OUT_READ - + globalPos - #endif - ) - == 0) - return LZMA_RESULT_DATA_ERROR; - state = state < 7 ? 9 : 11; - #ifdef _LZMA_OUT_READ - pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - previousByte = dictionary[pos]; - dictionary[dictionaryPos] = previousByte; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - #else - previousByte = outStream[nowPos - rep0]; - #endif - outStream[nowPos++] = previousByte; - continue; - } - } - else - { - UInt32 distance; - if(RangeDecoderBitDecode(p + IsRepG1 + state, &rd) == 0) - distance = rep1; - else - { - if(RangeDecoderBitDecode(p + IsRepG2 + state, &rd) == 0) - distance = rep2; - else - { - distance = rep3; - rep3 = rep2; - } - rep2 = rep1; - } - rep1 = rep0; - rep0 = distance; - } - len = LzmaLenDecode(p + RepLenCoder, &rd, posState); - state = state < 7 ? 8 : 11; - } - else - { - int posSlot; - rep3 = rep2; - rep2 = rep1; - rep1 = rep0; - state = state < 7 ? 7 : 10; - len = LzmaLenDecode(p + LenCoder, &rd, posState); - posSlot = RangeDecoderBitTreeDecode(p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << - kNumPosSlotBits), kNumPosSlotBits, &rd); - if (posSlot >= kStartPosModelIndex) - { - int numDirectBits = ((posSlot >> 1) - 1); - rep0 = ((2 | ((UInt32)posSlot & 1)) << numDirectBits); - if (posSlot < kEndPosModelIndex) - { - rep0 += RangeDecoderReverseBitTreeDecode( - p + SpecPos + rep0 - posSlot - 1, numDirectBits, &rd); - } - else - { - rep0 += RangeDecoderDecodeDirectBits(&rd, - numDirectBits - kNumAlignBits) << kNumAlignBits; - rep0 += RangeDecoderReverseBitTreeDecode(p + Align, kNumAlignBits, &rd); - } - } - else - rep0 = posSlot; - rep0++; - } - if (rep0 == (UInt32)(0)) - { - /* it's for stream version */ - len = -1; - break; - } - if (rep0 > nowPos - #ifdef _LZMA_OUT_READ - + globalPos - #endif - ) - { - return LZMA_RESULT_DATA_ERROR; - } - len += kMatchMinLen; - do - { - #ifdef _LZMA_OUT_READ - UInt32 pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - previousByte = dictionary[pos]; - dictionary[dictionaryPos] = previousByte; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - #else - previousByte = outStream[nowPos - rep0]; - #endif - outStream[nowPos++] = previousByte; - len--; - } - while(len > 0 && nowPos < outSize); - } - } - - #ifdef _LZMA_OUT_READ - vs->RangeDecoder = rd; - vs->DictionaryPos = dictionaryPos; - vs->GlobalPos = globalPos + nowPos; - vs->Reps[0] = rep0; - vs->Reps[1] = rep1; - vs->Reps[2] = rep2; - vs->Reps[3] = rep3; - vs->State = state; - vs->PreviousIsMatch = previousIsMatch; - vs->RemainLen = len; - #endif - - *outSizeProcessed = nowPos; - return LZMA_RESULT_OK; -} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.h b/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.h deleted file mode 100644 index f58944e3c3..0000000000 --- a/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - LzmaDecode.h - LZMA Decoder interface - - LZMA SDK 4.05 Copyright (c) 1999-2004 Igor Pavlov (2004-08-25) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#ifndef __LZMADECODE_H -#define __LZMADECODE_H - -/* #define _LZMA_IN_CB */ -/* Use callback for input data */ - -/* #define _LZMA_OUT_READ */ -/* Use read function for output data */ - -/* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, - but memory usage will be doubled in that case */ - -/* #define _LZMA_LOC_OPT */ -/* Enable local speed optimizations inside code */ - -#ifndef UInt32 -#ifdef _LZMA_UINT32_IS_ULONG -#define UInt32 unsigned long -#else -#define UInt32 unsigned int -#endif -#endif - -#ifdef _LZMA_PROB32 -#define CProb UInt32 -#else -#define CProb unsigned short -#endif - -#define LZMA_RESULT_OK 0 -#define LZMA_RESULT_DATA_ERROR 1 -#define LZMA_RESULT_NOT_ENOUGH_MEM 2 - -#ifdef _LZMA_IN_CB -typedef struct _ILzmaInCallback -{ - int (*Read)(void *object, unsigned char **buffer, UInt32 *bufferSize); -} ILzmaInCallback; -#endif - -#define LZMA_BASE_SIZE 1846 -#define LZMA_LIT_SIZE 768 - -/* -bufferSize = (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp)))* sizeof(CProb) -bufferSize += 100 in case of _LZMA_OUT_READ -by default CProb is unsigned short, -but if specify _LZMA_PROB_32, CProb will be UInt32(unsigned int) -*/ - -#ifdef _LZMA_OUT_READ -int LzmaDecoderInit( - unsigned char *buffer, UInt32 bufferSize, - int lc, int lp, int pb, - unsigned char *dictionary, UInt32 dictionarySize, - #ifdef _LZMA_IN_CB - ILzmaInCallback *inCallback - #else - unsigned char *inStream, UInt32 inSize - #endif -); -#endif - -int LzmaDecode( - unsigned char *buffer, - #ifndef _LZMA_OUT_READ - UInt32 bufferSize, - int lc, int lp, int pb, - #ifdef _LZMA_IN_CB - ILzmaInCallback *inCallback, - #else - unsigned char *inStream, UInt32 inSize, - #endif - #endif - unsigned char *outStream, UInt32 outSize, - UInt32 *outSizeProcessed); - -#endif diff --git a/target/linux/brcm63xx/image/lzma-loader/src/Makefile b/target/linux/brcm63xx/image/lzma-loader/src/Makefile deleted file mode 100644 index 83e2c52386..0000000000 --- a/target/linux/brcm63xx/image/lzma-loader/src/Makefile +++ /dev/null @@ -1,77 +0,0 @@ -# -# Makefile for Broadcom BCM947XX boards -# -# Copyright 2001-2003, Broadcom Corporation -# All Rights Reserved. -# -# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY -# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM -# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS -# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. -# -# Copyright 2004 Manuel Novoa III -# Modified to support bzip'd kernels. -# Of course, it would be better to integrate bunzip capability into CFE. -# -# Copyright 2005 Oleg I. Vdovikin -# Cleaned up, modified for lzma support, removed from kernel -# - -TEXT_START := 0x80010000 -BZ_TEXT_START := 0x80300000 - -OBJCOPY := $(CROSS_COMPILE)objcopy -O binary -R .reginfo -R .note -R .comment -R .mdebug -S - -CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ - -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 -mno-abicalls -fno-pic \ - -ffunction-sections -pipe -mlong-calls -fno-common \ - -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap -CFLAGS += -DLOADADDR=$(TEXT_START) -D_LZMA_IN_CB - -ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ -DBZ_TEXT_START=$(BZ_TEXT_START) - -SEDFLAGS := s/BZ_TEXT_START/$(BZ_TEXT_START)/;s/TEXT_START/$(TEXT_START)/ - -OBJECTS := head.o data.o - -all: loader.gz loader.elf - -# Don't build dependencies, this may die if $(CC) isn't gcc -dep: - -install: - -loader.gz: loader - gzip -nc9 $< > $@ - -loader.elf: loader.o - cp $< $@ - -loader: loader.o - $(OBJCOPY) $< $@ - -loader.o: loader.lds $(OBJECTS) - $(LD) -static --gc-sections -no-warn-mismatch -T loader.lds -o $@ $(OBJECTS) - -loader.lds: loader.lds.in Makefile - @sed "$(SEDFLAGS)" < $< > $@ - -data.o: data.lds decompress.image - $(LD) -no-warn-mismatch -T data.lds -r -o $@ -b binary decompress.image -b elf32-tradlittlemips - -data.lds: - @echo "SECTIONS { .data : { code_start = .; *(.data) code_stop = .; }}" > $@ - -decompress.image: decompress - $(OBJCOPY) $< $@ - -decompress: decompress.lds decompress.o LzmaDecode.o - $(LD) -static --gc-sections -no-warn-mismatch -T decompress.lds -o $@ decompress.o LzmaDecode.o - -decompress.lds: decompress.lds.in Makefile - @sed "$(SEDFLAGS)" < $< > $@ - -mrproper: clean - -clean: - rm -f loader.gz loader decompress *.lds *.o *.image diff --git a/target/linux/brcm63xx/image/lzma-loader/src/README b/target/linux/brcm63xx/image/lzma-loader/src/README deleted file mode 100644 index 16649e9500..0000000000 --- a/target/linux/brcm63xx/image/lzma-loader/src/README +++ /dev/null @@ -1,55 +0,0 @@ -/* - * LZMA compressed kernel decompressor for bcm947xx boards - * - * Copyright (C) 2005 by Oleg I. Vdovikin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -The code is intended to decompress kernel, being compressed using lzma utility -build using 7zip LZMA SDK. This utility is located in the LZMA_Alone directory - -decompressor code expects that your .trx file consist of three partitions: - -1) decompressor itself (this is gziped code which pmon/cfe will extract and run -on boot-up instead of real kernel) -2) LZMA compressed kernel (both streamed and regular modes are supported now) -3) Root filesystem - -Please be sure to apply the following patch for use this new trx layout (it will -allow using both new and old trx files for root filesystem lookup code) - ---- linuz/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:24:27.503322896 +0300 -+++ linux/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:29:05.237100944 +0300 -@@ -221,7 +221,9 @@ - /* Try looking at TRX header for rootfs offset */ - if (le32_to_cpu(trx->magic) == TRX_MAGIC) { - bcm947xx_parts[1].offset = off; -- if (le32_to_cpu(trx->offsets[1]) > off) -+ if (le32_to_cpu(trx->offsets[2]) > off) -+ off = le32_to_cpu(trx->offsets[2]); -+ else if (le32_to_cpu(trx->offsets[1]) > off) - off = le32_to_cpu(trx->offsets[1]); - continue; - } - - -Revision history: - 0.02 Initial release - 0.03 Added Mineharu Takahara patch to pass actual - output size to decoder (stream mode compressed input is not - a requirement anymore) - 0.04 Reordered functions using lds script diff --git a/target/linux/brcm63xx/image/lzma-loader/src/decompress.c b/target/linux/brcm63xx/image/lzma-loader/src/decompress.c deleted file mode 100644 index ec510e21e3..0000000000 --- a/target/linux/brcm63xx/image/lzma-loader/src/decompress.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * LZMA compressed kernel decompressor for bcm947xx boards - * - * Copyright (C) 2005 by Oleg I. Vdovikin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * - * Please note, this was code based on the bunzip2 decompressor code - * by Manuel Novoa III (mjn3@codepoet.org), although the only thing left - * is an idea and part of original vendor code - * - * - * 12-Mar-2005 Mineharu Takahara - * pass actual output size to decoder (stream mode - * compressed input is not a requirement anymore) - * - * 24-Apr-2005 Oleg I. Vdovikin - * reordered functions using lds script, removed forward decl - * - */ - -#include "LzmaDecode.h" - -#define BCM4710_FLASH 0x1fc00000 /* Flash */ - -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 - -#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1) - -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 - -#define cache_unroll(base,op) \ - __asm__ __volatile__( \ - ".set noreorder;\n" \ - ".set mips3;\n" \ - "cache %1, (%0);\n" \ - ".set mips0;\n" \ - ".set reorder\n" \ - : \ - : "r" (base), \ - "i" (op)); - -static __inline__ void blast_icache(unsigned long size, unsigned long lsize) -{ - unsigned long start = KSEG0; - unsigned long end = (start + size); - - while(start < end) { - cache_unroll(start,Index_Invalidate_I); - start += lsize; - } -} - -static __inline__ void blast_dcache(unsigned long size, unsigned long lsize) -{ - unsigned long start = KSEG0; - unsigned long end = (start + size); - - while(start < end) { - cache_unroll(start,Index_Writeback_Inv_D); - start += lsize; - } -} - -#define TRX_MAGIC 0x30524448 /* "HDR0" */ - -struct trx_header { - unsigned int magic; /* "HDR0" */ - unsigned int len; /* Length of file including header */ - unsigned int crc32; /* 32-bit CRC from flag_version to end of file */ - unsigned int flag_version; /* 0:15 flags, 16:31 version */ - unsigned int offsets[3]; /* Offsets of partitions from start of header */ -}; - -/* beyound the image end, size not known in advance */ -extern unsigned char workspace[]; - -unsigned int offset; -unsigned char *data; - -/* flash access should be aligned, so wrapper is used */ -/* read byte from the flash, all accesses are 32-bit aligned */ -static int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize) -{ - static unsigned int val; - - if (((unsigned int)offset % 4) == 0) { - val = *(unsigned int *)data; - data += 4; - } - - *bufferSize = 1; - *buffer = ((unsigned char *)&val) + (offset++ & 3); - - return LZMA_RESULT_OK; -} - -static __inline__ unsigned char get_byte(void) -{ - unsigned char *buffer; - UInt32 fake; - - return read_byte(0, &buffer, &fake), *buffer; -} - -/* should be the first function */ -void entry(unsigned long icache_size, unsigned long icache_lsize, - unsigned long dcache_size, unsigned long dcache_lsize) -{ - unsigned int i; /* temp value */ - unsigned int lc; /* literal context bits */ - unsigned int lp; /* literal pos state bits */ - unsigned int pb; /* pos state bits */ - unsigned int osize; /* uncompressed size */ - - ILzmaInCallback callback; - callback.Read = read_byte; - - /* look for trx header, 32-bit data access */ - for (data = ((unsigned char *) KSEG1ADDR(BCM4710_FLASH)); - ((struct trx_header *)data)->magic != TRX_MAGIC; data += 65536); - - /* compressed kernel is in the partition 0 or 1 */ - if (((struct trx_header *)data)->offsets[1] > 65536) - data += ((struct trx_header *)data)->offsets[0]; - else - data += ((struct trx_header *)data)->offsets[1]; - - offset = 0; - - /* lzma args */ - i = get_byte(); - lc = i % 9, i = i / 9; - lp = i % 5, pb = i / 5; - - /* skip rest of the LZMA coder property */ - for (i = 0; i < 4; i++) - get_byte(); - - /* read the lower half of uncompressed size in the header */ - osize = ((unsigned int)get_byte()) + - ((unsigned int)get_byte() << 8) + - ((unsigned int)get_byte() << 16) + - ((unsigned int)get_byte() << 24); - - /* skip rest of the header (upper half of uncompressed size) */ - for (i = 0; i < 4; i++) - get_byte(); - - /* decompress kernel */ - if (LzmaDecode(workspace, ~0, lc, lp, pb, &callback, - (unsigned char*)LOADADDR, osize, &i) == LZMA_RESULT_OK) - { - blast_dcache(dcache_size, dcache_lsize); - blast_icache(icache_size, icache_lsize); - - /* Jump to load address */ - ((void (*)(void)) LOADADDR)(); - } -} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/decompress.lds.in b/target/linux/brcm63xx/image/lzma-loader/src/decompress.lds.in deleted file mode 100644 index 33f56f8a09..0000000000 --- a/target/linux/brcm63xx/image/lzma-loader/src/decompress.lds.in +++ /dev/null @@ -1,20 +0,0 @@ -OUTPUT_ARCH(mips) -ENTRY(entry) -SECTIONS { - . = BZ_TEXT_START; - .text : { - *(.text.entry) - *(.text) - *(.rodata) - } - - .data : { - *(.data) - } - - .bss : { - *(.bss) - } - - workspace = .; -} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/head.S b/target/linux/brcm63xx/image/lzma-loader/src/head.S deleted file mode 100644 index 9bfbd53d51..0000000000 --- a/target/linux/brcm63xx/image/lzma-loader/src/head.S +++ /dev/null @@ -1,155 +0,0 @@ -/* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su) */ -/* cache manipulation adapted from Broadcom code */ -/* idea taken from original bunzip2 decompressor code */ -/* Copyright 2004 Manuel Novoa III (mjn3@codepoet.org) */ -/* Licensed under the linux kernel's version of the GPL.*/ - -#include -#include - -#define KSEG0 0x80000000 - -#define C0_CONFIG $16 -#define C0_TAGLO $28 -#define C0_TAGHI $29 - -#define CONF1_DA_SHIFT 7 /* D$ associativity */ -#define CONF1_DA_MASK 0x00000380 -#define CONF1_DA_BASE 1 -#define CONF1_DL_SHIFT 10 /* D$ line size */ -#define CONF1_DL_MASK 0x00001c00 -#define CONF1_DL_BASE 2 -#define CONF1_DS_SHIFT 13 /* D$ sets/way */ -#define CONF1_DS_MASK 0x0000e000 -#define CONF1_DS_BASE 64 -#define CONF1_IA_SHIFT 16 /* I$ associativity */ -#define CONF1_IA_MASK 0x00070000 -#define CONF1_IA_BASE 1 -#define CONF1_IL_SHIFT 19 /* I$ line size */ -#define CONF1_IL_MASK 0x00380000 -#define CONF1_IL_BASE 2 -#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */ -#define CONF1_IS_MASK 0x01c00000 -#define CONF1_IS_BASE 64 - -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 - - .text - LEAF(startup) - .set noreorder - - /* Copy decompressor code to the right place */ - li t2, BZ_TEXT_START - add a0, t2, 0 - la a1, code_start - la a2, code_stop -$L1: - lw t0, 0(a1) - sw t0, 0(a0) - add a1, 4 - add a0, 4 - blt a1, a2, $L1 - nop - - /* At this point we need to invalidate dcache and */ - /* icache before jumping to new code */ - -1: /* Get cache sizes */ - .set mips32 - mfc0 s0,C0_CONFIG,1 - .set mips0 - - li s1,CONF1_DL_MASK - and s1,s0 - beq s1,zero,nodc - nop - - srl s1,CONF1_DL_SHIFT - li t0,CONF1_DL_BASE - sll s1,t0,s1 /* s1 has D$ cache line size */ - - li s2,CONF1_DA_MASK - and s2,s0 - srl s2,CONF1_DA_SHIFT - addiu s2,CONF1_DA_BASE /* s2 now has D$ associativity */ - - li t0,CONF1_DS_MASK - and t0,s0 - srl t0,CONF1_DS_SHIFT - li s3,CONF1_DS_BASE - sll s3,s3,t0 /* s3 has D$ sets per way */ - - multu s2,s3 /* sets/way * associativity */ - mflo t0 /* total cache lines */ - - multu s1,t0 /* D$ linesize * lines */ - mflo s2 /* s2 is now D$ size in bytes */ - - /* Initilize the D$: */ - mtc0 zero,C0_TAGLO - mtc0 zero,C0_TAGHI - - li t0,KSEG0 /* Just an address for the first $ line */ - addu t1,t0,s2 /* + size of cache == end */ - - .set mips3 -1: cache Index_Writeback_Inv_D,0(t0) - .set mips0 - bne t0,t1,1b - addu t0,s1 - -nodc: - /* Now we get to do it all again for the I$ */ - - move s3,zero /* just in case there is no icache */ - move s4,zero - - li t0,CONF1_IL_MASK - and t0,s0 - beq t0,zero,noic - nop - - srl t0,CONF1_IL_SHIFT - li s3,CONF1_IL_BASE - sll s3,t0 /* s3 has I$ cache line size */ - - li t0,CONF1_IA_MASK - and t0,s0 - srl t0,CONF1_IA_SHIFT - addiu s4,t0,CONF1_IA_BASE /* s4 now has I$ associativity */ - - li t0,CONF1_IS_MASK - and t0,s0 - srl t0,CONF1_IS_SHIFT - li s5,CONF1_IS_BASE - sll s5,t0 /* s5 has I$ sets per way */ - - multu s4,s5 /* sets/way * associativity */ - mflo t0 /* s4 is now total cache lines */ - - multu s3,t0 /* I$ linesize * lines */ - mflo s4 /* s4 is cache size in bytes */ - - /* Initilize the I$: */ - mtc0 zero,C0_TAGLO - mtc0 zero,C0_TAGHI - - li t0,KSEG0 /* Just an address for the first $ line */ - addu t1,t0,s4 /* + size of cache == end */ - - .set mips3 -1: cache Index_Invalidate_I,0(t0) - .set mips0 - bne t0,t1,1b - addu t0,s3 - -noic: - move a0,s3 /* icache line size */ - move a1,s4 /* icache size */ - move a2,s1 /* dcache line size */ - jal t2 - move a3,s2 /* dcache size */ - - .set reorder - END(startup) diff --git a/target/linux/brcm63xx/image/lzma-loader/src/loader.lds.in b/target/linux/brcm63xx/image/lzma-loader/src/loader.lds.in deleted file mode 100644 index 20f2ea98ec..0000000000 --- a/target/linux/brcm63xx/image/lzma-loader/src/loader.lds.in +++ /dev/null @@ -1,17 +0,0 @@ -OUTPUT_ARCH(mips) -ENTRY(startup) -SECTIONS { - . = TEXT_START; - .text : { - *(.text) - *(.rodata) - } - - .data : { - *(.data) - } - - .bss : { - *(.bss) - } -} diff --git a/target/linux/brcm63xx/patches-2.6.25/001-bcm963xx.patch b/target/linux/brcm63xx/patches-2.6.25/001-bcm963xx.patch deleted file mode 100644 index 909ff61a56..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/001-bcm963xx.patch +++ /dev/null @@ -1,170 +0,0 @@ -From 2b2b8e163d28646cbbfde81c900fbb57d6572a11 Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Thu, 15 May 2008 11:00:43 +0200 -Subject: [PATCH] bcm963xx: board support - - -Signed-off-by: Axel Gembe ---- - arch/mips/Kconfig | 11 +++++++++++ - arch/mips/Makefile | 4 ++++ - arch/mips/kernel/cpu-probe.c | 16 ++++++++++++++++ - arch/mips/mm/c-r4k.c | 7 +++++++ - arch/mips/mm/tlbex.c | 4 ++++ - arch/mips/pci/Makefile | 1 + - include/asm-mips/bootinfo.h | 12 ++++++++++++ - include/asm-mips/cpu.h | 7 ++++++- - 8 files changed, 61 insertions(+), 1 deletions(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -59,6 +59,17 @@ - help - Support for BCM47XX based boards - -+config BCM963XX -+ bool "Support for Broadcom BCM963xx SoC" -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_HAS_CPU_MIPS32_R1 -+ select HW_HAS_PCI -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ help -+ This is a fmaily of boards based on the Broadcom MIPS32 -+ - config MIPS_COBALT - bool "Cobalt Server" - select CEVT_R4K ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -560,6 +560,10 @@ - cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx - load-$(CONFIG_BCM47XX) := 0xffffffff80001000 - -+core-$(CONFIG_BCM963XX) += arch/mips/bcm963xx/ -+cflags-$(CONFIG_BCM963XX) += -Iinclude/asm-mips/mach-bcm963xx -+load-$(CONFIG_BCM963XX) := 0xffffffff8001000 -+ - # - # SNI RM - # ---- a/arch/mips/kernel/cpu-probe.c -+++ b/arch/mips/kernel/cpu-probe.c -@@ -803,6 +803,21 @@ - case PRID_IMP_BCM4710: - c->cputype = CPU_BCM4710; - break; -+// case PRID_IMP_BCM6338: -+// c->cputype = CPU_BCM6338; -+// break; -+ case PRID_IMP_BCM6345: -+ c->cputype = CPU_BCM6345; -+ break; -+ case PRID_IMP_BCM6348: -+ c->cputype = CPU_BCM6348; -+ break; -+ case PRID_IMP_BCM6358: -+ c->cputype = CPU_BCM6358; -+ break; -+ case PRID_IMP_BCM3350: -+ c->cputype = CPU_BCM3350; -+ break; - default: - c->cputype = CPU_UNKNOWN; - break; -@@ -887,6 +902,11 @@ - case CPU_SR71000: name = "Sandcraft SR71000"; break; - case CPU_BCM3302: name = "Broadcom BCM3302"; break; - case CPU_BCM4710: name = "Broadcom BCM4710"; break; -+ case CPU_BCM6338: name = "Broadcom BCM6338"; break; -+ case CPU_BCM6345: name = "Broadcom BCM6345"; break; -+ case CPU_BCM6348: name = "Broadcom BCM6348"; break; -+ case CPU_BCM6358: name = "Broadcom BCM6358"; break; -+ case CPU_BCM3350: name = "Broadcom BCM3350"; break; - case CPU_PR4450: name = "Philips PR4450"; break; - case CPU_LOONGSON2: name = "ICT Loongson-2"; break; - default: ---- a/arch/mips/mm/c-r4k.c -+++ b/arch/mips/mm/c-r4k.c -@@ -882,6 +882,13 @@ - if (!(config & MIPS_CONF_M)) - panic("Don't know how to probe P-caches on this cpu."); - -+ if (c->cputype == CPU_BCM6338 || c->cputype == CPU_BCM6345 || c->cputype == CPU_BCM6348 || c->cputype == CPU_BCM6358 || c->cputype == CPU_BCM3350) -+ { -+ printk("bcm963xx: enabling icache and dcache...\n"); -+ /* Enable caches */ -+ write_c0_diag(read_c0_diag() | 0xC0000000); -+ } -+ - /* - * So we seem to be a MIPS32 or MIPS64 CPU - * So let's probe the I-cache ... ---- a/arch/mips/mm/tlbex.c -+++ b/arch/mips/mm/tlbex.c -@@ -315,6 +315,11 @@ - case CPU_25KF: - case CPU_BCM3302: - case CPU_BCM4710: -+// case CPU_BCM6338: -+ case CPU_BCM6345: -+ case CPU_BCM6348: -+ case CPU_BCM6358: -+ case CPU_BCM3350: - case CPU_LOONGSON2: - if (m4kc_tlbp_war()) - uasm_i_nop(p); ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -48,3 +48,4 @@ - obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o - obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o - obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o -+obj-$(CONFIG_BCM963XX) += fixup-bcm96348.o pci-bcm96348.o ops-bcm96348.o ---- a/include/asm-mips/bootinfo.h -+++ b/include/asm-mips/bootinfo.h -@@ -94,6 +94,19 @@ - #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ - #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ - -+#define MACH_WRPPMC 1 -+ -+/* -+ * Valid machtype for group Broadcom -+ */ -+#define MACH_GROUP_BRCM 23 /* Broadcom */ -+#define MACH_BCM47XX 1 /* Broadcom BCM47XX */ -+#define MACH_BCM96338 2 -+#define MACH_BCM96345 3 -+#define MACH_BCM96348 4 -+#define MACH_BCM96358 5 -+#define MACH_BCM3350 6 -+ - #define CL_SIZE COMMAND_LINE_SIZE - - extern char *system_type; ---- a/include/asm-mips/cpu.h -+++ b/include/asm-mips/cpu.h -@@ -111,6 +111,11 @@ - - #define PRID_IMP_BCM4710 0x4000 - #define PRID_IMP_BCM3302 0x9000 -+//#define PRID_IMP_BCM6338 0x9000 -+#define PRID_IMP_BCM6345 0x8000 -+#define PRID_IMP_BCM6348 0x9100 -+#define PRID_IMP_BCM6358 0xA000 -+#define PRID_IMP_BCM3350 0x28000 - - /* - * Definitions for 7:0 on legacy processors -@@ -196,7 +201,8 @@ - */ - CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, - CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550, -- CPU_PR4450, CPU_BCM3302, CPU_BCM4710, -+ CPU_PR4450, CPU_BCM3302, CPU_BCM4710, CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, -+ CPU_BCM6358, CPU_BCM3350, - - /* - * MIPS64 class processors diff --git a/target/linux/brcm63xx/patches-2.6.25/002-bcm963xx_serial.patch b/target/linux/brcm63xx/patches-2.6.25/002-bcm963xx_serial.patch deleted file mode 100644 index 7c46a79e74..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/002-bcm963xx_serial.patch +++ /dev/null @@ -1,18 +0,0 @@ -From 53bc5316c1123689dddf2c78a4cdfd15834237e8 Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Mon, 12 May 2008 18:53:47 +0200 -Subject: [PATCH] bcm963xx: serial port support - - -Signed-off-by: Axel Gembe ---- - drivers/serial/Makefile | 1 + - 1 files changed, 1 insertions(+), 0 deletions(-) - ---- a/drivers/serial/Makefile -+++ b/drivers/serial/Makefile -@@ -67,3 +67,4 @@ - obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o - obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o - obj-$(CONFIG_SERIAL_QE) += ucc_uart.o -+obj-$(CONFIG_BCM963XX) += bcm63xx_cons.o diff --git a/target/linux/brcm63xx/patches-2.6.25/040-bcm963xx_flashmap.patch b/target/linux/brcm63xx/patches-2.6.25/040-bcm963xx_flashmap.patch deleted file mode 100644 index e4e6ff5c58..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/040-bcm963xx_flashmap.patch +++ /dev/null @@ -1,73 +0,0 @@ -From e734ace5baa04e0e8af1d4483475fbd6bd2b32a1 Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Mon, 12 May 2008 18:54:09 +0200 -Subject: [PATCH] bcm963xx: flashmap support - - -Signed-off-by: Axel Gembe ---- - drivers/mtd/maps/Kconfig | 7 +++++++ - drivers/mtd/maps/Makefile | 1 + - drivers/mtd/redboot.c | 13 ++++++++++--- - 3 files changed, 18 insertions(+), 3 deletions(-) - ---- a/drivers/mtd/maps/Kconfig -+++ b/drivers/mtd/maps/Kconfig -@@ -262,6 +262,13 @@ - Flash memory access on 4G Systems MTX-1 Board. If you have one of - these boards and would like to use the flash chips on it, say 'Y'. - -+config MTD_BCM963XX -+ tristate "BCM963xx Flash device" -+ depends on MIPS && BCM963XX -+ help -+ Flash memory access on BCM963xx boards. Currently only works with -+ RedBoot and CFE. -+ - config MTD_DILNETPC - tristate "CFI Flash device mapped on DIL/Net PC" - depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT ---- a/drivers/mtd/maps/Makefile -+++ b/drivers/mtd/maps/Makefile -@@ -68,3 +68,4 @@ - obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o - obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o - obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o -+obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o ---- a/drivers/mtd/redboot.c -+++ b/drivers/mtd/redboot.c -@@ -39,7 +39,7 @@ - return 1; - } - --static int parse_redboot_partitions(struct mtd_info *master, -+int parse_redboot_partitions(struct mtd_info *master, - struct mtd_partition **pparts, - unsigned long fis_origin) - { -@@ -161,6 +161,14 @@ - goto out; - } - -+ if (!fis_origin) { -+ for (i = 0; i < numslots; i++) { -+ if (!strncmp(buf[i].name, "RedBoot", 8)) { -+ fis_origin = (buf[i].flash_base & (master->size << 1) - 1); -+ } -+ } -+ } -+ - for (i = 0; i < numslots; i++) { - struct fis_list *new_fl, **prev; - -@@ -183,9 +191,8 @@ - new_fl->img = &buf[i]; - if (fis_origin) { - buf[i].flash_base -= fis_origin; -- } else { -- buf[i].flash_base &= master->size-1; - } -+ buf[i].flash_base &= (master->size << 1) - 1; - - /* I'm sure the JFFS2 code has done me permanent damage. - * I now think the following is _normal_ diff --git a/target/linux/brcm63xx/patches-2.6.25/050-bcm963xx_add_trailing_zero.patch b/target/linux/brcm63xx/patches-2.6.25/050-bcm963xx_add_trailing_zero.patch deleted file mode 100644 index d13ca92664..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/050-bcm963xx_add_trailing_zero.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 40dd38388c3d1c87efe254cee533fc5db5ffc4ed Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Wed, 14 May 2008 12:43:34 +0200 -Subject: [PATCH] bcm963xx: add missing trailing zero to load address - -The load address for BCM963xx is 0x80010000, not 0xf8001000 as in the current -sources. I think this is just a typo, so this patch fixes it (tested on 96345). - -Signed-off-by: Axel Gembe ---- - arch/mips/Makefile | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -562,7 +562,7 @@ - - core-$(CONFIG_BCM963XX) += arch/mips/bcm963xx/ - cflags-$(CONFIG_BCM963XX) += -Iinclude/asm-mips/mach-bcm963xx --load-$(CONFIG_BCM963XX) := 0xffffffff8001000 -+load-$(CONFIG_BCM963XX) := 0xffffffff80010000 - - # - # SNI RM diff --git a/target/linux/brcm63xx/patches-2.6.25/060-bcm963xx_rewrite_irq_handling_code.patch b/target/linux/brcm63xx/patches-2.6.25/060-bcm963xx_rewrite_irq_handling_code.patch deleted file mode 100644 index 349010486f..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/060-bcm963xx_rewrite_irq_handling_code.patch +++ /dev/null @@ -1,452 +0,0 @@ -From 9a70f2dcb24a5aab29386373c86ba035acba4891 Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Sun, 18 May 2008 12:07:21 +0200 -Subject: [PATCH] bcm963xx: rewrite irq handling code - -This patch adds interrupt handling as on AR7. The old code was very messy and -didn't work too well. - -Signed-off-by: Axel Gembe ---- - arch/mips/bcm963xx/irq.c | 308 ++++++++++------------------- - drivers/serial/bcm63xx_cons.c | 13 +- - include/asm-mips/mach-bcm963xx/bcm_intr.h | 18 +-- - 3 files changed, 119 insertions(+), 220 deletions(-) - ---- a/arch/mips/bcm963xx/irq.c -+++ b/arch/mips/bcm963xx/irq.c -@@ -1,259 +1,159 @@ - /* --<:copyright-gpl -- Copyright 2002 Broadcom Corp. All Rights Reserved. -- -- This program is free software; you can distribute it and/or modify it -- under the terms of the GNU General Public License (Version 2) as -- published by the Free Software Foundation. -- -- This program is distributed in the hope it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. --:> --*/ --/* -- * Interrupt control functions for Broadcom 963xx MIPS boards -+ * Copyright (C) 2006,2007 Felix Fietkau -+ * Copyright (C) 2006,2007 Eugene Konev -+ * Copyright (C) 2008 Axel Gembe -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - --#include -- --#include --#include --#include --#include - #include --#include --#include --#include -+#include - --#include -+#include - #include --#include --#include -+ - #include <6348_map_part.h> - #include <6348_intr.h> - #include - #include - --static void irq_dispatch_int(void) --{ -- unsigned int pendingIrqs; -- static unsigned int irqBit; -- static unsigned int isrNumber = 31; -- -- pendingIrqs = PERF->IrqStatus & PERF->IrqMask; -- if (!pendingIrqs) { -- return; -- } -+static int bcm963xx_irq_base; - -- while (1) { -- irqBit <<= 1; -- isrNumber++; -- if (isrNumber == 32) { -- isrNumber = 0; -- irqBit = 0x1; -- } -- if (pendingIrqs & irqBit) { -- PERF->IrqMask &= ~irqBit; // mask -- do_IRQ(isrNumber + INTERNAL_ISR_TABLE_OFFSET); -- break; -- } -- } -+void bcm963xx_unmask_irq(unsigned int irq) -+{ -+ PERF->IrqMask |= (1 << (irq - bcm963xx_irq_base)); - } - --static void irq_dispatch_ext(uint32 irq) -+void bcm963xx_mask_irq(unsigned int irq) - { -- if (!(PERF->ExtIrqCfg & (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)))) { -- printk("**** Ext IRQ mask. Should not dispatch ****\n"); -- } -- /* disable and clear interrupt in the controller */ -- PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT)); -- PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); -- do_IRQ(irq); -+ PERF->IrqMask &= ~(1 << (irq - bcm963xx_irq_base)); - } - -- --//extern void brcm_timer_interrupt(struct pt_regs *regs); -- --asmlinkage void plat_irq_dispatch(void) -+void bcm963xx_ack_irq(unsigned int irq) - { -- unsigned long cause; -- -- cause = read_c0_status() & read_c0_cause() & ST0_IM; -- if (cause & CAUSEF_IP7) -- do_IRQ(7); -- else if (cause & CAUSEF_IP2) -- irq_dispatch_int(); -- else if (cause & CAUSEF_IP3) -- irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_0); -- else if (cause & CAUSEF_IP4) -- irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_1); -- else if (cause & CAUSEF_IP5) -- irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_2); -- else if (cause & CAUSEF_IP6) { -- irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_3); -- local_irq_disable(); -- } -+ PERF->IrqStatus &= ~(1 << (irq - bcm963xx_irq_base)); - } - -- --void enable_brcm_irq(unsigned int irq) -+void bcm963xx_unmask_ext_irq(unsigned int irq) - { -- unsigned long flags; -- -- local_irq_save(flags); -- if( irq >= INTERNAL_ISR_TABLE_OFFSET ) { -- PERF->IrqMask |= (1 << (irq - INTERNAL_ISR_TABLE_OFFSET)); -- } -- else if (irq >= INTERRUPT_ID_EXTERNAL_0 && irq <= INTERRUPT_ID_EXTERNAL_3) { -- /* enable and clear interrupt in the controller */ -- PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT)); - PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); -- } -- local_irq_restore(flags); - } - --void disable_brcm_irq(unsigned int irq) -+void bcm963xx_mask_ext_irq(unsigned int irq) - { -- unsigned long flags; -- -- local_irq_save(flags); -- if( irq >= INTERNAL_ISR_TABLE_OFFSET ) { -- PERF->IrqMask &= ~(1 << (irq - INTERNAL_ISR_TABLE_OFFSET)); -- } -- else if (irq >= INTERRUPT_ID_EXTERNAL_0 && irq <= INTERRUPT_ID_EXTERNAL_3) { -- /* disable interrupt in the controller */ - PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); -- } -- local_irq_restore(flags); - } - --void ack_brcm_irq(unsigned int irq) -+void bcm963xx_ack_ext_irq(unsigned int irq) - { -- /* Already done in brcm_irq_dispatch */ -+ PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT)); - } - --unsigned int startup_brcm_irq(unsigned int irq) -+static void bcm963xx_dispatch_ext_irq(unsigned int irq) - { -- enable_brcm_irq(irq); -- -- return 0; /* never anything pending */ -+ bcm963xx_ack_ext_irq(irq); -+ bcm963xx_mask_ext_irq(irq); -+ do_IRQ(irq); - } - --unsigned int startup_brcm_none(unsigned int irq) -+static void bcm963xx_cascade(void) - { -- return 0; --} -+ uint32_t pending, bit, irq; - --void end_brcm_irq(unsigned int irq) --{ -- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) -- enable_brcm_irq(irq); --} -+ if (!(pending = PERF->IrqStatus & PERF->IrqMask)) -+ return; - --void end_brcm_none(unsigned int irq) --{ --} -+ for (irq = 0, bit = 1; irq < 32; irq++, bit <<= 1) { -+ if (pending & bit) { -+ bcm963xx_ack_irq(irq + bcm963xx_irq_base); -+ bcm963xx_mask_irq(irq + bcm963xx_irq_base); -+ do_IRQ(irq + bcm963xx_irq_base); -+ return; -+ } -+ } -+ -+ spurious_interrupt(); -+} -+ -+static struct irq_chip bcm963xx_irq_type = { -+ .name = "bcm963xx", -+ .unmask = bcm963xx_unmask_irq, -+ .mask = bcm963xx_mask_irq, -+ .ack = bcm963xx_ack_irq -+}; - --static struct hw_interrupt_type brcm_irq_type = { -- .typename = "MIPS", -- .startup = startup_brcm_irq, -- .shutdown = disable_brcm_irq, -- .enable = enable_brcm_irq, -- .disable = disable_brcm_irq, -- .ack = ack_brcm_irq, -- .end = end_brcm_irq, -- .set_affinity = NULL -+static struct irq_chip bcm963xx_ext_irq_type = { -+ .name = "bcm963xx_ext", -+ .unmask = bcm963xx_unmask_ext_irq, -+ .mask = bcm963xx_mask_ext_irq, -+ .ack = bcm963xx_ack_ext_irq, - }; - --static struct hw_interrupt_type brcm_irq_no_end_type = { -- .typename = "MIPS", -- .startup = startup_brcm_none, -- .shutdown = disable_brcm_irq, -- .enable = enable_brcm_irq, -- .disable = disable_brcm_irq, -- .ack = ack_brcm_irq, -- .end = end_brcm_none, -- .set_affinity = NULL -+static struct irqaction bcm963xx_cascade_action = { -+ .handler = no_action, -+ .name = "BCM963xx cascade interrupt" - }; - --void __init arch_init_irq(void) -+static void __init bcm963xx_irq_init(int base) - { - int i; - -- clear_c0_status(ST0_BEV); -- change_c0_status(ST0_IM, (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)); -+ bcm963xx_irq_base = base; - -- for (i = 0; i < NR_IRQS; i++) { -- irq_desc[i].status = IRQ_DISABLED; -- irq_desc[i].action = 0; -- irq_desc[i].depth = 1; -- irq_desc[i].chip = &brcm_irq_type; -- } -+ /* External IRQs */ -+ set_irq_chip_and_handler(INTERRUPT_ID_EXTERNAL_0, &bcm963xx_ext_irq_type, -+ handle_level_irq); -+ set_irq_chip_and_handler(INTERRUPT_ID_EXTERNAL_1, &bcm963xx_ext_irq_type, -+ handle_level_irq); -+ set_irq_chip_and_handler(INTERRUPT_ID_EXTERNAL_2, &bcm963xx_ext_irq_type, -+ handle_level_irq); -+ set_irq_chip_and_handler(INTERRUPT_ID_EXTERNAL_3, &bcm963xx_ext_irq_type, -+ handle_level_irq); -+ -+ for (i = 0; i < 32; i++) { -+ set_irq_chip_and_handler(base + i, &bcm963xx_irq_type, -+ handle_level_irq); -+ } -+ -+ setup_irq(2, &bcm963xx_cascade_action); -+ setup_irq(bcm963xx_irq_base, &bcm963xx_cascade_action); -+ set_c0_status(IE_IRQ0); - } - --int request_external_irq(unsigned int irq, -- FN_HANDLER handler, -- unsigned long irqflags, -- const char * devname, -- void *dev_id) -+asmlinkage void plat_irq_dispatch(void) - { -- unsigned long flags; -- -- local_irq_save(flags); -+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - -- PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT)); // Clear -- PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); // Mask -- PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_INSENS_SHFT)); // Edge insesnsitive -- PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_LEVEL_SHFT)); // Level triggered -- PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_SENSE_SHFT)); // Low level -- -- local_irq_restore(flags); -- -- return( request_irq(irq, handler, irqflags, devname, dev_id) ); -+ if (pending & STATUSF_IP7) /* cpu timer */ -+ do_IRQ(7); -+ else if (pending & STATUSF_IP2) /* internal interrupt cascade */ -+ bcm963xx_cascade(); -+ else if (pending & STATUSF_IP3) -+ bcm963xx_dispatch_ext_irq(INTERRUPT_ID_EXTERNAL_0); -+ else if (pending & STATUSF_IP4) -+ bcm963xx_dispatch_ext_irq(INTERRUPT_ID_EXTERNAL_1); -+ else if (pending & STATUSF_IP5) -+ bcm963xx_dispatch_ext_irq(INTERRUPT_ID_EXTERNAL_2); -+ else if (pending & STATUSF_IP6) -+ bcm963xx_dispatch_ext_irq(INTERRUPT_ID_EXTERNAL_3); -+ else -+ spurious_interrupt(); - } - --/* VxWorks compatibility function(s). */ -- --unsigned int BcmHalMapInterrupt(FN_HANDLER pfunc, unsigned int param, -- unsigned int interruptId) -+void __init arch_init_irq(void) - { -- int nRet = -1; -- char *devname; -- -- devname = kmalloc(16, GFP_KERNEL); -- if (devname) -- sprintf( devname, "brcm_%d", interruptId ); -- -- /* Set the IRQ description to not automatically enable the interrupt at -- * the end of an ISR. The driver that handles the interrupt must -- * explicitly call BcmHalInterruptEnable or enable_brcm_irq. This behavior -- * is consistent with interrupt handling on VxWorks. -- */ -- irq_desc[interruptId].chip = &brcm_irq_no_end_type; -- -- if( interruptId >= INTERNAL_ISR_TABLE_OFFSET ) -- { -- printk("BcmHalMapInterrupt : internal IRQ\n"); -- nRet = request_irq( interruptId, pfunc, IRQF_DISABLED, devname, (void *) param ); -- } -- else if (interruptId >= INTERRUPT_ID_EXTERNAL_0 && interruptId <= INTERRUPT_ID_EXTERNAL_3) -- { -- printk("BcmHalMapInterrupt : external IRQ\n"); -- nRet = request_external_irq( interruptId, pfunc, IRQF_DISABLED, devname, (void *) param ); -- } -- -- return( nRet ); -+ mips_cpu_irq_init(); -+ bcm963xx_irq_init(INTERNAL_ISR_TABLE_OFFSET); - } -- -- --EXPORT_SYMBOL(enable_brcm_irq); --EXPORT_SYMBOL(disable_brcm_irq); --EXPORT_SYMBOL(request_external_irq); --EXPORT_SYMBOL(BcmHalMapInterrupt); -- ---- a/drivers/serial/bcm63xx_cons.c -+++ b/drivers/serial/bcm63xx_cons.c -@@ -267,7 +267,7 @@ - } - - // Clear the interrupt -- enable_brcm_irq(INTERRUPT_ID_UART); -+// bcm963xx_unmask_irq(INTERRUPT_ID_UART); - #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) - return IRQ_HANDLED; - #endif -@@ -880,7 +880,7 @@ - info->count++; - tty->driver_data = info; - info->tty = tty; -- enable_brcm_irq(INTERRUPT_ID_UART); -+ bcm963xx_unmask_irq(INTERRUPT_ID_UART); - - // Start up serial port - retval = startup(info); -@@ -927,7 +927,7 @@ - -------------------------------------------------------------------------- */ - static int __init bcm63xx_serialinit(void) - { -- int i, flags; -+ int i, flags, res; - struct bcm_serial *info; - - // Print the driver version information -@@ -981,7 +981,12 @@ - */ - if (!info->port) - return 0; -- BcmHalMapInterrupt(bcm_interrupt, 0, INTERRUPT_ID_UART); -+ -+ res = request_irq(INTERRUPT_ID_UART, bcm_interrupt, 0, "bcm-uart", NULL); -+ if (res) { -+ spin_unlock_irqrestore(&bcm963xx_serial_lock, flags); -+ return res; -+ } - } - - /* order matters here... the trick is that flags ---- a/include/asm-mips/mach-bcm963xx/bcm_intr.h -+++ b/include/asm-mips/mach-bcm963xx/bcm_intr.h -@@ -39,18 +39,12 @@ - typedef int (*FN_HANDLER) (int, void *); - - /* prototypes */ --extern void enable_brcm_irq(unsigned int irq); --extern void disable_brcm_irq(unsigned int irq); --extern int request_external_irq(unsigned int irq, -- FN_HANDLER handler, unsigned long irqflags, -- const char * devname, void *dev_id); --extern unsigned int BcmHalMapInterrupt(FN_HANDLER isr, unsigned int param, -- unsigned int interruptId); --extern void dump_intr_regs(void); -- --/* compatibility definitions */ --#define BcmHalInterruptEnable(irq) enable_brcm_irq( irq ) --#define BcmHalInterruptDisable(irq) disable_brcm_irq( irq ) -+extern void bcm963xx_unmask_irq(unsigned int irq); -+extern void bcm963xx_mask_irq(unsigned int irq); -+extern void bcm963xx_ack_irq(unsigned int irq); -+extern void bcm963xx_unmask_ext_irq(unsigned int irq); -+extern void bcm963xx_mask_ext_irq(unsigned int irq); -+extern void bcm963xx_ack_ext_irq(unsigned int irq); - - #ifdef __cplusplus - } diff --git a/target/linux/brcm63xx/patches-2.6.25/070-bcm963xx_fix_uart_isr.patch b/target/linux/brcm63xx/patches-2.6.25/070-bcm963xx_fix_uart_isr.patch deleted file mode 100644 index a90bde3f89..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/070-bcm963xx_fix_uart_isr.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 7bc3950017d2c54883591367723b7fd84cc65d6f Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Sun, 18 May 2008 12:09:14 +0200 -Subject: [PATCH] bcm963xx: fix uart isr - -The ISR ended up in an endless loop because the TX ISR never got used or masked. -This patch basically makes the TX ISR mask the the TX interrupt when it -encounters it, because it doesn't even use the TX interrupt. - -Signed-off-by: Axel Gembe ---- - drivers/serial/bcm63xx_cons.c | 6 ++++++ - 1 files changed, 6 insertions(+), 0 deletions(-) - ---- a/drivers/serial/bcm63xx_cons.c -+++ b/drivers/serial/bcm63xx_cons.c -@@ -258,8 +258,14 @@ - while (intStat) { - if (intStat & RXINT) - receive_chars(info); -+ -+#if 0 /* This code is total bullshit, TXINT doesn't get masked anywhere, so this will give an endless loop */ -+ - else if (intStat & TXINT) - info->port->intStatus = TXINT; -+ -+#endif /* 0 */ -+ - else /* don't know what it was, so let's mask it */ - info->port->intMask &= ~intStat; - diff --git a/target/linux/brcm63xx/patches-2.6.25/080-bcm963xx_remove_unused_int_handler.patch b/target/linux/brcm63xx/patches-2.6.25/080-bcm963xx_remove_unused_int_handler.patch deleted file mode 100644 index 0abfd98855..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/080-bcm963xx_remove_unused_int_handler.patch +++ /dev/null @@ -1,87 +0,0 @@ -From e3abd028e7631ee952fe73d8f9ee97bc615526a8 Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Sat, 17 May 2008 16:07:46 +0200 -Subject: [PATCH] bcm963xx: remove unused int-handler.S - -The code is not used anymore. - -Signed-off-by: Axel Gembe ---- - arch/mips/bcm963xx/Makefile | 2 +- - arch/mips/bcm963xx/int-handler.S | 59 -------------------------------------- - 2 files changed, 1 insertions(+), 60 deletions(-) - delete mode 100644 arch/mips/bcm963xx/int-handler.S - ---- a/arch/mips/bcm963xx/Makefile -+++ b/arch/mips/bcm963xx/Makefile -@@ -3,7 +3,7 @@ - # - # Copyright (C) 2004 Broadcom Corporation - # --obj-y := irq.o prom.o setup.o time.o ser_init.o int-handler.o info.o wdt.o -+obj-y := irq.o prom.o setup.o time.o ser_init.o info.o wdt.o - - SRCBASE := $(TOPDIR) - EXTRA_CFLAGS += -I$(SRCBASE)/include ---- a/arch/mips/bcm963xx/int-handler.S -+++ /dev/null -@@ -1,59 +0,0 @@ --/* --<:copyright-gpl -- Copyright 2002 Broadcom Corp. All Rights Reserved. -- -- This program is free software; you can distribute it and/or modify it -- under the terms of the GNU General Public License (Version 2) as -- published by the Free Software Foundation. -- -- This program is distributed in the hope it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. --:> --*/ --/* -- * Generic interrupt handler for Broadcom MIPS boards -- */ -- --#include -- --#include --#include --#include --#include -- --/* -- * MIPS IRQ Source -- * -------- ------ -- * 0 Software (ignored) -- * 1 Software (ignored) -- * 2 Combined hardware interrupt (hw0) -- * 3 Hardware -- * 4 Hardware -- * 5 Hardware -- * 6 Hardware -- * 7 R4k timer -- */ -- -- .text -- .set noreorder -- .set noat -- .align 5 -- NESTED(brcmIRQ, PT_SIZE, sp) -- SAVE_ALL -- CLI -- .set noreorder -- .set at -- -- jal plat_irq_dispatch -- move a0, sp -- -- j ret_from_irq -- nop -- -- END(brcmIRQ) diff --git a/target/linux/brcm63xx/patches-2.6.25/090-bcm963xx_remove_obsolete_timer_code.patch b/target/linux/brcm63xx/patches-2.6.25/090-bcm963xx_remove_obsolete_timer_code.patch deleted file mode 100644 index 72ccfea7f6..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/090-bcm963xx_remove_obsolete_timer_code.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 42ecc15386869684cf29881a3a6941bafaa3bf69 Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Wed, 14 May 2008 00:25:28 +0200 -Subject: [PATCH] bcm963xx: remove obsolete timer code - -This removes some code that has been deprecated in kernels >= 2.6.24. - -Signed-off-by: Axel Gembe ---- - arch/mips/bcm963xx/setup.c | 2 -- - arch/mips/bcm963xx/time.c | 29 ----------------------------- - 2 files changed, 0 insertions(+), 31 deletions(-) - ---- a/arch/mips/bcm963xx/setup.c -+++ b/arch/mips/bcm963xx/setup.c -@@ -465,8 +465,6 @@ - _machine_halt = brcm_machine_halt; - pm_power_off = brcm_machine_halt; - -- //board_time_init = brcm_time_init; -- - /* mpi initialization */ - mpi_init(); - } ---- a/arch/mips/bcm963xx/time.c -+++ b/arch/mips/bcm963xx/time.c -@@ -71,26 +71,6 @@ - return (mips_hpt_frequency / HZ); - } - -- --/* -- * There are a lot of conceptually broken versions of the MIPS timer interrupt -- * handler floating around. This one is rather different, but the algorithm -- * is provably more robust. -- */ --#if 0 --irqreturn_t brcm_timer_interrupt(struct pt_regs *regs) --{ -- int irq = MIPS_TIMER_INT; -- -- irq_enter(); -- kstat_this_cpu.irqs[irq]++; -- -- timer_interrupt(irq, regs); -- irq_exit(); -- return IRQ_HANDLED; --} --#endif -- - void __init plat_time_init(void) - { - unsigned int est_freq, flags; -@@ -107,12 +87,3 @@ - (est_freq % 1000000) * 100 / 1000000); - local_irq_restore(flags); - } -- --#if 0 --void __init plat_timer_setup(struct irqaction *irq) --{ -- r4k_cur = (read_c0_count() + r4k_offset); -- write_c0_compare(r4k_cur); -- set_c0_status(IE_IRQ5); --} --#endif diff --git a/target/linux/brcm63xx/patches-2.6.25/100-bcm963xx_add_new_timer_code.patch b/target/linux/brcm63xx/patches-2.6.25/100-bcm963xx_add_new_timer_code.patch deleted file mode 100644 index 9d08ab087b..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/100-bcm963xx_add_new_timer_code.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 7d6656dc127b54e53e507e8f264bb7e14e620cad Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Sat, 17 May 2008 15:02:39 +0200 -Subject: [PATCH] bcm963xx: add new timer code - -This basically selects the new generic MIPS timer code for BCM963xx and -simplifies the timer setup code. - -Signed-off-by: Axel Gembe ---- - arch/mips/Kconfig | 2 + - arch/mips/bcm963xx/time.c | 64 ++++++++++++++++++++------------------------ - 2 files changed, 31 insertions(+), 35 deletions(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -67,6 +67,8 @@ - select HW_HAS_PCI - select DMA_NONCOHERENT - select IRQ_CPU -+ select CEVT_R4K -+ select CSRC_R4K - help - This is a fmaily of boards based on the Broadcom MIPS32 - ---- a/arch/mips/bcm963xx/time.c -+++ b/arch/mips/bcm963xx/time.c -@@ -1,6 +1,7 @@ - /* - <:copyright-gpl - Copyright 2004 Broadcom Corp. All Rights Reserved. -+ Copyright (C) 2008 Axel Gembe - - This program is free software; you can distribute it and/or modify it - under the terms of the GNU General Public License (Version 2) as -@@ -40,50 +41,43 @@ - #include - #include - --static unsigned long r4k_offset; /* Amount to increment compare reg each time */ --static unsigned long r4k_cur; /* What counter should be at next timer irq */ -- --/* ********************************************************************* -- * calculateCpuSpeed() -- * Calculate the BCM6348 CPU speed by reading the PLL strap register -- * and applying the following formula: -- * cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) -- * Input parameters: -- * none -- * Return value: -- * none -- ********************************************************************* */ -- -+/* -+ * calculateCpuSpeed() -+ * -+ * Calculate the BCM6348 CPU speed by reading the PLL strap register and applying -+ * the following formula: -+ * -+ * cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) -+ */ - static inline unsigned long __init calculateCpuSpeed(void) - { -- u32 pllStrap = PERF->PllStrap; -- int n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT; -- int n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT; -- int m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT; -+ u32 pllStrap; -+ int n1, n2, m1cpu; -+ -+ pllStrap = PERF->PllStrap; -+ n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT; -+ n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT; -+ m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT; - - return (16 * (n1 + 1) * (n2 + 2) / (m1cpu + 1)) * 1000000; - } - - --static inline unsigned long __init cal_r4koff(void) --{ -- mips_hpt_frequency = calculateCpuSpeed() / 2; -- return (mips_hpt_frequency / HZ); --} -- - void __init plat_time_init(void) - { -- unsigned int est_freq, flags; -- local_irq_save(flags); -+ unsigned long cpu_clock; -+ -+ cpu_clock = calculateCpuSpeed(); -+ -+ printk("CPU frequency %lu.%02lu MHz\n", cpu_clock / 1000000, -+ (cpu_clock % 1000000) * 100 / 1000000); -+ -+ mips_hpt_frequency = cpu_clock / 2; - -- printk("calculating r4koff... "); -- r4k_offset = cal_r4koff(); -- printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset); -- -- est_freq = 2 * r4k_offset * HZ; -- est_freq += 5000; /* round */ -- est_freq -= est_freq % 10000; -- printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000, -- (est_freq % 1000000) * 100 / 1000000); -- local_irq_restore(flags); -+ /* -+ * Use deterministic values for initial counter interrupt -+ * so that calibrate delay avoids encountering a counter wrap. -+ */ -+ write_c0_count(0); -+ write_c0_compare(0xffff); - } diff --git a/target/linux/brcm63xx/patches-2.6.25/110-bcm963xx_fix_cfe_detection.patch b/target/linux/brcm63xx/patches-2.6.25/110-bcm963xx_fix_cfe_detection.patch deleted file mode 100644 index 3cf4602666..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/110-bcm963xx_fix_cfe_detection.patch +++ /dev/null @@ -1,41 +0,0 @@ -From f1a605c36cf1659f5f486ae4135de1e285fdf86c Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Sat, 17 May 2008 16:17:22 +0200 -Subject: [PATCH] bcm963xx: fix cfe detection - -The CFE detection failed to account for zero termination. - -Signed-off-by: Axel Gembe ---- - drivers/mtd/maps/bcm963xx-flash.c | 11 ++++++----- - 1 files changed, 6 insertions(+), 5 deletions(-) - ---- a/drivers/mtd/maps/bcm963xx-flash.c -+++ b/drivers/mtd/maps/bcm963xx-flash.c -@@ -1,8 +1,7 @@ - /* -- * $Id$ - * Copyright (C) 2006 Florian Fainelli -- * Mike Albon -- * Copyright (C) $Date$ $Author$ -+ * Mike Albon -+ * Copyright (C) 2008 Axel Gembe - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by -@@ -184,11 +183,13 @@ - static int bcm963xx_detect_cfe(struct mtd_info *master) - { - int idoffset = 0x4e0; -- static char idstring[8] = "CFE1CFE1"; -- char buf[8]; -+ static char idstring[9] = "CFE1CFE1"; -+ char buf[9]; - int ret; - size_t retlen; - -+ memset(buf, 0, sizeof(buf)); -+ - ret = master->read(master, idoffset, 8, &retlen, (void *)buf); - printk("bcm963xx: Read Signature value of %s\n", buf); - return strcmp(idstring,buf); diff --git a/target/linux/brcm63xx/patches-2.6.25/500-bcm96345_fixes.patch b/target/linux/brcm63xx/patches-2.6.25/500-bcm96345_fixes.patch deleted file mode 100644 index dd55cd163a..0000000000 --- a/target/linux/brcm63xx/patches-2.6.25/500-bcm96345_fixes.patch +++ /dev/null @@ -1,116 +0,0 @@ -From d1259cf42ce84246c695f06b44d58e3aca0a480b Mon Sep 17 00:00:00 2001 -From: Axel Gembe -Date: Sat, 17 May 2008 14:59:35 +0200 -Subject: [PATCH] bcm96345: correct some 6345 specific stuff - -This fixes some problems with the 6345 support and adds a macro for CPU -identification that is easier on the eyes. The first thing it does is to not -initialize MPI on the 6345 as it does not have PCI. The second thing it does is -to use a static value for the CPU frequency of the 6345 chip to provide an -accurate timer. - -Signed-off-by: Axel Gembe ---- - arch/mips/bcm963xx/setup.c | 8 ++++++-- - arch/mips/bcm963xx/time.c | 5 ++++- - arch/mips/pci/pci-bcm96348.c | 21 +++++++++++++-------- - include/asm-mips/mach-bcm963xx/board.h | 2 ++ - 4 files changed, 25 insertions(+), 11 deletions(-) - ---- a/arch/mips/bcm963xx/setup.c -+++ b/arch/mips/bcm963xx/setup.c -@@ -43,6 +43,7 @@ - #include - #include - #include -+#include - - extern void brcm_time_init(void); - extern int boot_loader_type; -@@ -465,6 +466,9 @@ - _machine_halt = brcm_machine_halt; - pm_power_off = brcm_machine_halt; - -- /* mpi initialization */ -- mpi_init(); -+ /* BCM96345 has no MPI */ -+ if (!ISBCM(0x6345)) { -+ /* mpi initialization */ -+ mpi_init(); -+ } - } ---- a/arch/mips/bcm963xx/time.c -+++ b/arch/mips/bcm963xx/time.c -@@ -40,6 +40,8 @@ - #include <6348_intr.h> - #include - #include -+#include -+ - - /* - * calculateCpuSpeed() -@@ -63,11 +65,12 @@ - } - - -+#define BCM96345_CPU_CLOCK 140000000 - void __init plat_time_init(void) - { - unsigned long cpu_clock; - -- cpu_clock = calculateCpuSpeed(); -+ cpu_clock = ISBCM(0x6345) ? BCM96345_CPU_CLOCK : calculateCpuSpeed(); - - printk("CPU frequency %lu.%02lu MHz\n", cpu_clock / 1000000, - (cpu_clock % 1000000) * 100 / 1000000); ---- a/arch/mips/pci/pci-bcm96348.c -+++ b/arch/mips/pci/pci-bcm96348.c -@@ -21,6 +21,8 @@ - #include - #include - -+#include -+#include - #include - - static struct resource bcm_pci_io_resource = { -@@ -47,16 +49,19 @@ - - static __init int bcm96348_pci_init(void) - { -- /* Avoid ISA compat ranges. */ -- PCIBIOS_MIN_IO = 0x00000000; -- PCIBIOS_MIN_MEM = 0x00000000; -- -- /* Set I/O resource limits. */ -- ioport_resource.end = 0x1fffffff; -- iomem_resource.end = 0xffffffff; -+ if (!ISBCM(0x6345)) { -+ /* Avoid ISA compat ranges. */ -+ PCIBIOS_MIN_IO = 0x00000000; -+ PCIBIOS_MIN_MEM = 0x00000000; -+ -+ /* Set I/O resource limits. */ -+ ioport_resource.end = 0x1fffffff; -+ iomem_resource.end = 0xffffffff; - -- register_pci_controller(&bcm96348_controller); -- return 0; -+ register_pci_controller(&bcm96348_controller); -+ } -+ -+ return 0; - } - - arch_initcall(bcm96348_pci_init); ---- a/include/asm-mips/mach-bcm963xx/board.h -+++ b/include/asm-mips/mach-bcm963xx/board.h -@@ -369,5 +369,7 @@ - - extern int boot_loader_type; - -+#define ISBCM(x) (((PERF->RevID & 0xFFFF0000) >> 16) == x) -+ - #endif /* _BOARD_H */ - diff --git a/target/linux/brcm63xx/patches/001-bcm963xx.patch b/target/linux/brcm63xx/patches/001-bcm963xx.patch deleted file mode 100644 index 4dae0ac7f6..0000000000 --- a/target/linux/brcm63xx/patches/001-bcm963xx.patch +++ /dev/null @@ -1,153 +0,0 @@ -Index: linux-2.6.24.7/arch/mips/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/arch/mips/Kconfig -+++ linux-2.6.24.7/arch/mips/Kconfig -@@ -67,6 +67,17 @@ config BCM47XX - help - Support for BCM47XX based boards - -+config BCM963XX -+ bool "Support for Broadcom BCM963xx SoC" -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_HAS_CPU_MIPS32_R1 -+ select HW_HAS_PCI -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ help -+ This is a fmaily of boards based on the Broadcom MIPS32 -+ - config MIPS_COBALT - bool "Cobalt Server" - select CEVT_R4K -Index: linux-2.6.24.7/arch/mips/kernel/cpu-probe.c -=================================================================== ---- linux-2.6.24.7.orig/arch/mips/kernel/cpu-probe.c -+++ linux-2.6.24.7/arch/mips/kernel/cpu-probe.c -@@ -796,6 +796,18 @@ static inline void cpu_probe_broadcom(st - case PRID_IMP_BCM4710: - c->cputype = CPU_BCM4710; - break; -+// case PRID_IMP_BCM6338: -+// c->cputype = CPU_BCM6338; -+// break; -+ case PRID_IMP_BCM6345: -+ c->cputype = CPU_BCM6345; -+ break; -+ case PRID_IMP_BCM6348: -+ c->cputype = CPU_BCM6348; -+ break; -+ case PRID_IMP_BCM6358: -+ c->cputype = CPU_BCM6358; -+ break; - default: - c->cputype = CPU_UNKNOWN; - break; -@@ -878,6 +890,10 @@ static __init const char *cpu_to_name(st - case CPU_SR71000: name = "Sandcraft SR71000"; break; - case CPU_BCM3302: name = "Broadcom BCM3302"; break; - case CPU_BCM4710: name = "Broadcom BCM4710"; break; -+ case CPU_BCM6338: name = "Broadcom BCM6338"; break; -+ case CPU_BCM6345: name = "Broadcom BCM6345"; break; -+ case CPU_BCM6348: name = "Broadcom BCM6348"; break; -+ case CPU_BCM6358: name = "Broadcom BCM6358"; break; - case CPU_PR4450: name = "Philips PR4450"; break; - case CPU_LOONGSON2: name = "ICT Loongson-2"; break; - default: -Index: linux-2.6.24.7/arch/mips/Makefile -=================================================================== ---- linux-2.6.24.7.orig/arch/mips/Makefile -+++ linux-2.6.24.7/arch/mips/Makefile -@@ -543,6 +543,10 @@ core-$(CONFIG_BCM47XX) += arch/mips/bcm - cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx - load-$(CONFIG_BCM47XX) := 0xffffffff80001000 - -+core-$(CONFIG_BCM963XX) += arch/mips/bcm963xx/ -+cflags-$(CONFIG_BCM963XX) += -Iinclude/asm-mips/mach-bcm963xx -+load-$(CONFIG_BCM963XX) := 0xffffffff8001000 -+ - # - # SNI RM - # -Index: linux-2.6.24.7/arch/mips/mm/c-r4k.c -=================================================================== ---- linux-2.6.24.7.orig/arch/mips/mm/c-r4k.c -+++ linux-2.6.24.7/arch/mips/mm/c-r4k.c -@@ -878,6 +878,13 @@ static void __init probe_pcache(void) - if (!(config & MIPS_CONF_M)) - panic("Don't know how to probe P-caches on this cpu."); - -+ if (c->cputype == CPU_BCM6338 || c->cputype == CPU_BCM6345 || c->cputype == CPU_BCM6348 || c->cputype == CPU_BCM6358) -+ { -+ printk("bcm963xx: enabling icache and dcache...\n"); -+ /* Enable caches */ -+ write_c0_diag(read_c0_diag() | 0xC0000000); -+ } -+ - /* - * So we seem to be a MIPS32 or MIPS64 CPU - * So let's probe the I-cache ... -Index: linux-2.6.24.7/arch/mips/mm/tlbex.c -=================================================================== ---- linux-2.6.24.7.orig/arch/mips/mm/tlbex.c -+++ linux-2.6.24.7/arch/mips/mm/tlbex.c -@@ -909,6 +909,10 @@ static __init void build_tlb_write_entry - case CPU_25KF: - case CPU_BCM3302: - case CPU_BCM4710: -+// case CPU_BCM6338: -+ case CPU_BCM6345: -+ case CPU_BCM6348: -+ case CPU_BCM6358: - case CPU_LOONGSON2: - if (m4kc_tlbp_war()) - i_nop(p); -Index: linux-2.6.24.7/arch/mips/pci/Makefile -=================================================================== ---- linux-2.6.24.7.orig/arch/mips/pci/Makefile -+++ linux-2.6.24.7/arch/mips/pci/Makefile -@@ -48,3 +48,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup- - obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o - obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o - obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o -+obj-$(CONFIG_BCM963XX) += fixup-bcm96348.o pci-bcm96348.o ops-bcm96348.o -Index: linux-2.6.24.7/include/asm-mips/bootinfo.h -=================================================================== ---- linux-2.6.24.7.orig/include/asm-mips/bootinfo.h -+++ linux-2.6.24.7/include/asm-mips/bootinfo.h -@@ -197,6 +197,10 @@ - */ - #define MACH_GROUP_BRCM 23 /* Broadcom */ - #define MACH_BCM47XX 1 /* Broadcom BCM47XX */ -+#define MACH_BCM96338 2 -+#define MACH_BCM96345 3 -+#define MACH_BCM96348 4 -+#define MACH_BCM96358 5 - - #define CL_SIZE COMMAND_LINE_SIZE - -Index: linux-2.6.24.7/include/asm-mips/cpu.h -=================================================================== ---- linux-2.6.24.7.orig/include/asm-mips/cpu.h -+++ linux-2.6.24.7/include/asm-mips/cpu.h -@@ -111,6 +111,10 @@ - - #define PRID_IMP_BCM4710 0x4000 - #define PRID_IMP_BCM3302 0x9000 -+//#define PRID_IMP_BCM6338 0x9000 -+#define PRID_IMP_BCM6345 0x8000 -+#define PRID_IMP_BCM6348 0x9100 -+#define PRID_IMP_BCM6358 0xA000 - - /* - * Definitions for 7:0 on legacy processors -@@ -196,7 +200,8 @@ enum cpu_type_enum { - */ - CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, - CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450, -- CPU_BCM3302, CPU_BCM4710, -+ CPU_BCM3302, CPU_BCM4710, CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, -+ CPU_BCM6358, - - /* - * MIPS64 class processors diff --git a/target/linux/brcm63xx/patches/002-bcm963xx_serial.patch b/target/linux/brcm63xx/patches/002-bcm963xx_serial.patch deleted file mode 100644 index dbcf30e70c..0000000000 --- a/target/linux/brcm63xx/patches/002-bcm963xx_serial.patch +++ /dev/null @@ -1,9 +0,0 @@ -Index: linux-2.6.24.7/drivers/serial/Makefile -=================================================================== ---- linux-2.6.24.7.orig/drivers/serial/Makefile -+++ linux-2.6.24.7/drivers/serial/Makefile -@@ -65,3 +65,4 @@ obj-$(CONFIG_SERIAL_NETX) += netx-serial - obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o - obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o - obj-$(CONFIG_SERIAL_QE) += ucc_uart.o -+obj-$(CONFIG_BCM963XX) += bcm63xx_cons.o diff --git a/target/linux/brcm63xx/patches/040-bcm963xx_flashmap.patch b/target/linux/brcm63xx/patches/040-bcm963xx_flashmap.patch deleted file mode 100644 index 7a62fffa3c..0000000000 --- a/target/linux/brcm63xx/patches/040-bcm963xx_flashmap.patch +++ /dev/null @@ -1,66 +0,0 @@ -Index: linux-2.6.24.7/drivers/mtd/maps/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/drivers/mtd/maps/Kconfig -+++ linux-2.6.24.7/drivers/mtd/maps/Kconfig -@@ -269,6 +269,13 @@ config MTD_MTX1 - Flash memory access on 4G Systems MTX-1 Board. If you have one of - these boards and would like to use the flash chips on it, say 'Y'. - -+config MTD_BCM963XX -+ tristate "BCM963xx Flash device" -+ depends on MIPS && BCM963XX -+ help -+ Flash memory access on BCM963xx boards. Currently only works with -+ RedBoot and CFE. -+ - config MTD_DILNETPC - tristate "CFI Flash device mapped on DIL/Net PC" - depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT -Index: linux-2.6.24.7/drivers/mtd/redboot.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/mtd/redboot.c -+++ linux-2.6.24.7/drivers/mtd/redboot.c -@@ -39,7 +39,7 @@ static inline int redboot_checksum(struc - return 1; - } - --static int parse_redboot_partitions(struct mtd_info *master, -+int parse_redboot_partitions(struct mtd_info *master, - struct mtd_partition **pparts, - unsigned long fis_origin) - { -@@ -146,6 +146,14 @@ static int parse_redboot_partitions(stru - goto out; - } - -+ if (!fis_origin) { -+ for (i = 0; i < numslots; i++) { -+ if (!strncmp(buf[i].name, "RedBoot", 8)) { -+ fis_origin = (buf[i].flash_base & (master->size << 1) - 1); -+ } -+ } -+ } -+ - for (i = 0; i < numslots; i++) { - struct fis_list *new_fl, **prev; - -@@ -168,9 +176,8 @@ static int parse_redboot_partitions(stru - new_fl->img = &buf[i]; - if (fis_origin) { - buf[i].flash_base -= fis_origin; -- } else { -- buf[i].flash_base &= master->size-1; - } -+ buf[i].flash_base &= (master->size << 1) - 1; - - /* I'm sure the JFFS2 code has done me permanent damage. - * I now think the following is _normal_ -Index: linux-2.6.24.7/drivers/mtd/maps/Makefile -=================================================================== ---- linux-2.6.24.7.orig/drivers/mtd/maps/Makefile -+++ linux-2.6.24.7/drivers/mtd/maps/Makefile -@@ -69,3 +69,4 @@ obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o - obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o - obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o - obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o -+obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o diff --git a/target/linux/brcm63xx/profiles/Atheros.mk b/target/linux/brcm63xx/profiles/Atheros.mk deleted file mode 100644 index 029586848f..0000000000 --- a/target/linux/brcm63xx/profiles/Atheros.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Atheros - NAME:=Atheros WiFi (default) - PACKAGES:=kmod-madwifi -endef - -define Profile/Atheros/Description - Package set compatible with hardware using Atheros WiFi cards -endef -$(eval $(call Profile,Atheros)) - diff --git a/target/linux/brcm63xx/profiles/Broadcom.mk b/target/linux/brcm63xx/profiles/Broadcom.mk deleted file mode 100644 index 5fe71bb525..0000000000 --- a/target/linux/brcm63xx/profiles/Broadcom.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Broadcom - NAME:=Broadcom WiFi (default) - PACKAGES:=kmod-net-bcm43xx -endef - -define Profile/Broadcom/Description - Package set compatible with hardware using Broadcom WiFi cards -endef -$(eval $(call Profile,Broadcom)) - diff --git a/target/linux/brcm63xx/profiles/Ralink.mk b/target/linux/brcm63xx/profiles/Ralink.mk deleted file mode 100644 index 0d78ae4a5a..0000000000 --- a/target/linux/brcm63xx/profiles/Ralink.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Ralink - NAME:=Ralink WiFi - PACKAGES:=kmod-rt61-pci -endef -$(eval $(call Profile,Ralink)) - diff --git a/target/linux/ifxmips/Makefile b/target/linux/ifxmips/Makefile deleted file mode 100644 index de982abf17..0000000000 --- a/target/linux/ifxmips/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (C) 2007 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=mips -BOARD:=ifxmips -BOARDNAME:=Infineon Mips -FEATURES:=squashfs jffs2 -LINUX_VERSION:=2.6.26.5 - -include $(INCLUDE_DIR)/target.mk -DEFAULT_PACKAGES+=uboot-ifxmips - -define Target/Description - Build firmware images for Infineon Mips Controllers -endef - -$(eval $(call BuildTarget)) diff --git a/target/linux/ifxmips/base-files/etc/hotplug.d/button/00-reset b/target/linux/ifxmips/base-files/etc/hotplug.d/button/00-reset deleted file mode 100644 index ef70cd49a5..0000000000 --- a/target/linux/ifxmips/base-files/etc/hotplug.d/button/00-reset +++ /dev/null @@ -1,3 +0,0 @@ -[ "$ACTION" = "released" -a "$BUTTON" = reset ] && { - reboot -} diff --git a/target/linux/ifxmips/base-files/etc/inittab b/target/linux/ifxmips/base-files/etc/inittab deleted file mode 100644 index 7989a7f60e..0000000000 --- a/target/linux/ifxmips/base-files/etc/inittab +++ /dev/null @@ -1,4 +0,0 @@ -::sysinit:/etc/init.d/rcS S boot -::shutdown:/etc/init.d/rcS K stop -ttyS0::askfirst:/bin/ash --login -ttyS1::askfirst:/bin/ash --login diff --git a/target/linux/ifxmips/config-2.6.26 b/target/linux/ifxmips/config-2.6.26 deleted file mode 100644 index 9b506672ec..0000000000 --- a/target/linux/ifxmips/config-2.6.26 +++ /dev/null @@ -1,236 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -# CONFIG_8139TOO is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_POPULATES_NODE_MAP=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ATM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BCM47XX is not set -CONFIG_BITREVERSE=y -# CONFIG_BT is not set -CONFIG_CEVT_R4K=y -CONFIG_CLASSIC_RCU=y -CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2 init=/etc/preinit" -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_LOONGSON2 is not set -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR1=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CSRC_R4K=y -CONFIG_DEVPORT=y -# CONFIG_DM9000 is not set -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_E1000E_ENABLED is not set -CONFIG_EARLY_PRINTK=y -CONFIG_FS_POSIX_ACL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CMOS_UPDATE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_GPIO=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -CONFIG_GPIO_DEVICE=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_HAVE_IDE=y -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_STD_PC_SERIAL_PORT=y -# CONFIG_HIGH_RES_TIMERS is not set -# CONFIG_HOSTAP is not set -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -# CONFIG_I2C is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IDE is not set -CONFIG_IFXMIPS=y -CONFIG_IFXMIPS_EEPROM=y -CONFIG_IFXMIPS_GPIO_RST_BTN=y -# CONFIG_IFXMIPS_MEI is not set -CONFIG_IFXMIPS_MII0=y -# CONFIG_IFXMIPS_PROM_ASC0 is not set -CONFIG_IFXMIPS_PROM_ASC1=y -CONFIG_IFXMIPS_SSC=y -CONFIG_IFXMIPS_WDT=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IRQ_CPU=y -# CONFIG_IWLWIFI_LEDS is not set -CONFIG_KALLSYMS=y -# CONFIG_LEDS_ALIX is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_IFXMIPS=y -# CONFIG_LEMOTE_FULONG is not set -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -CONFIG_MIPS=y -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_IFXMIPS=y -# CONFIG_MTD_JEDECPROBE is not set -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_ONENAND is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PCI is not set -# CONFIG_MTD_PHRAM is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_BANKWIDTH=0 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_START=0x0 -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_OCF_OCF is not set -CONFIG_PAGEFLAGS_EXTENDED=y -# CONFIG_PAGE_SIZE_16KB is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_64KB is not set -# CONFIG_PAGE_SIZE_8KB is not set -CONFIG_PCI=y -# CONFIG_PCIPCWATCHDOG is not set -CONFIG_PCI_DOMAINS=y -CONFIG_PCSPKR_PLATFORM=y -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_R6040 is not set -CONFIG_RFKILL_LEDS=y -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_SCSI_WAIT_SCAN=m -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_IFXMIPS=y -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_SSB_POSSIBLE=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -# CONFIG_TC35815 is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_TICK_ONESHOT is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_TRAD_SIGNALS=y -CONFIG_USB=m -# CONFIG_USB_DWC_HCD is not set -# CONFIG_USB_EHCI_HCD is not set -# CONFIG_USB_ISIGHTFW is not set -CONFIG_USB_SUPPORT=y -# CONFIG_USB_UHCI_HCD is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIA_RHINE is not set -CONFIG_VIDEO_MEDIA=m -CONFIG_VIDEO_V4L1=m -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/Kconfig b/target/linux/ifxmips/files/arch/mips/ifxmips/Kconfig deleted file mode 100644 index 621020f83f..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -# copyright 2007 john crispin - -menu "IFXMips built-in" - -config MTD_IFXMIPS - bool "IFXMips flash map" - default y - -config IFXMIPS_SSC - bool "IFXMips ssc" - default y - -config IFXMIPS_EEPROM - bool "IFXMips eeprom" - default y - -config IFXMIPS_MEI - bool "IFXMips mei" - default y - -config IFXMIPS_GPIO_RST_BTN - bool "Reset Button" - default y - -choice - prompt "prom_printf ASC" - help - Choose which serial port is used, until the console driver is loaded - -config IFXMIPS_PROM_ASC0 - bool "ASC0" - -config IFXMIPS_PROM_ASC1 - bool "ASC1" - -endchoice - - -endmenu - diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/Makefile b/target/linux/ifxmips/files/arch/mips/ifxmips/Makefile deleted file mode 100644 index eb9a77ede4..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o board.o clock.o timer.o gpio.o diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/board.c b/target/linux/ifxmips/files/arch/mips/ifxmips/board.c deleted file mode 100644 index 86a2595fad..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/board.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAX_BOARD_NAME_LEN 32 -#define MAX_IFXMIPS_DEVS 9 - -#define SYSTEM_DANUBE "Danube" -#define SYSTEM_DANUBE_CHIPID1 0x10129083 -#define SYSTEM_DANUBE_CHIPID2 0x3012B083 - -#define SYSTEM_TWINPASS "Twinpass" -#define SYSTEM_TWINPASS_CHIPID 0x3012D083 - -enum { - EASY50712, - EASY4010, - ARV4519, -}; - -extern int ifxmips_pci_external_clock; - -static unsigned int chiprev; -static int cmdline_mac = 0; -char board_name[MAX_BOARD_NAME_LEN + 1] = { 0 }; - -struct ifxmips_board { - int type; - char name[32]; - unsigned int system_type; - struct platform_device **devs; - struct resource reset_resource; - struct resource gpiodev_resource; - struct gpio_led *ifxmips_leds; - struct gpio_led *gpio_leds; - int pci_external_clock; - int num_devs; -}; - -spinlock_t ebu_lock = SPIN_LOCK_UNLOCKED; -EXPORT_SYMBOL_GPL(ebu_lock); - -static unsigned char ifxmips_mii_mac[6]; -static int ifxmips_brn = 0; - -static struct gpio_led_platform_data ifxmips_led_data; - -static struct platform_device -ifxmips_led = -{ - .id = 0, - .name = "ifxmips_led", - .dev = { - .platform_data = (void *) &ifxmips_led_data, - } -}; - -static struct platform_device -ifxmips_gpio = -{ - .id = 0, - .name = "ifxmips_gpio", - .num_resources = 1, -}; - -static struct platform_device -ifxmips_mii = -{ - .id = 0, - .name = "ifxmips_mii0", - .dev = { - .platform_data = ifxmips_mii_mac, - } -}; - -static struct platform_device -ifxmips_wdt = -{ - .id = 0, - .name = "ifxmips_wdt", -}; - -static struct resource -ifxmips_mtd_resource = { - .start = IFXMIPS_FLASH_START, - .end = IFXMIPS_FLASH_START + IFXMIPS_FLASH_MAX - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device -ifxmips_mtd = -{ - .id = 0, - .name = "ifxmips_mtd", - .num_resources = 1, - .resource = &ifxmips_mtd_resource, -}; - -static struct platform_device -ifxmips_gpio_dev = { - .name = "GPIODEV", - .id = -1, - .num_resources = 1, -}; - -#ifdef CONFIG_LEDS_GPIO -static struct gpio_led arv4519_gpio_leds[] = { - { .name = "ifx:green:power", .gpio = 3, .active_low = 1, }, - { .name = "ifx:red:power", .gpio = 7, .active_low = 1, }, - { .name = "ifx:green:adsl", .gpio = 4, .active_low = 1, }, - { .name = "ifx:green:internet", .gpio = 5, .active_low = 1, }, - { .name = "ifx:red:internet", .gpio = 8, .active_low = 1, }, - { .name = "ifx:green:wlan", .gpio = 6, .active_low = 1, }, - { .name = "ifx:green:usb", .gpio = 19, .active_low = 1, }, -}; - -static struct gpio_led_platform_data ifxmips_gpio_led_data; - -static struct platform_device ifxmips_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = (void *) &ifxmips_gpio_led_data, - } -}; -#endif - -struct platform_device *easy50712_devs[] = { - &ifxmips_led, &ifxmips_gpio, &ifxmips_mii, - &ifxmips_mtd, &ifxmips_wdt, &ifxmips_gpio_dev -}; - -struct platform_device *easy4010_devs[] = { - &ifxmips_led, &ifxmips_gpio, &ifxmips_mii, - &ifxmips_mtd, &ifxmips_wdt, &ifxmips_gpio_dev -}; - -struct platform_device *arv5419_devs[] = { - &ifxmips_gpio, &ifxmips_mii, &ifxmips_mtd, &ifxmips_wdt, -#ifdef CONFIG_LEDS_GPIO - &ifxmips_gpio_leds, -#endif -}; - -static struct gpio_led easy50712_leds[] = { - { .name = "ifx:green:test0", .gpio = 0,}, - { .name = "ifx:green:test1", .gpio = 1,}, - { .name = "ifx:green:test2", .gpio = 2,}, - { .name = "ifx:green:test3", .gpio = 3,}, -}; - -static struct gpio_led easy4010_leds[] = { - { .name = "ifx:green:test0", .gpio = 0,}, - { .name = "ifx:green:test1", .gpio = 1,}, - { .name = "ifx:green:test2", .gpio = 2,}, - { .name = "ifx:green:test3", .gpio = 3,}, -}; - -static struct ifxmips_board boards[] = -{ - { - .type = EASY50712, - .name = "EASY50712", - .system_type = SYSTEM_DANUBE_CHIPID1, - .devs = easy50712_devs, - .reset_resource = {.name = "reset", .start = 1, .end = 15,}, - .gpiodev_resource = {.name = "gpio", .start = (1 << 0) | (1 << 1), - .end = (1 << 0) | (1 << 1)}, - .ifxmips_leds = easy50712_leds, - }, { - .type = EASY4010, - .name = "EASY4010", - .system_type = SYSTEM_TWINPASS_CHIPID, - .devs = easy4010_devs, - .reset_resource = {.name = "reset", .start = 1, .end = 15}, - .gpiodev_resource = {.name = "gpio", .start = (1 << 0) | (1 << 1), - .end = (1 << 0) | (1 << 1)}, - .ifxmips_leds = easy4010_leds, - }, { - .type = ARV4519, - .name = "ARV4519", - .system_type = SYSTEM_DANUBE_CHIPID2, - .devs = arv5419_devs, - .reset_resource = {.name = "reset", .start = 1, .end = 14}, - .pci_external_clock = 1, - .gpio_leds = arv4519_gpio_leds, - }, -}; - -const char* -get_system_type(void) -{ - chiprev = ifxmips_r32(IFXMIPS_MPS_CHIPID); - switch(chiprev) - { - case SYSTEM_DANUBE_CHIPID1: - case SYSTEM_DANUBE_CHIPID2: - return SYSTEM_DANUBE; - - case SYSTEM_TWINPASS_CHIPID: - return SYSTEM_TWINPASS; - } - - return BOARD_SYSTEM_TYPE; -} - -static int __init -ifxmips_set_board_type(char *str) -{ - str = strchr(str, '='); - if(!str) - goto out; - str++; - if(strlen(str) > MAX_BOARD_NAME_LEN) - goto out; - strncpy(board_name, str, MAX_BOARD_NAME_LEN); - printk("bootloader told us, that this is a %s board\n", board_name); -out: - return 1; -} -__setup("ifxmips_board", ifxmips_set_board_type); - -static int __init -ifxmips_set_mii0_mac(char *str) -{ -#define IS_HEX(x) \ - (((x >='0' && x <= '9') || (x >='a' && x <= 'f') || (x >='A' && x <= 'F'))?(1):(0)) - int i; - str = strchr(str, '='); - if(!str) - goto out; - str++; - if(strlen(str) != 17) - goto out; - for(i = 0; i < 6; i++) - { - if(!IS_HEX(str[3 * i]) || !IS_HEX(str[(3 * i) + 1])) - goto out; - if((i != 5) && (str[(3 * i) + 2] != ':')) - goto out; - ifxmips_mii_mac[i] = simple_strtoul(&str[3 * i], NULL, 16); - } - if(is_valid_ether_addr(ifxmips_mii_mac)) - cmdline_mac = 1; -out: - return 1; -} -__setup("mii0_mac", ifxmips_set_mii0_mac); - -int -ifxmips_find_brn_block(void){ - unsigned char temp[8]; - memcpy_fromio(temp, (void*)KSEG1ADDR(IFXMIPS_FLASH_START + 0x800000 - 0x10000), 8); - if(memcmp(temp, "BRN-BOOT", 8) == 0) - { - if(!cmdline_mac) - memcpy_fromio(ifxmips_mii_mac, (void*)KSEG1ADDR(IFXMIPS_FLASH_START + 0x800000 - 0x10000 + 0x16), 6); - cmdline_mac = 1; - return 1; - } else { - return 0; - } -} - -int -ifxmips_has_brn_block(void) -{ - return ifxmips_brn; -} -EXPORT_SYMBOL(ifxmips_has_brn_block); - -struct ifxmips_board* -ifxmips_find_board(void) -{ - int i; - if(!*board_name) - return 0; - for(i = 0; i < ARRAY_SIZE(boards); i++) - if((boards[i].system_type == chiprev) && (!strcmp(boards[i].name, board_name))) - return &boards[i]; - return 0; -} - -int __init -ifxmips_init_devices(void) -{ - struct ifxmips_board *board = ifxmips_find_board(); - - chiprev = ifxmips_r32(IFXMIPS_MPS_CHIPID); - ifxmips_brn = ifxmips_find_brn_block(); - - if(!cmdline_mac) - random_ether_addr(ifxmips_mii_mac); - - if(!board) - { - switch(chiprev) - { - case SYSTEM_DANUBE_CHIPID1: - case SYSTEM_DANUBE_CHIPID2: - board = &boards[0]; - break; - case SYSTEM_TWINPASS_CHIPID: - board = &boards[1]; - break; - } - } - - switch(board->type) - { - case EASY50712: - board->num_devs = ARRAY_SIZE(easy50712_devs); - ifxmips_led_data.num_leds = ARRAY_SIZE(easy50712_leds); - break; - case EASY4010: - board->num_devs = ARRAY_SIZE(easy4010_devs); - ifxmips_led_data.num_leds = ARRAY_SIZE(easy4010_leds); - break; - case ARV4519: - gpio_set_value(3, 0); - gpio_set_value(4, 0); - gpio_set_value(5, 0); - gpio_set_value(6, 0); - gpio_set_value(7, 1); - gpio_set_value(8, 1); - gpio_set_value(19, 0); - board->num_devs = ARRAY_SIZE(arv5419_devs); -#ifdef CONFIG_LEDS_GPIO - ifxmips_gpio_led_data.num_leds = ARRAY_SIZE(arv4519_gpio_leds); -#endif - break; - } -#ifdef CONFIG_LEDS_GPIO - ifxmips_gpio_led_data.leds = board->gpio_leds; -#endif - ifxmips_led_data.leds = board->ifxmips_leds; - - printk("%s:%s[%d]adding %d devs\n", __FILE__, __func__, __LINE__, board->num_devs); - - ifxmips_gpio.resource = &board->reset_resource; - ifxmips_gpio_dev.resource = &board->gpiodev_resource; - if(board->pci_external_clock) - ifxmips_pci_external_clock = 1; - printk("using board definition %s\n", board->name); - return platform_add_devices(board->devs, board->num_devs); -} - -arch_initcall(ifxmips_init_devices); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c b/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c deleted file mode 100644 index fc3658b71f..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 Xu Liang, infineon - * Copyright (C) 2008 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000 -#define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000 - -#define BASIS_INPUT_CRYSTAL_USB 12000000 - -#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) - - -#define CGU_PLL0_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31)) -#define CGU_PLL0_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30)) -#define CGU_PLL0_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28)) -#define CGU_PLL0_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27)) -#define CGU_PLL1_SRC (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31)) -#define CGU_PLL1_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30)) -#define CGU_PLL1_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28)) -#define CGU_PLL1_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27)) -#define CGU_PLL2_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20)) -#define CGU_PLL2_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19)) -#define CGU_SYS_FPI_SEL (1 << 6) -#define CGU_SYS_DDR_SEL 0x3 -#define CGU_PLL0_SRC (1 << 29) - -#define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17) -#define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6) -#define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2) -#define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17) -#define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6) -#define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2) -#define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17) -#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13) -#define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6) -#define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2) -#define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20) - -static unsigned int cgu_get_pll0_fdiv(void); -unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; - -#define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3] - - -static inline unsigned int -get_input_clock(int pll) -{ - switch(pll) - { - case 0: - if(ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC) - return BASIS_INPUT_CRYSTAL_USB; - else if(CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_INPUT_CLOCK_FREQUENCY_1; - else - return BASIC_INPUT_CLOCK_FREQUENCY_2; - case 1: - if(CGU_PLL1_SRC) - return BASIS_INPUT_CRYSTAL_USB; - else if(CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_INPUT_CLOCK_FREQUENCY_1; - else - return BASIC_INPUT_CLOCK_FREQUENCY_2; - case 2: - switch(CGU_PLL2_SRC) - { - case 0: - return cgu_get_pll0_fdiv(); - case 1: - return CGU_PLL2_PHASE_DIVIDER_ENABLE ? BASIC_INPUT_CLOCK_FREQUENCY_1 : BASIC_INPUT_CLOCK_FREQUENCY_2; - case 2: - return BASIS_INPUT_CRYSTAL_USB; - } - default: - return 0; - } -} - -static inline unsigned int -cal_dsm(int pll, unsigned int num, unsigned int den) -{ - u64 res, clock = get_input_clock(pll); - - res = num * clock; - do_div(res, den); - return res; -} - -static inline unsigned int -mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K) -{ - unsigned int num = ((N + 1) << 10) + K; - unsigned int den = (M + 1) << 10; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int -ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K) -{ - unsigned int num = ((N + 1) << 11) + K + 512; - unsigned int den = (M + 1) << 11; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int -ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K) -{ - unsigned int num = K >= 512 ? - ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; - unsigned int den = (M + 1) << 12; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int -dsm(int pll, unsigned int M, unsigned int N, unsigned int K, - unsigned int dsmsel, unsigned int phase_div_en) -{ - if(!dsmsel) - return mash_dsm(pll, M, N, K); - else if(!phase_div_en) - return mash_dsm(pll, M, N, K); - else - return ssff_dsm_2(pll, M, N, K); -} - -static inline unsigned int -cgu_get_pll0_fosc(void) -{ - if(CGU_PLL0_BYPASS) - return get_input_clock(0); - else - return !CGU_PLL0_CFG_FRAC_EN - ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE) - : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK, - CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE); -} - -static unsigned int -cgu_get_pll0_fdiv(void) -{ - register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; - return (cgu_get_pll0_fosc() + (div >> 1)) / div; -} - -unsigned int -cgu_get_io_region_clock(void) -{ - register unsigned int ret = cgu_get_pll0_fosc(); - switch(ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) - { - default: - case 0: - return (ret + 1) / 2; - case 1: - return (ret * 2 + 2) / 5; - case 2: - return (ret + 1) / 3; - case 3: - return (ret + 2) / 4; - } -} - -unsigned int -cgu_get_fpi_bus_clock(int fpi) -{ - register unsigned int ret = cgu_get_io_region_clock(); - if((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL)) - ret >>= 1; - return ret; -} - -void cgu_setup_pci_clk(int external_clock) -{ - //set clock to 33Mhz - ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR); - ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR); - if(external_clock) - { - ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR); - ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR); - } else { - ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR); - ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR); - } -} - -unsigned int -ifxmips_get_cpu_hz(void) -{ - unsigned int ddr_clock = DDR_HZ; - switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc) - { - case 0: - return CLOCK_333M; - case 4: - return ddr_clock; - } - return ddr_clock << 1; -} -EXPORT_SYMBOL(ifxmips_get_cpu_hz); - -unsigned int -ifxmips_get_fpi_hz(void) -{ - unsigned int ddr_clock = DDR_HZ; - if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40) - return ddr_clock >> 1; - return ddr_clock; -} -EXPORT_SYMBOL(ifxmips_get_fpi_hz); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c b/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c deleted file mode 100644 index a57b803e53..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c +++ /dev/null @@ -1,758 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/*25 descriptors for each dma channel,4096/8/20=25.xx*/ -#define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25 - -#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */ -#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */ -#define DMA_INT_BUDGET 100 /*budget for interrupt handling */ -#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */ - -extern void ifxmips_mask_and_ack_irq (unsigned int irq_nr); -extern void ifxmips_enable_irq (unsigned int irq_nr); -extern void ifxmips_disable_irq (unsigned int irq_nr); - -u64 *g_desc_list; -_dma_device_info dma_devs[MAX_DMA_DEVICE_NUM]; -_dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM]; - -char global_device_name[MAX_DMA_DEVICE_NUM][20] = - { {"PPE"}, {"DEU"}, {"SPI"}, {"SDIO"}, {"MCTRL0"}, {"MCTRL1"} }; - -_dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = { - {"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0}, - {"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0}, - {"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1}, - {"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1}, - {"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2}, - {"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2}, - {"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3}, - {"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3}, - {"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0}, - {"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0}, - {"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1}, - {"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1}, - {"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0}, - {"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0}, - {"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0}, - {"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0}, - {"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0}, - {"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0}, - {"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1}, - {"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1} -}; - -_dma_chan_map *chan_map = default_dma_map; -volatile u32 g_ifxmips_dma_int_status = 0; -volatile int g_ifxmips_dma_in_process = 0;/*0=not in process,1=in process*/ - -void do_dma_tasklet (unsigned long); -DECLARE_TASKLET (dma_tasklet, do_dma_tasklet, 0); - -u8* -common_buffer_alloc (int len, int *byte_offset, void **opt) -{ - u8 *buffer = (u8 *) kmalloc (len * sizeof (u8), GFP_KERNEL); - - *byte_offset = 0; - - return buffer; -} - -void -common_buffer_free (u8 *dataptr, void *opt) -{ - if (dataptr) - kfree(dataptr); -} - -void -enable_ch_irq (_dma_channel_info *pCh) -{ - int chan_no = (int)(pCh - dma_chan); - int flag; - - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(0x4a, IFXMIPS_DMA_CIE); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN); - local_irq_restore(flag); - ifxmips_enable_irq(pCh->irq); -} - -void -disable_ch_irq (_dma_channel_info *pCh) -{ - int flag; - int chan_no = (int) (pCh - dma_chan); - - local_irq_save(flag); - g_ifxmips_dma_int_status &= ~(1 << chan_no); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(0, IFXMIPS_DMA_CIE); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); - local_irq_restore(flag); - ifxmips_mask_and_ack_irq(pCh->irq); -} - -void -open_chan (_dma_channel_info *pCh) -{ - int flag; - int chan_no = (int)(pCh - dma_chan); - - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL); - if(pCh->dir == IFXMIPS_DMA_RX) - enable_ch_irq(pCh); - local_irq_restore(flag); -} - -void -close_chan(_dma_channel_info *pCh) -{ - int flag; - int chan_no = (int) (pCh - dma_chan); - - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - disable_ch_irq(pCh); - local_irq_restore(flag); -} - -void -reset_chan (_dma_channel_info *pCh) -{ - int chan_no = (int) (pCh - dma_chan); - - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL); -} - -void -rx_chan_intr_handler (int chan_no) -{ - _dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev; - _dma_channel_info *pCh = &dma_chan[chan_no]; - struct rx_desc *rx_desc_p; - int tmp; - int flag; - - /*handle command complete interrupt */ - rx_desc_p = (struct rx_desc*)pCh->desc_base + pCh->curr_desc; - if (rx_desc_p->status.field.OWN == CPU_OWN - && rx_desc_p->status.field.C - && rx_desc_p->status.field.data_length < 1536){ - /*Every thing is correct, then we inform the upper layer */ - pDev->current_rx_chan = pCh->rel_chan_no; - if(pDev->intr_handler) - pDev->intr_handler(pDev, RCV_INT); - pCh->weight--; - } else { - local_irq_save(flag); - tmp = ifxmips_r32(IFXMIPS_DMA_CS); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS); - ifxmips_w32(tmp, IFXMIPS_DMA_CS); - g_ifxmips_dma_int_status &= ~(1 << chan_no); - local_irq_restore(flag); - ifxmips_enable_irq(dma_chan[chan_no].irq); - } -} - -inline void -tx_chan_intr_handler (int chan_no) -{ - _dma_device_info *pDev = (_dma_device_info*)dma_chan[chan_no].dma_dev; - _dma_channel_info *pCh = &dma_chan[chan_no]; - int tmp; - int flag; - - local_irq_save(flag); - tmp = ifxmips_r32(IFXMIPS_DMA_CS); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS); - ifxmips_w32(tmp, IFXMIPS_DMA_CS); - g_ifxmips_dma_int_status &= ~(1 << chan_no); - local_irq_restore(flag); - pDev->current_tx_chan = pCh->rel_chan_no; - if (pDev->intr_handler) - pDev->intr_handler(pDev, TRANSMIT_CPT_INT); -} - -void -do_dma_tasklet (unsigned long unused) -{ - int i; - int chan_no = 0; - int budget = DMA_INT_BUDGET; - int weight = 0; - int flag; - - while (g_ifxmips_dma_int_status) - { - if (budget-- < 0) - { - tasklet_schedule(&dma_tasklet); - return; - } - chan_no = -1; - weight = 0; - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { - if ((g_ifxmips_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) - { - if (dma_chan[i].weight > weight) - { - chan_no = i; - weight = dma_chan[chan_no].weight; - } - } - } - - if (chan_no >= 0) - { - if (chan_map[chan_no].dir == IFXMIPS_DMA_RX) - rx_chan_intr_handler(chan_no); - else - tx_chan_intr_handler(chan_no); - } else { - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { - dma_chan[i].weight = dma_chan[i].default_weight; - } - } - } - - local_irq_save(flag); - g_ifxmips_dma_in_process = 0; - if (g_ifxmips_dma_int_status) - { - g_ifxmips_dma_in_process = 1; - tasklet_schedule(&dma_tasklet); - } - local_irq_restore(flag); -} - -irqreturn_t -dma_interrupt (int irq, void *dev_id) -{ - _dma_channel_info *pCh; - int chan_no = 0; - int tmp; - - pCh = (_dma_channel_info*)dev_id; - chan_no = (int)(pCh - dma_chan); - if (chan_no < 0 || chan_no > 19) - BUG(); - - tmp = ifxmips_r32(IFXMIPS_DMA_IRNEN); - ifxmips_w32(0, IFXMIPS_DMA_IRNEN); - g_ifxmips_dma_int_status |= 1 << chan_no; - ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN); - ifxmips_mask_and_ack_irq(irq); - - if (!g_ifxmips_dma_in_process) - { - g_ifxmips_dma_in_process = 1; - tasklet_schedule(&dma_tasklet); - } - - return IRQ_HANDLED; -} - -_dma_device_info* -dma_device_reserve (char *dev_name) -{ - int i; - - for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) - { - if (strcmp(dev_name, dma_devs[i].device_name) == 0) - { - if (dma_devs[i].reserved) - return NULL; - dma_devs[i].reserved = 1; - break; - } - } - - return &dma_devs[i]; -} - -void -dma_device_release (_dma_device_info *dev) -{ - dev->reserved = 0; -} - -void -dma_device_register(_dma_device_info *dev) -{ - int i, j; - int chan_no = 0; - u8 *buffer; - int byte_offset; - int flag; - _dma_device_info *pDev; - _dma_channel_info *pCh; - struct rx_desc *rx_desc_p; - struct tx_desc *tx_desc_p; - - for (i = 0; i < dev->max_tx_chan_num; i++) - { - pCh = dev->tx_chan[i]; - if (pCh->control == IFXMIPS_DMA_CH_ON) - { - chan_no = (int)(pCh - dma_chan); - for (j = 0; j < pCh->desc_len; j++) - { - tx_desc_p = (struct tx_desc*)pCh->desc_base + j; - memset(tx_desc_p, 0, sizeof(struct tx_desc)); - } - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - /*check if the descriptor length is changed */ - if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len) - ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN); - - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2){}; - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN); - ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL); /*reset and enable channel,enable channel later */ - local_irq_restore(flag); - } - } - - for (i = 0; i < dev->max_rx_chan_num; i++) - { - pCh = dev->rx_chan[i]; - if (pCh->control == IFXMIPS_DMA_CH_ON) - { - chan_no = (int)(pCh - dma_chan); - - for (j = 0; j < pCh->desc_len; j++) - { - rx_desc_p = (struct rx_desc*)pCh->desc_base + j; - pDev = (_dma_device_info*)(pCh->dma_dev); - buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void*)&(pCh->opt[j])); - if (!buffer) - break; - - dma_cache_inv((unsigned long) buffer, pCh->packet_size); - - rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer); - rx_desc_p->status.word = 0; - rx_desc_p->status.field.byte_offset = byte_offset; - rx_desc_p->status.field.OWN = DMA_OWN; - rx_desc_p->status.field.data_length = pCh->packet_size; - } - - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - /*check if the descriptor length is changed */ - if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len) - ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2){}; - ifxmips_w32(0x0a, IFXMIPS_DMA_CIE); /*fix me, should enable all the interrupts here? */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN); - ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL); - local_irq_restore(flag); - ifxmips_enable_irq(dma_chan[chan_no].irq); - } - } -} - -void -dma_device_unregister (_dma_device_info *dev) -{ - int i, j; - int chan_no; - _dma_channel_info *pCh; - struct rx_desc *rx_desc_p; - struct tx_desc *tx_desc_p; - int flag; - - for (i = 0; i < dev->max_tx_chan_num; i++) - { - pCh = dev->tx_chan[i]; - if (pCh->control == IFXMIPS_DMA_CH_ON) - { - chan_no = (int)(dev->tx_chan[i] - dma_chan); - local_irq_save (flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - pCh->curr_desc = 0; - pCh->prev_desc = 0; - pCh->control = IFXMIPS_DMA_CH_OFF; - ifxmips_w32(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) {}; - local_irq_restore (flag); - - for (j = 0; j < pCh->desc_len; j++) - { - tx_desc_p = (struct tx_desc*)pCh->desc_base + j; - if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) - || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) - { - dev->buffer_free ((u8 *) __va (tx_desc_p->Data_Pointer), (void*)pCh->opt[j]); - } - tx_desc_p->status.field.OWN = CPU_OWN; - memset (tx_desc_p, 0, sizeof (struct tx_desc)); - } - //TODO should free buffer that is not transferred by dma - } - } - - for (i = 0; i < dev->max_rx_chan_num; i++) - { - pCh = dev->rx_chan[i]; - chan_no = (int)(dev->rx_chan[i] - dma_chan); - ifxmips_disable_irq(pCh->irq); - - local_irq_save(flag); - g_ifxmips_dma_int_status &= ~(1 << chan_no); - pCh->curr_desc = 0; - pCh->prev_desc = 0; - pCh->control = IFXMIPS_DMA_CH_OFF; - - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) {}; - - local_irq_restore (flag); - for (j = 0; j < pCh->desc_len; j++) - { - rx_desc_p = (struct rx_desc *) pCh->desc_base + j; - if ((rx_desc_p->status.field.OWN == CPU_OWN - && rx_desc_p->status.field.C) - || (rx_desc_p->status.field.OWN == DMA_OWN - && rx_desc_p->status.field.data_length > 0)) { - dev->buffer_free ((u8 *) - __va (rx_desc_p-> - Data_Pointer), - (void *) pCh->opt[j]); - } - } - } -} - -int -dma_device_read (struct dma_device_info *dma_dev, u8 ** dataptr, void **opt) -{ - u8 *buf; - int len; - int byte_offset = 0; - void *p = NULL; - _dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan]; - struct rx_desc *rx_desc_p; - - /*get the rx data first */ - rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc; - if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C)) - { - return 0; - } - - buf = (u8 *) __va (rx_desc_p->Data_Pointer); - *(u32*)dataptr = (u32)buf; - len = rx_desc_p->status.field.data_length; - - if (opt) - { - *(int*)opt = (int)pCh->opt[pCh->curr_desc]; - } - - /*replace with a new allocated buffer */ - buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p); - - if (buf) - { - dma_cache_inv ((unsigned long) buf, - pCh->packet_size); - pCh->opt[pCh->curr_desc] = p; - wmb (); - - rx_desc_p->Data_Pointer = (u32) CPHYSADDR ((u32) buf); - rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size; - wmb (); - } else { - *(u32 *) dataptr = 0; - if (opt) - *(int *) opt = 0; - len = 0; - } - - /*increase the curr_desc pointer */ - pCh->curr_desc++; - if (pCh->curr_desc == pCh->desc_len) - pCh->curr_desc = 0; - - return len; -} - -int -dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *opt) -{ - int flag; - u32 tmp, byte_offset; - _dma_channel_info *pCh; - int chan_no; - struct tx_desc *tx_desc_p; - local_irq_save (flag); - - pCh = dma_dev->tx_chan[dma_dev->current_tx_chan]; - chan_no = (int)(pCh - (_dma_channel_info *) dma_chan); - - tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->prev_desc; - while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) - { - dma_dev->buffer_free((u8 *) __va (tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]); - memset(tx_desc_p, 0, sizeof (struct tx_desc)); - pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len); - tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->prev_desc; - } - tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->curr_desc; - /*Check whether this descriptor is available */ - if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) - { - /*if not , the tell the upper layer device */ - dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT); - local_irq_restore(flag); - printk (KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__); - - return 0; - } - pCh->opt[pCh->curr_desc] = opt; - /*byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */ - byte_offset = ((u32) CPHYSADDR ((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4); - dma_cache_wback ((unsigned long) dataptr, len); - wmb (); - tx_desc_p->Data_Pointer = (u32) CPHYSADDR ((u32) dataptr) - byte_offset; - wmb (); - tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len; - wmb (); - - pCh->curr_desc++; - if (pCh->curr_desc == pCh->desc_len) - pCh->curr_desc = 0; - - /*Check whether this descriptor is available */ - tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc; - if (tx_desc_p->status.field.OWN == DMA_OWN) - { - /*if not , the tell the upper layer device */ - dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT); - } - - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - tmp = ifxmips_r32(IFXMIPS_DMA_CCTRL); - - if (!(tmp & 1)) - pCh->open (pCh); - - local_irq_restore (flag); - - return len; -} - -int -map_dma_chan(_dma_chan_map *map) -{ - int i, j; - int result; - - for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) - { - strcpy(dma_devs[i].device_name, global_device_name[i]); - } - - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { - dma_chan[i].irq = map[i].irq; - result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, "dma-core", (void*)&dma_chan[i]); - if (result) - { - printk("error, cannot get dma_irq!\n"); - free_irq(dma_chan[i].irq, (void *) &dma_interrupt); - - return -EFAULT; - } - } - - for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) - { - dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */ - dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */ - dma_devs[i].max_rx_chan_num = 0; - dma_devs[i].max_tx_chan_num = 0; - dma_devs[i].buffer_alloc = &common_buffer_alloc; - dma_devs[i].buffer_free = &common_buffer_free; - dma_devs[i].intr_handler = NULL; - dma_devs[i].tx_burst_len = 4; - dma_devs[i].rx_burst_len = 4; - if (i == 0) - { - ifxmips_w32(0, IFXMIPS_DMA_PS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL); /*enable dma drop */ - } - - if (i == 1) - { - ifxmips_w32(1, IFXMIPS_DMA_PS); - ifxmips_w32(0x14, IFXMIPS_DMA_PCTRL); /*deu port setting */ - } - - for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) - { - dma_chan[j].byte_offset = 0; - dma_chan[j].open = &open_chan; - dma_chan[j].close = &close_chan; - dma_chan[j].reset = &reset_chan; - dma_chan[j].enable_irq = &enable_ch_irq; - dma_chan[j].disable_irq = &disable_ch_irq; - dma_chan[j].rel_chan_no = map[j].rel_chan_no; - dma_chan[j].control = IFXMIPS_DMA_CH_OFF; - dma_chan[j].default_weight = IFXMIPS_DMA_CH_DEFAULT_WEIGHT; - dma_chan[j].weight = dma_chan[j].default_weight; - dma_chan[j].curr_desc = 0; - dma_chan[j].prev_desc = 0; - } - - for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) - { - if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) - { - if (map[j].dir == IFXMIPS_DMA_RX) - { - dma_chan[j].dir = IFXMIPS_DMA_RX; - dma_devs[i].max_rx_chan_num++; - dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j]; - dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri; - dma_chan[j].dma_dev = (void*)&dma_devs[i]; - } else if(map[j].dir == IFXMIPS_DMA_TX) - { /*TX direction */ - dma_chan[j].dir = IFXMIPS_DMA_TX; - dma_devs[i].max_tx_chan_num++; - dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j]; - dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri; - dma_chan[j].dma_dev = (void*)&dma_devs[i]; - } else { - printk ("WRONG DMA MAP!\n"); - } - } - } - } - - return 0; -} - -void -dma_chip_init(void) -{ - int i; - - // enable DMA from PMU - ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA); - - // reset DMA - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL); - - // diable all interrupts - ifxmips_w32(0, IFXMIPS_DMA_IRNEN); - - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { - ifxmips_w32(i, IFXMIPS_DMA_CS); - ifxmips_w32(0x2, IFXMIPS_DMA_CCTRL); - ifxmips_w32(0x80000040, IFXMIPS_DMA_CPOLL); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL); - - } -} - -int -ifxmips_dma_init (void) -{ - int i; - - dma_chip_init(); - if (map_dma_chan(default_dma_map)) - BUG(); - - g_desc_list = (u64*)KSEG1ADDR(__get_free_page(GFP_DMA)); - - if (g_desc_list == NULL) - { - printk("no memory for desriptor\n"); - return -ENOMEM; - } - - memset(g_desc_list, 0, PAGE_SIZE); - - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { - dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8; - dma_chan[i].curr_desc = 0; - dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET; - - ifxmips_w32(i, IFXMIPS_DMA_CS); - ifxmips_w32((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA); - ifxmips_w32(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN); - } - - return 0; -} - -arch_initcall(ifxmips_dma_init); - -void -dma_cleanup(void) -{ - int i; - - free_page(KSEG0ADDR((unsigned long) g_desc_list)); - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - free_irq(dma_chan[i].irq, (void*)&dma_interrupt); -} - -EXPORT_SYMBOL (dma_device_reserve); -EXPORT_SYMBOL (dma_device_release); -EXPORT_SYMBOL (dma_device_register); -EXPORT_SYMBOL (dma_device_unregister); -EXPORT_SYMBOL (dma_device_read); -EXPORT_SYMBOL (dma_device_write); - -MODULE_LICENSE ("GPL"); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c b/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c deleted file mode 100644 index eef5146698..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2004 btxu Generate from INCA-IP project - * Copyright (C) 2005 Jin-Sze.Sow Comments edited - * Copyright (C) 2006 Huang Xiaogang Modification & verification on Danube chip - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAX_PORTS 2 -#define PINS_PER_PORT 16 - -#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN - -unsigned int rst_port = 1; -unsigned int rst_pin = 15; -static struct timer_list rst_button_timer; - -extern struct sock *uevent_sock; -extern u64 uevent_next_seqnum(void); -static unsigned long seen; -static int pressed = 0; - -struct event_t { - struct work_struct wq; - int set; - unsigned long jiffies; -}; -#endif - -#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; } -int -ifxmips_port_reserve_pin(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - printk("%s : call to obseleted function\n", __func__); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_reserve_pin); - -int -ifxmips_port_free_pin(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - printk("%s : call to obseleted function\n", __func__); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_free_pin); - -int -ifxmips_port_set_open_drain(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_OD + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_open_drain); - -int -ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_OD + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_open_drain); - -int -ifxmips_port_set_pudsel(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_pudsel); - -int -ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_pudsel); - -int -ifxmips_port_set_puden(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_puden); - -int -ifxmips_port_clear_puden(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_puden); - -int -ifxmips_port_set_stoff(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_STOFF + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_stoff); - -int -ifxmips_port_clear_stoff(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_STOFF + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_stoff); - -int -ifxmips_port_set_dir_out(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_DIR + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_dir_out); - -int -ifxmips_port_set_dir_in(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_DIR + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_dir_in); - -int -ifxmips_port_set_output(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_OUT + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_output); - -int -ifxmips_port_clear_output(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_OUT + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_output); - -int -ifxmips_port_get_input(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin)) - return 0; - else - return 1; -} -EXPORT_SYMBOL(ifxmips_port_get_input); - -int -ifxmips_port_set_altsel0(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_altsel0); - -int -ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_altsel0); - -int -ifxmips_port_set_altsel1(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_altsel1); - -int -ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_altsel1); - -#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN -static inline void -add_msg(struct sk_buff *skb, char *msg) -{ - char *scratch; - scratch = skb_put(skb, strlen(msg) + 1); - sprintf(scratch, msg); -} - -static void -hotplug_button(struct work_struct *wq) -{ - struct sk_buff *skb; - struct event_t *event; - size_t len; - char *scratch, *s; - char buf[128]; - - event = container_of(wq, struct event_t, wq); - if(!uevent_sock) - goto done; - - s = event->set ? "pressed" : "released"; - len = strlen(s) + 2; - skb = alloc_skb(len + 2048, GFP_KERNEL); - if(!skb) - goto done; - - scratch = skb_put(skb, len); - sprintf(scratch, "%s@",s); - add_msg(skb, "HOME=/"); - add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); - add_msg(skb, "SUBSYSTEM=button"); - add_msg(skb, "BUTTON=reset"); - add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); - sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); - add_msg(skb, buf); - snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); - add_msg(skb, buf); - - NETLINK_CB(skb).dst_group = 1; - netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); -done: - kfree(event); -} - -static void -reset_button_poll(unsigned long unused) -{ - struct event_t *event; - - rst_button_timer.expires = jiffies + (HZ / 4); - add_timer(&rst_button_timer); - - if (pressed != ifxmips_port_get_input(rst_port, rst_pin)) - { - if(pressed) - pressed = 0; - else - pressed = 1; - event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); - if (!event) - { - printk("Could not alloc hotplug event\n"); - return; - } - event->set = pressed; - event->jiffies = jiffies; - INIT_WORK(&event->wq, (void *)(void *)hotplug_button); - schedule_work(&event->wq); - seen = jiffies; - } -} -#endif - -static int -ifxmips_gpio_probe(struct platform_device *dev) -{ - int retval = 0; - -#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN - rst_port = dev->resource[0].start; - rst_pin = dev->resource[0].end; - ifxmips_port_set_open_drain(rst_port, rst_pin); - ifxmips_port_clear_altsel0(rst_port, rst_pin); - ifxmips_port_clear_altsel1(rst_port, rst_pin); - ifxmips_port_set_dir_in(rst_port, rst_pin); - seen = jiffies; - init_timer(&rst_button_timer); - rst_button_timer.function = reset_button_poll; - rst_button_timer.expires = jiffies + HZ; - add_timer(&rst_button_timer); -#endif - return retval; -} - -static int -ifxmips_gpio_remove(struct platform_device *pdev) -{ -#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN - del_timer_sync(&rst_button_timer); -#endif - return 0; -} - -static struct -platform_driver ifxmips_gpio_driver = { - .probe = ifxmips_gpio_probe, - .remove = ifxmips_gpio_remove, - .driver = { - .name = "ifxmips_gpio", - .owner = THIS_MODULE, - }, -}; - -int __init -ifxmips_gpio_init(void) -{ - int ret = platform_driver_register(&ifxmips_gpio_driver); - if (ret) - printk(KERN_INFO "ifxmips_gpio : Error registering platfom driver!"); - return ret; -} - -void __exit -ifxmips_gpio_exit(void) -{ - platform_driver_unregister(&ifxmips_gpio_driver); -} - -module_init(ifxmips_gpio_init); -module_exit(ifxmips_gpio_exit); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c b/target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c deleted file mode 100644 index b47074d79c..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 Wu Qi Ming infineon - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -void -ifxmips_disable_irq(unsigned int irq_nr) -{ - int i; - u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER; - - irq_nr -= INT_NUM_IRQ0; - for(i = 0; i <= 4; i++) - { - if(irq_nr < INT_NUM_IM_OFFSET){ - ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier); - return; - } - ifxmips_ier += IFXMIPS_ICU_OFFSET; - irq_nr -= INT_NUM_IM_OFFSET; - } -} -EXPORT_SYMBOL(ifxmips_disable_irq); - -void -ifxmips_mask_and_ack_irq(unsigned int irq_nr) -{ - int i; - u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER; - u32 *ifxmips_isr = IFXMIPS_ICU_IM0_ISR; - - irq_nr -= INT_NUM_IRQ0; - for(i = 0; i <= 4; i++) - { - if(irq_nr < INT_NUM_IM_OFFSET) - { - ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier); - ifxmips_w32((1 << irq_nr ), ifxmips_isr); - return; - } - ifxmips_ier += IFXMIPS_ICU_OFFSET; - ifxmips_isr += IFXMIPS_ICU_OFFSET; - irq_nr -= INT_NUM_IM_OFFSET; - } -} -EXPORT_SYMBOL(ifxmips_mask_and_ack_irq); - -void -ifxmips_enable_irq(unsigned int irq_nr) -{ - int i; - u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER; - - irq_nr -= INT_NUM_IRQ0; - for(i = 0; i <= 4; i++) - { - if(irq_nr < INT_NUM_IM_OFFSET) - { - ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr ), ifxmips_ier); - return; - } - ifxmips_ier += IFXMIPS_ICU_OFFSET; - irq_nr -= INT_NUM_IM_OFFSET; - } -} -EXPORT_SYMBOL(ifxmips_enable_irq); - -static unsigned int -ifxmips_startup_irq(unsigned int irq) -{ - ifxmips_enable_irq(irq); - return 0; -} - -static void -ifxmips_end_irq(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - ifxmips_enable_irq (irq); -} - -static struct hw_interrupt_type -ifxmips_irq_type = { - "IFXMIPS", - .startup = ifxmips_startup_irq, - .enable = ifxmips_enable_irq, - .disable = ifxmips_disable_irq, - .unmask = ifxmips_enable_irq, - .ack = ifxmips_end_irq, - .mask = ifxmips_disable_irq, - .mask_ack = ifxmips_mask_and_ack_irq, - .end = ifxmips_end_irq, -}; - -static inline int -ls1bit32(unsigned long x) -{ - __asm__ ( - ".set push \n" - ".set mips32 \n" - "clz %0, %1 \n" - ".set pop \n" - : "=r" (x) - : "r" (x)); - return 31 - x; -} - -void -ifxmips_hw_irqdispatch(int module) -{ - u32 irq; - - irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET)); - if(irq == 0) - return; - - /* we need to do this due to a silicon bug */ - irq = ls1bit32(irq); - do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); - - if((irq == 22) && (module == 0)){ - ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT); - } -} - -asmlinkage void -plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - unsigned int i; - - if(pending & CAUSEF_IP7) - { - do_IRQ(MIPS_CPU_TIMER_IRQ); - goto out; - } else { - for(i = 0; i < 5; i++) - { - if(pending & (CAUSEF_IP2 << i)) - { - ifxmips_hw_irqdispatch(i); - goto out; - } - } - } - printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); - -out: - return; -} - -static struct irqaction -cascade = { - .handler = no_action, - .flags = IRQF_DISABLED, - .name = "cascade", -}; - -void __init -arch_init_irq(void) -{ - int i; - - for(i = 0; i < 5; i++) - ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET)); - - mips_cpu_irq_init(); - - for(i = 2; i <= 6; i++) - setup_irq(i, &cascade); - - for(i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) - set_irq_chip_and_handler(i, &ifxmips_irq_type, handle_level_irq); - - set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); -} diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c b/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c deleted file mode 100644 index 2831182ab8..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include - -void -ifxmips_pmu_enable(unsigned int module) -{ - int err = 1000000; - - ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR); - while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module)) {} - - if (!err) - panic("activating PMU module failed!"); -} -EXPORT_SYMBOL(ifxmips_pmu_enable); - -void -ifxmips_pmu_disable(unsigned int module) -{ - ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR); -} -EXPORT_SYMBOL(ifxmips_pmu_disable); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c b/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c deleted file mode 100644 index 880febc62b..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 Wu Qi Ming infineon - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include - -static char buf[1024]; -unsigned int *prom_cp1_base = NULL; -unsigned int prom_cp1_size = 0; - -#ifdef IFXMIPS_PROM_ASC0 -#define IFXMIPS_ASC_DIFF 0 -#else -#define IFXMIPS_ASC_DIFF IFXMIPS_ASC_BASE_DIFF -#endif - -static inline u32 -asc_r32(unsigned long r) -{ - return ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r)); -} - -static inline void -asc_w32(u32 v, unsigned long r) -{ - ifxmips_w32(v, (u32*)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r)); -} - -void -prom_free_prom_memory(void) -{ -} - -void -prom_putchar(char c) -{ - unsigned long flags; - - local_irq_save(flags); - while((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF); - - if(c == '\n') - asc_w32('\r', IFXMIPS_ASC_TBUF); - asc_w32(c, IFXMIPS_ASC_TBUF); - local_irq_restore(flags); -} - -void -prom_printf(const char * fmt, ...) -{ - va_list args; - int l; - char *p, *buf_end; - - va_start(args, fmt); - l = vsprintf(buf, fmt, args); - va_end(args); - buf_end = buf + l; - - for(p = buf; p < buf_end; p++) - prom_putchar(*p); -} - -unsigned int *prom_get_cp1_base(void) -{ - return prom_cp1_base; -} -EXPORT_SYMBOL(prom_get_cp1_base); - -unsigned int prom_get_cp1_size(void) -{ - return prom_cp1_size; -} -EXPORT_SYMBOL(prom_get_cp1_size); - -void __init -prom_init(void) -{ - int argc = fw_arg0; - char **argv = (char **) fw_arg1; - char **envp = (char **) fw_arg2; - - int memsize = 16; - int i; - - mips_machtype = MACH_INFINEON_IFXMIPS; - - argv = (char**)KSEG1ADDR((unsigned long)argv); - arcs_cmdline[0] = '\0'; - for(i = 1; i < argc; i++) - { - char *a = (char*)KSEG1ADDR(argv[i]); - if(!a) - continue; - if(strlen(arcs_cmdline) + strlen(a + 1) >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, a); - strcat(arcs_cmdline, " "); - } - - envp = (char**)KSEG1ADDR((unsigned long)envp); - while(*envp) - { - char *e = (char*)KSEG1ADDR(*envp); - - if(!strncmp(e, "memsize=", 8)) - { - e += 8; - memsize = simple_strtoul(e, NULL, 10); - } - envp++; - } - - prom_cp1_size = 2; - memsize -= prom_cp1_size; - prom_cp1_base = (unsigned int*)(0xA0000000 + (memsize * 1024 * 1024)); - - prom_printf("Using %dMB Ram and reserving %dMB for cp1\n", memsize, prom_cp1_size); - memsize *= 1024 * 1024; - - if(!*arcs_cmdline) - strcpy(&(arcs_cmdline[0]), - "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit"); - - add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); -} diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c b/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c deleted file mode 100644 index d94d8ac810..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include - -static void -ifxmips_machine_restart(char *command) -{ - printk(KERN_NOTICE "System restart\n"); - local_irq_disable(); - - ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL, IFXMIPS_RCU_RST); - for(;;); -} - -static void -ifxmips_machine_halt(void) -{ - printk(KERN_NOTICE "System halted.\n"); - local_irq_disable(); - for(;;); -} - -static void -ifxmips_machine_power_off(void) -{ - printk (KERN_NOTICE "Please turn off the power now.\n"); - local_irq_disable(); - for(;;); -} - -void -ifxmips_reboot_setup(void) -{ - _machine_restart = ifxmips_machine_restart; - _machine_halt = ifxmips_machine_halt; - pm_power_off = ifxmips_machine_power_off; -} diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c b/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c deleted file mode 100644 index a29a54d288..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2004 peng.liu@infineon.com - * Copyright (C) 2007 John Crispin - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static unsigned int r4k_offset; -static unsigned int r4k_cur; - -extern void ifxmips_reboot_setup(void); - -unsigned int -ifxmips_get_cpu_ver(void) -{ - return (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0xF0000000) >> 28; -} -EXPORT_SYMBOL(ifxmips_get_cpu_ver); - -static __inline__ u32 -ifxmips_get_counter_resolution(void) -{ - u32 res; - __asm__ __volatile__( - ".set push\n" - ".set mips32r2\n" - ".set noreorder\n" - "rdhwr %0, $3\n" - "ehb\n" - ".set pop\n" - : "=&r" (res) - : /* no input */ - : "memory"); - instruction_hazard(); - return res; -} - -void __init -plat_time_init(void) -{ - mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution(); - r4k_cur = (read_c0_count() + r4k_offset); - write_c0_compare(r4k_cur); - - ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI); - ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC); // set clock divider to 1 -} - -void __init -plat_mem_setup(void) -{ - u32 status; - prom_printf("This %s has a cpu rev of 0x%X\n", get_system_type(), ifxmips_get_cpu_ver()); - - status = read_c0_status(); - status &= (~(1<<25)); - write_c0_status(status); - - ifxmips_reboot_setup(); - - ioport_resource.start = IOPORT_RESOURCE_START; - ioport_resource.end = IOPORT_RESOURCE_END; - iomem_resource.start = IOMEM_RESOURCE_START; - iomem_resource.end = IOMEM_RESOURCE_END; -} diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c b/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c deleted file mode 100644 index 738f420030..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c +++ /dev/null @@ -1,844 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 - -#ifdef TIMER1A -#define FIRST_TIMER TIMER1A -#else -#define FIRST_TIMER 2 -#endif - -/* - * GPTC divider is set or not. - */ -#define GPTU_CLC_RMC_IS_SET 0 - -/* - * Timer Interrupt (IRQ) - */ -#define TIMER_INTERRUPT INT_NUM_IM3_IRL0 + 22 // Must be adjusted when ICU driver is available - -/* - * Bits Operation - */ -#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) - -/* - * GPTU Register Mapping - */ -#define IFXMIPS_GPTU (KSEG1 + 0x1E100A00) -#define IFXMIPS_GPTU_CLC ((volatile u32*)(IFXMIPS_GPTU + 0x0000)) -#define IFXMIPS_GPTU_ID ((volatile u32*)(IFXMIPS_GPTU + 0x0008)) -#define IFXMIPS_GPTU_CON(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B -#define IFXMIPS_GPTU_RUN(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B -#define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B -#define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B -#define IFXMIPS_GPTU_IRNEN ((volatile u32*)(IFXMIPS_GPTU + 0x00F4)) -#define IFXMIPS_GPTU_IRNICR ((volatile u32*)(IFXMIPS_GPTU + 0x00F8)) -#define IFXMIPS_GPTU_IRNCR ((volatile u32*)(IFXMIPS_GPTU + 0x00FC)) - -/* - * Clock Control Register - */ -#define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16) -#define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8) -#define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5)) -#define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3)) -#define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2)) -#define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1)) -#define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0)) - -#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) -#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) -#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) -#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) -#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) -#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) -#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) - -/* - * ID Register - */ -#define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8) -#define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5) -#define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0) - -/* - * Control Register of Timer/Counter nX - * n is the index of block (1 based index) - * X is either A or B - */ -#define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10)) -#define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9)) -#define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8)) -#define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6) -#define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5)) -#define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) // Timer/Counter B does not have this bit -#define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3)) -#define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2)) -#define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1)) -#define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0)) - -#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) -#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) -#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) -#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) -#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) -#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) -#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) -#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) -#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) - -#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) -#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) -#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) - -#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) - -#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) -#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) -#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) -#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) -#define TIMER_FLAG_NONE_EDGE 0x0000 -#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) -#define TIMER_FLAG_REAL 0x0000 -#define TIMER_FLAG_INVERT 0x0040 -#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) -#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) -#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) -#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 -#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) -#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) - -struct timer_dev_timer { - unsigned int f_irq_on; - unsigned int irq; - unsigned int flag; - unsigned long arg1; - unsigned long arg2; -}; - -struct timer_dev { - struct mutex gptu_mutex; - unsigned int number_of_timers; - unsigned int occupation; - unsigned int f_gptu_on; - struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; -}; - -static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long); -static int gptu_open(struct inode *, struct file *); -static int gptu_release(struct inode *, struct file *); - -static struct file_operations gptu_fops = { - .owner = THIS_MODULE, - .ioctl = gptu_ioctl, - .open = gptu_open, - .release = gptu_release -}; - -static struct miscdevice gptu_miscdev = { - .minor = MISC_DYNAMIC_MINOR, - .name = "gptu", - .fops = &gptu_fops, -}; - -static struct timer_dev timer_dev; - - -static irqreturn_t -timer_irq_handler(int irq, void *p) -{ - unsigned int timer; - unsigned int flag; - struct timer_dev_timer *dev_timer = (struct timer_dev_timer*) p; - - timer = irq - TIMER_INTERRUPT; - if(timer < timer_dev.number_of_timers && dev_timer == &timer_dev.timer[timer]) - { - /* Clear interrupt. */ - ifxmips_w32(1 << timer, IFXMIPS_GPTU_IRNCR); - - /* Call user hanler or signal. */ - flag = dev_timer->flag; - if (!(timer & 0x01) || TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT) - { /* 16-bit timer or timer A of 32-bit timer */ - switch(TIMER_FLAG_MASK_HANDLE (flag)) - { - case TIMER_FLAG_CALLBACK_IN_IRQ: - case TIMER_FLAG_CALLBACK_IN_HB: - if (dev_timer->arg1) - (*(timer_callback) dev_timer->arg1) (dev_timer->arg2); - break; - case TIMER_FLAG_SIGNAL: - send_sig ((int) dev_timer->arg2, (struct task_struct *) dev_timer->arg1, 0); - break; - } - } - } - return IRQ_HANDLED; -} - -static inline void -ifxmips_enable_gptu(void) -{ - ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT); - - /* Set divider as 1, disable write protection for SPEN, enable module. */ - *IFXMIPS_GPTU_CLC = - GPTU_CLC_SMC_SET(0x00) | GPTU_CLC_RMC_SET(0x01) | GPTU_CLC_FSOE_SET(0) | - GPTU_CLC_SBWE_SET(1) | GPTU_CLC_EDIS_SET(0) | GPTU_CLC_SPEN_SET(0) | GPTU_CLC_DISR_SET(0); -} - -static inline void -ifxmips_disable_gptu(void) -{ - ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN); - ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR); - - /* Set divider as 0, enable write protection for SPEN, disable module. */ - *IFXMIPS_GPTU_CLC = - GPTU_CLC_SMC_SET (0x00) | GPTU_CLC_RMC_SET (0x00) | GPTU_CLC_FSOE_SET (0) | - GPTU_CLC_SBWE_SET (0) | GPTU_CLC_EDIS_SET (0) | GPTU_CLC_SPEN_SET (0) | GPTU_CLC_DISR_SET (1); - - ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT); -} - -int -ifxmips_request_timer(unsigned int timer, unsigned int flag, unsigned long value, - unsigned long arg1, unsigned long arg2) -{ - int ret = 0; - unsigned int con_reg, irnen_reg; - int n, X; - - if(timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", (u32)timer, (u32)flag, value); - - if(TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) - value &= 0xFFFF; - else - timer &= ~0x01; - - mutex_lock(&timer_dev.gptu_mutex); - - /* - * Allocate timer. - */ - if (timer < FIRST_TIMER) { - unsigned int mask; - unsigned int shift; - unsigned int offset = TIMER2A;/* This takes care of TIMER1B which is the only choice for Voice TAPI system */ - - /* - * Pick up a free timer. - */ - if (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT) { - mask = 1 << offset; - shift = 1; - } - else { - mask = 3 << offset; - shift = 2; - } - for (timer = offset; - timer < offset + timer_dev.number_of_timers; - timer += shift, mask <<= shift) - if (!(timer_dev.occupation & mask)) { - timer_dev.occupation |= mask; - break; - } - if (timer >= offset + timer_dev.number_of_timers) { - printk("failed![%d]\n", __LINE__); - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - else - ret = timer; - } - else { - register unsigned int mask; - - /* - * Check if the requested timer is free. - */ - mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if ((timer_dev.occupation & mask)) { - printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", __LINE__, mask, timer_dev.occupation); - mutex_unlock(&timer_dev.gptu_mutex); - return -EBUSY; - } - else { - timer_dev.occupation |= mask; - ret = 0; - } - } - - /* - * Prepare control register value. - */ - switch (TIMER_FLAG_MASK_EDGE (flag)) { - default: - case TIMER_FLAG_NONE_EDGE: - con_reg = GPTU_CON_EDGE_SET (0x00); - break; - case TIMER_FLAG_RISE_EDGE: - con_reg = GPTU_CON_EDGE_SET (0x01); - break; - case TIMER_FLAG_FALL_EDGE: - con_reg = GPTU_CON_EDGE_SET (0x02); - break; - case TIMER_FLAG_ANY_EDGE: - con_reg = GPTU_CON_EDGE_SET (0x03); - break; - } - if (TIMER_FLAG_MASK_TYPE (flag) == TIMER_FLAG_TIMER) - con_reg |= - TIMER_FLAG_MASK_SRC (flag) == - TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET (1) : - GPTU_CON_SRC_EXT_SET (0); - else - con_reg |= - TIMER_FLAG_MASK_SRC (flag) == - TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET (1) : - GPTU_CON_SRC_EG_SET (0); - con_reg |= - TIMER_FLAG_MASK_SYNC (flag) == - TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET (0) : - GPTU_CON_SYNC_SET (1); - con_reg |= - TIMER_FLAG_MASK_INVERT (flag) == - TIMER_FLAG_REAL ? GPTU_CON_INV_SET (0) : GPTU_CON_INV_SET (1); - con_reg |= - TIMER_FLAG_MASK_SIZE (flag) == - TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET (0) : - GPTU_CON_EXT_SET (1); - con_reg |= - TIMER_FLAG_MASK_STOP (flag) == - TIMER_FLAG_ONCE ? GPTU_CON_STP_SET (1) : GPTU_CON_STP_SET (0); - con_reg |= - TIMER_FLAG_MASK_TYPE (flag) == - TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET (0) : - GPTU_CON_CNT_SET (1); - con_reg |= - TIMER_FLAG_MASK_DIR (flag) == - TIMER_FLAG_UP ? GPTU_CON_DIR_SET (1) : GPTU_CON_DIR_SET (0); - - /* - * Fill up running data. - */ - timer_dev.timer[timer - FIRST_TIMER].flag = flag; - timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; - timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; - if (TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT) - timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; - - /* - * Enable GPTU module. - */ - if (!timer_dev.f_gptu_on) { - ifxmips_enable_gptu (); - timer_dev.f_gptu_on = 1; - } - - /* - * Enable IRQ. - */ - if (TIMER_FLAG_MASK_HANDLE (flag) != TIMER_FLAG_NO_HANDLE) { - if (TIMER_FLAG_MASK_HANDLE (flag) == TIMER_FLAG_SIGNAL) - timer_dev.timer[timer - FIRST_TIMER].arg1 = - (unsigned long) find_task_by_pid ((int) arg1); - - irnen_reg = 1 << (timer - FIRST_TIMER); - - if (TIMER_FLAG_MASK_HANDLE (flag) == TIMER_FLAG_SIGNAL - || (TIMER_FLAG_MASK_HANDLE (flag) == - TIMER_FLAG_CALLBACK_IN_IRQ - && timer_dev.timer[timer - FIRST_TIMER].arg1)) { - enable_irq (timer_dev.timer[timer - FIRST_TIMER].irq); - timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; - } - } - else - irnen_reg = 0; - - /* - * Write config register, reload value and enable interrupt. - */ - n = timer >> 1; - X = timer & 0x01; - *IFXMIPS_GPTU_CON (n, X) = con_reg; - *IFXMIPS_GPTU_RELOAD (n, X) = value; -// printk("reload value = %d\n", (u32)value); - *IFXMIPS_GPTU_IRNEN |= irnen_reg; - - mutex_unlock(&timer_dev.gptu_mutex); - printk("successful!\n"); - return ret; -} - -int -ifxmips_free_timer(unsigned int timer) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if(!timer_dev.f_gptu_on) - return -EINVAL; - - if(timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if(TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if(((timer_dev.occupation & mask) ^ mask)) - { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - if(GPTU_CON_EN (n, X)) - *IFXMIPS_GPTU_RUN (n, X) = GPTU_RUN_CEN_SET (1); - - *IFXMIPS_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET (n, X, 1); - *IFXMIPS_GPTU_IRNCR |= GPTU_IRNCR_TC_SET (n, X, 1); - - if(timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { - disable_irq (timer_dev.timer[timer - FIRST_TIMER].irq); - timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; - } - - timer_dev.occupation &= ~mask; - if(!timer_dev.occupation && timer_dev.f_gptu_on) - { - ifxmips_disable_gptu(); - timer_dev.f_gptu_on = 0; - } - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} - -int -ifxmips_start_timer(unsigned int timer, int is_resume) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if(!timer_dev.f_gptu_on) - return -EINVAL; - - if(timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if(TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE (flag) == - TIMER_FLAG_16BIT ? 1 : 3) << timer; - if(((timer_dev.occupation & mask) ^ mask)) - { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - *IFXMIPS_GPTU_RUN (n, X) = GPTU_RUN_RL_SET (!is_resume) | GPTU_RUN_SEN_SET (1); - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} - -int -ifxmips_stop_timer(unsigned int timer) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER - || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if(TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if(((timer_dev.occupation & mask) ^ mask)) - { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - *IFXMIPS_GPTU_RUN (n, X) = GPTU_RUN_CEN_SET (1); - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} - -int -ifxmips_reset_counter_flags(u32 timer, u32 flags) -{ - unsigned int oflag; - unsigned int mask, con_reg; - int n, X; - - if(!timer_dev.f_gptu_on) - return -EINVAL; - - if(timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - oflag = timer_dev.timer[timer - FIRST_TIMER].flag; - if(TIMER_FLAG_MASK_SIZE (oflag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE (oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if(((timer_dev.occupation & mask) ^ mask)) - { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - switch(TIMER_FLAG_MASK_EDGE (flags)) - { - default: - case TIMER_FLAG_NONE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x00); - break; - case TIMER_FLAG_RISE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x01); - break; - case TIMER_FLAG_FALL_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x02); - break; - case TIMER_FLAG_ANY_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x03); - break; - } - if(TIMER_FLAG_MASK_TYPE (flags) == TIMER_FLAG_TIMER) - con_reg |= TIMER_FLAG_MASK_SRC (flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET (1) : GPTU_CON_SRC_EXT_SET (0); - else - con_reg |= TIMER_FLAG_MASK_SRC (flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET (1) : GPTU_CON_SRC_EG_SET (0); - con_reg |= TIMER_FLAG_MASK_SYNC (flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET (0) : GPTU_CON_SYNC_SET (1); - con_reg |= TIMER_FLAG_MASK_INVERT (flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET (0) : GPTU_CON_INV_SET (1); - con_reg |= TIMER_FLAG_MASK_SIZE (flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET (0) : GPTU_CON_EXT_SET (1); - con_reg |= TIMER_FLAG_MASK_STOP (flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET (1) : GPTU_CON_STP_SET (0); - con_reg |= TIMER_FLAG_MASK_TYPE (flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET (0) : GPTU_CON_CNT_SET (1); - con_reg |= TIMER_FLAG_MASK_DIR (flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET (1) : GPTU_CON_DIR_SET (0); - - timer_dev.timer[timer - FIRST_TIMER].flag = flags; - if(TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) - timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; - - n = timer >> 1; - X = timer & 0x01; - - *IFXMIPS_GPTU_CON(n, X) = con_reg; - smp_wmb(); - printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *IFXMIPS_GPTU_CON (n, X)); - mutex_unlock(&timer_dev.gptu_mutex); - return 0; -} -EXPORT_SYMBOL(ifxmips_reset_counter_flags); - -inline int -ifxmips_get_count_value(unsigned int timer, unsigned long *value) -{ - - unsigned int flag; - unsigned int mask; - int n, X; - - if(!timer_dev.f_gptu_on) - return -EINVAL; - - if(timer < FIRST_TIMER - || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if(TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) - { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - *value = *IFXMIPS_GPTU_COUNT (n, X); - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} - -u32 -ifxmips_cal_divider(unsigned long freq) -{ - u64 module_freq, fpi = cgu_get_fpi_bus_clock(2); - u32 clock_divider = 1; - module_freq = fpi * 1000; - do_div(module_freq, clock_divider * freq); - return module_freq; -} - -int -ifxmips_set_timer (unsigned int timer, unsigned int freq, int is_cyclic, - int is_ext_src, unsigned int handle_flag, unsigned long arg1, - unsigned long arg2) -{ - unsigned long divider; - unsigned int flag; - - divider = ifxmips_cal_divider(freq); - if (divider == 0) - return -EINVAL; - flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) - | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) - | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) - | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN - | TIMER_FLAG_MASK_HANDLE (handle_flag); - - printk(KERN_INFO "set_timer(%d, %d), divider = %lu\n", timer, freq, divider); - return ifxmips_request_timer (timer, flag, divider, arg1, arg2); -} - -int -ifxmips_set_counter(unsigned int timer, unsigned int flag, u32 reload, unsigned long arg1, unsigned long arg2) -{ - printk(KERN_INFO "set_counter(%d, %#x, %d)\n", timer, flag, reload); - return ifxmips_request_timer(timer, flag, reload, arg1, arg2); -} - -static int -gptu_ioctl (struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) -{ - int ret; - struct gptu_ioctl_param param; - - if (!access_ok (VERIFY_READ, arg, sizeof (struct gptu_ioctl_param))) - return -EFAULT; - copy_from_user (¶m, (void *) arg, sizeof (param)); - - if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER - || GPTU_SET_COUNTER) && param.timer < 2) - || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) - && !access_ok (VERIFY_WRITE, arg, - sizeof (struct gptu_ioctl_param))) - return -EFAULT; - - switch (cmd) { - case GPTU_REQUEST_TIMER: - ret = ifxmips_request_timer (param.timer, param.flag, param.value, - (unsigned long) param.pid, - (unsigned long) param.sig); - if (ret > 0) { - copy_to_user (&((struct gptu_ioctl_param *) arg)-> - timer, &ret, sizeof (&ret)); - ret = 0; - } - break; - case GPTU_FREE_TIMER: - ret = ifxmips_free_timer (param.timer); - break; - case GPTU_START_TIMER: - ret = ifxmips_start_timer (param.timer, param.flag); - break; - case GPTU_STOP_TIMER: - ret = ifxmips_stop_timer (param.timer); - break; - case GPTU_GET_COUNT_VALUE: - ret = ifxmips_get_count_value (param.timer, ¶m.value); - if (!ret) - copy_to_user (&((struct gptu_ioctl_param *) arg)-> - value, ¶m.value, - sizeof (param.value)); - break; - case GPTU_CALCULATE_DIVIDER: - param.value = ifxmips_cal_divider (param.value); - if (param.value == 0) - ret = -EINVAL; - else { - copy_to_user (&((struct gptu_ioctl_param *) arg)-> - value, ¶m.value, - sizeof (param.value)); - ret = 0; - } - break; - case GPTU_SET_TIMER: - ret = ifxmips_set_timer (param.timer, param.value, - TIMER_FLAG_MASK_STOP (param.flag) != - TIMER_FLAG_ONCE ? 1 : 0, - TIMER_FLAG_MASK_SRC (param.flag) == - TIMER_FLAG_EXT_SRC ? 1 : 0, - TIMER_FLAG_MASK_HANDLE (param.flag) == - TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : - TIMER_FLAG_NO_HANDLE, - (unsigned long) param.pid, - (unsigned long) param.sig); - if (ret > 0) { - copy_to_user (&((struct gptu_ioctl_param *) arg)-> - timer, &ret, sizeof (&ret)); - ret = 0; - } - break; - case GPTU_SET_COUNTER: - ifxmips_set_counter (param.timer, param.flag, param.value, 0, 0); - if (ret > 0) { - copy_to_user (&((struct gptu_ioctl_param *) arg)-> - timer, &ret, sizeof (&ret)); - ret = 0; - } - break; - default: - ret = -ENOTTY; - } - - return ret; -} - -static int -gptu_open(struct inode *inode, struct file *file) -{ - return 0; -} - -static int -gptu_release(struct inode *inode, struct file *file) -{ - return 0; -} -int __init -ifxmips_gptu_init(void) -{ - int ret; - unsigned int i; - - ifxmips_w32(0, IFXMIPS_GPTU_IRNEN); - ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR); - - memset(&timer_dev, 0, sizeof (timer_dev)); - mutex_init(&timer_dev.gptu_mutex); - - ifxmips_enable_gptu(); - timer_dev.number_of_timers = GPTU_ID_CFG * 2; - ifxmips_disable_gptu (); - if(timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) - timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; - printk (KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); - - ret = misc_register(&gptu_miscdev); - if(ret) - { - printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); - return ret; - } else { - printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); - } - - for(i = 0; i < timer_dev.number_of_timers; i++) - { - ret = request_irq (TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); - if(ret) - { - for (; i >= 0; i--) - free_irq (TIMER_INTERRUPT + i, &timer_dev.timer[i]); - misc_deregister(&gptu_miscdev); - printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); - return ret; - } else { - timer_dev.timer[i].irq = TIMER_INTERRUPT + i; - disable_irq(timer_dev.timer[i].irq); - printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); - } - } - - return 0; -} - -void __exit -ifxmips_gptu_exit(void) -{ - unsigned int i; - - for(i = 0; i < timer_dev.number_of_timers; i++) - { - if(timer_dev.timer[i].f_irq_on) - disable_irq (timer_dev.timer[i].irq); - free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); - } - ifxmips_disable_gptu(); - misc_deregister(&gptu_miscdev); -} - -EXPORT_SYMBOL(ifxmips_request_timer); -EXPORT_SYMBOL(ifxmips_free_timer); -EXPORT_SYMBOL(ifxmips_start_timer); -EXPORT_SYMBOL(ifxmips_stop_timer); -EXPORT_SYMBOL(ifxmips_get_count_value); -EXPORT_SYMBOL(ifxmips_cal_divider); -EXPORT_SYMBOL(ifxmips_set_timer); -EXPORT_SYMBOL(ifxmips_set_counter); - -module_init(ifxmips_gptu_init); -module_exit(ifxmips_gptu_exit); diff --git a/target/linux/ifxmips/files/arch/mips/pci/ops-ifxmips.c b/target/linux/ifxmips/files/arch/mips/pci/ops-ifxmips.c deleted file mode 100644 index e04c246eae..0000000000 --- a/target/linux/ifxmips/files/arch/mips/pci/ops-ifxmips.c +++ /dev/null @@ -1,120 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IFXMIPS_PCI_CFG_BUSNUM_SHF 16 -#define IFXMIPS_PCI_CFG_DEVNUM_SHF 11 -#define IFXMIPS_PCI_CFG_FUNNUM_SHF 8 - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -extern u32 ifxmips_pci_mapped_cfg; - -static int -ifxmips_pci_config_access(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data) -{ - unsigned long cfg_base; - unsigned long flags; - - u32 temp; - - /* IFXMips support slot from 0 to 15 */ - /* dev_fn 0&0x68 (AD29) is ifxmips itself */ - if ((bus->number != 0) || ((devfn & 0xf8) > 0x78) - || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68)) - return 1; - - spin_lock_irqsave(&ebu_lock, flags); - - cfg_base = ifxmips_pci_mapped_cfg; - cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn << - IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3); - - /* Perform access */ - if (access_type == PCI_ACCESS_WRITE) - { -#ifdef CONFIG_SWAP_IO_SPACE - ifxmips_w32(swab32(*data), ((u32*)cfg_base)); -#else - ifxmips_w32(*data, ((u32*)cfg_base)); -#endif - } else { - *data = ifxmips_r32(((u32*)(cfg_base))); -#ifdef CONFIG_SWAP_IO_SPACE - *data = swab32(*data); -#endif - } - wmb(); - - /* clean possible Master abort */ - cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4; - temp = ifxmips_r32(((u32*)(cfg_base))); -#ifdef CONFIG_SWAP_IO_SPACE - temp = swab32 (temp); -#endif - cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4; - ifxmips_w32(temp, ((u32*)cfg_base)); - - spin_unlock_irqrestore(&ebu_lock, flags); - - if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ)) - return 1; - - return 0; -} - -int -ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - u32 data = 0; - - if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - -int -ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data = 0; - - if (size == 4) - { - data = val; - } else { - if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - } - - if (ifxmips_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - return PCIBIOS_SUCCESSFUL; -} diff --git a/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c b/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c deleted file mode 100644 index 97efa37dd1..0000000000 --- a/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c +++ /dev/null @@ -1,193 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IFXMIPS_PCI_MEM_BASE 0x18000000 -#define IFXMIPS_PCI_MEM_SIZE 0x02000000 -#define IFXMIPS_PCI_IO_BASE 0x1AE00000 -#define IFXMIPS_PCI_IO_SIZE 0x00200000 - -extern int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); -extern int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); - -struct pci_ops ifxmips_pci_ops = -{ - .read = ifxmips_pci_read_config_dword, - .write = ifxmips_pci_write_config_dword -}; - -static struct resource pci_io_resource = -{ - .name = "io pci IO space", - .start = IFXMIPS_PCI_IO_BASE, - .end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1, - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = -{ - .name = "ext pci memory space", - .start = IFXMIPS_PCI_MEM_BASE, - .end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - -static struct pci_controller ifxmips_pci_controller = -{ - .pci_ops = &ifxmips_pci_ops, - .mem_resource = &pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_resource = &pci_io_resource, - .io_offset = 0x00000000UL, -}; - -u32 ifxmips_pci_mapped_cfg; -int ifxmips_pci_external_clock = 0; - -static int __init -ifxmips_pci_set_external_clk(char *str) -{ - printk("cgu: setting up external pci clock\n"); - ifxmips_pci_external_clock = 1; - return 1; -} -__setup("pci_external_clk", ifxmips_pci_set_external_clk); - -int -pcibios_plat_dev_init(struct pci_dev *dev) -{ - u8 pin; - - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); - switch(pin) - { - case 0: - break; - case 1: - //falling edge level triggered:0x4, low level:0xc, rising edge:0x2 - ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON); - ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN); - break; - case 2: - case 3: - case 4: - printk ("WARNING: interrupt pin %d not supported yet!\n", pin); - default: - printk ("WARNING: invalid interrupt pin %d\n", pin); - return 1; - } - return 0; -} - -static void __init -ifxmips_pci_startup(void) -{ - u32 temp_buffer; - - cgu_setup_pci_clk(ifxmips_pci_external_clock); - - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0); - /* enable auto-switching between PCI and EBU */ - ifxmips_w32(0xa, PCI_CR_CLK_CTRL); - /* busy, i.e. configuration is not done, PCI access has to be retried */ - ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD); - wmb (); - /* BUS Master/IO/MEM access */ - ifxmips_w32(ifxmips_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD); - - /* enable external 2 PCI masters */ - temp_buffer = ifxmips_r32(PCI_CR_PC_ARB); - temp_buffer &= (~(0xf << 16)); - /* enable internal arbiter */ - temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); - /* enable internal PCI master reqest */ - temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS)); - - /* enable EBU reqest */ - temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS)); - - /* enable all external masters request */ - temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS)); - ifxmips_w32(temp_buffer, PCI_CR_PC_ARB); - wmb (); - - ifxmips_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0); - ifxmips_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1); - ifxmips_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2); - ifxmips_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3); - ifxmips_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4); - ifxmips_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5); - ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6); - ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7); - ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg); - ifxmips_w32(0x0e000008, PCI_CR_BAR11MASK); - ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11); - ifxmips_w32(0, PCI_CS_BASE_ADDR1); -#ifdef CONFIG_SWAP_IO_SPACE - /* both TX and RX endian swap are enabled */ - ifxmips_w32(ifxmips_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI); - wmb (); -#endif - /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */ - ifxmips_w32(ifxmips_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK); - ifxmips_w32(ifxmips_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK); - /*use 8 dw burst length */ - ifxmips_w32(0x303, PCI_CR_FCI_BURST_LENGTH); - ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD); - wmb(); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT); - wmb(); - mdelay(1); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT); -} - -int __init -pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){ - switch(slot) - { - case 13: - /* IDSEL = AD29 --> USB Host Controller */ - return (INT_NUM_IM1_IRL0 + 17); - case 14: - /* IDSEL = AD30 --> mini PCI connector */ - return (INT_NUM_IM0_IRL0 + 22); - default: - printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin); - return 0; - } -} - -int -pcibios_init(void) -{ - extern int pci_probe_only; - - pci_probe_only = 0; - printk("PCI: Probing PCI hardware on host bus 0.\n"); - ifxmips_pci_startup (); - // IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8); - ifxmips_pci_mapped_cfg = (u32)ioremap_nocache(0x17000000, 0x800 * 16); - printk("IFXMips PCI mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_mapped_cfg); - ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1); - printk("IFXMips PCI I/O mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_controller.io_map_base); - register_pci_controller(&ifxmips_pci_controller); - return 0; -} - -arch_initcall(pcibios_init); diff --git a/target/linux/ifxmips/files/drivers/char/ifxmips_eeprom.c b/target/linux/ifxmips/files/drivers/char/ifxmips_eeprom.c deleted file mode 100644 index ea1303cd66..0000000000 --- a/target/linux/ifxmips/files/drivers/char/ifxmips_eeprom.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * This driver was originally based on the INCA-IP driver, but due to - * fundamental conceptual drawbacks there has been changed a lot. - * - * Based on INCA-IP driver Copyright (c) 2003 Gary Jennejohn - * Based on the VxWorks drivers Copyright (c) 2002, Infineon Technologies. - * - * Copyright (C) 2006 infineon - * Copyright (C) 2007 John Crispin - * - */ - -#define IFAP_EEPROM_DRV_VERSION "0.0.1" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -/* allow the user to set the major device number */ -static int ifxmips_eeprom_maj = 0; - -extern int ifx_ssc_init (void); -extern int ifx_ssc_open (struct inode *inode, struct file *filp); -extern int ifx_ssc_close (struct inode *inode, struct file *filp); -extern void ifx_ssc_cleanup_module (void); -extern int ifx_ssc_ioctl (struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long data); -extern ssize_t ifx_ssc_kwrite (int port, const char *kbuf, size_t len); -extern ssize_t ifx_ssc_kread (int port, char *kbuf, size_t len); - -extern int ifx_ssc_cs_low (unsigned int pin); -extern int ifx_ssc_cs_high (unsigned int pin); -extern int ifx_ssc_txrx (char *tx_buf, unsigned int tx_len, char *rx_buf, unsigned int rx_len); -extern int ifx_ssc_tx (char *tx_buf, unsigned int tx_len); -extern int ifx_ssc_rx (char *rx_buf, unsigned int rx_len); - -#define EEPROM_CS IFX_SSC_WHBGPOSTAT_OUT0_POS - -/* commands for EEPROM, x25160, x25140 */ -#define EEPROM_WREN ((unsigned char)0x06) -#define EEPROM_WRDI ((unsigned char)0x04) -#define EEPROM_RDSR ((unsigned char)0x05) -#define EEPROM_WRSR ((unsigned char)0x01) -#define EEPROM_READ ((unsigned char)0x03) -#define EEPROM_WRITE ((unsigned char)0x02) -#define EEPROM_PAGE_SIZE 4 -#define EEPROM_SIZE 512 - -static int -eeprom_rdsr (void) -{ - int ret = 0; - unsigned char cmd = EEPROM_RDSR; - unsigned long flag; - char status; - - local_irq_save(flag); - - if ((ret = ifx_ssc_cs_low(EEPROM_CS)) == 0) - if ((ret = ifx_ssc_txrx(&cmd, 1, &status, 1)) >= 0) - ret = status & 1; - - ifx_ssc_cs_high(EEPROM_CS); - local_irq_restore(flag); - - return ret; -} - -void -eeprom_wip_over (void) -{ - while (eeprom_rdsr()) - printk("waiting for eeprom\n"); -} - -static int -eeprom_wren (void) -{ - unsigned char cmd = EEPROM_WREN; - int ret = 0; - unsigned long flag; - - local_irq_save(flag); - if ((ret = ifx_ssc_cs_low(EEPROM_CS)) == 0) - if ((ret = ifx_ssc_tx(&cmd, 1)) >= 0) - ret = 0; - - ifx_ssc_cs_high(EEPROM_CS); - local_irq_restore(flag); - - if (!ret) - eeprom_wip_over(); - - return ret; -} - -static int -eeprom_wrsr (void) -{ - int ret = 0; - unsigned char cmd[2]; - unsigned long flag; - - cmd[0] = EEPROM_WRSR; - cmd[1] = 0; - - if ((ret = eeprom_wren())) - { - printk ("eeprom_wren fails\n"); - goto out1; - } - - local_irq_save(flag); - - if ((ret = ifx_ssc_cs_low(EEPROM_CS))) - goto out; - - if ((ret = ifx_ssc_tx(cmd, 2)) < 0) { - ifx_ssc_cs_high(EEPROM_CS); - goto out; - } - - if ((ret = ifx_ssc_cs_low(EEPROM_CS))) - goto out; - - local_irq_restore(flag); - eeprom_wip_over(); - - return ret; - -out: - local_irq_restore (flag); - eeprom_wip_over (); - -out1: - return ret; -} - -static int -eeprom_read (unsigned int addr, unsigned char *buf, unsigned int len) -{ - int ret = 0; - unsigned char write_buf[2]; - unsigned int eff = 0; - unsigned long flag; - - while (1) - { - eeprom_wip_over(); - eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE); - eff = (eff < len) ? eff : len; - local_irq_save(flag); - - if ((ret = ifx_ssc_cs_low(EEPROM_CS)) < 0) - goto out; - - write_buf[0] = EEPROM_READ | ((unsigned char) ((addr & 0x100) >> 5)); - write_buf[1] = (addr & 0xff); - - if ((ret = ifx_ssc_txrx (write_buf, 2, buf, eff)) != eff) - { - printk("ssc_txrx fails %d\n", ret); - ifx_ssc_cs_high (EEPROM_CS); - goto out; - } - - buf += ret; - len -= ret; - addr += ret; - - if ((ret = ifx_ssc_cs_high(EEPROM_CS))) - goto out; - - local_irq_restore(flag); - - if (len <= 0) - goto out2; - } - -out: - local_irq_restore (flag); -out2: - return ret; -} - -static int -eeprom_write (unsigned int addr, unsigned char *buf, unsigned int len) -{ - int ret = 0; - unsigned int eff = 0; - unsigned char write_buf[2]; - int i; - unsigned char rx_buf[EEPROM_PAGE_SIZE]; - - while (1) - { - eeprom_wip_over(); - - if ((ret = eeprom_wren())) - { - printk("eeprom_wren fails\n"); - goto out; - } - - write_buf[0] = EEPROM_WRITE | ((unsigned char) ((addr & 0x100) >> 5)); - write_buf[1] = (addr & 0xff); - - eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE); - eff = (eff < len) ? eff : len; - - printk("EEPROM Write:\n"); - for (i = 0; i < eff; i++) { - printk("%2x ", buf[i]); - if ((i % 16) == 15) - printk("\n"); - } - printk("\n"); - - if ((ret = ifx_ssc_cs_low(EEPROM_CS))) - goto out; - - if ((ret = ifx_ssc_tx (write_buf, 2)) < 0) - { - printk("ssc_tx fails %d\n", ret); - ifx_ssc_cs_high(EEPROM_CS); - goto out; - } - - if ((ret = ifx_ssc_tx (buf, eff)) != eff) - { - printk("ssc_tx fails %d\n", ret); - ifx_ssc_cs_high(EEPROM_CS); - goto out; - } - - buf += ret; - len -= ret; - addr += ret; - - if ((ret = ifx_ssc_cs_high (EEPROM_CS))) - goto out; - - printk ("<=="); - eeprom_read((addr - eff), rx_buf, eff); - for (i = 0; i < eff; i++) - { - printk ("[%x]", rx_buf[i]); - } - printk ("\n"); - - if (len <= 0) - break; - } - -out: - return ret; -} - -int -ifxmips_eeprom_open (struct inode *inode, struct file *filp) -{ - filp->f_pos = 0; - return 0; -} - -int -ifxmips_eeprom_close (struct inode *inode, struct file *filp) -{ - return 0; -} - -int -ifxmips_eeprom_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data) -{ - return 0; -} - -ssize_t -ifxmips_eeprom_read (char *buf, size_t len, unsigned int addr) -{ - int ret = 0; - unsigned int data; - - printk("addr:=%d\n", addr); - printk("len:=%d\n", len); - - if ((addr + len) > EEPROM_SIZE) - { - printk("invalid len\n"); - addr = 0; - len = EEPROM_SIZE / 2; - } - - if ((ret = ifx_ssc_open((struct inode *) 0, NULL))) - { - printk("ifxmips_eeprom_open fails\n"); - goto out; - } - - data = (unsigned int)IFX_SSC_MODE_RXTX; - - if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) - { - printk("set RXTX mode fails\n"); - goto out; - } - - if ((ret = eeprom_wrsr())) - { - printk("EEPROM reset fails\n"); - goto out; - } - - if ((ret = eeprom_read(addr, buf, len))) - { - printk("eeprom read fails\n"); - goto out; - } - -out: - if (ifx_ssc_close((struct inode *) 0, NULL)) - printk("ifxmips_eeprom_close fails\n"); - - return len; -} -EXPORT_SYMBOL(ifxmips_eeprom_read); - -static ssize_t -ifxmips_eeprom_fops_read (struct file *filp, char *ubuf, size_t len, loff_t * off) -{ - int ret = 0; - unsigned char ssc_rx_buf[EEPROM_SIZE]; - long flag; - - if (*off >= EEPROM_SIZE) - return 0; - - if (*off + len > EEPROM_SIZE) - len = EEPROM_SIZE - *off; - - if (len == 0) - return 0; - - local_irq_save(flag); - - if ((ret = ifxmips_eeprom_read(ssc_rx_buf, len, *off)) < 0) - { - printk("read fails, err=%x\n", ret); - local_irq_restore(flag); - return ret; - } - - if (copy_to_user((void*)ubuf, ssc_rx_buf, ret) != 0) - { - local_irq_restore(flag); - ret = -EFAULT; - } - - local_irq_restore(flag); - *off += len; - - return len; -} - -ssize_t -ifxmips_eeprom_write (char *buf, size_t len, unsigned int addr) -{ - int ret = 0; - unsigned int data; - - if ((ret = ifx_ssc_open ((struct inode *) 0, NULL))) - { - printk ("ifxmips_eeprom_open fails\n"); - goto out; - } - - data = (unsigned int) IFX_SSC_MODE_RXTX; - - if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) - { - printk ("set RXTX mode fails\n"); - goto out; - } - - if ((ret = eeprom_wrsr ())) { - printk ("EEPROM reset fails\n"); - goto out; - } - - if ((ret = eeprom_write (addr, buf, len))) { - printk ("eeprom write fails\n"); - goto out; - } - -out: - if (ifx_ssc_close ((struct inode *) 0, NULL)) - printk ("ifxmips_eeprom_close fails\n"); - - return ret; -} -EXPORT_SYMBOL(ifxmips_eeprom_write); - -static ssize_t -ifxmips_eeprom_fops_write (struct file *filp, const char *ubuf, size_t len, loff_t * off) -{ - int ret = 0; - unsigned char ssc_tx_buf[EEPROM_SIZE]; - - if (*off >= EEPROM_SIZE) - return 0; - - if (len + *off > EEPROM_SIZE) - len = EEPROM_SIZE - *off; - - if ((ret = copy_from_user (ssc_tx_buf, ubuf, len))) - return EFAULT; - - ret = ifxmips_eeprom_write (ssc_tx_buf, len, *off); - - if (ret > 0) - *off = ret; - - return ret; -} - -loff_t -ifxmips_eeprom_llseek (struct file * filp, loff_t off, int whence) -{ - loff_t newpos; - switch (whence) { - case SEEK_SET: - newpos = off; - break; - - case SEEK_CUR: - newpos = filp->f_pos + off; - break; - - default: - return -EINVAL; - } - - if (newpos < 0) - return -EINVAL; - - filp->f_pos = newpos; - - return newpos; -} - -static struct file_operations ifxmips_eeprom_fops = { - owner:THIS_MODULE, - llseek:ifxmips_eeprom_llseek, - read:ifxmips_eeprom_fops_read, - write:ifxmips_eeprom_fops_write, - ioctl:ifxmips_eeprom_ioctl, - open:ifxmips_eeprom_open, - release:ifxmips_eeprom_close, -}; - -int __init -ifxmips_eeprom_init (void) -{ - int ret = 0; - - ifxmips_eeprom_maj = register_chrdev(0, "eeprom", &ifxmips_eeprom_fops); - - if (ifxmips_eeprom_maj < 0) - { - printk("failed to register eeprom device\n"); - ret = -EINVAL; - - goto out; - } - - printk("ifxmips_eeprom : /dev/eeprom mayor %d\n", ifxmips_eeprom_maj); - -out: - return ret; -} - -void __exit -ifxmips_eeprom_cleanup_module (void) -{ - /*if (unregister_chrdev (ifxmips_eeprom_maj, "eeprom")) { - printk ("Unable to unregister major %d for the EEPROM\n", - maj); - }*/ -} - -module_exit (ifxmips_eeprom_cleanup_module); -module_init (ifxmips_eeprom_init); - -MODULE_LICENSE ("GPL"); -MODULE_AUTHOR ("Peng Liu"); -MODULE_DESCRIPTION ("IFAP EEPROM driver"); -MODULE_SUPPORTED_DEVICE ("ifxmips_eeprom"); - - diff --git a/target/linux/ifxmips/files/drivers/char/ifxmips_mei_core.c b/target/linux/ifxmips/files/drivers/char/ifxmips_mei_core.c deleted file mode 100644 index e8787c5710..0000000000 --- a/target/linux/ifxmips/files/drivers/char/ifxmips_mei_core.c +++ /dev/null @@ -1,3658 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_mei_core.c -** PROJECT : Danube -** MODULES : MEI -** -** DATE : 1 Jan 2006 -** AUTHOR : TC Chen -** DESCRIPTION : MEI Driver -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Version $Date $Author $Comment - 1.00.01 TC Chen Fixed cell rate calculation issue - Fixed pvovider_id of adsl mib swapping issue - 1.00.02 TC Chen Added L3 Low Poewr Mode support. - 1.00.03 TC Chen Fixed Clear Eoc transmit issue. - 1.00.04 31/08/2006 TC Chen Add ADSL Link/Data Led - Add Dual Latency Path - Add AUTOBOOT_ENABLE_SET ioctl for autoboot - mode enable/disable - Fix fast path cell rate calculation - 1.00.05 25/09/2006 TC Chen Fix ATM QoS fail on interface 0(fast path). - 1.00.06 02/10/2006 TC Chen Change ifxmips_ppe_set_cell_rate to - ifx_atm_set_cell_rate - Add ATM Led callback function - 1.00.07 13/11/2006 TC Chen Invert ADSL Link LED Signal - 1.00.08 08/12/2006 TC Chen Fix loop diagnostic warning message issue - 1.00.09 20/12/2006 TC Chen Workaround for USB OC interrupt which is trigegred once DSL reset -******************************************************************************/ - -/* - * =========================================================================== - * INCLUDE FILES - * =========================================================================== - */ - -#include - -char IFXMIPS_MEI_VERSION[] = "1.00.09"; - -#define IFXMIPS_MEI_CMV_EXTRA //WINHOST debug -#define IFX_ADSL_L3_MODE_SUPPORT //L3 Low Power Mode Support -#define IFX_ADSL_DUAL_LATENCY_SUPPORT -#undef IFXMIPS_CLEAR_EOC //clear eoc support - -// for ARC memory access -#define WHILE_DELAY 20000 -#if defined(IFXMIPS_PORT_RTEMS) -#undef IFXMIPS_DMA_DEBUG_MUTEX -#else -#define IFXMIPS_DMA_DEBUG_MUTEX -#endif - -#define IMAGE_SWAP -#define BOOT_SWAP -#define HEADER_SWAP - -//TODO -#undef DFE_LOOPBACK // testing code //undefined by Henry , start to real link test. - //165203:henryhsu - -#ifdef DFE_LOOPBACK -//#define DFE_MEM_TEST -//#define DFE_PING_TEST -#define DFE_ATM_LOOPBACK -#endif - -#undef DATA_LED_ON_MODE -#define DATA_LED_SUPPORT // support adsl data led -//#define DATA_LED_ADSL_FW_HANDLE // adsl data led handle by firmware -#define CONFIG_IFXMIPS_MEI_LED // adsl led support - -// Block size per BAR -#define SDRAM_SEGMENT_SIZE (64*1024) -// Number of Bar registers -#define MAX_BAR_REGISTERS (17) - -#define XDATA_REGISTER (15) - -#define IFXMIPS_MEI_DEVNAME "mei" - -#ifdef DFE_LOOPBACK -#ifndef UINT32 -#define UINT32 unsigned long -#endif -#ifdef DFE_PING_TEST -#include "dsp_xmem_arb_rand_em.h" -#endif -#ifdef DFE_MEM_TEST -#include "aai_mem_test.h" -#endif -#ifdef DFE_ATM_LOOPBACK -#include "aai_lpbk_dyn_rate.h" -#endif -#endif - -/************************************************************************ - * Function declaration - ************************************************************************/ -static MEI_ERROR meiDMAWrite (u32 destaddr, u32 * databuff, u32 databuffsize); -static MEI_ERROR meiDMARead (u32 srcaddr, u32 * databuff, u32 databuffsize); -static void meiControlModeSwitch (int mode); -static void meiPollForDbgDone (void); -static MEI_ERROR _meiDebugLongWordRead (u32 DEC_mode, u32 address, - u32 * data); -static MEI_ERROR _meiDebugLongWordWrite (u32 DEC_mode, u32 address, u32 data); -MEI_ERROR meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize); -static MEI_ERROR meiDebugRead (u32 srcaddr, u32 * databuff, u32 databuffsize); -static MEI_ERROR meiMailboxWrite (u16 * msgsrcbuffer, u16 msgsize); -static MEI_ERROR meiDownloadBootCode (void); -static MEI_ERROR meiHaltArc (void); -static MEI_ERROR meiRunArc (void); -static MEI_ERROR meiRunAdslModem (void); -static int meiGetPage (u32 Page, u32 data, u32 MaxSize, u32 * Buffer, - u32 * Dest); -void makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size, - u16 * data, u16 * CMVMSG); -MEI_ERROR meiCMV (u16 * request, int reply, u16 * response); -static void meiMailboxInterruptsDisable (void); -static void meiMailboxInterruptsEnable (void); -static int update_bar_register (int nTotalBar); -static int free_image_buffer (int type); -static int alloc_processor_memory (unsigned long size, - smmu_mem_info_t * adsl_mem_info); -ssize_t mei_write (MEI_file_t * filp, char *buf, size_t size, loff_t * loff); -int mei_ioctl (MEI_inode_t * ino, MEI_file_t * fil, unsigned int command, - unsigned long lon); - -#ifdef CONFIG_PROC_FS -static int proc_read (struct file *file, char *buf, size_t nbytes, - loff_t * ppos); -static ssize_t proc_write (struct file *file, const char *buffer, - size_t count, loff_t * ppos); -#endif - -#ifdef CONFIG_IFXMIPS_MEI_MIB -int mei_mib_ioctl (MEI_inode_t * ino, MEI_file_t * fil, unsigned int command, - unsigned long lon); -int mei_mib_adsl_link_up (void); -int mei_mib_adsl_link_down (void); -int ifxmips_mei_mib_init (void); -int ifxmips_mei_mib_cleanup (void); -#endif -#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT) -static int ifxmips_mei_led_init (void); -static int ifxmips_mei_led_cleanup (void); -static int adsl_led_flash_task (void); -#endif -// for clearEoC -#ifdef IFXMIPS_CLEAR_EOC -extern void ifx_push_eoc (struct sk_buff *pkt); -#endif - -/************************************************************************ - * variable declaration - ************************************************************************/ -static smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS]; -static unsigned long image_size = 0; -static struct timeval time_disconnect, time_showtime; -static u16 unavailable_seconds = 0; -#ifdef IFXMIPS_CLEAR_EOC -static wait_queue_head_t wait_queue_hdlc_poll; ///clear eoc -#endif - -static int showtime_lock_flag = 0; -static int quiet_mode_flag = 0; - -int showtime = 0; -static int major = IFXMIPS_MEI_MAJOR; -MEI_mutex_t mei_sema; - -// Mei to ARC CMV count, reply count, ARC Indicator count -static int indicator_count = 0; -static int cmv_count = 0; -static int reply_count = 0; -static u16 Recent_indicator[MSG_LENGTH]; -static int reset_arc_flag = 0; - -// Used in interrupt handler as flags -static int arcmsgav = 0; -static int cmv_reply = 0; -static int cmv_waiting = 0; -static int modem_ready = 0; -// to wait for arc cmv reply, sleep on wait_queue_arcmsgav; -static wait_queue_head_t wait_queue_arcmsgav; - -// CMV mailbox messages -// ARC to MEI message -static u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4))); -// MEI to ARC message -static u16 CMV_TxMsg[MSG_LENGTH] __attribute__ ((aligned (4))); - -static u32 *mei_arc_swap_buff = NULL; // holding swap pages -static ARC_IMG_HDR *img_hdr; -static int arc_halt_flag = 0; -static int nBar = 0; // total bars to be used. - -static u32 loop_diagnostics_mode = 0; -wait_queue_head_t wait_queue_loop_diagnostic; -int loop_diagnostics_completed = 0; -u32 adsl_mode, adsl_mode_extend; // adsl mode : adsl/ 2/ 2+ -static int autoboot_enable_flag = 0; - -#ifdef IFX_ADSL_DUAL_LATENCY_SUPPORT -static u8 bDualLatency = 0; -#endif - -#ifdef IFXMIPS_CLEAR_EOC -static u16 ceoc_read_idx = 0; -#endif - -#ifdef IFX_ADSL_L3_MODE_SUPPORT -static wait_queue_head_t wait_queue_l3; // l3 power mode -static int l3_shutdown = 0; -int get_l3_power_status (void); -#endif - -#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT) -int led_status_on = 0, led_need_to_flash = 0; -static int stop_led_module = 0; //wakeup and clean led module -static wait_queue_head_t wait_queue_led_polling; // adsl led -#endif - -static struct file_operations mei_operations = { - write : mei_write, - ioctl : mei_ioctl, -}; - -#ifdef CONFIG_PROC_FS -static struct proc_dir_entry *meidir; -static struct file_operations proc_operations = { - read:proc_read, - write:proc_write, -}; -static reg_entry_t regs[PROC_ITEMS]; //total items to be monitored by /proc/mei -#define NUM_OF_REG_ENTRY (sizeof(regs)/sizeof(reg_entry_t)) -#endif //#ifdef CONFIG_PROC_FS - -#ifdef DFE_LOOPBACK -unsigned char got_int = 0; -#endif - -///////////////// mei access Rd/Wr methods /////////////// -/** - * Write a value to register - * This function writes a value to ifxmips register - * - * \param ul_address The address to write - * \param ul_data The value to write - * \ingroup Internal - */ -static void -meiLongwordWrite (u32* ul_address, u32 ul_data) -{ - ifxmips_w32(ul_data, ul_address); - wmb(); - return; -} // end of "meiLongwordWrite(..." - -/** - * Read the ifxmips register - * This function read the value from ifxmips register - * - * \param ul_address The address to write - * \param pul_data Pointer to the data - * \ingroup Internal - */ -static void -meiLongwordRead (u32* ul_address, u32 * pul_data) -{ - //*pul_data = *((volatile u32 *)ul_address); - *pul_data = ifxmips_r32(ul_address); - wmb(); - return; -} // end of "meiLongwordRead(..." - -/** - * Write several DWORD datas to ARC memory via ARC DMA interface - * This function writes several DWORD datas to ARC memory via DMA interface. - * - * \param destaddr The address to write - * \param databuff Pointer to the data buffer - * \param databuffsize Number of DWORDs to write - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiDMAWrite (u32 destaddr, u32 * databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - MEI_intstat_t flags; - - if (destaddr & 3) - return MEI_FAILURE; - -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_LOCKINT (flags); -#endif - - //printk("destaddr=%X,size=%d\n",destaddr,databuffsize); - // Set the write transfer address - meiLongwordWrite (MEI_XFR_ADDR, destaddr); - - // Write the data pushed across DMA - while (databuffsize--) { - temp = *p; - if (databuff == (u32 *) CMV_TxMsg) - MEI_HALF_WORD_SWAP (temp); - meiLongwordWrite (MEI_DATA_XFR, temp); - p++; - } // end of "while(..." - -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_UNLOCKINT (flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMAWrite(..." - -/** - * Read several DWORD datas from ARC memory via ARC DMA interface - * This function reads several DWORD datas from ARC memory via DMA interface. - * - * \param srcaddr The address to read - * \param databuff Pointer to the data buffer - * \param databuffsize Number of DWORDs to read - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiDMARead (u32 srcaddr, u32 * databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_intstat_t flags; -#endif - //printk("destaddr=%X,size=%X\n",srcaddr,databuffsize); - if (srcaddr & 3) - return MEI_FAILURE; - -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_LOCKINT (flags); -#endif - - // Set the read transfer address - meiLongwordWrite (MEI_XFR_ADDR, srcaddr); - - // Read the data popped across DMA - while (databuffsize--) { - meiLongwordRead (MEI_DATA_XFR, &temp); - if (databuff == (u32 *) CMV_RxMsg) // swap half word - MEI_HALF_WORD_SWAP (temp); - *p = temp; - p++; - } // end of "while(..." - -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_UNLOCKINT (flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMARead(..." - -/** - * Switch the ARC control mode - * This function switchs the ARC control mode to JTAG mode or MEI mode - * - * \param mode The mode want to switch: JTAG_MASTER_MODE or MEI_MASTER_MODE. - * \ingroup Internal - */ -static void -meiControlModeSwitch (int mode) -{ - u32 temp = 0x0; - meiLongwordRead ( MEI_DBG_MASTER, &temp); - switch (mode) { - case JTAG_MASTER_MODE: - temp &= ~(HOST_MSTR); - break; - case MEI_MASTER_MODE: - temp |= (HOST_MSTR); - break; - default: - printk ("meiControlModeSwitch: unkonwn mode [%d]\n", - mode); - return; - } - meiLongwordWrite (MEI_DBG_MASTER, temp); -} - -/** - * Poll for transaction complete signal - * This function polls and waits for transaction complete signal. - * - * \ingroup Internal - */ -static void -meiPollForDbgDone (void) -{ - u32 query = 0; - int i = 0; - while (i < WHILE_DELAY) { - meiLongwordRead (ARC_TO_MEI_INT, &query); - query &= (ARC_TO_MEI_DBG_DONE); - if (query) - break; - i++; - if (i == WHILE_DELAY) { - printk ("\n\n PollforDbg fail"); - } - } - meiLongwordWrite ( ARC_TO_MEI_INT, ARC_TO_MEI_DBG_DONE); // to clear this interrupt -} // end of "meiPollForDbgDone(..." - -/** - * ARC Debug Memory Access for a single DWORD reading. - * This function used for direct, address-based access to ARC memory. - * - * \param DEC_mode ARC memory space to used - * \param address Address to read - * \param data Pointer to data - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -_meiDebugLongWordRead (u32 DEC_mode, u32 address, u32 * data) -{ - meiLongwordWrite ( MEI_DEBUG_DEC, DEC_mode); - meiLongwordWrite ( MEI_DEBUG_RAD, address); - meiPollForDbgDone (); - meiLongwordRead (MEI_DEBUG_DATA, data); - return MEI_SUCCESS; -} - -/** - * ARC Debug Memory Access for a single DWORD writing. - * This function used for direct, address-based access to ARC memory. - * - * \param DEC_mode ARC memory space to used - * \param address The address to write - * \param data The data to write - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -_meiDebugLongWordWrite (u32 DEC_mode, u32 address, u32 data) -{ - meiLongwordWrite (MEI_DEBUG_DEC, DEC_mode); - meiLongwordWrite (MEI_DEBUG_WAD, address); - meiLongwordWrite (MEI_DEBUG_DATA, data); - meiPollForDbgDone (); - return MEI_SUCCESS; -} - -/** - * ARC Debug Memory Access for writing. - * This function used for direct, address-based access to ARC memory. - * - * \param destaddr The address to ead - * \param databuffer Pointer to data - * \param databuffsize The number of DWORDs to read - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ - -MEI_ERROR -meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_intstat_t flags; -#endif - -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_LOCKINT (flags); -#endif - - // Open the debug port before DMP memory write - meiControlModeSwitch (MEI_MASTER_MODE); - - meiLongwordWrite (MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK); - - // For the requested length, write the address and write the data - address = destaddr; - buffer = databuff; - for (i = 0; i < databuffsize; i++) { - temp = *buffer; - _meiDebugLongWordWrite (MEI_DEBUG_DEC_DMP1_MASK, address, - temp); - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory write - meiControlModeSwitch (JTAG_MASTER_MODE); - -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_UNLOCKINT (flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugWrite(..." - -/** - * ARC Debug Memory Access for reading. - * This function used for direct, address-based access to ARC memory. - * - * \param srcaddr The address to read - * \param databuffer Pointer to data - * \param databuffsize The number of DWORDs to read - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiDebugRead (u32 srcaddr, u32 * databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_intstat_t flags; -#endif - -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_LOCKINT (flags); -#endif - - // Open the debug port before DMP memory read - meiControlModeSwitch (MEI_MASTER_MODE); - - meiLongwordWrite (MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK); - - // For the requested length, write the address and read the data - address = srcaddr; - buffer = databuff; - for (i = 0; i < databuffsize; i++) { - _meiDebugLongWordRead (MEI_DEBUG_DEC_DMP1_MASK, address, - &temp); - *buffer = temp; - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory read - meiControlModeSwitch (JTAG_MASTER_MODE); - -#ifdef IFXMIPS_DMA_DEBUG_MUTEX - MEI_UNLOCKINT (flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugRead(..." - -/** - * Send a message to ARC MailBox. - * This function sends a message to ARC Mailbox via ARC DMA interface. - * - * \param msgsrcbuffer Pointer to message. - * \param msgsize The number of words to write. - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiMailboxWrite (u16 * msgsrcbuffer, u16 msgsize) -{ - int i; - u32 arc_mailbox_status = 0x0; - u32 temp = 0; - MEI_ERROR meiMailboxError = MEI_SUCCESS; - - // Write to mailbox - meiMailboxError = - meiDMAWrite (MEI_TO_ARC_MAILBOX, (u32 *) msgsrcbuffer, - msgsize / 2); - meiMailboxError = - meiDMAWrite (MEI_TO_ARC_MAILBOXR, (u32 *) (&temp), 1); - - // Notify arc that mailbox write completed - cmv_waiting = 1; - meiLongwordWrite (MEI_TO_ARC_INT, MEI_TO_ARC_MSGAV); - - i = 0; - while (i < WHILE_DELAY) { // wait for ARC to clear the bit - meiLongwordRead ( MEI_TO_ARC_INT, &arc_mailbox_status); - if ((arc_mailbox_status & MEI_TO_ARC_MSGAV) != - MEI_TO_ARC_MSGAV) - break; - i++; - if (i == WHILE_DELAY) { - printk - ("\n\n MEI_TO_ARC_MSGAV not cleared by ARC"); - meiMailboxError = MEI_FAILURE; - } - } - - // Return - return meiMailboxError; - -} // end of "meiMailboxWrite(..." - -/** - * Read a message from ARC MailBox. - * This function reads a message from ARC Mailbox via ARC DMA interface. - * - * \param msgsrcbuffer Pointer to message. - * \param msgsize The number of words to read - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiMailboxRead (u16 * msgdestbuffer, u16 msgsize) -{ - MEI_ERROR meiMailboxError = MEI_SUCCESS; - // Read from mailbox - meiMailboxError = - meiDMARead (ARC_TO_MEI_MAILBOX, (u32 *) msgdestbuffer, - msgsize / 2); - - // Notify arc that mailbox read completed - meiLongwordWrite (ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV); - - // Return - return meiMailboxError; - -} // end of "meiMailboxRead(..." - -/** - * Download boot pages to ARC. - * This function downloads boot pages to ARC. - * - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiDownloadBootPages (void) -{ - int boot_loop; - int page_size; - u32 dest_addr; - - /* - ** DMA the boot code page(s) - */ -#ifndef HEADER_SWAP - for (boot_loop = 1; boot_loop < le32_to_cpu (img_hdr->count); - boot_loop++) -#else - for (boot_loop = 1; boot_loop < (img_hdr->count); boot_loop++) -#endif - { -#ifndef HEADER_SWAP - if (le32_to_cpu (img_hdr->page[boot_loop].p_size) & BOOT_FLAG) -#else - if ((img_hdr->page[boot_loop].p_size) & BOOT_FLAG) -#endif - { - page_size = - meiGetPage (boot_loop, GET_PROG, MAXSWAPSIZE, - mei_arc_swap_buff, &dest_addr); - if (page_size > 0) { - meiDMAWrite (dest_addr, mei_arc_swap_buff, - page_size); - } - } -#ifndef HEADER_SWAP - if (le32_to_cpu (img_hdr->page[boot_loop].d_size) & BOOT_FLAG) -#else - if ((img_hdr->page[boot_loop].d_size) & BOOT_FLAG) -#endif - { - page_size = - meiGetPage (boot_loop, GET_DATA, MAXSWAPSIZE, - mei_arc_swap_buff, &dest_addr); - if (page_size > 0) { - meiDMAWrite (dest_addr, mei_arc_swap_buff, - page_size); - } - } - } - return MEI_SUCCESS; -} - -/** - * Initial efuse rar. - **/ -static void -mei_fuse_rar_init (void) -{ - u32 data = 0; - meiDMAWrite (IRAM0_BASE, &data, 1); - meiDMAWrite (IRAM0_BASE + 4, &data, 1); - meiDMAWrite (IRAM1_BASE, &data, 1); - meiDMAWrite (IRAM1_BASE + 4, &data, 1); - meiDMAWrite (BRAM_BASE, &data, 1); - meiDMAWrite (BRAM_BASE + 4, &data, 1); - meiDMAWrite (ADSL_DILV_BASE, &data, 1); - meiDMAWrite (ADSL_DILV_BASE + 4, &data, 1); -} - -/** - * efuse rar program - **/ -static void -mei_fuse_prg (void) -{ - u32 reg_data, fuse_value; - int i = 0; - meiLongwordRead ( IFXMIPS_RCU_RST, ®_data); - while ((reg_data & 0x10000000) == 0) { - meiLongwordRead ( IFXMIPS_RCU_RST, ®_data); - //add a watchdog - i++; - /* 0x4000 translate to about 16 ms@111M, so should be enough */ - if (i == 0x4000) - return; - } - // STEP a: Prepare memory for external accesses - // Write fuse_en bit24 - meiLongwordRead (IFXMIPS_RCU_RST, ®_data); - meiLongwordWrite (IFXMIPS_RCU_RST, reg_data | (1 << 24)); - - mei_fuse_rar_init (); - for (i = 0; i < 4; i++) { - meiLongwordRead((u32*)(IFXMIPS_FUSE_BASE_ADDR + (i * 4)), &fuse_value); - switch (fuse_value & 0xF0000) { - case 0x80000: - reg_data = - ((fuse_value & RX_DILV_ADDR_BIT_MASK) | - (RX_DILV_ADDR_BIT_MASK + 0x1)); - meiDMAWrite (ADSL_DILV_BASE, ®_data, 1); - break; - case 0x90000: - reg_data = - ((fuse_value & RX_DILV_ADDR_BIT_MASK) | - (RX_DILV_ADDR_BIT_MASK + 0x1)); - meiDMAWrite (ADSL_DILV_BASE + 4, ®_data, 1); - break; - case 0xA0000: - reg_data = - ((fuse_value & IRAM0_ADDR_BIT_MASK) | - (IRAM0_ADDR_BIT_MASK + 0x1)); - meiDMAWrite (IRAM0_BASE, ®_data, 1); - break; - case 0xB0000: - reg_data = - ((fuse_value & IRAM0_ADDR_BIT_MASK) | - (IRAM0_ADDR_BIT_MASK + 0x1)); - meiDMAWrite (IRAM0_BASE + 4, ®_data, 1); - break; - case 0xC0000: - reg_data = - ((fuse_value & IRAM1_ADDR_BIT_MASK) | - (IRAM1_ADDR_BIT_MASK + 0x1)); - meiDMAWrite (IRAM1_BASE, ®_data, 1); - break; - case 0xD0000: - reg_data = - ((fuse_value & IRAM1_ADDR_BIT_MASK) | - (IRAM1_ADDR_BIT_MASK + 0x1)); - meiDMAWrite (IRAM1_BASE + 4, ®_data, 1); - break; - case 0xE0000: - reg_data = - ((fuse_value & BRAM_ADDR_BIT_MASK) | - (BRAM_ADDR_BIT_MASK + 0x1)); - meiDMAWrite (BRAM_BASE, ®_data, 1); - break; - case 0xF0000: - reg_data = - ((fuse_value & BRAM_ADDR_BIT_MASK) | - (BRAM_ADDR_BIT_MASK + 0x1)); - meiDMAWrite (BRAM_BASE + 4, ®_data, 1); - break; - default: // PPE efuse - break; - } - } - meiLongwordRead (IFXMIPS_RCU_RST, ®_data); - meiLongwordWrite (IFXMIPS_RCU_RST, reg_data & 0xF7FFFFFF); -} - -/** - * Download boot code to ARC. - * This function downloads boot code to ARC. - * - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiDownloadBootCode (void) -{ - u32 arc_debug_data = ACL_CLK_MODE_ENABLE; //0x10 - - meiMailboxInterruptsDisable (); - - // Switch arc control from JTAG mode to MEI mode - meiControlModeSwitch (MEI_MASTER_MODE); - //enable ac_clk signal - _meiDebugLongWordRead (MEI_DEBUG_DEC_DMP1_MASK, CRI_CCR0, - &arc_debug_data); - arc_debug_data |= ACL_CLK_MODE_ENABLE; - _meiDebugLongWordWrite (MEI_DEBUG_DEC_DMP1_MASK, CRI_CCR0, - arc_debug_data); - //Switch arc control from MEI mode to JTAG mode - meiControlModeSwitch (JTAG_MASTER_MODE); - - mei_fuse_prg (); //program fuse rar - - meiDownloadBootPages (); - - return MEI_SUCCESS; - -} // end of "meiDownloadBootCode(..." - -//#endif - -/** - * Halt the ARC. - * This function halts the ARC. - * - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiHaltArc (void) -{ - u32 arc_debug_data = 0x0; - - // Switch arc control from JTAG mode to MEI mode - meiControlModeSwitch (MEI_MASTER_MODE); - _meiDebugLongWordRead (MEI_DEBUG_DEC_AUX_MASK, ARC_DEBUG, - &arc_debug_data); - arc_debug_data |= (BIT1); - _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, ARC_DEBUG, - arc_debug_data); - // Switch arc control from MEI mode to JTAG mode - meiControlModeSwitch (JTAG_MASTER_MODE); - arc_halt_flag = 1; - - MEI_WAIT (10); - // Return - return MEI_SUCCESS; - -} // end of "meiHalt(..." - -/** - * Run the ARC. - * This function runs the ARC. - * - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiRunArc (void) -{ - u32 arc_debug_data = 0x0; - - // Switch arc control from JTAG mode to MEI mode- write '1' to bit0 - meiControlModeSwitch (MEI_MASTER_MODE); - _meiDebugLongWordRead (MEI_DEBUG_DEC_AUX_MASK, AUX_STATUS, - &arc_debug_data); - - // Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared) - arc_debug_data &= ~(BIT25); - _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, AUX_STATUS, - arc_debug_data); - - // Switch arc control from MEI mode to JTAG mode- write '0' to bit0 - meiControlModeSwitch (JTAG_MASTER_MODE); - // Enable mask for arc codeswap interrupts - meiMailboxInterruptsEnable (); - arc_halt_flag = 0; - - // Return - return MEI_SUCCESS; - -} // end of "meiActivate(..." - -/** - * Reset the ARC. - * This function resets the ARC. - * - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiResetARC (void) -{ - - u32 arc_debug_data = 0; - showtime = 0; - - meiHaltArc (); - - meiLongwordRead (IFXMIPS_RCU_RST, &arc_debug_data); - meiLongwordWrite (IFXMIPS_RCU_RST, - arc_debug_data | IFXMIPS_RCU_RST_REQ_DFE | - IFXMIPS_RCU_RST_REQ_AFE); - meiLongwordWrite (IFXMIPS_RCU_RST, arc_debug_data); - // reset ARC - meiLongwordWrite(MEI_RST_CONTROL, MEI_SOFT_RESET); - meiLongwordWrite(MEI_RST_CONTROL, 0); - - meiMailboxInterruptsDisable (); - MEI_MUTEX_INIT (mei_sema, 1); - reset_arc_flag = 1; - modem_ready = 0; - return MEI_SUCCESS; -} - -/** - * Reset the ARC, download boot codes, and run the ARC. - * This function resets the ARC, downloads boot codes to ARC, and runs the ARC. - * - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -static MEI_ERROR -meiRunAdslModem (void) -{ - int nSize = 0, idx = 0; - - img_hdr = (ARC_IMG_HDR *) adsl_mem_info[0].address; -#if defined(HEADER_SWAP) - if ((img_hdr->count) * sizeof (ARC_SWP_PAGE_HDR) > SDRAM_SEGMENT_SIZE) -#else //define(HEADER_SWAP) - if (le32_to_cpu (img_hdr->count) * sizeof (ARC_SWP_PAGE_HDR) > - SDRAM_SEGMENT_SIZE) -#endif //define(HEADER_SWAP) - { - printk - ("segment_size is smaller than firmware header size\n"); - return -1; - } - // check image size - for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) { - nSize += adsl_mem_info[idx].nCopy; - } - if (nSize != image_size) { - printk - ("Firmware download is not completed. \nPlease download firmware again!\n"); - return -1; - } - // TODO: check crc - /// - if (reset_arc_flag == 0) { - u32 arc_debug_data; - - meiResetARC (); - meiControlModeSwitch (MEI_MASTER_MODE); - //enable ac_clk signal - _meiDebugLongWordRead (MEI_DEBUG_DEC_DMP1_MASK, CRI_CCR0, - &arc_debug_data); - arc_debug_data |= ACL_CLK_MODE_ENABLE; - _meiDebugLongWordWrite (MEI_DEBUG_DEC_DMP1_MASK, CRI_CCR0, - arc_debug_data); - meiControlModeSwitch (JTAG_MASTER_MODE); - meiHaltArc (); - update_bar_register (nBar); - } - reset_arc_flag = 0; - if (arc_halt_flag == 0) { - meiHaltArc (); - } - printk ("Starting to meiDownloadBootCode\n"); - - meiDownloadBootCode(); - - // 1.00.09 20/12/2006 TC Chen - // disable USB OC interrupt, reset DSL chip will triger OC interrupt - disable_irq(IFXMIPS_USB_OC_INT); - - meiRunArc (); - - MEI_WAIT (100); //wait 100ms - - //1.00.09 20/12/2006 TC Chen - // restore USB OC interrupt - MEI_MASK_AND_ACK_IRQ(IFXMIPS_USB_OC_INT); - enable_irq(IFXMIPS_USB_OC_INT); - - if (modem_ready != 1) { - printk ("Running ADSL modem firmware fail!\n"); - return MEI_FAILURE; - } - - - return MEI_SUCCESS; -} - -/** - * Get the page's data pointer - * This function caculats the data address from the firmware header. - * - * \param Page The page number. - * \param data Data page or program page. - * \param MaxSize The maximum size to read. - * \param Buffer Pointer to data. - * \param Dest Pointer to the destination address. - * \return The number of bytes to read. - * \ingroup Internal - */ -static int -meiGetPage (u32 Page, u32 data, u32 MaxSize, u32 * Buffer, u32 * Dest) -{ - u32 size; - u32 i; - u32 *p; - u32 idx, offset, nBar = 0; - - if (Page > img_hdr->count) - return -2; - /* - ** Get program or data size, depending on "data" flag - */ -#ifndef HEADER_SWAP - size = (data == - GET_DATA) ? le32_to_cpu (img_hdr->page[Page]. - d_size) : le32_to_cpu (img_hdr-> - page[Page]. - p_size); -#else - size = (data == - GET_DATA) ? (img_hdr->page[Page].d_size) : (img_hdr-> - page[Page]. - p_size); -#endif - size &= BOOT_FLAG_MASK; // Clear boot bit! - if (size > MaxSize) - return -1; - - if (size == 0) - return 0; - /* - ** Get program or data offset, depending on "data" flag - */ -#ifndef HEADER_SWAP - i = data ? le32_to_cpu (img_hdr->page[Page]. - d_offset) : le32_to_cpu (img_hdr->page[Page]. - p_offset); -#else - i = data ? (img_hdr->page[Page].d_offset) : (img_hdr->page[Page]. - p_offset); -#endif - - /* - ** Copy data/program to buffer - */ - - idx = i / SDRAM_SEGMENT_SIZE; - offset = i % SDRAM_SEGMENT_SIZE; - p = (u32 *) ((u8 *) adsl_mem_info[idx].address + offset); - - for (i = 0; i < size; i++) { - if (offset + i * 4 - (nBar * SDRAM_SEGMENT_SIZE) >= - SDRAM_SEGMENT_SIZE) { - idx++; - nBar++; - p = (u32 *) ((u8 *) - KSEG1ADDR ((u32) adsl_mem_info[idx]. - address)); - } - Buffer[i] = *p++; -#ifdef BOOT_SWAP -#ifndef IMAGE_SWAP - Buffer[i] = le32_to_cpu (Buffer[i]); -#endif -#endif - } - - /* - ** Pass back data/program destination address - */ -#ifndef HEADER_SWAP - *Dest = data ? le32_to_cpu (img_hdr->page[Page]. - d_dest) : le32_to_cpu (img_hdr-> - page[Page].p_dest); -#else - *Dest = data ? (img_hdr->page[Page].d_dest) : (img_hdr->page[Page]. - p_dest); -#endif - - return size; -} - -////////////////makeCMV(Opcode, Group, Address, Index, Size, Data), CMV in u16 TxMessage[MSG_LENGTH]/////////////////////////// - -/** - * Compose a message. - * This function compose a message from opcode, group, address, index, size, and data - * - * \param opcode The message opcode - * \param group The message group number - * \param address The message address. - * \param index The message index. - * \param size The number of words to read/write. - * \param data The pointer to data. - * \param CMVMSG The pointer to message buffer. - * \ingroup Internal - */ -void -makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data, - u16 * CMVMSG) -{ - memset (CMVMSG, 0, MSG_LENGTH * 2); - CMVMSG[0] = (opcode << 4) + (size & 0xf); - CMVMSG[1] = (((index == 0) ? 0 : 1) << 7) + (group & 0x7f); - CMVMSG[2] = address; - CMVMSG[3] = index; - if (opcode == H2D_CMV_WRITE) - memcpy (CMVMSG + 4, data, size * 2); - return; -} - -/** - * Send a message to ARC and read the response - * This function sends a message to arc, waits the response, and reads the responses. - * - * \param request Pointer to the request - * \param reply Wait reply or not. - * \param response Pointer to the response - * \return MEI_SUCCESS or MEI_FAILURE - * \ingroup Internal - */ -MEI_ERROR -meiCMV (u16 * request, int reply, u16 * response) // write cmv to arc, if reply needed, wait for reply -{ - MEI_ERROR meierror; -#if defined(IFXMIPS_PORT_RTEMS) - int delay_counter = 0; -#endif - - cmv_reply = reply; - memcpy (CMV_TxMsg, request, MSG_LENGTH * 2); - arcmsgav = 0; - - meierror = meiMailboxWrite (CMV_TxMsg, MSG_LENGTH); - - if (meierror != MEI_SUCCESS) { - cmv_waiting = 0; - arcmsgav = 0; - printk ("\n\n MailboxWrite Fail."); - return meierror; - } - else { - cmv_count++; - } - - if (cmv_reply == NO_REPLY) - return MEI_SUCCESS; - -#if !defined(IFXMIPS_PORT_RTEMS) - if (arcmsgav == 0) - MEI_WAIT_EVENT_TIMEOUT (wait_queue_arcmsgav, CMV_TIMEOUT); -#else - while (arcmsgav == 0 && delay_counter < CMV_TIMEOUT / 5) { - MEI_WAIT (5); - delay_counter++; - } -#endif - - cmv_waiting = 0; - if (arcmsgav == 0) { //CMV_timeout - arcmsgav = 0; - printk ("\nmeiCMV: MEI_MAILBOX_TIMEOUT\n"); - return MEI_MAILBOX_TIMEOUT; - } - else { - arcmsgav = 0; - reply_count++; - memcpy (response, CMV_RxMsg, MSG_LENGTH * 2); - return MEI_SUCCESS; - } - return MEI_SUCCESS; -} - -///////////////////// Interrupt handler ///////////////////////// -/** - * Disable ARC to MEI interrupt - * - * \ingroup Internal - */ -static void -meiMailboxInterruptsDisable (void) -{ - meiLongwordWrite (ARC_TO_MEI_INT_MASK, 0x0); -} // end of "meiMailboxInterruptsDisable(..." - -/** - * Eable ARC to MEI interrupt - * - * \ingroup Internal - */ -static void -meiMailboxInterruptsEnable (void) -{ - meiLongwordWrite (ARC_TO_MEI_INT_MASK, MSGAV_EN); -} // end of "meiMailboxInterruptsEnable(..." - -/** - * MEI interrupt handler - * - * \param int1 - * \param void0 - * \param regs Pointer to the structure of ifxmips mips registers - * \ingroup Internal - */ -irqreturn_t -mei_interrupt_arcmsgav (int int1, void *void0) -{ - u32 scratch; - -#if defined(DFE_LOOPBACK) && defined(DFE_PING_TEST) - dfe_loopback_irq_handler (); - goto out; -#endif //DFE_LOOPBACK - - meiDebugRead (ARC_MEI_MAILBOXR, &scratch, 1); - if (scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK) { - printk("\n\n Receive Code Swap Request interrupt!!!"); - goto out; - } - else if (scratch & OMB_CLEAREOC_INTERRUPT_CODE) // clear eoc message interrupt - { - meiLongwordWrite (ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV); -#if defined (IFXMIPS_CLEAR_EOC) - MEI_WAKEUP_EVENT (wait_queue_hdlc_poll); -#endif - MEI_MASK_AND_ACK_IRQ (IFXMIPS_MEI_INT); - goto out; - } - else { // normal message - meiMailboxRead (CMV_RxMsg, MSG_LENGTH); -#if 0 - { - int msg_idx = 0; - printk ("got interrupt\n"); - for (msg_idx = 0; msg_idx < MSG_LENGTH; msg_idx++) { - printk ("%04X ", CMV_RxMsg[msg_idx]); - if (msg_idx % 8 == 7) - printk ("\n"); - } - printk ("\n"); - } -#endif - if (cmv_waiting == 1) { - arcmsgav = 1; - cmv_waiting = 0; -#if !defined(IFXMIPS_PORT_RTEMS) - MEI_WAKEUP_EVENT (wait_queue_arcmsgav); -#endif - } - else { - indicator_count++; - memcpy ((char *) Recent_indicator, (char *) CMV_RxMsg, - MSG_LENGTH * 2); - if (((CMV_RxMsg[0] & 0xff0) >> 4) == D2H_AUTONOMOUS_MODEM_READY_MSG) // arc ready - { //check ARC ready message - printk ("Got MODEM_READY_MSG\n"); - modem_ready = 1; - MEI_MUTEX_UNLOCK (mei_sema); // allow cmv access - } - } - } - - MEI_MASK_AND_ACK_IRQ (IFXMIPS_MEI_INT); -out: - return IRQ_HANDLED;; -} - -////////////////////////hdlc //////////////// - -/** - * Get the hdlc status - * - * \return HDLC status - * \ingroup Internal - */ -static unsigned int -ifx_me_hdlc_status (void) -{ - u16 CMVMSG[MSG_LENGTH]; - int ret; - - if (showtime != 1) - return -ENETRESET; - - makeCMV (H2D_CMV_READ, STAT, 14, 0, 1, NULL, CMVMSG); //Get HDLC status - ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return -EIO; - } - return CMVMSG[4] & 0x0F; -} - -/** - * Check if the me is reslved. - * - * \param status the me status - * \return ME_HDLC_UNRESOLVED or ME_HDLC_RESOLVED - * \ingroup Internal - */ -int -ifx_me_is_resloved (int status) -{ - u16 CMVMSG[MSG_LENGTH]; - int ret; - if (adsl_mode <= 8 && adsl_mode_extend == 0) // adsl mode - { - makeCMV (H2D_CMV_READ, CNTL, 2, 0, 1, NULL, CMVMSG); //Get ME-HDLC Control - ret = mei_ioctl ((struct inode *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return ME_HDLC_UNRESOLVED; - } - if (CMVMSG[4] & (1 << 0)) { - return ME_HDLC_UNRESOLVED; - } - } - else { - if (status == ME_HDLC_MSG_QUEUED - || status == ME_HDLC_MSG_SENT) - return ME_HDLC_UNRESOLVED; - if (status == ME_HDLC_IDLE) { - makeCMV (H2D_CMV_READ, CNTL, 2, 0, 1, NULL, CMVMSG); //Get ME-HDLC Control - ret = mei_ioctl ((struct inode *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return IFX_POP_EOC_FAIL; - } - if (CMVMSG[4] & (1 << 0)) { - return ME_HDLC_UNRESOLVED; - } - } - } - return ME_HDLC_RESOLVED; -} - -int -_ifx_me_hdlc_send (unsigned char *hdlc_pkt, int pkt_len, int max_length) -{ - int ret; - u16 CMVMSG[MSG_LENGTH]; - u16 data = 0; - u16 len = 0; - int rx_length = 0; - int write_size = 0; - - if (pkt_len > max_length) { - makeCMV (H2D_CMV_READ, INFO, 85, 2, 1, NULL, CMVMSG); //Get ME-HDLC Control - ret = mei_ioctl ((struct inode *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return -EIO; - } - rx_length = CMVMSG[4]; - if (rx_length + max_length < pkt_len) { - printk ("Exceed maximum eoc rx(%d)+tx(%d) message length\n", rx_length, max_length); - return -EMSGSIZE; - } - data = 1; - makeCMV (H2D_CMV_WRITE, INFO, 85, 6, 1, &data, CMVMSG); //disable RX Eoc - ret = mei_ioctl ((struct inode *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return -EIO; - } - } - while (len < pkt_len) { - write_size = pkt_len - len; - if (write_size > 24) - write_size = 24; - //printk("len=%d,write_size=%d,pkt_len=%d\n",len,write_size,pkt_len); - memset (CMVMSG, 0, sizeof (CMVMSG)); - makeCMV (H2D_CMV_WRITE, INFO, 81, len / 2, (write_size + 1) / 2, (u16 *) (hdlc_pkt + len), CMVMSG); //Write clear eoc message to ARC - ret = mei_ioctl ((struct inode *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return -EIO; - } - len += write_size; - } - makeCMV (H2D_CMV_WRITE, INFO, 83, 2, 1, &len, CMVMSG); //Update tx message length - ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return -EIO; - } - - data = (1 << 0); - makeCMV (H2D_CMV_WRITE, CNTL, 2, 0, 1, &data, CMVMSG); //Start to send - ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return -EIO; - } - return 0; -} - -/** - * Send hdlc packets - * - * \param hdlc_pkt Pointer to hdlc packet - * \param hdlc_pkt_len The number of bytes to send - * \return success or failure. - * \ingroup Internal - */ -int -ifx_me_hdlc_send (unsigned char *hdlc_pkt, int hdlc_pkt_len) -{ - int hdlc_status = 0; - u16 CMVMSG[MSG_LENGTH]; - int max_hdlc_tx_length = 0, ret = 0, retry = 0; - int power_mode = 0; - int send_busy_counter = 0; - int send_retry = 0; - - HDLC_SEND: - // retry 1000 times (10 seconds) - while (retry < 1000) { - /* In L2 power mode, do not read the OHC related parameters, - instead give the indication to the calling IOCTL, - that the readout fails (just return -EBUSY). */ - power_mode = get_l3_power_status(); - if (power_mode == L2_POWER_MODE) { - return -EBUSY; - } - - hdlc_status = ifx_me_hdlc_status (); - if (ifx_me_is_resloved (hdlc_status) == ME_HDLC_RESOLVED) // arc ready to send HDLC message - { - makeCMV (H2D_CMV_READ, INFO, 83, 0, 1, NULL, CMVMSG); //Get Maximum Allowed HDLC Tx Message Length - ret = mei_ioctl ((struct inode *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - printk - ("ifx_me_hdlc_send failed. Return -EIO"); - return -EIO; - } - max_hdlc_tx_length = CMVMSG[4]; - ret = _ifx_me_hdlc_send (hdlc_pkt, hdlc_pkt_len, - max_hdlc_tx_length); - return ret; - } - else { - if (hdlc_status == ME_HDLC_MSG_SENT) - send_busy_counter++; - } - retry++; - MEI_WAIT (1); - } - // wait 10 seconds and FW still report busy -> reset FW HDLC status - if (send_busy_counter > 950 && send_retry == 0) { - u16 data = 0; - send_retry = 1; - retry = 0; - printk ("Reset FW HDLC status!!\n"); - send_busy_counter = 0; - data = (1 << 1); - makeCMV (H2D_CMV_WRITE, CNTL, 2, 0, 1, NULL, CMVMSG); //Force reset to idle - ret = mei_ioctl ((struct inode *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return -EIO; - } - goto HDLC_SEND; - } - printk ("ifx_me_hdlc_send failed. Return -EBUSY"); - return -EBUSY; -} - -/** - * Read the hdlc packets - * - * \param hdlc_pkt Pointer to hdlc packet - * \param hdlc_pkt_len The maximum number of bytes to read - * \return The number of bytes which reads. - * \ingroup Internal - */ -int -ifx_mei_hdlc_read (char *hdlc_pkt, int max_hdlc_pkt_len) -{ - u16 CMVMSG[MSG_LENGTH]; - int msg_read_len, ret = 0, pkt_len = 0, retry = 0; - - while (retry < 10) { - ret = ifx_me_hdlc_status (); - if (ret == ME_HDLC_RESP_RCVD) { - int current_size = 0; - makeCMV (H2D_CMV_READ, INFO, 83, 3, 1, NULL, CMVMSG); //Get EoC packet length - ret = mei_ioctl ((MEI_inode_t *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return -EIO; - } - - pkt_len = CMVMSG[4]; - if (pkt_len > max_hdlc_pkt_len) { - ret = -ENOMEM; - goto error; - } - while (current_size < pkt_len) { - if (pkt_len - current_size > - (MSG_LENGTH * 2 - 8)) - msg_read_len = (MSG_LENGTH * 2 - 8); - else - msg_read_len = - pkt_len - (current_size); - makeCMV (H2D_CMV_READ, INFO, 82, 0 + (current_size / 2), (msg_read_len + 1) / 2, NULL, CMVMSG); //Get hdlc packet - ret = mei_ioctl ((MEI_inode_t *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - goto error; - } - memcpy (hdlc_pkt + current_size, &CMVMSG[4], - msg_read_len); - current_size += msg_read_len; - } - ret = current_size; - break; - } - else { - ret = -ENODATA; - } - - retry++; - - MEI_WAIT (10); - } - error: - return ret; -} - -#if defined(IFXMIPS_CLEAR_EOC) -int -ifx_me_ceoc_send (struct sk_buff *eoc_pkt) -{ - int ret, pkt_len = 0; - unsigned char *pkt_data_ptr; - int offset = 0; - int swap_idx = 0; - - if (adsl_mode <= 8 && adsl_mode_extend == 0) // adsl mode - { - pkt_len = eoc_pkt->len; - - pkt_data_ptr = kmalloc (pkt_len + 3, GFP_KERNEL); - - offset = 2; - pkt_data_ptr[0] = 0x4c; - pkt_data_ptr[1] = 0x81; - pkt_len += 2; - } else { - pkt_len = eoc_pkt->len + 4; - pkt_data_ptr = kmalloc (pkt_len + 1 + 2, GFP_KERNEL); - memset (pkt_data_ptr, 0, pkt_len + 1 + 2); - //fill clear eoc header - pkt_data_ptr[0] = 0x1; - pkt_data_ptr[1] = 0x8; - pkt_data_ptr[2] = 0x4c; - pkt_data_ptr[3] = 0x81; - offset = 4; - } - for (swap_idx = 0; swap_idx < (eoc_pkt->len / 2) * 2; swap_idx += 2) - { - //printk("%02X %02X ",eoc_pkt->data[swap_idx],eoc_pkt->data[swap_idx+1]); - pkt_data_ptr[swap_idx + offset] = eoc_pkt->data[swap_idx + 1]; - pkt_data_ptr[swap_idx + 1 + offset] = eoc_pkt->data[swap_idx]; - } - if (eoc_pkt->len % 2) - { - //printk("%02X ",eoc_pkt->data[eoc_pkt->len-1]); - pkt_data_ptr[eoc_pkt->len - 1 + offset] = - eoc_pkt->data[eoc_pkt->len - 1]; - pkt_data_ptr[eoc_pkt->len + offset] = - eoc_pkt->data[eoc_pkt->len - 1]; - } - ret = ifx_me_hdlc_send (pkt_data_ptr, pkt_len); - - if (pkt_data_ptr != eoc_pkt->data) - { - kfree (pkt_data_ptr); - } - dev_kfree_skb (eoc_pkt); - return ret; -} - -int -get_me_ceoc_data (int pkt_len, int rx_buffer_addr, int rx_buffer_len, - u8 * data_ptr1) -{ - int ret; - MEI_ERROR dma_ret; - u16 CMVMSG[MSG_LENGTH]; - int read_size, aread_size; - int offset = 0; - u8 *data = NULL, *data_ptr = NULL; - int i, j; - int over_read = 0; - - i = j = 0; - - read_size = (pkt_len / 4) + 4; - offset = ceoc_read_idx % 4; - over_read = read_size * 4 - pkt_len - offset; - - ceoc_read_idx = (ceoc_read_idx & 0xFFFFFFFC); - - data = kmalloc (read_size * 4, GFP_KERNEL); - if (data == NULL) - goto error; - data_ptr = kmalloc (read_size * 4, GFP_KERNEL); - if (data_ptr == NULL) - goto error; - if (ceoc_read_idx + read_size * 4 >= rx_buffer_len) { - aread_size = (rx_buffer_len - ceoc_read_idx) / 4; - } - else { - aread_size = read_size; - } - - //printk("aread_size = %d,ceoc_read_idx=%d,read_size=%d,offset=%d\n",aread_size,ceoc_read_idx,read_size,offset); - dma_ret = - meiDebugRead (rx_buffer_addr + ceoc_read_idx, (u32 *) (data), - aread_size); - ceoc_read_idx += aread_size * 4; - if (aread_size != read_size) { - dma_ret = - meiDebugRead (rx_buffer_addr, - (u32 *) (data) + aread_size, - read_size - aread_size); - ceoc_read_idx = (read_size - aread_size) * 4; - } - if (ceoc_read_idx < over_read) - ceoc_read_idx = rx_buffer_len + ceoc_read_idx - over_read; - else - ceoc_read_idx -= over_read; - - if (offset == 0 || offset == 2) { - for (i = 0; i < read_size; i++) { - // 3412 --> 1234 - - for (j = 0; j < 4; j++) { - if (i * 4 + j - offset >= 0) - data_ptr[i * 4 + j - offset] = - data[i * 4 + (3 - j)]; - } - } - - } - else if (offset == 1) { - for (i = 0; i < pkt_len; i = i + 4) { - - data_ptr[i + 1] = data[i + 1]; - data_ptr[i] = data[i + 2]; - data_ptr[i + 3] = data[i + 7]; - data_ptr[i + 2] = data[i]; - } - } - else if (offset == 3) { - for (i = 0; i < pkt_len; i = i + 4) { - data_ptr[i + 1] = data[i + 7]; - data_ptr[i + 0] = data[i]; - data_ptr[i + 3] = data[i + 5]; - data_ptr[i + 2] = data[i + 6]; - } - } - if (pkt_len % 2 == 1) - data_ptr[pkt_len - 1] = data_ptr[pkt_len]; - - kfree (data); - memcpy (data_ptr1, data_ptr, pkt_len); - kfree (data_ptr); - - makeCMV (H2D_CMV_WRITE, INFO, 85, 3, 1, &ceoc_read_idx, CMVMSG); - ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - goto error; - } - - return dma_ret; - error: - kfree (data); - kfree (data_ptr); - return -1; -} - -int -ifx_me_ceoc_receive (int ceoc_write_idx, int rx_buffer_len, - struct sk_buff **eoc_pkt) -{ - u16 CMVMSG[MSG_LENGTH]; - int pkt_len, ret; - u16 lsw_addr, msw_addr; - u32 rx_buffer_addr = 0; - MEI_ERROR dma_ret; - - //printk("rx_buffer_len=%d,ceoc_read_idx=%d,ceoc_write_idx=%d\n",rx_buffer_len,ceoc_read_idx,ceoc_write_idx); - if (ceoc_write_idx > ceoc_read_idx) { - pkt_len = ceoc_write_idx - ceoc_read_idx; - } - else { - pkt_len = rx_buffer_len - ceoc_read_idx + ceoc_write_idx; - } - *eoc_pkt = dev_alloc_skb (pkt_len); - if (*eoc_pkt == NULL) { - printk ("Out of memory!\n"); - ret = -ENOMEM; - goto error; - } - - makeCMV (H2D_CMV_READ, INFO, 85, 0, 1, NULL, CMVMSG); //Get HDLC packet - ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - goto error; - } - lsw_addr = CMVMSG[4]; - - makeCMV (H2D_CMV_READ, INFO, 85, 1, 1, NULL, CMVMSG); //Get HDLC packet - ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - goto error; - } - msw_addr = CMVMSG[4]; - rx_buffer_addr = msw_addr << 16 | lsw_addr; - dma_ret = - get_me_ceoc_data (pkt_len, rx_buffer_addr, rx_buffer_len, - (u16 *) skb_put (*eoc_pkt, pkt_len)); - if (dma_ret != MEI_SUCCESS) { - ret = -EIO; - goto error; - } - - return 0; - error: - if (*eoc_pkt != NULL) - dev_kfree_skb (*eoc_pkt); - return ret; -} - -int -ifx_mei_ceoc_rx (void) -{ - u16 CMVMSG[MSG_LENGTH]; - int rx_buffer_len, ret, pkt_len = 0; - struct sk_buff *eoc_pkt; - u16 ceoc_write_idx = 0; - - makeCMV (H2D_CMV_READ, INFO, 85, 2, 1, NULL, CMVMSG); //Get EoC packet length - ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - printk ("ioctl fail!!\n"); - } - rx_buffer_len = CMVMSG[4]; - - makeCMV (H2D_CMV_READ, INFO, 85, 4, 1, NULL, CMVMSG); //Get write index - ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - if (ret != 0) { - return -EIO; - } - - ceoc_write_idx = CMVMSG[4]; - ret = ifx_me_ceoc_receive (ceoc_write_idx, rx_buffer_len, &eoc_pkt); -#if defined (CONFIG_ATM_IFXMIPS) - if (ret == 0) { - skb_pull (eoc_pkt, 2); // skip 4c 81 header - ifx_push_ceoc (eoc_pkt); //pass data to higher layer - } - - return ret; -#endif -} - -static int -adsl_clear_eoc_poll (void *unused) -{ - struct task_struct *tsk = current; - - daemonize("mei_eoc_poll"); - strcpy(tsk->comm, "mei_ceoc_poll"); - sigfillset(&tsk->blocked); - - while (1) - { - MEI_WAIT_EVENT (wait_queue_hdlc_poll); - if (showtime) - ifx_mei_ceoc_rx(); - } - return 0; -} -#endif //#if defined(IFXMIPS_CLEAR_EOC) - -#ifdef IFXMIPS_CLEAR_EOC -static int -ifxmips_mei_ceoc_init (void) -{ - kernel_thread (adsl_clear_eoc_poll, NULL, - CLONE_FS | CLONE_FILES | CLONE_SIGNAL); - return 0; -} -#endif - -////////////////////// Driver Structure /////////////////////// - -/** - * Free the memory for ARC firmware - * - * \param type Free all memory or free the unused memory after showtime - * \ingroup Internal - */ -static int -free_image_buffer (int type) -{ - int idx = 0; - for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) { - printk ("meminfo[%d].type=%d,size=%ld,addr=%X\n", idx, - adsl_mem_info[idx].type, adsl_mem_info[idx].size, - (unsigned int)adsl_mem_info[idx].address); - if (type == FREE_ALL || adsl_mem_info[idx].type == type) { - if (adsl_mem_info[idx].size > 0) { - kfree (adsl_mem_info[idx].org_address); - adsl_mem_info[idx].address = 0; - adsl_mem_info[idx].size = 0; - adsl_mem_info[idx].type = 0; - adsl_mem_info[idx].nCopy = 0; - } - } - } - return 0; -} - -/** - * Allocate memory for ARC firmware - * - * \param size The number of bytes to allocate. - * \param adsl_mem_info Pointer to firmware information. - * \ingroup Internal - */ -static int -alloc_processor_memory (unsigned long size, smmu_mem_info_t * adsl_mem_info) -{ - char *mem_ptr = NULL; - char *org_mem_ptr = NULL; - int idx = 0; - long total_size = 0; - long img_size = size; - int err = 0; - - // Alloc Swap Pages - while (img_size > 0 && idx < MAX_BAR_REGISTERS) { - // skip bar15 for XDATA usage. -#ifndef DFE_LOOPBACK - if (idx == XDATA_REGISTER) - idx++; -#endif - if (idx == MAX_BAR_REGISTERS - 1) - { - //allocate 1MB memory for bar16 - org_mem_ptr = kmalloc (1024 * 1024, GFP_ATOMIC); - mem_ptr = (char*)((unsigned long) (org_mem_ptr + 1023) & 0xFFFFFC00); - adsl_mem_info[idx].size = 1024 * 1024; - } else { - org_mem_ptr = kmalloc (SDRAM_SEGMENT_SIZE, GFP_ATOMIC); - mem_ptr = (char*)((unsigned long) (org_mem_ptr + 1023) & 0xFFFFFC00); - adsl_mem_info[idx].size = SDRAM_SEGMENT_SIZE; - } - if (org_mem_ptr == NULL) - { - printk ("kmalloc memory fail!\n"); - err = -ENOMEM; - goto allocate_error; - } - adsl_mem_info[idx].address = mem_ptr; - adsl_mem_info[idx].org_address = org_mem_ptr; - - img_size -= SDRAM_SEGMENT_SIZE; - total_size += SDRAM_SEGMENT_SIZE; - printk("alloc memory idx=%d,img_size=%ld,addr=%X\n", - idx, img_size, (unsigned int)adsl_mem_info[idx].address); - idx++; - } - if (img_size > 0) - { - printk ("Image size is too large!\n"); - err = -EFBIG; - goto allocate_error; - } - err = idx; - return err; - - allocate_error: - free_image_buffer (FREE_ALL); - return err; -} - -/** - * Program the BAR registers - * - * \param nTotalBar The number of bar to program. - * \ingroup Internal - */ -static int -update_bar_register (int nTotalBar) -{ - int idx = 0; - - for (idx = 0; idx < nTotalBar; idx++) { - //skip XDATA register - if (idx == XDATA_REGISTER) - idx++; - meiLongwordWrite ( MEI_XMEM_BAR_BASE + idx * 4, - (((uint32_t) adsl_mem_info[idx]. - address) & 0x0FFFFFFF)); - printk ("BAR%d=%08X, addr=%08X\n", idx, - (((uint32_t) adsl_mem_info[idx]. - address) & 0x0FFFFFFF), - (((uint32_t) adsl_mem_info[idx].address))); - } - for (idx = nTotalBar; idx < MAX_BAR_REGISTERS; idx++) { - if (idx == XDATA_REGISTER) - idx++; - meiLongwordWrite ( MEI_XMEM_BAR_BASE + idx * 4, - (((uint32_t) adsl_mem_info[nTotalBar - 1]. - address) & 0x0FFFFFFF)); - } - - meiLongwordWrite (MEI_XMEM_BAR_BASE + XDATA_REGISTER * 4, - (((uint32_t) adsl_mem_info[XDATA_REGISTER]. - address) & 0x0FFFFFFF)); - // update MEI_XDATA_BASE_SH - printk ("update bar15 register with %08lX\n", - ((unsigned long) adsl_mem_info[XDATA_REGISTER]. - address) & 0x0FFFFFFF); - meiLongwordWrite (MEI_XDATA_BASE_SH, - ((unsigned long) adsl_mem_info[XDATA_REGISTER]. - address) & 0x0FFFFFFF); - return MEI_SUCCESS; -} - -/** - * Copy the firmware to BARs memory. - * - * \param filp Pointer to the file structure. - * \param buf Pointer to the data. - * \param size The number of bytes to copy. - * \param loff The file offset. - * \return The current file position. - * \ingroup Internal - */ -ssize_t -mei_write (MEI_file_t * filp, char *buf, size_t size, loff_t * loff) -{ - ARC_IMG_HDR img_hdr_tmp, *img_hdr; - - size_t nRead = 0, nCopy = 0; - char *mem_ptr; - ssize_t retval = -ENOMEM; - int idx = 0; - - if (*loff == 0) { - if (size < sizeof (img_hdr)) { - printk ("Firmware size is too small!\n"); - return retval; - } - copy_from_user ((char *) &img_hdr_tmp, buf, - sizeof (img_hdr_tmp)); - image_size = le32_to_cpu (img_hdr_tmp.size) + 8; // header of image_size and crc are not included. - if (image_size > 1024 * 1024) { - printk ("Firmware size is too large!\n"); - return retval; - } - // check if arc is halt - if (arc_halt_flag != 1) { - meiResetARC (); - meiHaltArc (); - } - - // reset part of PPE - *(unsigned long *) (IFXMIPS_PPE32_SRST) = 0xC30; - *(unsigned long *) (IFXMIPS_PPE32_SRST) = 0xFFF; - - free_image_buffer (FREE_ALL); //free all - - retval = alloc_processor_memory (image_size, adsl_mem_info); - if (retval < 0) { - printk ("Error: No memory space left.\n"); - goto error; - } - - for (idx = 0; idx < retval; idx++) { - //skip XDATA register - if (idx == XDATA_REGISTER) - idx++; - if (idx * SDRAM_SEGMENT_SIZE < - le32_to_cpu (img_hdr_tmp.page[0].p_offset)) { - adsl_mem_info[idx].type = FREE_RELOAD; - } - else { - adsl_mem_info[idx].type = FREE_SHOWTIME; - } - - } - nBar = retval; - - img_hdr = (ARC_IMG_HDR *) adsl_mem_info[0].address; - -#if !defined(__LINUX__) - adsl_mem_info[XDATA_REGISTER].org_address = - kmalloc (SDRAM_SEGMENT_SIZE + 1023, GFP_ATOMIC); -#else - adsl_mem_info[XDATA_REGISTER].org_address = - kmalloc (SDRAM_SEGMENT_SIZE, GFP_ATOMIC); -#endif - adsl_mem_info[XDATA_REGISTER].address = - (char - *) ((unsigned long) (adsl_mem_info[XDATA_REGISTER]. - org_address + - 1023) & 0xFFFFFC00); - adsl_mem_info[XDATA_REGISTER].size = SDRAM_SEGMENT_SIZE; - if (adsl_mem_info[XDATA_REGISTER].address == NULL) { - printk ("kmalloc memory fail!\n"); - retval = -ENOMEM; - goto error; - } - adsl_mem_info[XDATA_REGISTER].type = FREE_RELOAD; - update_bar_register (nBar); - - } - else if (image_size == 0) { - printk ("Error: Firmware size=0! \n"); - goto error; - } - else { - if (arc_halt_flag == 0) { - printk - ("Please download the firmware from the beginning of the firmware!\n"); - goto error; - } - } - - nRead = 0; - while (nRead < size) { - long offset = ((long) (*loff) + nRead) % SDRAM_SEGMENT_SIZE; - idx = (((long) (*loff)) + nRead) / SDRAM_SEGMENT_SIZE; - mem_ptr = (char *) - KSEG1ADDR ((unsigned long) (adsl_mem_info[idx]. - address) + offset); - if ((size - nRead + offset) > SDRAM_SEGMENT_SIZE) - nCopy = SDRAM_SEGMENT_SIZE - offset; - else - nCopy = size - nRead; - copy_from_user (mem_ptr, buf + nRead, nCopy); -#ifdef IMAGE_SWAP - for (offset = 0; offset < (nCopy / 4); offset++) { - ((unsigned long *) mem_ptr)[offset] = - le32_to_cpu (((unsigned long *) - mem_ptr)[offset]); - } -#endif //IMAGE_SWAP - nRead += nCopy; - adsl_mem_info[idx].nCopy += nCopy; - } - -#if ( defined(HEADER_SWAP) && !defined(IMAGE_SWAP)) || (defined(IMAGE_SWAP) && !defined(HEADER_SWAP)) - if (*loff == 0) { - - for (idx = 0; - idx < - (sizeof (ARC_IMG_HDR) + - (le32_to_cpu (img_hdr_tmp.count) - - 1) * sizeof (ARC_SWP_PAGE_HDR)) / 4; idx++) { - ((unsigned long *) img_hdr)[idx] = - le32_to_cpu (((unsigned long *) - img_hdr)[idx]); - } - } -#endif //( defined(HEADER_SWAP) && !defined(IMAGE_SWAP)) || (defined(IMAGE_SWAP) && !defined(HEADER_SWAP)) - printk ("size=%X,loff=%08X\n", size, (unsigned int) *loff); - - *loff += size; - return size; - error: - free_image_buffer (FREE_ALL); - - return retval; -} - -/******************************************************** - * L3 Power Mode * - ********************************************************/ -/** - * Send a CMV message. - * This function sends a CMV message to ARC - * - * \param opcode The message opcode - * \param group The message group number - * \param address The message address. - * \param index The message index. - * \param size The number of words to read/write. - * \param data The pointer to data. - * \param CMVMSG The pointer to message buffer. - * \return 0: success - * \ingroup Internal - */ -int -send_cmv (u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data, u16 * CMVMSG) -{ - int ret; - - makeCMV(opcode, group, address, index, size, data, CMVMSG); - ret = mei_ioctl((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, (unsigned long)CMVMSG); - return ret; -} - -#ifdef IFX_ADSL_L3_MODE_SUPPORT - -/** - * Check the L3 request from CO - * This function Check if CPE received the L3 request from CO - * \return 1: got L3 request. - * \ingroup Internal - */ -int -check_co_l3_shutdown_request (void) -{ - u16 CMVMSG[MSG_LENGTH]; - if (modem_ready == 1) { - if (send_cmv (H2D_CMV_READ, STAT, 4, 0, 1, NULL, CMVMSG) != 0) { - return -EBUSY; - } - if (CMVMSG[4] & BIT14) { - return 1; - } - } - return 0; -} - -/** - * Check the L3 status - * This function get the CPE Power Management Mode status - * \return 0: L0 Mode - * 2: L2 Mode - * 3: L3 Mode - * \ingroup Internal - */ -int -get_l3_power_status (void) -{ - u16 CMVMSG[MSG_LENGTH]; - if (modem_ready == 0) { - return L3_POWER_MODE; - } - else { - if (send_cmv (H2D_CMV_READ, STAT, 18, 0, 1, NULL, CMVMSG) != - 0) { - return -EBUSY; - } - return ((int) CMVMSG[4]); - - } - return 0; -} - -/** - * Send a L3 request to CO - * This function send a L3 request to CO and check the CO response. - * \return 0: Success. Others: Fail. - * \ingroup Internal - */ -int -send_l3_shutdown_cmd (void) -{ - u16 cmd = 0x1; - int nRetry = 0; - u16 CMVMSG[MSG_LENGTH]; - - if (modem_ready == 0) { - return -EBUSY; - } - // send l3 request to CO - if (send_cmv (H2D_CMV_WRITE, CNTL, 3, 0, 1, &cmd, CMVMSG) != 0) { - return -EBUSY; - } - retry: - MEI_WAIT (10); - - // check CO response - if (send_cmv (H2D_CMV_READ, STAT, 20, 0, 1, NULL, CMVMSG) != 0) { - return -EBUSY; - } - if (CMVMSG[4] == 0) { - nRetry++; - if (nRetry < 10) { - goto retry; - } - else { - return -EBUSY; - } - - } - else if (CMVMSG[4] == 1) // reject - { - return -EPERM; - } - else if (CMVMSG[4] == 2) // ok - { - return 0; - } - else if (CMVMSG[4] == 3) // failure - { - return -EAGAIN; - } - return 0; -} - -/** - * Enable L3 Power Mode - * This function send a L3 request to CO and check the CO response. Then reboot the CPE to enter L3 Mode. - * \return 0: Success. Others: Fail. - * \ingroup Internal - */ -int -set_l3_shutdown (void) -{ - int ret = 0; - if (l3_shutdown == 0) { - // send l3 request to CO - ret = send_l3_shutdown_cmd (); - if (ret == 0) //got CO ACK - { - //reboot adsl and block autoboot daemon - ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_REBOOT, (unsigned long)NULL); - l3_shutdown = 1; - } - } - return ret; -} - -/** - * Disable L3 Power Mode - * This function disable L3 Mode and wake up the autoboot daemon. - * \return 0: Success. - * \ingroup Internal - */ -//l3 power mode disable -int -set_l3_power_on (void) -{ - if (l3_shutdown == 1) { - l3_shutdown = 0; - // wakeup autoboot daemon - MEI_WAKEUP_EVENT (wait_queue_l3); - - } - return 0; -} - -/******************************************************** - * End of L3 Power Mode * - ********************************************************/ -#endif //IFX_ADSL_L3_MODE_SUPPORT - -#ifdef CONFIG_IFXMIPS_MEI_LED -/* - * LED Initialization function - */ -int -meiADSLLedInit (void) -{ - u16 data = 0x0600; - u16 CMVMSG[MSG_LENGTH]; - - data = 0x0400; -#if defined(DATA_LED_SUPPORT) && defined (DATA_LED_ADSL_FW_HANDLE) - data |= 0x200; -#endif - // Setup ADSL Link/Data LED - if (send_cmv (H2D_CMV_WRITE, INFO, 91, 0, 1, &data, CMVMSG) != 0) { - return -EBUSY; - } - - if (send_cmv (H2D_CMV_WRITE, INFO, 91, 2, 1, &data, CMVMSG) != 0) { - return -EBUSY; - } - - // Let FW to handle ADSL Link LED - data = 0x0a03; //invert the LED signal as per input from Stefan on 13/11/2006 - if (send_cmv (H2D_CMV_WRITE, INFO, 91, 4, 1, &data, CMVMSG) != 0) { - return -EBUSY; - } - -#ifdef DATA_LED_SUPPORT -#ifdef DATA_LED_ADSL_FW_HANDLE - - // Turn ADSL Data LED on - data = 0x0900; - if (send_cmv (H2D_CMV_WRITE, INFO, 91, 5, 1, &data, CMVMSG) != 0) { - return -EBUSY; - } -#else - ifxmips_led_set(0x1); -#endif -#endif - return 0; -} -#endif - -#ifdef IFX_ADSL_DUAL_LATENCY_SUPPORT -/* - * Dual Latency Path Initialization function - */ -int -meiDualLatencyInit (void) -{ - u16 nDual = 0; - u16 CMVMSG[MSG_LENGTH]; - - // setup up stream path - if (bDualLatency & DUAL_LATENCY_US_ENABLE) { - nDual = 2; - } - else { - nDual = 1; - } - - if (send_cmv (H2D_CMV_WRITE, CNFG, 10, 0, 1, &nDual, CMVMSG) != 0) { - return -EBUSY; - } - - if (send_cmv (H2D_CMV_WRITE, CNFG, 11, 0, 1, &nDual, CMVMSG) != 0) { - return -EBUSY; - } - - // setup down stream path - if (bDualLatency & DUAL_LATENCY_DS_ENABLE) { - nDual = 2; - } - else { - nDual = 1; - } - - if (send_cmv (H2D_CMV_WRITE, CNFG, 21, 0, 1, &nDual, CMVMSG) != 0) { - return -EBUSY; - } - if (send_cmv (H2D_CMV_WRITE, CNFG, 22, 0, 1, &nDual, CMVMSG) != 0) { - return -EBUSY; - } - return 0; -} - -int -mei_is_dual_latency_enabled (void) -{ - return bDualLatency; -} -#endif - -int -meiAdslStartupInit (void) -{ -#ifdef CONFIG_IFXMIPS_MEI_LED - meiADSLLedInit (); -#endif -#ifdef IFX_ADSL_DUAL_LATENCY_SUPPORT - meiDualLatencyInit (); -#endif - return 0; -} - -/** - * MEI IO controls for user space accessing - * - * \param ino Pointer to the stucture of inode. - * \param fil Pointer to the stucture of file. - * \param command The ioctl command. - * \param lon The address of data. - * \return Success or failure. - * \ingroup Internal - */ -int -mei_ioctl (MEI_inode_t * ino, MEI_file_t * fil, unsigned int command, - unsigned long lon) -{ - int i; - - int meierr = MEI_SUCCESS; - meireg regrdwr; - meidebug debugrdwr; - u32 arc_debug_data, reg_data; -#ifdef IFXMIPS_CLEAR_EOC - u16 data; - struct sk_buff *eoc_skb; -#endif //IFXMIPS_CLEAR_EOC - u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4))); - u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4))); - - int from_kernel = 0; //joelin - if (ino == (MEI_inode_t *) 0) - from_kernel = 1; //joelin - if (command < IFXMIPS_MEI_START) { -#ifdef CONFIG_IFXMIPS_MEI_MIB - return mei_mib_ioctl (ino, fil, command, lon); -#endif //CONFIG_IFXMIPS_MEI_MIB - - if (command == IFXMIPS_MIB_LO_ATUR - || command == IFXMIPS_MIB_LO_ATUC) - return MEI_SUCCESS; - printk - ("No such ioctl command (0x%X)! MEI ADSL MIB is not supported!\n", - command); - return -ENOIOCTLCMD; - } - else { - switch (command) { - case IFXMIPS_MEI_START: - - showtime = 0; - loop_diagnostics_completed = 0; - if (time_disconnect.tv_sec == 0) - do_gettimeofday (&time_disconnect); - - if (MEI_MUTEX_LOCK (mei_sema)) //disable CMV access until ARC ready - { - printk ("-ERESTARTSYS\n"); - return -ERESTARTSYS; - } - - meiMailboxInterruptsDisable (); //disable all MEI interrupts - if (mei_arc_swap_buff == NULL) { - mei_arc_swap_buff = - (u32 *) kmalloc (MAXSWAPSIZE * 4, - GFP_KERNEL); - if (mei_arc_swap_buff == NULL) { - printk - ("\n\n malloc fail for codeswap buff"); - meierr = MEI_FAILURE; - } - } - if (meiRunAdslModem () != MEI_SUCCESS) { - printk - ("meiRunAdslModem() error..."); - meierr = MEI_FAILURE; - } -#ifdef IFX_ADSL_L3_MODE_SUPPORT - /* L3 Power Mode Start */ - if (l3_shutdown == 1) { - // block autoboot daemon until l3 power mode disable - MEI_WAIT_EVENT (wait_queue_l3); - } - /* L3 Power Mode End */ -#endif //IFX_ADSL_L3_MODE_SUPPORT - if (autoboot_enable_flag) - meiAdslStartupInit (); - break; - - case IFXMIPS_MEI_SHOWTIME: - if (MEI_MUTEX_LOCK (mei_sema)) - return -ERESTARTSYS; - - do_gettimeofday (&time_showtime); - unavailable_seconds += - time_showtime.tv_sec - time_disconnect.tv_sec; - time_disconnect.tv_sec = 0; - makeCMV (H2D_CMV_READ, RATE, 0, 0, 4, NULL, TxMessage); //maximum allowed tx message length, in bytes - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != - MEI_SUCCESS) { - printk - ("\n\nCMV fail, Group RAGE Address 0 Index 0"); - } - else { - u32 rate_fast; - u32 rate_intl; - rate_intl = RxMessage[4] | RxMessage[5] << 16; - rate_fast = RxMessage[6] | RxMessage[7] << 16; - // 609251:tc.chen Fix ATM QoS issue start - if (rate_intl && rate_fast) // apply cell rate to each path - { -#ifdef CONFIG_ATM_IFXMIPS - ifx_atm_set_cell_rate (1, - rate_intl / - (53 * 8)); - ifx_atm_set_cell_rate (0, - rate_fast / - (53 * 8)); -#endif - } - else if (rate_fast) // apply fast path cell rate to atm interface 0 - { -#ifdef CONFIG_ATM_IFXMIPS - ifx_atm_set_cell_rate (0, - rate_fast / - (53 * 8)); -#endif - } - else if (rate_intl) // apply interleave path cell rate to atm interface 0 - { -#ifdef CONFIG_ATM_IFXMIPS - ifx_atm_set_cell_rate (0, - rate_intl / - (53 * 8)); -#endif - } - else { - printk ("Got rate fail.\n"); - } - // 609251:tc.chen end - } - -#ifdef IFXMIPS_CLEAR_EOC - data = 1; - makeCMV (H2D_CMV_WRITE, OPTN, 24, 0, 1, &data, - TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != - MEI_SUCCESS) { - printk ("Enable clear eoc fail!\n"); - } -#endif - // read adsl mode - makeCMV (H2D_CMV_READ, STAT, 1, 0, 1, NULL, - TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != - MEI_SUCCESS) { -#ifdef IFXMIPS_MEI_DEBUG_ON - printk ("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - } - adsl_mode = RxMessage[4]; - makeCMV (H2D_CMV_READ, STAT, 17, 0, 1, NULL, - TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != - MEI_SUCCESS) { -#ifdef IFXMIPS_MEI_DEBUG_ON - printk ("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - } - adsl_mode_extend = RxMessage[4]; -#ifdef CONFIG_IFXMIPS_MEI_MIB - mei_mib_adsl_link_up (); -#endif - -//joelin 04/16/2005-start - makeCMV (H2D_CMV_WRITE, PLAM, 10, 0, 1, - &unavailable_seconds, TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != - MEI_SUCCESS) { - printk - ("\n\nCMV fail, Group 7 Address 10 Index 0"); - } - -//joelin 04/16/2005-end - showtime = 1; - free_image_buffer (FREE_SHOWTIME); - MEI_MUTEX_UNLOCK (mei_sema); - break; - - case IFXMIPS_MEI_HALT: - if (arc_halt_flag == 0) { - meiResetARC (); - meiHaltArc (); - } - break; - case IFXMIPS_MEI_RUN: - if (arc_halt_flag == 1) { - meiRunArc (); - } - break; - case IFXMIPS_MEI_CMV_WINHOST: - if (MEI_MUTEX_LOCK (mei_sema)) - return -ERESTARTSYS; - - if (!from_kernel) - copy_from_user ((char *) TxMessage, (char *) lon, MSG_LENGTH * 2); //joelin - else - memcpy (TxMessage, (char *) lon, - MSG_LENGTH * 2); - - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != - MEI_SUCCESS) { - printk - ("\n\nWINHOST CMV fail :TxMessage:%X %X %X %X, RxMessage:%X %X %X %X %X\n", - TxMessage[0], TxMessage[1], - TxMessage[2], TxMessage[3], - RxMessage[0], RxMessage[1], - RxMessage[2], RxMessage[3], - RxMessage[4]); - meierr = MEI_FAILURE; - } - else { - if (!from_kernel) //joelin - copy_to_user ((char *) lon, - (char *) RxMessage, - MSG_LENGTH * 2); - else - memcpy ((char *) lon, - (char *) RxMessage, - MSG_LENGTH * 2); - } - - MEI_MUTEX_UNLOCK (mei_sema); - break; -#ifdef IFXMIPS_MEI_CMV_EXTRA - case IFXMIPS_MEI_CMV_READ: - copy_from_user ((char *) (®rdwr), (char *) lon, - sizeof (meireg)); - meiLongwordRead ((u32*)regrdwr.iAddress, &(regrdwr.iData)); - - copy_to_user((char *) lon, (char *) (®rdwr), sizeof (meireg)); - break; - - case IFXMIPS_MEI_CMV_WRITE: - copy_from_user ((char *) (®rdwr), (char *) lon, sizeof (meireg)); - meiLongwordWrite ((u32*)regrdwr.iAddress, regrdwr.iData); - break; - - case IFXMIPS_MEI_REMOTE: - copy_from_user ((char *) (&i), (char *) lon, - sizeof (int)); - if (i == 0) { - meiMailboxInterruptsEnable (); - - MEI_MUTEX_UNLOCK (mei_sema); - } - else if (i == 1) { - meiMailboxInterruptsDisable (); - if (MEI_MUTEX_LOCK (mei_sema)) - return -ERESTARTSYS; - } - else { - printk - ("\n\n IFXMIPS_MEI_REMOTE argument error"); - meierr = MEI_FAILURE; - } - break; - - case IFXMIPS_MEI_READDEBUG: - case IFXMIPS_MEI_WRITEDEBUG: -#if 0 //tc.chen:It is no necessary to acquire lock to read debug memory!! - if (MEI_MUTEX_LOCK (mei_sema)) - return -ERESTARTSYS; -#endif - if (!from_kernel) - copy_from_user ((char *) (&debugrdwr), - (char *) lon, - sizeof (debugrdwr)); - else - memcpy ((char *) (&debugrdwr), (char *) lon, - sizeof (debugrdwr)); - - if (command == IFXMIPS_MEI_READDEBUG) - meiDebugRead (debugrdwr.iAddress, - debugrdwr.buffer, - debugrdwr.iCount); - else - meiDebugWrite (debugrdwr.iAddress, - debugrdwr.buffer, - debugrdwr.iCount); - - if (!from_kernel) - copy_to_user ((char *) lon, (char *) (&debugrdwr), sizeof (debugrdwr)); //dying gasp -#if 0 //tc.chen:It is no necessary to acquire lock to read debug memory!! - MEI_MUTEX_UNLOCK (mei_sema); -#endif - break; - case IFXMIPS_MEI_RESET: - case IFXMIPS_MEI_REBOOT: - -#ifdef CONFIG_IFXMIPS_MEI_MIB - mei_mib_adsl_link_down (); -#endif - -#ifdef IFX_ADSL_L3_MODE_SUPPORT - /* L3 Power Mode start */ - if (check_co_l3_shutdown_request () == 1) //co request - { - // cpe received co L3 request - l3_shutdown = 1; - } - /* L3 Power Mode end */ -#endif //IFX_ADSL_L3_MODE_SUPPORT - - meiResetARC (); - meiControlModeSwitch (MEI_MASTER_MODE); - //enable ac_clk signal - _meiDebugLongWordRead (MEI_DEBUG_DEC_DMP1_MASK, - CRI_CCR0, &arc_debug_data); - arc_debug_data |= ACL_CLK_MODE_ENABLE; - _meiDebugLongWordWrite (MEI_DEBUG_DEC_DMP1_MASK, - CRI_CCR0, arc_debug_data); - meiControlModeSwitch (JTAG_MASTER_MODE); - meiHaltArc (); - update_bar_register (nBar); - break; - case IFXMIPS_MEI_DOWNLOAD: - // DMA the boot code page(s) - printk ("Start download pages"); - meiDownloadBootPages (); - break; -#endif //IFXMIPS_MEI_CMV_EXTRA - //for clearEoC -#ifdef IFXMIPS_CLEAR_EOC - case IFXMIPS_MEI_EOC_SEND: - if (!showtime) { - return -EIO; - } - if (!from_kernel) { - copy_from_user ((char *) (&debugrdwr), - (char *) lon, - sizeof (debugrdwr)); - eoc_skb = - dev_alloc_skb (debugrdwr.iCount * 4); - if (eoc_skb == NULL) { - printk - ("\n\nskb alloc fail"); - break; - } - - eoc_skb->len = debugrdwr.iCount * 4; - memcpy (skb_put - (eoc_skb, debugrdwr.iCount * 4), - (char *) debugrdwr.buffer, - debugrdwr.iCount * 4); - } - else { - eoc_skb = (struct sk_buff *) lon; - } - ifx_me_ceoc_send (eoc_skb); //pass data to higher layer - break; -#endif // IFXMIPS_CLEAR_EOC - case IFXMIPS_MEI_JTAG_ENABLE: - printk ("ARC JTAG Enable.\n"); - *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) & (~0x800); // set gpio11 to input - *(IFXMIPS_GPIO_P0_ALTSEL0) = ((*IFXMIPS_GPIO_P0_ALTSEL0) & (~0x800)); - *(IFXMIPS_GPIO_P0_ALTSEL1) = ((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x800)); - *IFXMIPS_GPIO_P0_OD = (*IFXMIPS_GPIO_P0_OD) | 0x800; - - //enable ARC JTAG - meiLongwordRead(IFXMIPS_RCU_RST, ®_data); - meiLongwordWrite(IFXMIPS_RCU_RST, reg_data | IFXMIPS_RCU_RST_REQ_ARC_JTAG); - break; - - case GET_ADSL_LOOP_DIAGNOSTICS_MODE: - copy_to_user ((char *) lon, (char *) &loop_diagnostics_mode, sizeof(int)); - break; - case LOOP_DIAGNOSTIC_MODE_COMPLETE: - loop_diagnostics_completed = 1; -#ifdef CONFIG_IFXMIPS_MEI_MIB - // read adsl mode - makeCMV (H2D_CMV_READ, STAT, 1, 0, 1, NULL, TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) { -#ifdef IFXMIPS_MEI_DEBUG_ON - printk ("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - } - adsl_mode = RxMessage[4]; - - makeCMV (H2D_CMV_READ, STAT, 17, 0, 1, NULL, TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) { -#ifdef IFXMIPS_MEI_DEBUG_ON - printk ("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - } - adsl_mode_extend = RxMessage[4]; -#endif - MEI_WAKEUP_EVENT (wait_queue_loop_diagnostic); - break; - case SET_ADSL_LOOP_DIAGNOSTICS_MODE: - if (lon != loop_diagnostics_mode) { - loop_diagnostics_completed = 0; - loop_diagnostics_mode = lon; -#if 0 //08/12/2006 tc.chen : autoboot daemon should reset dsl - mei_ioctl ((MEI_inode_t *) 0, NULL, - IFXMIPS_MEI_REBOOT, - (unsigned long) NULL); -#endif - } - break; - case IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE: - copy_to_user ((char *) lon, - (char *) &loop_diagnostics_completed, - sizeof (int)); - break; -#ifdef IFX_ADSL_L3_MODE_SUPPORT - /* L3 Power Mode Start */ - case GET_POWER_MANAGEMENT_MODE: - i = get_l3_power_status (); - copy_to_user ((char *) lon, (char *) &i, - sizeof (int)); - break; - case SET_L3_POWER_MODE: - i = 1; - copy_from_user ((char *) &i, (char *) lon, - sizeof (int)); - if (i == 0) { - return set_l3_shutdown (); - } - else { - return set_l3_power_on (); - } - break; - /* L3 Power Mode End */ -#endif //IFX_ADSL_L3_MODE_SUPPORT -#ifdef IFX_ADSL_DUAL_LATENCY_SUPPORT - case GET_ADSL_DUAL_LATENCY: - i = mei_is_dual_latency_enabled (); - if (i < 0) - return i; - copy_to_user ((char *) lon, (char *) &i, - sizeof (int)); - break; - case SET_ADSL_DUAL_LATENCY: - i = 0; - copy_from_user ((char *) &i, (char *) lon, - sizeof (int)); - if (i > DUAL_LATENCY_US_DS_ENABLE) { - return -EINVAL; - } - if (i != bDualLatency) { - bDualLatency = i; - i = 1; // DualLatency update,need to reboot arc - } - else { - i = 0; // DualLatency is the same - } - if (modem_ready && i) // modem is already start, reboot arc to apply Dual Latency changed - { - mei_ioctl ((MEI_inode_t *) 0, NULL, - IFXMIPS_MEI_REBOOT, - (unsigned long) NULL); - } - break; - -#endif - case QUIET_MODE_GET: - copy_to_user ((char *) lon, (char *) &quiet_mode_flag, - sizeof (int)); - break; - case QUIET_MODE_SET: - copy_from_user ((char *) &i, (char *) lon, - sizeof (int)); - if (i > 1 || i < 0) - return -EINVAL; - if (i == 1) { - u16 CMVMSG[MSG_LENGTH]; - u16 data = 0; - makeCMV (H2D_CMV_WRITE, INFO, 94, 0, 1, &data, CMVMSG); // set tx power to 0 - meierr = mei_ioctl ((struct inode *) 0, NULL, - IFXMIPS_MEI_CMV_WINHOST, - (unsigned long) CMVMSG); - } - quiet_mode_flag = i; - break; - case SHOWTIME_LOCK_GET: - copy_to_user ((char *) lon, - (char *) &showtime_lock_flag, - sizeof (int)); - break; - case SHOWTIME_LOCK_SET: - copy_from_user ((char *) &i, (char *) lon, - sizeof (int)); - if (i > 1 || i < 0) - return -EINVAL; - showtime_lock_flag = i; - break; - case AUTOBOOT_ENABLE_SET: - copy_from_user ((char *) &i, (char *) lon, - sizeof (int)); - if (i > 1 || i < 0) - return -EINVAL; - autoboot_enable_flag = i; - break; - default: - printk - ("The ioctl command(0x%X is not supported!\n", - command); - meierr = -ENOIOCTLCMD; - } - } - return meierr; -} //mei_ioctl - -//////////////////// procfs debug /////////////////////////// - -#ifdef CONFIG_PROC_FS -static int -proc_read (struct file *file, char *buf, size_t nbytes, loff_t * ppos) -{ - int i_ino = (file->f_dentry->d_inode)->i_ino; - char outputbuf[64]; - int count = 0; - int i; - u32 version = 0; - reg_entry_t *current_reg = NULL; - u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4))); - u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4))); - - for (i = 0; i < NUM_OF_REG_ENTRY; i++) { - if (regs[i].low_ino == i_ino) { - current_reg = ®s[i]; - break; - } - } - if (current_reg == NULL) - return -EINVAL; - - if (current_reg->flag == (int *) 8) { - ///proc/mei/version - //format: - //Firmware version: major.minor.sub_version.int_version.rel_state.spl_appl - ///Firmware Date Time Code: date/month min:hour - if (*ppos > 0) /* Assume reading completed in previous read */ - return 0; // indicates end of file - if (MEI_MUTEX_LOCK (mei_sema)) - return -ERESTARTSYS; - - if (indicator_count < 1) { - MEI_MUTEX_UNLOCK (mei_sema); - return -EAGAIN; - } - //major:bits 0-7 - //minor:bits 8-15 - makeCMV (H2D_CMV_READ, INFO, 54, 0, 1, NULL, TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) { - MEI_MUTEX_UNLOCK (mei_sema); - return -EIO; - } - version = RxMessage[4]; - count = sprintf (outputbuf, "%d.%d.", (version) & 0xff, - (version >> 8) & 0xff); - - //sub_version:bits 4-7 - //int_version:bits 0-3 - //spl_appl:bits 8-13 - //rel_state:bits 14-15 - makeCMV (H2D_CMV_READ, INFO, 54, 1, 1, NULL, TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) { - MEI_MUTEX_UNLOCK (mei_sema); - return -EFAULT; - } - version = RxMessage[4]; - count += sprintf (outputbuf + count, "%d.%d.%d.%d", - (version >> 4) & 0xf, - version & 0xf, - (version >> 14) & 0x3, - (version >> 8) & 0x3f); - //Date:bits 0-7 - //Month:bits 8-15 - makeCMV (H2D_CMV_READ, INFO, 55, 0, 1, NULL, TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) { - MEI_MUTEX_UNLOCK (mei_sema); - return -EIO; - } - version = RxMessage[4]; - - //Hour:bits 0-7 - //Minute:bits 8-15 - makeCMV (H2D_CMV_READ, INFO, 55, 1, 1, NULL, TxMessage); - if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) { - MEI_MUTEX_UNLOCK (mei_sema); - return -EFAULT; - } - version += (RxMessage[4] << 16); - count += sprintf (outputbuf + count, " %d/%d %d:%d\n", - version & 0xff, (version >> 8) & 0xff, - (version >> 25) & 0xff, - (version >> 16) & 0xff); - MEI_MUTEX_UNLOCK (mei_sema); - - *ppos += count; - } - else if (current_reg->flag != (int *) Recent_indicator) { - if (*ppos > 0) /* Assume reading completed in previous read */ - return 0; // indicates end of file - count = sprintf (outputbuf, "0x%08X\n\n", - *(current_reg->flag)); - *ppos += count; - if (count > nbytes) /* Assume output can be read at one time */ - return -EINVAL; - } - else { - if ((int) (*ppos) / ((int) 7) == 16) - return 0; // indicate end of the message - count = sprintf (outputbuf, "0x%04X\n\n", - *(((u16 *) (current_reg->flag)) + - (int) (*ppos) / ((int) 7))); - *ppos += count; - } - if (copy_to_user (buf, outputbuf, count)) - return -EFAULT; - return count; -} - -static ssize_t -proc_write (struct file *file, const char *buffer, size_t count, - loff_t * ppos) -{ - int i_ino = (file->f_dentry->d_inode)->i_ino; - reg_entry_t *current_reg = NULL; - int i; - unsigned long newRegValue; - char *endp; - - for (i = 0; i < NUM_OF_REG_ENTRY; i++) { - if (regs[i].low_ino == i_ino) { - current_reg = ®s[i]; - break; - } - } - if ((current_reg == NULL) - || (current_reg->flag == (int *) Recent_indicator)) - return -EINVAL; - - newRegValue = simple_strtoul (buffer, &endp, 0); - *(current_reg->flag) = (int) newRegValue; - return (count + endp - buffer); -} -#endif //CONFIG_PROC_FS - -//TODO, for loopback test -#ifdef DFE_LOOPBACK -#define mte_reg_base (0x4800*4+0x20000) - -/* Iridia Registers Address Constants */ -#define MTE_Reg(r) (int)(mte_reg_base + (r*4)) - -#define IT_AMODE MTE_Reg(0x0004) - -#define OMBOX_BASE 0xDF80 -#define OMBOX1 (OMBOX_BASE+0x4) -#define IMBOX_BASE 0xDFC0 - -#define TIMER_DELAY (1024) -#define BC0_BYTES (32) -#define BC1_BYTES (30) -#define NUM_MB (12) -#define TIMEOUT_VALUE 2000 - -static void -BFMWait (u32 cycle) -{ - u32 i; - for (i = 0; i < cycle; i++); -} - -static void -WriteRegLong (u32 addr, u32 data) -{ - //*((volatile u32 *)(addr)) = data; - IFXMIPS_WRITE_REGISTER_L (data, addr); -} - -static u32 -ReadRegLong (u32 addr) -{ - // u32 rd_val; - //rd_val = *((volatile u32 *)(addr)); - // return rd_val; - return IFXMIPS_READ_REGISTER_L (addr); -} - -/* This routine writes the mailbox with the data in an input array */ -static void -WriteMbox (u32 * mboxarray, u32 size) -{ - meiDebugWrite (IMBOX_BASE, mboxarray, size); - printk ("write to %X\n", IMBOX_BASE); - meiLongwordWrite ( MEI_TO_ARC_INT, MEI_TO_ARC_MSGAV); -} - -/* This routine reads the output mailbox and places the results into an array */ -static void -ReadMbox (u32 * mboxarray, u32 size) -{ - meiDebugRead (OMBOX_BASE, mboxarray, size); - printk ("read from %X\n", OMBOX_BASE); -} - -static void -MEIWriteARCValue (u32 address, u32 value) -{ - u32 i, check = 0; - - /* Write address register */ - IFXMIPS_WRITE_REGISTER_L (address, MEI_DEBUG_WAD); - - /* Write data register */ - IFXMIPS_WRITE_REGISTER_L (value, MEI_DEBUG_DATA); - - /* wait until complete - timeout at 40 */ - for (i = 0; i < 40; i++) { - check = IFXMIPS_READ_REGISTER_L (ARC_TO_MEI_INT); - - if ((check & ARC_TO_MEI_DBG_DONE)) - break; - } - /* clear the flag */ - IFXMIPS_WRITE_REGISTER_L (ARC_TO_MEI_DBG_DONE, ARC_TO_MEI_INT); -} - -void -arc_code_page_download (uint32_t arc_code_length, uint32_t * start_address) -{ - int count; - printk ("try to download pages,size=%d\n", arc_code_length); - meiControlModeSwitch (MEI_MASTER_MODE); - if (arc_halt_flag == 0) { - meiHaltArc (); - } - meiLongwordWrite ( MEI_XFR_ADDR, 0); - for (count = 0; count < arc_code_length; count++) { - meiLongwordWrite ( MEI_DATA_XFR, - *(start_address + count)); - } - meiControlModeSwitch (JTAG_MASTER_MODE); -} -static int -load_jump_table (unsigned long addr) -{ - int i; - uint32_t addr_le, addr_be; - uint32_t jump_table[32]; - for (i = 0; i < 16; i++) { - addr_le = i * 8 + addr; - addr_be = ((addr_le >> 16) & 0xffff); - addr_be |= ((addr_le & 0xffff) << 16); - jump_table[i * 2 + 0] = 0x0f802020; - jump_table[i * 2 + 1] = addr_be; - //printk("jt %X %08X %08X\n",i,jump_table[i*2+0],jump_table[i*2+1]); - } - arc_code_page_download (32, &jump_table[0]); - return 0; -} - -void -dfe_loopback_irq_handler (void) -{ - uint32_t rd_mbox[10]; - - memset (&rd_mbox[0], 0, 10 * 4); - ReadMbox (&rd_mbox[0], 6); - if (rd_mbox[0] == 0x0) { - printk ("Get ARC_ACK\n"); - got_int = 1; - } - else if (rd_mbox[0] == 0x5) { - printk ("Get ARC_BUSY\n"); - got_int = 2; - } - else if (rd_mbox[0] == 0x3) { - printk ("Get ARC_EDONE\n"); - if (rd_mbox[1] == 0x0) { - got_int = 3; - printk ("Get E_MEMTEST\n"); - if (rd_mbox[2] != 0x1) { - got_int = 4; - printk ("Get Result %X\n", - rd_mbox[2]); - } - } - } - meiLongwordWrite ( ARC_TO_MEI_INT, ARC_TO_MEI_DBG_DONE); - MEI_MASK_AND_ACK_IRQ (IFXMIPS_MEI_INT); - disable_irq (IFXMIPS_MEI_INT); - //got_int = 1; - return; -} - -static void -wait_mem_test_result (void) -{ - uint32_t mbox[5]; - mbox[0] = 0; - printk ("Waiting Starting\n"); - while (mbox[0] == 0) { - ReadMbox (&mbox[0], 5); - } - printk ("Try to get mem test result.\n"); - ReadMbox (&mbox[0], 5); - if (mbox[0] == 0xA) { - printk ("Success.\n"); - } - else if (mbox[0] == 0xA) { - printk - ("Fail,address %X,except data %X,receive data %X\n", - mbox[1], mbox[2], mbox[3]); - } - else { - printk ("Fail\n"); - } -} - -static int -arc_ping_testing (void) -{ -#define MEI_PING 0x00000001 - uint32_t wr_mbox[10], rd_mbox[10]; - int i; - for (i = 0; i < 10; i++) { - wr_mbox[i] = 0; - rd_mbox[i] = 0; - } - - printk ("send ping msg\n"); - wr_mbox[0] = MEI_PING; - WriteMbox (&wr_mbox[0], 10); - - while (got_int == 0) { - MEI_WAIT (100); - } - - printk ("send start event\n"); - got_int = 0; - - wr_mbox[0] = 0x4; - wr_mbox[1] = 0; - wr_mbox[2] = 0; - wr_mbox[3] = (uint32_t) 0xf5acc307e; - wr_mbox[4] = 5; - wr_mbox[5] = 2; - wr_mbox[6] = 0x1c000; - wr_mbox[7] = 64; - wr_mbox[8] = 0; - wr_mbox[9] = 0; - WriteMbox (&wr_mbox[0], 10); - enable_irq (IFXMIPS_MEI_INT); - //printk("meiMailboxWrite ret=%d\n",i); - meiLongwordWrite ( MEI_TO_ARC_INT, MEI_TO_ARC_MSGAV); - printk ("sleeping\n"); - while (1) { - if (got_int > 0) { - - if (got_int > 3) - printk ("got_int >>>> 3\n"); - else - printk ("got int = %d\n", got_int); - got_int = 0; - //schedule(); - enable_irq (IFXMIPS_MEI_INT); - } - //mbox_read(&rd_mbox[0],6); - MEI_WAIT (100); - } -} - -static MEI_ERROR -DFE_Loopback_Test (void) -{ - int i = 0; - u32 arc_debug_data = 0, temp; - - meiResetARC (); - // start the clock - arc_debug_data = ACL_CLK_MODE_ENABLE; - meiDebugWrite (CRI_CCR0, &arc_debug_data, 1); - -#if defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK) - // WriteARCreg(AUX_XMEM_LTEST,0); - meiControlModeSwitch (MEI_MASTER_MODE); -#define AUX_XMEM_LTEST 0x128 - _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, AUX_XMEM_LTEST, 0); - meiControlModeSwitch (JTAG_MASTER_MODE); - - // WriteARCreg(AUX_XDMA_GAP,0); - meiControlModeSwitch (MEI_MASTER_MODE); -#define AUX_XDMA_GAP 0x114 - _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, AUX_XDMA_GAP, 0); - meiControlModeSwitch (JTAG_MASTER_MODE); - - meiControlModeSwitch (MEI_MASTER_MODE); - temp = 0; - _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, - (u32) MEI_XDATA_BASE_SH, temp); - meiControlModeSwitch (JTAG_MASTER_MODE); - - i = alloc_processor_memory (SDRAM_SEGMENT_SIZE * 16, adsl_mem_info); - if (i >= 0) { - int idx; - - for (idx = 0; idx < i; idx++) { - adsl_mem_info[idx].type = FREE_RELOAD; - IFXMIPS_WRITE_REGISTER_L ((((uint32_t) - adsl_mem_info[idx]. - address) & 0x0fffffff), - MEI_XMEM_BAR_BASE + idx * 4); - printk ("bar%d(%X)=%X\n", idx, - MEI_XMEM_BAR_BASE + idx * 4, - (((uint32_t) adsl_mem_info[idx]. - address) & 0x0fffffff)); - memset ((u8 *) adsl_mem_info[idx].address, 0, - SDRAM_SEGMENT_SIZE); - } - - meiLongwordWrite ( MEI_XDATA_BASE_SH, ((unsigned long) - adsl_mem_info - [XDATA_REGISTER]. - address) & - 0x0FFFFFFF); - - } - else { - printk ("cannot load image: no memory\n\n"); - return MEI_FAILURE; - } - //WriteARCreg(AUX_IC_CTRL,2); - meiControlModeSwitch (MEI_MASTER_MODE); -#define AUX_IC_CTRL 0x11 - _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, AUX_IC_CTRL, 2); - meiControlModeSwitch (JTAG_MASTER_MODE); - - meiHaltArc (); - -#ifdef DFE_PING_TEST - - printk ("ping test image size=%d\n", sizeof (code_array)); - memcpy ((u8 *) (adsl_mem_info[0].address + 0x1004), &code_array[0], - sizeof (code_array)); - load_jump_table (0x80000 + 0x1004); - -#endif //DFE_PING_TEST - - printk ("ARC ping test code download complete\n"); -#endif //defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK) -#ifdef DFE_MEM_TEST - meiLongwordWrite (ARC_TO_MEI_INT_MASK, MSGAV_EN); - - arc_code_page_download (1537, &mem_test_code_array[0]); - printk ("ARC mem test code download complete\n"); -#endif //DFE_MEM_TEST -#ifdef DFE_ATM_LOOPBACK - arc_debug_data = 0xf; - arc_code_page_download (1077, &code_array[0]); - // Start Iridia IT_AMODE (in dmp access) why is it required? - meiDebugWrite (0x32010, &arc_debug_data, 1); -#endif //DFE_ATM_LOOPBACK - meiMailboxInterruptsEnable (); - meiRunArc (); - -#ifdef DFE_PING_TEST - arc_ping_testing (); -#endif //DFE_PING_TEST -#ifdef DFE_MEM_TEST - wait_mem_test_result (); -#endif //DFE_MEM_TEST - - free_image_buffer (FREE_ALL); - return MEI_SUCCESS; -} - -#endif //DFE_LOOPBACK -//end of TODO, for loopback test - -#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT) - -/* - * Led Thread Main function - */ -static int -led_poll (void *unused) -{ - struct task_struct *tsk = current; - - daemonize("mei_led_poll"); - strcpy (tsk->comm, "atm_led"); - sigfillset (&tsk->blocked); - - stop_led_module = 0; //begin polling ... - - while (!stop_led_module) { - if (led_status_on || led_need_to_flash) { - adsl_led_flash_task (); - } - if (led_status_on) //sleep 200 ms to check if need to turn led off - { - interruptible_sleep_on_timeout - (&wait_queue_led_polling, 25); - } - else { - interruptible_sleep_on (&wait_queue_led_polling); - } - } - return 0; -} - -/* - * API for atm driver to notify led thread a data coming/sending - */ -#if defined (CONFIG_ATM_IFXMIPS) -static int -adsl_led_flash (void) -{ - if (!modem_ready) - return 0; - - if (led_status_on == 0 && led_need_to_flash == 0) - { - wake_up_interruptible (&wait_queue_led_polling); //wake up and clean led module - } - led_need_to_flash = 1; //asking to flash led - - return 0; -} -#endif -/* - * Main task for led controlling. - */ -static int -adsl_led_flash_task (void) -{ -#ifdef DATA_LED_ADSL_FW_HANDLE - u16 one = 1; - u16 zero = 0; - u16 data = 0x0600; - u16 CMVMSG[MSG_LENGTH]; -#endif - -// printk("Task Running...\n"); //joelin test - - if (!showtime) { - led_need_to_flash = 0; - led_status_on = 0; - return 0; - } - - if (led_status_on == 0 && led_need_to_flash == 1) { - -#ifdef DATA_LED_ADSL_FW_HANDLE - data = 0x0901; //flash - send_cmv (H2D_CMV_WRITE, INFO, 91, 5, 1, &data, CMVMSG); //use GPIO9 for TR68 data led .flash. -#else - ifxmips_led_blink_set(0x0); // data - ifxmips_led_blink_set(0x1); // link -#endif - led_status_on = 1; - - } - else if (led_status_on == 1 && led_need_to_flash == 0) { -#ifdef DATA_LED_ADSL_FW_HANDLE -#ifdef DATA_LED_ON_MODE - data = 0x0903; //use GPIO9 for TR68 data led .turn on. -#else - data = 0x0900; //off -#endif - printk ("off %04X\n", data); - send_cmv (H2D_CMV_WRITE, INFO, 91, 5, 1, &data, CMVMSG); //use GPIO9 for TR68 data led .off. -#else -#endif - led_status_on = 0; - } - led_need_to_flash = 0; - return 0; -} - -/* - * Led initialization function - * This function create a thread to polling atm traffic and do led blanking - */ -static int -ifxmips_mei_led_init (void) -{ - init_waitqueue_head (&wait_queue_led_polling); // adsl led for led function - kernel_thread (led_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGHAND | CLONE_THREAD); - return 0; -} - -/* - * Led destory function - */ -static int -ifxmips_mei_led_cleanup (void) -{ - stop_led_module = 1; //wake up and clean led module - wake_up_interruptible (&wait_queue_led_polling); //wake up and clean led module - return 0; -} -#endif //#ifdef CONFIG_IFXMIPS_MEI_LED - -//////////////////////////////////////////////////////////////////////////// -int __init -ifxmips_mei_init_module (void) -{ - struct proc_dir_entry *entry; - int i; - u32 temp; -#ifdef CONFIG_DEVFS_FS - char buf[10]; -#endif - reg_entry_t regs_temp[PROC_ITEMS] = // Items being debugged - { - /* { flag, name, description } */ - {&arcmsgav, "arcmsgav", "arc to mei message ", 0}, - {&cmv_reply, "cmv_reply", "cmv needs reply", 0}, - {&cmv_waiting, "cmv_waiting", - "waiting for cmv reply from arc", 0}, - {&indicator_count, "indicator_count", - "ARC to MEI indicator count", 0}, - {&cmv_count, "cmv_count", "MEI to ARC CMVs", 0}, - {&reply_count, "reply_count", "ARC to MEI Reply", 0}, - {(int *) Recent_indicator, "Recent_indicator", - "most recent indicator", 0}, - {(int *) 8, "version", "version of firmware", 0}, - }; - do_gettimeofday (&time_disconnect); - - printk ("Danube MEI version:%s\n", IFXMIPS_MEI_VERSION); - - memcpy ((char *) regs, (char *) regs_temp, sizeof (regs_temp)); - MEI_MUTEX_INIT (mei_sema, 1); // semaphore initialization, mutex - MEI_INIT_WAKELIST ("arcq", wait_queue_arcmsgav); // for ARCMSGAV - MEI_INIT_WAKELIST ("arcldq", wait_queue_loop_diagnostic); // for loop diagnostic function -#ifdef IFX_ADSL_L3_MODE_SUPPORT - MEI_INIT_WAKELIST ("arcl3q", wait_queue_l3); // for l3 power mode -#endif //IFX_ADSL_L3_MODE_SUPPORT - - - memset (&adsl_mem_info[0], 0, sizeof (smmu_mem_info_t) * MAX_BAR_REGISTERS); -#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT) - printk("not enabling mei leds due to bug that makes the board hang\n"); -// ifxmips_mei_led_init (); -#endif - -#ifdef CONFIG_IFXMIPS_MEI_MIB - ifxmips_mei_mib_init (); -#endif - -#ifdef IFXMIPS_CLEAR_EOC - MEI_INIT_WAKELIST ("arceoc", wait_queue_hdlc_poll); - ifxmips_mei_ceoc_init (); -#endif - // power up mei - temp = ifxmips_r32(IFXMIPS_PMU_PWDCR); - temp &= 0xffff7dbe; - ifxmips_w32(temp, IFXMIPS_PMU_PWDCR); - -#if defined (CONFIG_ATM_IFXMIPS) - IFX_ATM_LED_Callback_Register (adsl_led_flash); -#endif - if (register_chrdev (major, IFXMIPS_MEI_DEVNAME, &mei_operations) != 0) { - printk("\n\n unable to register major for ifxmips_mei!!!"); - return -ENODEV; - } else { - printk("registered ifxmips_mei on #%d\n", major); - } - - disable_irq(IFXMIPS_MEI_INT); - - if (request_irq(IFXMIPS_MEI_INT, mei_interrupt_arcmsgav, 0, "ifxmips_mei_arcmsgav", NULL) != 0) { - printk("\n\n unable to register irq(%d) for ifxmips_mei!!!", - IFXMIPS_MEI_INT); - return -1; - } - -// enable_irq(IFXMIPS_MEI_INT); - // procfs - meidir = proc_mkdir(MEI_DIRNAME, &proc_root); - if (meidir == NULL) - { - printk(": can't create /proc/" MEI_DIRNAME "\n\n"); - return -ENOMEM; - } - - for (i = 0; i < NUM_OF_REG_ENTRY; i++) { - entry = create_proc_entry (regs[i].name, - S_IWUSR | S_IRUSR | S_IRGRP | S_IROTH, meidir); - if (entry) - { - regs[i].low_ino = entry->low_ino; - entry->proc_fops = &proc_operations; - } else { - printk (": can't create /proc/" MEI_DIRNAME "/%s\n\n", regs[i].name); - return -ENOMEM; - } - } - - ///////////////////////////////// register net device //////////////////////////// -#ifdef DFE_LOOPBACK - DFE_Loopback_Test (); -#endif //DFE_LOOPBACK - return 0; -} - -void __exit -ifxmips_mei_cleanup_module (void) -{ - int i; - -#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT) - ifxmips_mei_led_cleanup (); -#endif - showtime = 0; //joelin,clear task - -#ifdef CONFIG_PROC_FS - for (i = 0; i < NUM_OF_REG_ENTRY; i++) - remove_proc_entry (regs[i].name, meidir); - - remove_proc_entry (MEI_DIRNAME, &proc_root); -#endif //CONFIG_PROC_FS - -#if defined (CONFIG_ATM_IFXMIPS) - IFX_ATM_LED_Callback_Unregister (adsl_led_flash); -#endif - disable_irq (IFXMIPS_MEI_INT); - free_irq(IFXMIPS_MEI_INT, NULL); - -#ifdef CONFIG_DEVFS_FS - devfs_unregister (mei_devfs_handle); -#else - unregister_chrdev (major, "ifxmips_mei"); -#endif -#ifdef CONFIG_IFXMIPS_MEI_MIB - ifxmips_mei_mib_cleanup (); -#endif - - free_image_buffer (FREE_ALL); - return; -} - -EXPORT_SYMBOL (meiDebugRead); -EXPORT_SYMBOL (meiDebugWrite); -EXPORT_SYMBOL (ifx_me_hdlc_send); -EXPORT_SYMBOL (ifx_mei_hdlc_read); -MODULE_LICENSE ("GPL"); - -module_init (ifxmips_mei_init_module); -module_exit (ifxmips_mei_cleanup_module); diff --git a/target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c b/target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c deleted file mode 100644 index 35b32e8529..0000000000 --- a/target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c +++ /dev/null @@ -1,1417 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2006 infineon - * Copyright (C) 2007 John Crispin - * - */ - -// ### TO DO: general issues: -// - power management -// - interrupt handling (direct/indirect) -// - pin/mux-handling (just overall concept due to project dependency) -// - multiple instances capability -// - slave functionality - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -/* allow the user to set the major device number */ -static int maj = 0; - -/* - * This is the per-channel data structure containing pointers, flags - * and variables for the port. This driver supports a maximum of PORT_CNT. - * isp is allocated in ifx_ssc_init() based on the chip version. - */ -static struct ifx_ssc_port *isp; - -/* other forward declarations */ -static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info); -static void tx_int (struct ifx_ssc_port *); - -extern unsigned int ifxmips_get_fpi_hz (void); -extern void ifxmips_mask_and_ack_irq (unsigned int irq_nr); - -static inline unsigned int -ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info) -{ - unsigned int rmc; - - rmc = (ifxmips_r32(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET; - if (rmc == 0) - { - printk ("ifx_ssc_get_kernel_clk rmc==0 \n"); - return 0; - } - return ifxmips_get_fpi_hz () / rmc; -} - -inline static void -rx_int (struct ifx_ssc_port *info) -{ - int fifo_fill_lev, bytes_in_buf, i; - unsigned long tmp_val; - unsigned long *tmp_ptr; - unsigned int rx_valid_cnt; - /* number of words waiting in the RX FIFO */ - fifo_fill_lev = (ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET; - bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr; - // transfer with 32 bits per entry - while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) { - tmp_ptr = (unsigned long *) info->rxbuf_ptr; - *tmp_ptr = ifxmips_r32(IFXMIPS_SSC_RB); - info->rxbuf_ptr += 4; - info->stats.rxBytes += 4; - fifo_fill_lev--; - bytes_in_buf -= 4; - } - - // now do the rest as mentioned in STATE.RXBV - while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) { - rx_valid_cnt = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET; - if (rx_valid_cnt == 0) - break; - - if (rx_valid_cnt > bytes_in_buf) - rx_valid_cnt = bytes_in_buf; - - tmp_val = ifxmips_r32(IFXMIPS_SSC_RB); - - for (i = 0; i < rx_valid_cnt; i++) - { - *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff; - bytes_in_buf--; - info->rxbuf_ptr++; - } - info->stats.rxBytes += rx_valid_cnt; - } - - // check if transfer is complete - if (info->rxbuf_ptr >= info->rxbuf_end) - { - disable_irq(IFXMIPS_SSC_RIR); - wake_up_interruptible (&info->rwait); - } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (ifxmips_r32(IFXMIPS_SSC_RXCNT) == 0)) - { - if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE) - ifxmips_w32((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ); - else - ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ); - } -} - -inline static void -tx_int (struct ifx_ssc_port *info) -{ - - int fifo_space, fill, i; - fifo_space = ((ifxmips_r32(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) - - ((ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET); - - if (fifo_space == 0) - return; - - fill = info->txbuf_end - info->txbuf_ptr; - - if (fill > fifo_space * 4) - fill = fifo_space * 4; - - for (i = 0; i < fill / 4; i++) - { - // at first 32 bit access - ifxmips_w32(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB); - info->txbuf_ptr += 4; - } - - fifo_space -= fill / 4; - info->stats.txBytes += fill & ~0x3; - fill &= 0x3; - if ((fifo_space > 0) & (fill > 1)) - { - // trailing 16 bit access - WRITE_PERIPHERAL_REGISTER_16 (*(UINT16 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB); - info->txbuf_ptr += 2; - info->stats.txBytes += 2; - fifo_space--; - fill -= 2; - } - - if ((fifo_space > 0) & (fill > 0)) - { - // trailing 8 bit access - WRITE_PERIPHERAL_REGISTER_8 (*(UINT8 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB); - info->txbuf_ptr++; - info->stats.txBytes++; - } - - // check if transmission complete - if (info->txbuf_ptr >= info->txbuf_end) - { - disable_irq(IFXMIPS_SSC_TIR); - kfree (info->txbuf); - info->txbuf = NULL; - } - -} - -irqreturn_t -ifx_ssc_rx_int (int irq, void *dev_id) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id; - rx_int (info); - - return IRQ_HANDLED; -} - -irqreturn_t -ifx_ssc_tx_int (int irq, void *dev_id) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id; - tx_int (info); - - return IRQ_HANDLED; -} - -irqreturn_t -ifx_ssc_err_int (int irq, void *dev_id) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id; - unsigned int state; - unsigned int write_back = 0; - unsigned long flags; - - local_irq_save (flags); - state = ifxmips_r32(IFXMIPS_SSC_STATE); - - if ((state & IFX_SSC_STATE_RX_UFL) != 0) { - info->stats.rxUnErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR; - } - - if ((state & IFX_SSC_STATE_RX_OFL) != 0) { - info->stats.rxOvErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR; - } - - if ((state & IFX_SSC_STATE_TX_OFL) != 0) { - info->stats.txOvErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR; - } - - if ((state & IFX_SSC_STATE_TX_UFL) != 0) { - info->stats.txUnErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR; - } - - if ((state & IFX_SSC_STATE_MODE_ERR) != 0) { - info->stats.modeErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR; - } - - if (write_back) - ifxmips_w32(write_back, IFXMIPS_SSC_WHBSTATE); - - local_irq_restore (flags); - - return IRQ_HANDLED; -} - -static void -ifx_ssc_abort (struct ifx_ssc_port *info) -{ - unsigned long flags; - bool enabled; - - local_irq_save (flags); - - disable_irq(IFXMIPS_SSC_RIR); - disable_irq(IFXMIPS_SSC_TIR); - disable_irq(IFXMIPS_SSC_EIR); - - local_irq_restore (flags); - - // disable SSC (also aborts a receive request!) - // ### TO DO: Perhaps it's better to abort after the receiption of a - // complete word. The disable cuts the transmission immediatly and - // releases the chip selects. This could result in unpredictable - // behavior of connected external devices! - enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0; - ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE); - - // flush fifos - ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON); - ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON); - - // free txbuf - if (info->txbuf != NULL) - { - kfree (info->txbuf); - info->txbuf = NULL; - } - - // wakeup read process - if (info->rxbuf != NULL) - wake_up_interruptible (&info->rwait); - - // clear pending int's - ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR); - ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR); - ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR); - - // clear error flags - ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE); - - if (enabled) - ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE); - -} - -/* - * This routine is called whenever a port is opened. It enforces - * exclusive opening of a port and enables interrupts, etc. - */ -int -ifx_ssc_open (struct inode *inode, struct file *filp) -{ - struct ifx_ssc_port *info; - int line; - int from_kernel = 0; - - if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) { - from_kernel = 1; - line = (int) inode; - } else { - line = MINOR (filp->f_dentry->d_inode->i_rdev); - } - - /* don't open more minor devices than we can support */ - if (line < 0 || line >= PORT_CNT) - return -ENXIO; - - info = &isp[line]; - - /* exclusive open */ - if (info->port_is_open != 0) - return -EBUSY; - info->port_is_open++; - - disable_irq(IFXMIPS_SSC_RIR); - disable_irq(IFXMIPS_SSC_TIR); - disable_irq(IFXMIPS_SSC_EIR); - - /* Flush and enable TX/RX FIFO */ - ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON); - ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON); - - /* logically flush the software FIFOs */ - info->rxbuf_ptr = 0; - info->txbuf_ptr = 0; - - /* clear all error bits */ - ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE); - - // clear pending interrupts - ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR); - ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR); - ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR); - - ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE); - - return 0; -} -EXPORT_SYMBOL(ifx_ssc_open); - -int -ifx_ssc_close (struct inode *inode, struct file *filp) -{ - struct ifx_ssc_port *info; - int idx; - - if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) - idx = (int) inode; - else - idx = MINOR (filp->f_dentry->d_inode->i_rdev); - - if (idx < 0 || idx >= PORT_CNT) - return -ENXIO; - - info = &isp[idx]; - if (!info) - return -ENXIO; - - ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE); - - ifx_ssc_abort(info); - - info->port_is_open--; - - return 0; -} -EXPORT_SYMBOL(ifx_ssc_close); - -static ssize_t -ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel) -{ - ssize_t ret_val; - unsigned long flags; - - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - return -EFAULT; - local_irq_save (flags); - info->rxbuf_ptr = info->rxbuf; - info->rxbuf_end = info->rxbuf + len; - local_irq_restore (flags); - /* Vinetic driver always works in IFX_SSC_MODE_RXTX */ - /* TXRX in poll mode */ - while (info->rxbuf_ptr < info->rxbuf_end) - { - if (info->txbuf_ptr < info->txbuf_end) - tx_int (info); - - rx_int (info); - }; - - ret_val = info->rxbuf_ptr - info->rxbuf; - - return ret_val; -} - -static ssize_t -ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel) -{ - ssize_t ret_val; - unsigned long flags; - DECLARE_WAITQUEUE (wait, current); - - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - return -EFAULT; - - local_irq_save (flags); - info->rxbuf_ptr = info->rxbuf; - info->rxbuf_end = info->rxbuf + len; - - if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) - { - if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf)) - { - local_irq_restore (flags); - printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__); - return -EFAULT; - } - - local_irq_restore(flags); - tx_int (info); - - if (info->txbuf_ptr < info->txbuf_end) - enable_irq(IFXMIPS_SSC_TIR); - - enable_irq(IFXMIPS_SSC_RIR); - } else { - local_irq_restore(flags); - if (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK) - return -EBUSY; - enable_irq(IFXMIPS_SSC_RIR); - if (len < IFX_SSC_RXREQ_BLOCK_SIZE) - ifxmips_w32(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ); - else - ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ); - } - - __add_wait_queue (&info->rwait, &wait); - set_current_state (TASK_INTERRUPTIBLE); - - do { - local_irq_save (flags); - if (info->rxbuf_ptr >= info->rxbuf_end) - break; - - local_irq_restore (flags); - - if (signal_pending (current)) - { - ret_val = -ERESTARTSYS; - goto out; - } - schedule(); - } while (1); - - ret_val = info->rxbuf_ptr - info->rxbuf; - local_irq_restore (flags); - -out: - current->state = TASK_RUNNING; - __remove_wait_queue (&info->rwait, &wait); - - return (ret_val); -} - -static ssize_t -ifx_ssc_write_helper (struct ifx_ssc_port *info, const char *buf, - size_t len, int from_kernel) -{ - if (info->opts.modeRxTx == IFX_SSC_MODE_RX) - return -EFAULT; - - info->txbuf_ptr = info->txbuf; - info->txbuf_end = len + info->txbuf; - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - { - tx_int (info); - if (info->txbuf_ptr < info->txbuf_end) - { - enable_irq(IFXMIPS_SSC_TIR); - } - } - - return len; -} - -ssize_t -ifx_ssc_kread (int port, char *kbuf, size_t len) -{ - struct ifx_ssc_port *info; - ssize_t ret_val; - - if (port < 0 || port >= PORT_CNT) - return -ENXIO; - - if (len == 0) - return 0; - - info = &isp[port]; - - if (info->rxbuf != NULL) - { - printk ("SSC device busy\n"); - return -EBUSY; - } - - info->rxbuf = kbuf; - if (info->rxbuf == NULL) - { - printk ("SSC device error\n"); - return -EINVAL; - } - - ret_val = ifx_ssc_read_helper_poll (info, kbuf, len, 1); - info->rxbuf = NULL; - - disable_irq(IFXMIPS_SSC_RIR); - - return ret_val; -} -EXPORT_SYMBOL(ifx_ssc_kread); - -ssize_t -ifx_ssc_kwrite (int port, const char *kbuf, size_t len) -{ - struct ifx_ssc_port *info; - ssize_t ret_val; - - if (port < 0 || port >= PORT_CNT) - return -ENXIO; - - if (len == 0) - return 0; - - info = &isp[port]; - - // check if transmission in progress - if (info->txbuf != NULL) - return -EBUSY; - - info->txbuf = (char *) kbuf; - - ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 1); - - if (ret_val < 0) - info->txbuf = NULL; - - return ret_val; -} -EXPORT_SYMBOL(ifx_ssc_kwrite); - -static ssize_t -ifx_ssc_read (struct file *filp, char *ubuf, size_t len, loff_t * off) -{ - ssize_t ret_val; - int idx; - struct ifx_ssc_port *info; - - idx = MINOR (filp->f_dentry->d_inode->i_rdev); - info = &isp[idx]; - - if (info->rxbuf != NULL) - return -EBUSY; - - info->rxbuf = kmalloc (len + 3, GFP_KERNEL); - if (info->rxbuf == NULL) - return -ENOMEM; - - ret_val = ifx_ssc_read_helper (info, info->rxbuf, len, 0); - if (copy_to_user ((void *) ubuf, info->rxbuf, ret_val) != 0) - ret_val = -EFAULT; - - disable_irq(IFXMIPS_SSC_RIR); - - kfree (info->rxbuf); - info->rxbuf = NULL; - - return (ret_val); -} - -static ssize_t -ifx_ssc_write (struct file *filp, const char *ubuf, size_t len, loff_t * off) -{ - int idx; - struct ifx_ssc_port *info; - int ret_val; - - if (len == 0) - return (0); - - idx = MINOR (filp->f_dentry->d_inode->i_rdev); - info = &isp[idx]; - - if (info->txbuf != NULL) - return -EBUSY; - - info->txbuf = kmalloc (len + 3, GFP_KERNEL); - if (info->txbuf == NULL) - return -ENOMEM; - - ret_val = copy_from_user (info->txbuf, ubuf, len); - if (ret_val == 0) - ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 0); - else - ret_val = -EFAULT; - - if (ret_val < 0) - { - kfree (info->txbuf); - info->txbuf = NULL; - } - - return (ret_val); -} - -static struct ifx_ssc_frm_status * -ifx_ssc_frm_status_get (struct ifx_ssc_port *info) -{ - unsigned long tmp; - - tmp = ifxmips_r32(IFXMIPS_SSC_SFSTAT); - info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0; - info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0; - info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET; - info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET; - tmp = ifxmips_r32(IFXMIPS_SSC_SFCON); - info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0; - info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0; - - return &info->frm_status; -} - - -static struct ifx_ssc_frm_opts * -ifx_ssc_frm_control_get (struct ifx_ssc_port *info) -{ - unsigned long tmp; - - tmp = ifxmips_r32(IFXMIPS_SSC_SFCON); - info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0; - info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET; - info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET; - info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET; - info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET; - info->frm_opts.StopAfterPause = (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0; - - return &info->frm_opts; -} - -static int -ifx_ssc_frm_control_set (struct ifx_ssc_port *info) -{ - unsigned long tmp; - - if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX) - || (info->frm_opts.DataLength < 1) - || (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX) - || (info->frm_opts.PauseLength < 1) - || (info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET)) - || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET))) - return -EINVAL; - - // read interrupt bits (they're not changed here) - tmp = ifxmips_r32(IFXMIPS_SSC_SFCON) & - (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE); - - // set all values with respect to it's bit position (for data and pause - // length set N-1) - tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET; - tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET; - tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET; - tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET; - tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE; - tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE; - - ifxmips_w32(tmp, IFXMIPS_SSC_SFCON); - - return 0; -} - -static int -ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val) -{ - unsigned long tmp; - - if (!(info) || (val & ~(IFX_SSC_MODE_MASK))) - return -EINVAL; - - if ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY) - || (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)) - return -EBUSY; - - tmp = (ifxmips_r32(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val); - ifxmips_w32(tmp, IFXMIPS_SSC_SFCON); - info->opts.modeRxTx = val; - - return 0; -} - -static int -ifx_ssc_sethwopts (struct ifx_ssc_port *info) -{ - unsigned long flags, bits; - struct ifx_ssc_hwopts *opts = &info->opts; - - if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH) - || (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH)) - return -EINVAL; - - bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET; - bits |= IFX_SSC_CON_ENABLE_BYTE_VALID; - - if (opts->rxOvErrDetect) - bits |= IFX_SSC_CON_RX_OFL_CHECK; - if (opts->rxUndErrDetect) - bits |= IFX_SSC_CON_RX_UFL_CHECK; - if (opts->txOvErrDetect) - bits |= IFX_SSC_CON_TX_OFL_CHECK; - if (opts->txUndErrDetect) - bits |= IFX_SSC_CON_TX_UFL_CHECK; - if (opts->loopBack) - bits |= IFX_SSC_CON_LOOPBACK_MODE; - if (opts->echoMode) - bits |= IFX_SSC_CON_ECHO_MODE_ON; - if (opts->headingControl) - bits |= IFX_SSC_CON_MSB_FIRST; - if (opts->clockPhase) - bits |= IFX_SSC_CON_LATCH_THEN_SHIFT; - if (opts->clockPolarity) - bits |= IFX_SSC_CON_CLOCK_FALL; - - switch (opts->modeRxTx) - { - case IFX_SSC_MODE_TX: - bits |= IFX_SSC_CON_RX_OFF; - break; - case IFX_SSC_MODE_RX: - bits |= IFX_SSC_CON_TX_OFF; - break; - } - - local_irq_save (flags); - - ifxmips_w32(bits, IFXMIPS_SSC_CON); - ifxmips_w32((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) | - (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON); - - ifxmips_w32(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT); - - //master mode - if (opts->masterSelect) - ifxmips_w32(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE); - else - ifxmips_w32(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE); - - // init serial framing - ifxmips_w32(0, IFXMIPS_SSC_SFCON); - /* set up the port pins */ - //check for general requirements to switch (external) pad/pin characteristics - /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */ - /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */ - /* Set p0.15 to alternative 01, others to 00 (In/OUT) */ - *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000); - *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000))); - *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000))); - *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000; - - /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */ - *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1); - *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47)); - *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47); - *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046; - - /*CS3 */ - /*TODO: CS4 CS5 CS6 */ - *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000); - - local_irq_restore (flags); - - return 0; -} - -static int -ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud) -{ - unsigned int ifx_ssc_clock; - unsigned int br; - unsigned long flags; - bool enabled; - int retval = 0; - - ifx_ssc_clock = ifx_ssc_get_kernel_clk(info); - if (ifx_ssc_clock == 0) - { - retval = -EINVAL; - goto out; - } - - local_irq_save (flags); - - enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED); - ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE); - - br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1; - wmb(); - - if (br > 0xffff || ((br == 0) && - ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) { - local_irq_restore (flags); - printk ("%s: invalid baudrate %u\n", __func__, baud); - return -EINVAL; - } - - ifxmips_w32(br, IFXMIPS_SSC_BR); - - if (enabled) - ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE); - - local_irq_restore(flags); - -out: - return retval; -} - -static int -ifx_ssc_hwinit (struct ifx_ssc_port *info) -{ - unsigned long flags; - bool enabled; - - enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED); - ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE); - - if (ifx_ssc_sethwopts (info) < 0) - { - printk ("%s: setting the hardware options failed\n", __func__); - return -EINVAL; - } - - if (ifx_ssc_set_baud (info, info->baud) < 0) - { - printk ("%s: setting the baud rate failed\n", __func__); - return -EINVAL; - } - - local_irq_save (flags); - - /* TX FIFO */ - ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON); - /* RX FIFO */ - ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON); - - local_irq_restore (flags); - - if (enabled) - ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE); - - return 0; -} - -int -ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data) -{ - struct ifx_ssc_port *info; - int line, ret_val = 0; - unsigned long flags; - unsigned long tmp; - int from_kernel = 0; - - if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) - { - from_kernel = 1; - line = (int) inode; - } else { - line = MINOR (filp->f_dentry->d_inode->i_rdev); - } - - if (line < 0 || line >= PORT_CNT) - return -ENXIO; - - info = &isp[line]; - - switch (cmd) - { - case IFX_SSC_STATS_READ: - /* data must be a pointer to a struct ifx_ssc_statistics */ - if (from_kernel) - memcpy ((void *) data, (void *) &info->stats, - sizeof (struct ifx_ssc_statistics)); - else if (copy_to_user ((void *) data, - (void *) &info->stats, - sizeof (struct ifx_ssc_statistics))) - ret_val = -EFAULT; - break; - case IFX_SSC_STATS_RESET: - /* just resets the statistics counters */ - memset ((void *) &info->stats, 0, - sizeof (struct ifx_ssc_statistics)); - break; - case IFX_SSC_BAUD_SET: - /* if the buffers are not empty then the port is */ - /* busy and we shouldn't change things on-the-fly! */ - if (!info->txbuf || !info->rxbuf || - (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) { - ret_val = -EBUSY; - break; - } - /* misuse flags */ - if (from_kernel) - flags = *((unsigned long *) data); - else if (copy_from_user ((void *) &flags, - (void *) data, sizeof (flags))) { - ret_val = -EFAULT; - break; - } - if (flags == 0) { - ret_val = -EINVAL; - break; - } - if (ifx_ssc_set_baud (info, flags) < 0) { - ret_val = -EINVAL; - break; - } - info->baud = flags; - break; - case IFX_SSC_BAUD_GET: - if (from_kernel) - *((unsigned int *) data) = info->baud; - else if (copy_to_user ((void *) data, - (void *) &info->baud, - sizeof (unsigned long))) - ret_val = -EFAULT; - break; - case IFX_SSC_RXTX_MODE_SET: - if (from_kernel) - tmp = *((unsigned long *) data); - else if (copy_from_user ((void *) &tmp, - (void *) data, sizeof (tmp))) { - ret_val = -EFAULT; - break; - } - ret_val = ifx_ssc_rxtx_mode_set (info, tmp); - break; - case IFX_SSC_RXTX_MODE_GET: - tmp = ifxmips_r32(IFXMIPS_SSC_CON) & - (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)); - if (from_kernel) - *((unsigned int *) data) = tmp; - else if (copy_to_user ((void *) data, - (void *) &tmp, sizeof (tmp))) - ret_val = -EFAULT; - break; - - case IFX_SSC_ABORT: - ifx_ssc_abort (info); - break; - - case IFX_SSC_GPO_OUT_SET: - if (from_kernel) - tmp = *((unsigned long *) data); - else if (copy_from_user ((void *) &tmp, - (void *) data, sizeof (tmp))) { - ret_val = -EFAULT; - break; - } - if (tmp > IFX_SSC_MAX_GPO_OUT) - ret_val = -EINVAL; - else - ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS), - IFXMIPS_SSC_WHBGPOSTAT); - break; - case IFX_SSC_GPO_OUT_CLR: - if (from_kernel) - tmp = *((unsigned long *) data); - else if (copy_from_user ((void *) &tmp, (void *) data, sizeof (tmp))) { - ret_val = -EFAULT; - break; - } - if (tmp > IFX_SSC_MAX_GPO_OUT) - ret_val = -EINVAL; - else { - ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS), - IFXMIPS_SSC_WHBGPOSTAT); - } - break; - case IFX_SSC_GPO_OUT_GET: - tmp = ifxmips_r32(IFXMIPS_SSC_GPOSTAT); - if (from_kernel) - *((unsigned int *) data) = tmp; - else if (copy_to_user ((void *) data, - (void *) &tmp, sizeof (tmp))) - ret_val = -EFAULT; - break; - case IFX_SSC_FRM_STATUS_GET: - ifx_ssc_frm_status_get (info); - if (from_kernel) - memcpy ((void *) data, (void *) &info->frm_status, - sizeof (struct ifx_ssc_frm_status)); - else if (copy_to_user ((void *) data, - (void *) &info->frm_status, - sizeof (struct ifx_ssc_frm_status))) - ret_val = -EFAULT; - break; - case IFX_SSC_FRM_CONTROL_GET: - ifx_ssc_frm_control_get (info); - if (from_kernel) - memcpy ((void *) data, (void *) &info->frm_opts, - sizeof (struct ifx_ssc_frm_opts)); - else if (copy_to_user ((void *) data, - (void *) &info->frm_opts, - sizeof (struct ifx_ssc_frm_opts))) - ret_val = -EFAULT; - break; - case IFX_SSC_FRM_CONTROL_SET: - if (from_kernel) - memcpy ((void *) &info->frm_opts, (void *) data, - sizeof (struct ifx_ssc_frm_opts)); - else if (copy_to_user ((void *) &info->frm_opts, - (void *) data, - sizeof (struct ifx_ssc_frm_opts))) { - ret_val = -EFAULT; - break; - } - ret_val = ifx_ssc_frm_control_set (info); - break; - case IFX_SSC_HWOPTS_SET: - /* data must be a pointer to a struct ifx_ssc_hwopts */ - /* if the buffers are not empty then the port is */ - /* busy and we shouldn't change things on-the-fly! */ - if (!info->txbuf || !info->rxbuf || - (ifxmips_r32(IFXMIPS_SSC_STATE) - & IFX_SSC_STATE_BUSY)) { - ret_val = -EBUSY; - break; - } - if (from_kernel) - memcpy ((void *) &info->opts, (void *) data, - sizeof (struct ifx_ssc_hwopts)); - else if (copy_from_user ((void *) &info->opts, - (void *) data, sizeof(struct ifx_ssc_hwopts))) { - ret_val = -EFAULT; - break; - } - if (ifx_ssc_hwinit (info) < 0) { - ret_val = -EIO; - } - break; - case IFX_SSC_HWOPTS_GET: - /* data must be a pointer to a struct ifx_ssc_hwopts */ - if (from_kernel) - memcpy ((void *) data, (void *) &info->opts, - sizeof (struct ifx_ssc_hwopts)); - else if (copy_to_user ((void *) data, - (void *) &info->opts, - sizeof (struct ifx_ssc_hwopts))) - ret_val = -EFAULT; - break; - default: - ret_val = -ENOIOCTLCMD; - } - - return ret_val; -} -EXPORT_SYMBOL(ifx_ssc_ioctl); - -static struct file_operations ifx_ssc_fops = { - .owner = THIS_MODULE, - .read = ifx_ssc_read, - .write = ifx_ssc_write, - .ioctl = ifx_ssc_ioctl, - .open = ifx_ssc_open, - .release = ifx_ssc_close, -}; - -int __init -ifx_ssc_init (void) -{ - struct ifx_ssc_port *info; - int i, nbytes; - unsigned long flags; - int ret_val; - - ret_val = -ENOMEM; - nbytes = PORT_CNT * sizeof(struct ifx_ssc_port); - isp = (struct ifx_ssc_port*)kmalloc(nbytes, GFP_KERNEL); - - if (isp == NULL) - { - printk("%s: no memory for isp\n", __func__); - return (ret_val); - } - memset(isp, 0, nbytes); - - ret_val = -ENXIO; - if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0) - { - printk ("Unable to register major %d for the Infineon SSC\n", maj); - if (maj == 0) - { - goto errout; - } else { - maj = 0; - if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0) - { - printk ("Unable to register major %d for the Infineon SSC\n", maj); - goto errout; - } - } - } - - if (maj == 0) - maj = i; - - /* set default values in ifx_ssc_port */ - for (i = 0; i < PORT_CNT; i++) { - info = &isp[i]; - info->port_nr = i; - /* default values for the HwOpts */ - info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT; - info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT; - info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT; - info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT; - info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT; - info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK; - info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE; - info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA; - info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY; - info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE; - info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL; - info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH; - info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX; - info->opts.gpoCs = IFX_SSC_DEF_GPO_CS; - info->opts.gpoInv = IFX_SSC_DEF_GPO_INV; - info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE; - info->baud = IFX_SSC_DEF_BAUDRATE; - info->rxbuf = NULL; - info->txbuf = NULL; - /* values specific to SSC1 */ - if (i == 0) { - info->mapbase = IFXMIPS_SSC_BASE_ADDR; - } - - ifxmips_w32(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC); - - init_waitqueue_head (&info->rwait); - - local_irq_save (flags); - - // init serial framing register - ifxmips_w32(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON); - - ret_val = request_irq(IFXMIPS_SSC_TIR, ifx_ssc_tx_int, IRQF_DISABLED, "ifx_ssc_tx", info); - if (ret_val) - { - printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_TIR); - local_irq_restore(flags); - goto errout; - } - - ret_val = request_irq(IFXMIPS_SSC_RIR, ifx_ssc_rx_int, IRQF_DISABLED, "ifx_ssc_rx", info); - if (ret_val) - { - printk ("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_RIR); - local_irq_restore (flags); - goto irqerr; - } - - ret_val = request_irq(IFXMIPS_SSC_EIR, ifx_ssc_err_int, IRQF_DISABLED, "ifx_ssc_err", info); - if (ret_val) - { - printk ("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_EIR); - local_irq_restore (flags); - goto irqerr; - } - ifxmips_w32(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN); - - //enable_irq(IFXMIPS_SSC_TIR); - //enable_irq(IFXMIPS_SSC_RIR); - //enable_irq(IFXMIPS_SSC_EIR); - - local_irq_restore (flags); - } - - for (i = 0; i < PORT_CNT; i++) { - info = &isp[i]; - if (ifx_ssc_hwinit (info) < 0) - { - printk ("%s: hardware init failed for port %d\n", __func__, i); - goto irqerr; - } - } - - - return 0; - -irqerr: - free_irq(IFXMIPS_SSC_TIR, &isp[0]); - free_irq(IFXMIPS_SSC_RIR, &isp[0]); - free_irq(IFXMIPS_SSC_EIR, &isp[0]); -errout: - kfree (isp); - return (ret_val); -} - -void -ifx_ssc_cleanup_module (void) -{ - int i; - - for (i = 0; i < PORT_CNT; i++) { - ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE); - free_irq(IFXMIPS_SSC_TIR, &isp[i]); - free_irq(IFXMIPS_SSC_RIR, &isp[i]); - free_irq(IFXMIPS_SSC_EIR, &isp[i]); - } - kfree (isp); -} - -module_init(ifx_ssc_init); -module_exit(ifx_ssc_cleanup_module); - - -inline int -ifx_ssc_cs_low (u32 pin) -{ - int ret = 0; - if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin))) - printk ("clear CS %d fails\n", pin); - wmb (); - - return ret; -} -EXPORT_SYMBOL(ifx_ssc_cs_low); - -inline int -ifx_ssc_cs_high (u32 pin) -{ - int ret = 0; - if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin))) - printk ("set CS %d fails\n", pin); - wmb (); - - return ret; -} -EXPORT_SYMBOL(ifx_ssc_cs_high); - -static int -ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len) -{ - int ret = 0; - - char *ssc_tx_buf = NULL; - char *ssc_rx_buf = NULL; - int eff_size = 0; - u8 mode = 0; - - if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) { - printk ("invalid parameters\n"); - ret = -EINVAL; - goto ssc_session_exit; - } - else if (tx_buf == NULL || tx_len == 0) { - if (rx_buf != NULL && rx_len != 0) { - mode = IFX_SSC_MODE_RX; - } - else { - printk ("invalid parameters\n"); - ret = -EINVAL; - goto ssc_session_exit; - } - } - else if (rx_buf == NULL || rx_len == 0) { - if (tx_buf != NULL && tx_len != 0) { - mode = IFX_SSC_MODE_TX; - } - else { - printk ("invalid parameters\n"); - ret = -EINVAL; - goto ssc_session_exit; - } - } - else { - mode = IFX_SSC_MODE_RXTX; - } - - if (mode == IFX_SSC_MODE_RXTX) { - eff_size = tx_len + rx_len; - } - else if (mode == IFX_SSC_MODE_RX) { - eff_size = rx_len; - } - else { - eff_size = tx_len; - } - - //4 bytes alignment, required by driver - /* change by TaiCheng */ - //if (in_irq()){ - if (1) { - ssc_tx_buf = - (char *) kmalloc (sizeof (char) * - ((eff_size + 3) & (~3)), - GFP_ATOMIC); - ssc_rx_buf = - (char *) kmalloc (sizeof (char) * - ((eff_size + 3) & (~3)), - GFP_ATOMIC); - } - else { - ssc_tx_buf = - (char *) kmalloc (sizeof (char) * - ((eff_size + 3) & (~3)), - GFP_KERNEL); - ssc_rx_buf = - (char *) kmalloc (sizeof (char) * - ((eff_size + 3) & (~3)), - GFP_KERNEL); - } - if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) { - printk ("no memory for size of %d\n", eff_size); - ret = -ENOMEM; - goto ssc_session_exit; - } - memset ((void *) ssc_tx_buf, 0, eff_size); - memset ((void *) ssc_rx_buf, 0, eff_size); - - if (tx_len > 0) { - memcpy (ssc_tx_buf, tx_buf, tx_len); - } - - ret = ifx_ssc_kwrite (0, ssc_tx_buf, eff_size); - - if (ret > 0) { - ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite - } - - if (ret != eff_size) { - printk ("ifx_ssc_write return %d\n", ret); - goto ssc_session_exit; - } - ret = ifx_ssc_kread (0, ssc_rx_buf, eff_size); - if (ret != eff_size) { - printk ("ifx_ssc_read return %d\n", ret); - goto ssc_session_exit; - } - - memcpy (rx_buf, ssc_rx_buf + tx_len, rx_len); - - if (mode == IFX_SSC_MODE_TX) { - ret = tx_len; - } - else { - ret = rx_len; - } - ssc_session_exit: - - if (ssc_tx_buf != NULL) - kfree (ssc_tx_buf); - if (ssc_rx_buf != NULL) - kfree (ssc_rx_buf); - - if (ret < 0) { - printk ("ssc session fails\n"); - } - return ret; -} - -int -ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len) -{ - return ssc_session(tx_buf, tx_len, rx_buf, rx_len); -} -EXPORT_SYMBOL(ifx_ssc_txrx); - -int -ifx_ssc_tx (char *tx_buf, u32 tx_len) -{ - return ssc_session(tx_buf, tx_len, NULL, 0); -} -EXPORT_SYMBOL(ifx_ssc_tx); - -int -ifx_ssc_rx (char *rx_buf, u32 rx_len) -{ - return ssc_session(NULL, 0, rx_buf, rx_len); -} -EXPORT_SYMBOL(ifx_ssc_rx); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("John Crispin "); -MODULE_DESCRIPTION("ifxmips ssc driver"); - diff --git a/target/linux/ifxmips/files/drivers/leds/leds-ifxmips.c b/target/linux/ifxmips/files/drivers/leds/leds-ifxmips.c deleted file mode 100644 index 090516c5ad..0000000000 --- a/target/linux/ifxmips/files/drivers/leds/leds-ifxmips.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2006 infineon - * Copyright (C) 2007 John Crispin - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DRVNAME "ifxmips_led" - -#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING -//#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_RISING - -#define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ - -#define IFXMIPS_LED_GPIO_PORT 0 - -#define IFXMIPS_MAX_LED 24 - -struct ifxmips_led { - struct led_classdev cdev; - u8 bit; -}; - -void -ifxmips_led_set (unsigned int led) -{ - led &= 0xffffff; - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0); -} -EXPORT_SYMBOL(ifxmips_led_set); - -void -ifxmips_led_clear (unsigned int led) -{ - led = ~(led & 0xffffff); - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0); -} -EXPORT_SYMBOL(ifxmips_led_clear); - -void -ifxmips_led_blink_set (unsigned int led) -{ - led &= 0xffffff; - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0); -} -EXPORT_SYMBOL(ifxmips_led_blink_set); - -void -ifxmips_led_blink_clear (unsigned int led) -{ - led = ~(led & 0xffffff); - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0); -} -EXPORT_SYMBOL(ifxmips_led_blink_clear); - -void -ifxmips_ledapi_set(struct led_classdev *led_cdev, enum led_brightness value) -{ - struct ifxmips_led *led_dev = container_of(led_cdev, struct ifxmips_led, cdev); - - if(value) - ifxmips_led_set(1 << led_dev->bit); - else - ifxmips_led_clear(1 << led_dev->bit); -} - -void -ifxmips_led_setup_gpio (void) -{ - int i = 0; - - /* we need to setup pins SH,D,ST (4,5,6) */ - for (i = 4; i < 7; i++) - { - ifxmips_port_set_altsel0(IFXMIPS_LED_GPIO_PORT, i); - ifxmips_port_clear_altsel1(IFXMIPS_LED_GPIO_PORT, i); - ifxmips_port_set_dir_out(IFXMIPS_LED_GPIO_PORT, i); - ifxmips_port_set_open_drain(IFXMIPS_LED_GPIO_PORT, i); - } -} - -static int -ifxmips_led_probe(struct platform_device *dev) -{ - int i = 0; - - ifxmips_led_setup_gpio(); - - ifxmips_w32(0, IFXMIPS_LED_AR); - ifxmips_w32(0, IFXMIPS_LED_CPU0); - ifxmips_w32(0, IFXMIPS_LED_CPU1); - ifxmips_w32(LED_CON0_SWU, IFXMIPS_LED_CON0); - ifxmips_w32(0, IFXMIPS_LED_CON1); - - /* setup the clock edge that the shift register is triggered on */ - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, IFXMIPS_LED_CON0); - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, IFXMIPS_LED_CON0); - - /* per default leds 15-0 are set */ - ifxmips_w32(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1); - - /* leds are update periodically by the FPID */ - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, IFXMIPS_LED_CON1); - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, IFXMIPS_LED_CON1); - - /* set led update speed */ - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, IFXMIPS_LED_CON1); - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, IFXMIPS_LED_CON1); - - /* adsl 0 and 1 leds are updated by the arc */ - ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, IFXMIPS_LED_CON0); - - /* per default, the leds are turned on */ - ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_LED); - - for(i = 0; i < IFXMIPS_MAX_LED; i++) - { - struct ifxmips_led *tmp = kzalloc(sizeof(struct ifxmips_led), GFP_KERNEL); - tmp->cdev.brightness_set = ifxmips_ledapi_set; - tmp->cdev.name = kmalloc(sizeof("ifxmips:led:00"), GFP_KERNEL); - sprintf((char*)tmp->cdev.name, "ifxmips:led:%02d", i); - tmp->cdev.default_trigger = NULL; - tmp->bit = i; - led_classdev_register(&dev->dev, &tmp->cdev); - } - - return 0; -} - -static int -ifxmips_led_remove(struct platform_device *pdev) -{ - return 0; -} - -static struct -platform_driver ifxmips_led_driver = { - .probe = ifxmips_led_probe, - .remove = ifxmips_led_remove, - .driver = { - .name = DRVNAME, - .owner = THIS_MODULE, - }, -}; - -int __init -ifxmips_led_init (void) -{ - int ret = platform_driver_register(&ifxmips_led_driver); - if (ret) - printk(KERN_INFO "ifxmips_led: Error registering platfom driver!"); - - return ret; -} - -void __exit -ifxmips_led_exit (void) -{ - platform_driver_unregister(&ifxmips_led_driver); -} - -module_init(ifxmips_led_init); -module_exit(ifxmips_led_exit); diff --git a/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c b/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c deleted file mode 100644 index b3692e72a0..0000000000 --- a/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE - * Copyright (C) 2008 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct map_info -ifxmips_map = { - .name = "ifxmips_mtd", - .bankwidth = 2, - .size = 0x400000, -}; - -static map_word -ifxmips_read16(struct map_info * map, unsigned long adr) -{ - unsigned long flags; - map_word temp; - spin_lock_irqsave(&ebu_lock, flags); - adr ^= 2; - temp.x[0] = *((__u16*)(map->virt + adr)); - spin_unlock_irqrestore(&ebu_lock, flags); - return temp; -} - -static void -ifxmips_write16(struct map_info *map, map_word d, unsigned long adr) -{ - unsigned long flags; - spin_lock_irqsave(&ebu_lock, flags); - adr ^= 2; - *((__u16*)(map->virt + adr)) = d.x[0]; - spin_unlock_irqrestore(&ebu_lock, flags); -} - -void -ifxmips_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) -{ - unsigned char *p; - unsigned char *to_8; - unsigned long flags; - spin_lock_irqsave(&ebu_lock, flags); - from = (unsigned long)(from + map->virt); - p = (unsigned char*) from; - to_8 = (unsigned char*) to; - while(len--) - *to_8++ = *p++; - spin_unlock_irqrestore(&ebu_lock, flags); -} - -void -ifxmips_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) -{ - unsigned char *p = (unsigned char*)from; - unsigned char *to_8; - unsigned long flags; - spin_lock_irqsave(&ebu_lock, flags); - to += (unsigned long) map->virt; - to_8 = (unsigned char*)to; - while(len--) - *p++ = *to_8++; - spin_unlock_irqrestore(&ebu_lock, flags); -} - -static struct mtd_partition -ifxmips_partitions[] = { - { - name:"uboot", - offset:0x00000000, - size:0x00020000, - }, - { - name:"uboot_env", - offset:0x00020000, - size:0x00010000, - }, - { - name:"kernel", - offset:0x00030000, - size:0x0, - }, - { - name:"rootfs", - offset:0x0, - size:0x0, - }, - { - name:"board_config", - offset:0x0, - size:0x0, - }, -}; - -int -find_uImage_size(unsigned long start_offset){ - unsigned long temp; - ifxmips_copy_from(&ifxmips_map, &temp, start_offset + 12, 4); - printk(KERN_INFO "ifxmips_mtd: kernel size is %ld \n", temp + 0x40); - return temp + 0x40; -} - -int -find_brn_block(unsigned long start_offset){ - unsigned char temp[9]; - ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 8); - temp[8] = '\0'; - printk(KERN_INFO "data in brn block %s\n", temp); - if(memcmp(temp, "BRN-BOOT", 8) == 0) - return 1; - else - return 0; -} - -int -detect_squashfs_partition(unsigned long start_offset){ - unsigned long temp; - ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 4); - return (temp == SQUASHFS_MAGIC); -} - -static int -ifxmips_mtd_probe(struct platform_device *dev) -{ - struct mtd_info *ifxmips_mtd = NULL; - struct mtd_partition *parts = NULL; - unsigned long uimage_size; - - ifxmips_w32(0x1d7ff, IFXMIPS_EBU_BUSCON0); - - ifxmips_map.read = ifxmips_read16; - ifxmips_map.write = ifxmips_write16; - ifxmips_map.copy_from = ifxmips_copy_from; - ifxmips_map.copy_to = ifxmips_copy_to; - ifxmips_map.phys = dev->resource->start; - ifxmips_map.size = dev->resource->end - ifxmips_map.phys + 1; - ifxmips_map.virt = ioremap_nocache(ifxmips_map.phys, ifxmips_map.size); - - if(!ifxmips_map.virt) - { - printk(KERN_WARNING "ifxmips_mtd: failed to ioremap!\n"); - return -EIO; - } - - ifxmips_mtd = (struct mtd_info *) do_map_probe("cfi_probe", &ifxmips_map); - if(!ifxmips_mtd) - { - iounmap(ifxmips_map.virt); - printk(KERN_WARNING "ifxmips_mtd: probing failed\n"); - return -ENXIO; - } - - ifxmips_mtd->owner = THIS_MODULE; - uimage_size = find_uImage_size(ifxmips_partitions[2].offset); - - if(detect_squashfs_partition(ifxmips_partitions[2].offset + uimage_size)) - { - printk(KERN_INFO "ifxmips_mtd: found a squashfs following the uImage\n"); - } else { - uimage_size &= ~0xffff; - uimage_size += 0x10000; - } - - parts = &ifxmips_partitions[0]; - ifxmips_partitions[2].size = uimage_size; - ifxmips_partitions[3].offset = ifxmips_partitions[2].offset + ifxmips_partitions[2].size; - ifxmips_partitions[3].size = ((ifxmips_mtd->size >> 20) * 1024 * 1024) - ifxmips_partitions[3].offset; - if(ifxmips_has_brn_block()) - { - ifxmips_partitions[3].size -= ifxmips_mtd->erasesize; - ifxmips_partitions[4].offset = ifxmips_mtd->size - ifxmips_mtd->erasesize; - ifxmips_partitions[4].size = ifxmips_mtd->erasesize; - add_mtd_partitions(ifxmips_mtd, parts, 5); - } else { - add_mtd_partitions(ifxmips_mtd, parts, 4); - } - - printk(KERN_INFO "ifxmips_mtd: added ifxmips flash with %dMB\n", ifxmips_mtd->size >> 20); - return 0; -} - -static struct -platform_driver ifxmips_mtd_driver = { - .probe = ifxmips_mtd_probe, - .driver = { - .name = "ifxmips_mtd", - .owner = THIS_MODULE, - }, -}; - -int __init -init_ifxmips_mtd(void) -{ - int ret = platform_driver_register(&ifxmips_mtd_driver); - if(ret) - printk(KERN_INFO "ifxmips_mtd: error registering platfom driver!"); - return ret; -} - -static void __exit -cleanup_ifxmips_mtd(void) -{ - platform_driver_unregister(&ifxmips_mtd_driver); -} - -module_init(init_ifxmips_mtd); -module_exit(cleanup_ifxmips_mtd); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("John Crispin "); -MODULE_DESCRIPTION("MTD map driver for IFXMIPS boards"); diff --git a/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c b/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c deleted file mode 100644 index fe7f25ec2a..0000000000 --- a/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c +++ /dev/null @@ -1,416 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 Wu Qi Ming - * Copyright (C) 2008 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct ifxmips_mii_priv { - struct net_device_stats stats; - struct dma_device_info *dma_device; - struct sk_buff *skb; -}; - -static struct net_device *ifxmips_mii0_dev; -static unsigned char mac_addr[MAX_ADDR_LEN]; - -void -ifxmips_write_mdio(u32 phy_addr, u32 phy_reg, u16 phy_data) -{ - u32 val = MDIO_ACC_REQUEST | - ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) | - ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) | - phy_data; - - while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST); - ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); -} -EXPORT_SYMBOL(ifxmips_write_mdio); - -unsigned short -ifxmips_read_mdio(u32 phy_addr, u32 phy_reg) -{ - u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ | - ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) | - ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET); - - while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST); - ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); - while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){}; - val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK; - return val; -} -EXPORT_SYMBOL(ifxmips_read_mdio); - -int -ifxmips_ifxmips_mii_open(struct net_device *dev) -{ - struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv; - struct dma_device_info* dma_dev = priv->dma_device; - int i; - - for(i = 0; i < dma_dev->max_rx_chan_num; i++) - { - if((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON) - (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]); - } - netif_start_queue(dev); - return 0; -} - -int -ifxmips_mii_release(struct net_device *dev){ - struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv; - struct dma_device_info* dma_dev = priv->dma_device; - int i; - - for(i = 0; i < dma_dev->max_rx_chan_num; i++) - dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]); - netif_stop_queue(dev); - return 0; -} - -int -ifxmips_mii_hw_receive(struct net_device* dev,struct dma_device_info* dma_dev) -{ - struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)dev->priv; - unsigned char* buf = NULL; - struct sk_buff *skb = NULL; - int len = 0; - - len = dma_device_read(dma_dev, &buf, (void**)&skb); - - if(len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) - { - printk(KERN_INFO "ifxmips_mii0: packet too large %d\n",len); - goto ifxmips_mii_hw_receive_err_exit; - } - - /* remove CRC */ - len -= 4; - if(skb == NULL) - { - printk(KERN_INFO "ifxmips_mii0: cannot restore pointer\n"); - goto ifxmips_mii_hw_receive_err_exit; - } - - if(len > (skb->end - skb->tail)) - { - printk(KERN_INFO "ifxmips_mii0: BUG, len:%d end:%p tail:%p\n", - (len+4), skb->end, skb->tail); - goto ifxmips_mii_hw_receive_err_exit; - } - - skb_put(skb, len); - skb->dev = dev; - skb->protocol = eth_type_trans(skb, dev); - netif_rx(skb); - - priv->stats.rx_packets++; - priv->stats.rx_bytes += len; - return 0; - -ifxmips_mii_hw_receive_err_exit: - if(len == 0) - { - if(skb) - dev_kfree_skb_any(skb); - priv->stats.rx_errors++; - priv->stats.rx_dropped++; - return -EIO; - } else { - return len; - } -} - -int -ifxmips_mii_hw_tx(char *buf, int len, struct net_device *dev) -{ - int ret = 0; - struct ifxmips_mii_priv *priv = dev->priv; - struct dma_device_info* dma_dev = priv->dma_device; - ret = dma_device_write(dma_dev, buf, len, priv->skb); - return ret; -} - -int -ifxmips_mii_tx(struct sk_buff *skb, struct net_device *dev) -{ - int len; - char *data; - struct ifxmips_mii_priv *priv = dev->priv; - struct dma_device_info* dma_dev = priv->dma_device; - - len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; - data = skb->data; - priv->skb = skb; - dev->trans_start = jiffies; - // TODO we got more than 1 dma channel, so we should do something intelligent - // here to select one - dma_dev->current_tx_chan = 0; - - wmb(); - - if(ifxmips_mii_hw_tx(data, len, dev) != len) - { - dev_kfree_skb_any(skb); - priv->stats.tx_errors++; - priv->stats.tx_dropped++; - } else { - priv->stats.tx_packets++; - priv->stats.tx_bytes+=len; - } - - return 0; -} - -void -ifxmips_mii_tx_timeout(struct net_device *dev) -{ - int i; - struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv; - - priv->stats.tx_errors++; - for(i = 0; i < priv->dma_device->max_tx_chan_num; i++) - priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]); - netif_wake_queue(dev); - return; -} - -int -dma_intr_handler(struct dma_device_info* dma_dev, int status) -{ - int i; - - switch(status) - { - case RCV_INT: - ifxmips_mii_hw_receive(ifxmips_mii0_dev, dma_dev); - break; - - case TX_BUF_FULL_INT: - printk(KERN_INFO "ifxmips_mii0: tx buffer full\n"); - netif_stop_queue(ifxmips_mii0_dev); - for (i = 0; i < dma_dev->max_tx_chan_num; i++) - { - if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON) - dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]); - } - break; - - case TRANSMIT_CPT_INT: - for(i = 0; i < dma_dev->max_tx_chan_num; i++) - dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]); - - netif_wake_queue(ifxmips_mii0_dev); - break; - } - - return 0; -} - -unsigned char* -ifxmips_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt) -{ - unsigned char *buffer = NULL; - struct sk_buff *skb = NULL; - - skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE); - if(skb == NULL) - return NULL; - - buffer = (unsigned char*)(skb->data); - skb_reserve(skb, 2); - *(int*)opt = (int)skb; - *byte_offset = 2; - - return buffer; -} - -void -ifxmips_etop_dma_buffer_free(unsigned char *dataptr, void *opt) -{ - struct sk_buff *skb = NULL; - - if(opt == NULL) - { - kfree(dataptr); - } else { - skb = (struct sk_buff*)opt; - dev_kfree_skb_any(skb); - } -} - -static struct net_device_stats* -ifxmips_get_stats(struct net_device *dev) -{ - return (struct net_device_stats *)dev->priv; -} - -static int -ifxmips_mii_dev_init(struct net_device *dev) -{ - int i; - struct ifxmips_mii_priv *priv; - - ether_setup(dev); - printk(KERN_INFO "ifxmips_mii0: %s is up\n", dev->name); - dev->open = ifxmips_ifxmips_mii_open; - dev->stop = ifxmips_mii_release; - dev->hard_start_xmit = ifxmips_mii_tx; - dev->get_stats = ifxmips_get_stats; - dev->tx_timeout = ifxmips_mii_tx_timeout; - dev->watchdog_timeo = 10 * HZ; - memset(dev->priv, 0, sizeof(struct ifxmips_mii_priv)); - priv = dev->priv; - priv->dma_device = dma_device_reserve("PPE"); - if(!priv->dma_device){ - BUG(); - return -ENODEV; - } - priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc; - priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free; - priv->dma_device->intr_handler = &dma_intr_handler; - priv->dma_device->max_rx_chan_num = 4; - - for(i = 0; i < priv->dma_device->max_rx_chan_num; i++) - { - priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE; - priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON; - } - - for(i = 0; i < priv->dma_device->max_tx_chan_num; i++) - if(i == 0) - priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON; - else - priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF; - - dma_device_register(priv->dma_device); - - printk(KERN_INFO "ifxmips_mii0: using mac="); - for(i = 0; i < 6; i++) - { - dev->dev_addr[i] = mac_addr[i]; - printk("%02X%c", dev->dev_addr[i], (i == 5)?('\n'):(':')); - } - return 0; -} - -static void -ifxmips_mii_chip_init(int mode) -{ - ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA); - ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE); - - if(mode == REV_MII_MODE) - ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG); - else if(mode == MII_MODE) - ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG); - ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL); - ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG); - wmb(); -} - -static int -ifxmips_mii_probe(struct platform_device *dev) -{ - int result = 0; - unsigned char *mac = (unsigned char*)dev->dev.platform_data; - ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv)); - ifxmips_mii0_dev->init = ifxmips_mii_dev_init; - memcpy(mac_addr, mac, 6); - strcpy(ifxmips_mii0_dev->name, "eth%d"); - ifxmips_mii_chip_init(REV_MII_MODE); - result = register_netdev(ifxmips_mii0_dev); - if (result) - { - printk(KERN_INFO "ifxmips_mii0: error %i registering device \"%s\"\n", result, ifxmips_mii0_dev->name); - goto out; - } - - printk(KERN_INFO "ifxmips_mii0: driver loaded!\n"); - -out: - return result; -} - -static int -ifxmips_mii_remove(struct platform_device *dev) -{ - struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)ifxmips_mii0_dev->priv; - - printk(KERN_INFO "ifxmips_mii0: ifxmips_mii0 cleanup\n"); - - dma_device_unregister(priv->dma_device); - dma_device_release(priv->dma_device); - kfree(priv->dma_device); - kfree(ifxmips_mii0_dev->priv); - unregister_netdev(ifxmips_mii0_dev); - return 0; -} - -static struct -platform_driver ifxmips_mii_driver = { - .probe = ifxmips_mii_probe, - .remove = ifxmips_mii_remove, - .driver = { - .name = "ifxmips_mii0", - .owner = THIS_MODULE, - }, -}; - -int __init -ifxmips_mii_init(void) -{ - int ret = platform_driver_register(&ifxmips_mii_driver); - if (ret) - printk(KERN_INFO "ifxmips_mii0: Error registering platfom driver!"); - return ret; -} - -static void __exit -ifxmips_mii_cleanup(void) -{ - platform_driver_unregister(&ifxmips_mii_driver); -} - -module_init(ifxmips_mii_init); -module_exit(ifxmips_mii_cleanup); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("John Crispin "); -MODULE_DESCRIPTION("ethernet map driver for IFXMIPS boards"); diff --git a/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c b/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c deleted file mode 100644 index 2dc8917fe1..0000000000 --- a/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c +++ /dev/null @@ -1,599 +0,0 @@ -/* - * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright (C) 2004 Infineon IFAP DC COM CPE - * Copyright (C) 2007 Felix Fietkau - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PORT_IFXMIPSASC 111 - -#include - -#define UART_DUMMY_UER_RX 1 - -static void ifxmipsasc_tx_chars(struct uart_port *port); -extern void prom_printf(const char * fmt, ...); -static struct uart_port ifxmipsasc_port[2]; -static struct uart_driver ifxmipsasc_reg; -extern unsigned int ifxmips_get_fpi_hz(void); - -static void -ifxmipsasc_stop_tx(struct uart_port *port) -{ - return; -} - -static void -ifxmipsasc_start_tx(struct uart_port *port) -{ - unsigned long flags; - local_irq_save(flags); - ifxmipsasc_tx_chars(port); - local_irq_restore(flags); - return; -} - -static void -ifxmipsasc_stop_rx(struct uart_port *port) -{ - ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE); -} - -static void -ifxmipsasc_enable_ms(struct uart_port *port) -{ -} - -static void -ifxmipsasc_rx_chars(struct uart_port *port) -{ - struct tty_struct *tty = port->info->tty; - unsigned int ch = 0, rsr = 0, fifocnt; - - fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; - while(fifocnt--) - { - u8 flag = TTY_NORMAL; - ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF); - rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX; - tty_flip_buffer_push(tty); - port->icount.rx++; - - /* - * Note that the error handling code is - * out of the main execution path - */ - if(rsr & ASCSTATE_ANY) - { - if(rsr & ASCSTATE_PE) - { - port->icount.parity++; - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE); - } else if(rsr & ASCSTATE_FE) - { - port->icount.frame++; - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE); - } - if(rsr & ASCSTATE_ROE) - { - port->icount.overrun++; - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE); - } - - rsr &= port->read_status_mask; - - if(rsr & ASCSTATE_PE) - flag = TTY_PARITY; - else if(rsr & ASCSTATE_FE) - flag = TTY_FRAME; - } - - if((rsr & port->ignore_status_mask) == 0) - tty_insert_flip_char(tty, ch, flag); - - if(rsr & ASCSTATE_ROE) - /* - * Overrun is special, since it's reported - * immediately, and doesn't affect the current - * character - */ - tty_insert_flip_char(tty, 0, TTY_OVERRUN); - } - if(ch != 0) - tty_flip_buffer_push(tty); - return; -} - - -static void -ifxmipsasc_tx_chars(struct uart_port *port) -{ - struct circ_buf *xmit = &port->info->xmit; - if(uart_tx_stopped(port)) - { - ifxmipsasc_stop_tx(port); - return; - } - - while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) - >> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL) - { - if(port->x_char) - { - ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF); - port->icount.tx++; - port->x_char = 0; - continue; - } - - if(uart_circ_empty(xmit)) - break; - - ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], port->membase + IFXMIPS_ASC_TBUF); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); - port->icount.tx++; - } - - if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(port); -} - -static irqreturn_t -ifxmipsasc_tx_int(int irq, void *_port) -{ - struct uart_port *port = (struct uart_port*) _port; - ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR); - ifxmipsasc_start_tx(port); - ifxmips_mask_and_ack_irq(irq); - return IRQ_HANDLED; -} - -static irqreturn_t -ifxmipsasc_er_int(int irq, void *_port) -{ - struct uart_port *port = (struct uart_port*) _port; - /* clear any pending interrupts */ - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE | - ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE); - return IRQ_HANDLED; -} - -static irqreturn_t -ifxmipsasc_rx_int(int irq, void *_port) -{ - struct uart_port *port = (struct uart_port*)_port; - ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR); - ifxmipsasc_rx_chars((struct uart_port*)port); - ifxmips_mask_and_ack_irq(irq); - return IRQ_HANDLED; -} - -static unsigned int -ifxmipsasc_tx_empty(struct uart_port *port) -{ - int status; - status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; - return status ? 0 : TIOCSER_TEMT; -} - -static unsigned int -ifxmipsasc_get_mctrl(struct uart_port *port) -{ - return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; -} - -static void -ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl) -{ -} - -static void -ifxmipsasc_break_ctl(struct uart_port *port, int break_state) -{ -} - -static int -ifxmipsasc_startup(struct uart_port *port) -{ - unsigned long flags; - int retval; - - port->uartclk = ifxmips_get_fpi_hz(); - - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC); - ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC); - ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL); - ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON); - ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON); - wmb (); - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON); - - local_irq_save(flags); - - retval = request_irq(port->irq, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port); - if(retval) - { - printk("failed to request ifxmipsasc_tx_int\n"); - return retval; - } - - retval = request_irq(port->irq + 2, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port); - if(retval) - { - printk("failed to request ifxmipsasc_rx_int\n"); - goto err1; - } - - retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port); - if(retval) - { - printk("failed to request ifxmipsasc_er_int\n"); - goto err2; - } - - ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + IFXMIPS_ASC_IRNREN); - - local_irq_restore(flags); - return 0; - -err2: - free_irq(port->irq + 2, port); -err1: - free_irq(port->irq, port); - local_irq_restore(flags); - return retval; -} - -static void -ifxmipsasc_shutdown(struct uart_port *port) -{ - free_irq(port->irq, port); - free_irq(port->irq + 2, port); - free_irq(port->irq + 3, port); - - ifxmips_w32(0, port->membase + IFXMIPS_ASC_CON); - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON); - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) & ~ASCRXFCON_RXFEN, port->membase + IFXMIPS_ASC_RXFCON); - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON); - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) & ~ASCTXFCON_TXFEN, port->membase + IFXMIPS_ASC_TXFCON); -} - -static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old) -{ - unsigned int cflag; - unsigned int iflag; - unsigned int quot; - unsigned int baud; - unsigned int con = 0; - unsigned long flags; - - cflag = new->c_cflag; - iflag = new->c_iflag; - - switch(cflag & CSIZE) - { - case CS7: - con = ASCCON_M_7ASYNC; - break; - - case CS5: - case CS6: - default: - con = ASCCON_M_8ASYNC; - break; - } - - if(cflag & CSTOPB) - con |= ASCCON_STP; - - if(cflag & PARENB) - { - if(!(cflag & PARODD)) - con &= ~ASCCON_ODD; - else - con |= ASCCON_ODD; - } - - port->read_status_mask = ASCSTATE_ROE; - if(iflag & INPCK) - port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; - - port->ignore_status_mask = 0; - if(iflag & IGNPAR) - port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; - - if(iflag & IGNBRK) - { - /* - * If we're ignoring parity and break indicators, - * ignore overruns too (for real raw support). - */ - if(iflag & IGNPAR) - port->ignore_status_mask |= ASCSTATE_ROE; - } - - if((cflag & CREAD) == 0) - port->ignore_status_mask |= UART_DUMMY_UER_RX; - - /* set error signals - framing, parity and overrun, enable receiver */ - con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; - - local_irq_save(flags); - - /* set up CON */ - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON); - - /* Set baud rate - take a divider of 2 into account */ - baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); - quot = uart_get_divisor(port, baud); - quot = quot / 2 - 1; - - /* disable the baudrate generator */ - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_R, port->membase + IFXMIPS_ASC_CON); - - /* make sure the fractional divider is off */ - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_FDE, port->membase + IFXMIPS_ASC_CON); - - /* set up to use divisor of 2 */ - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_BRS, port->membase + IFXMIPS_ASC_CON); - - /* now we can write the new baudrate into the register */ - ifxmips_w32(quot, port->membase + IFXMIPS_ASC_BG); - - /* turn the baudrate generator back on */ - ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_R, port->membase + IFXMIPS_ASC_CON); - - /* enable rx */ - ifxmips_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE); - - local_irq_restore(flags); -} - -static const char* -ifxmipsasc_type(struct uart_port *port) -{ - if(port->type == PORT_IFXMIPSASC) - { - if(port->membase == (void*)IFXMIPS_ASC_BASE_ADDR) - return "asc0"; - else - return "asc1"; - } else { - return NULL; - } -} - -static void -ifxmipsasc_release_port(struct uart_port *port) -{ -} - -static int -ifxmipsasc_request_port(struct uart_port *port) -{ - return 0; -} - -static void -ifxmipsasc_config_port(struct uart_port *port, int flags) -{ - if(flags & UART_CONFIG_TYPE) - { - port->type = PORT_IFXMIPSASC; - ifxmipsasc_request_port(port); - } -} - -static int -ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser) -{ - int ret = 0; - if(ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC) - ret = -EINVAL; - if(ser->irq < 0 || ser->irq >= NR_IRQS) - ret = -EINVAL; - if(ser->baud_base < 9600) - ret = -EINVAL; - return ret; -} - -static struct uart_ops ifxmipsasc_pops = -{ - .tx_empty = ifxmipsasc_tx_empty, - .set_mctrl = ifxmipsasc_set_mctrl, - .get_mctrl = ifxmipsasc_get_mctrl, - .stop_tx = ifxmipsasc_stop_tx, - .start_tx = ifxmipsasc_start_tx, - .stop_rx = ifxmipsasc_stop_rx, - .enable_ms = ifxmipsasc_enable_ms, - .break_ctl = ifxmipsasc_break_ctl, - .startup = ifxmipsasc_startup, - .shutdown = ifxmipsasc_shutdown, - .set_termios = ifxmipsasc_set_termios, - .type = ifxmipsasc_type, - .release_port = ifxmipsasc_release_port, - .request_port = ifxmipsasc_request_port, - .config_port = ifxmipsasc_config_port, - .verify_port = ifxmipsasc_verify_port, -}; - -static struct uart_port ifxmipsasc_port[2] = -{ - { - membase: (void *)IFXMIPS_ASC_BASE_ADDR, - mapbase: IFXMIPS_ASC_BASE_ADDR, - iotype: SERIAL_IO_MEM, - irq: IFXMIPSASC_TIR(0), - uartclk: 0, - fifosize: 16, - type: PORT_IFXMIPSASC, - ops: &ifxmipsasc_pops, - flags: ASYNC_BOOT_AUTOCONF, - line: 0 - }, { - membase: (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF), - mapbase: IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF, - iotype: SERIAL_IO_MEM, - irq: IFXMIPSASC_TIR(1), - uartclk: 0, - fifosize: 16, - type: PORT_IFXMIPSASC, - ops: &ifxmipsasc_pops, - flags: ASYNC_BOOT_AUTOCONF, - line: 1 - } -}; - -static void -ifxmipsasc_console_write(struct console *co, const char *s, u_int count) -{ - int port = co->index; - int i, fifocnt; - unsigned long flags; - local_irq_save(flags); - for(i = 0; i < count; i++) - { - do { - fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) - >> ASCFSTAT_TXFFLOFF; - } while(fifocnt == TXFIFO_FULL); - - if(s[i] == '\0') - break; - - if(s[i] == '\n') - { - ifxmips_w32('\r', (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF)); - do { - fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) - >> ASCFSTAT_TXFFLOFF; - } while(fifocnt == TXFIFO_FULL); - } - ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF)); - } - - local_irq_restore(flags); -} - -static int __init -ifxmipsasc_console_setup(struct console *co, char *options) -{ - int port = co->index; - int baud = 115200; - int bits = 8; - int parity = 'n'; - int flow = 'n'; - ifxmipsasc_port[port].uartclk = ifxmips_get_fpi_hz(); - ifxmipsasc_port[port].type = PORT_IFXMIPSASC; - if(options) - uart_parse_options(options, &baud, &parity, &bits, &flow); - return uart_set_options(&ifxmipsasc_port[port], co, baud, parity, bits, flow); -} - -static struct console ifxmipsasc_console[2] = -{ - { - name: "ttyS", - write: ifxmipsasc_console_write, - device: uart_console_device, - setup: ifxmipsasc_console_setup, - flags: CON_PRINTBUFFER, - index: 0, - data: &ifxmipsasc_reg, - }, { - name: "ttyS", - write: ifxmipsasc_console_write, - device: uart_console_device, - setup: ifxmipsasc_console_setup, - flags: CON_PRINTBUFFER, - index: 1, - data: &ifxmipsasc_reg, - } -}; - -static int __init -ifxmipsasc_console_init(void) -{ - register_console(&ifxmipsasc_console[0]); - register_console(&ifxmipsasc_console[1]); - return 0; -} -console_initcall(ifxmipsasc_console_init); - -static struct uart_driver ifxmipsasc_reg = -{ - .owner = THIS_MODULE, - .driver_name = "serial", - .dev_name = "ttyS", - .major = TTY_MAJOR, - .minor = 64, - .nr = 2, - .cons = &ifxmipsasc_console[1], -}; - -int __init -ifxmipsasc_init(void) -{ - int ret; - uart_register_driver(&ifxmipsasc_reg); - ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[0]); - ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[1]); - return 0; -} - -void __exit -ifxmipsasc_exit(void) -{ - uart_unregister_driver(&ifxmipsasc_reg); -} - -module_init(ifxmipsasc_init); -module_exit(ifxmipsasc_exit); - -MODULE_AUTHOR("John Crispin "); -MODULE_DESCRIPTION("MIPS IFXMips serial port driver"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/ifxmips/files/drivers/watchdog/ifxmips_wdt.c b/target/linux/ifxmips/files/drivers/watchdog/ifxmips_wdt.c deleted file mode 100644 index 58e2161489..0000000000 --- a/target/linux/ifxmips/files/drivers/watchdog/ifxmips_wdt.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright (C) 2008 John Crispin - * Based on EP93xx wdt driver - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IFXMIPS_WDT_PW1 0x00BE0000 -#define IFXMIPS_WDT_PW2 0x00DC0000 - -#ifndef CONFIG_WATCHDOG_NOWAYOUT -static int wdt_ok_to_close = 0; -#endif - -int wdt_timeout = 30; - -int -ifxmips_wdt_enable(unsigned int timeout) -{ - u32 fpi; - fpi = cgu_get_io_region_clock(); - ifxmips_w32(IFXMIPS_WDT_PW1, IFXMIPS_BIU_WDT_CR); - ifxmips_w32(IFXMIPS_WDT_PW2 | - (0x3 << 26) | // PWL - (0x3 << 24) | // CLKDIV - (0x1 << 31) | // enable - ((timeout * (fpi / 0x40000)) + 0x1000), // reload - IFXMIPS_BIU_WDT_CR); - return 0; -} - -void -ifxmips_wdt_disable(void) -{ -#ifndef CONFIG_WATCHDOG_NOWAYOUT - wdt_ok_to_close = 0; -#endif - ifxmips_w32(IFXMIPS_WDT_PW1, IFXMIPS_BIU_WDT_CR); - ifxmips_w32(IFXMIPS_WDT_PW2, IFXMIPS_BIU_WDT_CR); -} - -static ssize_t -ifxmips_wdt_write(struct file *file, const char __user *data, size_t len, - loff_t *ppos) -{ - size_t i; - - if(!len) - return 0; - -#ifndef CONFIG_WATCHDOG_NOWAYOUT - for(i = 0; i != len; i++) - { - char c; - if(get_user(c, data + i)) - return -EFAULT; - if(c == 'V') - wdt_ok_to_close = 1; - } -#endif - ifxmips_wdt_enable(wdt_timeout); - return len; -} - -static struct watchdog_info ident = { - .options = WDIOF_MAGICCLOSE, - .identity = "ifxmips Watchdog", -}; - -static int -ifxmips_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) -{ - int ret = -ENOTTY; - - switch(cmd) - { - case WDIOC_GETSUPPORT: - ret = copy_to_user((struct watchdog_info __user *)arg, &ident, - sizeof(ident)) ? -EFAULT : 0; - break; - - case WDIOC_GETTIMEOUT: - ret = put_user(wdt_timeout, (int __user *)arg); - break; - - case WDIOC_SETTIMEOUT: - ret = get_user(wdt_timeout, (int __user*)arg); - break; - - case WDIOC_KEEPALIVE: - ifxmips_wdt_enable(wdt_timeout); - ret = 0; - break; - } - return ret; -} - -static int -ifxmips_wdt_open(struct inode *inode, struct file *file) -{ - ifxmips_wdt_enable(wdt_timeout); - return nonseekable_open(inode, file); -} - -static int ifxmips_wdt_release(struct inode *inode, struct file *file) -{ -#ifndef CONFIG_WATCHDOG_NOWAYOUT - if(wdt_ok_to_close) - ifxmips_wdt_disable(); - else -#endif - printk("ifxmips_wdt: watchdog closed without warning, rebooting system\n"); - return 0; -} - -static const struct file_operations ifxmips_wdt_fops = { - .owner = THIS_MODULE, - .write = ifxmips_wdt_write, - .ioctl = ifxmips_wdt_ioctl, - .open = ifxmips_wdt_open, - .release = ifxmips_wdt_release, -}; - -static struct miscdevice ifxmips_wdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &ifxmips_wdt_fops, -}; - -static int -ifxmips_wdt_probe(struct platform_device *dev) -{ - int err; - err = misc_register(&ifxmips_wdt_miscdev); - if(err) - printk("ifxmips_wdt: error creating device\n"); - else - printk("ifxmips_wdt: loaded\n"); - return err; -} - -static int -ifxmips_wdt_remove(struct platform_device *dev) -{ - ifxmips_wdt_disable(); - misc_deregister(&ifxmips_wdt_miscdev); - return 0; -} - - -static struct platform_driver ifxmips_wdt_driver = { - .probe = ifxmips_wdt_probe, - .remove = ifxmips_wdt_remove, - .driver = { - .name = "ifxmips_wdt", - .owner = THIS_MODULE, - }, -}; - -static int __init -init_ifxmips_wdt(void) -{ - int ret = platform_driver_register(&ifxmips_wdt_driver); - if(ret) - printk(KERN_INFO "ifxmips_wdt: error registering platfom driver!"); - return ret; -} - -static void __exit -exit_ifxmips_wdt(void) -{ - platform_driver_unregister(&ifxmips_wdt_driver); -} - -module_init(init_ifxmips_wdt); -module_exit(exit_ifxmips_wdt); - -MODULE_AUTHOR("John Crispin "); -MODULE_DESCRIPTION("ifxmips Watchdog"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifx_peripheral_definitions.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifx_peripheral_definitions.h deleted file mode 100644 index 5bd788fff6..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifx_peripheral_definitions.h +++ /dev/null @@ -1,119 +0,0 @@ -//************************************************************************* -//* Summary of definitions which are used in each peripheral * -//************************************************************************* - -#ifndef peripheral_definitions_h -#define peripheral_definitions_h - -////#include "cpu.h" -// -///* These files have to be included by each peripheral */ -//#include -//#include -//#include -//#include -//#include -//#include "SRAM_address_map.h" -// -///* common header files for all CPU's */ -//#include "iiu.h" -//#include "bcu.h" -//#include "FPI_address_map.h" -//#include "direct_interrupts.h" - -///////////////////////////////////////////////////////////////////////// - -//extern int _clz(); -//extern void _nop(); -//extern void _sleep(); -//extern void sys_enable_int(); - -typedef unsigned char UINT8; -typedef signed char INT8; -typedef unsigned short UINT16; -typedef signed short INT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef signed long long INT64; - -#define REG8( addr ) (*(volatile UINT8 *) (addr)) -#define REG16( addr ) (*(volatile UINT16 *)(addr)) -#define REG32( addr ) (*(volatile UINT32 *)(addr)) -#define REG64( addr ) (*(volatile UINT64 *)(addr)) - -/* define routine to set FPI access in Supervisor Mode */ -#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01 -/* Supervisor mode ends, following functions will be done in User mode */ -#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00 -/* Supervisor mode ends, following functions will be done in User mode */ -#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG) -/* Supervisor mode ends, following functions will be done in User mode */ -#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm -/* enable all Interrupts in IIU */ -//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask -///* get all high priority interrupt bits in IIU */ -//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED) -///* signal ends of interrupt to IIU */ -//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit -///* force IIU interrupt register */ -//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data -///* get all bits of interrupt register */ -//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR) -/* insert a NOP instruction */ -#define NOP _nop() -/* CPU goes to power down mode until interrupt occurs */ -#define IFX_CPU_SLEEP _sleep() -/* enable all interrupts to CPU */ -#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int() -/* get all low priority interrupt bits in peripheral */ -#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg) -/* clear low priority interrupt bit in peripheral */ -#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit -/* write FPI bus */ -#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data -#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data -#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data -/* read FPI bus */ -#define READ_FPI_BYTE(addr) REG8(addr) -#define READ_FPI_16BIT(addr) REG16(addr) -#define READ_FPI_32BIT(addr) REG32(addr) -/* write peripheral register */ -#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data -#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data -#else //not CONFIG_CPU_LITTLE_ENDIAN -#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data -#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data -#endif //CONFIG_CPU_LITTLE_ENDIAN - -/* read peripheral register */ -#define READ_PERIPHERAL_REGISTER(addr) REG32(addr) - -/* read/modify(or)/write peripheral register */ -#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data -/* read/modify(and)/write peripheral register */ -#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data - -/* CPU-independent mnemonic constants */ -/* CLC register bits */ -#define IFX_CLC_ENABLE 0x00000000 -#define IFX_CLC_DISABLE 0x00000001 -#define IFX_CLC_DISABLE_STATUS 0x00000002 -#define IFX_CLC_SUSPEND_ENABLE 0x00000004 -#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008 -#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010 -#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020 -#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00 -#define IFX_CLC_RUN_DIVIDER_OFFSET 8 -#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000 -#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16 -#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000 -#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24 - -/* number of cycles to wait for interrupt service routine to be called */ -#define WAIT_CYCLES 50 - -#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */ diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifx_ssc.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifx_ssc.h deleted file mode 100644 index c6dd5d47a9..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifx_ssc.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * ifx_ssc.h defines some data sructures used in ifx_ssc.c - * - * Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT) - * - * - */ - -#ifndef __IFX_SSC_H -#define __IFX_SSC_H -#ifdef __KERNEL__ -#include -#endif //__KERNEL__ - -#define PORT_CNT 1 // assume default value - -/* symbolic constants to be used in SSC routines */ - -// ### TO DO: bad performance -#define IFX_SSC_TXFIFO_ITL 1 -#define IFX_SSC_RXFIFO_ITL 1 - -struct ifx_ssc_statistics { - unsigned int abortErr; /* abort error */ - unsigned int modeErr; /* master/slave mode error */ - unsigned int txOvErr; /* TX Overflow error */ - unsigned int txUnErr; /* TX Underrun error */ - unsigned int rxOvErr; /* RX Overflow error */ - unsigned int rxUnErr; /* RX Underrun error */ - unsigned int rxBytes; - unsigned int txBytes; -}; - -struct ifx_ssc_hwopts { - unsigned int AbortErrDetect:1; /* Abort Error detection (in slave mode) */ - unsigned int rxOvErrDetect:1; /* Receive Overflow Error detection */ - unsigned int rxUndErrDetect:1; /* Receive Underflow Error detection */ - unsigned int txOvErrDetect:1; /* Transmit Overflow Error detection */ - unsigned int txUndErrDetect:1; /* Transmit Underflow Error detection */ - unsigned int echoMode:1; /* Echo mode */ - unsigned int loopBack:1; /* Loopback mode */ - unsigned int idleValue:1; /* Idle value */ - unsigned int clockPolarity:1; /* Idle clock is high or low */ - unsigned int clockPhase:1; /* Tx on trailing or leading edge */ - unsigned int headingControl:1; /* LSB first or MSB first */ - unsigned int dataWidth:6; /* from 2 up to 32 bits */ - unsigned int masterSelect:1; /* Master or Slave mode */ - unsigned int modeRxTx:2; /* rx/tx mode */ - unsigned int gpoCs:8; /* choose outputs to use for chip select */ - unsigned int gpoInv:8; /* invert GPO outputs */ -}; - -struct ifx_ssc_frm_opts { - bool FrameEnable; // SFCON.SFEN - unsigned int DataLength; // SFCON.DLEN - unsigned int PauseLength; // SFCON.PLEN - unsigned int IdleData; // SFCON.IDAT - unsigned int IdleClock; // SFCON.ICLK - bool StopAfterPause; // SFCON.STOP -}; - -struct ifx_ssc_frm_status { - bool DataBusy; // SFSTAT.DBSY - bool PauseBusy; // SFSTAT.PBSY - unsigned int DataCount; // SFSTAT.DCNT - unsigned int PauseCount; // SFSTAT.PCNT - bool EnIntAfterData; // SFCON.IBEN - bool EnIntAfterPause; // SFCON.IAEN -}; - -typedef struct { - char *buf; - size_t len; -} ifx_ssc_buf_item_t; - -// data structures for batch execution -typedef union { - struct { - bool save_options; - } init; - ifx_ssc_buf_item_t read; - ifx_ssc_buf_item_t write; - ifx_ssc_buf_item_t rd_wr; - unsigned int set_baudrate; - struct ifx_ssc_frm_opts set_frm; - unsigned int set_gpo; - struct ifx_ssc_hwopts set_hwopts; -} ifx_ssc_batch_cmd_param; - -struct ifx_ssc_batch_list { - unsigned int cmd; - ifx_ssc_batch_cmd_param cmd_param; - struct ifx_ssc_batch_list *next; -}; - -#ifdef __KERNEL__ -#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE) - -struct ifx_ssc_port { - unsigned long mapbase; - struct ifx_ssc_hwopts opts; - struct ifx_ssc_statistics stats; - struct ifx_ssc_frm_status frm_status; - struct ifx_ssc_frm_opts frm_opts; - /* wait queue for ifx_ssc_read() */ - wait_queue_head_t rwait, pwait; - int port_nr; - char port_is_open; /* exclusive open - boolean */ -// int no_of_bits; /* number of _valid_ bits */ -// int elem_size; /* shift for element (no of bytes)*/ - /* buffer and pointers to the read/write position */ - char *rxbuf; /* buffer for RX */ - char *rxbuf_end; /* buffer end pointer for RX */ - volatile char *rxbuf_ptr; /* buffer write pointer for RX */ - char *txbuf; /* buffer for TX */ - char *txbuf_end; /* buffer end pointer for TX */ - volatile char *txbuf_ptr; /* buffer read pointer for TX */ - unsigned int baud; - /* each channel has its own interrupts */ - /* (transmit/receive/error/frame) */ - unsigned int txirq, rxirq, errirq, frmirq; -}; -/* default values for SSC configuration */ -// values of CON -#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */ -#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */ -#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */ -#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */ -#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */ -#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */ -#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */ -#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */ -#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST -#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX -// other values -#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */ -#ifdef CONFIG_USE_EMULATOR -#define IFX_SSC_DEF_BAUDRATE 10000 -#else -#define IFX_SSC_DEF_BAUDRATE 2000000 -#endif -#define IFX_SSC_DEF_RMC 0x10 - -#define IFX_SSC_DEF_TXFIFO_FL 8 -#define IFX_SSC_DEF_RXFIFO_FL 1 - -#if 1 //TODO -#define IFX_SSC_DEF_GPO_CS 0x3 /* no chip select */ -#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */ -#else -#error "what is ur Chip Select???" -#endif -#define IFX_SSC_DEF_SFCON 0 /* no serial framing */ -#if 0 -#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ - IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT -#endif -#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ - IFX_SSC_R_BIT | IFX_SSC_E_BIT -#endif /* __KERNEL__ */ - -// batch execution commands -#define IFX_SSC_BATCH_CMD_INIT 1 -#define IFX_SSC_BATCH_CMD_READ 2 -#define IFX_SSC_BATCH_CMD_WRITE 3 -#define IFX_SSC_BATCH_CMD_RD_WR 4 -#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5 -#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6 -#define IFX_SSC_BATCH_CMD_SET_FRM 7 -#define IFX_SSC_BATCH_CMD_SET_GPO 8 -#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9 -//#define IFX_SSC_BATCH_CMD_ -//#define IFX_SSC_BATCH_CMD_ -#define IFX_SSC_BATCH_CMD_END_EXEC 0 - -/* Macros to configure SSC hardware */ -/* headingControl: */ -#define IFX_SSC_LSB_FIRST 0 -#define IFX_SSC_MSB_FIRST 1 -/* dataWidth: */ -#define IFX_SSC_MIN_DATA_WIDTH 2 -#define IFX_SSC_MAX_DATA_WIDTH 32 -/* master/slave mode select */ -#define IFX_SSC_MASTER_MODE 1 -#define IFX_SSC_SLAVE_MODE 0 -/* rx/tx mode */ -// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h -#define IFX_SSC_MODE_RXTX 0 -#define IFX_SSC_MODE_RX 1 -#define IFX_SSC_MODE_TX 2 -#define IFX_SSC_MODE_OFF 3 -#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX - -/* GPO values */ -#define IFX_SSC_MAX_GPO_OUT 7 - -#define IFX_SSC_RXREQ_BLOCK_SIZE 32768 - -/***********************/ -/* defines for ioctl's */ -/***********************/ -#define IFX_SSC_IOCTL_MAGIC 'S' -/* read out the statistics */ -#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics) -/* clear the statistics */ -#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2) -/* set the baudrate */ -#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int) -/* get the current baudrate */ -#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int) -/* set hardware options */ -#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts) -/* get the current hardware options */ -#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts) -/* set transmission mode */ -#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int) -/* get the current transmission mode */ -#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int) -/* abort transmission */ -#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9) -#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9) - -/* set general purpose outputs */ -#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int) -/* clear general purpose outputs */ -#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int) -/* get general purpose outputs */ -#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int) - -/*** serial framing ***/ -/* get status of serial framing */ -#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status) -/* get counter reload values and control bits */ -#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts) -/* set counter reload values and control bits */ -#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts) - -/*** batch execution ***/ -/* do batch execution */ -#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list) - -#ifdef __KERNEL__ -// routines from ifx_ssc.c -// ### TO DO -/* kernel interface for read and write */ -ssize_t ifx_ssc_kread (int, char *, size_t); -ssize_t ifx_ssc_kwrite (int, const char *, size_t); - -#ifdef CONFIG_IFX_VP_KERNEL_TEST -void ifx_ssc_tc (void); -#endif // CONFIG_IFX_VP_KERNEL_TEST - -#endif //__KERNEL__ -#endif // __IFX_SSC_H diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifx_ssc_defines.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifx_ssc_defines.h deleted file mode 100644 index 805d48ad84..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifx_ssc_defines.h +++ /dev/null @@ -1,547 +0,0 @@ -#ifndef IFX_SSC_DEFINES_H -#define IFX_SSC_DEFINES_H - -#include "ifx_peripheral_definitions.h" - -/* maximum SSC FIFO size */ -#define IFX_SSC_MAX_FIFO_SIZE 32 - -/* register map of SSC */ - -/* address of the Clock Control Register of the SSC */ -#define IFX_SSC_CLC 0x00000000 -/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0 - bit 1 is hardware modified*/ -#define IFX_SSC_CLC_readmask 0x00FFFFEF -#define IFX_SSC_CLC_writemask 0x00FFFF3D -#define IFX_SSC_CLC_hwmask 0x00000002 -#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask) - -/* address of Port Input Select Register of the SSC */ -#define IFX_SSC_PISEL 0x00000004 -/* IFX_SSC_PISEL register is significant in lowest three bits only */ -#define IFX_SSC_PISEL_readmask 0x00000007 -#define IFX_SSC_PISEL_writemask 0x00000007 -#define IFX_SSC_PISEL_hwmask 0x00000000 -#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask) - -/* address of Identification Register of the SSC */ -#define IFX_SSC_ID 0x00000008 -/* IFX_SSC_ID register is significant in no bit */ -#define IFX_SSC_ID_readmask 0x0000FF3F -#define IFX_SSC_ID_writemask 0x00000000 -#define IFX_SSC_ID_hwmask 0x00000000 -#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask) - -/* address of the Control Register of the SSC */ -#define IFX_SSC_CON 0x00000010 -/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */ -#define IFX_SSC_CON_readmask 0x01DF1FFF -#define IFX_SSC_CON_writemask 0x01DF1FFF -#define IFX_SSC_CON_hwmask 0x00000000 -#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask) - -/* address of the Status Register of the SSC */ -#define IFX_SSC_STATE 0x00000014 -/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0 - all bits except 1:0 are hardware modified */ -#define IFX_SSC_STATE_readmask 0x771F3F87 -#define IFX_SSC_STATE_writemask 0x00000000 -#define IFX_SSC_STATE_hwmask 0x771F3F84 -#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask) - -/* address of the Write Hardware Modified Control Register Bits of the SSC */ -#define IFX_SSC_WHBSTATE 0x00000018 -/* IFX_SSC_WHBSTATE register is write only */ -#define IFX_SSC_WHBSTATE_readmask 0x00000000 -#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF -#define IFX_SSC_WHBSTATE_hwmask 0x00000000 -#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask) - -/* address of the Baudrate Timer Reload Register of the SSC */ -#define IFX_SSC_BR 0x00000040 -/* IFX_SSC_BR register is significant in bit 15 downto 0*/ -#define IFX_SSC_BR_readmask 0x0000FFFF -#define IFX_SSC_BR_writemask 0x0000FFFF -#define IFX_SSC_BR_hwmask 0x00000000 -#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask) - -/* address of the Baudrate Timer Status Register of the SSC */ -#define IFX_SSC_BRSTAT 0x00000044 -/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/ -#define IFX_SSC_BRSTAT_readmask 0x0000FFFF -#define IFX_SSC_BRSTAT_writemask 0x00000000 -#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF -#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask) - -/* address of the Transmitter Buffer Register of the SSC */ -#define IFX_SSC_TB 0x00000020 -/* IFX_SSC_TB register is significant in bit 31 downto 0*/ -#define IFX_SSC_TB_readmask 0xFFFFFFFF -#define IFX_SSC_TB_writemask 0xFFFFFFFF -#define IFX_SSC_TB_hwmask 0x00000000 -#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask) - -/* address of the Reciver Buffer Register of the SSC */ -#define IFX_SSC_RB 0x00000024 -/* IFX_SSC_RB register is significant in no bits*/ -#define IFX_SSC_RB_readmask 0xFFFFFFFF -#define IFX_SSC_RB_writemask 0x00000000 -#define IFX_SSC_RB_hwmask 0xFFFFFFFF -#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask) - -/* address of the Receive FIFO Control Register of the SSC */ -#define IFX_SSC_RXFCON 0x00000030 -/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ -#define IFX_SSC_RXFCON_readmask 0x00003F03 -#define IFX_SSC_RXFCON_writemask 0x00003F03 -#define IFX_SSC_RXFCON_hwmask 0x00000000 -#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask) - -/* address of the Transmit FIFO Control Register of the SSC */ -#define IFX_SSC_TXFCON 0x00000034 -/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ -#define IFX_SSC_TXFCON_readmask 0x00003F03 -#define IFX_SSC_TXFCON_writemask 0x00003F03 -#define IFX_SSC_TXFCON_hwmask 0x00000000 -#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask) - -/* address of the FIFO Status Register of the SSC */ -#define IFX_SSC_FSTAT 0x00000038 -/* IFX_SSC_FSTAT register is significant in no bit*/ -#define IFX_SSC_FSTAT_readmask 0x00003F3F -#define IFX_SSC_FSTAT_writemask 0x00000000 -#define IFX_SSC_FSTAT_hwmask 0x00003F3F -#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask) - -/* address of the Data Frame Control register of the SSC */ -#define IFX_SSC_SFCON 0x00000060 -#define IFX_SSC_SFCON_readmask 0xFFDFFFFD -#define IFX_SSC_SFCON_writemask 0xFFDFFFFD -#define IFX_SSC_SFCON_hwmask 0x00000000 -#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask) - -/* address of the Data Frame Status register of the SSC */ -#define IFX_SSC_SFSTAT 0x00000064 -#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3 -#define IFX_SSC_SFSTAT_writemask 0x00000000 -#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3 -#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask) - -/* address of the General Purpose Output Control register of the SSC */ -#define IFX_SSC_GPOCON 0x00000070 -#define IFX_SSC_GPOCON_readmask 0x0000FFFF -#define IFX_SSC_GPOCON_writemask 0x0000FFFF -#define IFX_SSC_GPOCON_hwmask 0x00000000 -#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask) - -/* address of the General Purpose Output Status register of the SSC */ -#define IFX_SSC_GPOSTAT 0x00000074 -#define IFX_SSC_GPOSTAT_readmask 0x000000FF -#define IFX_SSC_GPOSTAT_writemask 0x00000000 -#define IFX_SSC_GPOSTAT_hwmask 0x00000000 -#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask) - -/* address of the Force GPO Status register of the SSC */ -#define IFX_SSC_WHBGPOSTAT 0x00000078 -#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000 -#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF -#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000 -#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask) - -/* address of the Receive Request Register of the SSC */ -#define IFX_SSC_RXREQ 0x00000080 -#define IFX_SSC_RXREQ_readmask 0x0000FFFF -#define IFX_SSC_RXREQ_writemask 0x0000FFFF -#define IFX_SSC_RXREQ_hwmask 0x00000000 -#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask) - -/* address of the Receive Count Register of the SSC */ -#define IFX_SSC_RXCNT 0x00000084 -#define IFX_SSC_RXCNT_readmask 0x0000FFFF -#define IFX_SSC_RXCNT_writemask 0x00000000 -#define IFX_SSC_RXCNT_hwmask 0x0000FFFF -#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask) - -/* address of the DMA Configuration Register of the SSC */ -#define IFX_SSC_DMACON 0x000000EC -#define IFX_SSC_DMACON_readmask 0x0000FFFF -#define IFX_SSC_DMACON_writemask 0x00000000 -#define IFX_SSC_DMACON_hwmask 0x0000FFFF -#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask) - -//------------------------------------------------------ -// interrupt register for enabling interrupts, mask register of irq_reg -#define IFX_SSC_IRN_EN 0xF4 -// read/write -#define IFX_SSC_IRN_EN_readmask 0x0000000F -#define IFX_SSC_IRN_EN_writemask 0x0000000F -#define IFX_SSC_IRN_EN_hwmask 0x00000000 -#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask) - -// interrupt register for accessing interrupts -#define IFX_SSC_IRN_CR 0xF8 -// read/write -#define IFX_SSC_IRN_CR_readmask 0x0000000F -#define IFX_SSC_IRN_CR_writemask 0x0000000F -#define IFX_SSC_IRN_CR_hwmask 0x0000000F -#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask) - -// interrupt register for stimulating interrupts -#define IFX_SSC_IRN_ICR 0xFC -// read/write -#define IFX_SSC_IRN_ICR_readmask 0x0000000F -#define IFX_SSC_IRN_ICR_writemask 0x0000000F -#define IFX_SSC_IRN_ICR_hwmask 0x00000000 -#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask) - -//--------------------------------------------------------------------- -// Number of IRQs and bitposition of IRQ -#define IFX_SSC_NUM_IRQ 4 -#define IFX_SSC_T_BIT 0x00000001 -#define IFX_SSC_R_BIT 0x00000002 -#define IFX_SSC_E_BIT 0x00000004 -#define IFX_SSC_F_BIT 0x00000008 - -/* bit masks for SSC registers */ - -/* ID register */ -#define IFX_SSC_PERID_REV_MASK 0x0000001F -#define IFX_SSC_PERID_CFG_MASK 0x00000020 -#define IFX_SSC_PERID_ID_MASK 0x0000FF00 -#define IFX_SSC_PERID_REV_OFFSET 0 -#define IFX_SSC_PERID_CFG_OFFSET 5 -#define IFX_SSC_PERID_ID_OFFSET 8 -#define IFX_SSC_PERID_ID 0x45 -#define IFX_SSC_PERID_DMA_ON 0x00000020 -#define IFX_SSC_PERID_RXFS_MASK 0x003F0000 -#define IFX_SSC_PERID_RXFS_OFFSET 16 -#define IFX_SSC_PERID_TXFS_MASK 0x3F000000 -#define IFX_SSC_PERID_TXFS_OFFSET 24 - -/* PISEL register */ -#define IFX_SSC_PISEL_MASTER_IN_A 0x0000 -#define IFX_SSC_PISEL_MASTER_IN_B 0x0001 -#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000 -#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002 -#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000 -#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004 - -/* IFX_SSC_CON register */ -#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000 -#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000 -#define IFX_SSC_CON_IDLE_HIGH 0x00800000 -#define IFX_SSC_CON_IDLE_LOW 0x00000000 -#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000 -#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000 -#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16 -#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000 -#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK) - -#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000 -#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000 - -#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000 -#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000 -#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800 -#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000 -#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400 -#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000 -#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200 -#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000 -#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100 -#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000 -#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00 -#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000 - -#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080 -#define IFX_SSC_CON_NO_LOOPBACK 0x00000000 -#define IFX_SSC_CON_HALF_DUPLEX 0x00000080 -#define IFX_SSC_CON_FULL_DUPLEX 0x00000000 -#define IFX_SSC_CON_CLOCK_FALL 0x00000040 -#define IFX_SSC_CON_CLOCK_RISE 0x00000000 -#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000 -#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020 -#define IFX_SSC_CON_MSB_FIRST 0x00000010 -#define IFX_SSC_CON_LSB_FIRST 0x00000000 -#define IFX_SSC_CON_ENABLE_CSB 0x00000008 -#define IFX_SSC_CON_DISABLE_CSB 0x00000000 -#define IFX_SSC_CON_INVERT_CSB 0x00000004 -#define IFX_SSC_CON_TRUE_CSB 0x00000000 -#define IFX_SSC_CON_RX_OFF 0x00000002 -#define IFX_SSC_CON_RX_ON 0x00000000 -#define IFX_SSC_CON_TX_OFF 0x00000001 -#define IFX_SSC_CON_TX_ON 0x00000000 - -/* IFX_SSC_STATE register */ -#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28 -#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000 -#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET) -#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24 -#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000 -#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET) -#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16 -#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000 -#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1) -#define IFX_SSC_STATE_BUSY 0x00002000 -#define IFX_SSC_STATE_RX_UFL 0x00001000 -#define IFX_SSC_STATE_TX_UFL 0x00000800 -#define IFX_SSC_STATE_ABORT_ERR 0x00000400 -#define IFX_SSC_STATE_RX_OFL 0x00000200 -#define IFX_SSC_STATE_TX_OFL 0x00000100 -#define IFX_SSC_STATE_MODE_ERR 0x00000080 -#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004 -#define IFX_SSC_STATE_IS_MASTER 0x00000002 -#define IFX_SSC_STATE_IS_ENABLED 0x00000001 - -/* WHBSTATE register */ -#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001 -#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001 -#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001 - -#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002 -#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002 -#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002 - -#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004 -#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004 - -#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008 -#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008 - -#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010 -#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020 - -#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040 -#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080 - -#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100 -#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200 -#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400 -#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800 -#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000 -#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000 -#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000 -#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000 -#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50 -#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0 - -/* BR register */ -#define IFX_SSC_BR_BAUDRATE_OFFSET 0 -#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF - -/* BR_STAT register */ -#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0 -#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF - -/* TB register */ -#define IFX_SSC_TB_DATA_OFFSET 0 -#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF - -/* RB register */ -#define IFX_SSC_RB_DATA_OFFSET 0 -#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF - -/* RXFCON and TXFCON registers */ -#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000 -#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001 -#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002 -#define IFX_SSC_XFCON_ITL_MASK 0x00003F00 -#define IFX_SSC_XFCON_ITL_OFFSET 8 - -/* FSTAT register */ -#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0 -#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F -#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8 -#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00 - -/* GPOCON register */ -#define IFX_SSC_GPOCON_INVOUT0_POS 0 -#define IFX_SSC_GPOCON_INV_OUT0 0x00000001 -#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000 -#define IFX_SSC_GPOCON_INVOUT1_POS 1 -#define IFX_SSC_GPOCON_INV_OUT1 0x00000002 -#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000 -#define IFX_SSC_GPOCON_INVOUT2_POS 2 -#define IFX_SSC_GPOCON_INV_OUT2 0x00000003 -#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000 -#define IFX_SSC_GPOCON_INVOUT3_POS 3 -#define IFX_SSC_GPOCON_INV_OUT3 0x00000008 -#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000 -#define IFX_SSC_GPOCON_INVOUT4_POS 4 -#define IFX_SSC_GPOCON_INV_OUT4 0x00000010 -#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000 -#define IFX_SSC_GPOCON_INVOUT5_POS 5 -#define IFX_SSC_GPOCON_INV_OUT5 0x00000020 -#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000 -#define IFX_SSC_GPOCON_INVOUT6_POS 6 -#define IFX_SSC_GPOCON_INV_OUT6 0x00000040 -#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000 -#define IFX_SSC_GPOCON_INVOUT7_POS 7 -#define IFX_SSC_GPOCON_INV_OUT7 0x00000080 -#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000 -#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF -#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000 - -#define IFX_SSC_GPOCON_ISCSB0_POS 8 -#define IFX_SSC_GPOCON_IS_CSB0 0x00000100 -#define IFX_SSC_GPOCON_IS_GPO0 0x00000000 -#define IFX_SSC_GPOCON_ISCSB1_POS 9 -#define IFX_SSC_GPOCON_IS_CSB1 0x00000200 -#define IFX_SSC_GPOCON_IS_GPO1 0x00000000 -#define IFX_SSC_GPOCON_ISCSB2_POS 10 -#define IFX_SSC_GPOCON_IS_CSB2 0x00000400 -#define IFX_SSC_GPOCON_IS_GPO2 0x00000000 -#define IFX_SSC_GPOCON_ISCSB3_POS 11 -#define IFX_SSC_GPOCON_IS_CSB3 0x00000800 -#define IFX_SSC_GPOCON_IS_GPO3 0x00000000 -#define IFX_SSC_GPOCON_ISCSB4_POS 12 -#define IFX_SSC_GPOCON_IS_CSB4 0x00001000 -#define IFX_SSC_GPOCON_IS_GPO4 0x00000000 -#define IFX_SSC_GPOCON_ISCSB5_POS 13 -#define IFX_SSC_GPOCON_IS_CSB5 0x00002000 -#define IFX_SSC_GPOCON_IS_GPO5 0x00000000 -#define IFX_SSC_GPOCON_ISCSB6_POS 14 -#define IFX_SSC_GPOCON_IS_CSB6 0x00004000 -#define IFX_SSC_GPOCON_IS_GPO6 0x00000000 -#define IFX_SSC_GPOCON_ISCSB7_POS 15 -#define IFX_SSC_GPOCON_IS_CSB7 0x00008000 -#define IFX_SSC_GPOCON_IS_GPO7 0x00000000 -#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00 -#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000 - -/* GPOSTAT register */ -#define IFX_SSC_GPOSTAT_OUT0 0x00000001 -#define IFX_SSC_GPOSTAT_OUT1 0x00000002 -#define IFX_SSC_GPOSTAT_OUT2 0x00000004 -#define IFX_SSC_GPOSTAT_OUT3 0x00000008 -#define IFX_SSC_GPOSTAT_OUT4 0x00000010 -#define IFX_SSC_GPOSTAT_OUT5 0x00000020 -#define IFX_SSC_GPOSTAT_OUT6 0x00000040 -#define IFX_SSC_GPOSTAT_OUT7 0x00000080 -#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF - -/* WHBGPOSTAT register */ -#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001 -#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002 -#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004 -#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008 -#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010 -#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020 -#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040 -#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF - -#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0 -#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1 -#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2 -#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3 -#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4 -#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5 -#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6 -#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7 - -#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8 -#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100 -#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9 -#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200 -#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10 -#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400 -#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11 -#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800 -#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12 -#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000 -#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13 -#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000 -#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14 -#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000 -#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15 -#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000 -#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00 - -/* SFCON register */ -#define IFX_SSC_SFCON_SF_ENABLE 0x00000001 -#define IFX_SSC_SFCON_SF_DISABLE 0x00000000 -#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004 -#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000 -#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008 -#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000 -#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0 -#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4 -#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000 -#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16 -#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000 -#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000 -#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18 -#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000 -#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000 -#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000 -#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000 -#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22 -#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096 -#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024 - -#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET) -#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) -#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK) -#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) - -/* SFSTAT register */ -#define IFX_SSC_SFSTAT_IN_DATA 0x00000001 -#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002 -#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0 -#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4 -#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000 -#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20 - -#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET) -#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET) - -/* RXREQ register */ -#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF -#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0 - -/* RXCNT register */ -#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF -#define IFX_SSC_RXCNT_TODO_OFFSET 0 - -/* DMACON register */ -#define IFX_SSC_DMACON_RXON 0x00000001 -#define IFX_SSC_DMACON_RXOFF 0x00000000 -#define IFX_SSC_DMACON_TXON 0x00000002 -#define IFX_SSC_DMACON_TXOFF 0x00000000 -#define IFX_SSC_DMACON_DMAON 0x00000003 -#define IFX_SSC_DMACON_DMAOFF 0x00000000 -#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C -#define IFX_SSC_DMACON_CLASS_OFFSET 2 - -/* register access macros */ -#define ifx_ssc_fstat_received_words(status) (status & 0x003F) -#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8) - -#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE)) -#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON)) -#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON)) -#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE)) -#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB)) -#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB)) -#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT)) -#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR)) - -#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET) -#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h deleted file mode 100644 index 2180f44394..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h +++ /dev/null @@ -1,515 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 infineon - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_H__ -#define _IFXMIPS_H__ - -#define ifxmips_r32(reg) __raw_readl(reg) -#define ifxmips_w32(val,reg) __raw_writel(val,reg) -#define ifxmips_w32_mask(clear,set,reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg) - -/*------------ GENERAL */ - -#define BOARD_SYSTEM_TYPE "IFXMIPS" - -#define IOPORT_RESOURCE_START 0x10000000 -#define IOPORT_RESOURCE_END 0xffffffff -#define IOMEM_RESOURCE_START 0x10000000 -#define IOMEM_RESOURCE_END 0xffffffff - -#define IFXMIPS_FLASH_START 0x10000000 -#define IFXMIPS_FLASH_MAX 0x2000000 - - -/*------------ ASC1 */ - -#define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400) -#define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400) - -#define IFXMIPS_ASC_FSTAT 0x0048 -#define IFXMIPS_ASC_TBUF 0x0020 -#define IFXMIPS_ASC_WHBSTATE 0x0018 -#define IFXMIPS_ASC_RBUF 0x0024 -#define IFXMIPS_ASC_STATE 0x0014 -#define IFXMIPS_ASC_IRNCR 0x00F8 -#define IFXMIPS_ASC_CLC 0x0000 -#define IFXMIPS_ASC_PISEL 0x0004 -#define IFXMIPS_ASC_TXFCON 0x0044 -#define IFXMIPS_ASC_RXFCON 0x0040 -#define IFXMIPS_ASC_CON 0x0010 -#define IFXMIPS_ASC_BG 0x0050 -#define IFXMIPS_ASC_IRNREN 0x00F4 - -#define IFXMIPS_ASC_CLC_DISS 0x2 -#define ASC_IRNREN_RX_BUF 0x8 -#define ASC_IRNREN_TX_BUF 0x4 -#define ASC_IRNREN_ERR 0x2 -#define ASC_IRNREN_TX 0x1 -#define ASC_IRNCR_TIR 0x4 -#define ASC_IRNCR_RIR 0x2 -#define ASC_IRNCR_EIR 0x4 -#define ASCOPT_CSIZE 0x3 -#define ASCOPT_CS7 0x1 -#define ASCOPT_CS8 0x2 -#define ASCOPT_PARENB 0x4 -#define ASCOPT_STOPB 0x8 -#define ASCOPT_PARODD 0x0 -#define ASCOPT_CREAD 0x20 -#define TXFIFO_FL 1 -#define RXFIFO_FL 1 -#define TXFIFO_FULL 16 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 -#define ASCCON_M_8ASYNC 0x0 -#define ASCCON_M_7ASYNC 0x2 -#define ASCCON_ODD 0x00000020 -#define ASCCON_STP 0x00000080 -#define ASCCON_BRS 0x00000100 -#define ASCCON_FDE 0x00000200 -#define ASCCON_R 0x00008000 -#define ASCCON_FEN 0x00020000 -#define ASCCON_ROEN 0x00080000 -#define ASCCON_TOEN 0x00100000 -#define ASCSTATE_PE 0x00010000 -#define ASCSTATE_FE 0x00020000 -#define ASCSTATE_ROE 0x00080000 -#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) -#define ASCWHBSTATE_CLRREN 0x00000001 -#define ASCWHBSTATE_SETREN 0x00000002 -#define ASCWHBSTATE_CLRPE 0x00000004 -#define ASCWHBSTATE_CLRFE 0x00000008 -#define ASCWHBSTATE_CLRROE 0x00000020 -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - - - -/*------------ RCU */ -#define IFXMIPS_RCU_BASE_ADDR 0xBF203000 - -/* reset request */ -#define IFXMIPS_RCU_RST ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010)) -#define IFXMIPS_RCU_RST_CPU1 (1 << 3) -#define IFXMIPS_RCU_RST_ALL 0x40000000 - -#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7) -#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11) -#define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20) - - -/*------------ GPTU */ - -#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300 - -/* clock control register */ -#define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000)) - -/* captur reload register */ -#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030)) - -/* timer 6 control register */ -#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020)) - - -/*------------ EBU */ - -#define IFXMIPS_EBU_BASE_ADDR 0xBE105300 - -/* bus configuration register */ -#define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060)) -#define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090)) -#define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4)) -#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0)) - - -/*------------ CGU */ -#define IFXMIPS_CGU_BASE_ADDR (KSEG1 + 0x1F103000) -#define IFXMIPS_CGU_PLL0_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0004)) -#define IFXMIPS_CGU_PLL1_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0008)) -#define IFXMIPS_CGU_PLL2_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x000C)) -#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) -#define IFXMIPS_CGU_UPDATE ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0014)) -#define IFXMIPS_CGU_IF_CLK ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) -#define IFXMIPS_CGU_OSC_CON ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x001C)) -#define IFXMIPS_CGU_SMD ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0020)) -#define IFXMIPS_CGU_CT1SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0028)) -#define IFXMIPS_CGU_CT2SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x002C)) -#define IFXMIPS_CGU_PCMCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0030)) -#define IFXMIPS_CGU_PCI_CR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) -#define IFXMIPS_CGU_PD_PC ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0038)) -#define IFXMIPS_CGU_FMR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x003C)) - -/* clock mux */ -#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) -#define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) -#define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) - -#define CLOCK_60M 60000000 -#define CLOCK_83M 83333333 -#define CLOCK_111M 111111111 -#define CLOCK_133M 133333333 -#define CLOCK_167M 166666667 -#define CLOCK_333M 333333333 - - -/*------------ CGU */ - -#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000) - -#define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C)) -#define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020)) - - -/*------------ ICU */ - -#define IFXMIPS_ICU_BASE_ADDR 0xBF880200 - - -#define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000)) -#define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008)) -#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010)) -#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018)) -#define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020)) - -#define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028)) -#define IFXMIPS_ICU_IM2_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0058)) -#define IFXMIPS_ICU_IM5_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00D0)) - -#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR) - - -/*------------ ETOP */ - -#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000 - -#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 - -#define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000)) -#define IFXMIPS_PPE32_SRST ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10080)) - -#define MII_MODE 1 -#define REV_MII_MODE 2 - -/* mdio access */ -#define IFXMIPS_PPE32_MDIO_CFG ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11800)) -#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11804)) - -#define MDIO_ACC_REQUEST 0x80000000 -#define MDIO_ACC_READ 0x40000000 -#define MDIO_ACC_ADDR_MASK 0x1f -#define MDIO_ACC_ADDR_OFFSET 0x15 -#define MDIO_ACC_REG_MASK 0xff -#define MDIO_ACC_REG_OFFSET 0x10 -#define MDIO_ACC_VAL_MASK 0xffff - -/* configuration */ -#define IFXMIPS_PPE32_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1808)) - -#define PPE32_MII_MASK 0xfffffffc -#define PPE32_MII_NORMAL 0x8 -#define PPE32_MII_REVERSE 0xe - -/* packet length */ -#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1820)) - -#define PPE32_PLEN_OVER 0x5ee -#define PPE32_PLEN_UNDER 0x400000 - -/* enet */ -#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840)) - -#define PPE32_CGEN 0x800 - - -/*------------ DMA */ -#define IFXMIPS_DMA_BASE_ADDR 0xBE104100 - -#define IFXMIPS_DMA_CS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x18)) -#define IFXMIPS_DMA_CIE ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x2C)) -#define IFXMIPS_DMA_IRNEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0xf4)) -#define IFXMIPS_DMA_CCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x1C)) -#define IFXMIPS_DMA_CIS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x28)) -#define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24)) -#define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40)) -#define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44)) -#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10)) -#define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14)) -#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20)) - - -/*------------ PCI */ -#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400) - -#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0)) -#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4)) -#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8)) -#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC)) -#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0)) -#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4)) -#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8)) -#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC)) -#define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000)) -#define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030)) -#define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080)) -#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4)) -#define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044)) -#define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048)) -#define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C)) -#define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010)) -#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064)) -#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8)) -#define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C)) - -#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000) - -#define PCI_CS_STS_CMD ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004)) - -#define PCI_MASTER0_REQ_MASK_2BITS 8 -#define PCI_MASTER1_REQ_MASK_2BITS 10 -#define PCI_MASTER2_REQ_MASK_2BITS 12 -#define INTERNAL_ARB_ENABLE_BIT 0 - - -/*------------ WDT */ - -#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000) - -#define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0)) -#define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8)) - - -/*------------ LED */ - -#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0) -#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000)) -#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004)) -#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008)) -#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C)) -#define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010)) - -#define LED_CON0_SWU (1 << 31) -#define LED_CON0_AD1 (1 << 25) -#define LED_CON0_AD0 (1 << 24) - -#define IFXMIPS_LED_2HZ (0) -#define IFXMIPS_LED_4HZ (1 << 23) -#define IFXMIPS_LED_8HZ (2 << 23) -#define IFXMIPS_LED_10HZ (3 << 23) -#define IFXMIPS_LED_MASK (0xf << 23) - -#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31) -#define IFXMIPS_LED_UPD_MASK (3 << 30) -#define IFXMIPS_LED_ADSL_SRC (3 << 24) - -#define IFXMIPS_LED_GROUP0 (1 << 0) -#define IFXMIPS_LED_GROUP1 (1 << 1) -#define IFXMIPS_LED_GROUP2 (1 << 2) - -#define IFXMIPS_LED_RISING 0 -#define IFXMIPS_LED_FALLING (1 << 26) -#define IFXMIPS_LED_EDGE_MASK (1 << 26) - - -/*------------ GPIO */ - -#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00) - -#define IFXMIPS_GPIO_P0_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0010)) -#define IFXMIPS_GPIO_P1_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0040)) -#define IFXMIPS_GPIO_P0_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0014)) -#define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044)) -#define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018)) -#define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048)) -#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) -#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) -#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) -#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) -#define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024)) -#define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054)) -#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) -#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) -#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) -#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) -#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) -#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) - - -/*------------ SSC */ - -#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800) - - -#define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000)) -#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4)) -#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060)) -#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078)) -#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014)) -#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018)) -#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038)) -#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008)) -#define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020)) -#define IFXMIPS_SSC_RXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0030)) -#define IFXMIPS_SSC_TXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0034)) -#define IFXMIPS_SSC_CON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0010)) -#define IFXMIPS_SSC_GPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0074)) -#define IFXMIPS_SSC_RB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0024)) -#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) -#define IFXMIPS_SSC_GPOCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0070)) -#define IFXMIPS_SSC_BR ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0040)) -#define IFXMIPS_SSC_RXREQ ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0080)) -#define IFXMIPS_SSC_SFSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0064)) -#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) - - -/*------------ MEI */ - -#define IFXMIPS_MEI_BASE_ADDR (0xBE116000) - -#define MEI_DATA_XFR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0000)) -#define MEI_VERSION ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0004)) -#define MEI_ARC_GP_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0008)) -#define MEI_DATA_XFR_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x000C)) -#define MEI_XFR_ADDR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0010)) -#define MEI_MAX_WAIT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0014)) -#define MEI_TO_ARC_INT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0018)) -#define ARC_TO_MEI_INT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x001C)) -#define ARC_TO_MEI_INT_MASK ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0020)) -#define MEI_DEBUG_WAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0024)) -#define MEI_DEBUG_RAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0028)) -#define MEI_DEBUG_DATA ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x002C)) -#define MEI_DEBUG_DEC ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0030)) -#define MEI_CONFIG ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0034)) -#define MEI_RST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0038)) -#define MEI_DBG_MASTER ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x003C)) -#define MEI_CLK_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0040)) -#define MEI_BIST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0044)) -#define MEI_BIST_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0048)) -#define MEI_XDATA_BASE_SH ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x004c)) -#define MEI_XDATA_BASE ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0050)) -#define MEI_XMEM_BAR_BASE ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) -#define MEI_XMEM_BAR0 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) -#define MEI_XMEM_BAR1 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0058)) -#define MEI_XMEM_BAR2 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x005C)) -#define MEI_XMEM_BAR3 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0060)) -#define MEI_XMEM_BAR4 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0064)) -#define MEI_XMEM_BAR5 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0068)) -#define MEI_XMEM_BAR6 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x006C)) -#define MEI_XMEM_BAR7 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0070)) -#define MEI_XMEM_BAR8 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0074)) -#define MEI_XMEM_BAR9 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0078)) -#define MEI_XMEM_BAR10 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x007C)) -#define MEI_XMEM_BAR11 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0080)) -#define MEI_XMEM_BAR12 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0084)) -#define MEI_XMEM_BAR13 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0088)) -#define MEI_XMEM_BAR14 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x008C)) -#define MEI_XMEM_BAR15 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0090)) -#define MEI_XMEM_BAR16 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094)) - - -/*------------ DEU */ - -#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100) -#define IFXMIPS_DEU_CLK ((u32 *)(IFXMIPS_DEU_BASE + 0x0000)) -#define IFXMIPS_DEU_ID ((u32 *)(IFXMIPS_DEU_BASE + 0x0008)) - -#define IFXMIPS_DES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0010)) -#define IFXMIPS_DES_IHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0014)) -#define IFXMIPS_DES_ILR ((u32 *)(IFXMIPS_DEU_BASE + 0x0018)) -#define IFXMIPS_DES_K1HR ((u32 *)(IFXMIPS_DEU_BASE + 0x001C)) -#define IFXMIPS_DES_K1LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0020)) -#define IFXMIPS_DES_K3HR ((u32 *)(IFXMIPS_DEU_BASE + 0x0024)) -#define IFXMIPS_DES_K3LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0028)) -#define IFXMIPS_DES_IVHR ((u32 *)(IFXMIPS_DEU_BASE + 0x002C)) -#define IFXMIPS_DES_IVLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0030)) -#define IFXMIPS_DES_OHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0040)) -#define IFXMIPS_DES_OLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0050)) -#define IFXMIPS_AES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0050)) -#define IFXMIPS_AES_ID3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0054)) -#define IFXMIPS_AES_ID2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0058)) -#define IFXMIPS_AES_ID1R ((u32 *)(IFXMIPS_DEU_BASE + 0x005C)) -#define IFXMIPS_AES_ID0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0060)) -#define IFXMIPS_AES_K7R ((u32 *)(IFXMIPS_DEU_BASE + 0x0064)) -#define IFXMIPS_AES_K6R ((u32 *)(IFXMIPS_DEU_BASE + 0x0068)) -#define IFXMIPS_AES_K5R ((u32 *)(IFXMIPS_DEU_BASE + 0x006C)) -#define IFXMIPS_AES_K4R ((u32 *)(IFXMIPS_DEU_BASE + 0x0070)) -#define IFXMIPS_AES_K3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0074)) -#define IFXMIPS_AES_K2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0078)) -#define IFXMIPS_AES_K1R ((u32 *)(IFXMIPS_DEU_BASE + 0x007C)) -#define IFXMIPS_AES_K0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0080)) -#define IFXMIPS_AES_IV3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0084)) -#define IFXMIPS_AES_IV2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0088)) -#define IFXMIPS_AES_IV1R ((u32 *)(IFXMIPS_DEU_BASE + 0x008C)) -#define IFXMIPS_AES_IV0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0090)) -#define IFXMIPS_AES_0D3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0094)) -#define IFXMIPS_AES_0D2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0098)) -#define IFXMIPS_AES_OD1R ((u32 *)(IFXMIPS_DEU_BASE + 0x009C)) -#define IFXMIPS_AES_OD0R ((u32 *)(IFXMIPS_DEU_BASE + 0x00A0)) - -/*------------ FUSE */ - -#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354) - - -/*------------ MPS */ - -#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000) -#define IFXMIPS_MPS_SRAM ((u32*)(KSEG1 + 0x1F200000)) - -#define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344)) -#define IFXMIPS_MPS_VC0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0000)) -#define IFXMIPS_MPS_VC1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0004)) -#define IFXMIPS_MPS_VC2ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0008)) -#define IFXMIPS_MPS_VC3ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x000C)) -#define IFXMIPS_MPS_RVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0010)) -#define IFXMIPS_MPS_RVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0014)) -#define IFXMIPS_MPS_RVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0018)) -#define IFXMIPS_MPS_RVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x001C)) -#define IFXMIPS_MPS_SVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0020)) -#define IFXMIPS_MPS_SVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0024)) -#define IFXMIPS_MPS_SVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0028)) -#define IFXMIPS_MPS_SVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x002C)) -#define IFXMIPS_MPS_CVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0030)) -#define IFXMIPS_MPS_CVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0034)) -#define IFXMIPS_MPS_CVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0038)) -#define IFXMIPS_MPS_CVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x003C)) -#define IFXMIPS_MPS_RAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0040)) -#define IFXMIPS_MPS_RAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0044)) -#define IFXMIPS_MPS_SAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0048)) -#define IFXMIPS_MPS_SAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x004C)) -#define IFXMIPS_MPS_CAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0050)) -#define IFXMIPS_MPS_CAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0054)) -#define IFXMIPS_MPS_AD0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058)) -#define IFXMIPS_MPS_AD1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C)) - -#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -#define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h deleted file mode 100644 index 899bbbca3e..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_CGU_H__ -#define _IFXMIPS_CGU_H__ - -unsigned int cgu_get_mips_clock(int cpu); -unsigned int cgu_get_io_region_clock(void); -unsigned int cgu_get_fpi_bus_clock(int fpi); -void cgu_setup_pci_clk(int internal_clock); -unsigned int ifxmips_get_ddr_hz(void); -unsigned int ifxmips_get_fpi_hz(void); -unsigned int ifxmips_get_cpu_hz(void); - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h deleted file mode 100644 index 02c7aec539..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 infineon - * Copyright (C) 2007 John Crispin - * - */ -#ifndef _IFXMIPS_DMA_H__ -#define _IFXMIPS_DMA_H__ - -#define RCV_INT 1 -#define TX_BUF_FULL_INT 2 -#define TRANSMIT_CPT_INT 4 -#define IFXMIPS_DMA_CH_ON 1 -#define IFXMIPS_DMA_CH_OFF 0 -#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100 - -enum attr_t{ - TX = 0, - RX = 1, - RESERVED = 2, - DEFAULT = 3, -}; - -#define DMA_OWN 1 -#define CPU_OWN 0 -#define DMA_MAJOR 250 - -#define DMA_DESC_OWN_CPU 0x0 -#define DMA_DESC_OWN_DMA 0x80000000 -#define DMA_DESC_CPT_SET 0x40000000 -#define DMA_DESC_SOP_SET 0x20000000 -#define DMA_DESC_EOP_SET 0x10000000 - -#define MISCFG_MASK 0x40 -#define RDERR_MASK 0x20 -#define CHOFF_MASK 0x10 -#define DESCPT_MASK 0x8 -#define DUR_MASK 0x4 -#define EOP_MASK 0x2 - -#define DMA_DROP_MASK (1<<31) - -#define IFXMIPS_DMA_RX -1 -#define IFXMIPS_DMA_TX 1 - -typedef struct dma_chan_map { - char dev_name[15]; - enum attr_t dir; - int pri; - int irq; - int rel_chan_no; -} _dma_chan_map; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -typedef struct rx_desc{ - u32 data_length:16; - volatile u32 reserved:7; - volatile u32 byte_offset:2; - volatile u32 Burst_length_offset:3; - volatile u32 EoP:1; - volatile u32 Res:1; - volatile u32 C:1; - volatile u32 OWN:1; - volatile u32 Data_Pointer; - /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/ -}_rx_desc; - -typedef struct tx_desc{ - volatile u32 data_length:16; - volatile u32 reserved1:7; - volatile u32 byte_offset:5; - volatile u32 EoP:1; - volatile u32 SoP:1; - volatile u32 C:1; - volatile u32 OWN:1; - volatile u32 Data_Pointer;//fix me:should be 28 bits here -}_tx_desc; -#else //BIG -typedef struct rx_desc{ - union - { - struct - { - volatile u32 OWN:1; - volatile u32 C:1; - volatile u32 SoP:1; - volatile u32 EoP:1; - volatile u32 Burst_length_offset:3; - volatile u32 byte_offset:2; - volatile u32 reserve:7; - volatile u32 data_length:16; - }field; - volatile u32 word; - }status; - volatile u32 Data_Pointer; -}_rx_desc; - -typedef struct tx_desc{ - union - { - struct - { - volatile u32 OWN:1; - volatile u32 C:1; - volatile u32 SoP:1; - volatile u32 EoP:1; - volatile u32 byte_offset:5; - volatile u32 reserved:7; - volatile u32 data_length:16; - }field; - volatile u32 word; - }status; - volatile u32 Data_Pointer; -}_tx_desc; -#endif //ENDIAN - -typedef struct dma_channel_info{ - /*relative channel number*/ - int rel_chan_no; - /*class for this channel for QoS*/ - int pri; - /*specify byte_offset*/ - int byte_offset; - /*direction*/ - int dir; - /*irq number*/ - int irq; - /*descriptor parameter*/ - int desc_base; - int desc_len; - int curr_desc; - int prev_desc;/*only used if it is a tx channel*/ - /*weight setting for WFQ algorithm*/ - int weight; - int default_weight; - int packet_size; - int burst_len; - /*on or off of this channel*/ - int control; - /**optional information for the upper layer devices*/ -#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA) - void* opt[64]; -#else - void* opt[25]; -#endif - /*Pointer to the peripheral device who is using this channel*/ - void* dma_dev; - /*channel operations*/ - void (*open)(struct dma_channel_info* pCh); - void (*close)(struct dma_channel_info* pCh); - void (*reset)(struct dma_channel_info* pCh); - void (*enable_irq)(struct dma_channel_info* pCh); - void (*disable_irq)(struct dma_channel_info* pCh); -}_dma_channel_info; - -typedef struct dma_device_info{ - /*device name of this peripheral*/ - char device_name[15]; - int reserved; - int tx_burst_len; - int rx_burst_len; - int default_weight; - int current_tx_chan; - int current_rx_chan; - int num_tx_chan; - int num_rx_chan; - int max_rx_chan_num; - int max_tx_chan_num; - _dma_channel_info* tx_chan[20]; - _dma_channel_info* rx_chan[20]; - /*functions, optional*/ - u8* (*buffer_alloc)(int len,int* offset, void** opt); - void (*buffer_free)(u8* dataptr, void* opt); - int (*intr_handler)(struct dma_device_info* info, int status); - void * priv; /* used by peripheral driver only */ -}_dma_device_info; - -_dma_device_info* dma_device_reserve(char* dev_name); - -void dma_device_release(_dma_device_info* dev); - -void dma_device_register(_dma_device_info* info); - -void dma_device_unregister(_dma_device_info* info); - -int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt); - -int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt); -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ebu.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ebu.h deleted file mode 100644 index f9278ed15f..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ebu.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_EBU_H__ -#define _IFXMIPS_EBU_H__ - -extern spinlock_t ebu_lock; - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h deleted file mode 100644 index 237db01ec4..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_GPIO_H__ -#define _IFXMIPS_GPIO_H__ - -extern int ifxmips_port_reserve_pin (unsigned int port, unsigned int pin); -extern int ifxmips_port_free_pin (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_open_drain (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_open_drain (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_pudsel (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_puden (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_puden (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_stoff (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_stoff (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_dir_out (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_dir_in (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_output (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_output (unsigned int port, unsigned int pin); -extern int ifxmips_port_get_input (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_altsel0 (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_altsel0 (unsigned int port, unsigned int pin); -extern int ifxmips_port_set_altsel1 (unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_altsel1 (unsigned int port, unsigned int pin); - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h deleted file mode 100644 index 6ad4cc58ca..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h +++ /dev/null @@ -1,161 +0,0 @@ -#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ - - -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - - -/* - * #################################### - * Definition - * #################################### - */ - -/* - * Available Timer/Counter Index - */ -#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) -#define TIMER_ANY 0x00 -#define TIMER1A TIMER(1, 0) -#define TIMER1B TIMER(1, 1) -#define TIMER2A TIMER(2, 0) -#define TIMER2B TIMER(2, 1) -#define TIMER3A TIMER(3, 0) -#define TIMER3B TIMER(3, 1) - -/* - * Flag of Timer/Counter - * These flags specify the way in which timer is configured. - */ -/* Bit size of timer/counter. */ -#define TIMER_FLAG_16BIT 0x0000 -#define TIMER_FLAG_32BIT 0x0001 -/* Switch between timer and counter. */ -#define TIMER_FLAG_TIMER 0x0000 -#define TIMER_FLAG_COUNTER 0x0002 -/* Stop or continue when overflowing/underflowing. */ -#define TIMER_FLAG_ONCE 0x0000 -#define TIMER_FLAG_CYCLIC 0x0004 -/* Count up or counter down. */ -#define TIMER_FLAG_UP 0x0000 -#define TIMER_FLAG_DOWN 0x0008 -/* Count on specific level or edge. */ -#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 -#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 -#define TIMER_FLAG_RISE_EDGE 0x0010 -#define TIMER_FLAG_FALL_EDGE 0x0020 -#define TIMER_FLAG_ANY_EDGE 0x0030 -/* Signal is syncronous to module clock or not. */ -#define TIMER_FLAG_UNSYNC 0x0000 -#define TIMER_FLAG_SYNC 0x0080 -/* Different interrupt handle type. */ -#define TIMER_FLAG_NO_HANDLE 0x0000 -#if defined(__KERNEL__) - #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 -#endif // defined(__KERNEL__) -#define TIMER_FLAG_SIGNAL 0x0300 -/* Internal clock source or external clock source */ -#define TIMER_FLAG_INT_SRC 0x0000 -#define TIMER_FLAG_EXT_SRC 0x1000 - - -/* - * ioctl Command - */ -#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ -#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ -#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ -#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ -#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ -#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ -#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ -#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ - -/* - * Data Type Used to Call ioctl - */ -struct gptu_ioctl_param { - unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * - * GPTU_SET_COUNTER, this field is ID of expected * - * timer/counter. If it's zero, a timer/counter would * - * be dynamically allocated and ID would be stored in * - * this field. * - * In command GPTU_GET_COUNT_VALUE, this field is * - * ignored. * - * In other command, this field is ID of timer/counter * - * allocated. */ - unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * - * GPTU_SET_COUNTER, this field contains flags to * - * specify how to configure timer/counter. * - * In command GPTU_START_TIMER, zero indicate start * - * and non-zero indicate resume timer/counter. * - * In other command, this field is ignored. */ - unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * - * init/reload value. * - * In command GPTU_SET_TIMER, this field contains * - * frequency (0.001Hz) of timer. * - * In command GPTU_GET_COUNT_VALUE, current count * - * value would be stored in this field. * - * In command GPTU_CALCULATE_DIVIDER, this field * - * contains frequency wanted, and after calculation, * - * divider would be stored in this field to overwrite * - * the frequency. * - * In other command, this field is ignored. */ - int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * - * if signal is required, this field contains process * - * ID to which signal would be sent. * - * In other command, this field is ignored. */ - int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * - * if signal is required, this field contains signal * - * number which would be sent. * - * In other command, this field is ignored. */ -}; - -/* - * #################################### - * Data Type - * #################################### - */ -typedef void (*timer_callback)(unsigned long arg); - - -#if defined(__KERNEL__) - extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); - extern int ifxmips_free_timer(unsigned int); - extern int ifxmips_start_timer(unsigned int, int); - extern int ifxmips_stop_timer(unsigned int); - extern int ifxmips_reset_counter_flags(u32 timer, u32 flags); - extern int ifxmips_get_count_value(unsigned int, unsigned long *); - - extern u32 cal_divider(unsigned long); - - extern int set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -extern int set_counter (unsigned int timer, unsigned int flag, u32 reload, unsigned long arg1, unsigned long arg2); -// extern int set_counter(unsigned int, int, int, int, unsigned int, unsigned int, unsigned long, unsigned long); -#endif // defined(__KERNEL__) - - -#endif // __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h deleted file mode 100644 index 694a646e86..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 infineon - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_IRQ__ -#define _IFXMIPS_IRQ__ - -#define INT_NUM_IRQ0 8 -#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) -#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) -#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) -#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) -#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) -#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) - -#define IFXMIPSASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 7)) -#define IFXMIPSASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 2) -#define IFXMIPSASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 3) - -#define IFXMIPS_SSC_TIR (INT_NUM_IM0_IRL0 + 15) -#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14) -#define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16) - -#define IFXMIPS_MEI_INT (INT_NUM_IM1_IRL0 + 23) - -#define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) -#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) - -#define MIPS_CPU_TIMER_IRQ 7 - -#define IFXMIPS_DMA_CH0_INT (INT_NUM_IM2_IRL0) -#define IFXMIPS_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) -#define IFXMIPS_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) -#define IFXMIPS_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) -#define IFXMIPS_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) -#define IFXMIPS_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) -#define IFXMIPS_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) -#define IFXMIPS_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) -#define IFXMIPS_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) -#define IFXMIPS_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) -#define IFXMIPS_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) -#define IFXMIPS_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) -#define IFXMIPS_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) -#define IFXMIPS_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) -#define IFXMIPS_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) -#define IFXMIPS_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) -#define IFXMIPS_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) -#define IFXMIPS_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) -#define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) -#define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) - -#define IFXMIPS_USB_INT (INT_NUM_IM4_IRL0 + 22) -#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) - - -extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr); - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h deleted file mode 100644 index 5e0d7f3e1d..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_LED_H__ -#define _IFXMIPS_LED_H__ - -extern void ifxmips_led_set(unsigned int led); -extern void ifxmips_led_clear(unsigned int led); -extern void ifxmips_led_blink_set(unsigned int led); -extern void ifxmips_led_blink_clear(unsigned int led); - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei.h deleted file mode 100644 index d8a4b8867f..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei.h +++ /dev/null @@ -1,270 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : danube_mei.h -** PROJECT : Danube -** MODULES : MEI -** -** DATE : 1 Jan 2006 -** AUTHOR : TC Chen -** DESCRIPTION : MEI Driver -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Version $Date $Author $Comment -*******************************************************************************/ -#ifndef _IFXMIPS_MEI_H -#define _IFXMIPS_MEI_H -///////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#include "ifxmips_mei_app.h" - -#define IFXMIPS_MEI_DEBUG -#define IFXMIPS_MEI_CMV_EXTRA -#define IFXMIPS_MEI_MAJOR 106 - -/* -** Define where in ME Processor's memory map the Stratify chip lives -*/ - -#define MAXSWAPSIZE 8 * 1024 //8k *(32bits) - -// Mailboxes -#define MSG_LENGTH 16 // x16 bits -#define YES_REPLY 1 -#define NO_REPLY 0 - -#define CMV_TIMEOUT 100 //jiffies -#define MIB_INTERVAL 10000 //msec - -/*** Bit definitions ***/ - -#define FALSE 0 -#define TRUE 1 -#define BIT0 1<<0 -#define BIT1 1<<1 -#define BIT2 1<<2 -#define BIT3 1<<3 -#define BIT4 1<<4 -#define BIT5 1<<5 -#define BIT6 1<<6 -#define BIT7 1<<7 -#define BIT8 1<<8 -#define BIT9 1<<9 -#define BIT10 1<<10 -#define BIT11 1<<11 -#define BIT12 1<<12 -#define BIT13 1<<13 -#define BIT14 1<<14 -#define BIT15 1<<15 -#define BIT16 1<<16 -#define BIT17 1<<17 -#define BIT18 1<<18 -#define BIT19 1<<19 -#define BIT20 1<<20 -#define BIT21 1<<21 -#define BIT22 1<<22 -#define BIT23 1<<23 -#define BIT24 1<<24 -#define BIT25 1<<25 -#define BIT26 1<<26 -#define BIT27 1<<27 -#define BIT28 1<<28 -#define BIT29 1<<29 -#define BIT30 1<<30 -#define BIT31 1<<31 - -// ARC register addresss -#define ARC_STATUS 0x0 -#define ARC_LP_START 0x2 -#define ARC_LP_END 0x3 -#define ARC_DEBUG 0x5 -#define ARC_INT_MASK 0x10A - -#define IRAM0_BASE (0x00000) -#define IRAM1_BASE (0x04000) -#define BRAM_BASE (0x0A000) - -#define ADSL_BASE (0x20000) -#define CRI_BASE (ADSL_BASE + 0x11F00) -#define CRI_CCR0 (CRI_BASE + 0x00) -#define CRI_RST (CRI_BASE + 0x04*4) -#define ADSL_DILV_BASE (ADSL_BASE+0x20000) - -// -#define IRAM0_ADDR_BIT_MASK 0xFFF -#define IRAM1_ADDR_BIT_MASK 0xFFF -#define BRAM_ADDR_BIT_MASK 0xFFF -#define RX_DILV_ADDR_BIT_MASK 0x1FFF - -// CRI_CCR0 Register definitions -#define CLK_2M_MODE_ENABLE BIT6 -#define ACL_CLK_MODE_ENABLE BIT4 -#define FDF_CLK_MODE_ENABLE BIT2 -#define STM_CLK_MODE_ENABLE BIT0 - -// CRI_RST Register definitions -#define FDF_SRST BIT3 -#define MTE_SRST BIT2 -#define FCI_SRST BIT1 -#define AAI_SRST BIT0 - -// MEI_TO_ARC_INTERRUPT Register definitions -#define MEI_TO_ARC_INT1 BIT3 -#define MEI_TO_ARC_INT0 BIT2 -#define MEI_TO_ARC_CS_DONE BIT1 //need to check -#define MEI_TO_ARC_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT Register definitions -#define ARC_TO_MEI_INT1 BIT8 -#define ARC_TO_MEI_INT0 BIT7 -#define ARC_TO_MEI_CS_REQ BIT6 -#define ARC_TO_MEI_DBG_DONE BIT5 -#define ARC_TO_MEI_MSGACK BIT4 -#define ARC_TO_MEI_NO_ACCESS BIT3 -#define ARC_TO_MEI_CHECK_AAITX BIT2 -#define ARC_TO_MEI_CHECK_AAIRX BIT1 -#define ARC_TO_MEI_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT_MASK Register definitions -#define GP_INT1_EN BIT8 -#define GP_INT0_EN BIT7 -#define CS_REQ_EN BIT6 -#define DBG_DONE_EN BIT5 -#define MSGACK_EN BIT4 -#define NO_ACC_EN BIT3 -#define AAITX_EN BIT2 -#define AAIRX_EN BIT1 -#define MSGAV_EN BIT0 - -#define MEI_SOFT_RESET BIT0 - -#define HOST_MSTR BIT0 - -#define JTAG_MASTER_MODE 0x0 -#define MEI_MASTER_MODE HOST_MSTR - -// MEI_DEBUG_DECODE Register definitions -#define MEI_DEBUG_DEC_MASK (0x3) -#define MEI_DEBUG_DEC_AUX_MASK (0x0) -#define MEI_DEBUG_DEC_DMP1_MASK (0x1) -#define MEI_DEBUG_DEC_DMP2_MASK (0x2) -#define MEI_DEBUG_DEC_CORE_MASK (0x3) - -#define AUX_STATUS (0x0) -// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate -// page swap requests. -#define MEI_TO_ARC_MAILBOX (0xDFD0) -#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C) - -#define ARC_TO_MEI_MAILBOX (0xDFA0) -#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C) - -// Codeswap request messages are indicated by setting BIT31 -#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000) - -// Clear Eoc messages received are indicated by setting BIT17 -#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000) - -/* -** Swap page header -*/ -// Page must be loaded at boot time if size field has BIT31 set -#define BOOT_FLAG (BIT31) -#define BOOT_FLAG_MASK ~BOOT_FLAG - -#define FREE_RELOAD 1 -#define FREE_SHOWTIME 2 -#define FREE_ALL 3 - -#define IFX_POP_EOC_DONE 0 -#define IFX_POP_EOC_FAIL -1 - -#define CLREOC_BUFF_SIZE 12 //number of clreoc commands being buffered - -// marcos -#define IFXMIPS_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data);} while (0) -#define IFXMIPS_READ_REGISTER_L(addr) (*((volatile u32*)(addr))) -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - -#define ALIGN_SIZE ( 1L<<10 ) //1K size align -#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) ) - -// swap marco -#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);} -#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);} - -// Swap page header describes size in 32-bit words, load location, and image offset -// for program and/or data segments -typedef struct _arc_swp_page_hdr { - u32 p_offset; //Offset bytes of progseg from beginning of image - u32 p_dest; //Destination addr of progseg on processor - u32 p_size; //Size in 32-bitwords of program segment - u32 d_offset; //Offset bytes of dataseg from beginning of image - u32 d_dest; //Destination addr of dataseg on processor - u32 d_size; //Size in 32-bitwords of data segment -} ARC_SWP_PAGE_HDR; - -#ifdef CONFIG_PROC_FS -typedef struct reg_entry { - int *flag; - char name[30]; // big enough to hold names - char description[100]; // big enough to hold description - unsigned short low_ino; -} reg_entry_t; -#endif - -/* -** Swap image header -*/ -#define GET_PROG 0 // Flag used for program mem segment -#define GET_DATA 1 // Flag used for data mem segment - -// Image header contains size of image, checksum for image, and count of -// page headers. Following that are 'count' page headers followed by -// the code and/or data segments to be loaded -typedef struct _arc_img_hdr { - u32 size; // Size of binary image in bytes - u32 checksum; // Checksum for image - u32 count; // Count of swp pages in image - ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy -} ARC_IMG_HDR; - -typedef struct smmu_mem_info { - int type; - unsigned long nCopy; - unsigned long size; - unsigned char *address; - unsigned char *org_address; -} smmu_mem_info_t; - -/* -** Native size for the Stratiphy interface is 32-bits. All reads and writes -** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or -** byte data. Read routines are provided. Write routines are probably a bad idea, as the -** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle -** could very well have unintended results. -*/ -MEI_ERROR meiCMV (u16 *, int, u16 *); // first arg is CMV to ARC, second to indicate whether need reply - -MEI_ERROR meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize); -extern int ifx_mei_hdlc_send (char *hdlc_pkt, int hdlc_pkt_len); -extern int ifx_mei_hdlc_read (char *hdlc_pkt, int max_hdlc_pkt_len); -#if defined(__KERNEL__) || defined (IFXMIPS_PORT_RTEMS) -extern void makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size, - u16 * data, u16 * CMVMSG); -int ifx_mei_hdlc_send (char *, int); -int ifx_mei_hdlc_read (char *, int); -#endif - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app.h deleted file mode 100644 index cba742e58a..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app.h +++ /dev/null @@ -1,116 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_mei_app.h -** PROJECT : Danube -** MODULES : MEI -** -** DATE : 1 Jan 2006 -** AUTHOR : TC Chen -** DESCRIPTION : MEI Driver -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Version $Date $Author $Comment -*******************************************************************************/ -#ifndef _IFXMIPS_MEI_APP_H -#define _IFXMIPS_MEI_APP_H - // ioctl control -#define IFXMIPS_MEI_START 300 -#define IFXMIPS_MEI_REPLY 301 -#define IFXMIPS_MEI_NOREPLY 302 - -#define IFXMIPS_MEI_RESET 303 -#define IFXMIPS_MEI_REBOOT 304 -#define IFXMIPS_MEI_HALT 305 -#define IFXMIPS_MEI_CMV_WINHOST 306 -#define IFXMIPS_MEI_CMV_READ 307 -#define IFXMIPS_MEI_CMV_WRITE 308 -#define IFXMIPS_MEI_MIB_DAEMON 309 -#define IFXMIPS_MEI_SHOWTIME 310 -#define IFXMIPS_MEI_REMOTE 311 -#define IFXMIPS_MEI_READDEBUG 312 -#define IFXMIPS_MEI_WRITEDEBUG 313 -#define IFXMIPS_MEI_LOP 314 - -#define IFXMIPS_MEI_PCM_SETUP 315 -#define IFXMIPS_MEI_PCM_START_TIMER 316 -#define IFXMIPS_MEI_PCM_STOP_TIMER 317 -#define IFXMIPS_MEI_PCM_CHECK 318 -#define IFXMIPS_MEI_GET_EOC_LEN 319 -#define IFXMIPS_MEI_GET_EOC_DATA 320 -#define IFXMIPS_MEI_PCM_GETDATA 321 -#define IFXMIPS_MEI_PCM_GPIO 322 -#define IFXMIPS_MEI_EOC_SEND 323 -#define IFXMIPS_MEI_DOWNLOAD 326 -#define IFXMIPS_MEI_JTAG_ENABLE 327 -#define IFXMIPS_MEI_RUN 328 -#define IFXMIPS_MEI_DEBUG_MODE 329 - -/* Loop diagnostics mode of the ADSL line related constants */ -#define SET_ADSL_LOOP_DIAGNOSTICS_MODE 330 -#define GET_ADSL_LOOP_DIAGNOSTICS_MODE 331 -#define LOOP_DIAGNOSTIC_MODE_COMPLETE 332 -#define IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE 333 - -/* L3 Power Mode */ -/* Get current Power Moaagement Mode Status*/ -#define GET_POWER_MANAGEMENT_MODE 334 -/* Set L3 Power Mode /disable L3 power mode */ -#define SET_L3_POWER_MODE 335 - -/* get current dual latency configuration */ -#define GET_ADSL_DUAL_LATENCY 336 -/* enable/disable dual latency path */ -#define SET_ADSL_DUAL_LATENCY 337 - -/* Enable/Disable autoboot mode. */ -/* When the autoboot mode is disabled, the driver will excute some cmv - commands for led control and dual latency when DSL startup.*/ -#define AUTOBOOT_ENABLE_SET 338 - -/* Enable/Disable Quiet Mode*/ -/* Quiet mode is used for firmware debug. if the quiet mode enable, the autoboot daemon will not reset arc when the arc need to reboot */ -#define QUIET_MODE_GET 339 -#define QUIET_MODE_SET 340 - -/* Enable/Disable showtime lock*/ -/* showtime lock is used for firmware debug. if the showtime lock enable, the autoboot daemon will not reset arc when the arc reach showtime and need to reboot */ -#define SHOWTIME_LOCK_GET 341 -#define SHOWTIME_LOCK_SET 342 - -#define L0_POWER_MODE 0 -#define L2_POWER_MODE 2 -#define L3_POWER_MODE 3 - -#define DUAL_LATENCY_US_DS_DISABLE 0 -#define DUAL_LATENCY_US_ENABLE (1<<0) -#define DUAL_LATENCY_DS_ENABLE (1<<1) -#define DUAL_LATENCY_US_DS_ENABLE (DUAL_LATENCY_US_ENABLE|DUAL_LATENCY_DS_ENABLE) - -#define ME_HDLC_IDLE 0 -#define ME_HDLC_INVALID_MSG 1 -#define ME_HDLC_MSG_QUEUED 2 -#define ME_HDLC_MSG_SENT 3 -#define ME_HDLC_RESP_RCVD 4 -#define ME_HDLC_RESP_TIMEOUT 5 -#define ME_HDLC_RX_BUF_OVERFLOW 6 -#define ME_HDLC_UNRESOLVED 1 -#define ME_HDLC_RESOLVED 2 - -/*** Enums ***/ -typedef enum mei_error { - MEI_SUCCESS = 0, - MEI_FAILURE = -1, - MEI_MAILBOX_FULL = -2, - MEI_MAILBOX_EMPTY = -3, - MEI_MAILBOX_TIMEOUT = -4, -} MEI_ERROR; - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app_ioctl.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app_ioctl.h deleted file mode 100644 index 08c3dd3fc1..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_app_ioctl.h +++ /dev/null @@ -1,1191 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_mei_app_ioctl.h -** PROJECT : Danube -** MODULES : MEI -** -** DATE : 1 Jan 2006 -** AUTHOR : TC Chen -** DESCRIPTION : MEI Driver -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Version $Date $Author $Comment -*******************************************************************************/ -#ifndef __IFXMIPS_MEI_APP_IOCTL_H -#define __IFXMIPS_MEI_APP_IOCTL_H - -#ifdef __KERNEL__ -#include "ifxmips_mei_ioctl.h" -#endif - -/* Interface Name */ -//#define INTERFACE_NAME - -/* adslLineTable constants */ -#define GET_ADSL_LINE_CODE 1 - -/* adslAtucPhysTable constants */ -#define GET_ADSL_ATUC_PHY 4 - -/* adslAturPhysTable constants */ -#define GET_ADSL_ATUR_PHY 10 - -/* adslAtucChanTable constants */ -#define GET_ADSL_ATUC_CHAN_INFO 15 - -/* adslAturChanTable constants */ -#define GET_ADSL_ATUR_CHAN_INFO 18 - -/* adslAtucPerfDataTable constants */ -#define GET_ADSL_ATUC_PERF_DATA 21 - -/* adslAturPerfDataTable constants */ -#define GET_ADSL_ATUR_PERF_DATA 40 - -/* adslAtucIntervalTable constants */ -#define GET_ADSL_ATUC_INTVL_INFO 60 - -/* adslAturIntervalTable constants */ -#define GET_ADSL_ATUR_INTVL_INFO 65 - -/* adslAtucChanPerfDataTable constants */ -#define GET_ADSL_ATUC_CHAN_PERF_DATA 70 - -/* adslAturChanPerfDataTable constants */ -#define GET_ADSL_ATUR_CHAN_PERF_DATA 90 - -/* adslAtucChanIntervalTable constants */ -#define GET_ADSL_ATUC_CHAN_INTVL_INFO 110 - -/* adslAturChanIntervalTable constants */ -#define GET_ADSL_ATUR_CHAN_INTVL_INFO 115 - -/* adslLineAlarmConfProfileTable constants */ -#define GET_ADSL_ALRM_CONF_PROF 120 -#define SET_ADSL_ALRM_CONF_PROF 121 - -/* adslAturTrap constants */ -#define ADSL_ATUR_TRAPS 135 - -////////////////// RFC-3440 ////////////// - -#ifdef IFXMIPS_MEI_MIB_RFC3440 -/* adslLineExtTable */ -#define GET_ADSL_ATUC_LINE_EXT 201 -#define SET_ADSL_ATUC_LINE_EXT 203 - -/* adslAtucPerfDateExtTable */ -#define GET_ADSL_ATUC_PERF_DATA_EXT 205 - -/* adslAtucIntervalExtTable */ -#define GET_ADSL_ATUC_INTVL_EXT_INFO 221 - -/* adslAturPerfDataExtTable */ -#define GET_ADSL_ATUR_PERF_DATA_EXT 225 - -/* adslAturIntervalExtTable */ -#define GET_ADSL_ATUR_INTVL_EXT_INFO 233 - -/* adslAlarmConfProfileExtTable */ -#define GET_ADSL_ALRM_CONF_PROF_EXT 235 -#define SET_ADSL_ALRM_CONF_PROF_EXT 236 - -/* adslAturExtTrap */ -#define ADSL_ATUR_EXT_TRAPS 240 - -#endif - -/* The following constants are added to support the WEB related ADSL Statistics */ - -/* adslLineStatus constants */ -#define GET_ADSL_LINE_STATUS 245 - -/* adslLineRate constants */ -#define GET_ADSL_LINE_RATE 250 - -/* adslLineInformation constants */ -#define GET_ADSL_LINE_INFO 255 - -/* adslNearEndPerformanceStats constants */ -#define GET_ADSL_NEAREND_STATS 270 - -/* adslFarEndPerformanceStats constants */ -#define GET_ADSL_FAREND_STATS 290 - -/* Sub-carrier related parameters */ -#define GET_ADSL_LINE_INIT_STATS 150 -#define GET_ADSL_POWER_SPECTRAL_DENSITY 151 - -#define IFXMIPS_MIB_LO_ATUC 295 -#define IFXMIPS_MIB_LO_ATUR 296 - -#define GET_ADSL_ATUC_SUBCARRIER_STATS 297 -#define GET_ADSL_ATUR_SUBCARRIER_STATS 298 - - - -/////////////////////////////////////////////////////////// -// makeCMV(Opcode, Group, Address, Index, Size, Data) - -/* adslLineCode Flags */ -#define LINE_CODE_FLAG 0x1 /* BIT 0th position */ - -/* adslAtucPhysTable Flags */ -#define ATUC_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 57, 0, 12, data,TxMessage) -#define ATUC_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 57, 12, 4, data,TxMessage) - -#define ATUC_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */ -#define ATUC_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 64, 0, 4, data,TxMessage) - -#define ATUC_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */ -#define ATUC_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 58, 0, 8, data,TxMessage) - -#define ATUC_CURR_STAT_FLAG 0x8 /* BIT 3 */ - -#define ATUC_CURR_OUT_PWR_FLAG 0x10 /* BIT 4 */ -#define ATUC_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 5, 1, data,TxMessage) - -#define ATUC_CURR_ATTR_FLAG 0x20 /* BIT 5 */ -#define ATUC_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 0, 2, data,TxMessage) - - -/* adslAturPhysTable Flags */ -#define ATUR_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */ -#define ATUR_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 62, 0, 12, data,TxMessage) -#define ATUR_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 62, 12, 4, data,TxMessage) - -#define ATUR_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */ -#define ATUR_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 65, 0, 4, data,TxMessage) - -#define ATUR_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */ -#define ATUR_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 61, 0, 8, data,TxMessage) - -#define ATUR_SNRMGN_FLAG 0x8 -#if 0 /* [ Ritesh. Use PLAM 45 0 for 0.1dB resolution rather than INFO 68 3 */ -#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 1, data,TxMessage) -#else -#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, PLAM_SNRMargin_0_1db, 0, 1, data, TxMessage) -#endif - -#define ATUR_ATTN_FLAG 0x10 -#define ATUR_ATTN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data,TxMessage) - -#define ATUR_CURR_STAT_FLAG 0x20 /* BIT 3 */ - -#define ATUR_CURR_OUT_PWR_FLAG 0x40 /* BIT 4 */ -#define ATUR_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 5, 1, data,TxMessage) - -#define ATUR_CURR_ATTR_FLAG 0x80 /* BIT 5 */ -#define ATUR_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 0, 2, data,TxMessage) - -/* adslAtucChanTable Flags */ -#define ATUC_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */ -//KD #define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 1, 1, data,TxMessage) -#define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 92, 1, 1, data,TxMessage) - -#define ATUC_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */ -#define ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data,TxMessage) - -#define ATUC_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */ - -/* adslAturChanTable Flags */ -#define ATUR_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */ -//KD #define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 2, 1, 1, data,TxMessage) -#define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 93, 1, 1, data,TxMessage) - -#define ATUR_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */ -#define ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data,TxMessage) - -#define ATUR_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */ - -#define ATUR_CHAN_CRC_BLK_LEN_FLAG 0x8 /* BIT 3 */ - -/* adslAtucPerfDataTable Flags */ -#define ATUC_PERF_LOFS_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PERF_LOSS_FLAG 0x2 /* BIT 1 */ -#define ATUC_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data,TxMessage) -#define ATUC_PERF_ESS_FLAG 0x4 /* BIT 2 */ -#define ATUC_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data,TxMessage) -#define ATUC_PERF_INITS_FLAG 0x8 /* BIT 3 */ -#define ATUC_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */ -#define ATUC_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */ -#define ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUC_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */ -#define ATUC_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */ -#define ATUC_PERF_CURR_15MIN_ESS_FLAG 0x200 /* BIT 9 */ -#define ATUC_PERF_CURR_15MIN_INIT_FLAG 0x400 /* BIT 10 */ -#define ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ -#define ATUC_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */ -#define ATUC_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */ -#define ATUC_PERF_CURR_1DAY_ESS_FLAG 0x4000 /* BIT 14 */ -#define ATUC_PERF_CURR_1DAY_INIT_FLAG 0x8000 /* BIT 15 */ -#define ATUC_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUC_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */ -#define ATUC_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */ -#define ATUC_PERF_PREV_1DAY_ESS_FLAG 0x80000 /* BIT 19 */ -#define ATUC_PERF_PREV_1DAY_INITS_FLAG 0x100000 /* BIT 20 */ - -/* adslAturPerfDataTable Flags */ -#define ATUR_PERF_LOFS_FLAG 0x1 /* BIT 0th position */ -#define ATUR_PERF_LOSS_FLAG 0x2 /* BIT 1 */ -#define ATUR_PERF_LPR_FLAG 0x4 /* BIT 2 */ -#define ATUR_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data,TxMessage) -#define ATUR_PERF_ESS_FLAG 0x8 /* BIT 3 */ -#define ATUR_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data,TxMessage) -#define ATUR_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */ -#define ATUR_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */ -#define ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUR_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */ -#define ATUR_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */ -#define ATUR_PERF_CURR_15MIN_LPR_FLAG 0x200 /* BIT 9 */ -#define ATUR_PERF_CURR_15MIN_ESS_FLAG 0x400 /* BIT 10 */ -#define ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ -#define ATUR_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */ -#define ATUR_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */ -#define ATUR_PERF_CURR_1DAY_LPR_FLAG 0x4000 /* BIT 14 */ -#define ATUR_PERF_CURR_1DAY_ESS_FLAG 0x8000 /* BIT 15 */ -#define ATUR_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUR_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */ -#define ATUR_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */ -#define ATUR_PERF_PREV_1DAY_LPR_FLAG 0x80000 /* BIT 19 */ -#define ATUR_PERF_PREV_1DAY_ESS_FLAG 0x100000 /* BIT 20 */ - -/* adslAtucIntervalTable Flags */ -#define ATUC_INTVL_LOF_FLAG 0x1 /* BIT 0th position */ -#define ATUC_INTVL_LOS_FLAG 0x2 /* BIT 1 */ -#define ATUC_INTVL_ESS_FLAG 0x4 /* BIT 2 */ -#define ATUC_INTVL_INIT_FLAG 0x8 /* BIT 3 */ -#define ATUC_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */ - -/* adslAturIntervalTable Flags */ -#define ATUR_INTVL_LOF_FLAG 0x1 /* BIT 0th position */ -#define ATUR_INTVL_LOS_FLAG 0x2 /* BIT 1 */ -#define ATUR_INTVL_LPR_FLAG 0x4 /* BIT 2 */ -#define ATUR_INTVL_ESS_FLAG 0x8 /* BIT 3 */ -#define ATUR_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */ - -/* adslAtucChanPerfDataTable Flags */ -#define ATUC_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */ -#define ATUC_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */ -#define ATUC_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */ -#define ATUC_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */ -#define ATUC_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */ -#define ATUC_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */ -#define ATUC_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUC_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */ -#define ATUC_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */ -#define ATUC_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */ -#define ATUC_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */ -#define ATUC_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11*/ -#define ATUC_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */ -#define ATUC_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */ -#define ATUC_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */ -#define ATUC_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */ -#define ATUC_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUC_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */ -#define ATUC_CHAN_PERF_PREV_1DAY_TX_BLK_FLAG 0x40000 /* BIT 18 */ -#define ATUC_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */ -#define ATUC_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */ - - -/* adslAturChanPerfDataTable Flags */ -#define ATUR_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */ -#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data,TxMessage) -#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data,TxMessage) -#define ATUR_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */ -#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data,TxMessage) -#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data,TxMessage) -#define ATUR_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */ -#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data,TxMessage) -#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data,TxMessage) -#define ATUR_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */ -#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data,TxMessage) -#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data,TxMessage) -#define ATUR_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */ -#define ATUR_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */ -#define ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */ -#define ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */ -#define ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */ -#define ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */ -#define ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ -#define ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */ -#define ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */ -#define ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */ -#define ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */ -#define ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */ -#define ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG 0x40000 /* BIT 18 */ -#define ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */ -#define ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */ - -/* adslAtucChanIntervalTable Flags */ -#define ATUC_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th position */ -#define ATUC_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */ -#define ATUC_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */ -#define ATUC_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */ -#define ATUC_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */ -#define ATUC_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */ - -/* adslAturChanIntervalTable Flags */ -#define ATUR_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th Position */ -#define ATUR_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */ -#define ATUR_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */ -#define ATUR_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */ -#define ATUR_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */ -#define ATUR_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */ - -/* adslLineAlarmConfProfileTable Flags */ -#define ATUC_THRESH_15MIN_LOFS_FLAG 0x01 /* BIT 0th position */ -#define ATUC_THRESH_15MIN_LOSS_FLAG 0x02 /* BIT 1 */ -#define ATUC_THRESH_15MIN_ESS_FLAG 0x04 /* BIT 2 */ -#define ATUC_THRESH_FAST_RATEUP_FLAG 0x08 /* BIT 3 */ -#define ATUC_THRESH_INTERLEAVE_RATEUP_FLAG 0x10 /* BIT 4 */ -#define ATUC_THRESH_FAST_RATEDOWN_FLAG 0x20 /* BIT 5 */ -#define ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x40 /* BIT 6 */ -#define ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG 0x80 /* BIT 7 */ -#define ATUR_THRESH_15MIN_LOFS_FLAG 0x100 /* BIT 8 */ -#define ATUR_THRESH_15MIN_LOSS_FLAG 0x200 /* BIT 9 */ -#define ATUR_THRESH_15MIN_LPRS_FLAG 0x400 /* BIT 10 */ -#define ATUR_THRESH_15MIN_ESS_FLAG 0x800 /* BIT 11 */ -#define ATUR_THRESH_FAST_RATEUP_FLAG 0x1000 /* BIT 12 */ -#define ATUR_THRESH_INTERLEAVE_RATEUP_FLAG 0x2000 /* BIT 13 */ -#define ATUR_THRESH_FAST_RATEDOWN_FLAG 0x4000 /* BIT 14 */ -#define ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x8000 /* BIT 15 */ -#define LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG 0x10000 /* BIT 16 */ - - -/* adslAturTraps Flags */ -#define ATUC_PERF_LOFS_THRESH_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PERF_LOSS_THRESH_FLAG 0x2 /* BIT 1 */ -#define ATUC_PERF_ESS_THRESH_FLAG 0x4 /* BIT 2 */ -#define ATUC_RATE_CHANGE_FLAG 0x8 /* BIT 3 */ -#define ATUR_PERF_LOFS_THRESH_FLAG 0x10 /* BIT 4 */ -#define ATUR_PERF_LOSS_THRESH_FLAG 0x20 /* BIT 5 */ -#define ATUR_PERF_LPRS_THRESH_FLAG 0x40 /* BIT 6 */ -#define ATUR_PERF_ESS_THRESH_FLAG 0x80 /* BIT 7 */ -#define ATUR_RATE_CHANGE_FLAG 0x100 /* BIT 8 */ - -//RFC- 3440 FLAG DEFINITIONS - -#ifdef IFXMIPS_MEI_MIB_RFC3440 -/* adslLineExtTable flags */ -#define ATUC_LINE_TRANS_CAP_FLAG 0x1 /* BIT 0th position */ -#define ATUC_LINE_TRANS_CAP_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data,TxMessage) -#define ATUC_LINE_TRANS_CONFIG_FLAG 0x2 /* BIT 1 */ -#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data,TxMessage) -#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR makeCMV(H2D_CMV_WRITE,INFO, 67, 0, 1, data,TxMessage) -#define ATUC_LINE_TRANS_ACTUAL_FLAG 0x4 /* BIT 2 */ -#define ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 1, 0, 1, data,TxMessage) -#define LINE_GLITE_POWER_STATE_FLAG 0x8 /* BIT 3 */ -#define LINE_GLITE_POWER_STATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 0, 0, 1, data,TxMessage) - -/* adslAtucPerfDataExtTable flags */ -#define ATUC_PERF_STAT_FASTR_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PERF_STAT_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data, TxMessage) -#define ATUC_PERF_STAT_FAILED_FASTR_FLAG 0x2 /* BIT 1 */ -#define ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data, TxMessage) -#define ATUC_PERF_STAT_SESL_FLAG 0X4 /* BIT 2 */ -#define ATUC_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data, TxMessage) -#define ATUC_PERF_STAT_UASL_FLAG 0X8 /* BIT 3 */ -#define ATUC_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data, TxMessage) -#define ATUC_PERF_CURR_15MIN_FASTR_FLAG 0X10 /* BIT 4 */ -#define ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG 0X20 /* BIT 5 */ -#define ATUC_PERF_CURR_15MIN_SESL_FLAG 0X40 /* BIT 6 */ -#define ATUC_PERF_CURR_15MIN_UASL_FLAG 0X80 /* BIT 7 */ -#define ATUC_PERF_CURR_1DAY_FASTR_FLAG 0X100 /* BIT 8 */ -#define ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG 0X200 /* BIT 9 */ -#define ATUC_PERF_CURR_1DAY_SESL_FLAG 0X400 /* BIT 10 */ -#define ATUC_PERF_CURR_1DAY_UASL_FLAG 0X800 /* BIT 11 */ -#define ATUC_PERF_PREV_1DAY_FASTR_FLAG 0X1000 /* BIT 12 */ -#define ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG 0X2000 /* BIT 13 */ -#define ATUC_PERF_PREV_1DAY_SESL_FLAG 0X4000 /* BIT 14 */ -#define ATUC_PERF_PREV_1DAY_UASL_FLAG 0X8000 /* BIT 15 */ - -/* adslAturPerfDataExtTable */ -#define ATUR_PERF_STAT_SESL_FLAG 0X1 /* BIT 0th position */ -#define ATUR_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data, TxMessage) -#define ATUR_PERF_STAT_UASL_FLAG 0X2 /* BIT 1 */ -#define ATUR_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data, TxMessage) -#define ATUR_PERF_CURR_15MIN_SESL_FLAG 0X4 /* BIT 2 */ -#define ATUR_PERF_CURR_15MIN_UASL_FLAG 0X8 /* BIT 3 */ -#define ATUR_PERF_CURR_1DAY_SESL_FLAG 0X10 /* BIT 4 */ -#define ATUR_PERF_CURR_1DAY_UASL_FLAG 0X20 /* BIT 5 */ -#define ATUR_PERF_PREV_1DAY_SESL_FLAG 0X40 /* BIT 6 */ -#define ATUR_PERF_PREV_1DAY_UASL_FLAG 0X80 /* BIT 7 */ - -/* adslAutcIntervalExtTable flags */ -#define ATUC_INTERVAL_FASTR_FLAG 0x1 /* Bit 0 */ -#define ATUC_INTERVAL_FAILED_FASTR_FLAG 0x2 /* Bit 1 */ -#define ATUC_INTERVAL_SESL_FLAG 0x4 /* Bit 2 */ -#define ATUC_INTERVAL_UASL_FLAG 0x8 /* Bit 3 */ - -/* adslAturIntervalExtTable */ -#define ATUR_INTERVAL_SESL_FLAG 0X1 /* BIT 0th position */ -#define ATUR_INTERVAL_UASL_FLAG 0X2 /* BIT 1 */ - -/* adslAlarmConfProfileExtTable */ -#define ATUC_THRESH_15MIN_FAILED_FASTR_FLAG 0X1/* BIT 0th position */ -#define ATUC_THRESH_15MIN_SESL_FLAG 0X2 /* BIT 1 */ -#define ATUC_THRESH_15MIN_UASL_FLAG 0X4 /* BIT 2 */ -#define ATUR_THRESH_15MIN_SESL_FLAG 0X8 /* BIT 3 */ -#define ATUR_THRESH_15MIN_UASL_FLAG 0X10 /* BIT 4 */ - -/* adslAturExtTraps */ -#define ATUC_15MIN_FAILED_FASTR_TRAP_FLAG 0X1 /* BIT 0th position */ -#define ATUC_15MIN_SESL_TRAP_FLAG 0X2 /* BIT 1 */ -#define ATUC_15MIN_UASL_TRAP_FLAG 0X4 /* BIT 2 */ -#define ATUR_15MIN_SESL_TRAP_FLAG 0X8 /* BIT 3 */ -#define ATUR_15MIN_UASL_TRAP_FLAG 0X10 /* BIT 4 */ - -#endif - -/* adslLineStatus Flags */ -#define LINE_STAT_MODEM_STATUS_FLAG 0x1 /* BIT 0th position */ -#define LINE_STAT_MODEM_STATUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data, TxMessage) -#define LINE_STAT_MODE_SEL_FLAG 0x2 /* BIT 1 */ -#define LINE_STAT_MODE_SEL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data, TxMessage) -#define LINE_STAT_TRELLCOD_ENABLE_FLAG 0x4 /* BIT 2 */ -#define LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, OPTN, 2, 0, 1, data, TxMessage) -#define LINE_STAT_LATENCY_FLAG 0x8 /* BIT 3 */ -#define LINE_STAT_LATENCY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 12, 0, 1, data, TxMessage) - -/* adslLineRate Flags */ -#define LINE_RATE_DATA_RATEDS_FLAG 0x1 /* BIT 0th position */ -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data, TxMessage) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 2, 2, data, TxMessage) - - -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 0, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 0, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 0, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 0, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 0, 2, data, TxMessage) - -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 1, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 1, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 1, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 1, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 2, 2, data, TxMessage) - -#define LINE_RATE_DATA_RATEUS_FLAG 0x2 /* BIT 1 */ -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data, TxMessage) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 2, 2, data, TxMessage) - - -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 0, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 0, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 0, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 0, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 0, 2, data, TxMessage) - -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 1, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 1, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 1, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 1, 1, data, TxMessage) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 2, 2, data, TxMessage) - -#define LINE_RATE_ATTNDRDS_FLAG 0x4 /* BIT 2 */ -#define LINE_RATE_ATTNDRDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 2, data, TxMessage) - -#define LINE_RATE_ATTNDRUS_FLAG 0x8 /* BIT 3 */ -#define LINE_RATE_ATTNDRUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 4, 2, data, TxMessage) - -/* adslLineInformation Flags */ -#define LINE_INFO_INTLV_DEPTHDS_FLAG 0x1 /* BIT 0th position */ -#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 0, 1, data, TxMessage) -#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 1, 1, data, TxMessage) -#define LINE_INFO_INTLV_DEPTHUS_FLAG 0x2 /* BIT 1 */ -#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 0, 1, data, TxMessage) -#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 1, 1, data, TxMessage) -#define LINE_INFO_LATNDS_FLAG 0x4 /* BIT 2 */ -#define LINE_INFO_LATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 1, 1, data, TxMessage) -#define LINE_INFO_LATNUS_FLAG 0x8 /* BIT 3 */ -#define LINE_INFO_LATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 1, 1, data, TxMessage) -#define LINE_INFO_SATNDS_FLAG 0x10 /* BIT 4 */ -#define LINE_INFO_SATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data, TxMessage) -#define LINE_INFO_SATNUS_FLAG 0x20 /* BIT 5 */ -#define LINE_INFO_SATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 2, 1, data, TxMessage) -#define LINE_INFO_SNRMNDS_FLAG 0x40 /* BIT 6 */ -#define LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 3, 1, data, TxMessage) -#define LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 0, 1, data, TxMessage) -#define LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 46, 0, 1, data, TxMessage) -#define LINE_INFO_SNRMNUS_FLAG 0x80 /* BIT 7 */ -#define LINE_INFO_SNRMNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 3, 1, data, TxMessage) -#define LINE_INFO_ACATPDS_FLAG 0x100 /* BIT 8 */ -#define LINE_INFO_ACATPDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 6, 1, data, TxMessage) -#define LINE_INFO_ACATPUS_FLAG 0x200 /* BIT 9 */ -#define LINE_INFO_ACATPUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 6, 1, data, TxMessage) - -/* adslNearEndPerformanceStats Flags */ -#define NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data, TxMessage) -#define NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data, TxMessage) -#define NEAREND_PERF_SUPERFRAME_FLAG 0x1 /* BIT 0th position */ -#define NEAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data, TxMessage) -#define NEAREND_PERF_LOS_FLAG 0x2 /* BIT 1 */ -#define NEAREND_PERF_LOF_FLAG 0x4 /* BIT 2 */ -#define NEAREND_PERF_LPR_FLAG 0x8 /* BIT 3 */ -#define NEAREND_PERF_NCD_FLAG 0x10 /* BIT 4 */ -#define NEAREND_PERF_LCD_FLAG 0x20 /* BIT 5 */ -#define NEAREND_PERF_CRC_FLAG 0x40 /* BIT 6 */ -#define NEAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data, TxMessage) -#define NEAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data, TxMessage) -#define NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data, TxMessage) -#define NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data, TxMessage) -#define NEAREND_PERF_RSCORR_FLAG 0x80 /* BIT 7 */ -#define NEAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 6, 0, 1, data, TxMessage) -#define NEAREND_PERF_FECS_FLAG 0x100 /* BIT 8 */ -#define NEAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data, TxMessage) -#define NEAREND_PERF_ES_FLAG 0x200 /* BIT 9 */ -#define NEAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data, TxMessage) -#define NEAREND_PERF_SES_FLAG 0x400 /* BIT 10 */ -#define NEAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 9, 0, 1, data, TxMessage) -#define NEAREND_PERF_LOSS_FLAG 0x800 /* BIT 11 */ -#define NEAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data, TxMessage) -#define NEAREND_PERF_UAS_FLAG 0x1000 /* BIT 12 */ -#define NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 0, 2, data, TxMessage) -#define NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 2, 2, data, TxMessage) -#define NEAREND_PERF_HECERR_FLAG 0x2000 /* BIT 13 */ - -/* adslFarEndPerformanceStats Flags */ -#define FAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data, TxMessage) -#define FAREND_PERF_LOS_FLAG 0x1 /* BIT 0th position */ -#define FAREND_PERF_LOF_FLAG 0x2 /* BIT 1 */ -#define FAREND_PERF_LPR_FLAG 0x4 /* BIT 2 */ -#define FAREND_PERF_NCD_FLAG 0x8 /* BIT 3 */ -#define FAREND_PERF_LCD_FLAG 0x10 /* BIT 4 */ -#define FAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 0, 1, data, TxMessage) -#define FAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 1, 1, data, TxMessage) -#define FAREND_PERF_CRC_FLAG 0x20 /* BIT 5 */ -#define FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 0, 1, data, TxMessage) -#define FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 1, 1, data, TxMessage) -#define FAREND_PERF_RSCORR_FLAG 0x40 /* BIT 6 */ -#define FAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 32, 0, 1, data, TxMessage) -#define FAREND_PERF_FECS_FLAG 0x80 /* BIT 7 */ -#define FAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data, TxMessage) -#define FAREND_PERF_ES_FLAG 0x100 /* BIT 8 */ -#define FAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data, TxMessage) -#define FAREND_PERF_SES_FLAG 0x200 /* BIT 9 */ -#define FAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 35, 0, 1, data, TxMessage) -#define FAREND_PERF_LOSS_FLAG 0x400 /* BIT 10 */ -#define FAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data, TxMessage) -#define FAREND_PERF_UAS_FLAG 0x800 /* BIT 11 */ -#define FAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 0, 2, data, TxMessage) -#define FAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 2, 2, data, TxMessage) -#define FAREND_PERF_HECERR_FLAG 0x1000 /* BIT 12 */ -// 603221:tc.chen end -/* TR-69 related additional parameters - defines */ -/* Defines for struct adslATURSubcarrierInfo */ -#define NEAREND_HLINSC 0x1 -#define NEAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 71, 2, 1, data, TxMessage) -#define NEAREND_HLINPS 0x2 -#define NEAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 73, idx, size, data, TxMessage) -#define NEAREND_HLOGMT 0x4 -#define NEAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 0, 1, data, TxMessage) -#define NEAREND_HLOGPS 0x8 -#define NEAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 75, idx, size, data, TxMessage) -#define NEAREND_QLNMT 0x10 -#define NEAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 1, 1, data, TxMessage) -#define NEAREND_QLNPS 0x20 -#define NEAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 77, idx, size, data, TxMessage) -#define NEAREND_SNRMT 0x40 -#define NEAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 2, 1, data, TxMessage) -#define NEAREND_SNRPS 0x80 -#define NEAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 78, idx, size, data, TxMessage) -#define NEAREND_BITPS 0x100 -#define NEAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 22, idx, size, data, TxMessage) -#define NEAREND_GAINPS 0x200 -#define NEAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 24, idx, size, data, TxMessage) - -/* Defines for struct adslATUCSubcarrierInfo */ -#define FAREND_HLINSC 0x1 - -/* As per the feedback from Knut on 21/08/2006, the cmv command of HLINSC should be INFO 70 2 */ -#define FAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 70, 2, 1, data, TxMessage) -#define FAREND_HLINPS 0x2 -#define FAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 72, idx, size, data, TxMessage) -#define FAREND_HLOGMT 0x4 -#define FAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 0, 1, data, TxMessage) -#define FAREND_HLOGPS 0x8 -#define FAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 74, idx, size, data, TxMessage) -#define FAREND_QLNMT 0x10 -#define FAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 1, 1, data, TxMessage) -#define FAREND_QLNPS 0x20 -#define FAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 76, idx, size, data, TxMessage) -#define FAREND_SNRMT 0x40 -#define FAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 2, 1, data, TxMessage) -#define FAREND_SNRPS 0x80 -#define FAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 11, idx, size, data, TxMessage) -#define FAREND_SNRPS_DIAG_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 10, idx, size, data, TxMessage) -#define FAREND_BITPS 0x100 -#define FAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 23, idx, size, data, TxMessage) -#define FAREND_GAINPS 0x200 -#define FAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 25, idx, size, data, TxMessage) - - -// GET_ADSL_POWER_SPECTRAL_DENSITY -#define NOMPSD_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 0, 1, data, TxMessage) -#define NOMPSD_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 1, 1, data, TxMessage) -#define PCB_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 6, 1, data, TxMessage) -#define PCB_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 7, 1, data, TxMessage) -#define RMSGI_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 10, 1, data, TxMessage) -#define RMSGI_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 11, 1, data, TxMessage) - -/////////////////////////////////////////////////Macro Definitions ? FLAG Setting & Testing - -#define SET_FLAG(flags, flag_val) ((*flags) = ((*flags) | flag_val)) -// -- This macro sets the flags with the flag_val. Here flags is passed as a pointer - -#define IS_FLAG_SET(flags, test_flag) (((*flags) & (test_flag)) == (test_flag)? test_flag:0) -// -- This macro verifies whether test_flag has been set in flags. Here flags is passed as a pointer - - -#define CLR_FLAG(flags, flag_bit) ((*flags) = (*flags) & (~flag_bit)) -// -- This macro resets the specified flag_bit in the flags. Here flags is passed as a pointer - - -////////////////////////////////////////////////DATA STRUCTURES ORGANIZATION - -//Here are the data structures used for accessing mib parameters. The ioctl call includes the third parameter as a void pointer. This parameter has to be type-casted in the driver code to the corresponding structure depending upon the command type. For Ex: consider the ioctl used to get the adslLineCode type, ioctl(fd,GET_ADSL_LINE_CODE,void *struct_adslLineTableEntry). In the driver code we check on the type of the command, i.e GET_ADSL_LINE_CODE and type-cast the void pointer to struct adslLineTableEntry type. - // -#define u32 unsigned int -#define u16 unsigned short -#define s16 short -#define u8 unsigned char - - -typedef u32 AdslPerfTimeElapsed; -typedef u32 AdslPerfPrevDayCount; -typedef u32 PerfCurrentCount; -typedef u32 PerfIntervalCount; -typedef u32 AdslPerfCurrDayCount; - - -//ioctl(int fd, GET_ADSL_LINE_CODE, void *struct_adslLineTableEntry) - -typedef struct adslLineTableEntry { - int ifIndex; - int adslLineCode; - u8 flags; -} adslLineTableEntry; - -#ifdef IFXMIPS_MEI_MIB_RFC3440 -typedef struct adslLineExtTableEntry { - int ifIndex; - u16 adslLineTransAtucCap; - u16 adslLineTransAtucConfig; - u16 adslLineTransAtucActual; - int adslLineGlitePowerState; - u32 flags; -}adslLineExtTableEntry; -#endif -//ioctl(int fd, GET_ADSL_ATUC_PHY, void *struct_adslAtucPhysEntry) -#ifndef u_char -#define u_char u8 -#endif - -typedef struct adslVendorId { - u16 country_code; - u_char provider_id[4]; /* Ascii characters */ - u_char revision_info[2]; -}adslVendorId; - -typedef struct adslAtucPhysEntry { - int ifIndex; - char serial_no[32]; - union { - char vendor_id[16]; - adslVendorId vendor_info; - } vendor_id; - char version_no[16]; - u32 status; - int outputPwr; - u32 attainableRate; - u8 flags; -} adslAtucPhysEntry; - - -//ioctl(int fd, GET_ADSL_ATUR_PHY, void *struct_adslAturPhysEntry) - -typedef struct adslAturPhysEntry { - int ifIndex; - char serial_no[32]; - union { - char vendor_id[16]; - adslVendorId vendor_info; - } vendor_id; - char version_no[16]; - int SnrMgn; - u32 Attn; - u32 status; - int outputPwr; - u32 attainableRate; - u8 flags; -} adslAturPhysEntry; - - -//ioctl(int fd, GET_ADSL_ATUC_CHAN_INFO, void *struct_adslAtucChanInfo) - -typedef struct adslAtucChanInfo { - int ifIndex; - u32 interleaveDelay; - u32 currTxRate; - u32 prevTxRate; - u8 flags; -} adslAtucChanInfo; - - -//ioctl(int fd, GET_ADSL_ATUR_CHAN_INFO, void *struct_adslAturChanInfo) - -typedef struct adslAturChanInfo { - int ifIndex; - u32 interleaveDelay; - u32 currTxRate; - u32 prevTxRate; - u32 crcBlkLen; - u8 flags; -} adslAturChanInfo; - - -//ioctl(int fd, GET_ADSL_ATUC_PERF_DATA, void *struct_atucPerfDataEntry) - -typedef struct atucPerfDataEntry -{ - int ifIndex; - u32 adslAtucPerfLofs; - u32 adslAtucPerfLoss; - u32 adslAtucPerfESs; - u32 adslAtucPerfInits; - int adslAtucPerfValidIntervals; - int adslAtucPerfInvalidIntervals; - AdslPerfTimeElapsed adslAtucPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAtucPerfCurr15MinLofs; - PerfCurrentCount adslAtucPerfCurr15MinLoss; - PerfCurrentCount adslAtucPerfCurr15MinESs; - PerfCurrentCount adslAtucPerfCurr15MinInits; - AdslPerfTimeElapsed adslAtucPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAtucPerfCurr1DayLofs; - AdslPerfCurrDayCount adslAtucPerfCurr1DayLoss; - AdslPerfCurrDayCount adslAtucPerfCurr1DayESs; - AdslPerfCurrDayCount adslAtucPerfCurr1DayInits; - int adslAtucPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAtucPerfPrev1DayLofs; - AdslPerfPrevDayCount adslAtucPerfPrev1DayLoss; - AdslPerfPrevDayCount adslAtucPerfPrev1DayESs; - AdslPerfPrevDayCount adslAtucPerfPrev1DayInits; - u32 flags; -} atucPerfDataEntry; - -#ifdef IFXMIPS_MEI_MIB_RFC3440 -typedef struct atucPerfDataExtEntry - { - int ifIndex; - u32 adslAtucPerfStatFastR; - u32 adslAtucPerfStatFailedFastR; - u32 adslAtucPerfStatSesL; - u32 adslAtucPerfStatUasL; - u32 adslAtucPerfCurr15MinFastR; - u32 adslAtucPerfCurr15MinFailedFastR; - u32 adslAtucPerfCurr15MinSesL; - u32 adslAtucPerfCurr15MinUasL; - u32 adslAtucPerfCurr1DayFastR; - u32 adslAtucPerfCurr1DayFailedFastR; - u32 adslAtucPerfCurr1DaySesL; - u32 adslAtucPerfCurr1DayUasL; - u32 adslAtucPerfPrev1DayFastR; - u32 adslAtucPerfPrev1DayFailedFastR; - u32 adslAtucPerfPrev1DaySesL; - u32 adslAtucPerfPrev1DayUasL; - u32 flags; -} atucPerfDataExtEntry; - -#endif -//ioctl(int fd, GET_ADSL_ATUR_PERF_DATA, void *struct_aturPerfDataEntry) - -typedef struct aturPerfDataEntry -{ - int ifIndex; - u32 adslAturPerfLofs; - u32 adslAturPerfLoss; - u32 adslAturPerfLprs; - u32 adslAturPerfESs; - int adslAturPerfValidIntervals; - int adslAturPerfInvalidIntervals; - AdslPerfTimeElapsed adslAturPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAturPerfCurr15MinLofs; - PerfCurrentCount adslAturPerfCurr15MinLoss; - PerfCurrentCount adslAturPerfCurr15MinLprs; - PerfCurrentCount adslAturPerfCurr15MinESs; - AdslPerfTimeElapsed adslAturPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAturPerfCurr1DayLofs; - AdslPerfCurrDayCount adslAturPerfCurr1DayLoss; - AdslPerfCurrDayCount adslAturPerfCurr1DayLprs; - AdslPerfCurrDayCount adslAturPerfCurr1DayESs; - int adslAturPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAturPerfPrev1DayLofs; - AdslPerfPrevDayCount adslAturPerfPrev1DayLoss; - AdslPerfPrevDayCount adslAturPerfPrev1DayLprs; - AdslPerfPrevDayCount adslAturPerfPrev1DayESs; - u32 flags; -} aturPerfDataEntry; - -#ifdef IFXMIPS_MEI_MIB_RFC3440 -typedef struct aturPerfDataExtEntry - { - int ifIndex; - u32 adslAturPerfStatSesL; - u32 adslAturPerfStatUasL; - u32 adslAturPerfCurr15MinSesL; - u32 adslAturPerfCurr15MinUasL; - u32 adslAturPerfCurr1DaySesL; - u32 adslAturPerfCurr1DayUasL; - u32 adslAturPerfPrev1DaySesL; - u32 adslAturPerfPrev1DayUasL; - u32 flags; -} aturPerfDataExtEntry; -#endif -//ioctl(int fd, GET_ADSL_ATUC_INTVL_INFO, void *struct_adslAtucInvtInfo) - -typedef struct adslAtucIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount intervalLOF; - PerfIntervalCount intervalLOS; - PerfIntervalCount intervalES; - PerfIntervalCount intervalInits; - int intervalValidData; - u8 flags; -} adslAtucIntvlInfo; - -#ifdef IFXMIPS_MEI_MIB_RFC3440 -typedef struct adslAtucInvtlExtInfo - { - int ifIndex; - int IntervalNumber; - u32 adslAtucIntervalFastR; - u32 adslAtucIntervalFailedFastR; - u32 adslAtucIntervalSesL; - u32 adslAtucIntervalUasL; - u32 flags; -} adslAtucInvtlExtInfo; -#endif -//ioctl(int fd, GET_ADSL_ATUR_INTVL_INFO, void *struct_adslAturInvtlInfo) - -typedef struct adslAturIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount intervalLOF; - PerfIntervalCount intervalLOS; - PerfIntervalCount intervalLPR; - PerfIntervalCount intervalES; - int intervalValidData; - u8 flags; -} adslAturIntvlInfo; - -#ifdef IFXMIPS_MEI_MIB_RFC3440 -typedef struct adslAturInvtlExtInfo - { - int ifIndex; - int IntervalNumber; - u32 adslAturIntervalSesL; - u32 adslAturIntervalUasL; - u32 flags; -} adslAturInvtlExtInfo; -#endif -//ioctl(int fd, GET_ADSL_ATUC_CHAN_PERF_DATA, void *struct_atucChannelPerfDataEntry) - -typedef struct atucChannelPerfDataEntry -{ - int ifIndex; - u32 adslAtucChanReceivedBlks; - u32 adslAtucChanTransmittedBlks; - u32 adslAtucChanCorrectedBlks; - u32 adslAtucChanUncorrectBlks; - int adslAtucChanPerfValidIntervals; - int adslAtucChanPerfInvalidIntervals; - AdslPerfTimeElapsed adslAtucChanPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAtucChanPerfCurr15MinReceivedBlks; - PerfCurrentCount adslAtucChanPerfCurr15MinTransmittedBlks; - PerfCurrentCount adslAtucChanPerfCurr15MinCorrectedBlks; - PerfCurrentCount adslAtucChanPerfCurr15MinUncorrectBlks; - AdslPerfTimeElapsed adslAtucChanPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayReceivedBlks; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayTransmittedBlks; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayCorrectedBlks; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayUncorrectBlks; - int adslAtucChanPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayReceivedBlks; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayTransmittedBlks; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayCorrectedBlks; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayUncorrectBlks; - u32 flags; -}atucChannelPerfDataEntry; - - -//ioctl(int fd, GET_ADSL_ATUR_CHAN_PERF_DATA, void *struct_aturChannelPerfDataEntry) - -typedef struct aturChannelPerfDataEntry -{ - int ifIndex; - u32 adslAturChanReceivedBlks; - u32 adslAturChanTransmittedBlks; - u32 adslAturChanCorrectedBlks; - u32 adslAturChanUncorrectBlks; - int adslAturChanPerfValidIntervals; - int adslAturChanPerfInvalidIntervals; - AdslPerfTimeElapsed adslAturChanPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAturChanPerfCurr15MinReceivedBlks; - PerfCurrentCount adslAturChanPerfCurr15MinTransmittedBlks; - PerfCurrentCount adslAturChanPerfCurr15MinCorrectedBlks; - PerfCurrentCount adslAturChanPerfCurr15MinUncorrectBlks; - AdslPerfTimeElapsed adslAturChanPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayReceivedBlks; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayTransmittedBlks; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayCorrectedBlks; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayUncorrectBlks; - int adslAturChanPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayReceivedBlks; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayTransmittedBlks; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayCorrectedBlks; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayUncorrectBlks; - u32 flags; -} aturChannelPerfDataEntry; - - -//ioctl(int fd, GET_ADSL_ATUC_CHAN_INTVL_INFO, void *struct_adslAtucChanIntvlInfo) - -typedef struct adslAtucChanIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount chanIntervalRecvdBlks; - PerfIntervalCount chanIntervalXmitBlks; - PerfIntervalCount chanIntervalCorrectedBlks; - PerfIntervalCount chanIntervalUncorrectBlks; - int intervalValidData; - u8 flags; -} adslAtucChanIntvlInfo; - - -//ioctl(int fd, GET_ADSL_ATUR_CHAN_INTVL_INFO, void *struct_adslAturChanIntvlInfo) - -typedef struct adslAturChanIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount chanIntervalRecvdBlks; - PerfIntervalCount chanIntervalXmitBlks; - PerfIntervalCount chanIntervalCorrectedBlks; - PerfIntervalCount chanIntervalUncorrectBlks; - int intervalValidData; - u8 flags; -} adslAturChanIntvlInfo; - - -//ioctl(int fd, GET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry) -//ioctl(int fd, SET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry) - -typedef struct adslLineAlarmConfProfileEntry - { - unsigned char adslLineAlarmConfProfileName[32]; - int adslAtucThresh15MinLofs; - int adslAtucThresh15MinLoss; - int adslAtucThresh15MinESs; - u32 adslAtucThreshFastRateUp; - u32 adslAtucThreshInterleaveRateUp; - u32 adslAtucThreshFastRateDown; - u32 adslAtucThreshInterleaveRateDown; - int adslAtucInitFailureTrapEnable; - int adslAturThresh15MinLofs; - int adslAturThresh15MinLoss; - int adslAturThresh15MinLprs; - int adslAturThresh15MinESs; - u32 adslAturThreshFastRateUp; - u32 adslAturThreshInterleaveRateUp; - u32 adslAturThreshFastRateDown; - u32 adslAturThreshInterleaveRateDown; - int adslLineAlarmConfProfileRowStatus; - u32 flags; -} adslLineAlarmConfProfileEntry; - -#ifdef IFXMIPS_MEI_MIB_RFC3440 -typedef struct adslLineAlarmConfProfileExtEntry - { - u8 adslLineAlarmConfProfileExtName[32]; - u32 adslAtucThreshold15MinFailedFastR; - u32 adslAtucThreshold15MinSesL; - u32 adslAtucThreshold15MinUasL; - u32 adslAturThreshold15MinSesL; - u32 adslAturThreshold15MinUasL; - u32 flags; -} adslLineAlarmConfProfileExtEntry; -#endif -//TRAPS - -/* The following Data Sturctures are added to support the WEB related parameters for ADSL Statistics */ -typedef struct adslLineStatus - { - int adslModemStatus; - u32 adslModeSelected; - int adslAtucThresh15MinESs; - int adslTrellisCodeEnable; - int adslLatency; - u8 flags; - } adslLineStatusInfo; - -typedef struct adslLineRate - { - u32 adslDataRateds; - u32 adslDataRateus; - u32 adslATTNDRds; - u32 adslATTNDRus; - u8 flags; - } adslLineRateInfo; - -typedef struct adslLineInfo - { - u32 adslInterleaveDepthds; - u32 adslInterleaveDepthus; - u32 adslLATNds; - u32 adslLATNus; - u32 adslSATNds; - u32 adslSATNus; - int adslSNRMds; - int adslSNRMus; - int adslACATPds; - int adslACATPus; - u32 flags; - } adslLineInfo; - -typedef struct adslNearEndPerfStats - { - u32 adslSuperFrames; - u32 adslneLOS; - u32 adslneLOF; - u32 adslneLPR; - u32 adslneNCD; - u32 adslneLCD; - u32 adslneCRC; - u32 adslneRSCorr; - u32 adslneFECS; - u32 adslneES; - u32 adslneSES; - u32 adslneLOSS; - u32 adslneUAS; - u32 adslneHECErrors; - u32 flags; - } adslNearEndPerfStats; - -typedef struct adslFarEndPerfStats - { - u32 adslfeLOS; - u32 adslfeLOF; - u32 adslfeLPR; - u32 adslfeNCD; - u32 adslfeLCD; - u32 adslfeCRC; - u32 adslfeRSCorr; - u32 adslfeFECS; - u32 adslfeES; - u32 adslfeSES; - u32 adslfeLOSS; - u32 adslfeUAS; - u32 adslfeHECErrors; - u32 flags; - } adslFarEndPerfStats; - -/* The number of tones (and hence indexes) is dependent on the ADSL mode - G.992.1, G.992.2, G.992.3, * G.992.4 and G.992.5 */ -typedef struct adslATURSubcarrierInfo { - int ifindex; - u16 HLINSCds; - u16 HLINpsds[1024];/* Even index = real part; Odd Index - = imaginary part for each tone */ - u16 HLOGMTds; - u16 HLOGpsds[512]; - u16 QLNMTds; - u16 QLNpsds[512]; - u16 SNRMTds; - u16 SNRpsds[512]; - u16 BITpsds[512]; - s16 GAINpsds[512]; /* Signed value in 0.1dB units. i.e dB * 10. - Needs to be converted into linear scale*/ - u16 flags; -}adslATURSubcarrierInfo; - -typedef struct adslATUCSubcarrierInfo { - int ifindex; - u16 HLINSCus; - u16 HLINpsus[128];/* Even index = real part; Odd Index - = imaginary part for each tone */ - u16 HLOGMTus; - u16 HLOGpsus[64]; - u16 QLNMTus; - u16 QLNpsus[64]; - u16 SNRMTus; - u16 SNRpsus[64]; - u16 BITpsus[64]; - s16 GAINpsus[64]; /* Signed value in 0.1dB units. i.e dB * 10. - Needs to be converted into linear scale*/ - u16 flags; -}adslATUCSubcarrierInfo; - -#ifndef u_int16 -#define u_int16 u16 -#endif - -typedef struct adslInitStats { - u_int16 FullInitializationCount; - u_int16 FailedFullInitializationCount; - u_int16 LINIT_Errors; - u_int16 Init_Timeouts; -}adslInitStats; - -typedef struct adslPowerSpectralDensity { - int ACTPSDds; - int ACTPSDus; -}adslPowerSpectralDensity; - -//ioctl(int fd, ADSL_ATUR_TRAPS, void *uint16_flags) -typedef union structpts { - adslLineTableEntry * adslLineTableEntry_pt; - adslAtucPhysEntry * adslAtucPhysEntry_pt; - adslAturPhysEntry * adslAturPhysEntry_pt; - adslAtucChanInfo * adslAtucChanInfo_pt; - adslAturChanInfo * adslAturChanInfo_pt; - atucPerfDataEntry * atucPerfDataEntry_pt; - aturPerfDataEntry * aturPerfDataEntry_pt; - adslAtucIntvlInfo * adslAtucIntvlInfo_pt; - adslAturIntvlInfo * adslAturIntvlInfo_pt; - atucChannelPerfDataEntry * atucChannelPerfDataEntry_pt; - aturChannelPerfDataEntry * aturChannelPerfDataEntry_pt; - adslAtucChanIntvlInfo * adslAtucChanIntvlInfo_pt; - adslAturChanIntvlInfo * adslAturChanIntvlInfo_pt; - adslLineAlarmConfProfileEntry * adslLineAlarmConfProfileEntry_pt; - // RFC 3440 - - #ifdef IFXMIPS_MEI_MIB_RFC3440 - adslLineExtTableEntry * adslLineExtTableEntry_pt; - atucPerfDataExtEntry * atucPerfDataExtEntry_pt; - adslAtucInvtlExtInfo * adslAtucInvtlExtInfo_pt; - aturPerfDataExtEntry * aturPerfDataExtEntry_pt; - adslAturInvtlExtInfo * adslAturInvtlExtInfo_pt; - adslLineAlarmConfProfileExtEntry * adslLineAlarmConfProfileExtEntry_pt; - #endif - adslLineStatusInfo * adslLineStatusInfo_pt; - adslLineRateInfo * adslLineRateInfo_pt; - adslLineInfo * adslLineInfo_pt; - adslNearEndPerfStats * adslNearEndPerfStats_pt; - adslFarEndPerfStats * adslFarEndPerfStats_pt; - adslATUCSubcarrierInfo * adslATUCSubcarrierInfo_pt; - adslATURSubcarrierInfo * adslATURSubcarrierInfo_pt; - adslPowerSpectralDensity * adslPowerSpectralDensity_pt; -}structpts; - -#endif /* ] __IFXMIPS_MEI_APP_IOCTL_H */ diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_bsp.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_bsp.h deleted file mode 100644 index c34662013c..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_bsp.h +++ /dev/null @@ -1,308 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_mei_bsp.h -** PROJECT : Danube -** MODULES : MEI -** -** DATE : 1 Jan 2006 -** AUTHOR : TC Chen -** DESCRIPTION : MEI Driver -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Version $Date $Author $Comment -*******************************************************************************/ -#ifndef _IFXMIPS_MEI_BSP_H_ -#define _IFXMIPS_MEI_BSP_H_ - -/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ -#define MEI_DATA_XFR_OFFSET (0x0000) -#define MEI_VERSION_OFFSET (0x0004) -#define MEI_ARC_GP_STAT_OFFSET (0x0008) -#define MEI_DATA_XFR_STAT_OFFSET (0x000C) -#define MEI_XFR_ADDR_OFFSET (0x0010) -#define MEI_MAX_WAIT_OFFSET (0x0014) -#define MEI_TO_ARC_INT_OFFSET (0x0018) -#define ARC_TO_MEI_INT_OFFSET (0x001C) -#define ARC_TO_MEI_INT_MASK_OFFSET (0x0020) -#define MEI_DEBUG_WAD_OFFSET (0x0024) -#define MEI_DEBUG_RAD_OFFSET (0x0028) -#define MEI_DEBUG_DATA_OFFSET (0x002C) -#define MEI_DEBUG_DEC_OFFSET (0x0030) -#define MEI_CONFIG_OFFSET (0x0034) -#define MEI_RST_CONTROL_OFFSET (0x0038) -#define MEI_DBG_MASTER_OFFSET (0x003C) -#define MEI_CLK_CONTROL_OFFSET (0x0040) -#define MEI_BIST_CONTROL_OFFSET (0x0044) -#define MEI_BIST_STAT_OFFSET (0x0048) -#define MEI_XDATA_BASE_SH_OFFSET (0x004c) -#define MEI_XDATA_BASE_OFFSET (0x0050) -#define MEI_XMEM_BAR_BASE_OFFSET (0x0054) -#define MEI_XMEM_BAR0_OFFSET (0x0054) -#define MEI_XMEM_BAR1_OFFSET (0x0058) -#define MEI_XMEM_BAR2_OFFSET (0x005C) -#define MEI_XMEM_BAR3_OFFSET (0x0060) -#define MEI_XMEM_BAR4_OFFSET (0x0064) -#define MEI_XMEM_BAR5_OFFSET (0x0068) -#define MEI_XMEM_BAR6_OFFSET (0x006C)) -#define MEI_XMEM_BAR7_OFFSET (0x0070) -#define MEI_XMEM_BAR8_OFFSET (0x0074) -#define MEI_XMEM_BAR9_OFFSET (0x0078) -#define MEI_XMEM_BAR10_OFFSET (0x007C) -#define MEI_XMEM_BAR11_OFFSET (0x0080) -#define MEI_XMEM_BAR12_OFFSET (0x0084) -#define MEI_XMEM_BAR13_OFFSET (0x0088) -#define MEI_XMEM_BAR14_OFFSET (0x008C) -#define MEI_XMEM_BAR15_OFFSET (0x0090) -#define MEI_XMEM_BAR16_OFFSET (0x0094) - -#define WHILE_DELAY 20000 -/* -** Define where in ME Processor's memory map the Stratify chip lives -*/ - -#define MAXSWAPSIZE 8 * 1024 //8k *(32bits) - -// Mailboxes -#define MSG_LENGTH 16 // x16 bits -#define YES_REPLY 1 -#define NO_REPLY 0 - -#define CMV_TIMEOUT 1000 //jiffies - -// Block size per BAR -#define SDRAM_SEGMENT_SIZE (64*1024) -// Number of Bar registers -#define MAX_BAR_REGISTERS (17) - -#define XDATA_REGISTER (15) - -#define IFXMIPS_MEI_IOCTL_CMV_WINHOST IFX_ADSL_IOC_CMV_WINHOST - -#define IFXMIPS_MEI_IOCTL_CMV_READ IFX_ADSL_IOC_CMV_READ -#define IFXMIPS_MEI_IOCTL_CMV_WRITE IFX_ADSL_IOC_CMV_WRITE - -#define IFXMIPS_MEI_IOCTL_GET_BASE_ADDRESS IFX_ADSL_IOC_GET_BASE_ADDRESS - -// ARC register addresss -#define ARC_STATUS 0x0 -#define ARC_LP_START 0x2 -#define ARC_LP_END 0x3 -#define ARC_DEBUG 0x5 -#define ARC_INT_MASK 0x10A - -#define IRAM0_BASE (0x00000) -#define IRAM1_BASE (0x04000) -#define BRAM_BASE (0x0A000) - -#define ADSL_BASE (0x20000) -#define CRI_BASE (ADSL_BASE + 0x11F00) -#define CRI_CCR0 (CRI_BASE + 0x00) -#define CRI_RST (CRI_BASE + 0x04*4) -#define ADSL_DILV_BASE (ADSL_BASE+0x20000) - -// -#define IRAM0_ADDR_BIT_MASK 0xFFF -#define IRAM1_ADDR_BIT_MASK 0xFFF -#define BRAM_ADDR_BIT_MASK 0xFFF -#define RX_DILV_ADDR_BIT_MASK 0x1FFF - -/*** Bit definitions ***/ - -#define FALSE 0 -#define TRUE 1 -#define BIT0 1<<0 -#define BIT1 1<<1 -#define BIT2 1<<2 -#define BIT3 1<<3 -#define BIT4 1<<4 -#define BIT5 1<<5 -#define BIT6 1<<6 -#define BIT7 1<<7 -#define BIT8 1<<8 -#define BIT9 1<<9 -#define BIT10 1<<10 -#define BIT11 1<<11 -#define BIT12 1<<12 -#define BIT13 1<<13 -#define BIT14 1<<14 -#define BIT15 1<<15 -#define BIT16 1<<16 -#define BIT17 1<<17 -#define BIT18 1<<18 -#define BIT19 1<<19 -#define BIT20 1<<20 -#define BIT21 1<<21 -#define BIT22 1<<22 -#define BIT23 1<<23 -#define BIT24 1<<24 -#define BIT25 1<<25 -#define BIT26 1<<26 -#define BIT27 1<<27 -#define BIT28 1<<28 -#define BIT29 1<<29 -#define BIT30 1<<30 -#define BIT31 1<<31 - -// CRI_CCR0 Register definitions -#define CLK_2M_MODE_ENABLE BIT6 -#define ACL_CLK_MODE_ENABLE BIT4 -#define FDF_CLK_MODE_ENABLE BIT2 -#define STM_CLK_MODE_ENABLE BIT0 - -// CRI_RST Register definitions -#define FDF_SRST BIT3 -#define MTE_SRST BIT2 -#define FCI_SRST BIT1 -#define AAI_SRST BIT0 - -// MEI_TO_ARC_INTERRUPT Register definitions -#define MEI_TO_ARC_INT1 BIT3 -#define MEI_TO_ARC_INT0 BIT2 -#define MEI_TO_ARC_CS_DONE BIT1 //need to check -#define MEI_TO_ARC_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT Register definitions -#define ARC_TO_MEI_INT1 BIT8 -#define ARC_TO_MEI_INT0 BIT7 -#define ARC_TO_MEI_CS_REQ BIT6 -#define ARC_TO_MEI_DBG_DONE BIT5 -#define ARC_TO_MEI_MSGACK BIT4 -#define ARC_TO_MEI_NO_ACCESS BIT3 -#define ARC_TO_MEI_CHECK_AAITX BIT2 -#define ARC_TO_MEI_CHECK_AAIRX BIT1 -#define ARC_TO_MEI_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT_MASK Register definitions -#define GP_INT1_EN BIT8 -#define GP_INT0_EN BIT7 -#define CS_REQ_EN BIT6 -#define DBG_DONE_EN BIT5 -#define MSGACK_EN BIT4 -#define NO_ACC_EN BIT3 -#define AAITX_EN BIT2 -#define AAIRX_EN BIT1 -#define MSGAV_EN BIT0 - -#define MEI_SOFT_RESET BIT0 - -#define HOST_MSTR BIT0 - -#define JTAG_MASTER_MODE 0x0 -#define MEI_MASTER_MODE HOST_MSTR - -// MEI_DEBUG_DECODE Register definitions -#define MEI_DEBUG_DEC_MASK (0x3) -#define MEI_DEBUG_DEC_AUX_MASK (0x0) -#define MEI_DEBUG_DEC_DMP1_MASK (0x1) -#define MEI_DEBUG_DEC_DMP2_MASK (0x2) -#define MEI_DEBUG_DEC_CORE_MASK (0x3) - -#define AUX_STATUS (0x0) -// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate -// page swap requests. -#define MEI_TO_ARC_MAILBOX (0xDFD0) -#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C) - -#define ARC_TO_MEI_MAILBOX (0xDFA0) -#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C) - -// Codeswap request messages are indicated by setting BIT31 -#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000) - -// Clear Eoc messages received are indicated by setting BIT17 -#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000) - -/* -** Swap page header -*/ -// Page must be loaded at boot time if size field has BIT31 set -#define BOOT_FLAG (BIT31) -#define BOOT_FLAG_MASK ~BOOT_FLAG - -#define FREE_RELOAD 1 -#define FREE_SHOWTIME 2 -#define FREE_ALL 3 - -// marcos -#define IFXMIPS_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data);} while (0) -#define IFXMIPS_READ_REGISTER_L(addr) (*((volatile u32*)(addr))) -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - -#define ALIGN_SIZE ( 1L<<10 ) //1K size align -#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) ) - -// swap marco -#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);} -#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);} - -// Swap page header describes size in 32-bit words, load location, and image offset -// for program and/or data segments -typedef struct _arc_swp_page_hdr { - u32 p_offset; //Offset bytes of progseg from beginning of image - u32 p_dest; //Destination addr of progseg on processor - u32 p_size; //Size in 32-bitwords of program segment - u32 d_offset; //Offset bytes of dataseg from beginning of image - u32 d_dest; //Destination addr of dataseg on processor - u32 d_size; //Size in 32-bitwords of data segment -} ARC_SWP_PAGE_HDR; - -/* -** Swap image header -*/ -#define GET_PROG 0 // Flag used for program mem segment -#define GET_DATA 1 // Flag used for data mem segment - -// Image header contains size of image, checksum for image, and count of -// page headers. Following that are 'count' page headers followed by -// the code and/or data segments to be loaded -typedef struct _arc_img_hdr { - u32 size; // Size of binary image in bytes - u32 checksum; // Checksum for image - u32 count; // Count of swp pages in image - ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy -} ARC_IMG_HDR; - -typedef struct smmu_mem_info { - int type; - unsigned long nCopy; - unsigned long size; - unsigned char *address; - unsigned char *org_address; -} smmu_mem_info_t; - -typedef struct ifxmips_mei_device_private { - int modem_ready; - int arcmsgav; - int cmv_reply; - int cmv_waiting; - // Mei to ARC CMV count, reply count, ARC Indicator count - int indicator_count; - int cmv_count; - int reply_count; - unsigned long image_size; - int nBar; - u16 Recent_indicator[MSG_LENGTH]; - - u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4))); - - smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS]; - ARC_IMG_HDR *img_hdr; - // to wait for arc cmv reply, sleep on wait_queue_arcmsgav; - wait_queue_head_t wait_queue_arcmsgav; - wait_queue_head_t wait_queue_modemready; - MEI_mutex_t mei_cmv_sema; -} ifxmips_mei_device_private_t; - -#endif //_IFXMIPS_MEI_BSP_H_ diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_ioctl.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_ioctl.h deleted file mode 100644 index d11f04ea97..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_ioctl.h +++ /dev/null @@ -1,734 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_mei_ioctl.h -** PROJECT : Danube -** MODULES : MEI -** -** DATE : 1 Jan 2006 -** AUTHOR : TC Chen -** DESCRIPTION : MEI Driver -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Version $Date $Author $Comment -*******************************************************************************/ -#ifndef _IFXMIPS_MEI_IOCTL_H -#define _IFXMIPS_MEI_IOCTL_H - -///////////////////////////////////////////////////////////////////////////////////////////////////// -#define PCM_BUFF_SIZE 1024 //bytes -// interrupt numbers - -#if !(defined(_IFXMIPS_ADSL_APP) || defined (_AMAZON_ADSL_APP)) - -// Number of intervals -#define INTERVAL_NUM 192 //two days -typedef struct ifxmips_mei_mib { - struct list_head list; - struct timeval start_time; //start of current interval - - int AtucPerfLof; - int AtucPerfLos; - int AtucPerfEs; - int AtucPerfInit; - - int AturPerfLof; - int AturPerfLos; - int AturPerfLpr; - int AturPerfEs; - - int AturChanPerfRxBlk; - int AturChanPerfTxBlk; - int AturChanPerfCorrBlk; - int AturChanPerfUncorrBlk; - - //RFC-3440 - int AtucPerfStatFastR; - int AtucPerfStatFailedFastR; - int AtucPerfStatSesL; - int AtucPerfStatUasL; - int AturPerfStatSesL; - int AturPerfStatUasL; -} ifxmips_mei_mib; - -typedef struct adslChanPrevTxRate { - u32 adslAtucChanPrevTxRate; - u32 adslAturChanPrevTxRate; -} adslChanPrevTxRate; - -typedef struct adslPhysCurrStatus { - u32 adslAtucCurrStatus; - u32 adslAturCurrStatus; -} adslPhysCurrStatus; - -typedef struct ChanType { - int interleave; - int fast; - int bearchannel0; - int bearchannel1; -} ChanType; - -typedef struct mib_previous_read { - u16 ATUC_PERF_ESS; - u16 ATUR_PERF_ESS; - u32 ATUR_CHAN_RECV_BLK; - u16 ATUR_CHAN_CORR_BLK_INTL; - u16 ATUR_CHAN_CORR_BLK_FAST; - u16 ATUR_CHAN_UNCORR_BLK_INTL; - u16 ATUR_CHAN_UNCORR_BLK_FAST; - u16 ATUC_PERF_STAT_FASTR; - u16 ATUC_PERF_STAT_FAILED_FASTR; - u16 ATUC_PERF_STAT_SESL; - u16 ATUC_PERF_STAT_UASL; - u16 ATUR_PERF_STAT_SESL; -} mib_previous_read; - -typedef struct mib_flags_pretime { - struct timeval ATUC_PERF_LOSS_PTIME; - struct timeval ATUC_PERF_LOFS_PTIME; - struct timeval ATUR_PERF_LOSS_PTIME; - struct timeval ATUR_PERF_LOFS_PTIME; - struct timeval ATUR_PERF_LPR_PTIME; -} mib_flags_pretime; - - // cmv message structures -#define MP_PAYLOAD_SIZE 12 -typedef struct mpmessage { - u16 iFunction; - u16 iGroup; - u16 iAddress; - u16 iIndex; - u16 iPayload[MP_PAYLOAD_SIZE]; -} MPMessage; -#endif - -typedef struct meireg { - u32 iAddress; - u32 iData; -} meireg; - -#define MEIDEBUG_BUFFER_SIZES 50 -typedef struct meidebug { - u32 iAddress; - u32 iCount; - u32 buffer[MEIDEBUG_BUFFER_SIZES]; -} meidebug; - -//============================================================================== -// Group definitions -//============================================================================== -#define OPTN 5 -#define CNFG 8 -#define CNTL 1 -#define STAT 2 -#define RATE 6 -#define PLAM 7 -#define INFO 3 -#define TEST 4 -//============================================================================== -// Opcode definitions -//============================================================================== -#define H2D_CMV_READ 0x00 -#define H2D_CMV_WRITE 0x04 -#define H2D_CMV_INDICATE_REPLY 0x10 -#define H2D_ERROR_OPCODE_UNKNOWN 0x20 -#define H2D_ERROR_CMV_UNKNOWN 0x30 - -#define D2H_CMV_READ_REPLY 0x01 -#define D2H_CMV_WRITE_REPLY 0x05 -#define D2H_CMV_INDICATE 0x11 -#define D2H_ERROR_OPCODE_UNKNOWN 0x21 -#define D2H_ERROR_CMV_UNKNOWN 0x31 -#define D2H_ERROR_CMV_READ_NOT_AVAILABLE 0x41 -#define D2H_ERROR_CMV_WRITE_ONLY 0x51 -#define D2H_ERROR_CMV_READ_ONLY 0x61 - -#define H2D_DEBUG_READ_DM 0x02 -#define H2D_DEBUG_READ_PM 0x06 -#define H2D_DEBUG_WRITE_DM 0x0a -#define H2D_DEBUG_WRITE_PM 0x0e - -#define D2H_DEBUG_READ_DM_REPLY 0x03 -#define D2H_DEBUG_READ_FM_REPLY 0x07 -#define D2H_DEBUG_WRITE_DM_REPLY 0x0b -#define D2H_DEBUG_WRITE_FM_REPLY 0x0f -#define D2H_ERROR_ADDR_UNKNOWN 0x33 - -#define D2H_AUTONOMOUS_MODEM_READY_MSG 0xf1 -//============================================================================== -// INFO register address field definitions -//============================================================================== - -#define INFO_TxState 0 -#define INFO_RxState 1 -#define INFO_TxNextState 2 -#define INFO_RxNextState 3 -#define INFO_TxStateJumpFrom 4 -#define INFO_RxStateJumpFrom 5 - -#define INFO_ReverbSnrBuf 8 -#define INFO_ReverbEchoSnrBuf 9 -#define INFO_MedleySnrBuf 10 -#define INFO_RxShowtimeSnrBuf 11 -#define INFO_DECdelay 12 -#define INFO_DECExponent 13 -#define INFO_DECTaps 14 -#define INFO_AECdelay 15 -#define INFO_AECExponent 16 -#define INFO_AECTaps 17 -#define INFO_TDQExponent 18 -#define INFO_TDQTaps 19 -#define INFO_FDQExponent 20 -#define INFO_FDQTaps 21 -#define INFO_USBat 22 -#define INFO_DSBat 23 -#define INFO_USFineGains 24 -#define INFO_DSFineGains 25 -#define INFO_BitloadFirstChannel 26 -#define INFO_BitloadLastChannel 27 -#define INFO_PollEOCData 28 // CO specific -#define INFO_CSNRMargin 29 // CO specific -#define INFO_RCMsgs1 30 -#define INFO_RMsgs1 31 -#define INFO_RMsgRA 32 -#define INFO_RCMsgRA 33 -#define INFO_RMsg2 34 -#define INFO_RCMsg2 35 -#define INFO_BitLoadOK 36 -#define INFO_RCRates1 37 -#define INFO_RRates1Tab 38 -#define INFO_RMsgs1Tab 39 -#define INFO_RMsgRATab 40 -#define INFO_RRatesRA 41 -#define INFO_RCRatesRA 42 -#define INFO_RRates2 43 -#define INFO_RCRates2 44 -#define INFO_PackedRMsg2 45 -#define INFO_RxBitSwapFlag 46 -#define INFO_TxBitSwapFlag 47 -#define INFO_ShowtimeSNRUpdateCount 48 -#define INFO_ShowtimeFDQUpdateCount 49 -#define INFO_ShowtimeDECUpdateCount 50 -#define INFO_CopyRxBuffer 51 -#define INFO_RxToneBuf 52 -#define INFO_TxToneBuf 53 -#define INFO_Version 54 -#define INFO_TimeStamp 55 -#define INFO_feVendorID 56 -#define INFO_feSerialNum 57 -#define INFO_feVersionNum 58 -#define INFO_BulkMemory 59 //Points to start of bulk memory -#define INFO_neVendorID 60 -#define INFO_neVersionNum 61 -#define INFO_neSerialNum 62 - -//============================================================================== -// RATE register address field definitions -//============================================================================== - -#define RATE_UsRate 0 -#define RATE_DsRate 1 - -//============================================================================== -// PLAM (Physical Layer Management) register address field definitions -// (See G997.1 for reference) -//============================================================================== - - // /// - // Failure Flags /// - // /// - -#define PLAM_NearEndFailureFlags 0 -#define PLAM_FarEndFailureFlags 1 - - // /// - // Near End Failure Flags Bit Definitions /// - // /// - -// ADSL Failures /// -#define PLAM_LOS_FailureBit 0x0001 -#define PLAM_LOF_FailureBit 0x0002 -#define PLAM_LPR_FailureBit 0x0004 -#define PLAM_RFI_FailureBit 0x0008 - -// ATM Failures /// -#define PLAM_NCD_LP0_FailureBit 0x0010 -#define PLAM_NCD_LP1_FailureBit 0x0020 -#define PLAM_LCD_LP0_FailureBit 0x0040 -#define PLAM_LCD_LP1_FailureBit 0x0080 - -#define PLAM_NCD_BC0_FailureBit 0x0100 -#define PLAM_NCD_BC1_FailureBit 0x0200 -#define PLAM_LCD_BC0_FailureBit 0x0400 -#define PLAM_LCD_BC1_FailureBit 0x0800 - // /// - // Performance Counts /// - // /// - -#define PLAM_NearEndCrcCnt 2 -#define PLAM_CorrectedRSErrors 3 - -#define PLAM_NearEndECSCnt 6 -#define PLAM_NearEndESCnt 7 -#define PLAM_NearEndSESCnt 8 -#define PLAM_NearEndLOSSCnt 9 -#define PLAM_NearEndUASLCnt 10 - -#define PLAM_NearEndHECErrCnt 11 - -#define PLAM_NearEndHECTotCnt 16 -#define PLAM_NearEndCellTotCnt 18 -#define PLAM_NearEndSfCntLSW 20 -#define PLAM_NearEndSfCntMSW 21 - -#define PLAM_FarEndFebeCnt 24 - -#define PLAM_FarEndFecCnt 28 - -#define PLAM_FarEndFECSCnt 32 -#define PLAM_FarEndESCnt 33 -#define PLAM_FarEndSESCnt 34 -#define PLAM_FarEndLOSSCnt 35 -#define PLAM_FarEndUASLCnt 36 - -#define PLAM_FarEndHECErrCnt 37 - -#define PLAM_FarEndHECTotCnt 41 - -#define PLAM_FarEndCellTotCnt 43 - -#define PLAM_SNRMargin_0_1db 45 - -#define PLAM_SNRMargin 46 - -//============================================================================== -// CNTL register address and bit field definitions -//============================================================================== - -#define CNTL_ModemControl 0 - -#define CNTL_ModemReset 0x0 -#define CNTL_ModemStart 0x2 - -//============================================================================== -// STAT register address and bit field definitions -//============================================================================== - -#define STAT_MacroState 0 -#define STAT_Mode 1 -#define STAT_DMTFramingMode 2 -#define STAT_SleepState 3 -#define STAT_Misc 4 -#define STAT_FailureState 5 - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // STAT_OLRStatus provides status of OLR - //16-bit STAT_OLRStatus_DS - // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted - // [3:2]: Reserved - // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA) - // [7:6]: Reserved - // [10:8]: >0=Request. 0=not. For DS, # of request transmissions/retransmissions (3 bits). - // [11]: 1=Receive Response, 0=not - // [15:12]: Reserved - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /// -#define STAT_OLRStatus_DS 6 - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // STAT_OLRStatus provides status of OLR - // 16-bit STAT_OLRStatus_US CMV - // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted - // [3:2]: Reserved - // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA) - // [7:6]: Reserved - // [8]: 1=Request Received. 0=not. - // [10:9]: Reserved - // [11]: 1=Response Sent, 0=not - // [15:12]: Reserved - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/// -#define STAT_OLRStatus_US 7 - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // STAT_PMStatus provides status of PM - // 16-bit STAT_PMStatus CMV - // [1:0] : PM Status 00=IDLE, 01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted - // [2] : 0=ATU_R initiated PM; 1 = ATU_C initiated PM - // [3]: Reserved - // [5:4]: PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim) - // [7:6]: Reserved - // [10:8]: >0=Request. 0=not. # of request transmissions/retransmissions (3 bits). - // [11]: 1=Response, 0=not - // [15:12]: Reserved - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /// -#define STAT_PMStatus 8 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError - // [3:0]: OLR/PM response reason code - // [7:4]: OLR/PM Internal error code - // [15:8]: OLR/PM Reserved for future - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /// -#define STAT_OLRError_DS 9 -#define STAT_OLRError_US 10 -#define STAT_PMError 11 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_MacroState -// MacroState reflects the high level state of the modem - -#define STAT_InitState 0x0000 -#define STAT_ReadyState 0x0001 -#define STAT_FailState 0x0002 -#define STAT_IdleState 0x0003 -#define STAT_QuietState 0x0004 -#define STAT_GhsState 0x0005 -#define STAT_FullInitState 0x0006 -#define STAT_ShowTimeState 0x0007 -#define STAT_FastRetrainState 0x0008 -#define STAT_LoopDiagMode 0x0009 -#define STAT_ShortInit 0x000A // Bis short initialization /// - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_Mode -// ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use -// G.Hs or some other mechanism to negotiate the specific mode of operation. -// The OPTN_modeControl CMV is used to select a set of desired modes. -// The STAT_Mode CMV indicates which mode was actually selected. - -#define STAT_ConfigMode_T1413 0x0001 -#define STAT_ConfigMode_G992_2_AB 0x0002 -#define STAT_ConfigMode_G992_1_A 0x0004 -#define STAT_ConfigMode_G992_1_B 0x0008 -#define STAT_ConfigMode_G992_1_C 0x0010 -#define STAT_ConfigMode_G992_2_C 0x0020 - -#define STAT_ConfigMode_G992_3_A 0x0100 -#define STAT_ConfigMode_G992_3_B 0x0200 -#define STAT_ConfigMode_G992_3_I 0x0400 -#define STAT_ConfigMode_G992_3_J 0x0800 -#define STAT_ConfigMode_G992_3_L 0x1000 - -#define STAT_ConfigMode_G992_4_A 0x2000 -#define STAT_ConfigMode_G992_4_I 0x4000 - -#define STAT_ConfigMode_G992_5 0x8000 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_DMTFramingMode -// FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode -// status is not applicable in BIS mode and its value is undefined -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define STAT_FramingModeMask 0x0003 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_Misc -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define STAT_OverlappedSpectrum 0x0008 -#define STAT_TCM 0x0010 -#define STAT_TDQ_at_1104 0x0020 -#define STAT_T1413_Signal_Detected 0x0040 -#define STAT_AnnexL_US_Mask1_PSD 0x1000 //indicate we actually selected G992.3 AnnexL US PSD mask1 -#define STAT_AnnexL_US_Mask2_PSD 0x2000 //indicate we actually selected G992.3 AnnexL US PSD mask2 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_FailureState -// when the MacroSTate indicates the fail state, FailureState provides a failure code -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define E_CODE_NO_ERROR 0 -#define E_CODE_BAT_TX 1 // TX BAT table is incorrect */ -#define E_CODE_BAT_RX 2 // RX BAT table is incorrect */ -#define E_CODE_PROFILE 3 // profile is not selected in fast retrain */ -#define E_CODE_TX_AOC_FIFO_OVERFLOW 4 -#define E_CODE_TRUNCATE_FR 5 //Fast Retrain truncated due to no stored profiles*/ -#define E_CODE_BITLOAD 6 // bit loading fails */ -#define E_CODE_ST_ERROR 7 // showtime CRC error */ -#define E_CODE_RESERVED 8 // using parameters reserved by the ITU-T */ -#define E_CODE_C_TONES 9 // detected C_TONES */ -#define E_CODE_CODESWAP_ERR 10 // codeswap not finished in time */ -#define E_CODE_FIFO_OVERFLOW 11 // we have run out of fifo space */ -#define E_CODE_C_BG_DECODE_ERR 12 // error in decoding C-BG message */ -#define E_CODE_C_RATES2_DECODE_ERR 13 // error in decoding C-MSGS2 and C-RATES2 */ -#define E_CODE_RCMedleyRx_C_SEGUE2_Failure 14 // Timeout after RCMedleyRx waiting for C_SEGUE2 */ -#define E_CODE_RReverbRATx_C_SEGUE2_Failure 15 // Timeout after RReverbRATx waiting for C_SEGUE2 */ -#define E_CODE_RReverb3Tx_C_SEGUE1_Failure 16 // Timeout after RReverb3Tx waiting for C_SEGUE1 */ -#define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR 17 // Received CRC not equal to computed CRC */ -#define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR 18 // Received CRC not equal to computed CRC */ -#define E_CODE_RReverb5Tx_C_SEGUE2_Failure 19 // Timeout after RReverb5Tx waiting for C_SEGUE2 */ -#define E_CODE_RReverb6Tx_C_SEGUE3_Failure 20 // Timeout after RReverb6Tx waiting for C_SEGUE3 */ -#define E_CODE_RSegue5Tx_C_SEGUE3_Failure 21 // Timeout after RSegue5Tx waiting for C_SEGUE3 */ -#define E_CODE_RCReverb5Rx_C_SEGUE_Failure 22 // Timeout after RCReverb5Rx waiting for C_SEGUE */ -#define E_CODE_RCReverbRARx_C_SEGUE2_Failure 23 // Timeout after RCReverbRARx waiting for C_SEGUE2 */ -#define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR 24 // Received CRC not equal to computed CRC */ -#define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR 25 // Received CRC not equal to computed CRC */ -#define E_CODE_RCCRC3Rx_DECOD_ERR 26 // Received CRC not equal to computed CRC */ -#define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT 27 // DEC Path Delay timeout */ -#define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT 28 // DEC Training timeout */ -#define E_CODE_RCReverb3Rx_C_SEGUE1_Failure 29 // Timeout after RCReverb3Rx waiting for C_SEGUE1 */ -#define E_CODE_RCReverb2Rx_SignalEnd_Failure 30 // Timeout waiting for the end of RCReverb2Rx signal */ -#define E_CODE_RQuiet2_SignalEnd_Failure 31 // Timeout waiting for the end of RQuiet2 signal */ -#define E_CODE_RCReverbFR1Rx_Failure 32 // Timeout waiting for the end of RCReverbFR1Rx signal */ -#define E_CODE_RCPilotFR1Rx_SignalEnd_Failure 33 // Timeout waiting for the end of RCPilotFR1Rx signal */ -#define E_CODE_RCReverbFR2Rx_C_Segue_Failure 34 // Timeout after RCReverbFR2Rx waiting for C_SEGUE */ -#define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT 35 // Timeout waiting for the end of RCReverbFR5Rx signal */ -#define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure 36 // Timeout after RCReverbFR6Rx waiting for C_SEGUE */ -#define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure 37 // Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */ -#define E_CODE_RCReverbFR8Rx_No_PROFILE 38 // Timeout since no profile was selected */ -#define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT 39 // Timeout waiting for the end of RCReverbFR8Rx signal */ -#define E_CODE_RCCRCFR1_DECOD_ERR 40 // Received CRC not equal to computed CRC */ -#define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT 41 // Timeout waiting for the end of RCRecovRx signal */ -#define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT 42 // Timeout after RSegueFR5Tx waiting for C_SEGUE2 */ -#define E_CODE_RRecovTx_SignalEnd_TIMEOUT 43 // Timeout waiting for the end of RRecovTx signal */ -#define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure 44 // Timeout after RCMedleyFRRx waiting for C_SEGUE2 */ -#define E_CODE_CONFIGURATION_PARAMETERS_ERROR 45 // one of the configuration parameters do not meet the standard */ -#define E_CODE_BAD_MEM_ACCESS 46 -#define E_CODE_BAD_INSTRUCTION_ACCESS 47 -#define E_CODE_TX_EOC_FIFO_OVERFLOW 48 -#define E_CODE_RX_EOC_FIFO_OVERFLOW 49 -#define E_CODE_GHS_CD_FLAG_TIME_OUT 50 // Timeout when transmitting Flag in handshake cleardown */ - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//STAT_OLRStatus: -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define STAT_OLRPM_IDLE 0x0000 -#define STAT_OLRPM_IN_PROGRESS 0x0001 -#define STAT_OLRPM_COMPLETE 0x0002 -#define STAT_OLRPM_ABORTED 0x0003 -#define STAT_OLRPM_RESPONSE 0x0800 - -#define STAT_OLR_BITSWAP 0x0010 -#define STAT_OLR_DRR 0x0020 -#define STAT_OLR_SRA 0x0030 - -//STAT_PMStatus_US: -#define STAT_PM_CO_REQ 0x0004 -#define STAT_PM_SIMPLE_REQ 0x0010 -#define STAT_PM_L2_REQ 0x0020 -#define STAT_PM_L2_TRIM_REQ 0x0030 - -// STAT_OLRError_DS, STAT_OLRError_US -//4 bit response reason code: -#define RESP_BUSY 0x01 -#define RESP_INVALID_PARAMETERS 0x02 -#define RESP_NOT_ENABLED 0x03 -#define RESP_NOT_SUPPORTED 0x04 - -//4 bit internal error code (common for OLR and PM) -#define REQ_INVALID_BiGi 0x10 -#define REQ_INVALID_Lp 0x20 -#define REQ_INVALID_Bpn 0x30 -#define REQ_INVALID_FRAMING_CONSTRAINT 0x40 -#define REQ_NOT_IN_L0_STATE 0x50 -#define REQ_NOT_IN_L2_STATE 0x60 -#define REQ_INVALID_PCB 0x70 -#define REQ_VIOLATES_MARGIN 0x80 - -//STAT_PMError -//4 bit response reason code: -#define RESP_STATE_NOT_DESIRED 0x03 -#define RESP_INFEASIBLE_PARAMETERS 0x04 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN register address and bit field definitions -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_ModeControl 0 -#define OPTN_DMTLnkCtl 1 -// Reserved 2 -#define OPTN_GhsControl 3 -// Reserved 4 -#define OPTN_PwrManControl 5 -#define OPTN_AnnexControl 6 -#define OPTN_ModeControl1 7 -// Reserved 8 -#define OPTN_StateMachineCtrl 9 -// Reserved 10 -// Reserved 11 -#define OPTN_BisLinkControl 12 -#define OPTN_ATMAddrConfig 13 -#define OPTN_ATMNumCellConfig 14 - -// Mode control defines the allowable operating modes of an ADSL link. In general, a modem may /// -// use G.Hs or some other mechanism to negotiate the specific mode of operation. /// -// The OPTN_ModeControl CMV is used to select a set of desired modes /// -// The STAT_ModeControl CMV indicates which mode was actually selected /// - -// OPTN_ModeControl -#define OPTN_ConfigMode_T1413 0x0001 -#define OPTN_ConfigMode_G992_2_AB 0x0002 -#define OPTN_ConfigMode_G992_1_A 0x0004 -#define OPTN_ConfigMode_G992_1_B 0x0008 -#define OPTN_ConfigMode_G992_1_C 0x0010 -#define OPTN_ConfigMode_G992_2_C 0x0020 - -#define OPTN_ConfigMode_G992_3_A 0x0100 -#define OPTN_ConfigMode_G992_3_B 0x0200 -#define OPTN_ConfigMode_G992_3_I 0x0400 -#define OPTN_ConfigMode_G992_3_J 0x0800 -#define OPTN_ConfigMode_G992_3_L 0x1000 - -#define OPTN_ConfigMode_G992_4_A 0x2000 -#define OPTN_ConfigMode_G992_4_I 0x4000 - -#define OPTN_ConfigMode_G992_5 0x8000 - -// OPTN_PwrManControl -#define OPTN_PwrManWakeUpGhs 0x1 -#define OPTN_PwrManWakeUpFR 0x2 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_DMT Link Control -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define OPTN_DMT_DualLatency_Dis 0x200 -#define OPTN_DMT_S_Dis 0x100 -#define OPTN_DMT_FRAMINGMODE 0x1 -#define OPTN_DMT_FRAMINGMODE_MASK 0x7 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_BIS Link Control -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define OPTN_BisLinkContrl_LineProbeDis 0x1 -#define OPTN_BisLinkContrl_DSBlackBitsEn 0x2 -#define OPTN_BisLinkContrl_DiagnosticModeEn 0x4 -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_GhsControl -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// -// for OPTN_GhsControl, we will assign 16bit word as follows -// bit 0~3: set the control over which start(initial) message CPE will send: -// -// BIT: 2 1 0 -// 0 0 1 CLR -// 0 1 0 MR -// 0 1 1 MS -// 1 0 0 MP -// -// // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange -// BIT: 5 4 -// 0 1 MS -// 1 0 MR -// 1 1 MP -// -// // bit 15: RT initiated G.hs sample sessions one through eight. Session one is default. -// BIT: 15 -// 1 means session one -// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_GHS_ST_GHS 0x8000 -#define OPTN_GHS_INIT_MASK 0x000F -#define OPTN_GHS_RESP_MASK 0x00F0 - -#define OPTN_RTInitTxMsg_CLR 0x0001 -#define OPTN_RTInitTxMsg_MR 0x0002 -#define OPTN_RTInitTxMsg_MS 0x0003 -#define OPTN_RTInitTxMsg_MP 0x0004 - -#define OPTN_RTRespTxMsg_MS 0x0010 -#define OPTN_RTRespTxMsg_MR 0x0020 -#define OPTN_RTRespTxMsg_MP 0x0030 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_AnnexControl -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -// G.992.3 Annex A/L1/L2 US PSD Mask preferred - -#define OPTN_G992_3_AnnexA_PreferredModeMask 0x3000 -#define OPTN_G992_3_AnnexA_PreferredModeA 0x0000 // default AnnexA PSD mask /// -#define OPTN_G992_3_AnnexA_PreferredModeL1 0x1000 // AnnexL wide spectrum upstream PSD mask /// -#define OPTN_G992_3_AnnexA_PreferredModeL2 0x2000 // AnnexL narrow spectrum upstream PSD mask /// - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//OPTN_ATMAddrConfig -// Bits 4:0 are Utopia address for BC1 -// Bits 9:5 are Utopia address for BC0 -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_UTPADDR_BC1 0x001F -#define OPTN_UTPADDR_BC0 0x03E0 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//OPTN_ATMNumCellConfig -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_BC1_NUM_CELL_PAGES 0x000F // Bits 0:3 /// -#define OPTN_BC0_NUM_CELL_PAGES 0x00F0 // Bits 4:7 /// - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// CNFG register address field /// -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -/////////////////////////////////////////// -// these cmvs are used by bis handshake /// -/////////////////////////////////////////// - -// Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t) -#define CNFG_TPS_TC_DS0 0 -#define CNFG_TPS_TC_DS1 1 -#define CNFG_TPS_TC_US0 2 -#define CNFG_TPS_TC_US1 3 - -#define CNFG_HDLC_Overhead_Requirements 4 - -// Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t) -#define CNFG_PMS_TC_DS0 5 -#define CNFG_PMS_TC_DS1 6 -#define CNFG_PMS_TC_US0 7 -#define CNFG_PMS_TC_US1 8 - -// CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t) -#define CNFG_PMD_PARAMETERS 9 - -//////////////////////////////////////////////////////////// -// these cmvs are used by bis training and showtime code /// -//////////////////////////////////////////////////////////// - -//////////////// -// Tx Config /// -//////////////// -#define CNFG_tx_Cnfg_Nbc 10 -#define CNFG_tx_Cnfg_Nlp 11 -#define CNFG_tx_Cnfg_Rp 12 -#define CNFG_tx_Cnfg_Mp 13 -#define CNFG_tx_Cnfg_Lp 14 -#define CNFG_tx_Cnfg_Tp 15 -#define CNFG_tx_Cnfg_Dp 16 -#define CNFG_tx_Cnfg_Bpn 17 -#define CNFG_tx_Cnfg_FramingMode 18 -#define CNFG_tx_Cnfg_MSGLp 19 -#define CNFG_tx_Cnfg_MSGc 20 - -//////////////// -// Rx Config /// -//////////////// -#define CNFG_rx_Cnfg_Nbc 21 -#define CNFG_rx_Cnfg_Nlp 22 -#define CNFG_rx_Cnfg_Rp 23 -#define CNFG_rx_Cnfg_Mp 24 -#define CNFG_rx_Cnfg_Lp 25 -#define CNFG_rx_Cnfg_Tp 26 -#define CNFG_rx_Cnfg_Dp 27 -#define CNFG_rx_Cnfg_Bpn 28 -#define CNFG_rx_Cnfg_FramingMode 29 -#define CNFG_rx_Cnfg_MSGLp 30 -#define CNFG_rx_Cnfg_MSGc 31 - -#define CNFG_tx_Cnfg_BCnToLPp 32 -#define CNFG_rx_Cnfg_BCnToLPp 33 - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_linux.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_linux.h deleted file mode 100644 index 79849ae4fb..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_linux.h +++ /dev/null @@ -1,112 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_mei_linux.h -** PROJECT : Danube -** MODULES : MEI -** -** DATE : 1 Jan 2006 -** AUTHOR : TC Chen -** DESCRIPTION : MEI Driver -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Version $Date $Author $Comment -*******************************************************************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef CONFIG_DEVFS_FS //165204:henryhsu devfs will make mei open file fail. - -#ifdef CONFIG_DEVFS_FS -#include -#endif -#ifdef CONFIG_PROC_FS -#include -#endif - -#include -#include -#define __LINUX__ - -#ifdef CONFIG_PROC_FS -#define PROC_ITEMS 8 -#define MEI_DIRNAME "mei" -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_DEVFS_FS -#define IFXMIPS_DEVNAME "ifxmips" -#endif //ifdef CONFIG_DEVFS_FS - -#define MEI_LOCKINT(var) \ - local_save_flags(var);\ - local_irq_disable() -#define MEI_UNLOCKINT(var) \ - local_irq_restore(var) - -#define MEI_MUTEX_INIT(id,flag) \ - sema_init(&id,flag) -#define MEI_MUTEX_LOCK(id) \ - down_interruptible(&id) -#define MEI_MUTEX_UNLOCK(id) \ - up(&id) - -#define MEI_MASK_AND_ACK_IRQ \ - ifxmips_mask_and_ack_irq - -#define MEI_DISABLE_IRQ \ - disable_irq -#define MEI_ENABLE_IRQ \ - enable_irq - -#define MEI_WAIT(ms) \ - {\ - set_current_state(TASK_INTERRUPTIBLE);\ - schedule_timeout(ms);\ - } - -#define MEI_INIT_WAKELIST(name,queue) \ - init_waitqueue_head(&queue) - -#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\ - interruptible_sleep_on_timeout(&ev,timeout) - -#define MEI_WAIT_EVENT(ev)\ - interruptible_sleep_on(&ev) -#define MEI_WAKEUP_EVENT(ev)\ - wake_up_interruptible(&ev) - -typedef unsigned long MEI_intstat_t; -typedef struct semaphore MEI_mutex_t; -typedef struct file MEI_file_t; -typedef struct inode MEI_inode_t; - -extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr); diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h deleted file mode 100644 index b842734452..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_PMU_H__ -#define _IFXMIPS_PMU_H__ - -#define IFXMIPS_PMU_PWDCR_DMA 0x20 -#define IFXMIPS_PMU_PWDCR_LED 0x800 -#define IFXMIPS_PMU_PWDCR_GPT 0x1000 -#define IFXMIPS_PMU_PWDCR_PPE 0x2000 -#define IFXMIPS_PMU_PWDCR_FPI 0x4000 - -void ifxmips_pmu_enable (unsigned int module); -void ifxmips_pmu_disable (unsigned int module); - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h deleted file mode 100644 index 822ff0bca6..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2008 John Crispin - */ -#ifndef _IFXPROM_H__ -#define _IFXPROM_H__ - -extern void prom_printf(const char * fmt, ...); -extern u32 *prom_get_cp1_base(void); -extern u32 prom_get_cp1_size(void); -extern int ifxmips_has_brn_block(void); - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h deleted file mode 100644 index 0dece372d1..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * include/asm-mips/mach-ifxmips/gpio.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - * - */ - - -#ifndef _IFXMIPS_GPIO_H_ -#define _IFXMIPS_GPIO_H_ - -#include -#include - -#define GPIO_TO_PORT(x) ((x > 15)?(1):(0)) -#define GPIO_TO_GPIO(x) ((x > 15)?(x-16):(x)) - -static inline int gpio_direction_input(unsigned gpio) { - ifxmips_port_set_open_drain(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - ifxmips_port_clear_altsel0(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - ifxmips_port_clear_altsel1(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - ifxmips_port_set_dir_in(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - return 0; -} - -static inline int gpio_direction_output(unsigned gpio, int value) { - ifxmips_port_clear_open_drain(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - ifxmips_port_clear_altsel0(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - ifxmips_port_clear_altsel1(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - ifxmips_port_set_dir_out(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - return 0; -} - -static inline int gpio_get_value(unsigned gpio) { - ifxmips_port_get_input(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - return 0; -} - -static inline void gpio_set_value(unsigned gpio, int value) { - if(value) - ifxmips_port_set_output(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); - else - ifxmips_port_clear_output(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); -} - -static inline int gpio_request(unsigned gpio, const char *label) { - return 0; -} - -static inline void gpio_free(unsigned gpio) { -} - -static inline int gpio_to_irq(unsigned gpio) { - return 0; -} - -static inline int irq_to_gpio(unsigned irq) { - return 0; -} - -static inline int gpio_cansleep(unsigned gpio) { - return 0; -} - -static inline int gpio_get_value_cansleep(unsigned gpio) { - might_sleep(); - return gpio_get_value(gpio); -} - -static inline void gpio_set_value_cansleep(unsigned gpio, int value) { - might_sleep(); - gpio_set_value(gpio, value); -} - -static inline int gpio_is_valid(int number) -{ - return ((unsigned)number) < 8; -} - -#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/irq.h b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/irq.h deleted file mode 100644 index f178abf485..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/irq.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * include/asm-mips/mach-ifxmips/irq.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - * - */ - -#ifndef __IFXMIPS_IRQ_H -#define __IFXMIPS_IRQ_H - -#define NR_IRQS 256 -#include_next - -#endif - diff --git a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/war.h b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/war.h deleted file mode 100644 index de3584ecf6..0000000000 --- a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/war.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ -#ifndef __ASM_MIPS_MACH_IFXMIPS_WAR_H -#define __ASM_MIPS_MACH_IFXMIPS_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif diff --git a/target/linux/ifxmips/image/Makefile b/target/linux/ifxmips/image/Makefile deleted file mode 100644 index 15e0bc5dc3..0000000000 --- a/target/linux/ifxmips/image/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Image/BuildKernel - $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.lzma - mkimage -A mips -O linux -T kernel -a 0x80002000 -C lzma -e \ - 0x80002000 \ - -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ - -d $(KDIR)/vmlinux.lzma $(KDIR)/uImage - - cp $(KDIR)/uImage $(BIN_DIR)/openwrt-$(BOARD)-uImage -endef - -define Image/Build/squashfs - cat $(KDIR)/uImage $(KDIR)/root.$(1) > $(BIN_DIR)/openwrt-$(BOARD)-$(1).image - $(call prepare_generic_squashfs,$(BIN_DIR)/openwrt-$(BOARD)-$(1).image) -endef - -define Image/Build/jffs2-64k - dd if=$(KDIR)/uImage of=$(KDIR)/uImage.$(1) bs=64k conv=sync - cat $(KDIR)/uImage.$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/openwrt-$(BOARD)-$(1).image -endef - -define Image/Build - $(call Image/Build/$(1),$(1)) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/ifxmips/patches/100-board.patch b/target/linux/ifxmips/patches/100-board.patch deleted file mode 100644 index db43c90b2c..0000000000 --- a/target/linux/ifxmips/patches/100-board.patch +++ /dev/null @@ -1,80 +0,0 @@ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -78,6 +78,21 @@ - select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ - -+config IFXMIPS -+ bool "Infineon Twinpass, Danube, Amazon-SE" -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select CEVT_R4K -+ select CSRC_R4K -+ select SYS_HAS_CPU_MIPS32_R1 -+ select HAVE_STD_PC_SERIAL_PORT -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_HAS_EARLY_PRINTK -+ select HW_HAS_PCI -+ select GENERIC_GPIO -+ select SWAP_IO_SPACE -+ - config MACH_DECSTATION - bool "DECstations" - select BOOT_ELF32 -@@ -697,6 +712,7 @@ - source "arch/mips/tx4927/Kconfig" - source "arch/mips/tx4938/Kconfig" - source "arch/mips/vr41xx/Kconfig" -+source "arch/mips/ifxmips/Kconfig" - - endmenu - ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -283,6 +283,13 @@ - load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000 - - # -+# Infineon IFXMIPS -+# -+core-$(CONFIG_IFXMIPS) += arch/mips/ifxmips/ -+cflags-$(CONFIG_IFXMIPS) += -Iinclude/asm-mips/mach-ifxmips -+load-$(CONFIG_IFXMIPS) += 0xffffffff80002000 -+ -+# - # DECstation family - # - core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/ ---- a/include/asm-mips/bootinfo.h -+++ b/include/asm-mips/bootinfo.h -@@ -94,6 +94,12 @@ - #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ - #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ - -+/* -+ * Valid machtype for group IFXMIPS -+ */ -+#define MACH_GROUP_IFXMIPS 29 -+#define MACH_INFINEON_IFXMIPS 0 -+ - #define CL_SIZE COMMAND_LINE_SIZE - - extern char *system_type; ---- a/arch/mips/kernel/traps.c -+++ b/arch/mips/kernel/traps.c -@@ -1464,6 +1464,7 @@ - */ - if (cpu_has_mips_r2) { - cp0_compare_irq = (read_c0_intctl() >> 29) & 7; -+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; - cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -48,3 +48,4 @@ - obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o - obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o - obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o -+obj-$(CONFIG_IFXMIPS) += pci-ifxmips.o ops-ifxmips.o diff --git a/target/linux/ifxmips/patches/110-drivers.patch b/target/linux/ifxmips/patches/110-drivers.patch deleted file mode 100644 index a25c57003a..0000000000 --- a/target/linux/ifxmips/patches/110-drivers.patch +++ /dev/null @@ -1,149 +0,0 @@ ---- a/drivers/char/Makefile -+++ b/drivers/char/Makefile -@@ -114,6 +114,10 @@ - obj-$(CONFIG_JS_RTC) += js-rtc.o - js-rtc-y = rtc.o - -+obj-$(CONFIG_IFXMIPS_SSC) += ifxmips_ssc.o -+obj-$(CONFIG_IFXMIPS_EEPROM) += ifxmips_eeprom.o -+obj-$(CONFIG_IFXMIPS_MEI) += ifxmips_mei_core.o -+ - # Files generated that shall be removed upon make clean - clean-files := consolemap_deftbl.c defkeymap.c - ---- a/drivers/mtd/maps/Makefile -+++ b/drivers/mtd/maps/Makefile -@@ -67,3 +67,4 @@ - obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o - obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o - obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o -+obj-$(CONFIG_MTD_IFXMIPS) += ifxmips.o ---- a/drivers/net/Kconfig -+++ b/drivers/net/Kconfig -@@ -351,6 +351,12 @@ - - source "drivers/net/arm/Kconfig" - -+config IFXMIPS_MII0 -+ tristate "Infineon IFXMips eth0 driver" -+ depends on IFXMIPS -+ help -+ Support for the MII0 inside the IFXMips SOC -+ - config AX88796 - tristate "ASIX AX88796 NE2000 clone support" - depends on ARM || MIPS || SUPERH ---- a/drivers/serial/Kconfig -+++ b/drivers/serial/Kconfig -@@ -1334,6 +1334,14 @@ - Currently, only 8250 compatible ports are supported, but - others can easily be added. - -+config SERIAL_IFXMIPS -+ bool "IFXMips serial driver" -+ depends on IFXMIPS -+ select SERIAL_CORE -+ select SERIAL_CORE_CONSOLE -+ help -+ Driver for the ifxmipss built in ASC hardware -+ - config SERIAL_QE - tristate "Freescale QUICC Engine serial port support" - depends on QUICC_ENGINE ---- a/drivers/serial/Makefile -+++ b/drivers/serial/Makefile -@@ -68,3 +68,4 @@ - obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o - obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o - obj-$(CONFIG_SERIAL_QE) += ucc_uart.o -+obj-$(CONFIG_SERIAL_IFXMIPS) += ifxmips_asc.o ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -97,6 +97,7 @@ - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+obj-$(CONFIG_IFXMIPS_WDT) += ifxmips_wdt.o - - # PARISC Architecture - ---- a/drivers/net/Makefile -+++ b/drivers/net/Makefile -@@ -256,4 +256,4 @@ - obj-$(CONFIG_NIU) += niu.o - obj-$(CONFIG_VIRTIO_NET) += virtio_net.o - obj-$(CONFIG_SFC) += sfc/ -- -+obj-$(CONFIG_IFXMIPS_MII0) += ifxmips_mii0.o ---- a/drivers/crypto/Kconfig -+++ b/drivers/crypto/Kconfig -@@ -9,6 +9,9 @@ - If you say N, all options in this submenu will be skipped and disabled. - - if CRYPTO_HW -+config CRYPTO_DEV_IFXMIPS -+ tristate "Support for IFXMIPS Data Encryption Unit" -+ depends on IFXMIPS - - config CRYPTO_DEV_PADLOCK - tristate "Support for VIA PadLock ACE" ---- a/drivers/crypto/Makefile -+++ b/drivers/crypto/Makefile -@@ -4,3 +4,4 @@ - obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o - obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o - obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o -+obj-$(CONFIG_CRYPTO_DEV_IFXMIPS) += ifxdeu-aes.o ifxdeu-des.o ifxdeu-dma.o ifxdeu-generic.o ifxdeu-md5.o ifxdeu-sha1.o ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -305,3 +305,10 @@ - help - This driver enables support for the on-chip R8A66597 in the - SH7366 and SH7723 processors. -+ -+config USB_DWC_HCD -+ tristate "IFXMIPS USB Host Controller Driver" -+ depends on USB && IFXMIPS -+ default y -+ help -+ Danube USB Host Controller ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -153,6 +153,12 @@ - To compile this driver as a module, choose M here: the - module will be called leds-clevo-mail. - -+config LEDS_IFXMIPS -+ tristate "LED Support for IFXMIPS LEDs" -+ depends on LEDS_CLASS && IFXMIPS -+ help -+ This option enables support for the CM-X270 LEDs. -+ - comment "LED Triggers" - - config LEDS_TRIGGERS ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -22,6 +22,7 @@ - obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o - obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o - obj-$(CONFIG_LEDS_FSG) += leds-fsg.o -+obj-$(CONFIG_LEDS_IFXMIPS) += leds-ifxmips.o - - # LED Triggers - obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -683,6 +683,12 @@ - help - Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs. - -+config IFXMIPS_WDT -+ bool "IFXMips watchdog" -+ depends on IFXMIPS -+ help -+ Hardware driver for the IFXMIPS Watchdog Timer. -+ - # PARISC Architecture - - # POWERPC Architecture diff --git a/target/linux/ifxmips/patches/160-cfi-swap.patch b/target/linux/ifxmips/patches/160-cfi-swap.patch deleted file mode 100644 index 7649ec1ff4..0000000000 --- a/target/linux/ifxmips/patches/160-cfi-swap.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -1041,7 +1041,9 @@ - int retry_cnt = 0; - - adr += chip->start; -- -+#ifdef CONFIG_IFXMIPS -+ adr ^= 2; -+#endif - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr, FL_WRITING); - if (ret) { diff --git a/target/linux/ifxmips/patches/170-dma_hack.patch b/target/linux/ifxmips/patches/170-dma_hack.patch deleted file mode 100644 index 38c58bb5cc..0000000000 --- a/target/linux/ifxmips/patches/170-dma_hack.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/mips/mm/cache.c -+++ b/arch/mips/mm/cache.c -@@ -50,6 +50,8 @@ - void (*_dma_cache_inv)(unsigned long start, unsigned long size); - - EXPORT_SYMBOL(_dma_cache_wback_inv); -+EXPORT_SYMBOL(_dma_cache_wback); -+EXPORT_SYMBOL(_dma_cache_inv); - - #endif /* CONFIG_DMA_NONCOHERENT */ - diff --git a/target/linux/ifxmips/profiles/100-Atheros.mk b/target/linux/ifxmips/profiles/100-Atheros.mk deleted file mode 100644 index 71804b294f..0000000000 --- a/target/linux/ifxmips/profiles/100-Atheros.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Atheros - NAME:=Atheros WiFi (default) - PACKAGES:=kmod-madwifi -endef - -define Profile/Atheros/Description - Package set compatible with hardware using Atheros WiFi cards -endef -$(eval $(call Profile,Atheros)) - diff --git a/target/linux/ifxmips/profiles/200-Ralink.mk b/target/linux/ifxmips/profiles/200-Ralink.mk deleted file mode 100644 index dd9716ab59..0000000000 --- a/target/linux/ifxmips/profiles/200-Ralink.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Ralink - NAME:=Ralink RT61 Wifi (ARV452) - PACKAGES:=kmod-rt61-pci -endef - -define Profile/Ralink/Description - Package set compatible with hardware using Ralink WiFi cards -endef -$(eval $(call Profile,Ralink)) - diff --git a/target/linux/ifxmips/series b/target/linux/ifxmips/series deleted file mode 100644 index 19bcf21175..0000000000 --- a/target/linux/ifxmips/series +++ /dev/null @@ -1,88 +0,0 @@ -Makefile -base-files/etc/config/network -config-2.6.23 -files/arch/mips/danube/Kconfig -files/arch/mips/danube/Makefile -files/arch/mips/danube/built-in.o -files/arch/mips/danube/dma-core.c -files/arch/mips/danube/dma-core.h -files/arch/mips/danube/dma-core.o -files/arch/mips/danube/interrupt.c -files/arch/mips/danube/interrupt.o -files/arch/mips/danube/kgdb_serial.c -files/arch/mips/danube/pci.c -files/arch/mips/danube/prom.c -files/arch/mips/danube/prom.o -files/arch/mips/danube/reset.c -files/arch/mips/danube/reset.o -files/arch/mips/danube/setup.c -files/arch/mips/danube/setup.o -files/drivers/mtd/maps/danube.c -files/drivers/serial/danube_asc.c -files/drivers/serial/danube_asc.c~ -files/drivers/serial/danube_asc.o -files/include/asm-mips/danube/adm6996.h -files/include/asm-mips/danube/atm_mib.h -files/include/asm-mips/danube/danube.h -files/include/asm-mips/danube/danube_bcu.h -files/include/asm-mips/danube/danube_cgu.h -files/include/asm-mips/danube/danube_deu.h -files/include/asm-mips/danube/danube_deu_structs.h -files/include/asm-mips/danube/danube_dma.h -files/include/asm-mips/danube/danube_eth2.h -files/include/asm-mips/danube/danube_eth2_fw.h -files/include/asm-mips/danube/danube_eth2_fw_with_dplus.h -files/include/asm-mips/danube/danube_eth2_fw_with_dplus_sb.h -files/include/asm-mips/danube/danube_eth_d2.h -files/include/asm-mips/danube/danube_eth_fw_d2.h -files/include/asm-mips/danube/danube_gpio.h -files/include/asm-mips/danube/danube_gptu.h -files/include/asm-mips/danube/danube_icu.h -files/include/asm-mips/danube/danube_led.h -files/include/asm-mips/danube/danube_mei.h -files/include/asm-mips/danube/danube_mei_app.h -files/include/asm-mips/danube/danube_mei_app_ioctl.h -files/include/asm-mips/danube/danube_mei_bsp.h -files/include/asm-mips/danube/danube_mei_ioctl.h -files/include/asm-mips/danube/danube_mei_linux.h -files/include/asm-mips/danube/danube_misc.h -files/include/asm-mips/danube/danube_pmu.h -files/include/asm-mips/danube/danube_ppa_api.h -files/include/asm-mips/danube/danube_ppa_eth_fw_d2.h -files/include/asm-mips/danube/danube_ppa_eth_fw_d3.h -files/include/asm-mips/danube/danube_ppa_hook.h -files/include/asm-mips/danube/danube_ppa_ppe_d3_hal.h -files/include/asm-mips/danube/danube_ppa_ppe_hal.h -files/include/asm-mips/danube/danube_ppa_stack_al.h -files/include/asm-mips/danube/danube_ppe.h -files/include/asm-mips/danube/danube_ppe_fw.h -files/include/asm-mips/danube/danube_ppe_fw_fix_for_pci.h -files/include/asm-mips/danube/danube_rcu.h -files/include/asm-mips/danube/danube_sdio_controller.h -files/include/asm-mips/danube/danube_sdio_controller_registers.h -files/include/asm-mips/danube/danube_ssc.h -files/include/asm-mips/danube/danube_sw.h -files/include/asm-mips/danube/danube_wdt.h -files/include/asm-mips/danube/danube_ws.h -files/include/asm-mips/danube/emulation.h -files/include/asm-mips/danube/ifx_mps.h -files/include/asm-mips/danube/ifx_peripheral_definitions.h -files/include/asm-mips/danube/ifx_sd_card.h -files/include/asm-mips/danube/ifx_serial.h -files/include/asm-mips/danube/ifx_ssc.h -files/include/asm-mips/danube/ifx_ssc_defines.h -files/include/asm-mips/danube/ifx_types.h -files/include/asm-mips/danube/infineon_sdio.h -files/include/asm-mips/danube/infineon_sdio_card.h -files/include/asm-mips/danube/infineon_sdio_cmds.h -files/include/asm-mips/danube/infineon_sdio_controller.h -files/include/asm-mips/danube/irq.h -files/include/asm-mips/danube/memcopy.h -files/include/asm-mips/danube/mps.h -files/include/asm-mips/danube/port.h -files/include/asm-mips/danube/ppe.h -files/include/asm-mips/danube/serial.h -files/include/asm-mips/mach-danube/irq.h -image/Makefile -patches/100-board.patch -patches/110-drivers.patch diff --git a/target/linux/iop32x/Makefile b/target/linux/iop32x/Makefile deleted file mode 100644 index 2fe245b50b..0000000000 --- a/target/linux/iop32x/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (C) 2007 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=iop32x -BOARDNAME:=Intel IOP32x -FEATURES:=squashfs jffs2 - -LINUX_VERSION:=2.6.26.5 - -include $(INCLUDE_DIR)/target.mk - -define Kernel/Configure - $(call Kernel/Configure/Default) - $(SED) 's,.*CONFIG_AEABI.*,$(if $(CONFIG_EABI_SUPPORT),CONFIG_AEABI=y,# CONFIG_AEABI is not set),' $(LINUX_DIR)/.config - $(if $(CONFIG_EABI_SUPPORT),echo '# CONFIG_OABI_COMPAT is not set' >> $(LINUX_DIR)/.config) -endef - -$(eval $(call BuildTarget)) diff --git a/target/linux/iop32x/base-files/etc/config/network b/target/linux/iop32x/base-files/etc/config/network deleted file mode 100644 index 1d9b55b2d3..0000000000 --- a/target/linux/iop32x/base-files/etc/config/network +++ /dev/null @@ -1,11 +0,0 @@ -# Network configuration file - -config interface loopback - option ifname lo - option proto static - option ipaddr 127.0.0.1 - option netmask 255.0.0.0 - -config interface lan - option ifname eth0 - option proto dhcp diff --git a/target/linux/iop32x/config-default b/target/linux/iop32x/config-default deleted file mode 100644 index 0555e8094c..0000000000 --- a/target/linux/iop32x/config-default +++ /dev/null @@ -1,364 +0,0 @@ -# CONFIG_8139TOO is not set -# CONFIG_AEABI is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP13XX is not set -CONFIG_ARCH_IOP32X=y -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IQ31244 is not set -# CONFIG_ARCH_IQ80321 is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_MSM7X00A is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_SHARK is not set -CONFIG_ARCH_SUPPORTS_AOUT=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ARCH_VERSATILE is not set -CONFIG_ARM=y -# CONFIG_ARM_THUMB is not set -# CONFIG_ARPD is not set -# CONFIG_ARTHUR is not set -CONFIG_ASYNC_CORE=y -CONFIG_ATA=m -# CONFIG_ATA_NONSTANDARD is not set -# CONFIG_ATM is not set -# CONFIG_ATMEL is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BINFMT_AOUT is not set -CONFIG_BITREVERSE=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BONDING is not set -CONFIG_BOUNCE=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_BT is not set -# CONFIG_CIFS_STATS is not set -CONFIG_CLASSIC_RCU=y -CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200 init=/etc/preinit" -# CONFIG_CONFIGFS_FS is not set -CONFIG_CPU_32=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_DISABLE is not set -CONFIG_CPU_PABRT_NOIFAR=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_XSCALE=y -CONFIG_CRC16=y -# CONFIG_CRC_CCITT is not set -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_GF128MUL=m -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_USER is not set -CONFIG_DEFAULT_TCP_CONG="westwood" -# CONFIG_DEFAULT_VEGAS is not set -CONFIG_DEFAULT_WESTWOOD=y -CONFIG_DEVPORT=y -CONFIG_DLCI=m -CONFIG_DLCI_MAX=8 -# CONFIG_DM9000 is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DNOTIFY=y -# CONFIG_DSCC4 is not set -# CONFIG_E100 is not set -CONFIG_E1000=y -# CONFIG_E1000E_ENABLED is not set -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set -CONFIG_E1000_NAPI=y -# CONFIG_FARSYNC is not set -# CONFIG_FPE_FASTFPE is not set -# CONFIG_FPE_NWFPE is not set -CONFIG_FRAME_POINTER=y -CONFIG_FS_POSIX_ACL=y -# CONFIG_GENERIC_CLOCKEVENTS is not set -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set -# CONFIG_GENERIC_GPIO is not set -# CONFIG_GENERIC_TIME is not set -# CONFIG_HAMRADIO is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_HAVE_IDE=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HDLC=m -CONFIG_HDLC_CISCO=m -CONFIG_HDLC_FR=m -CONFIG_HDLC_PPP=m -CONFIG_HDLC_RAW=m -# CONFIG_HDLC_RAW_ETH is not set -# CONFIG_HERMES is not set -CONFIG_HWMON=y -# CONFIG_HWMON_DEBUG_CHIP is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_IOP3XX is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IDE is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INTEL_IOP_ADMA=y -# CONFIG_IOP_WATCHDOG is not set -# CONFIG_IP6_NF_MANGLE is not set -# CONFIG_IP6_NF_MATCH_EUI64 is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_TARGET_LOG is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_MROUTE=y -# CONFIG_IP_NF_ARPTABLES is not set -# CONFIG_IP_NF_MATCH_ADDRTYPE is not set -# CONFIG_IP_NF_MATCH_ECN is not set -# CONFIG_IP_NF_MATCH_RECENT is not set -# CONFIG_IP_NF_MATCH_TIME is not set -# CONFIG_IP_NF_SET is not set -# CONFIG_IP_NF_TARGET_ECN is not set -# CONFIG_IP_NF_TARGET_LOG is not set -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_NF_TARGET_TTL is not set -# CONFIG_IP_NF_TARGET_ULOG is not set -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -# CONFIG_IWLWIFI_LEDS is not set -# CONFIG_IWMMXT is not set -# CONFIG_LANMEDIA is not set -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_LLC2 is not set -CONFIG_LZO_COMPRESS=m -CONFIG_LZO_DECOMPRESS=m -# CONFIG_MACH_EM7210 is not set -# CONFIG_MACH_GLANTANK is not set -CONFIG_MACH_N2100=y -# CONFIG_MAC_PARTITION is not set -CONFIG_MEDIA_TUNER=m -# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -# CONFIG_MINIX_FS is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -# CONFIG_MTD_CFI_AMDSTD is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_ONENAND is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PCI is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NET_CLS_ACT is not set -# CONFIG_NET_CLS_IND is not set -CONFIG_NET_DMA=y -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NO_IDLE_HZ is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_NVRAM is not set -# CONFIG_OABI_COMPAT is not set -# CONFIG_OCF_OCF is not set -# CONFIG_OUTER_CACHE is not set -CONFIG_PAGEFLAGS_EXTENDED=y -# CONFIG_PC300 is not set -CONFIG_PCI=y -# CONFIG_PCI200SYN is not set -# CONFIG_PCIPCWATCHDOG is not set -CONFIG_PCI_SYSCALL=y -CONFIG_PLAT_IOP=y -# CONFIG_PPP is not set -# CONFIG_PRISM54 is not set -# CONFIG_R6040 is not set -CONFIG_R8169=y -CONFIG_R8169_NAPI=y -CONFIG_R8169_VLAN=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DEBUG is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_M48T86 is not set -CONFIG_RTC_DRV_PCF8563=y -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_TEST is not set -# CONFIG_RTC_DRV_V3020 is not set -CONFIG_RTC_DRV_X1205=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_WAIT_SCAN=m -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SERIAL_8250_EXTENDED is not set -# CONFIG_SHMEM is not set -CONFIG_SLABINFO=y -# CONFIG_SMC91X is not set -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SOUND is not set -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -CONFIG_SSB_POSSIBLE=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TCP_CONG_HSTCP is not set -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_LP is not set -# CONFIG_TCP_CONG_SCALABLE is not set -CONFIG_TCP_CONG_VEGAS=m -# CONFIG_TCP_CONG_VENO is not set -CONFIG_TCP_CONG_WESTWOOD=y -# CONFIG_TICK_ONESHOT is not set -CONFIG_TINY_SHMEM=y -# CONFIG_TUN is not set -CONFIG_UID16=y -CONFIG_USB=m -# CONFIG_USB_ACM is not set -# CONFIG_USB_CATC is not set -CONFIG_USB_EHCI_HCD=m -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_HCD=m -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_USBAT is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_UHCI_HCD=m -# CONFIG_USB_USBNET is not set -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VGASTATE is not set -# CONFIG_VIA_RHINE is not set -CONFIG_VIDEO_MEDIA=m -CONFIG_VIDEO_V4L1=m -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WAN=y -# CONFIG_WANXL is not set -# CONFIG_XFS_FS is not set -# CONFIG_XIP_KERNEL is not set -CONFIG_XSCALE_PMU=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/iop32x/image/Makefile b/target/linux/iop32x/image/Makefile deleted file mode 100644 index b061c6d0ef..0000000000 --- a/target/linux/iop32x/image/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# Copyright (C) 2007 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Image/Prepare - cp $(LINUX_DIR)/arch/arm/boot/zImage $(KDIR)/zImage -endef - -define Image/BuildKernel - cp $(KDIR)/zImage $(BIN_DIR)/openwrt-$(BOARD)-zImage -# -# XXX - FIXME -# -# BIN_DIR=$(BIN_DIR) $(TOPDIR)/scripts/arm-magic.sh -endef - -define Image/Build - $(call Image/Build/$(1),$(1)) -endef - -define Image/Build/jffs2-64k - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=65536 conv=sync -endef - -define Image/Build/jffs2-128k - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync - $(call Image/Build/slug,$(1)) -endef - -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync - $(call Image/Build/slug,$(1)) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/olpc/Makefile b/target/linux/olpc/Makefile deleted file mode 100644 index 733d613727..0000000000 --- a/target/linux/olpc/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH=i386 -BOARD:=olpc -BOARDNAME:=OLPC XO-1 -FEATURES:=squashfs ext2 - -LINUX_VERSION:=2.6.26.5 - -include $(INCLUDE_DIR)/target.mk -DEFAULT_PACKAGES += kmod-natsemi kmod-ne2k-pci - -$(eval $(call Target,generic)) -$(eval $(call BuildTarget)) -$(eval $(call $(if $(CONFIG_TARGET_ROOTFS_ISO),RequireCommand,Ignore),mkisofs, \ - Please install mkisofs. \ -)) diff --git a/target/linux/olpc/base-files/etc/X11/xorg.conf b/target/linux/olpc/base-files/etc/X11/xorg.conf deleted file mode 100644 index d98a8f87a5..0000000000 --- a/target/linux/olpc/base-files/etc/X11/xorg.conf +++ /dev/null @@ -1,71 +0,0 @@ -# xorg configuration - -Section "ServerLayout" - Identifier "Default Layout" - Screen 0 "Screen0" 0 0 - InputDevice "Mouse0" "CorePointer" - InputDevice "Keyboard0" "CoreKeyboard" -EndSection - -Section "Files" - FontPath "/usr/lib/X11/fonts/misc" -EndSection - -Section "Module" - Load "dbe" - Load "extmod" - Load "fbdevhw" -# Load "glx" - Load "record" - Load "freetype" - Load "type1" -EndSection - -Section "InputDevice" - Identifier "Keyboard0" - Driver "keyboard" - Option "XkbModel" "pc105" - Option "XkbLayout" "us" -EndSection - -Section "InputDevice" - Identifier "Mouse0" - Driver "mouse" - Option "Protocol" "PS/2" - Option "Device" "/dev/psaux" - Option "ZAxisMapping" "4 5" - Option "Emulate3Buttons" "yes" -EndSection - -Section "Monitor" - Identifier "Monitor0" - VendorName "Monitor Vendor" - ModelName "OWRT" - Option "dpms" -EndSection - -Section "Device" - Identifier "FBDev" - Driver "fbdev" - #Option "shadowfb" "off" - VideoRam 4096 -EndSection - -Section "Screen" - Identifier "Screen0" - Device "FBDev" - Monitor "Monitor0" - DefaultDepth 16 - - SubSection "Display" - Depth 16 - Modes "1200x900-75" - EndSubsection - -EndSection - -Section "DRI" - Group 0 - Mode 0666 -EndSection - diff --git a/target/linux/olpc/base-files/etc/config/network b/target/linux/olpc/base-files/etc/config/network deleted file mode 100644 index faa8f0e782..0000000000 --- a/target/linux/olpc/base-files/etc/config/network +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (C) 2006 OpenWrt.org - -config interface loopback - option ifname lo - option proto static - option ipaddr 127.0.0.1 - option netmask 255.0.0.0 - -config interface wlan - option ifname eth0 - option proto dhcp diff --git a/target/linux/olpc/base-files/etc/preinit.arch b/target/linux/olpc/base-files/etc/preinit.arch deleted file mode 100644 index f29f0d448b..0000000000 --- a/target/linux/olpc/base-files/etc/preinit.arch +++ /dev/null @@ -1,2 +0,0 @@ -mount -t proc none /proc -grep 'failsafe=' /proc/cmdline && export FAILSAFE=true diff --git a/target/linux/olpc/base-files/lib/upgrade/platform.sh b/target/linux/olpc/base-files/lib/upgrade/platform.sh deleted file mode 100644 index ffd0b93ab4..0000000000 --- a/target/linux/olpc/base-files/lib/upgrade/platform.sh +++ /dev/null @@ -1,27 +0,0 @@ -platform_check_image() { - [ "$ARGC" -gt 1 ] && return 1 - - case "$(get_magic_word "$1")" in - 48eb) return 0;; - *) - echo "Invalid image type" - return 1 - ;; - esac -} - -platform_do_upgrade() { - get_image "$1" > /dev/hda - sync -} - -x86_prepare_ext2() { - # if we're running from ext2, we need to make sure that we have a mtd - # partition that points to the active rootfs partition. - # however this only matters if we actually need to preserve the config files - [ "$SAVE_CONFIG" -eq 1 ] && return 0 - grep rootfs /proc/mtd >/dev/null || { - echo /dev/hda2,65536,rootfs > /sys/module/block2mtd/parameters/block2mtd - } -} -append sysupgrade_pre_upgrade x86_prepare_ext2 diff --git a/target/linux/olpc/config-2.6.24 b/target/linux/olpc/config-2.6.24 deleted file mode 100644 index d1e795766e..0000000000 --- a/target/linux/olpc/config-2.6.24 +++ /dev/null @@ -1,2218 +0,0 @@ -# CONFIG_4KSTACKS is not set -# CONFIG_60XX_WDT is not set -# CONFIG_64BIT is not set -# CONFIG_6PACK is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_9P_FS is not set -# CONFIG_ACENIC is not set -# CONFIG_ACORN_PARTITION is not set -# CONFIG_ACPI is not set -# CONFIG_ACQUIRE_WDT is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADVANTECH_WDT is not set -# CONFIG_AFFS_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_AGP is not set -# CONFIG_AIRO is not set -CONFIG_AIRO_CS=m -# CONFIG_ALIM1535_WDT is not set -# CONFIG_ALIM7101_WDT is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_AMIGA_PARTITION is not set -CONFIG_ANON_INODES=y -# CONFIG_APM is not set -# CONFIG_APPLICOM is not set -CONFIG_ARCH_FLATMEM_ENABLE=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_MSI=y -CONFIG_ARCH_SUPPORTS_OPROFILE=y -# CONFIG_ARCNET is not set -CONFIG_ARPD=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_ATA is not set -# CONFIG_ATALK is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_ATA_GENERIC is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_ATL1 is not set -# CONFIG_ATM is not set -CONFIG_ATMEL=m -# CONFIG_ATM_AMBASSADOR is not set -CONFIG_ATM_BR2684=m -CONFIG_ATM_BR2684_IPFILTER=y -CONFIG_ATM_CLIP=m -CONFIG_ATM_CLIP_NO_ICMP=y -# CONFIG_ATM_DRIVERS is not set -CONFIG_ATM_DUMMY=m -# CONFIG_ATM_ENI is not set -# CONFIG_ATM_FIRESTREAM is not set -# CONFIG_ATM_FORE200E_MAYBE is not set -# CONFIG_ATM_HE is not set -# CONFIG_ATM_HORIZON is not set -# CONFIG_ATM_IA is not set -# CONFIG_ATM_IDT77252 is not set -# CONFIG_ATM_LANAI is not set -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -# CONFIG_ATM_NICSTAR is not set -CONFIG_ATM_TCP=m -# CONFIG_ATM_ZATM is not set -# CONFIG_AUDIT is not set -# CONFIG_AUDIT_ARCH is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_AUTOFS_FS is not set -CONFIG_AX25=m -# CONFIG_AX25_DAMA_SLAVE is not set -# CONFIG_AX88796 is not set -# CONFIG_B44 is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_CORGI is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_BACKLIGHT_PROGEAR is not set -CONFIG_BASE_FULL=y -CONFIG_BASE_SMALL=0 -# CONFIG_BASLER_EXCITE is not set -# CONFIG_BATTERY_DS2760 is not set -CONFIG_BATTERY_OLPC=y -# CONFIG_BAYCOM_EPP is not set -# CONFIG_BAYCOM_PAR is not set -# CONFIG_BAYCOM_SER_FDX is not set -# CONFIG_BAYCOM_SER_HDX is not set -CONFIG_BCM43XX=m -CONFIG_BCM43XX_DEBUG=y -CONFIG_BCM43XX_DMA=y -CONFIG_BCM43XX_DMA_AND_PIO_MODE=y -# CONFIG_BCM43XX_DMA_MODE is not set -CONFIG_BCM43XX_PIO=y -# CONFIG_BCM43XX_PIO_MODE is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=y -CONFIG_BITREVERSE=y -# CONFIG_BLINK is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_CPQ_DA is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_BLK_DEV_ATIIXP is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_CRYPTOLOOP=m -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_CS5535 is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_DELKIN is not set -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_GENERIC is not set -# CONFIG_BLK_DEV_HD is not set -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_BLK_DEV_IDEPNP is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_INITRD=y -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_BLK_DEV_IT8213 is not set -# CONFIG_BLK_DEV_IT821X is not set -# CONFIG_BLK_DEV_JMICRON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_OFFBOARD is not set -# CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_BLK_DEV_SC1200 is not set -CONFIG_BLK_DEV_SD=y -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SIS5513 is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_TC86C001 is not set -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_UB is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -CONFIG_BLOCK=y -# CONFIG_BNX2 is not set -# CONFIG_BONDING is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -CONFIG_BOUNCE=y -# CONFIG_BPQETHER is not set -CONFIG_BRIDGE=y -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_ULOG=m -CONFIG_BRIDGE_EBT_VLAN=m -# CONFIG_BRIDGE_NETFILTER is not set -# CONFIG_BRIDGE_NF_EBTABLES is not set -CONFIG_BROKEN_ON_SMP=y -CONFIG_BSD_DISKLABEL=y -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_BT is not set -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -# CONFIG_BT_CMTP is not set -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBFUSB=m -# CONFIG_BT_HCIBLUECARD is not set -CONFIG_BT_HCIBPA10X=m -# CONFIG_BT_HCIBT3C is not set -# CONFIG_BT_HCIBTUART is not set -# CONFIG_BT_HCIDTL1 is not set -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUSB=m -CONFIG_BT_HCIUSB_SCO=y -CONFIG_BT_HCIVHCI=m -CONFIG_BT_HIDP=m -CONFIG_BT_L2CAP=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_SCO=m -CONFIG_BUG=y -# CONFIG_CAPI_AVM is not set -# CONFIG_CAPI_EICON is not set -# CONFIG_CAPI_TRACE is not set -CONFIG_CARDBUS=y -# CONFIG_CARDMAN_4000 is not set -# CONFIG_CARDMAN_4040 is not set -# CONFIG_CASSINI is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_CDROM_PKTCDVD is not set -CONFIG_CFG80211=m -# CONFIG_CGROUPS is not set -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_CHR_DEV_SCH is not set -CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_EXPERIMENTAL is not set -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_STATS=y -# CONFIG_CIFS_STATS2 is not set -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_XATTR is not set -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_CLS_U32_MARK=y -CONFIG_CLS_U32_PERF=y -CONFIG_CMDLINE="" -# CONFIG_CODA_FS is not set -CONFIG_COMPAT_VDSO=y -CONFIG_CONFIGFS_FS=y -# CONFIG_CONNECTOR is not set -# CONFIG_CPU5_WDT is not set -# CONFIG_CPU_FREQ is not set -# CONFIG_CPU_IDLE is not set -# CONFIG_CRAMFS is not set -CONFIG_CRC16=m -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_CRC_CCITT=m -# CONFIG_CRC_ITU_T is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_AES_586 is not set -CONFIG_CRYPTO_ALGAPI=m -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_AUTHENC is not set -CONFIG_CRYPTO_BLKCIPHER=m -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_GF128MUL is not set -CONFIG_CRYPTO_HASH=m -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_TWOFISH_586 is not set -CONFIG_CRYPTO_TWOFISH_COMMON=m -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CS5535_GPIO is not set -# CONFIG_DAB is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_DCDBAS is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_INFO is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_RODATA is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_SHIRQ is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_STACKOVERFLOW is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DECNET is not set -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_BIC is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_CUBIC is not set -CONFIG_DEFAULT_DEADLINE=y -# CONFIG_DEFAULT_HTCP is not set -CONFIG_DEFAULT_IOSCHED="deadline" -# CONFIG_DEFAULT_NOOP is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="vegas" -CONFIG_DEFAULT_VEGAS=y -# CONFIG_DEFAULT_WESTWOOD is not set -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -# CONFIG_DELL_RBU is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVPORT=y -# CONFIG_DGRS is not set -# CONFIG_DISABLE_SUSPEND_VT_SWITCH is not set -# CONFIG_DISCONTIGMEM_MANUAL is not set -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_DL2K is not set -# CONFIG_DLM is not set -# CONFIG_DMADEVICES is not set -# CONFIG_DMA_ENGINE is not set -CONFIG_DMI=y -CONFIG_DMIID=y -CONFIG_DNOTIFY=y -CONFIG_DOUBLEFAULT=y -CONFIG_DRM=y -# CONFIG_DRM_MGA is not set -# CONFIG_DRM_R128 is not set -# CONFIG_DRM_RADEON is not set -# CONFIG_DRM_SAVAGE is not set -# CONFIG_DRM_TDFX is not set -# CONFIG_DRM_VIA is not set -# CONFIG_DS1682 is not set -# CONFIG_DTLK is not set -# CONFIG_DUMMY is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_DVB is not set -# CONFIG_DVB_CORE is not set -# CONFIG_E100 is not set -# CONFIG_E1000 is not set -# CONFIG_E1000E is not set -CONFIG_EARLY_PRINTK=y -# CONFIG_ECONET is not set -# CONFIG_EDAC is not set -# CONFIG_EDD is not set -# CONFIG_EEPRO100 is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_EFS_FS is not set -CONFIG_ELF_CORE=y -CONFIG_EMBEDDED=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -# CONFIG_EPIC100 is not set -CONFIG_EPOLL=y -# CONFIG_EQUALIZER is not set -# CONFIG_EUROTECH_WDT is not set -CONFIG_EVENTFD=y -CONFIG_EXPERIMENTAL=y -CONFIG_EXPORTFS=m -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set -# CONFIG_FAIR_GROUP_SCHED is not set -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_FAT_FS=m -# CONFIG_FAULT_INJECTION is not set -CONFIG_FB=y -# CONFIG_FB_3DFX is not set -# CONFIG_FB_ARC is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_CYBLA is not set -# CONFIG_FB_DDC is not set -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_EFI is not set -CONFIG_FB_GEODE=y -CONFIG_FB_GEODE_GX=y -CONFIG_FB_GEODE_GX1=y -CONFIG_FB_GEODE_LX=y -# CONFIG_FB_HECUBA is not set -# CONFIG_FB_HGA is not set -# CONFIG_FB_I810 is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_INTEL is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_LE80578 is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_NVIDIA is not set -CONFIG_FB_OLPC_DCON=y -# CONFIG_FB_PM2 is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_TILEBLITTING is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_VESA is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FDDI is not set -# CONFIG_FEALNX is not set -CONFIG_FIB_RULES=y -# CONFIG_FIREWIRE is not set -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FLATMEM=y -CONFIG_FLATMEM_MANUAL=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -# CONFIG_FORCEDETH is not set -CONFIG_FORCED_INLINING=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FRAME_POINTER is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_FTL is not set -# CONFIG_FUSE_FS is not set -# CONFIG_FUSION is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set -# CONFIG_FUSION_SPI is not set -CONFIG_FUTEX=y -CONFIG_FW_LOADER=y -CONFIG_GACT_PROB=y -# CONFIG_GAMEPORT is not set -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CMOS_UPDATE=y -# CONFIG_GENERIC_CPU is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_TIME=y -# CONFIG_GENERIC_TIME_VSYSCALL is not set -CONFIG_GEODE_MFGPT_TIMER=y -# CONFIG_GFS2_FS is not set -# CONFIG_GPIO_DEVICE is not set -# CONFIG_HAMACHI is not set -# CONFIG_HAMRADIO is not set -# CONFIG_HANGCHECK_TIMER is not set -# CONFIG_HAPPYMEAL is not set -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -# CONFIG_HEADERS_CHECK is not set -# CONFIG_HERMES is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_HFS_FS is not set -CONFIG_HIBERNATION=y -CONFIG_HIBERNATION_UP_POSSIBLE=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set -# CONFIG_HID_DEBUG is not set -# CONFIG_HID_FF is not set -CONFIG_HID_SUPPORT=y -# CONFIG_HIGHMEM4G is not set -# CONFIG_HIGHMEM64G is not set -CONFIG_HIGH_RES_TIMERS=y -# CONFIG_HIPPI is not set -# CONFIG_HOSTAP is not set -# CONFIG_HOSTAP_CS is not set -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -CONFIG_HOSTAP_PCI=m -CONFIG_HOSTAP_PLX=m -CONFIG_HOTPLUG=y -# CONFIG_HOTPLUG_CPU is not set -# CONFIG_HOTPLUG_PCI is not set -# CONFIG_HP100 is not set -# CONFIG_HPET_TIMER is not set -# CONFIG_HPFS_FS is not set -CONFIG_HT_IRQ=y -# CONFIG_HUGETLBFS is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_AMD is not set -CONFIG_HW_RANDOM_GEODE=y -# CONFIG_HW_RANDOM_INTEL is not set -CONFIG_HW_RANDOM_VIA=y -CONFIG_HZ=100 -CONFIG_HZ_100=y -# CONFIG_HZ_1000 is not set -# CONFIG_HZ_1024 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -# CONFIG_HZ_300 is not set -# CONFIG_HZ_48 is not set -CONFIG_I2C=y -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCA is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_CHARDEV is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_ELEKTOR is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_VOODOO3 is not set -# CONFIG_I2O is not set -# CONFIG_I6300ESB_WDT is not set -# CONFIG_I82092 is not set -# CONFIG_I8K is not set -# CONFIG_IB700_WDT is not set -# CONFIG_IBMASR is not set -# CONFIG_IBM_ASM is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_IDE is not set -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_IDEDMA_IVB is not set -# CONFIG_IDEDMA_ONLYDISK is not set -# CONFIG_IDEPCI_SHARE_IRQ is not set -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_IDE_PROC_FS=y -# CONFIG_IDE_TASK_IOCTL is not set -# CONFIG_IEEE1394 is not set -# CONFIG_IEEE80211 is not set -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m -CONFIG_IEEE80211_CRYPT_WEP=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_IFB=m -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_IMQ=m -# CONFIG_IMQ_BEHAVIOR_AA is not set -# CONFIG_IMQ_BEHAVIOR_AB is not set -CONFIG_IMQ_BEHAVIOR_BA=y -# CONFIG_IMQ_BEHAVIOR_BB is not set -CONFIG_IMQ_NUM_DEVS=2 -CONFIG_INET=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_BEET=m -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET_AH is not set -CONFIG_INET_DIAG=m -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_LRO is not set -CONFIG_INET_TCP_DIAG=m -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INFINIBAND is not set -# CONFIG_INFTL is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INIT_ENV_ARG_LIMIT=32 -# CONFIG_INOTIFY is not set -# CONFIG_INOTIFY_USER is not set -CONFIG_INPUT=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_EVBUG is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_JOYSTICK is not set -CONFIG_INPUT_KEYBOARD=y -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_MISC is not set -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_PCSPKR is not set -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_UINPUT is not set -# CONFIG_INPUT_WISTRON_BTNS is not set -CONFIG_INSTRUMENTATION=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_NOOP=y -# CONFIG_IP1000 is not set -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_LIMIT=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_OWNER=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_IMQ=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_TARGET_ROUTE=m -# CONFIG_IPC_NS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_IPSEC_NAT_TRAVERSAL=y -# CONFIG_IPV6 is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_IPV6_PRIVACY is not set -CONFIG_IPV6_ROUTER_PREF=y -# CONFIG_IPV6_ROUTE_INFO is not set -CONFIG_IPV6_SIT=m -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPW2100 is not set -# CONFIG_IPW2100_DEBUG is not set -CONFIG_IPW2100_MONITOR=y -# CONFIG_IPW2200 is not set -# CONFIG_IPW2200_DEBUG is not set -CONFIG_IPW2200_MONITOR=y -# CONFIG_IPW2200_PROMISCUOUS is not set -# CONFIG_IPW2200_QOS is not set -# CONFIG_IPW2200_RADIOTAP is not set -# CONFIG_IPX is not set -CONFIG_IP_ADVANCED_ROUTER=y -# CONFIG_IP_DCCP is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -# CONFIG_IP_MROUTE is not set -CONFIG_IP_MULTICAST=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_NF_AMANDA=m -CONFIG_IP_NF_ARPFILTER=m -# CONFIG_IP_NF_ARPTABLES is not set -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP_NF_CONNTRACK=y -# CONFIG_IP_NF_CONNTRACK_EVENTS is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -CONFIG_IP_NF_CT_ACCT=y -CONFIG_IP_NF_CT_PROTO_SCTP=m -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_H323=m -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_IRC=m -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_MATCH_ADDRTYPE=m -# CONFIG_IP_NF_MATCH_AH is not set -# CONFIG_IP_NF_MATCH_ECN is not set -CONFIG_IP_NF_MATCH_HASHLIMIT=m -# CONFIG_IP_NF_MATCH_IPP2P is not set -CONFIG_IP_NF_MATCH_IPRANGE=m -# CONFIG_IP_NF_MATCH_OWNER is not set -# CONFIG_IP_NF_MATCH_RECENT is not set -CONFIG_IP_NF_MATCH_SET=m -# CONFIG_IP_NF_MATCH_TIME is not set -# CONFIG_IP_NF_MATCH_TOS is not set -# CONFIG_IP_NF_MATCH_TTL is not set -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_NAT_AMANDA=m -CONFIG_IP_NF_NAT_FTP=m -CONFIG_IP_NF_NAT_H323=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_NAT_PPTP=m -CONFIG_IP_NF_NAT_SIP=m -# CONFIG_IP_NF_NAT_SNMP_BASIC is not set -CONFIG_IP_NF_NAT_TFTP=m -# CONFIG_IP_NF_NETBIOS_NS is not set -CONFIG_IP_NF_PPTP=m -# CONFIG_IP_NF_QUEUE is not set -CONFIG_IP_NF_RAW=m -# CONFIG_IP_NF_SET is not set -CONFIG_IP_NF_SET_HASHSIZE=1024 -CONFIG_IP_NF_SET_IPHASH=m -CONFIG_IP_NF_SET_IPMAP=m -CONFIG_IP_NF_SET_IPPORTHASH=m -CONFIG_IP_NF_SET_IPTREE=m -CONFIG_IP_NF_SET_IPTREEMAP=m -CONFIG_IP_NF_SET_MACIPMAP=m -CONFIG_IP_NF_SET_MAX=256 -CONFIG_IP_NF_SET_NETHASH=m -CONFIG_IP_NF_SET_PORTMAP=m -CONFIG_IP_NF_SIP=m -# CONFIG_IP_NF_TARGET_CLUSTERIP is not set -# CONFIG_IP_NF_TARGET_ECN is not set -# CONFIG_IP_NF_TARGET_IMQ is not set -# CONFIG_IP_NF_TARGET_LOG is not set -CONFIG_IP_NF_TARGET_MASQUERADE=y -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_NF_TARGET_REDIRECT is not set -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_TARGET_ROUTE=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_IP_NF_TARGET_SET=m -# CONFIG_IP_NF_TARGET_TOS is not set -# CONFIG_IP_NF_TARGET_TTL is not set -# CONFIG_IP_NF_TARGET_ULOG is not set -CONFIG_IP_NF_TFTP=m -# CONFIG_IP_PNP is not set -CONFIG_IP_ROUTE_FWMARK=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_MULTIPATH_CACHED=y -CONFIG_IP_ROUTE_MULTIPATH_DRR=m -CONFIG_IP_ROUTE_MULTIPATH_RANDOM=m -CONFIG_IP_ROUTE_MULTIPATH_RR=m -CONFIG_IP_ROUTE_MULTIPATH_WRANDOM=m -CONFIG_IP_ROUTE_VERBOSE=y -# CONFIG_IP_SCTP is not set -# CONFIG_IP_VS is not set -# CONFIG_IRDA is not set -# CONFIG_ISA is not set -CONFIG_ISA_DMA_API=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_ISDN is not set -CONFIG_ISDN_CAPI=m -CONFIG_ISDN_CAPI_CAPI20=m -CONFIG_ISDN_CAPI_CAPIFS=m -CONFIG_ISDN_CAPI_CAPIFS_BOOL=y -CONFIG_ISDN_CAPI_MIDDLEWARE=y -# CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON is not set -# CONFIG_ISDN_I4L is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_IT8712F_WDT is not set -# CONFIG_ITCO_WDT is not set -# CONFIG_IXGB is not set -CONFIG_JBD=m -# CONFIG_JBD_DEBUG is not set -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -# CONFIG_JFFS2_CMODE_NONE is not set -CONFIG_JFFS2_CMODE_PRIORITY=y -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS_FS is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_FS is not set -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_JOLIET=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_KEXEC=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYS is not set -CONFIG_KMOD=y -# CONFIG_KPROBES is not set -CONFIG_KTIME_SCALAR=y -# CONFIG_KVM is not set -# CONFIG_LAPB is not set -# CONFIG_LASAT is not set -# CONFIG_LBD is not set -CONFIG_LCD_CLASS_DEVICE=y -# CONFIG_LDM_PARTITION is not set -# CONFIG_LEDS_ALIX is not set -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -# CONFIG_LEDS_TRIGGER_IDE_DISK is not set -# CONFIG_LEDS_TRIGGER_MORSE is not set -CONFIG_LEDS_TRIGGER_TIMER=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_LGUEST is not set -CONFIG_LIBCRC32C=m -# CONFIG_LIBERTAS is not set -# CONFIG_LIBERTAS_USB is not set -CONFIG_LLC=y -CONFIG_LLC2=m -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCKD=m -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_LOCKD_V4=y -# CONFIG_LOCK_STAT is not set -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_LSF is not set -# CONFIG_LXT_PHY is not set -# CONFIG_M386 is not set -# CONFIG_M486 is not set -# CONFIG_M586 is not set -# CONFIG_M586MMX is not set -# CONFIG_M586TSC is not set -# CONFIG_M686 is not set -# CONFIG_MAC80211 is not set -# CONFIG_MAC80211_DEBUG is not set -# CONFIG_MAC80211_LEDS is not set -# CONFIG_MACHZ_WDT is not set -# CONFIG_MACINTOSH_DRIVERS is not set -# CONFIG_MACVLAN is not set -# CONFIG_MAC_EMUMOUSEBTN is not set -CONFIG_MAC_PARTITION=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MARKEINS is not set -# CONFIG_MARKERS is not set -# CONFIG_MARVELL_PHY is not set -# CONFIG_MATH_EMULATION is not set -# CONFIG_MCA is not set -# CONFIG_MCORE2 is not set -# CONFIG_MCRUSOE is not set -# CONFIG_MCYRIXIII is not set -# CONFIG_MD is not set -# CONFIG_MEFFICEON is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MGEODEGX1 is not set -CONFIG_MGEODE_LX=y -CONFIG_MICROCODE=y -CONFIG_MICROCODE_OLD_INTERFACE=y -CONFIG_MII=y -# CONFIG_MINIX_FS is not set -# CONFIG_MINIX_SUBPARTITION is not set -CONFIG_MINI_FO=y -CONFIG_MISC_DEVICES=y -# CONFIG_MK6 is not set -# CONFIG_MK7 is not set -# CONFIG_MK8 is not set -CONFIG_MKISS=m -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_RICOH_MMC is not set -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_TIFM_SD is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -# CONFIG_MMC_WBSD is not set -CONFIG_MMU=y -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_INPORT is not set -# CONFIG_MOUSE_LOGIBM is not set -# CONFIG_MOUSE_PC110PAD is not set -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -# CONFIG_MOUSE_PS2_OLPC is not set -CONFIG_MOUSE_PS2_SYNAPTICS=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MPENTIUM4 is not set -# CONFIG_MPENTIUMII is not set -# CONFIG_MPENTIUMIII is not set -# CONFIG_MPENTIUMM is not set -# CONFIG_MPSC is not set -# CONFIG_MSDOS_FS is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_ALAUDA is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_BLOCK2MTD=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CHAR=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -# CONFIG_MTD_INTEL_VR_NOR is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_CAFE=y -# CONFIG_MTD_NAND_CS553X is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_ONENAND is not set -CONFIG_MTD_OOPS=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_PCI=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_ROM is not set -CONFIG_MTD_ROOTFS_ROOT_DEV=y -CONFIG_MTD_ROOTFS_SPLIT=y -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_TS5500 is not set -# CONFIG_MTD_UBI is not set -# CONFIG_MTRR is not set -# CONFIG_MVIAC3_2 is not set -# CONFIG_MVIAC7 is not set -# CONFIG_MWAVE is not set -# CONFIG_MWINCHIP2 is not set -# CONFIG_MWINCHIP3D is not set -# CONFIG_MWINCHIPC6 is not set -# CONFIG_MYRI10GE is not set -# CONFIG_NATSEMI is not set -# CONFIG_NCP_FS is not set -# CONFIG_NE2K_PCI is not set -CONFIG_NET=y -# CONFIG_NETCONSOLE is not set -# CONFIG_NETDEBUG is not set -CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set -CONFIG_NETDEV_1000=y -# CONFIG_NETDEV_10000 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -# CONFIG_NETFILTER_NETLINK is not set -CONFIG_NETFILTER_XTABLES=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set -# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set -CONFIG_NETFILTER_XT_MATCH_DCCP=m -# CONFIG_NETFILTER_XT_MATCH_DSCP is not set -# CONFIG_NETFILTER_XT_MATCH_ESP is not set -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -# CONFIG_NETFILTER_XT_MATCH_HELPER is not set -CONFIG_NETFILTER_XT_MATCH_LAYER7=m -# CONFIG_NETFILTER_XT_MATCH_LAYER7_DEBUG is not set -# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -# CONFIG_NETFILTER_XT_MATCH_MAC is not set -# CONFIG_NETFILTER_XT_MATCH_MARK is not set -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set -CONFIG_NETFILTER_XT_MATCH_POLICY=m -# CONFIG_NETFILTER_XT_MATCH_PORTSCAN is not set -# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=y -# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set -# CONFIG_NETFILTER_XT_MATCH_STRING is not set -# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# CONFIG_NETFILTER_XT_TARGET_CHAOS is not set -# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set -# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set -# CONFIG_NETFILTER_XT_TARGET_DELUDE is not set -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -# CONFIG_NETFILTER_XT_TARGET_MARK is not set -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -# CONFIG_NETFILTER_XT_TARGET_TARPIT is not set -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_TARGET_TRACE=m -# CONFIG_NETPOLL is not set -# CONFIG_NETROM is not set -CONFIG_NETWORK_FILESYSTEMS=y -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_NET_9P is not set -CONFIG_NET_ACT_GACT=m -CONFIG_NET_ACT_IPT=m -CONFIG_NET_ACT_MIRRED=m -# CONFIG_NET_ACT_NAT is not set -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_POLICE=y -# CONFIG_NET_ACT_SIMP is not set -CONFIG_NET_CLS=y -CONFIG_NET_CLS_ACT=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_IND=y -CONFIG_NET_CLS_POLICE=y -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_U32=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_STACK=32 -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_ESTIMATOR=y -CONFIG_NET_ETHERNET=y -# CONFIG_NET_FC is not set -# CONFIG_NET_IPGRE is not set -CONFIG_NET_IPGRE_BROADCAST=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_KEY is not set -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_NET_PCI=y -# CONFIG_NET_PCMCIA is not set -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_POLL_CONTROLLER is not set -CONFIG_NET_RADIO=y -# CONFIG_NET_SB1000 is not set -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_CBQ=m -# CONFIG_NET_SCH_CLK_CPU is not set -# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set -CONFIG_NET_SCH_CLK_JIFFIES=y -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_ESFQ is not set -CONFIG_NET_SCH_ESFQ_NFCT=y -CONFIG_NET_SCH_FIFO=y -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_INGRESS is not set -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_PRIO=m -# CONFIG_NET_SCH_RED is not set -CONFIG_NET_SCH_RR=m -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_TULIP is not set -CONFIG_NET_VENDOR_3COM=y -CONFIG_NET_WIRELESS=y -CONFIG_NET_WIRELESS_RTNETLINK=y -# CONFIG_NEW_GPIO is not set -CONFIG_NEW_LEDS=y -# CONFIG_NFSD is not set -CONFIG_NFSD_TCP=y -# CONFIG_NFSD_V2_ACL is not set -CONFIG_NFSD_V3=y -# CONFIG_NFSD_V3_ACL is not set -CONFIG_NFSD_V4=y -# CONFIG_NFS_ACL_SUPPORT is not set -CONFIG_NFS_COMMON=y -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFS_FS is not set -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFTL is not set -CONFIG_NF_CONNTRACK=y -# CONFIG_NF_CONNTRACK_AMANDA is not set -CONFIG_NF_CONNTRACK_ENABLED=y -# CONFIG_NF_CONNTRACK_EVENTS is not set -CONFIG_NF_CONNTRACK_FTP=m -# CONFIG_NF_CONNTRACK_H323 is not set -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_MARK=y -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -# CONFIG_NF_CONNTRACK_PPTP is not set -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -# CONFIG_NF_CONNTRACK_RTSP is not set -# CONFIG_NF_CONNTRACK_SANE is not set -# CONFIG_NF_CONNTRACK_SIP is not set -CONFIG_NF_CONNTRACK_SUPPORT=y -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CT_PROTO_GRE=m -# CONFIG_NF_CT_PROTO_SCTP is not set -# CONFIG_NF_CT_PROTO_UDPLITE is not set -CONFIG_NF_NAT=y -# CONFIG_NF_NAT_AMANDA is not set -CONFIG_NF_NAT_FTP=m -# CONFIG_NF_NAT_H323 is not set -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_NEEDED=y -# CONFIG_NF_NAT_PPTP is not set -CONFIG_NF_NAT_PROTO_GRE=m -# CONFIG_NF_NAT_RTSP is not set -# CONFIG_NF_NAT_SIP is not set -# CONFIG_NF_NAT_SNMP_BASIC is not set -CONFIG_NF_NAT_TFTP=m -CONFIG_NL80211=y -# CONFIG_NLS is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_CODEPAGE_1250=m -# CONFIG_NLS_CODEPAGE_1251 is not set -CONFIG_NLS_CODEPAGE_437=m -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=m -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_ISO8859_1=m -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -CONFIG_NLS_ISO8859_15=m -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_ISO8859_9 is not set -CONFIG_NLS_KOI8_R=m -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=m -CONFIG_NOHIGHMEM=y -CONFIG_NORTEL_HERMES=m -CONFIG_NO_HZ=y -CONFIG_NR_QUICK=1 -# CONFIG_NS83820 is not set -CONFIG_NSC_GPIO=m -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_RW is not set -CONFIG_NVRAM=y -# CONFIG_OCFS2_FS is not set -CONFIG_OLPC=y -CONFIG_OLPC_PM=y -CONFIG_OPEN_FIRMWARE=y -# CONFIG_OSF_PARTITION is not set -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PARAVIRT_GUEST is not set -# CONFIG_PARPORT is not set -# CONFIG_PARPORT_PC is not set -CONFIG_PARTITION_ADVANCED=y -# CONFIG_PATA_ALI is not set -# CONFIG_PATA_AMD is not set -# CONFIG_PATA_ARTOP is not set -# CONFIG_PATA_ATIIXP is not set -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CS5520 is not set -# CONFIG_PATA_CS5530 is not set -# CONFIG_PATA_CS5535 is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_ISAPNP is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_LEGACY is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_OLDPIIX is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_OPTIDMA is not set -# CONFIG_PATA_PCMCIA is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_PDC_OLD is not set -CONFIG_PATA_PLATFORM=m -# CONFIG_PATA_QDI is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RZ1000 is not set -# CONFIG_PATA_SC1200 is not set -# CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set -# CONFIG_PATA_WINBOND_VLB is not set -# CONFIG_PC300TOO is not set -CONFIG_PC8736x_GPIO=m -# CONFIG_PC87413_WDT is not set -# CONFIG_PCCARD is not set -CONFIG_PCI=y -# CONFIG_PCIEPORTBUS is not set -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_PCI_ATMEL is not set -# CONFIG_PCI_DEBUG is not set -CONFIG_PCI_DIRECT=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_GOANY is not set -# CONFIG_PCI_GOBIOS is not set -# CONFIG_PCI_GODIRECT is not set -# CONFIG_PCI_GOMMCONFIG is not set -CONFIG_PCI_GOOLPC=y -CONFIG_PCI_HERMES=m -# CONFIG_PCI_LEGACY is not set -# CONFIG_PCI_MSI is not set -CONFIG_PCI_OLPC=y -# CONFIG_PCMCIA is not set -# CONFIG_PCMCIA_AHA152X is not set -# CONFIG_PCMCIA_ATMEL is not set -# CONFIG_PCMCIA_DEBUG is not set -# CONFIG_PCMCIA_FDOMAIN is not set -# CONFIG_PCMCIA_HERMES is not set -# CONFIG_PCMCIA_IOCTL is not set -# CONFIG_PCMCIA_LOAD_CIS is not set -# CONFIG_PCMCIA_NETWAVE is not set -# CONFIG_PCMCIA_NINJA_SCSI is not set -# CONFIG_PCMCIA_QLOGIC is not set -# CONFIG_PCMCIA_RAYCS is not set -# CONFIG_PCMCIA_SPECTRUM is not set -# CONFIG_PCMCIA_SYM53C500 is not set -# CONFIG_PCMCIA_WAVELAN is not set -# CONFIG_PCMCIA_WL3501 is not set -# CONFIG_PCNET32 is not set -# CONFIG_PD6729 is not set -# CONFIG_PDA_POWER is not set -# CONFIG_PDC_ADMA is not set -# CONFIG_PHANTOM is not set -# CONFIG_PHONE is not set -# CONFIG_PHYLIB is not set -CONFIG_PHYSICAL_ALIGN=0x100000 -CONFIG_PHYSICAL_START=0x100000 -# CONFIG_PID_NS is not set -CONFIG_PLIST=y -CONFIG_PLX_HERMES=m -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_PM_LEGACY=y -CONFIG_PM_SLEEP=y -CONFIG_PM_STD_PARTITION="" -# CONFIG_PM_TRACE is not set -# CONFIG_PM_VERBOSE is not set -# CONFIG_POSIX_MQUEUE is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -CONFIG_PPP=m -CONFIG_PPPOATM=m -CONFIG_PPPOE=m -CONFIG_PPPOL2TP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -# CONFIG_PPP_MPPE is not set -CONFIG_PPP_MULTILINK=y -# CONFIG_PPP_SYNC_TTY is not set -# CONFIG_PREEMPT is not set -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_PRINTK=y -# CONFIG_PRINTK_TIME is not set -# CONFIG_PRISM54 is not set -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -# CONFIG_PROFILING is not set -# CONFIG_PROMFS_FS is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_QEMU is not set -# CONFIG_QLA3XXX is not set -# CONFIG_QNX4FS_FS is not set -CONFIG_QUICKLIST=y -# CONFIG_QUOTA is not set -# CONFIG_R3964 is not set -# CONFIG_R8169 is not set -# CONFIG_RADIO_ADAPTERS is not set -# CONFIG_RADIO_AZTECH is not set -# CONFIG_RADIO_CADET is not set -# CONFIG_RADIO_GEMTEK is not set -# CONFIG_RADIO_GEMTEK_PCI is not set -# CONFIG_RADIO_MAESTRO is not set -# CONFIG_RADIO_MAXIRADIO is not set -# CONFIG_RADIO_RTRACK is not set -# CONFIG_RADIO_RTRACK2 is not set -# CONFIG_RADIO_SF16FMI is not set -# CONFIG_RADIO_SF16FMR2 is not set -# CONFIG_RADIO_TERRATEC is not set -# CONFIG_RADIO_TRUST is not set -# CONFIG_RADIO_TYPHOON is not set -# CONFIG_RADIO_ZOLTRIX is not set -# CONFIG_RAID_ATTRS is not set -CONFIG_RAMFS=y -# CONFIG_RAW_DRIVER is not set -# CONFIG_RCU_TORTURE_TEST is not set -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC16=y -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_FS_XATTR is not set -# CONFIG_REISERFS_PROC_INFO is not set -CONFIG_RELAY=y -# CONFIG_RELOCATABLE is not set -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_RFD_FTL is not set -# CONFIG_RFKILL is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_ROSE is not set -CONFIG_RPCSEC_GSS_KRB5=m -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_RTC=y -# CONFIG_RTC_CLASS is not set -CONFIG_RTC_DRV_CMOS=y -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTL8187 is not set -CONFIG_RT_MUTEXES=y -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_RWSEM_GENERIC_SPINLOCK is not set -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_S2IO is not set -# CONFIG_SAMPLES is not set -# CONFIG_SATA_AHCI is not set -# CONFIG_SATA_INIC162X is not set -# CONFIG_SATA_MV is not set -# CONFIG_SATA_NV is not set -# CONFIG_SATA_PROMISE is not set -# CONFIG_SATA_QSTOR is not set -# CONFIG_SATA_SIL is not set -# CONFIG_SATA_SIL24 is not set -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_SVW is not set -# CONFIG_SATA_SX4 is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set -# CONFIG_SBC7240_WDT is not set -# CONFIG_SBC8360_WDT is not set -# CONFIG_SBC_EPX_C3_WATCHDOG is not set -# CONFIG_SC1200_WDT is not set -# CONFIG_SC520_WDT is not set -# CONFIG_SC92031 is not set -# CONFIG_SCHEDSTATS is not set -CONFIG_SCHED_DEBUG=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_SCSI=y -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC94XX is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DEBUG is not set -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_ESP_CORE is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_LOGGING is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_SCSI_LPFC is not set -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_PAS16 is not set -CONFIG_SCSI_PROC_FS=y -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -# CONFIG_SCSI_SEAGATE is not set -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_SRP is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_STEX is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_ULTRASTOR is not set -CONFIG_SCSI_WAIT_SCAN=m -# CONFIG_SCx200 is not set -# CONFIG_SCx200_ACB is not set -# CONFIG_SDIO_UART is not set -# CONFIG_SECCOMP is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_SEMAPHORE_SLEEPERS=y -# CONFIG_SENSORS_ABITUGURU is not set -# CONFIG_SENSORS_ABITUGURU3 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_APPLESMC is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_CORETEMP is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_HDAPS is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_K8TEMP is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_CS=m -# CONFIG_SERIAL_8250_EXTENDED is not set -CONFIG_SERIAL_8250_NR_UARTS=2 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_SERIO=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_I8042=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_RAW is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SGI_IOC4 is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_SHAPER is not set -CONFIG_SHMEM=y -CONFIG_SIGNALFD=y -# CONFIG_SIS190 is not set -# CONFIG_SIS900 is not set -# CONFIG_SK98LIN is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -CONFIG_SLAB=y -CONFIG_SLABINFO=y -CONFIG_SLHC=m -# CONFIG_SLIP is not set -# CONFIG_SLOB is not set -# CONFIG_SLUB is not set -# CONFIG_SMB_FS is not set -# CONFIG_SMB_NLS_DEFAULT is not set -# CONFIG_SMP is not set -# CONFIG_SMSC37B787_WDT is not set -CONFIG_SND=m -# CONFIG_SND_AC97_POWER_SAVE is not set -# CONFIG_SND_AD1816A is not set -# CONFIG_SND_AD1848 is not set -# CONFIG_SND_AD1889 is not set -# CONFIG_SND_ADLIB is not set -# CONFIG_SND_ALI5451 is not set -# CONFIG_SND_ALS100 is not set -# CONFIG_SND_ALS300 is not set -# CONFIG_SND_ALS4000 is not set -# CONFIG_SND_ATIIXP is not set -# CONFIG_SND_ATIIXP_MODEM is not set -# CONFIG_SND_AU8810 is not set -# CONFIG_SND_AU8820 is not set -# CONFIG_SND_AU8830 is not set -# CONFIG_SND_AZT2320 is not set -# CONFIG_SND_AZT3328 is not set -# CONFIG_SND_BT87X is not set -# CONFIG_SND_CA0106 is not set -# CONFIG_SND_CMI8330 is not set -# CONFIG_SND_CMIPCI is not set -# CONFIG_SND_CS4231 is not set -# CONFIG_SND_CS4232 is not set -# CONFIG_SND_CS4236 is not set -# CONFIG_SND_CS4281 is not set -# CONFIG_SND_CS46XX is not set -# CONFIG_SND_CS5535AUDIO is not set -# CONFIG_SND_DARLA20 is not set -# CONFIG_SND_DARLA24 is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_DT019X is not set -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_ECHO3G is not set -# CONFIG_SND_EMU10K1 is not set -# CONFIG_SND_EMU10K1X is not set -# CONFIG_SND_ENS1370 is not set -# CONFIG_SND_ENS1371 is not set -# CONFIG_SND_ES1688 is not set -# CONFIG_SND_ES18XX is not set -# CONFIG_SND_ES1938 is not set -# CONFIG_SND_ES1968 is not set -# CONFIG_SND_ES968 is not set -# CONFIG_SND_FM801 is not set -# CONFIG_SND_GINA20 is not set -# CONFIG_SND_GINA24 is not set -# CONFIG_SND_GUSCLASSIC is not set -# CONFIG_SND_GUSEXTREME is not set -# CONFIG_SND_GUSMAX is not set -# CONFIG_SND_HDA_INTEL is not set -# CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set -CONFIG_SND_HWDEP=m -# CONFIG_SND_ICE1712 is not set -# CONFIG_SND_ICE1724 is not set -# CONFIG_SND_INDIGO is not set -# CONFIG_SND_INDIGODJ is not set -# CONFIG_SND_INDIGOIO is not set -# CONFIG_SND_INTEL8X0 is not set -# CONFIG_SND_INTEL8X0M is not set -# CONFIG_SND_INTERWAVE is not set -# CONFIG_SND_INTERWAVE_STB is not set -# CONFIG_SND_KORG1212 is not set -# CONFIG_SND_LAYLA20 is not set -# CONFIG_SND_LAYLA24 is not set -# CONFIG_SND_MAESTRO3 is not set -# CONFIG_SND_MIA is not set -# CONFIG_SND_MIRO is not set -# CONFIG_SND_MIXART is not set -CONFIG_SND_MIXER_OSS=m -# CONFIG_SND_MONA is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_NM256 is not set -# CONFIG_SND_OPL3SA2 is not set -# CONFIG_SND_OPTI92X_AD1848 is not set -# CONFIG_SND_OPTI92X_CS4231 is not set -# CONFIG_SND_OPTI93X is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_PCM=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_PCM_OSS_PLUGINS=y -# CONFIG_SND_PCXHR is not set -# CONFIG_SND_PDAUDIOCF is not set -CONFIG_SND_RAWMIDI=m -# CONFIG_SND_RIPTIDE is not set -# CONFIG_SND_RME32 is not set -# CONFIG_SND_RME96 is not set -# CONFIG_SND_RME9652 is not set -# CONFIG_SND_RTCTIMER is not set -# CONFIG_SND_SB16 is not set -# CONFIG_SND_SB8 is not set -# CONFIG_SND_SBAWE is not set -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_SGALAXY is not set -# CONFIG_SND_SOC is not set -# CONFIG_SND_SONICVIBES is not set -# CONFIG_SND_SSCAPE is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -CONFIG_SND_TIMER=m -# CONFIG_SND_TRIDENT is not set -CONFIG_SND_USB_AUDIO=m -# CONFIG_SND_USB_CAIAQ is not set -# CONFIG_SND_USB_USX2Y is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VIA82XX is not set -# CONFIG_SND_VIA82XX_MODEM is not set -# CONFIG_SND_VX222 is not set -# CONFIG_SND_VXPOCKET is not set -# CONFIG_SND_WAVEFRONT is not set -# CONFIG_SND_YMFPCI is not set -# CONFIG_SNI_RM is not set -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_SONYPI is not set -# CONFIG_SOUND is not set -# CONFIG_SOUND_PRIME is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_SPARSEMEM_STATIC=y -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -# CONFIG_SQUASHFS_VMALLOC is not set -# CONFIG_SSB is not set -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSFDC is not set -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_STANDALONE=y -# CONFIG_STRIP is not set -# CONFIG_SUNDANCE is not set -# CONFIG_SUNGEM is not set -CONFIG_SUNRPC=m -# CONFIG_SUNRPC_BIND34 is not set -CONFIG_SUNRPC_GSS=m -# CONFIG_SUN_PARTITION is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_UP_POSSIBLE=y -CONFIG_SWAP=y -# CONFIG_SYNCLINK_CS is not set -CONFIG_SYN_COOKIES=y -CONFIG_SYSCTL=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSFS=y -# CONFIG_SYSFS_DEPRECATED is not set -# CONFIG_SYSPROF is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_SYSV_FS is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_TASKSTATS is not set -# CONFIG_TCG_TPM is not set -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=m -CONFIG_TCP_CONG_CUBIC=m -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_VEGAS=y -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_YEAH=m -# CONFIG_TCP_MD5SIG is not set -# CONFIG_TELCLOCK is not set -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TICK_ONESHOT=y -# CONFIG_TIFM_CORE is not set -# CONFIG_TIGON3 is not set -CONFIG_TIMERFD=y -# CONFIG_TIMER_STATS is not set -# CONFIG_TINY_SHMEM is not set -# CONFIG_TIPC is not set -# CONFIG_TLAN is not set -CONFIG_TMD_HERMES=m -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_TOSHIBA is not set -# CONFIG_TR is not set -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_TUN is not set -# CONFIG_TUNER_3036 is not set -# CONFIG_TUNER_TEA5761 is not set -# CONFIG_TYPHOON is not set -# CONFIG_UDF_FS is not set -CONFIG_UDF_NLS=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_UFS_FS is not set -CONFIG_UID16=y -# CONFIG_UIO is not set -# CONFIG_ULTRIX_PARTITION is not set -CONFIG_UNIX=y -CONFIG_UNIX98_PTYS=y -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_USB=y -# CONFIG_USBPCWATCHDOG is not set -# CONFIG_USB_ACECAD is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AIPTEK is not set -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_APPLETOUCH is not set -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARMLINUX=y -# CONFIG_USB_ATI_REMOTE is not set -# CONFIG_USB_ATI_REMOTE2 is not set -CONFIG_USB_ATM=m -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_BANDWIDTH is not set -CONFIG_USB_BELKIN=y -# CONFIG_USB_BERRY_CHARGE is not set -CONFIG_USB_CATC=m -# CONFIG_USB_CXACRU is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_DABUSB is not set -# CONFIG_USB_DEBUG is not set -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DSBR is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_SPLIT_ISO=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EPSON2888 is not set -# CONFIG_USB_ET61X251 is not set -CONFIG_USB_EZUSB=y -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_GADGET is not set -# CONFIG_USB_HID is not set -# CONFIG_USB_HIDDEV is not set -CONFIG_USB_HIDINPUT=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_KBD is not set -# CONFIG_USB_KBTAB is not set -# CONFIG_USB_KC2190 is not set -# CONFIG_USB_KEYSPAN_REMOTE is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LIBUSUAL is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_MOUSE is not set -CONFIG_USB_NET_AX8817X=m -CONFIG_USB_NET_CDCETHER=m -CONFIG_USB_NET_CDC_SUBSET=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_NET1080=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_NET_ZAURUS=m -# CONFIG_USB_OHCI_BIG_ENDIAN is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -# CONFIG_USB_OTG is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_PERSIST is not set -# CONFIG_USB_PHIDGET is not set -# CONFIG_USB_POWERMATE is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_SE401 is not set -# CONFIG_USB_SERIAL is not set -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_AIRPRIME=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CP2101=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -# CONFIG_USB_SERIAL_DEBUG is not set -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_HP4X=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OTI6858=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SAFE_PADDED=y -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_XIRCOM=m -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_SN9C102 is not set -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_ALAUDA=y -CONFIG_USB_STORAGE_DATAFAB=y -# CONFIG_USB_STORAGE_DEBUG is not set -CONFIG_USB_STORAGE_DPCM=y -CONFIG_USB_STORAGE_FREECOM=y -# CONFIG_USB_STORAGE_ISD200 is not set -CONFIG_USB_STORAGE_JUMPSHOT=y -CONFIG_USB_STORAGE_KARMA=y -# CONFIG_USB_STORAGE_ONETOUCH is not set -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_USBAT=y -# CONFIG_USB_STV680 is not set -CONFIG_USB_SUPPORT=y -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_TOUCHSCREEN is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_UHCI_HCD=y -# CONFIG_USB_USBNET is not set -CONFIG_USB_USBNET_MII=m -# CONFIG_USB_VICAM is not set -# CONFIG_USB_W9968CF is not set -# CONFIG_USB_WACOM is not set -# CONFIG_USB_XPAD is not set -# CONFIG_USB_XUSBATM is not set -CONFIG_USB_YEALINK=m -# CONFIG_USB_ZC0301 is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USER_NS is not set -# CONFIG_UTS_NS is not set -# CONFIG_VETH is not set -# CONFIG_VFAT_FS is not set -CONFIG_VGACON_SOFT_SCROLLBACK=y -CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -# CONFIG_VGASTATE is not set -CONFIG_VGA_CONSOLE=y -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT848 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_CAFE_CCIC is not set -# CONFIG_VIDEO_CAPTURE_DRIVERS is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CS53L32A is not set -# CONFIG_VIDEO_CX2341X is not set -# CONFIG_VIDEO_CX25840 is not set -# CONFIG_VIDEO_CX88 is not set -# CONFIG_VIDEO_DEV is not set -# CONFIG_VIDEO_DPC is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -# CONFIG_VIDEO_HEXIUM_GEMINI is not set -# CONFIG_VIDEO_HEXIUM_ORION is not set -# CONFIG_VIDEO_IVTV is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_MSP3400 is not set -# CONFIG_VIDEO_MXB is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_VIDEO_PMS is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA7111 is not set -# CONFIG_VIDEO_SAA7114 is not set -# CONFIG_VIDEO_SAA711X is not set -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7134 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_SAA7191 is not set -CONFIG_VIDEO_SELECT=y -# CONFIG_VIDEO_STRADIS is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_VIDEO_V4L1 is not set -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_VIDEO_V4L2=y -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_VPX3220 is not set -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_WM8775 is not set -# CONFIG_VIDEO_ZORAN is not set -CONFIG_VIRTUALIZATION=y -CONFIG_VIRT_TO_BUS=y -# CONFIG_VITESSE_PHY is not set -CONFIG_VLAN_8021Q=y -CONFIG_VM86=y -# CONFIG_VMSPLIT_1G is not set -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_2G_OPT is not set -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_3G_OPT is not set -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_VORTEX is not set -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_VXFS_FS is not set -# CONFIG_W1 is not set -# CONFIG_W83627HF_WDT is not set -# CONFIG_W83697HF_WDT is not set -# CONFIG_W83877F_WDT is not set -# CONFIG_W83977F_WDT is not set -# CONFIG_WAFER_WDT is not set -# CONFIG_WAN is not set -# CONFIG_WAN_ROUTER is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set -# CONFIG_WDTPCI is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WLAN_80211=y -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WR_PPMC is not set -# CONFIG_X25 is not set -CONFIG_X86=y -CONFIG_X86_32=y -# CONFIG_X86_64 is not set -# CONFIG_X86_BIGSMP is not set -CONFIG_X86_BIOS_REBOOT=y -CONFIG_X86_BSWAP=y -CONFIG_X86_CMPXCHG=y -# CONFIG_X86_CPUID is not set -# CONFIG_X86_ELAN is not set -# CONFIG_X86_ES7000 is not set -CONFIG_X86_FIND_SMP_CONFIG=y -CONFIG_X86_GENERIC=y -# CONFIG_X86_GENERICARCH is not set -CONFIG_X86_INTEL_USERCOPY=y -CONFIG_X86_INVLPG=y -CONFIG_X86_IO_APIC=y -CONFIG_X86_L1_CACHE_SHIFT=7 -CONFIG_X86_LOCAL_APIC=y -# CONFIG_X86_MCE is not set -CONFIG_X86_MINIMUM_CPU_FAMILY=4 -CONFIG_X86_MPPARSE=y -# CONFIG_X86_MSR is not set -# CONFIG_X86_NUMAQ is not set -# CONFIG_X86_PAE is not set -CONFIG_X86_PC=y -CONFIG_X86_POPAD_OK=y -# CONFIG_X86_REBOOTFIXUPS is not set -# CONFIG_X86_SUMMIT is not set -CONFIG_X86_TSC=y -CONFIG_X86_UP_APIC=y -CONFIG_X86_UP_IOAPIC=y -CONFIG_X86_USE_3DNOW=y -CONFIG_X86_USE_PPRO_CHECKSUM=y -# CONFIG_X86_VISWS is not set -# CONFIG_X86_VOYAGER is not set -# CONFIG_X86_VSMP is not set -CONFIG_X86_WP_WORKS_OK=y -CONFIG_X86_XADD=y -CONFIG_XFRM=y -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_USER=m -# CONFIG_XFS_FS is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_RT is not set -# CONFIG_XFS_SECURITY is not set -# CONFIG_YAFFS_FS is not set -# CONFIG_YAM is not set -# CONFIG_YELLOWFIN is not set -CONFIG_YENTA=m -# CONFIG_YENTA_O2 is not set -# CONFIG_YENTA_RICOH is not set -# CONFIG_YENTA_TI is not set -# CONFIG_YENTA_TOSHIBA is not set -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set -CONFIG_ZISOFS=y -CONFIG_ZISOFS_FS=m -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA=y -# CONFIG_ZONE_DMA32 is not set -CONFIG_ZONE_DMA_FLAG=1 diff --git a/target/linux/olpc/config-2.6.26 b/target/linux/olpc/config-2.6.26 deleted file mode 100644 index 63972953f6..0000000000 --- a/target/linux/olpc/config-2.6.26 +++ /dev/null @@ -1,725 +0,0 @@ -CONFIG_4KSTACKS=y -# CONFIG_64BIT is not set -CONFIG_AC97_BUS=m -CONFIG_ACPI=y -CONFIG_ACPI_AC=y -# CONFIG_ACPI_ASUS is not set -CONFIG_ACPI_BATTERY=y -CONFIG_ACPI_BLACKLIST_YEAR=0 -CONFIG_ACPI_BUTTON=y -# CONFIG_ACPI_CONTAINER is not set -# CONFIG_ACPI_CUSTOM_DSDT is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DOCK is not set -CONFIG_ACPI_EC=y -CONFIG_ACPI_FAN=y -CONFIG_ACPI_POWER=y -CONFIG_ACPI_PROCESSOR=y -# CONFIG_ACPI_PROCFS is not set -CONFIG_ACPI_PROCFS_POWER=y -CONFIG_ACPI_PROC_EVENT=y -# CONFIG_ACPI_SBS is not set -CONFIG_ACPI_SLEEP=y -CONFIG_ACPI_SYSFS_POWER=y -CONFIG_ACPI_SYSTEM=y -CONFIG_ACPI_THERMAL=y -# CONFIG_ACPI_TOSHIBA is not set -# CONFIG_ACPI_WMI is not set -# CONFIG_AGP is not set -# CONFIG_AIRO is not set -# CONFIG_APM is not set -CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig" -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y -CONFIG_ARCH_HAS_CPU_RELAX=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_AOUT=y -CONFIG_ARCH_SUPPORTS_MSI=y -CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ATM is not set -# CONFIG_ATMEL is not set -# CONFIG_AUDIT_ARCH is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_CORGI is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_BACKLIGHT_PROGEAR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BATTERY_DS2760 is not set -CONFIG_BATTERY_OLPC=y -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_MISC=y -CONFIG_BITREVERSE=y -# CONFIG_BLK_DEV is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -# CONFIG_BONDING is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -CONFIG_BOUNCE=y -# CONFIG_BT is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_CFG80211=y -CONFIG_CHR_DEV_SG=y -CONFIG_CLASSIC_RCU=y -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_COMPAT_VDSO=y -# CONFIG_CPA_DEBUG is not set -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEBUG is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -# CONFIG_CPU_FREQ_STAT_DETAILS is not set -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_IDLE is not set -# CONFIG_CRC_ITU_T is not set -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_AES_586 is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_ECB is not set -CONFIG_CRYPTO_GF128MUL=m -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_SALSA20_586 is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_TWOFISH_586 is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CS5535_GPIO is not set -# CONFIG_DCDBAS is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_INFO is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_NX_TEST is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUG_RODATA is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_SHIRQ is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_STACKOVERFLOW is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -CONFIG_DEFAULT_IO_DELAY_TYPE=0 -# CONFIG_DELL_RBU is not set -CONFIG_DETECT_SOFTLOCKUP=y -CONFIG_DEVPORT=y -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_DMADEVICES is not set -CONFIG_DMI=y -CONFIG_DMIID=y -CONFIG_DOUBLEFAULT=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -# CONFIG_EDAC is not set -# CONFIG_EDD is not set -# CONFIG_EFI is not set -CONFIG_ELF_CORE=y -CONFIG_EXT2_FS=y -# CONFIG_EXT3_FS is not set -CONFIG_FAST_CMPXCHG_LOCAL=y -# CONFIG_FAULT_INJECTION is not set -CONFIG_FB=y -# CONFIG_FB_3DFX is not set -# CONFIG_FB_ARC is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_CYBLA is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_EFI is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_GEODE=y -# CONFIG_FB_GEODE_GX is not set -# CONFIG_FB_GEODE_GX1 is not set -CONFIG_FB_GEODE_LX=y -# CONFIG_FB_HGA is not set -# CONFIG_FB_I810 is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_INTEL is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_LE80578 is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_N411 is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_TILEBLITTING is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_VESA is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FRAME_POINTER is not set -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CMOS_UPDATE=y -# CONFIG_GENERIC_CPU is not set -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -# CONFIG_GENERIC_GPIO is not set -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_ISA_DMA=y -# CONFIG_GENERIC_LOCKBREAK is not set -# CONFIG_GENERIC_TIME_VSYSCALL is not set -CONFIG_GEODE_MFGPT_TIMER=y -# CONFIG_HAMRADIO is not set -# CONFIG_HANGCHECK_TIMER is not set -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_HAVE_CPUMASK_OF_CPU_MAP is not set -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_HAVE_IDE=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set -CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y -# CONFIG_HERMES is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_HFS_FS is not set -CONFIG_HIBERNATION=y -CONFIG_HID=y -CONFIG_HID_SUPPORT=y -# CONFIG_HIGHMEM4G is not set -# CONFIG_HIGHMEM64G is not set -# CONFIG_HOSTAP is not set -# CONFIG_HPET is not set -CONFIG_HPET_EMULATE_RTC=y -CONFIG_HPET_TIMER=y -CONFIG_HT_IRQ=y -# CONFIG_HUGETLBFS is not set -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_AMD is not set -CONFIG_HW_RANDOM_GEODE=y -# CONFIG_HW_RANDOM_INTEL is not set -CONFIG_HW_RANDOM_VIA=y -CONFIG_I2C=m -CONFIG_I2C_BOARDINFO=y -# CONFIG_I8K is not set -# CONFIG_IDE is not set -# CONFIG_IEEE80211 is not set -# CONFIG_IFB is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1200 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=900 -# CONFIG_IOMMU_HELPER is not set -CONFIG_IO_DELAY_0X80=y -# CONFIG_IO_DELAY_0XED is not set -# CONFIG_IO_DELAY_NONE is not set -CONFIG_IO_DELAY_TYPE_0X80=0 -CONFIG_IO_DELAY_TYPE_0XED=1 -CONFIG_IO_DELAY_TYPE_NONE=3 -CONFIG_IO_DELAY_TYPE_UDELAY=2 -# CONFIG_IO_DELAY_UDELAY is not set -# CONFIG_IPV6 is not set -# CONFIG_IPW2100 is not set -# CONFIG_IPW2200 is not set -# CONFIG_IP_NF_ARPTABLES is not set -# CONFIG_IP_NF_MATCH_AH is not set -# CONFIG_IP_NF_MATCH_ECN is not set -# CONFIG_IP_NF_MATCH_IPP2P is not set -# CONFIG_IP_NF_MATCH_RECENT is not set -# CONFIG_IP_NF_MATCH_TIME is not set -# CONFIG_IP_NF_MATCH_TTL is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_SET is not set -# CONFIG_IP_NF_TARGET_ECN is not set -# CONFIG_IP_NF_TARGET_LOG is not set -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_NF_TARGET_REDIRECT is not set -# CONFIG_IP_NF_TARGET_TTL is not set -# CONFIG_IP_NF_TARGET_ULOG is not set -# CONFIG_ISA is not set -CONFIG_ISA_DMA_API=y -# CONFIG_ISCSI_IBFT_FIND is not set -# CONFIG_ISDN is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_IWLWIFI_LEDS is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KEXEC=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KGDB is not set -CONFIG_KMOD=y -# CONFIG_KPROBES is not set -CONFIG_KTIME_SCALAR=y -# CONFIG_LATENCYTOP is not set -CONFIG_LCD_CLASS_DEVICE=y -# CONFIG_LEDS_ALIX is not set -# CONFIG_LEDS_CLEVO_MAIL is not set -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_DEBUG=y -# CONFIG_LIBERTAS_SDIO is not set -CONFIG_LIBERTAS_USB=m -CONFIG_LOCALVERSION_AUTO=y -# CONFIG_LOCK_STAT is not set -# CONFIG_LOGO is not set -# CONFIG_M386 is not set -# CONFIG_M486 is not set -# CONFIG_M586 is not set -# CONFIG_M586MMX is not set -# CONFIG_M586TSC is not set -# CONFIG_M686 is not set -# CONFIG_MACINTOSH_DRIVERS is not set -CONFIG_MARKERS=y -# CONFIG_MATH_EMULATION is not set -# CONFIG_MCA is not set -# CONFIG_MCORE2 is not set -# CONFIG_MCRUSOE is not set -# CONFIG_MCYRIXIII is not set -# CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -# CONFIG_MEFFICEON is not set -# CONFIG_MGEODEGX1 is not set -CONFIG_MGEODE_LX=y -CONFIG_MICROCODE=y -CONFIG_MICROCODE_OLD_INTERFACE=y -# CONFIG_MINIX_FS is not set -# CONFIG_MISC_DEVICES is not set -# CONFIG_MK6 is not set -# CONFIG_MK7 is not set -# CONFIG_MK8 is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_RICOH_MMC is not set -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_TIFM_SD is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -# CONFIG_MMC_WBSD is not set -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MPENTIUM4 is not set -# CONFIG_MPENTIUMII is not set -# CONFIG_MPENTIUMIII is not set -# CONFIG_MPENTIUMM is not set -# CONFIG_MPSC is not set -# CONFIG_MSDOS_FS is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_BLOCK2MTD=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CHAR=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_ONENAND is not set -CONFIG_MTD_OOPS=m -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_PCI=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_TS5500 is not set -# CONFIG_MTRR is not set -# CONFIG_MVIAC3_2 is not set -# CONFIG_MVIAC7 is not set -# CONFIG_MWINCHIP2 is not set -# CONFIG_MWINCHIP3D is not set -# CONFIG_MWINCHIPC6 is not set -# CONFIG_NETDEVICES_MULTIQUEUE is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set -# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set -# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set -# CONFIG_NETFILTER_XT_MATCH_DSCP is not set -# CONFIG_NETFILTER_XT_MATCH_ESP is not set -# CONFIG_NETFILTER_XT_MATCH_HELPER is not set -# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set -# CONFIG_NETFILTER_XT_MATCH_MAC is not set -# CONFIG_NETFILTER_XT_MATCH_MARK is not set -# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set -# CONFIG_NETFILTER_XT_MATCH_PORTSCAN is not set -# CONFIG_NETFILTER_XT_MATCH_STRING is not set -# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set -# CONFIG_NETFILTER_XT_TARGET_CHAOS is not set -# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set -# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set -# CONFIG_NETFILTER_XT_TARGET_DELUDE is not set -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -# CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -# CONFIG_NETFILTER_XT_TARGET_TARPIT is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_KEY is not set -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_ESFQ is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_INGRESS is not set -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NF_CONNTRACK_AMANDA is not set -# CONFIG_NF_CONNTRACK_H323 is not set -# CONFIG_NF_CONNTRACK_PPTP is not set -# CONFIG_NF_CONNTRACK_RTSP is not set -# CONFIG_NF_CONNTRACK_SIP is not set -# CONFIG_NF_NAT_AMANDA is not set -# CONFIG_NF_NAT_H323 is not set -# CONFIG_NF_NAT_PPTP is not set -# CONFIG_NF_NAT_RTSP is not set -# CONFIG_NF_NAT_SIP is not set -# CONFIG_NF_NAT_SNMP_BASIC is not set -CONFIG_NL80211=y -# CONFIG_NLS is not set -CONFIG_NOHIGHMEM=y -# CONFIG_NONPROMISC_DEVMEM is not set -CONFIG_NO_HZ=y -CONFIG_NSC_GPIO=m -CONFIG_NVRAM=y -# CONFIG_OCF_OCF is not set -CONFIG_OLPC=y -CONFIG_OPROFILE=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PARAVIRT_GUEST is not set -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PC8736x_GPIO=m -CONFIG_PCI=y -# CONFIG_PCIEPORTBUS is not set -# CONFIG_PCI_DEBUG is not set -CONFIG_PCI_DIRECT=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_GOANY is not set -# CONFIG_PCI_GOBIOS is not set -# CONFIG_PCI_GODIRECT is not set -# CONFIG_PCI_GOMMCONFIG is not set -CONFIG_PCI_GOOLPC=y -CONFIG_PCI_OLPC=y -CONFIG_PCSPKR_PLATFORM=y -# CONFIG_PDA_POWER is not set -CONFIG_PHYSICAL_ALIGN=0x100000 -CONFIG_PHYSICAL_START=0x100000 -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_PM_SLEEP=y -CONFIG_PM_STD_PARTITION="" -# CONFIG_PM_TRACE_RTC is not set -# CONFIG_PM_VERBOSE is not set -CONFIG_PNP=y -CONFIG_PNPACPI=y -# CONFIG_PNP_DEBUG is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PPP is not set -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_VOLUNTARY=y -# CONFIG_PRISM54 is not set -CONFIG_PROFILING=y -# CONFIG_PROVE_LOCKING is not set -# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_RCU_TORTURE_TEST is not set -CONFIG_RELAY=y -# CONFIG_RELOCATABLE is not set -# CONFIG_RFKILL is not set -CONFIG_RTC=y -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_RWSEM_GENERIC_SPINLOCK is not set -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_DEBUG=y -CONFIG_SCHED_HRTICK=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_SCSI=y -CONFIG_SCSI_WAIT_SCAN=m -# CONFIG_SCx200 is not set -# CONFIG_SCx200_ACB is not set -# CONFIG_SDIO_UART is not set -# CONFIG_SERIAL_8250_EXTENDED is not set -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_PNP=y -CONFIG_SERIO=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_I8042=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_RAW is not set -CONFIG_SERIO_SERPORT=y -CONFIG_SLAB=y -CONFIG_SLABINFO=y -# CONFIG_SLUB is not set -# CONFIG_SMP is not set -CONFIG_SND_AC97_CODEC=m -CONFIG_SND_AC97_POWER_SAVE=y -CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 -CONFIG_SND_CS5535AUDIO=m -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCSP is not set -# CONFIG_SND_SIS7019 is not set -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SONYPI is not set -CONFIG_SPARSEMEM_STATIC=y -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_SSB_POSSIBLE=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_TELCLOCK is not set -CONFIG_THERMAL=y -CONFIG_TICK_ONESHOT=y -CONFIG_TIMER_STATS=y -# CONFIG_TOSHIBA is not set -# CONFIG_TUN is not set -# CONFIG_UDF_FS is not set -CONFIG_UID16=y -CONFIG_USB=y -# CONFIG_USB_ACM is not set -# CONFIG_USB_CATC is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_HID is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_SUPPORT=y -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_PWC is not set -# CONFIG_USB_SERIAL is not set -CONFIG_USB_STORAGE=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_UHCI_HCD=y -# CONFIG_USB_USBNET is not set -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_V4L_USB_DRIVERS=y -# CONFIG_VFAT_FS is not set -CONFIG_VGACON_SOFT_SCROLLBACK=y -CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -# CONFIG_VGASTATE is not set -CONFIG_VGA_CONSOLE=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_CAFE_CCIC=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_CPIA2 is not set -CONFIG_VIDEO_MEDIA=m -CONFIG_VIDEO_OV7670=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_VIDEO_SELECT=y -CONFIG_VIDEO_V4L1=m -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_VM86=y -# CONFIG_VMSPLIT_1G is not set -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_2G_OPT is not set -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_3G_OPT is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_W1 is not set -# CONFIG_WATCHDOG is not set -CONFIG_X86=y -CONFIG_X86_32=y -# CONFIG_X86_64 is not set -# CONFIG_X86_ACPI_CPUFREQ is not set -# CONFIG_X86_BIGSMP is not set -CONFIG_X86_BIOS_REBOOT=y -CONFIG_X86_BSWAP=y -CONFIG_X86_CMPXCHG=y -CONFIG_X86_CPU=y -# CONFIG_X86_CPUFREQ_NFORCE2 is not set -# CONFIG_X86_CPUID is not set -CONFIG_X86_DEBUGCTLMSR=y -# CONFIG_X86_ELAN is not set -# CONFIG_X86_ES7000 is not set -# CONFIG_X86_E_POWERSAVER is not set -CONFIG_X86_FIND_SMP_CONFIG=y -CONFIG_X86_GENERIC=y -# CONFIG_X86_GENERICARCH is not set -# CONFIG_X86_GX_SUSPMOD is not set -CONFIG_X86_INTEL_USERCOPY=y -CONFIG_X86_INVLPG=y -CONFIG_X86_IO_APIC=y -CONFIG_X86_L1_CACHE_SHIFT=7 -CONFIG_X86_LOCAL_APIC=y -# CONFIG_X86_LONGHAUL is not set -# CONFIG_X86_LONGRUN is not set -# CONFIG_X86_MCE is not set -CONFIG_X86_MINIMUM_CPU_FAMILY=4 -CONFIG_X86_MPPARSE=y -# CONFIG_X86_MSR is not set -# CONFIG_X86_NUMAQ is not set -# CONFIG_X86_P4_CLOCKMOD is not set -# CONFIG_X86_PAE is not set -CONFIG_X86_PC=y -CONFIG_X86_PM_TIMER=y -CONFIG_X86_POPAD_OK=y -# CONFIG_X86_POWERNOW_K6 is not set -# CONFIG_X86_POWERNOW_K7 is not set -# CONFIG_X86_POWERNOW_K8 is not set -# CONFIG_X86_PTDUMP is not set -# CONFIG_X86_RDC321X is not set -# CONFIG_X86_REBOOTFIXUPS is not set -# CONFIG_X86_SPEEDSTEP_CENTRINO is not set -# CONFIG_X86_SPEEDSTEP_ICH is not set -# CONFIG_X86_SPEEDSTEP_LIB is not set -# CONFIG_X86_SPEEDSTEP_SMI is not set -# CONFIG_X86_SUMMIT is not set -CONFIG_X86_TSC=y -CONFIG_X86_UP_APIC=y -CONFIG_X86_UP_IOAPIC=y -CONFIG_X86_USE_3DNOW=y -CONFIG_X86_USE_PPRO_CHECKSUM=y -# CONFIG_X86_VISWS is not set -# CONFIG_X86_VOYAGER is not set -# CONFIG_X86_VSMP is not set -CONFIG_X86_WP_WORKS_OK=y -CONFIG_X86_XADD=y -# CONFIG_XFS_FS is not set -# CONFIG_ZONE_DMA32 is not set diff --git a/target/linux/olpc/generic/profiles/000-Generic.mk b/target/linux/olpc/generic/profiles/000-Generic.mk deleted file mode 100644 index d7e6b7eb1e..0000000000 --- a/target/linux/olpc/generic/profiles/000-Generic.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Generic - NAME:=Generic - PACKAGES:= -endef - -define Profile/Generic/Description - Generic Profile -endef -$(eval $(call Profile,Generic)) diff --git a/target/linux/olpc/generic/target.mk b/target/linux/olpc/generic/target.mk deleted file mode 100644 index ea16d63797..0000000000 --- a/target/linux/olpc/generic/target.mk +++ /dev/null @@ -1,6 +0,0 @@ -SUBTARGET:=generic - -define Target/Description - Build firmware images for OLPC -endef - diff --git a/target/linux/olpc/image/Config.in b/target/linux/olpc/image/Config.in deleted file mode 100644 index 295f916770..0000000000 --- a/target/linux/olpc/image/Config.in +++ /dev/null @@ -1,23 +0,0 @@ -config OLPC_BOOTSCRIPT_IMAGES - bool "Build images with bootscript" - depends TARGET_olpc - depends TARGET_ROOTFS_EXT2FS || TARGET_ROOTFS_JFFS2 || TARGET_ROOTFS_SQUASHFS || TARGET_ROOTFS_ISO - default y - -config OLPC_BOOTSCRIPT_IMAGES_PAD - bool "Pad bootscript images to filesystem size (for JFFS2)" - depends OLPC_BOOTSCRIPT_IMAGES - -config OLPC_BOOTSCRIPT_KERNELPART - int "Kernel partition size (in MB)" - depends OLPC_BOOTSCRIPT_IMAGES - default 4 - -config OLPC_BOOTSCRIPT_ROOTPART - string - prompt "Root partition on target device" if OLPC_BOOTSCRIPT_IMAGES - default "/dev/hda2" - help - The root partition on the final device. If you don't know, - you probably want the default (/dev/hda2). - diff --git a/target/linux/olpc/image/Makefile b/target/linux/olpc/image/Makefile deleted file mode 100644 index 4945022ba7..0000000000 --- a/target/linux/olpc/image/Makefile +++ /dev/null @@ -1,64 +0,0 @@ -# -# Copyright (C) 2007-2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -export PATH=$(TARGET_PATH):/sbin -ROOTPART=$(strip $(subst ",, $(CONFIG_OLPC_BOOTSCRIPT_ROOTPART))) -#"))")) # fix vim's broken syntax highlighting - -ROOTDELAY=5 - -ifeq ($(CONFIG_OLPC_BOOTSCRIPT_IMAGES),y) - define Image/cmdline/squashfs - block2mtd.block2mtd=$(ROOTPART),65536,rootfs root=/dev/mtdblock0 rootfstype=squashfs init=/etc/preinit rootdelay=$(ROOTDELAY) - endef - - define Image/cmdline/jffs2-64k - block2mtd.block2mtd=$(ROOTPART),65536,rootfs root=/dev/mtdblock0 rootfstype=jffs2 init=/etc/preinit rootdelay=$(ROOTDELAY) - endef - - define Image/cmdline/jffs2-128k - block2mtd.block2mtd=$(ROOTPART),131072,rootfs root=/dev/mtdblock0 rootfstype=jffs2 init=/etc/preinit rootdelay=$(ROOTDELAY) - endef - - define Image/cmdline/ext2 - root=$(ROOTPART) rootfstype=ext2 init=/etc/preinit - endef - - define Image/Build/bootscript - # left here because the image builder doesnt need these - $(INSTALL_DIR) $(KDIR)/root.bootscript/boot - $(CP) $(KDIR)/bzImage $(KDIR)/root.bootscript/boot/vmlinuz - sed -e 's#@CMDLINE@#$(strip $(call Image/cmdline/$(1))) $(BOOTOPTS)#g' \ - ./olpc.fth > $(KDIR)/root.bootscript/boot/olpc.fth - PADDING="$(CONFIG_OLPC_BOOTSCRIPT_IMAGES_PAD)" PATH="$(TARGET_PATH)" ./gen_image.sh $(BIN_DIR)/openwrt-$(BOARD)-$(1).image $(CONFIG_OLPC_BOOTSCRIPT_KERNELPART) $(KDIR)/root.bootscript $(CONFIG_TARGET_ROOTFS_FSPART) $(KDIR)/root.$(1) - endef -endif - -define Image/Prepare - cp $(LINUX_DIR)/arch/x86/boot/bzImage $(KDIR)/bzImage - $(call Image/Prepare/bootscript) -endef - -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) -endef - -define Image/BuildKernel - $(CP) $(KDIR)/bzImage $(BIN_DIR)/openwrt-$(BOARD)-vmlinuz -endef - -define Image/Build - $(call Image/Build/$(1)) - $(call Image/Build/bootscript,$(1)) - $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/openwrt-$(BOARD)-$(1).fs - $(CP) $(KDIR)/bzImage $(BIN_DIR)/openwrt-$(BOARD)-vmlinuz -endef - -$(eval $(call BuildImage)) - diff --git a/target/linux/olpc/image/gen_image.sh b/target/linux/olpc/image/gen_image.sh deleted file mode 100755 index 4fd6e377e5..0000000000 --- a/target/linux/olpc/image/gen_image.sh +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env bash -# Copyright (C) 2006 - 2007 OpenWrt.org -set -x -[ $# == 5 ] || { - echo "SYNTAX: $0 " - exit 1 -} - -OUTPUT="$1" -KERNELSIZE="$2" -KERNELDIR="$3" -ROOTFSSIZE="$4" -ROOTFSIMAGE="$5" - -rm -f "$OUTPUT" - -head=16 -sect=63 -cyl=$(( ($KERNELSIZE + $ROOTFSSIZE) * 1024 * 1024 / ($head * $sect * 512))) - -# create partition table -set `ptgen -o "$OUTPUT" -h $head -s $sect -p ${KERNELSIZE}m -p ${ROOTFSSIZE}m` - -KERNELOFFSET="$(($1 / 512))" -KERNELSIZE="$(($2 / 512))" -ROOTFSOFFSET="$(($3 / 512))" -ROOTFSSIZE="$(($4 / 512))" - -BLOCKS="$((($KERNELSIZE / 2) - 1))" - -genext2fs -d "$KERNELDIR" -b "$BLOCKS" "$OUTPUT.kernel" -dd if="$OUTPUT.kernel" of="$OUTPUT" bs=512 seek="$KERNELOFFSET" conv=notrunc -[ -n "$PADDING" ] && dd if=/dev/zero of="$OUTPUT" bs=512 seek="$ROOTFSOFFSET" conv=notrunc count="$ROOTFSSIZE" -dd if="$ROOTFSIMAGE" of="$OUTPUT" bs=512 seek="$ROOTFSOFFSET" conv=notrunc -#rm -f "$OUTPUT.kernel" diff --git a/target/linux/olpc/image/olpc.fth b/target/linux/olpc/image/olpc.fth deleted file mode 100644 index f250ab0c72..0000000000 --- a/target/linux/olpc/image/olpc.fth +++ /dev/null @@ -1,4 +0,0 @@ -\ Boot script -" u:\boot\vmlinuz" to boot-device -" @CMDLINE@ noinitrd console=tty0" to boot-file -boot diff --git a/target/linux/olpc/patches-2.6.24/100-olpc.patch b/target/linux/olpc/patches-2.6.24/100-olpc.patch deleted file mode 100644 index caea6012ad..0000000000 --- a/target/linux/olpc/patches-2.6.24/100-olpc.patch +++ /dev/null @@ -1,10300 +0,0 @@ -Index: linux-2.6.24.7/arch/x86/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/arch/x86/Kconfig -+++ linux-2.6.24.7/arch/x86/Kconfig -@@ -1415,6 +1415,9 @@ config PCI_GODIRECT - config PCI_GOANY - bool "Any" - -+config PCI_GOOLPC -+ bool "OLPC" -+ - endchoice - - config PCI_BIOS -@@ -1425,7 +1428,7 @@ config PCI_BIOS - # x86-64 doesn't support PCI BIOS access from long mode so always go direct. - config PCI_DIRECT - bool -- depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY) || X86_VISWS) -+ depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC) || X86_VISWS) - default y - - config PCI_MMCONFIG -@@ -1442,6 +1445,11 @@ config PCI_MMCONFIG - bool "Support mmconfig PCI config space access" - depends on X86_64 && PCI && ACPI - -+config PCI_OLPC -+ bool -+ depends on PCI && PCI_GOOLPC -+ default y -+ - config DMAR - bool "Support for DMA Remapping Devices (EXPERIMENTAL)" - depends on X86_64 && PCI_MSI && ACPI && EXPERIMENTAL -@@ -1561,6 +1569,21 @@ config K8_NB - def_bool y - depends on AGP_AMD64 || (X86_64 && (GART_IOMMU || (PCI && NUMA))) - -+config OLPC -+ bool "OLPC Support" -+ default n -+ help -+ Add OLPC Support -+ -+config OLPC_PM -+ bool "OLPC power management support" -+ default n -+ depends on OLPC -+ -+config OPEN_FIRMWARE -+ bool "Support for Open Firmware" -+ default y if OLPC -+ - source "drivers/pcmcia/Kconfig" - - source "drivers/pci/hotplug/Kconfig" -Index: linux-2.6.24.7/arch/x86/kernel/Makefile_32 -=================================================================== ---- linux-2.6.24.7.orig/arch/x86/kernel/Makefile_32 -+++ linux-2.6.24.7/arch/x86/kernel/Makefile_32 -@@ -50,6 +50,13 @@ obj-y += pcspeaker.o - - obj-$(CONFIG_SCx200) += scx200_32.o - -+obj-$(CONFIG_OLPC) += olpc.o -+obj-$(CONFIG_OLPC_PM) += olpc-pm.o olpc-wakeup.o -+obj-$(CONFIG_OPEN_FIRMWARE) += ofw.o -+obj-$(PROM_FS) += promfs.o -+ -+ -+ - # vsyscall_32.o contains the vsyscall DSO images as __initdata. - # We must build both images before we can assemble it. - # Note: kbuild does not track this dependency due to usage of .incbin -Index: linux-2.6.24.7/arch/x86/kernel/ofw.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/arch/x86/kernel/ofw.c -@@ -0,0 +1,100 @@ -+/* -+ * ofw.c - Open Firmware client interface for 32-bit systems. -+ * This code is intended to be portable to any 32-bit Open Firmware -+ * implementation with a standard client interface that can be -+ * called when Linux is running. -+ * -+ * Copyright (C) 2007 Mitch Bradley -+ * Copyright (C) 2007 Andres Salomon -+ */ -+ -+#include -+#include -+#include -+#include -+ -+ -+int (*call_firmware)(int *); -+ -+static DEFINE_SPINLOCK(prom_lock); -+ -+#define MAXARGS 20 -+ -+/* -+ * The return value from ofw() in all cases is 0 if the attempt to call the -+ * function succeeded, <0 otherwise. That return value is from the -+ * gateway function only. Any results from the called function are returned -+ * via output argument pointers. -+ * -+ * Here are call templates for all the standard OFW client services: -+ * -+ * ofw("test", 1, 1, namestr, &missing); -+ * ofw("peer", 1, 1, phandle, &sibling_phandle); -+ * ofw("child", 1, 1, phandle, &child_phandle); -+ * ofw("parent", 1, 1, phandle, &parent_phandle); -+ * ofw("instance_to_package", 1, 1, ihandle, &phandle); -+ * ofw("getproplen", 2, 1, phandle, namestr, &proplen); -+ * ofw("getprop", 4, 1, phandle, namestr, bufaddr, buflen, &size); -+ * ofw("nextprop", 3, 1, phandle, previousstr, bufaddr, &flag); -+ * ofw("setprop", 4, 1, phandle, namestr, bufaddr, len, &size); -+ * ofw("canon", 3, 1, devspecstr, bufaddr, buflen, &length); -+ * ofw("finddevice", 1, 1, devspecstr, &phandle); -+ * ofw("instance-to-path", 3, 1, ihandle, bufaddr, buflen, &length); -+ * ofw("package-to-path", 3, 1, phandle, bufaddr, buflen, &length); -+ * ofw("call_method", numin, numout, in0, in1, ..., &out0, &out1, ...); -+ * ofw("open", 1, 1, devspecstr, &ihandle); -+ * ofw("close", 1, 0, ihandle); -+ * ofw("read", 3, 1, ihandle, addr, len, &actual); -+ * ofw("write", 3, 1, ihandle, addr, len, &actual); -+ * ofw("seek", 3, 1, ihandle, pos_hi, pos_lo, &status); -+ * ofw("claim", 3, 1, virtaddr, size, align, &baseaddr); -+ * ofw("release", 2, 0, virtaddr, size); -+ * ofw("boot", 1, 0, bootspecstr); -+ * ofw("enter", 0, 0); -+ * ofw("exit", 0, 0); -+ * ofw("chain", 5, 0, virtaddr, size, entryaddr, argsaddr, len); -+ * ofw("interpret", numin+1, numout+1, cmdstr, in0, ..., &catchres, &out0, ...); -+ * ofw("set-callback", 1, 1, newfuncaddr, &oldfuncaddr); -+ * ofw("set-symbol-lookup", 2, 0, symtovaladdr, valtosymaddr); -+ * ofw("milliseconds", 0, 1, &ms); -+ */ -+ -+int ofw(char *name, int numargs, int numres, ...) -+{ -+ va_list ap; -+ int argarray[MAXARGS+3]; -+ int argnum = 3; -+ int retval; -+ int *intp; -+ unsigned long flags; -+ -+ if (!call_firmware) -+ return -1; -+ if ((numargs + numres) > MAXARGS) -+ return -1; /* spit out an error? */ -+ -+ argarray[0] = (int) name; -+ argarray[1] = numargs; -+ argarray[2] = numres; -+ -+ va_start(ap, numres); -+ while (numargs) { -+ argarray[argnum++] = va_arg(ap, int); -+ numargs--; -+ } -+ -+ spin_lock_irqsave(&prom_lock, flags); -+ retval = call_firmware(argarray); -+ spin_unlock_irqrestore(&prom_lock, flags); -+ -+ if (retval == 0) { -+ while (numres) { -+ intp = va_arg(ap, int *); -+ *intp = argarray[argnum++]; -+ numres--; -+ } -+ } -+ va_end(ap); -+ return retval; -+} -+EXPORT_SYMBOL(ofw); -Index: linux-2.6.24.7/arch/x86/kernel/olpc.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/arch/x86/kernel/olpc.c -@@ -0,0 +1,287 @@ -+/* Support for the OLPC DCON and OLPC EC access -+ * Copyright (C) 2006, Advanced Micro Devices, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+/* This is our new multi-purpose structure used to contain the -+ * information about the platform that we detect -+ */ -+ -+struct olpc_platform_t olpc_platform_info; -+EXPORT_SYMBOL_GPL(olpc_platform_info); -+ -+/********************************************************************* -+ * EC locking and access -+ *********************************************************************/ -+ -+static DEFINE_SPINLOCK(ec_lock); -+ -+/* what the timeout *should* be (in ms) */ -+#define EC_BASE_TIMEOUT 20 -+ -+/* the timeout that bugs in the EC might force us to actually use */ -+static int ec_timeout = EC_BASE_TIMEOUT; -+ -+static int __init olpc_ec_timeout_set(char *str) -+{ -+ if (get_option(&str, &ec_timeout) != 1) { -+ ec_timeout = EC_BASE_TIMEOUT; -+ printk(KERN_ERR "olpc-ec: invalid argument to " -+ "'olpc_ec_timeout=', ignoring!\n"); -+ } -+ printk(KERN_DEBUG "olpc-ec: using %d ms delay for EC commands.\n", -+ ec_timeout); -+ return 1; -+} -+__setup("olpc_ec_timeout=", olpc_ec_timeout_set); -+ -+/* -+ * These *bf_status functions return whether the buffers are full or not. -+ */ -+ -+static inline unsigned int ibf_status(unsigned int port) -+{ -+ return !!(inb(port) & 0x02); -+} -+ -+static inline unsigned int obf_status(unsigned int port) -+{ -+ return inb(port) & 0x01; -+} -+ -+#define wait_on_ibf(p, d) __wait_on_ibf(__LINE__, (p), (d)) -+static int __wait_on_ibf(unsigned int line, unsigned int port, int desired) -+{ -+ unsigned int timeo; -+ int state = ibf_status(port); -+ -+ for (timeo = ec_timeout; state != desired && timeo; timeo--) { -+ mdelay(1); -+ state = ibf_status(port); -+ } -+ -+ if ((state == desired) && (ec_timeout > EC_BASE_TIMEOUT) && -+ timeo < (ec_timeout - EC_BASE_TIMEOUT)) { -+ printk(KERN_WARNING "olpc-ec: %d: waited %u ms for IBF!\n", -+ line, ec_timeout - timeo); -+ } -+ -+ return !(state == desired); -+} -+ -+#define wait_on_obf(p, d) __wait_on_obf(__LINE__, (p), (d)) -+static int __wait_on_obf(unsigned int line, unsigned int port, int desired) -+{ -+ unsigned int timeo; -+ int state = obf_status(port); -+ -+ for (timeo = ec_timeout; state != desired && timeo; timeo--) { -+ mdelay(1); -+ state = obf_status(port); -+ } -+ -+ if ((state == desired) && (ec_timeout > EC_BASE_TIMEOUT) && -+ timeo < (ec_timeout - EC_BASE_TIMEOUT)) { -+ printk(KERN_WARNING "olpc-ec: %d: waited %u ms for OBF!\n", -+ line, ec_timeout - timeo); -+ } -+ -+ return !(state == desired); -+} -+ -+int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen, -+ unsigned char *outbuf, size_t outlen) -+{ -+ unsigned long flags; -+ int ret = -EIO; -+ int i; -+ -+ spin_lock_irqsave(&ec_lock, flags); -+ -+ /* Clear OBF */ -+ for (i = 0; i < 10 && (obf_status(0x6c) == 1); i++) -+ inb(0x68); -+ if (i == 10) { -+ printk(KERN_ERR "olpc-ec: timeout while attempting to " -+ "clear OBF flag!\n"); -+ goto err; -+ } -+ -+ if (wait_on_ibf(0x6c, 0)) { -+ printk(KERN_ERR "olpc-ec: timeout waiting for EC to " -+ "quiesce!\n"); -+ goto err; -+ } -+ -+restart: -+ /* -+ * Note that if we time out during any IBF checks, that's a failure; -+ * we have to return. There's no way for the kernel to clear that. -+ * -+ * If we time out during an OBF check, we can restart the command; -+ * reissuing it will clear the OBF flag, and we should be alright. -+ * The OBF flag will sometimes misbehave due to what we believe -+ * is a hardware quirk.. -+ */ -+ printk(KERN_DEBUG "olpc-ec: running cmd 0x%x\n", cmd); -+ outb(cmd, 0x6c); -+ -+ if (wait_on_ibf(0x6c, 0)) { -+ printk(KERN_ERR "olpc-ec: timeout waiting for EC to read " -+ "command!\n"); -+ goto err; -+ } -+ -+ if (inbuf && inlen) { -+ /* write data to EC */ -+ for (i = 0; i < inlen; i++) { -+ if (wait_on_ibf(0x6c, 0)) { -+ printk(KERN_ERR "olpc-ec: timeout waiting for" -+ " EC accept data!\n"); -+ goto err; -+ } -+ printk(KERN_DEBUG "olpc-ec: sending cmd arg 0x%x\n", -+ inbuf[i]); -+ outb(inbuf[i], 0x68); -+ } -+ } -+ if (outbuf && outlen) { -+ /* read data from EC */ -+ for (i = 0; i < outlen; i++) { -+ if (wait_on_obf(0x6c, 1)) { -+ printk(KERN_ERR "olpc-ec: timeout waiting for" -+ " EC to provide data!\n"); -+ goto restart; -+ } -+ outbuf[i] = inb(0x68); -+ printk(KERN_DEBUG "olpc-ec: received 0x%x\n", -+ outbuf[i]); -+ } -+ } -+ -+ ret = 0; -+err: -+ spin_unlock_irqrestore(&ec_lock, flags); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(olpc_ec_cmd); -+ -+/********************************************************************* -+ * DCON stuff -+ *********************************************************************/ -+ -+static void __init -+ec_detect(void) -+{ -+ olpc_ec_cmd(0x08, NULL, 0, (unsigned char *) &olpc_platform_info.ecver, 1); -+} -+ -+/* Check to see if this version of the OLPC board has VSA built -+ * in, and set a flag -+ */ -+ -+static void __init vsa_detect(void) -+{ -+ u16 rev; -+ -+ outw(0xFC53, 0xAC1C); -+ outw(0x0003, 0xAC1C); -+ -+ rev = inw(0xAC1E); -+ -+ if (rev == 0x4132) -+ olpc_platform_info.flags |= OLPC_F_VSA; -+} -+ -+static void __init platform_detect(void) -+{ -+ size_t propsize; -+ u32 rev; -+ -+ if (ofw("getprop", 4, 1, NULL, "board-revision-int", &rev, 4, -+ &propsize) || propsize != 4) { -+ printk(KERN_ERR "ofw: getprop call failed!\n"); -+ rev = 0; -+ } -+ olpc_platform_info.boardrev = be32_to_cpu(rev); -+} -+ -+static int olpc_dcon_present = -1; -+module_param(olpc_dcon_present, int, 0444); -+ -+/* REV_A CMOS map: -+ * bit 440; DCON present bit -+ */ -+ -+#define OLPC_CMOS_DCON_OFFSET (440 / 8) -+#define OLPC_CMOS_DCON_MASK 0x01 -+ -+static int __init olpc_init(void) -+{ -+ unsigned char *romsig; -+ -+ spin_lock_init(&ec_lock); -+ -+ romsig = ioremap(0xffffffc0, 16); -+ -+ if (!romsig) -+ return 0; -+ -+ if (strncmp(romsig, "CL1 Q", 7)) -+ goto unmap; -+ if (strncmp(romsig+6, romsig+13, 3)) { -+ printk(KERN_INFO "OLPC BIOS signature looks invalid. Assuming not OLPC\n"); -+ goto unmap; -+ } -+ printk(KERN_INFO "OLPC board with OpenFirmware: %.16s\n", romsig); -+ -+ olpc_platform_info.flags |= OLPC_F_PRESENT; -+ -+ /* Get the platform revision */ -+ platform_detect(); -+ -+ /* If olpc_dcon_present isn't set by the command line, then -+ * "detect" it -+ */ -+ -+ if (olpc_dcon_present == -1) { -+ /* B1 and greater always has a DCON */ -+ if (olpc_board_at_least(olpc_board(0xb1))) -+ olpc_dcon_present = 1; -+ } -+ -+ if (olpc_dcon_present) -+ olpc_platform_info.flags |= OLPC_F_DCON; -+ -+ /* Get the EC revision */ -+ ec_detect(); -+ -+ /* Check to see if the VSA exists */ -+ vsa_detect(); -+ -+ printk(KERN_INFO "OLPC board revision: %s%X (EC=%x)\n", -+ ((olpc_platform_info.boardrev & 0xf) < 8) ? "pre" : "", -+ olpc_platform_info.boardrev >> 4, -+ olpc_platform_info.ecver); -+ -+ unmap: -+ iounmap(romsig); -+ -+ return 0; -+} -+ -+postcore_initcall(olpc_init); -Index: linux-2.6.24.7/arch/x86/kernel/olpc-pm.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/arch/x86/kernel/olpc-pm.c -@@ -0,0 +1,946 @@ -+/* olpc-pm.c -+ * © 2006 Red Hat, Inc. -+ * Portions also copyright 2006 Advanced Micro Devices, Inc. -+ * GPLv2 -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* A few words about accessing the ACPI and PM registers. Long story short, -+ byte and word accesses of the ACPI and PM registers is broken. The only -+ way to do it really correctly is to use dword accesses, which we do -+ throughout this code. For more details, please consult Eratta 17 and 18 -+ here: -+ -+ http://www.amd.com/files/connectivitysolutions/geode/geode_gx/34472D_CS5536_B1_specupdate.pdf -+*/ -+ -+#define PM_IRQ 3 -+ -+#define CS5536_PM_PWRBTN (1 << 8) -+#define CS5536_PM_RTC (1 << 10) -+#define CS5536_PM_WAK (1 << 15) -+ -+#define GPIO_WAKEUP_EC (1 << 31) -+#define GPIO_WAKEUP_LID (1 << 30) -+ -+#define PM_MODE_NORMAL 0 -+#define PM_MODE_TEST 1 -+#define PM_MODE_MAX 2 -+ -+/* These, and the battery EC commands, should be in an olpc.h. */ -+#define EC_WRITE_SCI_MASK 0x1b -+#define EC_READ_SCI_MASK 0x1c -+ -+extern void do_olpc_suspend_lowlevel(void); -+ -+static struct { -+ unsigned long address; -+ unsigned short segment; -+} ofw_bios_entry = { 0, __KERNEL_CS }; -+ -+static int olpc_pm_mode = PM_MODE_NORMAL; -+static unsigned long acpi_base; -+static unsigned long pms_base; -+static int sci_irq; -+static int olpc_lid_flag; -+ -+static struct input_dev *pm_inputdev; -+static struct input_dev *lid_inputdev; -+static struct input_dev *ebook_inputdev; -+static struct platform_suspend_ops olpc_pm_ops; -+ -+static int gpio_wake_events = 0; -+static int ebook_state = -1; -+static u16 olpc_wakeup_mask = 0; -+ -+static unsigned int test_timeout = 0; -+static char *wackup_source = "none"; -+ -+struct platform_device olpc_powerbutton_dev = { -+ .name = "powerbutton", -+ .id = -1, -+}; -+ -+struct platform_device olpc_lid_dev = { -+ .name = "lid", -+ .id = -1, -+}; -+ -+static void __init init_ebook_state(void) -+{ -+ if (olpc_ec_cmd(0x2a, NULL, 0, (unsigned char *) &ebook_state, 1)) { -+ printk(KERN_WARNING "olpc-pm: failed to get EBOOK state!\n"); -+ ebook_state = 0; -+ } -+ ebook_state &= 1; -+ -+ /* the input layer needs to know what value to default to as well */ -+ input_report_switch(ebook_inputdev, SW_TABLET_MODE, ebook_state); -+ input_sync(ebook_inputdev); -+} -+ -+static void (*battery_callback)(unsigned long); -+static DEFINE_SPINLOCK(battery_callback_lock); -+ -+/* propagate_events is non-NULL if run from workqueue, -+ NULL when called at init time to flush SCI queue */ -+static void process_sci_queue(struct work_struct *propagate_events) -+{ -+ unsigned char data = 0; -+ unsigned char battery_events = 0; -+ int ret; -+ -+ do { -+ ret = olpc_ec_cmd(0x84, NULL, 0, &data, 1); -+ if (!ret) { -+ printk(KERN_DEBUG "olpc-pm: SCI 0x%x received\n", -+ data); -+ -+ if (wackup_source && !strcmp(wackup_source, "sci")) { -+ /* -+ * XXX: in order for this to not be racy, we -+ * need assurance that we will never get -+ * preempted by olpc_do_sleep here! -+ */ -+ switch (data) { -+ case EC_SCI_SRC_EMPTY: -+ wackup_source = "empty sci"; -+ break; -+ case EC_SCI_SRC_GAME: -+ wackup_source = "key press"; -+ break; -+ case EC_SCI_SRC_BATTERY: -+ wackup_source = "battery"; -+ break; -+ case EC_SCI_SRC_BATSOC: -+ wackup_source = "battery state change"; -+ break; -+ case EC_SCI_SRC_BATERR: -+ wackup_source = "battery error"; -+ break; -+ case EC_SCI_SRC_EBOOK: -+ wackup_source = "ebook"; -+ break; -+ case EC_SCI_SRC_WLAN: -+ wackup_source = "wlan packet"; -+ break; -+ case EC_SCI_SRC_ACPWR: -+ wackup_source = "ac power"; -+ break; -+ default: -+ wackup_source = "unknown"; -+ } -+ } -+ -+ if (data & (EC_SCI_SRC_BATERR | EC_SCI_SRC_BATSOC | -+ EC_SCI_SRC_BATTERY | EC_SCI_SRC_ACPWR)) -+ battery_events |= data; -+ else if (data == EC_SCI_SRC_EBOOK) { -+ ebook_state = !ebook_state; -+ if (propagate_events) { -+ input_report_switch(ebook_inputdev, -+ SW_TABLET_MODE, ebook_state); -+ input_sync(ebook_inputdev); -+ } -+ } -+ } -+ } while (data && !ret); -+ -+ if (battery_events && battery_callback && propagate_events) { -+ void (*cbk)(unsigned long); -+ -+ /* Older EC versions didn't distinguish between AC and battery -+ events */ -+ if (olpc_platform_info.ecver < 0x51) -+ battery_events = EC_SCI_SRC_BATTERY | EC_SCI_SRC_ACPWR; -+ -+ spin_lock(&battery_callback_lock); -+ cbk = battery_callback; -+ spin_unlock(&battery_callback_lock); -+ -+ cbk(battery_events); -+ } -+ -+ if (ret) -+ printk(KERN_WARNING "Failed to clear SCI queue!\n"); -+} -+ -+static DECLARE_WORK(sci_work, process_sci_queue); -+ -+void olpc_register_battery_callback(void (*f)(unsigned long)) -+{ -+ spin_lock(&battery_callback_lock); -+ battery_callback = f; -+ spin_unlock(&battery_callback_lock); -+} -+EXPORT_SYMBOL_GPL(olpc_register_battery_callback); -+ -+void olpc_deregister_battery_callback(void) -+{ -+ spin_lock(&battery_callback_lock); -+ battery_callback = NULL; -+ spin_unlock(&battery_callback_lock); -+ cancel_work_sync(&sci_work); -+} -+EXPORT_SYMBOL_GPL(olpc_deregister_battery_callback); -+ -+ -+static int olpc_pm_interrupt(int irq, void *id) -+{ -+ uint32_t sts, gpe = 0; -+ -+ sts = inl(acpi_base + PM1_STS); -+ outl(sts | 0xFFFF, acpi_base + PM1_STS); -+ -+ if (olpc_board_at_least(olpc_board(0xb2))) { -+ gpe = inl(acpi_base + PM_GPE0_STS); -+ outl(0xFFFFFFFF, acpi_base + PM_GPE0_STS); -+ } -+ -+ if (sts & CS5536_PM_PWRBTN) { -+ if (!wackup_source) -+ wackup_source = "power button"; -+ printk(KERN_DEBUG "olpm-pm: PM_PWRBTN %sevent received\n", -+ sts & CS5536_PM_WAK ? "wakeup " : ""); -+ if (!(sts & CS5536_PM_WAK)) { -+ input_report_key(pm_inputdev, KEY_POWER, 1); -+ input_sync(pm_inputdev); -+ /* Do we need to delay this? */ -+ input_report_key(pm_inputdev, KEY_POWER, 0); -+ input_sync(pm_inputdev); -+ } -+ } -+ -+ if (gpe & GPIO_WAKEUP_EC) { -+ geode_gpio_clear(OLPC_GPIO_ECSCI, GPIO_NEGATIVE_EDGE_STS); -+ if (!wackup_source) -+ wackup_source = "sci"; -+ schedule_work(&sci_work); -+ } -+ -+ if (gpe & GPIO_WAKEUP_LID) { -+ /* Disable events */ -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ -+ /* Clear the edge */ -+ -+ if (olpc_lid_flag) -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN); -+ else -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN); -+ -+ /* Clear the status too */ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_STS); -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_STS); -+ -+ /* The line is high when the LID is open, but SW_LID -+ * should be high when the LID is closed, so we pass the old -+ * value of olpc_lid_flag -+ */ -+ -+ input_report_switch(lid_inputdev, SW_LID, olpc_lid_flag); -+ input_sync(lid_inputdev); -+ if (!wackup_source) -+ wackup_source = "lid"; -+ -+ /* Swap the status */ -+ olpc_lid_flag = !olpc_lid_flag; -+ -+ if (olpc_lid_flag) -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN); -+ else -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN); -+ -+ /* re-enable the event */ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+int olpc_ec_mask_set(u8 bits) -+{ -+ int ret; -+ u8 byte; -+ -+ ret = olpc_ec_cmd(EC_READ_SCI_MASK, NULL, 0, &byte, 1); -+ if (ret) { -+ printk(KERN_ERR "olpc-pm: error getting SCI mask: %d\n", ret); -+ return ret; -+ } -+ /* the high bit is unused, if it is ever unset, that is a good sign -+ sign of EC communication corruption! */ -+ WARN_ON(!(byte & 0x80)); -+ -+ byte |= bits; -+ ret = olpc_ec_cmd(EC_WRITE_SCI_MASK, &byte, 1, NULL, 0); -+ if (ret) -+ printk(KERN_ERR "olpc-pm: error setting SCI mask: %d\n", ret); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(olpc_ec_mask_set); -+ -+int olpc_ec_mask_unset(u8 bits) -+{ -+ int ret; -+ u8 byte; -+ -+ ret = olpc_ec_cmd(EC_READ_SCI_MASK, NULL, 0, &byte, 1); -+ if (ret) { -+ printk(KERN_ERR "olpc-pm: error getting SCI mask: %d\n", ret); -+ return ret; -+ } -+ /* the high bit is unused, if it is ever unset, that is a good sign -+ sign of EC communication corruption! */ -+ WARN_ON(!(byte & 0x80)); -+ -+ byte &= ~bits; -+ ret = olpc_ec_cmd(EC_WRITE_SCI_MASK, &byte, 1, NULL, 0); -+ if (ret) -+ printk(KERN_ERR "olpc-pm: error setting SCI mask: %d\n", ret); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(olpc_ec_mask_unset); -+ -+/* -+ * For now, only support STR. We also don't support suspending on -+ * B1s, due to difficulties with the cafe FPGA. -+ */ -+static int olpc_pm_state_valid(suspend_state_t pm_state) -+{ -+ if (pm_state == PM_SUSPEND_MEM && olpc_board_at_least(olpc_board(0xb2))) -+ return 1; -+ -+ return 0; -+} -+ -+/* This is a catchall function for operations that just don't belong -+ * anywhere else. Later we will evaluate if these belong in the -+ * individual device drivers or the firmware. -+ * If you add something to this function, please explain yourself with -+ * a comment. -+ */ -+ -+extern void gxfb_flatpanel_control(int state); -+ -+static u32 gpio_wakeup[2]; -+static u64 irq_sources[4]; -+static u64 mfgpt_irq_msr, mfgpt_nr_msr; -+ -+void olpc_fixup_wakeup(void) -+{ -+ u32 base = geode_gpio_base(); -+ int i; -+ -+ /* Enable the flatpanel sequencing as early as possible, because -+ it takes ~64ms to resume. This probably belongs in the firmware */ -+ -+ //gxfb_flatpanel_control(1); -+ -+ /* Tell the EC to stop inhibiting SCIs */ -+ olpc_ec_cmd(0x34, NULL, 0, NULL, 0); -+ -+ /* Restore the interrupt sources */ -+ wrmsrl(MSR_PIC_YSEL_LOW, irq_sources[0]); -+ wrmsrl(MSR_PIC_ZSEL_LOW, irq_sources[1]); -+ wrmsrl(MSR_PIC_YSEL_HIGH, irq_sources[2]); -+ wrmsrl(MSR_PIC_ZSEL_HIGH, irq_sources[3]); -+ -+ /* Restore the X and Y sources for GPIO */ -+ outl(gpio_wakeup[0], base + GPIO_MAP_X); -+ outl(gpio_wakeup[1], base + GPIO_MAP_Y); -+ -+ /* Resture the MFGPT MSRs */ -+ wrmsrl(MFGPT_IRQ_MSR, mfgpt_irq_msr); -+ wrmsrl(MFGPT_NR_MSR, mfgpt_nr_msr); -+ -+ for (i=0;i<2;i++) { -+ /* tell the wireless module to restart USB communication */ -+ olpc_ec_cmd(0x24, NULL, 0, NULL, 0); -+ } -+ -+ /* Turn all events on */ -+ olpc_ec_mask_set(EC_SCI_SRC_ALL); -+} -+ -+void olpc_fixup_sleep(void) -+{ -+ u32 base = geode_gpio_base(); -+ int i; -+ -+ /* Save the X and Y sources for GPIO */ -+ gpio_wakeup[0] = inl(base + GPIO_MAP_X); -+ gpio_wakeup[1] = inl(base + GPIO_MAP_Y); -+ -+ /* Save the Y and Z unrestricted sources */ -+ -+ rdmsrl(MSR_PIC_YSEL_LOW, irq_sources[0]); -+ rdmsrl(MSR_PIC_ZSEL_LOW, irq_sources[1]); -+ rdmsrl(MSR_PIC_YSEL_HIGH, irq_sources[2]); -+ rdmsrl(MSR_PIC_ZSEL_HIGH, irq_sources[3]); -+ -+ /* Turn off the MFGPT timers on the way down */ -+ -+ for(i = 0; i < 8; i++) { -+ u32 val = geode_mfgpt_read(i, MFGPT_REG_SETUP); -+ -+ if (val & MFGPT_SETUP_SETUP) { -+ val &= ~MFGPT_SETUP_CNTEN; -+ geode_mfgpt_write(i, MFGPT_REG_SETUP, val); -+ } -+ } -+ -+ /* Save the MFGPT MSRs */ -+ rdmsrl(MFGPT_IRQ_MSR, mfgpt_irq_msr); -+ rdmsrl(MFGPT_NR_MSR, mfgpt_nr_msr); -+ -+ if (device_may_wakeup(&olpc_powerbutton_dev.dev)) -+ olpc_wakeup_mask |= CS5536_PM_PWRBTN; -+ else -+ olpc_wakeup_mask &= ~(CS5536_PM_PWRBTN); -+ -+ if (device_may_wakeup(&olpc_lid_dev.dev)) { -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ gpio_wake_events |= GPIO_WAKEUP_LID; -+ } else { -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ gpio_wake_events &= ~(GPIO_WAKEUP_LID); -+ } -+ -+ /* We don't want to wake up on superfluous events */ -+ olpc_ec_mask_unset(EC_SCI_SRC_BATSOC | EC_SCI_SRC_ACPWR); -+ -+ /* -+ * Cmd 0x32 tells the EC that we're going into suspend; this was -+ * added to work around hardware races related to SCI events. This -+ * should cause the EC to inhibit further SCIs while MAIN_ON is -+ * transitioning low. -+ * -+ * There's also some sort of EC race whereby the EC gets its -+ * IBF/OBF flags confused and all future communication (after -+ * resuming) fails if we suspend too soon after updating -+ * the EC SCI mask. Having this command after updating the -+ * SCI mask allows the EC enough time to finish doing what it's -+ * doing. -+ */ -+ olpc_ec_cmd(0x32, NULL, 0, NULL, 0); -+} -+ -+static int olpc_pm_enter(suspend_state_t pm_state) -+{ -+ /* Only STR is supported */ -+ if (pm_state != PM_SUSPEND_MEM) -+ return -EINVAL; -+ -+ olpc_fixup_sleep(); -+ -+ /* Set the GPIO wakeup bits */ -+ outl(gpio_wake_events, acpi_base + PM_GPE0_EN); -+ outl(0xFFFFFFFF, acpi_base + PM_GPE0_STS); -+ -+ /* Save CPU state */ -+ do_olpc_suspend_lowlevel(); -+ -+ olpc_fixup_wakeup(); -+ -+ /* Restore the SCI wakeup events */ -+ outl(gpio_wake_events, acpi_base + PM_GPE0_EN); -+ -+ return 0; -+} -+ -+int asmlinkage olpc_do_sleep(u8 sleep_state) -+{ -+ void *pgd_addr = __va(read_cr3()); -+ printk(KERN_ERR "olpc_do_sleep!\n"); /* this needs to remain here so -+ * that gcc doesn't optimize -+ * away our __va! */ -+ /* FIXME: Set the SCI bits we want to wake up on here */ -+ -+ /* FIXME: Set any other SCI events that we might want here */ -+ -+ outl((olpc_wakeup_mask << 16) | 0xFFFF, acpi_base + PM1_STS); -+ -+ wackup_source = NULL; -+ -+ /* If we are in test mode, then just return (simulate a successful -+ suspend/resume). Otherwise, if we are doing the real thing, -+ then go for the gusto */ -+ -+ if (olpc_pm_mode != PM_MODE_TEST) { -+ __asm__ __volatile__("movl %0,%%eax" : : "r" (pgd_addr)); -+ __asm__("call *(%%edi); cld" -+ : : "D" (&ofw_bios_entry)); -+ __asm__ __volatile__("movb $0x34, %al\n\t" -+ "outb %al, $0x70\n\t" -+ "movb $0x30, %al\n\t" -+ "outb %al, $0x71\n\t"); -+ -+ } -+ else if (test_timeout > 0) { -+ int t; -+ -+ /* Delay N seconds for testing purposes */ -+ -+ for(t = 0; t < test_timeout; t++) -+ mdelay(1000); -+ } -+ -+ return 0; -+} -+ -+static void olpc_power_off(void) -+{ -+ printk(KERN_INFO "OLPC power off sequence...\n"); -+ -+ /* Enable all of these controls with 0 delay */ -+ outl(0x40000000, pms_base + PM_SCLK); -+ outl(0x40000000, pms_base + PM_IN_SLPCTL); -+ outl(0x40000000, pms_base + PM_WKXD); -+ outl(0x40000000, pms_base + PM_WKD); -+ -+ /* Clear status bits (possibly unnecessary) */ -+ outl(0x0002ffff, pms_base + PM_SSC); -+ outl(0xffffffff, acpi_base + PM_GPE0_STS); -+ -+ /* Write SLP_EN bit to start the machinery */ -+ outl(0x00002000, acpi_base + PM1_CNT); -+} -+ -+/* This code will slowly disappear as we fixup the issues in the BIOS */ -+ -+static void __init olpc_fixup_bios(void) -+{ -+ unsigned long hi, lo; -+ -+ if (olpc_has_vsa()) { -+ /* The VSA aggressively sets up the ACPI and PM register for -+ * trapping - its not enough to force these values in the BIOS - -+ * they seem to be changed during PCI init as well. -+ */ -+ -+ /* Change the PM registers to decode to the DD */ -+ -+ rdmsr(0x510100e2, lo, hi); -+ hi |= 0x80000000; -+ wrmsr(0x510100e2, lo, hi); -+ -+ /* Change the ACPI registers to decode to the DD */ -+ -+ rdmsr(0x510100e3, lo, hi); -+ hi |= 0x80000000; -+ wrmsr(0x510100e3, lo, hi); -+ } -+ -+ /* GPIO24 controls WORK_AUX */ -+ -+ geode_gpio_set(OLPC_GPIO_WORKAUX, GPIO_OUTPUT_ENABLE); -+ geode_gpio_set(OLPC_GPIO_WORKAUX, GPIO_OUTPUT_AUX1); -+ -+ if (olpc_board_at_least(olpc_board(0xb2))) { -+ /* GPIO10 is connected to the thermal alarm */ -+ geode_gpio_set(OLPC_GPIO_THRM_ALRM, GPIO_INPUT_ENABLE); -+ geode_gpio_set(OLPC_GPIO_THRM_ALRM, GPIO_INPUT_AUX1); -+ -+ /* Set up to get LID events */ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_INPUT_ENABLE); -+ -+ /* Clear edge detection and event enable for now */ -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN); -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN); -+ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_STS); -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_STS); -+ -+ /* Set the LID to cause an PME event on group 6 */ -+ geode_gpio_event_pme(OLPC_GPIO_LID, 6); -+ -+ /* Set PME group 6 to fire the SCI interrupt */ -+ geode_gpio_set_irq(6, sci_irq); -+ } -+ -+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_INPUT_ENABLE); -+ -+ /* Clear pending events */ -+ -+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_NEGATIVE_EDGE_STS); -+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_POSITIVE_EDGE_STS); -+ -+ //geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_NEGATIVE_EDGE_EN); -+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_EVENTS_ENABLE); -+ -+ /* Set the SCI to cause a PME event on group 7 */ -+ geode_gpio_event_pme(OLPC_GPIO_ECSCI, 7); -+ -+ /* And have group 6 also fire the SCI interrupt */ -+ geode_gpio_set_irq(7, sci_irq); -+} -+ -+/* This provides a control file for setting up testing of the -+ power management system. For now, there is just one setting: -+ "test" which means that we don't actually enter the power -+ off routine. -+*/ -+ -+static const char * const pm_states[] = { -+ [PM_MODE_NORMAL] = "normal", -+ [PM_MODE_TEST] = "test", -+}; -+ -+extern struct mutex pm_mutex; -+extern struct kset power_subsys; -+ -+static ssize_t control_show(struct kset *s, char *buf) -+{ -+ return sprintf(buf, "%s\n", pm_states[olpc_pm_mode]); -+} -+ -+static ssize_t control_store(struct kset *s, const char *buf, size_t n) -+{ -+ int i, len; -+ char *p; -+ -+ p = memchr(buf, '\n', n); -+ len = p ? p - buf : n; -+ -+ /* Grab the mutex */ -+ mutex_lock(&pm_mutex); -+ -+ for(i = 0; i < PM_MODE_MAX; i++) { -+ if (!strncmp(buf, pm_states[i], len)) { -+ olpc_pm_mode = i; -+ break; -+ } -+ } -+ -+ mutex_unlock(&pm_mutex); -+ -+ return (i == PM_MODE_MAX) ? -EINVAL : n; -+} -+ -+static ssize_t timeout_show(struct kset *s, char *buf) -+{ -+ return sprintf(buf, "%d\n", test_timeout); -+} -+ -+static ssize_t timeout_store(struct kset *s, const char *buf, size_t n) -+{ -+ unsigned int t = simple_strtoul(buf, NULL, 0); -+ test_timeout = t; -+ -+ return n; -+} -+ -+static ssize_t wackup_show(struct kset *s, char *buf) -+{ -+ return sprintf(buf, "%s\n", wackup_source ? wackup_source : "none"); -+} -+ -+static struct subsys_attribute control_attr = { -+ .attr = { -+ .name = "olpc-pm", -+ .mode = 0644, -+ }, -+ .show = control_show, -+ .store = control_store, -+}; -+ -+static struct subsys_attribute test_attr = { -+ .attr = { -+ .name = "test-timeout", -+ .mode = 0644, -+ }, -+ .show = timeout_show, -+ .store = timeout_store, -+}; -+ -+static struct subsys_attribute wackup_attr = { -+ .attr = { -+ .name = "wakeup-source", -+ .mode = 0400, -+ }, -+ .show = wackup_show, -+}; -+ -+static struct attribute * olpc_attributes[] = { -+ &control_attr.attr, -+ &test_attr.attr, -+ &wackup_attr.attr, -+ NULL -+}; -+ -+static struct attribute_group olpc_attrs = { -+ .attrs = olpc_attributes, -+}; -+ -+static int __init alloc_inputdevs(void) -+{ -+ int ret = -ENOMEM; -+ -+ pm_inputdev = input_allocate_device(); -+ if (!pm_inputdev) -+ goto err; -+ -+ pm_inputdev->name = "OLPC PM"; -+ pm_inputdev->phys = "olpc_pm/input0"; -+ set_bit(EV_KEY, pm_inputdev->evbit); -+ set_bit(KEY_POWER, pm_inputdev->keybit); -+ -+ ret = input_register_device(pm_inputdev); -+ if (ret) { -+ printk(KERN_ERR "olpc-pm: failed to register PM input device: %d\n", ret); -+ goto err; -+ } -+ -+ lid_inputdev = input_allocate_device(); -+ if (!lid_inputdev) -+ goto err; -+ -+ lid_inputdev->name = "OLPC lid switch"; -+ lid_inputdev->phys = "olpc_pm/input1"; -+ set_bit(EV_SW, lid_inputdev->evbit); -+ set_bit(SW_LID, lid_inputdev->swbit); -+ -+ ret = input_register_device(lid_inputdev); -+ if (ret) { -+ printk(KERN_ERR "olpc-pm: failed to register lid input device: %d\n", ret); -+ goto err; -+ } -+ -+ ebook_inputdev = input_allocate_device(); -+ if (!ebook_inputdev) -+ goto err; -+ -+ ebook_inputdev->name = "OLPC ebook switch"; -+ ebook_inputdev->phys = "olpc_pm/input2"; -+ set_bit(EV_SW, ebook_inputdev->evbit); -+ set_bit(SW_TABLET_MODE, ebook_inputdev->swbit); -+ -+ ret = input_register_device(ebook_inputdev); -+ if (ret) { -+ printk(KERN_ERR "olpc-pm: failed to register ebook input device: %d\n", ret); -+ goto err; -+ } -+ -+ return ret; -+err: -+ if (ebook_inputdev) { -+ input_unregister_device(ebook_inputdev); -+ ebook_inputdev = NULL; -+ } -+ if (lid_inputdev) { -+ input_unregister_device(lid_inputdev); -+ lid_inputdev = NULL; -+ } -+ if (pm_inputdev) { -+ input_unregister_device(pm_inputdev); -+ pm_inputdev = NULL; -+ } -+ -+ return ret; -+} -+ -+static int __init olpc_pm_init(void) -+{ -+ uint32_t lo, hi; -+ int ret; -+ -+ if (!machine_is_olpc()) -+ return -ENODEV; -+ -+ acpi_base = geode_acpi_base(); -+ pms_base = geode_pms_base(); -+ -+ if (!acpi_base || !pms_base) -+ return -ENODEV; -+ -+ pm_power_off = olpc_power_off; -+ -+ ret = alloc_inputdevs(); -+ if (ret) -+ return ret; -+ -+ rdmsr(0x51400020, lo, hi); -+ sci_irq = (lo >> 20) & 15; -+ -+ if (sci_irq) { -+ printk(KERN_INFO "SCI is mapped to IRQ %d\n", sci_irq); -+ } else { -+ /* Zero doesn't mean zero -- it means masked */ -+ printk(KERN_INFO "SCI unmapped. Mapping to IRQ 3\n"); -+ sci_irq = 3; -+ lo |= 0x00300000; -+ wrmsrl(0x51400020, lo); -+ } -+ -+ olpc_fixup_bios(); -+ -+ lo = inl(pms_base + PM_FSD); -+ -+ /* Lock, enable failsafe, 4 seconds */ -+ outl(0xc001f400, pms_base + PM_FSD); -+ -+ /* Here we set up the SCI events we're interested in during -+ * real-time. We have no sleep button, and the RTC doesn't make -+ * sense, so set up the power button -+ */ -+ -+ outl(inl(acpi_base) | ((CS5536_PM_PWRBTN) << 16), acpi_base); -+ -+ if (olpc_board_at_least(olpc_board(0xb2))) { -+ gpio_wake_events |= GPIO_WAKEUP_LID; -+ -+ /* Get the current value of the GPIO, and set up the edges */ -+ olpc_lid_flag = geode_gpio_isset(OLPC_GPIO_LID, GPIO_READ_BACK); -+ -+ /* Watch for the opposite edge */ -+ -+ if (olpc_lid_flag) -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN); -+ else -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN); -+ -+ /* Enable the event */ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ } -+ -+ /* Set up the EC SCI */ -+ -+ gpio_wake_events |= GPIO_WAKEUP_EC; -+ -+ outl(gpio_wake_events, acpi_base + PM_GPE0_EN); -+ outl(0xFFFFFFFF, acpi_base + PM_GPE0_STS); -+ -+ /* Select level triggered in PIC */ -+ -+ if (sci_irq < 8) { -+ lo = inb(0x4d0); -+ lo |= 1 << sci_irq; -+ outb(lo, 0x4d0); -+ } else { -+ lo = inb(0x4d1); -+ lo |= 1 << (sci_irq - 8); -+ outb(lo, 0x4d1); -+ } -+ /* Clear pending interrupt */ -+ outl(inl(acpi_base) | 0xFFFF, acpi_base); -+ process_sci_queue(0); /* we just want to flush the queue here */ -+ init_ebook_state(); -+ -+ /* Enable the interrupt */ -+ -+ ret = request_irq(sci_irq, &olpc_pm_interrupt, 0, "SCI", &acpi_base); -+ -+ if (ret) { -+ printk(KERN_ERR "Error registering SCI: %d\n", ret); -+ return ret; -+ } -+ -+ ofw_bios_entry.address = 0xF0000 + PAGE_OFFSET; -+ suspend_set_ops(&olpc_pm_ops); -+ -+ sysfs_create_group(&power_subsys.kobj, &olpc_attrs); -+ -+ return 0; -+} -+ -+ -+#if defined (CONFIG_RTC_DRV_CMOS) || defined (CONFIG_RTC_DRV_CMOS_MODULE) -+struct resource rtc_platform_resource[2] = { -+ { -+ .flags = IORESOURCE_IO, -+ .start = RTC_PORT(0), -+ .end = RTC_PORT(0) + RTC_IO_EXTENT -+ }, -+ { -+ .flags = IORESOURCE_IRQ, -+ .start = 8, -+ .end = 8, -+ }, -+}; -+ -+ -+static void rtc_wake_on(struct device *dev) -+{ -+ olpc_wakeup_mask |= CS5536_PM_RTC; -+} -+ -+static void rtc_wake_off(struct device *dev) -+{ -+ olpc_wakeup_mask &= ~(CS5536_PM_RTC); -+} -+ -+static struct cmos_rtc_board_info rtc_info = { -+ .rtc_day_alarm = 0, -+ .rtc_mon_alarm = 0, -+ .rtc_century = 0, -+ .wake_on = rtc_wake_on, -+ .wake_off = rtc_wake_off, -+}; -+ -+struct platform_device olpc_rtc_device = { -+ .name = "rtc_cmos", -+ .id = -1, -+ .num_resources = ARRAY_SIZE(rtc_platform_resource), -+ .dev.platform_data = &rtc_info, -+ .resource = rtc_platform_resource, -+}; -+ -+static int __init olpc_platform_init(void) -+{ -+ rdmsrl(MSR_RTC_DOMA_OFFSET, rtc_info.rtc_day_alarm); -+ rdmsrl(MSR_RTC_MONA_OFFSET, rtc_info.rtc_mon_alarm); -+ rdmsrl(MSR_RTC_CEN_OFFSET, rtc_info.rtc_century); -+ -+ (void)platform_device_register(&olpc_rtc_device); -+ device_init_wakeup(&olpc_rtc_device.dev, 1); -+ -+ (void)platform_device_register(&olpc_powerbutton_dev); -+ device_init_wakeup(&olpc_powerbutton_dev.dev, 1); -+ -+ (void)platform_device_register(&olpc_lid_dev); -+ device_init_wakeup(&olpc_lid_dev.dev, 1); -+ -+ return 0; -+} -+arch_initcall(olpc_platform_init); -+#endif /* CONFIG_RTC_DRV_CMOS */ -+ -+static void olpc_pm_exit(void) -+{ -+ /* Clear any pending events, and disable them */ -+ outl(0xFFFF, acpi_base+2); -+ -+ free_irq(sci_irq, &acpi_base); -+ input_unregister_device(pm_inputdev); -+ input_unregister_device(lid_inputdev); -+ input_unregister_device(ebook_inputdev); -+} -+ -+static struct platform_suspend_ops olpc_pm_ops = { -+ .valid = olpc_pm_state_valid, -+ .enter = olpc_pm_enter, -+}; -+ -+module_init(olpc_pm_init); -+module_exit(olpc_pm_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("David Woodhouse "); -+MODULE_DESCRIPTION("AMD Geode power management for OLPC CL1"); -Index: linux-2.6.24.7/arch/x86/kernel/olpc-sleep.S -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/arch/x86/kernel/olpc-sleep.S -@@ -0,0 +1,39 @@ -+.text -+ -+ENTRY(olpc_sleep_asm) -+olpc_sleep: -+ ;; Get the value of PM1_CNT and store it off -+ -+ add 08h, ax -+ mov bx,dx -+ in dx,eax -+ or 2000h, ax -+ mov ax,di -+ -+ ;; flush the cache -+ wbinvd -+ -+ ;; GX2 must disable refresh before going into self-refresh -+ mov 2000000180xh, ecx -+ rdmsr -+ mov eax, esi -+ and 0FF0000FFh, eax -+ wrmsr -+ -+ ;; Now, put the memory into self refresh -+ mov 2004, cx -+ xor edx, edx -+ xor eax, eax -+ mov 04h, al -+ wrmsr -+ -+ ;; Thats all she wrote - time to go to sleep -+ -+ mov bx, dx -+ movzx di, eax -+ out eax, dx -+ -+ ;; -+ -+ -+ -Index: linux-2.6.24.7/arch/x86/kernel/olpc-wakeup.S -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/arch/x86/kernel/olpc-wakeup.S -@@ -0,0 +1,133 @@ -+.text -+#include -+#include -+#include -+ -+ .macro writepost,value -+ movb $0x34, %al -+ outb %al, $0x70 -+ movb $\value, %al -+ outb %al, $0x71 -+ .endm -+ -+ALIGN -+ .align 4096 -+ -+wakeup_start: -+# jmp wakeup_start -+ -+ cli -+ cld -+ -+ # Clear any dangerous flags -+ -+ pushl $0 -+ popfl -+ -+ writepost 0x31 -+ -+ # Set up %cr3 -+ movl $swsusp_pg_dir - __PAGE_OFFSET, %eax -+ movl %eax, %cr3 -+ -+ movl saved_cr4, %eax -+ movl %eax, %cr4 -+ -+ movl saved_cr0, %eax -+ movl %eax, %cr0 -+ -+ jmp 1f -+1: -+ ljmpl $__KERNEL_CS,$wakeup_return -+ -+ -+.org 0x1000 -+ -+wakeup_return: -+ movw $__KERNEL_DS, %ax -+ movw %ax, %ss -+ movw %ax, %ds -+ movw %ax, %es -+ movw %ax, %fs -+ movw %ax, %gs -+ -+ lgdt saved_gdt -+ lidt saved_idt -+ lldt saved_ldt -+ ljmp $(__KERNEL_CS),$1f -+1: -+ movl %cr3, %eax -+ movl %eax, %cr3 -+ wbinvd -+ -+ # Go back to the return point -+ jmp ret_point -+ -+save_registers: -+ sgdt saved_gdt -+ sidt saved_idt -+ sldt saved_ldt -+ -+ pushl %edx -+ movl %cr4, %edx -+ movl %edx, saved_cr4 -+ -+ movl %cr0, %edx -+ movl %edx, saved_cr0 -+ -+ popl %edx -+ -+ -+ movl %ebx, saved_context_ebx -+ movl %ebp, saved_context_ebp -+ movl %esi, saved_context_esi -+ movl %edi, saved_context_edi -+ -+ pushfl -+ popl saved_context_eflags -+ -+ ret -+ -+ -+restore_registers: -+ movl saved_context_ebp, %ebp -+ movl saved_context_ebx, %ebx -+ movl saved_context_esi, %esi -+ movl saved_context_edi, %edi -+ -+ pushl saved_context_eflags -+ popfl -+ -+ ret -+ -+ -+ENTRY(do_olpc_suspend_lowlevel) -+ call save_processor_state -+ call save_registers -+ -+ # This is the stack context we want to remember -+ movl %esp, saved_context_esp -+ -+ pushl $3 -+ call olpc_do_sleep -+ -+ jmp wakeup_start -+ .p2align 4,,7 -+ret_point: -+ movl saved_context_esp, %esp -+ -+ writepost 0x32 -+ -+ call restore_registers -+ call restore_processor_state -+ ret -+ -+.data -+ALIGN -+ -+saved_gdt: .long 0,0 -+saved_idt: .long 0,0 -+saved_ldt: .long 0 -+saved_cr4: .long 0 -+saved_cr0: .long 0 -+ -Index: linux-2.6.24.7/arch/x86/kernel/prom.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/arch/x86/kernel/prom.c -@@ -0,0 +1,478 @@ -+/* -+ * Procedures for creating, accessing and interpreting the device tree. -+ * -+ * Paul Mackerras August 1996. -+ * Copyright (C) 1996-2005 Paul Mackerras. -+ * -+ * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner. -+ * {engebret|bergner}@us.ibm.com -+ * -+ * Adapted for sparc64 by David S. Miller davem@davemloft.net -+ * -+ * Adapter for i386/OLPC by Andres Salomon -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * XXX: This is very much a stub; right now we're keeping 2 device trees -+ * in memory (one for promfs, and one here). That will not remain -+ * for long! -+ */ -+ -+static struct device_node *allnodes; -+ -+/* use when traversing tree through the allnext, child, sibling, -+ * or parent members of struct device_node. -+ */ -+static DEFINE_RWLOCK(devtree_lock); -+ -+int of_device_is_compatible(const struct device_node *device, -+ const char *compat) -+{ -+ const char* cp; -+ int cplen, l; -+ -+ cp = of_get_property(device, "compatible", &cplen); -+ if (cp == NULL) -+ return 0; -+ while (cplen > 0) { -+ if (strncmp(cp, compat, strlen(compat)) == 0) -+ return 1; -+ l = strlen(cp) + 1; -+ cp += l; -+ cplen -= l; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(of_device_is_compatible); -+ -+struct device_node *of_get_parent(const struct device_node *node) -+{ -+ struct device_node *np; -+ -+ if (!node) -+ return NULL; -+ -+ np = node->parent; -+ -+ return np; -+} -+EXPORT_SYMBOL(of_get_parent); -+ -+struct device_node *of_get_next_child(const struct device_node *node, -+ struct device_node *prev) -+{ -+ struct device_node *next; -+ -+ next = prev ? prev->sibling : node->child; -+ for (; next != 0; next = next->sibling) { -+ break; -+ } -+ -+ return next; -+} -+EXPORT_SYMBOL(of_get_next_child); -+ -+struct device_node *of_find_node_by_path(const char *path) -+{ -+ struct device_node *np = allnodes; -+ -+ for (; np != 0; np = np->allnext) { -+ if (np->full_name != 0 && strcmp(np->full_name, path) == 0) -+ break; -+ } -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_node_by_path); -+ -+struct device_node *of_find_node_by_phandle(phandle handle) -+{ -+ struct device_node *np; -+ -+ for (np = allnodes; np != 0; np = np->allnext) -+ if (np->node == handle) -+ break; -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_node_by_phandle); -+ -+struct device_node *of_find_node_by_name(struct device_node *from, -+ const char *name) -+{ -+ struct device_node *np; -+ -+ np = from ? from->allnext : allnodes; -+ for (; np != NULL; np = np->allnext) -+ if (np->name != NULL && strcmp(np->name, name) == 0) -+ break; -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_node_by_name); -+ -+struct device_node *of_find_node_by_type(struct device_node *from, -+ const char *type) -+{ -+ struct device_node *np; -+ -+ np = from ? from->allnext : allnodes; -+ for (; np != 0; np = np->allnext) -+ if (np->type != 0 && strcmp(np->type, type) == 0) -+ break; -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_node_by_type); -+ -+struct device_node *of_find_compatible_node(struct device_node *from, -+ const char *type, const char *compatible) -+{ -+ struct device_node *np; -+ -+ np = from ? from->allnext : allnodes; -+ for (; np != 0; np = np->allnext) { -+ if (type != NULL -+ && !(np->type != 0 && strcmp(np->type, type) == 0)) -+ continue; -+ if (of_device_is_compatible(np, compatible)) -+ break; -+ } -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_compatible_node); -+ -+struct property *of_find_property(const struct device_node *np, -+ const char *name, -+ int *lenp) -+{ -+ struct property *pp; -+ -+ for (pp = np->properties; pp != 0; pp = pp->next) { -+ if (strcasecmp(pp->name, name) == 0) { -+ if (lenp != 0) -+ *lenp = pp->length; -+ break; -+ } -+ } -+ return pp; -+} -+EXPORT_SYMBOL(of_find_property); -+ -+/* -+ * Find a property with a given name for a given node -+ * and return the value. -+ */ -+const void *of_get_property(const struct device_node *np, const char *name, -+ int *lenp) -+{ -+ struct property *pp = of_find_property(np,name,lenp); -+ return pp ? pp->value : NULL; -+} -+EXPORT_SYMBOL(of_get_property); -+ -+int of_getintprop_default(struct device_node *np, const char *name, int def) -+{ -+ struct property *prop; -+ int len; -+ -+ prop = of_find_property(np, name, &len); -+ if (!prop || len != 4) -+ return def; -+ -+ return *(int *) prop->value; -+} -+EXPORT_SYMBOL(of_getintprop_default); -+ -+int of_n_addr_cells(struct device_node *np) -+{ -+ const int* ip; -+ do { -+ if (np->parent) -+ np = np->parent; -+ ip = of_get_property(np, "#address-cells", NULL); -+ if (ip != NULL) -+ return *ip; -+ } while (np->parent); -+ /* No #address-cells property for the root node, default to 2 */ -+ return 2; -+} -+EXPORT_SYMBOL(of_n_addr_cells); -+ -+int of_n_size_cells(struct device_node *np) -+{ -+ const int* ip; -+ do { -+ if (np->parent) -+ np = np->parent; -+ ip = of_get_property(np, "#size-cells", NULL); -+ if (ip != NULL) -+ return *ip; -+ } while (np->parent); -+ /* No #size-cells property for the root node, default to 1 */ -+ return 1; -+} -+EXPORT_SYMBOL(of_n_size_cells); -+ -+int of_set_property(struct device_node *dp, const char *name, void *val, int len) -+{ -+ return -EIO; -+} -+EXPORT_SYMBOL(of_set_property); -+ -+static unsigned int prom_early_allocated; -+ -+static void * __init prom_early_alloc(unsigned long size) -+{ -+ void *ret; -+ -+ ret = kmalloc(size, GFP_KERNEL); -+ if (ret != NULL) -+ memset(ret, 0, size); -+ else -+ printk(KERN_ERR "ACK! couldn't allocate prom memory!\n"); -+ -+ prom_early_allocated += size; -+ -+ return ret; -+} -+ -+static int is_root_node(const struct device_node *dp) -+{ -+ if (!dp) -+ return 0; -+ -+ return (dp->parent == NULL); -+} -+ -+static char * __init build_path_component(struct device_node *dp) -+{ -+ int pathlen; -+ char *n, *i; -+ -+ if (ofw("package-to-path", 3, 1, dp->node, NULL, 0, &pathlen)) { -+ printk(KERN_ERR "PROM: unable to get path name from OFW!\n"); -+ return "ERROR"; -+ } -+ n = prom_early_alloc(pathlen + 1); -+ if (ofw("package-to-path", 3, 1, dp->node, n, pathlen+1, &pathlen)) -+ printk(KERN_ERR "PROM: unable to get path name from OFW\n"); -+ -+ if ((i = strrchr(n, '/'))) -+ n = ++i; /* we only want the file name */ -+ return n; -+} -+ -+static char * __init build_full_name(struct device_node *dp) -+{ -+ int len, ourlen, plen; -+ char *n; -+ -+ plen = strlen(dp->parent->full_name); -+ ourlen = strlen(dp->path_component_name); -+ len = ourlen + plen + 2; -+ -+ n = prom_early_alloc(len); -+ strcpy(n, dp->parent->full_name); -+ if (!is_root_node(dp->parent)) { -+ strcpy(n + plen, "/"); -+ plen++; -+ } -+ strcpy(n + plen, dp->path_component_name); -+ -+ return n; -+} -+ -+static struct property * __init build_one_prop(phandle node, char *prev, char *special_name, void *special_val, int special_len) -+{ -+ static struct property *tmp = NULL; -+ struct property *p; -+ -+ if (tmp) { -+ p = tmp; -+ memset(p, 0, sizeof(*p) + 32); -+ tmp = NULL; -+ } else { -+ p = prom_early_alloc(sizeof(struct property) + 32); -+ } -+ -+ p->name = (char *) (p + 1); -+ if (special_name) { -+ strcpy(p->name, special_name); -+ p->length = special_len; -+ p->value = prom_early_alloc(special_len); -+ memcpy(p->value, special_val, special_len); -+ } else { -+ int fl; -+ if (prev == NULL) { -+ if (ofw("nextprop", 3, 1, node, "", p->name, &fl)) { -+ printk(KERN_ERR "PROM: %s: nextprop failed!\n", __func__); -+ return NULL; -+ } -+ } else { -+ if (ofw("nextprop", 3, 1, node, prev, p->name, &fl)) { -+ printk(KERN_ERR "PROM: %s: nextprop failed!\n", __func__); -+ return NULL; -+ } -+ } -+ if (strlen(p->name) == 0 || fl != 1) { -+ tmp = p; -+ return NULL; -+ } -+ if (ofw("getproplen", 2, 1, node, p->name, &p->length)) { -+ printk(KERN_ERR "PROM: %s: getproplen failed!\n", __func__); -+ return NULL; -+ } -+ if (p->length <= 0) { -+ p->length = 0; -+ } else { -+ p->value = prom_early_alloc(p->length + 1); -+ if (ofw("getprop", 4, 1, node, p->name, p->value, p->length, &p->length)) { -+ printk(KERN_ERR "PROM: %s: getprop failed!\n", __func__); -+ return NULL; -+ } -+ ((unsigned char *)p->value)[p->length] = '\0'; -+ } -+ } -+ return p; -+} -+ -+static struct property * __init build_prop_list(phandle node) -+{ -+ struct property *head, *tail; -+ -+ head = tail = build_one_prop(node, NULL, -+ ".node", &node, sizeof(node)); -+ -+ tail->next = build_one_prop(node, NULL, NULL, NULL, 0); -+ tail = tail->next; -+ while(tail) { -+ tail->next = build_one_prop(node, tail->name, -+ NULL, NULL, 0); -+ tail = tail->next; -+ } -+ -+ return head; -+} -+ -+static char * __init get_one_property(phandle node, const char *name) -+{ -+ char *buf = ""; -+ int len; -+ -+ if (ofw("getproplen", 2, 1, node, name, &len)) { -+ printk(KERN_ERR "PROM: %s: getproplen failed!\n", __func__); -+ return NULL; -+ } -+ if (len > 0) { -+ buf = prom_early_alloc(len); -+ if (ofw("getprop", 4, 1, node, name, buf, len, &len)) { -+ printk(KERN_ERR "PROM: %s: getprop failed!\n", __func__); -+ return NULL; -+ } -+ } -+ -+ return buf; -+} -+ -+static struct device_node * __init create_node(phandle node, struct device_node *parent) -+{ -+ struct device_node *dp; -+ -+ if (!node) -+ return NULL; -+ -+ dp = prom_early_alloc(sizeof(*dp)); -+ dp->parent = parent; -+ -+ kref_init(&dp->kref); -+ -+ dp->name = get_one_property(node, "name"); -+ dp->type = get_one_property(node, "device_type"); -+ dp->node = node; -+ -+ dp->properties = build_prop_list(node); -+ -+ return dp; -+} -+ -+static struct device_node * __init build_tree(struct device_node *parent, phandle node, struct device_node ***nextp) -+{ -+ struct device_node *ret = NULL, *prev_sibling = NULL; -+ struct device_node *dp; -+ u32 child; -+ -+ while (1) { -+ dp = create_node(node, parent); -+ if (!dp) -+ break; -+ -+ if (prev_sibling) -+ prev_sibling->sibling = dp; -+ -+ if (!ret) -+ ret = dp; -+ prev_sibling = dp; -+ -+ *(*nextp) = dp; -+ *nextp = &dp->allnext; -+ -+ dp->path_component_name = build_path_component(dp); -+ dp->full_name = build_full_name(dp); -+ -+ if (ofw("child", 1, 1, node, &child)) { -+ printk(KERN_ERR "PROM: %s: fetching child failed!\n", __func__); -+ return NULL; -+ } -+ dp->child = build_tree(dp, child, nextp); -+ -+ if (ofw("peer", 1, 1, node, &node)) { -+ printk(KERN_ERR "PROM: %s: fetching peer failed!\n", __func__); -+ return NULL; -+ } -+ } -+ -+ return ret; -+} -+ -+static phandle root_node; -+ -+void __init prom_build_devicetree(void) -+{ -+ struct device_node **nextp; -+ u32 child; -+ -+ if (ofw("peer", 1, 1, 0, &root_node)) { -+ printk(KERN_ERR "PROM: unable to get root node from OFW!\n"); -+ return; -+ } -+ -+ allnodes = create_node(root_node, NULL); -+ allnodes->path_component_name = ""; -+ allnodes->full_name = "/"; -+ -+ nextp = &allnodes->allnext; -+ if (ofw("child", 1, 1, allnodes->node, &child)) { -+ printk(KERN_ERR "PROM: unable to get child node from OFW!\n"); -+ return; -+ } -+ allnodes->child = build_tree(allnodes, child, &nextp); -+ printk("PROM: Built device tree with %u bytes of memory.\n", -+ prom_early_allocated); -+} -Index: linux-2.6.24.7/arch/x86/pci/olpc.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/arch/x86/pci/olpc.c -@@ -0,0 +1,298 @@ -+/* -+ * olpcpci.c - Low-level PCI config space access for OLPC systems -+ * without the VSA PCI virtualization software. -+ * -+ * The AMD Geode chipset (GX2 processor, cs5536 I/O companion device) -+ * has some I/O functions (display, southbridge, sound, USB HCIs, etc) -+ * that more or less behave like PCI devices, but the hardware doesn't -+ * directly implement the PCI configuration space headers. AMD provides -+ * "VSA" (Virtual System Architecture) software that emulates PCI config -+ * space for these devices, by trapping I/O accesses to PCI config register -+ * (CF8/CFC) and running some code in System Management Mode interrupt state. -+ * On the OLPC platform, we don't want to use that VSA code because -+ * (a) it slows down suspend/resume, and (b) recompiling it requires special -+ * compilers that are hard to get. So instead of letting the complex VSA -+ * code simulate the PCI config registers for the on-chip devices, we -+ * just simulate them the easy way, by inserting the code into the -+ * pci_write_config and pci_read_config path. Most of the config registers -+ * are read-only anyway, so the bulk of the simulation is just table lookup. -+ */ -+ -+#include -+#include -+#include -+#include -+#include "pci.h" -+ -+static int is_lx; -+ -+/* -+ * In the tables below, the first two line (8 longwords) are the -+ * size masks that are used when the higher level PCI code determines -+ * the size of the region by writing ~0 to a base address register -+ * and reading back the result. -+ * -+ * The following lines are the values that are read during normal -+ * PCI config access cycles, i.e. not after just having written -+ * ~0 to a base address register. -+ */ -+ -+static const u32 lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x281022 , 0x2200005 , 0x6000021 , 0x80f808 , /* AMD Vendor ID */ -+ 0x0 , 0x0 , 0x0 , 0x0 , /* No virtual registers, hence no BAR for them */ -+ 0x0 , 0x0 , 0x0 , 0x28100b , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ -+ 0xfffffffd , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x28100b , 0x2200005 , 0x6000021 , 0x80f808 , /* NSC Vendor ID */ -+ 0xac1d , 0x0 , 0x0 , 0x0 , /* I/O BAR - base of virtual registers */ -+ 0x0 , 0x0 , 0x0 , 0x28100b , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ -+ 0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20811022 , 0x2200003 , 0x3000000 , 0x0 , /* AMD Vendor ID */ -+ 0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */ -+ 0xfe00c000 , 0x0 , 0x0 , 0x30100b , /* VIP */ -+ 0x0 , 0x0 , 0x0 , 0x10e , /* INTA, IRQ14 for graphics accel */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ -+ 0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x30100b , 0x2200003 , 0x3000000 , 0x0 , /* NSC Vendor ID */ -+ 0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */ -+ 0x0 , 0x0 , 0x0 , 0x30100b , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */ -+ 0xffffc000 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20821022 , 0x2a00006 , 0x10100000 , 0x8 , /* NSC Vendor ID */ -+ 0xfe010000 , 0x0 , 0x0 , 0x0 , /* AES registers */ -+ 0x0 , 0x0 , 0x0 , 0x20821022 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+ -+static const u32 isa_hdr[] = { /* dev f function 0 - devfn = 78 */ -+ 0xfffffff9 , 0xffffff01 , 0xffffffc1 , 0xffffffe1 , -+ 0xffffff81 , 0xffffffc1 , 0x0 , 0x0 , -+ -+ 0x20901022 , 0x2a00049 , 0x6010003 , 0x802000 , -+ 0x18b1 , 0x1001 , 0x1801 , 0x1881 , /* SMB-8 GPIO-256 MFGPT-64 IRQ-32 */ -+ 0x1401 , 0x1841 , 0x0 , 0x20901022 , /* PMS-128 ACPI-64 */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0xaa5b , /* interrupt steering */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 ac97_hdr[] = { /* dev f function 3 - devfn = 7b */ -+ 0xffffff81 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20931022 , 0x2a00041 , 0x4010001 , 0x0 , -+ 0x1481 , 0x0 , 0x0 , 0x0 , /* I/O BAR-128 */ -+ 0x0 , 0x0 , 0x0 , 0x20931022 , -+ 0x0 , 0x0 , 0x0 , 0x205 , /* IntB , IRQ5 */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 ohci_hdr[] = { /* dev f function 4 - devfn = 7c */ -+ 0xfffff000 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20941022 , 0x2300006 , 0xc031002 , 0x0 , -+ 0xfe01a000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */ -+ 0x0 , 0x0 , 0x0 , 0x20941022 , -+ 0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */ -+ 0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 ehci_hdr[] = { /* dev f function 4 - devfn = 7d */ -+ 0xfffff000 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20951022 , 0x2300006 , 0xc032002 , 0x0 , -+ 0xfe01b000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */ -+ 0x0 , 0x0 , 0x0 , 0x20951022 , -+ 0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */ -+ 0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */ -+#if 0 -+ 0x1 , 0x40080000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */ -+#endif -+ 0x01000001 , 0x00000000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */ -+ 0x2020 , 0x0 , 0x0 , 0x0 , /* (EHCI page 8) 60 SBRN (R/O), 61 FLADJ (R/W), PORTWAKECAP */ -+}; -+ -+static u32 ff_loc = ~0; -+static u32 zero_loc = 0; -+ -+static int bar_probing = 0; /* Set after a write of ~0 to a BAR */ -+ -+#define NB_SLOT 0x1 /* Northbridge - GX chip - Device 1 */ -+#define SB_SLOT 0xf /* Southbridge - CS5536 chip - Device F */ -+#define SIMULATED(bus, devfn) (((bus) == 0) && ((PCI_SLOT(devfn) == NB_SLOT) || (PCI_SLOT(devfn) == SB_SLOT))) -+ -+static u32 *hdr_addr(const u32 *hdr, int reg) -+{ -+ u32 addr; -+ -+ /* -+ * This is a little bit tricky. The header maps consist of -+ * 0x20 bytes of size masks, followed by 0x70 bytes of header data. -+ * In the normal case, when not probing a BAR's size, we want -+ * to access the header data, so we add 0x20 to the reg offset, -+ * thus skipping the size mask area. -+ * In the BAR probing case, we want to access the size mask for -+ * the BAR, so we subtract 0x10 (the config header offset for -+ * BAR0), and don't skip the size mask area. -+ */ -+ -+ addr = (u32)hdr + reg + (bar_probing ? -0x10 : 0x20); -+ -+ bar_probing = 0; -+ return (u32 *)addr; -+} -+ -+static int pci_olpc_read(unsigned int seg, unsigned int bus, -+ unsigned int devfn, int reg, int len, u32 *value) -+{ -+ u32 *addr; -+ -+ /* Use the hardware mechanism for non-simulated devices */ -+ if (!SIMULATED(bus, devfn)) -+ return pci_conf1_read(seg, bus, devfn, reg, len, value); -+ -+ /* -+ * No device has config registers past 0x70, so we save table space -+ * by not storing entries for the nonexistent registers -+ */ -+ if (reg >= 0x70) -+ addr = &zero_loc; -+ else { -+ switch (devfn) { -+ case 0x8: -+ addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg); -+ break; -+ case 0x9: -+ addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg); -+ break; -+ case 0xa: -+ addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc; -+ break; -+ case 0x78: -+ addr = hdr_addr(isa_hdr, reg); -+ break; -+ case 0x7b: -+ addr = hdr_addr(ac97_hdr, reg); -+ break; -+ case 0x7c: -+ addr = hdr_addr(ohci_hdr, reg); -+ break; -+ case 0x7d: -+ addr = hdr_addr(ehci_hdr, reg); -+ break; -+ default: -+ addr = &ff_loc; -+ break; -+ } -+ } -+ switch (len) { -+ case 1: -+ *value = *(u8 *) addr; -+ break; -+ case 2: -+ *value = *(u16 *) addr; -+ break; -+ case 4: -+ *value = *addr; -+ break; -+ default: -+ BUG(); -+ } -+ -+ return 0; -+} -+ -+static int pci_olpc_write(unsigned int seg, unsigned int bus, -+ unsigned int devfn, int reg, int len, u32 value) -+{ -+ /* Use the hardware mechanism for non-simulated devices */ -+ if (!SIMULATED(bus, devfn)) -+ return pci_conf1_write(seg, bus, devfn, reg, len, value); -+ -+ /* XXX we may want to extend this to simulate EHCI power management */ -+ -+ /* -+ * Mostly we just discard writes, but if the write is a size probe -+ * (i.e. writing ~0 to a BAR), we remember it and arrange to return -+ * the appropriate size mask on the next read. This is cheating -+ * to some extent, because it depends on the fact that the next -+ * access after such a write will always be a read to the same BAR. -+ */ -+ -+ if ((reg >= 0x10) && (reg < 0x2c)) { -+ /* Write is to a BAR */ -+ if (value == ~0) -+ bar_probing = 1; -+ } else { -+ /* -+ * No warning on writes to ROM BAR, CMD, LATENCY_TIMER, -+ * CACHE_LINE_SIZE, or PM registers. -+ */ -+ if ((reg != 0x30) && (reg != 0x04) && (reg != 0x0d) && -+ (reg != 0x0c) && (reg != 0x44)) -+ printk(KERN_WARNING "OLPC PCI: Config write to devfn %x reg %x value %x\n", devfn, reg, value); -+ } -+ -+ return 0; -+} -+ -+static struct pci_raw_ops pci_olpc_conf = { -+ .read = pci_olpc_read, -+ .write = pci_olpc_write, -+}; -+ -+void __init pci_olpc_init(void) -+{ -+ if (!machine_is_olpc() || olpc_has_vsa()) -+ return; -+ -+ printk(KERN_INFO "PCI: Using configuration type OLPC\n"); -+ raw_pci_ops = &pci_olpc_conf; -+ is_lx = is_geode_lx(); -+} -Index: linux-2.6.24.7/Documentation/kernel-parameters.txt -=================================================================== ---- linux-2.6.24.7.orig/Documentation/kernel-parameters.txt -+++ linux-2.6.24.7/Documentation/kernel-parameters.txt -@@ -1244,6 +1244,13 @@ and is between 256 and 4096 characters. - - nr_uarts= [SERIAL] maximum number of UARTs to be registered. - -+ olpc_ec_timeout= [OLPC] ms delay when issuing EC commands -+ Rather than timing out after 20 ms if an EC -+ command is not properly ACKed, override the length -+ of the timeout. We have interrupts disabled while -+ waiting for the ACK, so if this is set too high -+ interrupts *may* be lost! -+ - opl3= [HW,OSS] - Format: - -Index: linux-2.6.24.7/drivers/base/dd.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/base/dd.c -+++ linux-2.6.24.7/drivers/base/dd.c -@@ -293,7 +293,6 @@ static void __device_release_driver(stru - if (drv) { - driver_sysfs_remove(dev); - sysfs_remove_link(&dev->kobj, "driver"); -- klist_remove(&dev->knode_driver); - - if (dev->bus) - blocking_notifier_call_chain(&dev->bus->bus_notifier, -@@ -306,6 +305,7 @@ static void __device_release_driver(stru - drv->remove(dev); - devres_release_all(dev); - dev->driver = NULL; -+ klist_remove(&dev->knode_driver); - put_driver(drv); - } - } -Index: linux-2.6.24.7/drivers/char/vt_ioctl.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/char/vt_ioctl.c -+++ linux-2.6.24.7/drivers/char/vt_ioctl.c -@@ -38,6 +38,9 @@ - char vt_dont_switch; - extern struct tty_driver *console_driver; - -+/* Add a notifier chain to inform drivers of a VT_TEXT/VT_GRAPHICS switch */ -+RAW_NOTIFIER_HEAD(console_notifier_list); -+ - #define VT_IS_IN_USE(i) (console_driver->ttys[i] && console_driver->ttys[i]->count) - #define VT_BUSY(i) (VT_IS_IN_USE(i) || i == fg_console || vc_cons[i].d == sel_cons) - -@@ -492,6 +495,14 @@ int vt_ioctl(struct tty_struct *tty, str - vc->vc_mode = (unsigned char) arg; - if (console != fg_console) - return 0; -+ -+ /* Notify listeners if the current fg_console has switched */ -+ -+ raw_notifier_call_chain(&console_notifier_list, -+ (arg == KD_TEXT) ? -+ CONSOLE_EVENT_SWITCH_TEXT : -+ CONSOLE_EVENT_SWITCH_GRAPHICS, 0); -+ - /* - * explicitly blank/unblank the screen if switching modes - */ -Index: linux-2.6.24.7/drivers/i2c/busses/scx200_acb.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/i2c/busses/scx200_acb.c -+++ linux-2.6.24.7/drivers/i2c/busses/scx200_acb.c -@@ -46,6 +46,10 @@ static int base[MAX_DEVICES] = { 0x820, - module_param_array(base, int, NULL, 0); - MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers"); - -+static unsigned int smbclk = 0x70; -+module_param(smbclk, uint, 0); -+MODULE_PARM_DESC(smbclk, "Specify the SMB_CLK value"); -+ - #define POLL_TIMEOUT (HZ/5) - - enum scx200_acb_state { -@@ -108,6 +112,7 @@ struct scx200_acb_iface { - #define ACBADDR (iface->base + 4) - #define ACBCTL2 (iface->base + 5) - #define ACBCTL2_ENABLE 0x01 -+#define ACBCTL3 (iface->base + 6) - - /************************************************************************/ - -@@ -392,11 +397,13 @@ static __init int scx200_acb_probe(struc - { - u8 val; - -- /* Disable the ACCESS.bus device and Configure the SCL -- frequency: 16 clock cycles */ -- outb(0x70, ACBCTL2); -+ /* Disable the ACCESS.bus device and Configure the SCL */ -+ -+ outb((smbclk & 0x7F) << 1, ACBCTL2); -+ -+ outb((smbclk >> 7) & 0xFF, ACBCTL3); - -- if (inb(ACBCTL2) != 0x70) { -+ if (inb(ACBCTL2) != ((smbclk & 0x7F) << 1)) { - pr_debug(NAME ": ACBCTL2 readback failed\n"); - return -ENXIO; - } -Index: linux-2.6.24.7/drivers/input/keyboard/atkbd.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/input/keyboard/atkbd.c -+++ linux-2.6.24.7/drivers/input/keyboard/atkbd.c -@@ -63,12 +63,25 @@ static int atkbd_extra; - module_param_named(extra, atkbd_extra, bool, 0); - MODULE_PARM_DESC(extra, "Enable extra LEDs and keys on IBM RapidAcces, EzKey and similar keyboards"); - -+#define ATKBD_KEY_UNKNOWN 0 -+#define ATKBD_KEY_NULL 0xFF0000FF -+ -+#define ATKBD_SCR_1 0xFF0000FE -+#define ATKBD_SCR_2 0xFF0000FD -+#define ATKBD_SCR_4 0xFF0000FC -+#define ATKBD_SCR_8 0xFF0000FB -+#define ATKBD_SCR_CLICK 0xFF0000FA -+#define ATKBD_SCR_LEFT 0xFF0000F9 -+#define ATKBD_SCR_RIGHT 0xFF0000F8 -+ -+#define ATKBD_SPECIAL 0xFF0000F8 -+ - /* - * Scancode to keycode tables. These are just the default setting, and - * are loadable via an userland utility. - */ - --static unsigned char atkbd_set2_keycode[512] = { -+static unsigned int atkbd_set2_keycode[512] = { - - #ifdef CONFIG_KEYBOARD_ATKBD_HP_KEYCODES - -@@ -87,11 +100,17 @@ static unsigned char atkbd_set2_keycode[ - 82, 83, 80, 76, 77, 72, 1, 69, 87, 78, 81, 74, 55, 73, 70, 99, - - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 217,100,255, 0, 97,165, 0, 0,156, 0, 0, 0, 0, 0, 0,125, -+ -+ 217,100,ATKBD_KEY_NULL, 0, 97,165, 0, 0, -+ 156, 0, 0, 0, 0, 0, 0,125, -+ - 173,114, 0,113, 0, 0, 0,126,128, 0, 0,140, 0, 0, 0,127, - 159, 0,115, 0,164, 0, 0,116,158, 0,172,166, 0, 0, 0,142, - 157, 0, 0, 0, 0, 0, 0, 0,155, 0, 98, 0, 0,163, 0, 0, -- 226, 0, 0, 0, 0, 0, 0, 0, 0,255, 96, 0, 0, 0,143, 0, -+ -+ 226, 0, 0, 0, 0, 0, 0, 0, -+ 0,ATKBD_KEY_NULL, 96, 0, 0, 0,143, 0, -+ - 0, 0, 0, 0, 0, 0, 0, 0, 0,107, 0,105,102, 0, 0,112, - 110,111,108,112,106,103, 0,119, 0,118,109, 0, 99,104,119, 0, - -@@ -150,19 +169,6 @@ static unsigned char atkbd_unxlate_table - #define ATKBD_RET_HANGEUL 0xf2 - #define ATKBD_RET_ERR 0xff - --#define ATKBD_KEY_UNKNOWN 0 --#define ATKBD_KEY_NULL 255 -- --#define ATKBD_SCR_1 254 --#define ATKBD_SCR_2 253 --#define ATKBD_SCR_4 252 --#define ATKBD_SCR_8 251 --#define ATKBD_SCR_CLICK 250 --#define ATKBD_SCR_LEFT 249 --#define ATKBD_SCR_RIGHT 248 -- --#define ATKBD_SPECIAL 248 -- - #define ATKBD_LED_EVENT_BIT 0 - #define ATKBD_REP_EVENT_BIT 1 - -@@ -174,7 +180,7 @@ static unsigned char atkbd_unxlate_table - #define ATKBD_XL_HANJA 0x20 - - static struct { -- unsigned char keycode; -+ unsigned int keycode; - unsigned char set2; - } atkbd_scroll_keys[] = { - { ATKBD_SCR_1, 0xc5 }, -@@ -200,7 +206,7 @@ struct atkbd { - char phys[32]; - - unsigned short id; -- unsigned char keycode[512]; -+ unsigned int keycode[512]; - unsigned char set; - unsigned char translated; - unsigned char extra; -@@ -351,7 +357,7 @@ static irqreturn_t atkbd_interrupt(struc - unsigned int code = data; - int scroll = 0, hscroll = 0, click = -1, add_release_event = 0; - int value; -- unsigned char keycode; -+ unsigned int keycode; - - #ifdef ATKBD_DEBUG - printk(KERN_DEBUG "atkbd.c: Received %02x flags %02x\n", data, flags); -@@ -856,9 +862,11 @@ static void atkbd_set_keycode_table(stru - atkbd->keycode[i | 0x80] = atkbd_scroll_keys[j].keycode; - } - } else if (atkbd->set == 3) { -- memcpy(atkbd->keycode, atkbd_set3_keycode, sizeof(atkbd->keycode)); -+ for (i = 0; i < ARRAY_SIZE(atkbd_set3_keycode); i++) -+ atkbd->keycode[i] = atkbd_set3_keycode[i]; - } else { -- memcpy(atkbd->keycode, atkbd_set2_keycode, sizeof(atkbd->keycode)); -+ for (i = 0; i < ARRAY_SIZE(atkbd_set2_keycode); i++) -+ atkbd->keycode[i] = atkbd_set2_keycode[i]; - - if (atkbd->scroll) - for (i = 0; i < ARRAY_SIZE(atkbd_scroll_keys); i++) -@@ -930,8 +938,8 @@ static void atkbd_set_device_attrs(struc - } - - input_dev->keycode = atkbd->keycode; -- input_dev->keycodesize = sizeof(unsigned char); -- input_dev->keycodemax = ARRAY_SIZE(atkbd_set2_keycode); -+ input_dev->keycodesize = sizeof(unsigned int); -+ input_dev->keycodemax = ARRAY_SIZE(atkbd->keycode); - - for (i = 0; i < 512; i++) - if (atkbd->keycode[i] && atkbd->keycode[i] < ATKBD_SPECIAL) -@@ -1022,6 +1030,10 @@ static int atkbd_connect(struct serio *s - return err; - } - -+#ifdef CONFIG_OLPC -+#include -+#endif -+ - /* - * atkbd_reconnect() tries to restore keyboard into a sane state and is - * most likely called on resume. -@@ -1032,6 +1044,12 @@ static int atkbd_reconnect(struct serio - struct atkbd *atkbd = serio_get_drvdata(serio); - struct serio_driver *drv = serio->drv; - -+#ifdef CONFIG_OLPC -+ if (olpc_board_at_least(olpc_board_pre(0xb3))) -+ if (serio->dev.power.power_state.event != PM_EVENT_ON) -+ return 0; -+#endif -+ - if (!atkbd || !drv) { - printk(KERN_DEBUG "atkbd: reconnect request, but serio is disconnected, ignoring...\n"); - return -1; -Index: linux-2.6.24.7/drivers/input/mouse/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/drivers/input/mouse/Kconfig -+++ linux-2.6.24.7/drivers/input/mouse/Kconfig -@@ -96,6 +96,16 @@ config MOUSE_PS2_TOUCHKIT - - If unsure, say N. - -+config MOUSE_PS2_OLPC -+ bool "OLPC PS/2 mouse protocol extension" if EMBEDDED -+ default n -+ depends on MOUSE_PS2 && OLPC -+ ---help--- -+ Say Y here if you have an OLPC PS/2 touchpad connected to -+ your system. -+ -+ If unsure, say N. -+ - config MOUSE_SERIAL - tristate "Serial mouse" - select SERIO -Index: linux-2.6.24.7/drivers/input/mouse/Makefile -=================================================================== ---- linux-2.6.24.7.orig/drivers/input/mouse/Makefile -+++ linux-2.6.24.7/drivers/input/mouse/Makefile -@@ -24,3 +24,4 @@ psmouse-$(CONFIG_MOUSE_PS2_LOGIPS2PP) += - psmouse-$(CONFIG_MOUSE_PS2_LIFEBOOK) += lifebook.o - psmouse-$(CONFIG_MOUSE_PS2_TRACKPOINT) += trackpoint.o - psmouse-$(CONFIG_MOUSE_PS2_TOUCHKIT) += touchkit_ps2.o -+psmouse-$(CONFIG_MOUSE_PS2_OLPC) += olpc.o -Index: linux-2.6.24.7/drivers/input/mouse/olpc.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/input/mouse/olpc.c -@@ -0,0 +1,837 @@ -+/* -+ * OLPC touchpad PS/2 mouse driver -+ * -+ * Copyright (c) 2006-2008 One Laptop Per Child -+ * Authors: -+ * Zephaniah E. Hull -+ * Andres Salomon -+ * -+ * This driver is partly based on the ALPS driver, which is: -+ * -+ * Copyright (c) 2003 Neil Brown -+ * Copyright (c) 2003-2005 Peter Osterlund -+ * Copyright (c) 2004 Dmitry Torokhov -+ * Copyright (c) 2005 Vojtech Pavlik -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * The touchpad on the OLPC is fairly wide, with the entire area usable -+ * as a tablet (Pen Tablet/PT), and the center 1/3rd also usable as a -+ * touchpad (Glide Sensor/GS). The spec from ALPS is available from -+ * . It refers to this -+ * device as HGPK (Hybrid GS, PT, and Keymatrix). -+ * -+ * Earlier version of the device had simultaneous reporting; however, that -+ * was removed. Instead, the device now reports packets in one mode, and -+ * tells the driver when a mode switch needs to happen. -+ */ -+ -+#define DEBUG -+#include -+#include -+#include -+#include -+#include -+ -+#include "psmouse.h" -+#include "olpc.h" -+ -+static int tpdebug; -+module_param(tpdebug, int, 0644); -+ -+static int ignore_delta = 60; -+module_param(ignore_delta, int, 0644); -+MODULE_PARM_DESC(ignore_delta, "ignore packets that cause an X or Y delta larger than this value."); -+ -+/* -+ * With older hardware, a finger-up event is sometimes not sent. If it's been -+ * more than 50mS since the last packet, we can safely assume that there was -+ * a finger-up event that we never received. -+ */ -+static void hgpk_fingerup_hack(struct psmouse *psmouse, struct hgpk_packet *p) -+{ -+ struct hgpk_data *priv = psmouse->private; -+ struct timeval now_tv; -+ s64 now_ns; -+ -+ if (psmouse->model >= HGPK_MODEL_C) -+ return; -+ -+ if (p->gs_down || p->pt_down) { -+ do_gettimeofday(&now_tv); -+ now_ns = timeval_to_ns(&now_tv); -+ -+ if (priv->late && now_ns >= priv->late) { -+ struct input_dev *pt = psmouse->dev; -+ struct input_dev *gs = priv->gs; -+ -+ input_report_key(pt, BTN_TOUCH, 0); -+ input_report_key(gs, BTN_TOUCH, 0); -+ input_sync(pt); -+ input_sync(gs); -+ hgpk_dbg(psmouse, "Missing finger-up packet detected, " -+ "working around buggy hardware.\n"); -+ } -+ priv->late = now_ns + (50 * NSEC_PER_MSEC); -+ } else -+ priv->late = 0; -+} -+ -+/* -+ * C and D series touchpads send an extra finger-up packet to ensure we've -+ * seen it. That's all well and good, but for some uncomprehensible reason -+ * they sometimes also get stuck in a state where they also send an -+ * extra finger-down packet with coordinates of x=0, y=0. This royally -+ * screws relative positioning; end users see it as the touchpad jumping -+ * around when they first put their finger down. This works around that. -+ * -+ * *Sigh*. ALPS.. -+ */ -+static void hgpk_fingerdown_hack(struct psmouse *psmouse, struct hgpk_packet *p) -+{ -+ if (psmouse->model < HGPK_MODEL_C) -+ return; -+ -+ /* we only care about x=0, y=0 packets */ -+ if (p->x != 0 || p->y != 0) -+ return; -+ -+ /* -+ * if we're a gs_down packet but we were not previously down, -+ * we're going to assume that this is one of those spurious packets -+ * that needs to be worked around. -+ */ -+ if (p->gs_down && !test_bit(BTN_TOUCH, p->dev->key)) { -+ hgpk_dbg(psmouse, "spurious GS finger-down packet\n"); -+ p->gs_down = 0; -+ } else if (p->pt_down && !test_bit(BTN_TOUCH, p->dev->key)) { -+ hgpk_dbg(psmouse, "spurious PT finger-down packet\n"); -+ p->pt_down = 0; -+ } -+} -+ -+/* -+ * In general, we have lots of calibration problems that manifest -+ * themselves as jumpy mouse pointers. Miscalibration, capacitance issues -+ * with the hardware, etc; these make the touchpad detect errant packets -+ * at random places all over the place. Since we don't expect large deltas -+ * to ever actually be useful, we'll large axis changes that go over our -+ * threshold. -+ */ -+static void hgpk_big_delta_hack(struct psmouse *psmouse, struct hgpk_packet *p) -+{ -+ struct hgpk_data *priv = psmouse->private; -+ struct input_dev *dev = p->dev; -+ -+ /* afaik, this happens on all hardware */ -+ -+ /* ignore finger-up packets */ -+ if (!p->pt_down && !p->gs_down) -+ goto done; -+ -+ /* ensure that we're not a finger-down packet */ -+ if ((p->pt_down && !test_bit(BTN_TOUCH, dev->key)) || -+ (p->gs_down && !test_bit(BTN_TOUCH, dev->key))) -+ goto done; -+ -+ if (abs(dev->abs[ABS_X] - p->x) > ignore_delta || -+ abs(dev->abs[ABS_Y] - p->y) > ignore_delta) { -+ hgpk_dbg(psmouse, "axis change (%d,%d) => (%d,%d) is over " -+ "delta threshold\n", dev->abs[ABS_X], -+ dev->abs[ABS_Y], p->x, p->y); -+ input_report_key(dev, BTN_TOUCH, 0); -+ input_sync(dev); -+ -+ -+ /* two in a row is a pretty good indicator of miscalibration */ -+ if (priv->axis_errors++) { -+ /* wait 2s for finger removal, and then recalibrate */ -+ queue_delayed_work(kpsmoused_wq, &priv->recalib_wq, -+ msecs_to_jiffies(2000)); -+ priv->axis_errors = 0; -+ } -+ return; -+ } -+done: -+ priv->axis_errors = 0; -+} -+ -+/* -+ * This is my favorite touchpad hardware bug. I'm entirely not sure what -+ * triggers it (I've seen it triggered while the laptop was left on overnight, -+ * but my cat could have very well been using it/sleeping on it). However, -+ * the touchpad will randomly get stuck in a state where it constantly spews -+ * packets without a finger being on it. A recalibration will fix it, but -+ * without that it will go on for days (auto-recalibration doesn't catch it, -+ * either). The packets tend to either have the same coordinates, or be -+ * 1px away from each other; ie, (283,139,6) -> (284,139,5) -> (285,139,5) -> -+ * (286,139,6) -> (286,139,6) -> etc. We have a number of workarounds here.. -+ */ -+static void hgpk_spewing_hack(struct psmouse *psmouse, struct hgpk_packet *p) -+{ -+ struct hgpk_data *priv = psmouse->private; -+ struct input_dev *dev = p->dev; -+ int repeat_axes; -+ -+ if (psmouse->model < HGPK_MODEL_C) -+ return; -+ -+ /* ignore 0, 0 packets */ -+ if (p->x == 0 && p->y == 0) -+ return; -+ -+ /* PT packets don't count */ -+ if (p->pt_down) { -+ priv->repeat_pkts = 0; -+ return; -+ } -+ -+ /* -+ * If we see 2s+ worth of packets that have at least 2 axis deltas of -+ * only 1px, that's a good indication that we're spewing packets. -+ * We're going to ignore z=15, though; that's pretty indicative of -+ * an actual finger on the touchpad just staying still. -+ */ -+ if (p->z == 0 || p->z == 15) -+ goto next_hack; -+ repeat_axes = abs(p->x - dev->abs[ABS_X]) < 2 ? 1 : 0; -+ repeat_axes += abs(p->y - dev->abs[ABS_Y]) < 2 ? 1 : 0; -+ repeat_axes += abs(p->z - dev->abs[ABS_PRESSURE]) < 2 ? 1 : 0; -+ if (repeat_axes > 1) { -+ priv->repeat_pkts++; -+ /* we get 1 packet about every 24mS */ -+ if (priv->repeat_pkts > 83) { -+ queue_delayed_work(kpsmoused_wq, &priv->recalib_wq, 0); -+ priv->repeat_pkts = 0; -+ } -+ } -+ else -+ priv->repeat_pkts = 0; -+ return; -+ -+next_hack: -+ /* -+ * 10s of y and z not changing is another kind of miscalibration. -+ */ -+ repeat_axes = (p->y == dev->abs[ABS_Y]) ? 1 : 0; -+ repeat_axes += (p->z == dev->abs[ABS_PRESSURE]) ? 1 : 0; -+ if (repeat_axes > 1) { -+ priv->repeat_pkts++; -+ if (priv->repeat_pkts > 416) { -+ queue_delayed_work(kpsmoused_wq, &priv->recalib_wq, 0); -+ priv->repeat_pkts = 0; -+ } -+ } -+ else -+ priv->repeat_pkts = 0; -+} -+ -+/* -+ * HGPK Advanced Mode - single-mode format -+ * -+ * byte 0(PT): 1 1 0 0 1 1 1 1 -+ * byte 0(GS): 1 1 1 1 1 1 1 1 -+ * byte 1: 0 x6 x5 x4 x3 x2 x1 x0 -+ * byte 2(PT): 0 0 x9 x8 x7 ? pt-dsw 0 -+ * byte 2(GS): 0 x10 x9 x8 x7 ? gs-dsw pt-dsw -+ * byte 3: 0 y9 y8 y7 1 0 swr swl -+ * byte 4: 0 y6 y5 y4 y3 y2 y1 y0 -+ * byte 5: 0 z6 z5 z4 z3 z2 z1 z0 -+ * -+ * ?'s are not defined in the protocol spec, may vary between models. -+ * -+ * swr/swl are the left/right buttons. -+ * -+ * pt-dsw/gs-dsw indicate that the pt/gs sensor is detecting a -+ * pen/finger -+ */ -+ -+static int hgpk_validate_byte(unsigned char *packet, int pktcnt) -+{ -+ BUG_ON(pktcnt < 1); -+ -+ if (packet[0] != HGPK_PT && packet[0] != HGPK_GS) -+ return -1; -+ -+ /* bytes 2 - 6 should have 0 in the highest bit */ -+ if (pktcnt >= 2 && pktcnt <= 6 && (packet[pktcnt - 1] & 0x80)) -+ return -1; -+ -+ return 0; -+} -+ -+static void hgpk_decode_packet(struct psmouse *psmouse, struct hgpk_packet *p) -+{ -+ unsigned char *packet = psmouse->packet; -+ -+ BUG_ON(psmouse->pktcnt < 6); -+ -+ p->left = packet[3] & 1; -+ p->right = !!(packet[3] & 2); -+ p->x = packet[1] | ((packet[2] & 0x78) << 4); -+ p->y = packet[4] | ((packet[3] & 0x70) << 3); -+ p->z = packet[5]; -+ -+ if (packet[0] == HGPK_GS) { -+ p->pt_down = !!(packet[2] & 1); -+ p->gs_down = !!(packet[2] & 2); -+ p->dev = ((struct hgpk_data *) psmouse->private)->gs; -+ if (p->pt_down) { -+ /* we miss spurious PT finger-downs if pt_down is set */ -+ p->mode_switch = HGPK_PT; -+ p->pt_down = 0; -+ } else { -+ p->mode_switch = 0; -+ } -+ } else if (packet[0] == HGPK_PT) { -+ p->pt_down = !!(packet[2] & 2); -+ p->gs_down = 0; -+ p->dev = psmouse->dev; -+ p->mode_switch = !p->pt_down ? HGPK_GS : 0; -+ } -+ -+ if (tpdebug) { -+ hgpk_dbg(psmouse, "l=%d r=%d p=%d g=%d x=%d y=%d z=%d m=%x\n", -+ p->left, p->right, p->pt_down, p->gs_down, -+ p->x, p->y, p->z, p->mode_switch); -+ } -+} -+ -+static void hgpk_process_packet_gspt(struct psmouse *psmouse) -+{ -+ struct hgpk_data *priv = psmouse->private; -+ struct input_dev *pt = psmouse->dev; -+ struct input_dev *gs = priv->gs; -+ struct hgpk_packet pkt; -+ -+ hgpk_decode_packet(psmouse, &pkt); -+ -+ hgpk_fingerup_hack(psmouse, &pkt); -+ hgpk_fingerdown_hack(psmouse, &pkt); -+ hgpk_big_delta_hack(psmouse, &pkt); -+ hgpk_spewing_hack(psmouse, &pkt); -+ -+ input_report_key(pt, BTN_LEFT, pkt.left); -+ input_report_key(pt, BTN_RIGHT, pkt.right); -+ input_report_key(pt, BTN_TOUCH, pkt.pt_down); -+ -+ input_report_key(gs, BTN_LEFT, pkt.left); -+ input_report_key(gs, BTN_RIGHT, pkt.right); -+ input_report_key(gs, BTN_TOUCH, pkt.gs_down); -+ -+ input_report_abs(pkt.dev, ABS_X, pkt.x); -+ input_report_abs(pkt.dev, ABS_Y, pkt.y); -+ input_report_abs(pkt.dev, ABS_PRESSURE, pkt.z); -+ -+ input_sync(pt); -+ input_sync(gs); -+ -+ if (priv->recalib_window) { -+ if (time_before(jiffies, priv->recalib_window)) { -+ /* -+ * ugh, got a packet inside our recalibration -+ * window, schedule another recalibration. -+ */ -+ hgpk_dbg(psmouse, "packet inside calibration window, " -+ "queueing another recalibration\n"); -+ queue_delayed_work(kpsmoused_wq, &priv->recalib_wq, -+ msecs_to_jiffies(1000)); -+ } -+ priv->recalib_window = 0; -+ } -+ -+ if (psmouse->model != HGPK_MODEL_A) { -+ if (priv->pending_mode && (!pkt.mode_switch || -+ priv->current_mode == pkt.mode_switch)) { -+ priv->pending_mode = 0; -+ cancel_delayed_work(&priv->switch_wq); -+ } -+ else if (priv->pending_mode != pkt.mode_switch) { -+ priv->pending_mode = pkt.mode_switch; -+ -+ /* allow for spurious mode_switch packets by delaying */ -+ queue_delayed_work(kpsmoused_wq, &priv->switch_wq, -+ msecs_to_jiffies(50)); -+ } -+ } -+} -+ -+static psmouse_ret_t hgpk_process_byte(struct psmouse *psmouse) -+{ -+ if (hgpk_validate_byte(psmouse->packet, psmouse->pktcnt)) { -+ hgpk_dbg(psmouse, "%s: (%d) %02x %02x %02x %02x %02x %02x\n", -+ __func__, psmouse->pktcnt, psmouse->packet[0], -+ psmouse->packet[1], psmouse->packet[2], -+ psmouse->packet[3], psmouse->packet[4], -+ psmouse->packet[5]); -+ return PSMOUSE_BAD_DATA; -+ } -+ -+ if (psmouse->pktcnt == 6) { -+ hgpk_process_packet_gspt(psmouse); -+ return PSMOUSE_FULL_PACKET; -+ } -+ -+ return PSMOUSE_GOOD_DATA; -+} -+ -+static int hgpk_force_recalibrate(struct psmouse *psmouse) -+{ -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ struct hgpk_data *priv = psmouse->private; -+ struct input_dev *pt = psmouse->dev; -+ struct input_dev *gs = priv->gs; -+ -+ /* C-series touchpads added the recalibrate command */ -+ if (psmouse->model < HGPK_MODEL_C) -+ return 0; -+ -+ if (ps2_command(ps2dev, NULL, 0xf5) || -+ ps2_command(ps2dev, NULL, 0xf5) || -+ ps2_command(ps2dev, NULL, 0xe6) || -+ ps2_command(ps2dev, NULL, 0xf5)) -+ return -1; -+ -+ /* send a finger-up event so the cursor doesn't jump around */ -+ input_report_key(pt, BTN_TOUCH, 0); -+ input_report_key(gs, BTN_TOUCH, 0); -+ input_sync(pt); -+ input_sync(gs); -+ -+ /* according to ALPS, 150mS is required for recalibration */ -+ msleep(150); -+ -+ /* -+ * XXX: If a finger is down during this delay, recalibration will -+ * detect capacitance incorrectly. This is a hardware bug, and -+ * we may need to work around that here. -+ */ -+ -+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_ENABLE)) -+ return -1; -+ -+ /* -+ * After we recalibrate, we shouldn't get any packets for 2s. If -+ * we do, it's likely that someone's finger was on the touchpad. -+ * If someone's finger *was* on the touchpad, it's probably -+ * miscalibrated. So, we should schedule another recalibration -+ */ -+ priv->recalib_window = jiffies + msecs_to_jiffies(2000); -+ -+ return 0; -+} -+ -+static enum hgpk_model_t hgpk_get_model(struct psmouse *psmouse) -+{ -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ unsigned char param[3]; -+ -+ /* E7, E7, E7, E9 gets us a 3 byte identifier */ -+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21) || -+ ps2_command(ps2dev, param, PSMOUSE_CMD_GETINFO)) -+ return -EIO; -+ -+ hgpk_dbg(psmouse, "ID: %02x %02x %02x", param[0], param[1], param[2]); -+ -+ /* HGPK signature: 0x67, 0x00, 0x */ -+ if (param[0] != 0x67 || param[1] != 0x00) -+ return -ENODEV; -+ -+ hgpk_info(psmouse, "OLPC touchpad revision 0x%x\n", param[2]); -+ return param[2]; -+} -+ -+/* -+ * Touchpad should be disabled before calling this! -+ */ -+static int hgpk_new_mode(struct psmouse *psmouse, int mode) -+{ -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ struct hgpk_data *priv = psmouse->private; -+ -+ /* -+ * PT mode: F2, F2, F2, E7 -+ * GS mode: F2, F2, F2, E6 -+ */ -+ if (ps2_command(ps2dev, NULL, 0xF2) || -+ ps2_command(ps2dev, NULL, 0xF2) || -+ ps2_command(ps2dev, NULL, 0xF2)) -+ return -EIO; -+ -+ if (mode == HGPK_GS) { -+ if (ps2_command(ps2dev, NULL, 0xE6)) -+ return -EIO; -+ } else { -+ if (ps2_command(ps2dev, NULL, 0xE7)) -+ return -EIO; -+ } -+ -+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_ENABLE)) -+ return -EIO; -+ -+ /* tell the irq handler to stop ignoring packets */ -+ psmouse_set_state(psmouse, PSMOUSE_ACTIVATED); -+ -+ priv->current_mode = mode; -+ priv->pending_mode = 0; -+ if (tpdebug) -+ hgpk_warn(psmouse, "Switched to mode 0x%x successful.\n", mode); -+ -+ return 0; -+} -+ -+static int hgpk_advanced_mode(struct psmouse *psmouse) -+{ -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ -+ /* Switch to 'Advanced mode.', four disables in a row. */ -+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE)) -+ return -1; -+ -+ return hgpk_new_mode(psmouse, HGPK_GS); -+} -+ -+/* -+ * This kills power to the touchpad; according to ALPS, current consumption -+ * goes down to 50uA after running this. To turn power back on, we drive -+ * MS-DAT low. -+ */ -+static int hgpk_toggle_power(struct psmouse *psmouse, int enable) -+{ -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ int timeo; -+ -+ /* Added on D-series touchpads */ -+ if (psmouse->model < HGPK_MODEL_D) -+ return 0; -+ -+ if (enable) { -+ psmouse_set_state(psmouse, PSMOUSE_INITIALIZING); -+ -+ /* -+ * Sending a byte will drive MS-DAT low; this will wake up -+ * the controller. Once we get an ACK back from it, it -+ * means we can continue with the touchpad re-init. ALPS -+ * tells us that 1s should be long enough, so set that as -+ * the upper bound. -+ */ -+ for (timeo = 20; timeo > 0; timeo--) { -+ if (!ps2_sendbyte(&psmouse->ps2dev, -+ PSMOUSE_CMD_DISABLE, 20)) -+ break; -+ msleep(50); -+ } -+ -+ psmouse_reset(psmouse); -+ -+ if (hgpk_advanced_mode(psmouse)) { -+ hgpk_err(psmouse, "Failed to reinit touchpad!\n"); -+ return -1; -+ } -+ } else { -+ hgpk_dbg(psmouse, "Powering off touchpad.\n"); -+ psmouse_set_state(psmouse, PSMOUSE_IGNORE); -+ -+ if (ps2_command(ps2dev, NULL, 0xec) || -+ ps2_command(ps2dev, NULL, 0xec) || -+ ps2_command(ps2dev, NULL, 0xea)) -+ return -1; -+ /* probably won't see an ACK, the touchpad will be off */ -+ ps2_sendbyte(&psmouse->ps2dev, 0xec, 20); -+ } -+ -+ return 0; -+} -+ -+/* -+ * poll the touchpad for current motion packet. -+ * Used in resync. -+ * Note: We can't poll, so always return failure. -+ */ -+static int hgpk_poll(struct psmouse *psmouse) -+{ -+ return -1; -+} -+ -+static int hgpk_reconnect(struct psmouse *psmouse) -+{ -+ if (olpc_board_at_least(olpc_board(0xb2))) -+ if (psmouse->ps2dev.serio->dev.power.power_state.event != PM_EVENT_ON) -+ return 0; -+ -+ psmouse_reset(psmouse); -+ -+ if (hgpk_advanced_mode(psmouse)) { -+ hgpk_err(psmouse, "failed to reenable advanced mode.\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static ssize_t hgpk_show_powered(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct serio *serio = to_serio_port(dev); -+ struct psmouse *psmouse; -+ struct hgpk_data *priv; -+ int retval; -+ -+ retval = serio_pin_driver(serio); -+ if (retval) -+ return retval; -+ -+ psmouse = serio_get_drvdata(serio); -+ priv = psmouse->private; -+ -+ retval = sprintf(buf, "%d\n", priv->powered); -+ serio_unpin_driver(serio); -+ return retval; -+} -+ -+static ssize_t hgpk_set_powered(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct serio *serio = to_serio_port(dev); -+ struct psmouse *psmouse; -+ struct hgpk_data *priv; -+ unsigned long val; -+ int retval; -+ -+ if (*buf == '1') -+ val = 1; -+ else if (*buf == '0') -+ val = 0; -+ else -+ return -EINVAL; -+ -+ retval = serio_pin_driver(serio); -+ if (retval) -+ return retval; -+ -+/* -+ * FUCK IT. I don't fucking care. locking in psmouse is fucking retarded! -+ retval = mutex_lock_interruptible(&psmouse_mutex); -+ if (retval) -+ goto out_unpin; -+*/ -+ -+ psmouse = serio_get_drvdata(serio); -+ priv = psmouse->private; -+ -+ if (val == priv->powered) -+ goto done; -+ -+ retval = hgpk_toggle_power(psmouse, val); -+ if (!retval) -+ priv->powered = val; -+ -+done: -+ serio_unpin_driver(serio); -+ return retval ? retval : count; -+} -+ -+static DEVICE_ATTR(powered, S_IWUSR | S_IRUGO, hgpk_show_powered, -+ hgpk_set_powered); -+ -+static void hgpk_disconnect(struct psmouse *psmouse) -+{ -+ struct hgpk_data *priv = psmouse->private; -+ -+ device_remove_file(&psmouse->ps2dev.serio->dev, &dev_attr_powered); -+ psmouse_reset(psmouse); -+ flush_scheduled_work(); -+ input_unregister_device(priv->gs); -+ kfree(priv); -+} -+ -+static void hgpk_mode_switch(struct work_struct *work) -+{ -+ struct delayed_work *w = container_of(work, struct delayed_work, work); -+ struct hgpk_data *priv = container_of(w, struct hgpk_data, switch_wq); -+ struct psmouse *psmouse = priv->psmouse; -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ int pending_mode; -+ -+ if (tpdebug) -+ hgpk_dbg(psmouse, "Starting mode switch to 0x%x. [%lu]\n", -+ priv->pending_mode, jiffies); -+ -+ if (priv->pending_mode == priv->current_mode) { -+ priv->pending_mode = 0; -+ hgpk_dbg(psmouse, "Already in target mode, no-op.\n"); -+ return; -+ } -+ -+ /* tell the irq handler to ignore any further packets */ -+ psmouse_set_state(psmouse, PSMOUSE_INITIALIZING); -+ priv->late = 0; -+ -+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE)) -+ goto bad; -+ -+ /* -+ * ALPS tells us that it may take up to 20msec for the disable to -+ * take effect; however, ps2_command() will wait up to 200msec for -+ * the ACK to come back (and I'm assuming that by the time the -+ * hardware sends back its ACK, it has stopped sending bytes). -+ */ -+ pending_mode = priv->pending_mode; -+ -+ if (hgpk_new_mode(psmouse, priv->pending_mode)) -+ goto bad; -+ -+ /* -+ * Deal with a potential race condition. -+ * -+ * If there is a brief tap of a stylus or a fingernail that -+ * triggers a mode switch to PT mode, and the stylus/fingernail is -+ * lifted after the DISABLE above, but before we reenable in the -+ * new mode then we can get stuck in PT mode. -+ */ -+ if (pending_mode == HGPK_PT) { -+ priv->pending_mode = HGPK_GS; -+ queue_delayed_work(kpsmoused_wq, &priv->switch_wq, -+ msecs_to_jiffies(50)); -+ } -+ -+ return; -+bad: -+ hgpk_warn(psmouse, "Failure to switch modes, resetting device...\n"); -+ hgpk_reconnect(psmouse); -+} -+ -+static void hgpk_recalib_work(struct work_struct *work) -+{ -+ struct delayed_work *w = container_of(work, struct delayed_work, work); -+ struct hgpk_data *priv = container_of(w, struct hgpk_data, recalib_wq); -+ struct psmouse *psmouse = priv->psmouse; -+ -+ if (tpdebug) -+ hgpk_dbg(psmouse, "Recalibrating touchpad..\n"); -+ -+ if (hgpk_force_recalibrate(psmouse)) -+ hgpk_err(psmouse, "Recalibration failed!\n"); -+} -+ -+int olpc_init(struct psmouse *psmouse) -+{ -+ struct hgpk_data *priv; -+ struct input_dev *pt = psmouse->dev; -+ struct input_dev *gs; -+ -+ priv = kzalloc(sizeof(struct hgpk_data), GFP_KERNEL); -+ gs = input_allocate_device(); -+ if (!priv || !gs) -+ goto init_fail; -+ -+ psmouse->private = priv; -+ priv->gs = gs; -+ priv->psmouse = psmouse; -+ priv->powered = 1; -+ -+ psmouse_reset(psmouse); -+ -+ if (hgpk_advanced_mode(psmouse)) { -+ hgpk_err(psmouse, "failed to enable advanced mode\n"); -+ goto init_fail; -+ } -+ -+ /* Unset things that psmouse-base sets that we don't have */ -+ pt->evbit[0] &= ~BIT(EV_REL); -+ pt->keybit[LONG(BTN_MOUSE)] &= ~BIT(BTN_MIDDLE); -+ pt->relbit[0] &= ~(BIT(REL_X) | BIT(REL_Y)); -+ -+ /* Set all the things we *do* have */ -+ set_bit(EV_KEY, pt->evbit); -+ set_bit(EV_ABS, pt->evbit); -+ -+ set_bit(BTN_LEFT, pt->keybit); -+ set_bit(BTN_RIGHT, pt->keybit); -+ set_bit(BTN_TOUCH, pt->keybit); -+ -+ input_set_abs_params(pt, ABS_X, 2, 1000, 0, 0); -+ input_set_abs_params(pt, ABS_Y, 0, 717, 0, 0); -+ input_set_abs_params(pt, ABS_PRESSURE, 0, 127, 0, 0); -+ -+ snprintf(priv->phys, sizeof(priv->phys), -+ "%s/input1", psmouse->ps2dev.serio->phys); -+ gs->phys = priv->phys; -+ gs->name = "OLPC ALPS GlideSensor"; -+ gs->id.bustype = BUS_I8042; -+ gs->id.vendor = 0x0002; -+ gs->id.product = PSMOUSE_OLPC; -+ gs->id.version = psmouse->model; -+ -+ set_bit(EV_KEY, gs->evbit); -+ set_bit(EV_ABS, gs->evbit); -+ -+ set_bit(BTN_LEFT, gs->keybit); -+ set_bit(BTN_RIGHT, gs->keybit); -+ set_bit(BTN_TOUCH, gs->keybit); -+ -+ input_set_abs_params(gs, ABS_X, 350, 512, 0, 0); -+ input_set_abs_params(gs, ABS_Y, 70, 325, 0, 0); -+ input_set_abs_params(gs, ABS_PRESSURE, 0, 15, 0, 0); -+ -+ if (input_register_device(gs)) { -+ hgpk_err(psmouse, "Failed to register GlideSensor\n"); -+ goto init_fail; -+ } -+ -+ psmouse->protocol_handler = hgpk_process_byte; -+ psmouse->poll = hgpk_poll; -+ psmouse->disconnect = hgpk_disconnect; -+ psmouse->reconnect = hgpk_reconnect; -+ psmouse->pktsize = 6; -+ -+ /* Disable the idle resync. */ -+ psmouse->resync_time = 0; -+ /* Reset after a lot of bad bytes. */ -+ psmouse->resetafter = 1024; -+ -+ INIT_DELAYED_WORK(&priv->switch_wq, hgpk_mode_switch); -+ INIT_DELAYED_WORK(&priv->recalib_wq, hgpk_recalib_work); -+ -+ if (device_create_file(&psmouse->ps2dev.serio->dev, -+ &dev_attr_powered)) { -+ hgpk_err(psmouse, "Failed to create sysfs attribute\n"); -+ goto attr_fail; -+ } -+ -+ -+ return 0; -+ -+attr_fail: -+ input_unregister_device(gs); -+ gs = NULL; -+init_fail: -+ input_free_device(gs); -+ kfree(priv); -+ return -1; -+} -+ -+int olpc_detect(struct psmouse *psmouse, int set_properties) -+{ -+ int version; -+ -+ version = hgpk_get_model(psmouse); -+ if (version < 0) -+ return version; -+ -+ if (set_properties) { -+ psmouse->vendor = "ALPS"; -+ psmouse->name = "PenTablet"; -+ psmouse->model = version; -+ } -+ return 0; -+} -Index: linux-2.6.24.7/drivers/input/mouse/olpc.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/input/mouse/olpc.h -@@ -0,0 +1,78 @@ -+/* -+ * OLPC touchpad PS/2 mouse driver -+ * -+ * Copyright (c) 2006 One Laptop Per Child, inc. -+ * -+ * This driver is partly based on the ALPS driver. -+ * Copyright (c) 2003 Peter Osterlund -+ * Copyright (c) 2005 Vojtech Pavlik -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ */ -+ -+#ifndef _OLPC_H -+#define _OLPC_H -+ -+enum hgpk_model_t { -+ HGPK_MODEL_PreA = 0x0a, /* pre-B1s */ -+ HGPK_MODEL_A = 0x14, /* found on B1s, PT disabled in hardware */ -+ HGPK_MODEL_B = 0x28, /* B2s, has capacitance issues */ -+ HGPK_MODEL_C = 0x3c, -+ HGPK_MODEL_D = 0x50, /* C1, mass production */ -+}; -+ -+#define HGPK_GS 0xff /* The GlideSensor */ -+#define HGPK_PT 0xcf /* The PenTablet */ -+ -+struct hgpk_packet { -+ struct input_dev *dev; -+ int x, y, z; -+ unsigned char mode_switch; -+ unsigned int pt_down:1, gs_down:1; -+ unsigned int left:1, right:1; -+}; -+ -+struct hgpk_data { -+ struct input_dev *gs; /* GlideSensor */ -+ struct psmouse *psmouse; -+ char name[32]; /* Name */ -+ char phys[32]; /* Phys */ -+ int pending_mode; -+ int current_mode; -+ s64 late; -+ int axis_errors; -+ int repeat_pkts; -+ int powered; -+ unsigned long recalib_window; -+ struct delayed_work switch_wq; -+ struct delayed_work recalib_wq; -+}; -+ -+#define hgpk_dbg(psmouse, format, arg...) \ -+ dev_dbg(&(psmouse)->ps2dev.serio->dev, format, ## arg) -+#define hgpk_err(psmouse, format, arg...) \ -+ dev_err(&(psmouse)->ps2dev.serio->dev, format, ## arg) -+#define hgpk_info(psmouse, format, arg...) \ -+ dev_info(&(psmouse)->ps2dev.serio->dev, format, ## arg) -+#define hgpk_warn(psmouse, format, arg...) \ -+ dev_warn(&(psmouse)->ps2dev.serio->dev, format, ## arg) -+#define hgpk_notice(psmouse, format, arg...) \ -+ dev_notice(&(psmouse)->ps2dev.serio->dev, format, ## arg) -+ -+#ifdef CONFIG_MOUSE_PS2_OLPC -+int olpc_detect(struct psmouse *psmouse, int set_properties); -+int olpc_init(struct psmouse *psmouse); -+#else -+inline int olpc_detect(struct psmouse *psmouse, int set_properties) -+{ -+ return -ENOSYS; -+} -+inline int olpc_init(struct psmouse *psmouse) -+{ -+ return -ENOSYS; -+} -+#endif -+ -+#endif -Index: linux-2.6.24.7/drivers/input/mouse/psmouse-base.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/input/mouse/psmouse-base.c -+++ linux-2.6.24.7/drivers/input/mouse/psmouse-base.c -@@ -26,6 +26,7 @@ - #include "synaptics.h" - #include "logips2pp.h" - #include "alps.h" -+#include "olpc.h" - #include "lifebook.h" - #include "trackpoint.h" - #include "touchkit_ps2.h" -@@ -103,7 +104,7 @@ static struct attribute_group psmouse_at - */ - static DEFINE_MUTEX(psmouse_mutex); - --static struct workqueue_struct *kpsmoused_wq; -+struct workqueue_struct *kpsmoused_wq; - - struct psmouse_protocol { - enum psmouse_type type; -@@ -221,7 +222,7 @@ static inline void __psmouse_set_state(s - * is not a concern. - */ - --static void psmouse_set_state(struct psmouse *psmouse, enum psmouse_state new_state) -+void psmouse_set_state(struct psmouse *psmouse, enum psmouse_state new_state) - { - serio_pause_rx(psmouse->ps2dev.serio); - __psmouse_set_state(psmouse, new_state); -@@ -320,7 +321,7 @@ static irqreturn_t psmouse_interrupt(str - goto out; - } - -- if (psmouse->packet[1] == PSMOUSE_RET_ID) { -+ if (psmouse->packet[1] == PSMOUSE_RET_ID || psmouse->packet[1] == PSMOUSE_RET_BAT) { - __psmouse_set_state(psmouse, PSMOUSE_IGNORE); - serio_reconnect(serio); - goto out; -@@ -631,8 +632,21 @@ static int psmouse_extensions(struct psm - } - } - -+/* -+ * Try OLPC touchpad. -+ */ - if (max_proto > PSMOUSE_IMEX) { -+ if (olpc_detect(psmouse, set_properties) == 0) { -+ if (!set_properties || olpc_init(psmouse) == 0) -+ return PSMOUSE_OLPC; -+/* -+ * Init failed, try basic relative protocols -+ */ -+ max_proto = PSMOUSE_IMEX; -+ } -+ } - -+ if (max_proto > PSMOUSE_IMEX) { - if (genius_detect(psmouse, set_properties) == 0) - return PSMOUSE_GENPS; - -@@ -763,6 +777,14 @@ static const struct psmouse_protocol psm - .detect = touchkit_ps2_detect, - }, - #endif -+#ifdef CONFIG_MOUSE_PS2_OLPC -+ { -+ .type = PSMOUSE_OLPC, -+ .name = "OLPC", -+ .alias = "olpc", -+ .detect = olpc_detect, -+ }, -+#endif - { - .type = PSMOUSE_CORTRON, - .name = "CortronPS/2", -Index: linux-2.6.24.7/drivers/input/mouse/psmouse.h -=================================================================== ---- linux-2.6.24.7.orig/drivers/input/mouse/psmouse.h -+++ linux-2.6.24.7/drivers/input/mouse/psmouse.h -@@ -88,6 +88,7 @@ enum psmouse_type { - PSMOUSE_LIFEBOOK, - PSMOUSE_TRACKPOINT, - PSMOUSE_TOUCHKIT_PS2, -+ PSMOUSE_OLPC, - PSMOUSE_CORTRON, - PSMOUSE_AUTO /* This one should always be last */ - }; -@@ -95,7 +96,9 @@ enum psmouse_type { - int psmouse_sliced_command(struct psmouse *psmouse, unsigned char command); - int psmouse_reset(struct psmouse *psmouse); - void psmouse_set_resolution(struct psmouse *psmouse, unsigned int resolution); -+void psmouse_set_state(struct psmouse *psmouse, enum psmouse_state new_state); - -+extern struct workqueue_struct *kpsmoused_wq; - - struct psmouse_attribute { - struct device_attribute dattr; -Index: linux-2.6.24.7/drivers/input/serio/i8042.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/input/serio/i8042.c -+++ linux-2.6.24.7/drivers/input/serio/i8042.c -@@ -874,6 +874,11 @@ static long i8042_panic_blink(long count - #undef DELAY - - #ifdef CONFIG_PM -+ -+#ifdef CONFIG_OLPC -+#include -+#endif -+ - /* - * Here we try to restore the original BIOS settings. We only want to - * do that once, when we really suspend, not when we taking memory -@@ -884,8 +889,15 @@ static long i8042_panic_blink(long count - static int i8042_suspend(struct platform_device *dev, pm_message_t state) - { - if (dev->dev.power.power_state.event != state.event) { -+#ifdef CONFIG_OLPC -+ /* Anything newer than B2 remains powered; no reset needed */ -+ if (!olpc_board_at_least(olpc_board_pre(0xb3))) { -+#endif - if (state.event == PM_EVENT_SUSPEND) - i8042_controller_reset(); -+#ifdef CONFIG_OLPC -+ } -+#endif - - dev->dev.power.power_state = state; - } -@@ -908,9 +920,15 @@ static int i8042_resume(struct platform_ - if (dev->dev.power.power_state.event == PM_EVENT_ON) - return 0; - -+#ifdef CONFIG_OLPC -+ if (!olpc_board_at_least(olpc_board_pre(0xb3))) { -+#endif - error = i8042_controller_check(); - if (error) - return error; -+#ifdef CONFIG_OLPC -+ } -+#endif - - error = i8042_controller_selftest(); - if (error) -Index: linux-2.6.24.7/drivers/input/serio/serio.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/input/serio/serio.c -+++ linux-2.6.24.7/drivers/input/serio/serio.c -@@ -910,11 +910,22 @@ static int serio_uevent(struct device *d - #endif /* CONFIG_HOTPLUG */ - - #ifdef CONFIG_PM -+ -+#ifdef CONFIG_OLPC -+#include -+#endif -+ - static int serio_suspend(struct device *dev, pm_message_t state) - { - if (dev->power.power_state.event != state.event) { -+#ifdef CONFIG_OLPC -+ if (!olpc_board_at_least(olpc_board_pre(0xb3))) { -+#endif - if (state.event == PM_EVENT_SUSPEND) - serio_cleanup(to_serio_port(dev)); -+#ifdef CONFIG_OLPC -+ } -+#endif - - dev->power.power_state = state; - } -Index: linux-2.6.24.7/drivers/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/drivers/Kconfig -+++ linux-2.6.24.7/drivers/Kconfig -@@ -94,6 +94,8 @@ source "drivers/auxdisplay/Kconfig" - - source "drivers/kvm/Kconfig" - -+source "drivers/sysprof/Kconfig" -+ - source "drivers/uio/Kconfig" - - source "drivers/virtio/Kconfig" -Index: linux-2.6.24.7/drivers/Makefile -=================================================================== ---- linux-2.6.24.7.orig/drivers/Makefile -+++ linux-2.6.24.7/drivers/Makefile -@@ -23,6 +23,8 @@ obj-y += char/ - - obj-$(CONFIG_CONNECTOR) += connector/ - -+obj-$(CONFIG_SYSPROF) += sysprof/ -+ - # i810fb and intelfb depend on char/agp/ - obj-$(CONFIG_FB_I810) += video/i810/ - obj-$(CONFIG_FB_INTEL) += video/intelfb/ -Index: linux-2.6.24.7/drivers/media/video/cafe_ccic.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/media/video/cafe_ccic.c -+++ linux-2.6.24.7/drivers/media/video/cafe_ccic.c -@@ -372,6 +372,10 @@ static int cafe_smbus_write_data(struct - rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR); - cafe_reg_write(cam, REG_TWSIC1, rval); - spin_unlock_irqrestore(&cam->dev_lock, flags); -+ mdelay(2); /* It'll probably take about 900µs anyway, and the -+ CAFÉ is apparently quite sensitive to being poked -+ at this point. If we can work out precisely what's -+ going on and reduce this delay, it would be nice. */ - - /* - * Time to wait for the write to complete. THIS IS A RACY -@@ -907,8 +911,6 @@ static int cafe_cam_configure(struct caf - struct v4l2_format fmt; - int ret, zero = 0; - -- if (cam->state != S_IDLE) -- return -EINVAL; - fmt.fmt.pix = cam->pix_format; - ret = __cafe_cam_cmd(cam, VIDIOC_INT_INIT, &zero); - if (ret == 0) -@@ -2237,14 +2239,18 @@ static int cafe_pci_suspend(struct pci_d - int ret; - enum cafe_state cstate; - -+ mutex_lock(&cam->s_mutex); - ret = pci_save_state(pdev); -- if (ret) -+ if (ret) { -+ cam_warn(cam, "Unable to save PCI state\n"); - return ret; -+ } - cstate = cam->state; /* HACK - stop_dma sets to idle */ - cafe_ctlr_stop_dma(cam); - cafe_ctlr_power_down(cam); - pci_disable_device(pdev); - cam->state = cstate; -+ /* hold mutex until restore */ - return 0; - } - -@@ -2263,16 +2269,18 @@ static int cafe_pci_resume(struct pci_de - cam_warn(cam, "Unable to re-enable device on resume!\n"); - return ret; - } -+ /* we're still holding mutex from suspend */ - cafe_ctlr_init(cam); - cafe_ctlr_power_down(cam); - -- mutex_lock(&cam->s_mutex); -- if (cam->users > 0) { -- cafe_ctlr_power_up(cam); -- __cafe_cam_reset(cam); -- } -- mutex_unlock(&cam->s_mutex); -- -+ if (cam->users > 0) { -+ cafe_ctlr_power_up(cam); -+ __cafe_cam_reset(cam); -+ } -+ else -+ cafe_ctlr_power_down(cam); -+ mutex_unlock(&cam->s_mutex); -+ - set_bit(CF_CONFIG_NEEDED, &cam->flags); - if (cam->state == S_SPECREAD) - cam->state = S_IDLE; /* Don't bother restarting */ -Index: linux-2.6.24.7/drivers/misc/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/drivers/misc/Kconfig -+++ linux-2.6.24.7/drivers/misc/Kconfig -@@ -219,6 +219,11 @@ config THINKPAD_ACPI_BAY - - If you are not sure, say Y here. - -+config EEPROM_93CX6 -+ tristate "EEPROM 93CX6 support" -+ ---help--- -+ This is a driver for the EEPROM chipsets 93c46 and 93c66. -+ The driver supports both read as well as write commands. - - config ATMEL_SSC - tristate "Device driver for Atmel SSC peripheral" -Index: linux-2.6.24.7/drivers/mmc/card/block.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/mmc/card/block.c -+++ linux-2.6.24.7/drivers/mmc/card/block.c -@@ -237,6 +237,13 @@ static int mmc_blk_issue_rq(struct mmc_q - if (brq.data.blocks > card->host->max_blk_count) - brq.data.blocks = card->host->max_blk_count; - -+ if (mmc_card_sd(card) && !card->host->ios.clock) { -+ printk(KERN_ERR "%s: I/O to stopped card\n", -+ req->rq_disk->disk_name); -+ goto cmd_err; -+ } -+ mmc_set_data_timeout(&brq.data, card); -+ - /* - * If the host doesn't support multiple block writes, force - * block writes to single block. SD cards are excepted from -Index: linux-2.6.24.7/drivers/mmc/host/sdhci.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/mmc/host/sdhci.c -+++ linux-2.6.24.7/drivers/mmc/host/sdhci.c -@@ -441,6 +441,12 @@ static void sdhci_prepare_data(struct sd - break; - } - -+ /* -+ * There's an off-by-one error in the hw that we need to -+ * compensate for. -+ */ -+ count++; -+ - if (count >= 0xF) { - printk(KERN_WARNING "%s: Too large timeout requested!\n", - mmc_hostname(host->mmc)); -@@ -728,19 +734,17 @@ static void sdhci_set_power(struct sdhci - if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) - writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); - -- pwr = SDHCI_POWER_ON; -- - switch (1 << power) { - case MMC_VDD_165_195: -- pwr |= SDHCI_POWER_180; -+ pwr = SDHCI_POWER_180; - break; - case MMC_VDD_29_30: - case MMC_VDD_30_31: -- pwr |= SDHCI_POWER_300; -+ pwr = SDHCI_POWER_300; - break; - case MMC_VDD_32_33: - case MMC_VDD_33_34: -- pwr |= SDHCI_POWER_330; -+ pwr = SDHCI_POWER_330; - break; - default: - BUG(); -@@ -748,6 +752,10 @@ static void sdhci_set_power(struct sdhci - - writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); - -+ pwr |= SDHCI_POWER_ON; -+ -+ writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); -+ - out: - host->power = power; - } -Index: linux-2.6.24.7/drivers/mtd/nand/cafe_nand.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/mtd/nand/cafe_nand.c -+++ linux-2.6.24.7/drivers/mtd/nand/cafe_nand.c -@@ -11,6 +11,7 @@ - #undef DEBUG - #include - #include -+#include - #include - #include - #include -@@ -52,6 +53,7 @@ - - struct cafe_priv { - struct nand_chip nand; -+ struct mtd_partition *parts; - struct pci_dev *pdev; - void __iomem *mmio; - struct rs_control *rs; -@@ -84,6 +86,10 @@ static unsigned int numtimings; - static int timing[3]; - module_param_array(timing, int, &numtimings, 0644); - -+#ifdef CONFIG_MTD_PARTITIONS -+static const char *part_probes[] = { "RedBoot", NULL }; -+#endif -+ - /* Hrm. Why isn't this already conditional on something in the struct device? */ - #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) - -@@ -620,7 +626,9 @@ static int __devinit cafe_nand_probe(str - { - struct mtd_info *mtd; - struct cafe_priv *cafe; -+ struct mtd_partition *parts; - uint32_t ctrl; -+ int nr_parts; - int err = 0; - - /* Very old versions shared the same PCI ident for all three -@@ -787,7 +795,18 @@ static int __devinit cafe_nand_probe(str - goto out_irq; - - pci_set_drvdata(pdev, mtd); -+ -+ /* We register the whole device first, separate from the partitions */ - add_mtd_device(mtd); -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ nr_parts = parse_mtd_partitions(mtd, part_probes, &parts, 0); -+ if (nr_parts > 0) { -+ cafe->parts = parts; -+ dev_info(&cafe->pdev->dev, "%d RedBoot partitions found\n", nr_parts); -+ add_mtd_partitions(mtd, parts, nr_parts); -+ } -+#endif - goto out; - - out_irq: -Index: linux-2.6.24.7/drivers/mtd/redboot.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/mtd/redboot.c -+++ linux-2.6.24.7/drivers/mtd/redboot.c -@@ -59,16 +59,31 @@ static int parse_redboot_partitions(stru - static char nullstring[] = "unallocated"; - #endif - -+ if ( directory < 0 ) { -+ offset = master->size + directory * master->erasesize; -+ while (master->block_isbad && -+ master->block_isbad(master, offset)) { -+ if (!offset) { -+ nogood: -+ printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ return -EIO; -+ } -+ offset -= master->erasesize; -+ } -+ } else { -+ offset = directory * master->erasesize; -+ while (master->block_isbad && -+ master->block_isbad(master, offset)) { -+ offset += master->erasesize; -+ if (offset == master->size) -+ goto nogood; -+ } -+ } - buf = vmalloc(master->erasesize); - - if (!buf) - return -ENOMEM; - -- if ( directory < 0 ) -- offset = master->size + directory*master->erasesize; -- else -- offset = directory*master->erasesize; -- - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); - -Index: linux-2.6.24.7/drivers/net/forcedeth.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/net/forcedeth.c -+++ linux-2.6.24.7/drivers/net/forcedeth.c -@@ -3559,11 +3559,13 @@ static int nv_request_irq(struct net_dev - } - if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { - if ((ret = pci_enable_msi(np->pci_dev)) == 0) { -+ pci_intx(np->pci_dev, 0); - np->msi_flags |= NV_MSI_ENABLED; - dev->irq = np->pci_dev->irq; - if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { - printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); - pci_disable_msi(np->pci_dev); -+ pci_intx(np->pci_dev, 1); - np->msi_flags &= ~NV_MSI_ENABLED; - dev->irq = np->pci_dev->irq; - goto out_err; -@@ -3606,6 +3608,7 @@ static void nv_free_irq(struct net_devic - free_irq(np->pci_dev->irq, dev); - if (np->msi_flags & NV_MSI_ENABLED) { - pci_disable_msi(np->pci_dev); -+ pci_intx(np->pci_dev, 1); - np->msi_flags &= ~NV_MSI_ENABLED; - } - } -Index: linux-2.6.24.7/drivers/pci/quirks.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/pci/quirks.c -+++ linux-2.6.24.7/drivers/pci/quirks.c -@@ -1360,6 +1360,17 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); - - /* -+ * According to Tom Sylla, the Geode does not support PCI power management -+ * transition, so we shouldn't need the D3hot delay. -+ */ -+static void __init quirk_geode_pci_pm(struct pci_dev *dev) -+{ -+ pci_pm_d3_delay = 0; -+} -+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, quirk_geode_pci_pm); -+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_geode_pci_pm); -+ -+/* - * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size - * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. - * Re-allocate the region if needed... -Index: linux-2.6.24.7/drivers/power/ds2760_battery.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/power/ds2760_battery.c -+++ linux-2.6.24.7/drivers/power/ds2760_battery.c -@@ -409,6 +409,7 @@ static int ds2760_battery_suspend(struct - struct ds2760_device_info *di = platform_get_drvdata(pdev); - - di->charge_status = POWER_SUPPLY_STATUS_UNKNOWN; -+ power_supply_changed(&di->bat); - - return 0; - } -Index: linux-2.6.24.7/drivers/power/olpc_battery.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/power/olpc_battery.c -+++ linux-2.6.24.7/drivers/power/olpc_battery.c -@@ -14,12 +14,13 @@ - #include - #include - #include -+#include - #include - - - #define EC_BAT_VOLTAGE 0x10 /* uint16_t, *9.76/32, mV */ - #define EC_BAT_CURRENT 0x11 /* int16_t, *15.625/120, mA */ --#define EC_BAT_ACR 0x12 -+#define EC_BAT_ACR 0x12 /* int16_t *416.667 µAh */ - #define EC_BAT_TEMP 0x13 /* uint16_t, *100/256, °C */ - #define EC_AMB_TEMP 0x14 /* uint16_t, *100/256, °C */ - #define EC_BAT_STATUS 0x15 /* uint8_t, bitmask */ -@@ -84,6 +85,8 @@ static struct power_supply olpc_ac = { - .get_property = olpc_ac_get_prop, - }; - -+static char bat_serial[17]; /* Ick */ -+ - /********************************************************************* - * Battery properties - *********************************************************************/ -@@ -94,6 +97,7 @@ static int olpc_bat_get_property(struct - int ret = 0; - int16_t ec_word; - uint8_t ec_byte; -+ uint64_t ser_buf; - - ret = olpc_ec_cmd(EC_BAT_STATUS, NULL, 0, &ec_byte, 1); - if (ret) -@@ -127,8 +131,8 @@ static int olpc_bat_get_property(struct - val->intval = POWER_SUPPLY_STATUS_FULL; - else /* Not _necessarily_ true but EC doesn't tell all yet */ - val->intval = POWER_SUPPLY_STATUS_CHARGING; -- break; - } -+ break; - case POWER_SUPPLY_PROP_PRESENT: - val->intval = !!(ec_byte & BAT_STAT_PRESENT); - break; -@@ -249,6 +253,22 @@ static int olpc_bat_get_property(struct - ec_word = be16_to_cpu(ec_word); - val->intval = ec_word * 100 / 256; - break; -+ case POWER_SUPPLY_PROP_ACCUM_CURRENT: -+ ret = olpc_ec_cmd(EC_BAT_ACR, NULL, 0, (void *)&ec_word, 2); -+ if (ret) -+ return ret; -+ -+ ec_word = be16_to_cpu(ec_word); -+ val->intval = (uint16_t)ec_word; -+ break; -+ case POWER_SUPPLY_PROP_SERIAL_NUMBER: -+ ret = olpc_ec_cmd(EC_BAT_SERIAL, NULL, 0, (void *)&ser_buf, 8); -+ if (ret) -+ return ret; -+ -+ sprintf(bat_serial, "%016llx", (long long)be64_to_cpu(ser_buf)); -+ val->strval = bat_serial; -+ break; - default: - ret = -EINVAL; - break; -@@ -268,7 +288,51 @@ static enum power_supply_property olpc_b - POWER_SUPPLY_PROP_CAPACITY_LEVEL, - POWER_SUPPLY_PROP_TEMP, - POWER_SUPPLY_PROP_TEMP_AMBIENT, -+ POWER_SUPPLY_PROP_ACCUM_CURRENT, - POWER_SUPPLY_PROP_MANUFACTURER, -+ POWER_SUPPLY_PROP_SERIAL_NUMBER, -+}; -+ -+/* EEPROM reading goes completely around the power_supply API, sadly */ -+ -+#define EEPROM_START 0x20 -+#define EEPROM_END 0x80 -+#define EEPROM_SIZE (EEPROM_END - EEPROM_START) -+ -+static ssize_t olpc_bat_eeprom_read(struct kobject *kobj, char *buf, loff_t off, -+ size_t count) -+{ -+ uint8_t ec_byte; -+ int ret, end; -+ -+ if (off >= EEPROM_SIZE) -+ return 0; -+ if (off + count > EEPROM_SIZE) -+ count = EEPROM_SIZE - off; -+ -+ end = EEPROM_START + off + count; -+ for (ec_byte = EEPROM_START + off; ec_byte < end; ec_byte++) { -+ ret = olpc_ec_cmd(EC_BAT_EEPROM, &ec_byte, 1, -+ &buf[ec_byte - EEPROM_START], 1); -+ if (ret) { -+ printk(KERN_ERR "olpc-battery: EC command " -+ "EC_BAT_EEPROM @ 0x%x failed -" -+ " %d!\n", ec_byte, ret); -+ return -EIO; -+ } -+ } -+ -+ return count; -+} -+ -+static struct bin_attribute olpc_bat_eeprom = { -+ .attr = { -+ .name = "eeprom", -+ .mode = S_IRUGO, -+ .owner = THIS_MODULE, -+ }, -+ .size = 0, -+ .read = olpc_bat_eeprom_read, - }; - - /********************************************************************* -@@ -299,7 +363,7 @@ static int __init olpc_bat_init(void) - - if (!olpc_platform_info.ecver) - return -ENXIO; -- if (olpc_platform_info.ecver < 0x43) { -+ if (olpc_platform_info.ecver < 0x44) { - printk(KERN_NOTICE "OLPC EC version 0x%02x too old for battery driver.\n", olpc_platform_info.ecver); - return -ENXIO; - } -@@ -324,9 +388,15 @@ static int __init olpc_bat_init(void) - if (ret) - goto battery_failed; - -+ ret = device_create_bin_file(olpc_bat.dev, &olpc_bat_eeprom); -+ if (ret) -+ goto eeprom_failed; -+ - olpc_register_battery_callback(&olpc_battery_trigger_uevent); - goto success; - -+eeprom_failed: -+ power_supply_unregister(&olpc_bat); - battery_failed: - power_supply_unregister(&olpc_ac); - ac_failed: -@@ -338,6 +408,7 @@ success: - static void __exit olpc_bat_exit(void) - { - olpc_deregister_battery_callback(); -+ device_remove_bin_file(olpc_bat.dev, &olpc_bat_eeprom); - power_supply_unregister(&olpc_bat); - power_supply_unregister(&olpc_ac); - platform_device_unregister(bat_pdev); -Index: linux-2.6.24.7/drivers/power/power_supply_sysfs.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/power/power_supply_sysfs.c -+++ linux-2.6.24.7/drivers/power/power_supply_sysfs.c -@@ -114,9 +114,11 @@ static struct device_attribute power_sup - POWER_SUPPLY_ATTR(time_to_empty_avg), - POWER_SUPPLY_ATTR(time_to_full_now), - POWER_SUPPLY_ATTR(time_to_full_avg), -+ POWER_SUPPLY_ATTR(accum_current), - /* Properties of type `const char *' */ - POWER_SUPPLY_ATTR(model_name), - POWER_SUPPLY_ATTR(manufacturer), -+ POWER_SUPPLY_ATTR(serial_number), - }; - - static ssize_t power_supply_show_static_attrs(struct device *dev, -Index: linux-2.6.24.7/drivers/serial/serial_core.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/serial/serial_core.c -+++ linux-2.6.24.7/drivers/serial/serial_core.c -@@ -2013,6 +2013,7 @@ int uart_suspend_port(struct uart_driver - int uart_resume_port(struct uart_driver *drv, struct uart_port *port) - { - struct uart_state *state = drv->state + port->line; -+ struct ktermios termios; - - mutex_lock(&state->mutex); - -@@ -2035,20 +2036,6 @@ int uart_resume_port(struct uart_driver - * Re-enable the console device after suspending. - */ - if (uart_console(port)) { -- struct ktermios termios; -- -- /* -- * First try to use the console cflag setting. -- */ -- memset(&termios, 0, sizeof(struct ktermios)); -- termios.c_cflag = port->cons->cflag; -- -- /* -- * If that's unset, use the tty termios setting. -- */ -- if (state->info && state->info->tty && termios.c_cflag == 0) -- termios = *state->info->tty->termios; -- - port->ops->set_termios(port, &termios, NULL); - console_start(port->cons); - } -Index: linux-2.6.24.7/drivers/sysprof/config.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/sysprof/config.h -@@ -0,0 +1,23 @@ -+/* config.h. Generated by configure. */ -+/* config.h.in. Generated from configure.ac by autoheader. */ -+ -+/* Look for global separate debug info in this path */ -+#define DEBUGDIR "/usr/local/lib/debug" -+ -+/* Define to 1 if you have the `iberty' library (-liberty). */ -+/* #undef HAVE_LIBIBERTY */ -+ -+/* Define to the address where bug reports for this package should be sent. */ -+#define PACKAGE_BUGREPORT "" -+ -+/* Define to the full name of this package. */ -+#define PACKAGE_NAME "sysprof" -+ -+/* Define to the full name and version of this package. */ -+#define PACKAGE_STRING "sysprof 1.0.8" -+ -+/* Define to the one symbol short name of this package. */ -+#define PACKAGE_TARNAME "sysprof" -+ -+/* Define to the version of this package. */ -+#define PACKAGE_VERSION "1.0.8" -Index: linux-2.6.24.7/drivers/sysprof/Kconfig -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/sysprof/Kconfig -@@ -0,0 +1,12 @@ -+ -+menu "Sysprof" -+ -+config SYSPROF -+ tristate "Sysprof support" -+ help -+ Say M here to include the sysprof-module. -+ -+ Sysprof is a sampling profiler that uses a kernel module, -+ sysprof-module, to generate stacktraces which are then interpreted by -+ the userspace program "sysprof". -+endmenu -Index: linux-2.6.24.7/drivers/sysprof/Makefile -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/sysprof/Makefile -@@ -0,0 +1 @@ -+obj-$(CONFIG_SYSPROF) += sysprof-module.o -Index: linux-2.6.24.7/drivers/sysprof/sysprof-module.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/sysprof/sysprof-module.c -@@ -0,0 +1,271 @@ -+/* -*- c-basic-offset: 8 -*- */ -+ -+/* Sysprof -- Sampling, systemwide CPU profiler -+ * Copyright 2004, Red Hat, Inc. -+ * Copyright 2004, 2005, Soeren Sandmann -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#ifdef CONFIG_SMP -+# define __SMP__ -+#endif -+#include -+#include /* Needed for KERN_ALERT */ -+#include /* Needed by all modules */ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "sysprof-module.h" -+ -+#include "config.h" -+ -+#include -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+#include -+#endif -+ -+#if !CONFIG_PROFILING -+# error Sysprof needs a kernel with profiling support compiled in. -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+# error Sysprof needs a Linux 2.6.11 kernel or later -+#endif -+#include -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Soeren Sandmann (sandmann@daimi.au.dk)"); -+ -+#define SAMPLES_PER_SECOND (200) -+#define INTERVAL ((HZ <= SAMPLES_PER_SECOND)? 1 : (HZ / SAMPLES_PER_SECOND)) -+#define N_TRACES 256 -+ -+static SysprofStackTrace stack_traces[N_TRACES]; -+static SysprofStackTrace * head = &stack_traces[0]; -+static SysprofStackTrace * tail = &stack_traces[0]; -+DECLARE_WAIT_QUEUE_HEAD (wait_for_trace); -+DECLARE_WAIT_QUEUE_HEAD (wait_for_exit); -+ -+/* Macro the names of the registers that are used on each architecture */ -+#if defined(CONFIG_X86_64) -+# define REG_FRAME_PTR rbp -+# define REG_INS_PTR rip -+# define REG_STACK_PTR rsp -+#elif defined(CONFIG_X86) -+# define REG_FRAME_PTR ebp -+# define REG_INS_PTR eip -+# define REG_STACK_PTR esp -+#else -+# error Sysprof only supports the i386 and x86-64 architectures -+#endif -+ -+typedef struct userspace_reader userspace_reader; -+struct userspace_reader -+{ -+ struct task_struct *task; -+ unsigned long cache_address; -+ unsigned long *cache; -+}; -+ -+typedef struct StackFrame StackFrame; -+struct StackFrame { -+ unsigned long next; -+ unsigned long return_address; -+}; -+ -+struct work_struct work; -+ -+static int -+read_frame (void *frame_pointer, StackFrame *frame) -+{ -+#if 0 -+ /* This is commented out because we seem to be called with -+ * (current_thread_info()->addr_limit.seg)) == 0 -+ * which means access_ok() _always_ fails. -+ * -+ * Not sure why (or if) this isn't the case for oprofile -+ */ -+ if (!access_ok(VERIFY_READ, frame_pointer, sizeof(StackFrame))) -+ return 1; -+#endif -+ -+ if (__copy_from_user_inatomic ( -+ frame, frame_pointer, sizeof (StackFrame))) -+ return 1; -+ -+ return 0; -+} -+ -+DEFINE_PER_CPU(int, n_samples); -+ -+static int -+timer_notify (struct pt_regs *regs) -+{ -+ SysprofStackTrace *trace = head; -+ int i; -+ int is_user; -+ static atomic_t in_timer_notify = ATOMIC_INIT(1); -+ int n; -+ -+ n = ++get_cpu_var(n_samples); -+ put_cpu_var(n_samples); -+ -+ if (n % INTERVAL != 0) -+ return 0; -+ -+ /* 0: locked, 1: unlocked */ -+ -+ if (!atomic_dec_and_test(&in_timer_notify)) -+ goto out; -+ -+ is_user = user_mode(regs); -+ -+ if (!current || current->pid == 0) -+ goto out; -+ -+ if (is_user && current->state != TASK_RUNNING) -+ goto out; -+ -+ if (!is_user) -+ { -+ /* kernel */ -+ -+ trace->pid = current->pid; -+ trace->truncated = 0; -+ trace->n_addresses = 1; -+ -+ /* 0x1 is taken by sysprof to mean "in kernel" */ -+ trace->addresses[0] = (void *)0x1; -+ } -+ else -+ { -+ StackFrame *frame_pointer; -+ StackFrame frame; -+ memset(trace, 0, sizeof (SysprofStackTrace)); -+ -+ trace->pid = current->pid; -+ trace->truncated = 0; -+ -+ i = 0; -+ -+ trace->addresses[i++] = (void *)regs->REG_INS_PTR; -+ -+ frame_pointer = (void *)regs->REG_FRAME_PTR; -+ -+ while (read_frame (frame_pointer, &frame) == 0 && -+ i < SYSPROF_MAX_ADDRESSES && -+ (unsigned long)frame_pointer >= regs->REG_STACK_PTR) -+ { -+ trace->addresses[i++] = (void *)frame.return_address; -+ frame_pointer = (StackFrame *)frame.next; -+ } -+ -+ trace->n_addresses = i; -+ -+ if (i == SYSPROF_MAX_ADDRESSES) -+ trace->truncated = 1; -+ else -+ trace->truncated = 0; -+ } -+ -+ if (head++ == &stack_traces[N_TRACES - 1]) -+ head = &stack_traces[0]; -+ -+ wake_up (&wait_for_trace); -+ -+out: -+ atomic_inc(&in_timer_notify); -+ return 0; -+} -+ -+static int -+procfile_read(char *buffer, -+ char **buffer_location, -+ off_t offset, -+ int buffer_len, -+ int *eof, -+ void *data) -+{ -+ if (head == tail) -+ return -EWOULDBLOCK; -+ -+ *buffer_location = (char *)tail; -+ -+ BUG_ON(tail->pid == 0); -+ -+ if (tail++ == &stack_traces[N_TRACES - 1]) -+ tail = &stack_traces[0]; -+ -+ return sizeof (SysprofStackTrace); -+} -+ -+struct proc_dir_entry *trace_proc_file; -+static unsigned int -+procfile_poll(struct file *filp, poll_table *poll_table) -+{ -+ if (head != tail) -+ return POLLIN | POLLRDNORM; -+ -+ poll_wait(filp, &wait_for_trace, poll_table); -+ -+ if (head != tail) -+ return POLLIN | POLLRDNORM; -+ -+ return 0; -+} -+ -+int -+init_module(void) -+{ -+ static struct file_operations fops; -+ -+ trace_proc_file = -+ create_proc_entry ("sysprof-trace", S_IFREG | S_IRUGO, &proc_root); -+ -+ if (!trace_proc_file) -+ return 1; -+ -+ fops = *trace_proc_file->proc_fops; -+ fops.poll = procfile_poll; -+ -+ trace_proc_file->read_proc = procfile_read; -+ trace_proc_file->proc_fops = &fops; -+ trace_proc_file->size = sizeof (SysprofStackTrace); -+ -+ register_timer_hook (timer_notify); -+ -+ printk(KERN_ALERT "sysprof: loaded (%s)\n", PACKAGE_VERSION); -+ -+ return 0; -+} -+ -+void -+cleanup_module(void) -+{ -+ unregister_timer_hook (timer_notify); -+ -+ remove_proc_entry("sysprof-trace", &proc_root); -+ -+ printk(KERN_ALERT "sysprof: unloaded\n"); -+} -+ -Index: linux-2.6.24.7/drivers/sysprof/sysprof-module.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/sysprof/sysprof-module.h -@@ -0,0 +1,37 @@ -+/* Sysprof -- Sampling, systemwide CPU profiler -+ * Copyright 2004, Red Hat, Inc. -+ * Copyright 2004, 2005, Soeren Sandmann -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#ifndef SYSPROF_MODULE_H -+#define SYSPROF_MODULE_H -+ -+typedef struct SysprofStackTrace SysprofStackTrace; -+ -+#define SYSPROF_MAX_ADDRESSES 512 -+ -+struct SysprofStackTrace -+{ -+ int pid; /* -1 if in kernel */ -+ int truncated; -+ int n_addresses; /* note: this can be 1 if the process was compiled -+ * with -fomit-frame-pointer or is otherwise weird -+ */ -+ void *addresses[SYSPROF_MAX_ADDRESSES]; -+}; -+ -+#endif -Index: linux-2.6.24.7/drivers/usb/core/driver.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/usb/core/driver.c -+++ linux-2.6.24.7/drivers/usb/core/driver.c -@@ -1062,8 +1062,15 @@ static int usb_suspend_both(struct usb_d - break; - } - } -- if (status == 0) -+ if (status == 0) { -+ -+ /* Non-root devices don't need to do anything for FREEZE -+ * or PRETHAW. */ -+ if (udev->parent && (msg.event == PM_EVENT_FREEZE || -+ msg.event == PM_EVENT_PRETHAW)) -+ goto done; - status = usb_suspend_device(udev, msg); -+ } - - /* If the suspend failed, resume interfaces that did get suspended */ - if (status != 0) { -Index: linux-2.6.24.7/drivers/usb/core/quirks.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/usb/core/quirks.c -+++ linux-2.6.24.7/drivers/usb/core/quirks.c -@@ -48,6 +48,9 @@ static const struct usb_device_id usb_qu - /* SKYMEDI USB_DRIVE */ - { USB_DEVICE(0x1516, 0x8628), .driver_info = USB_QUIRK_RESET_RESUME }, - -+ /* Philips PSC805 audio device */ -+ { USB_DEVICE(0x0471, 0x0155), .driver_info = USB_QUIRK_RESET_RESUME }, -+ - { } /* terminating entry must be last */ - }; - -Index: linux-2.6.24.7/drivers/usb/core/usb.h -=================================================================== ---- linux-2.6.24.7.orig/drivers/usb/core/usb.h -+++ linux-2.6.24.7/drivers/usb/core/usb.h -@@ -41,6 +41,7 @@ extern void usb_host_cleanup(void); - extern void usb_autosuspend_work(struct work_struct *work); - extern int usb_port_suspend(struct usb_device *dev); - extern int usb_port_resume(struct usb_device *dev); -+extern int usb_reset_suspended_device(struct usb_device *udev); - extern int usb_external_suspend_device(struct usb_device *udev, - pm_message_t msg); - extern int usb_external_resume_device(struct usb_device *udev); -Index: linux-2.6.24.7/drivers/usb/host/ehci-hcd.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/usb/host/ehci-hcd.c -+++ linux-2.6.24.7/drivers/usb/host/ehci-hcd.c -@@ -653,9 +653,16 @@ static irqreturn_t ehci_irq (struct usb_ - - /* complete the unlinking of some qh [4.15.2.3] */ - if (status & STS_IAA) { -- COUNT (ehci->stats.reclaim); -- ehci->reclaim_ready = 1; -- bh = 1; -+ if (!ehci->reclaim) { -+ printk(KERN_WARNING "%s would set reclaim_ready with nothing to reclaim!\n", __func__); -+printk(KERN_DEBUG "%s: USBCMD: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->command)); -+printk(KERN_DEBUG "%s: USBSTS: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->status)); -+ WARN_ON(1); -+ } else { -+ COUNT (ehci->stats.reclaim); -+ ehci->reclaim_ready = 1; -+ bh = 1; -+ } - } - - /* remote wakeup [4.3.1] */ -Index: linux-2.6.24.7/drivers/usb/host/ehci-hub.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/usb/host/ehci-hub.c -+++ linux-2.6.24.7/drivers/usb/host/ehci-hub.c -@@ -132,10 +132,15 @@ static int ehci_bus_suspend (struct usb_ - ehci_quiesce (ehci); - hcd->state = HC_STATE_QUIESCING; - } -+printk(KERN_DEBUG "%s: USBCMD: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->command)); -+printk(KERN_DEBUG "%s: USBSTS: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->status)); -+ - ehci->command = ehci_readl(ehci, &ehci->regs->command); - if (ehci->reclaim) - ehci->reclaim_ready = 1; - ehci_work(ehci); -+printk(KERN_DEBUG "%s: USBCMD: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->command)); -+printk(KERN_DEBUG "%s: USBSTS: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->status)); - - /* Unlike other USB host controller types, EHCI doesn't have - * any notion of "global" or bus-wide suspend. The driver has -@@ -175,6 +180,9 @@ static int ehci_bus_suspend (struct usb_ - ehci_halt (ehci); - hcd->state = HC_STATE_SUSPENDED; - -+printk(KERN_DEBUG "%s: USBCMD: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->command)); -+printk(KERN_DEBUG "%s: USBSTS: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->status)); -+ - /* allow remote wakeup */ - mask = INTR_MASK; - if (!device_may_wakeup(&hcd->self.root_hub->dev)) -@@ -195,6 +203,18 @@ static int ehci_bus_resume (struct usb_h - u32 temp; - u32 power_okay; - int i; -+#ifdef CONFIG_OLPC -+ u32 lo; -+ static void __iomem *usb_ehc_addr; -+ -+ rdmsrl(0x51200009, lo); -+ usb_ehc_addr = ioremap(lo, 256); -+ writel(readl(usb_ehc_addr+0x54) | 0x1000, usb_ehc_addr+0x54); -+ writel(readl(usb_ehc_addr+0x58) | 0x1000, usb_ehc_addr+0x58); -+ writel(readl(usb_ehc_addr+0x5C) | 0x1000, usb_ehc_addr+0x5C); -+ writel(readl(usb_ehc_addr+0x60) | 0x1000, usb_ehc_addr+0x60); -+ iounmap(usb_ehc_addr); -+#endif - - if (time_before (jiffies, ehci->next_statechange)) - msleep(5); -Index: linux-2.6.24.7/drivers/usb/host/ehci-pci.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/usb/host/ehci-pci.c -+++ linux-2.6.24.7/drivers/usb/host/ehci-pci.c -@@ -247,6 +247,9 @@ static int ehci_pci_suspend(struct usb_h - rc = -EINVAL; - goto bail; - } -+printk(KERN_DEBUG "%s: USBCMD: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->command)); -+printk(KERN_DEBUG "%s: USBSTS: 0x%x\n", __func__, ehci_readl(ehci, &ehci->regs->status)); -+ - ehci_writel(ehci, 0, &ehci->regs->intr_enable); - (void)ehci_readl(ehci, &ehci->regs->intr_enable); - -Index: linux-2.6.24.7/drivers/usb/host/ehci-q.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/usb/host/ehci-q.c -+++ linux-2.6.24.7/drivers/usb/host/ehci-q.c -@@ -177,7 +177,7 @@ static int qtd_copy_status ( - if (QTD_CERR (token)) - status = -EPIPE; - else { -- ehci_dbg (ehci, "devpath %s ep%d%s 3strikes\n", -+ printk(KERN_ERR "devpath %s ep%d%s 3strikes\n", - urb->dev->devpath, - usb_pipeendpoint (urb->pipe), - usb_pipein (urb->pipe) ? "in" : "out"); -@@ -973,6 +973,11 @@ static void end_unlink_async (struct ehc - struct ehci_qh *qh = ehci->reclaim; - struct ehci_qh *next; - -+ if (!qh) { -+ printk(KERN_CRIT "%s with ehci->reclaim == NULL!\n", __func__); -+ WARN_ON(1); -+ return; -+ } - timer_action_done (ehci, TIMER_IAA_WATCHDOG); - - // qh->hw_next = cpu_to_hc32(qh->qh_dma); -Index: linux-2.6.24.7/drivers/usb/host/ohci-pci.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/usb/host/ohci-pci.c -+++ linux-2.6.24.7/drivers/usb/host/ohci-pci.c -@@ -317,6 +317,8 @@ static int ohci_pci_resume (struct usb_h - /* FIXME: we should try to detect loss of VBUS power here */ - prepare_for_handover(hcd); - -+ /* Force the PM core to resume the root hub */ -+ hcd_to_bus(hcd)->root_hub->dev.power.prev_state.event = PM_EVENT_ON; - return 0; - } - -Index: linux-2.6.24.7/drivers/usb/storage/usb.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/usb/storage/usb.c -+++ linux-2.6.24.7/drivers/usb/storage/usb.c -@@ -244,7 +244,7 @@ static int storage_pre_reset(struct usb_ - return 0; - } - --static int storage_post_reset(struct usb_interface *iface) -+static void storage_post_reset(struct usb_interface *iface, int reset_resume) - { - struct us_data *us = usb_get_intfdata(iface); - -@@ -256,8 +256,10 @@ static int storage_post_reset(struct usb - /* FIXME: Notify the subdrivers that they need to reinitialize - * the device */ - -- mutex_unlock(&us->dev_mutex); -- return 0; -+ /* If this is a reset-resume then the pre_reset routine wasn't -+ * called, so we don't need to unlock the mutex. */ -+ if (!reset_resume) -+ mutex_unlock(&us->dev_mutex); - } - - /* -Index: linux-2.6.24.7/drivers/video/fbmem.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/fbmem.c -+++ linux-2.6.24.7/drivers/video/fbmem.c -@@ -820,6 +820,53 @@ static void try_to_load(int fb) - #endif /* CONFIG_KMOD */ - - int -+fb_powerup(struct fb_info *info) -+{ -+ int ret = 0; -+ -+ if (!info || info->state == FBINFO_STATE_RUNNING) -+ return 0; -+ -+ if (info->fbops->fb_powerup) -+ ret = info->fbops->fb_powerup(info); -+ -+ if (!ret) { -+ acquire_console_sem(); -+ fb_set_suspend(info, 0); -+ release_console_sem(); -+ } -+ -+ return ret; -+} -+ -+int -+fb_powerdown(struct fb_info *info) -+{ -+ int ret = 0; -+ -+ if (!info || info->state == FBINFO_STATE_SUSPENDED) -+ return 0; -+ -+ /* Tell everybody that the fbdev is going down */ -+ acquire_console_sem(); -+ fb_set_suspend(info, 1); -+ release_console_sem(); -+ -+ if (info->fbops->fb_powerdown) -+ ret = info->fbops->fb_powerdown(info); -+ -+ /* If the power down failed, then un-notify */ -+ -+ if (ret) { -+ acquire_console_sem(); -+ fb_set_suspend(info, 0); -+ release_console_sem(); -+ } -+ -+ return ret; -+} -+ -+int - fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var) - { - struct fb_fix_screeninfo *fix = &info->fix; -Index: linux-2.6.24.7/drivers/video/geode/display_gx.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/display_gx.c -+++ linux-2.6.24.7/drivers/video/geode/display_gx.c -@@ -11,26 +11,44 @@ - * Free Software Foundation; either version 2 of the License, or * (at your - * option) any later version. - */ -+ -+#include - #include - #include - #include - #include - #include - #include -+#include - - #include "geodefb.h" - #include "display_gx.h" - --#ifdef CONFIG_FB_GEODE_GX_SET_FBSIZE --unsigned int gx_frame_buffer_size(void) -+static inline void rmwl(u32 val, u32 *reg) - { -- return CONFIG_FB_GEODE_GX_FBSIZE; -+ u32 in = readl(reg); -+ if (in != val) -+ writel(val, reg); - } --#else -+ - unsigned int gx_frame_buffer_size(void) - { - unsigned int val; - -+#ifdef CONFIG_OLPC -+ if (machine_is_olpc() && !olpc_has_vsa()) { -+ u32 hi,lo; -+ rdmsr(GLIU0_P2D_RO0, lo, hi); -+ -+ /* Top page number */ -+ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); -+ -+ val -= (lo & 0x000fffff); /* Subtract bottom page number */ -+ val += 1; /* Adjust page count */ -+ return (val << 12); -+ } -+#endif -+ - /* FB size is reported by a virtual register */ - /* Virtual register class = 0x02 */ - /* VG_MEM_SIZE(512Kb units) = 0x00 */ -@@ -41,7 +59,6 @@ unsigned int gx_frame_buffer_size(void) - val = (unsigned int)(inw(0xAC1E)) & 0xFFl; - return (val << 19); - } --#endif - - int gx_line_delta(int xres, int bpp) - { -@@ -63,23 +80,23 @@ static void gx_set_mode(struct fb_info * - gcfg = readl(par->dc_regs + DC_GENERAL_CFG); - dcfg = readl(par->dc_regs + DC_DISPLAY_CFG); - -- /* Disable the timing generator. */ -- dcfg &= ~(DC_DCFG_TGEN); -- writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); -- -- /* Wait for pending memory requests before disabling the FIFO load. */ -- udelay(100); -- -- /* Disable FIFO load and compression. */ -- gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); -- writel(gcfg, par->dc_regs + DC_GENERAL_CFG); -- -- /* Setup DCLK and its divisor. */ -- par->vid_ops->set_dclk(info); -- -- /* -- * Setup new mode. -- */ -+ /* Programming the clock is costly and ugly, so avoid if if we can */ -+ -+ if (par->curdclk != info->var.pixclock) { -+ /* Disable the timing generator. */ -+ dcfg &= ~(DC_DCFG_TGEN); -+ writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); -+ -+ /* Wait for pending memory requests before disabling the FIFO load. */ -+ udelay(100); -+ -+ /* Disable FIFO load and compression. */ -+ gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); -+ writel(gcfg, par->dc_regs + DC_GENERAL_CFG); -+ -+ /* Setup DCLK and its divisor. */ -+ par->vid_ops->set_dclk(info); -+ } - - /* Clear all unused feature bits. */ - gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE; -@@ -90,12 +107,13 @@ static void gx_set_mode(struct fb_info * - gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; - - /* Framebuffer start offset. */ -- writel(0, par->dc_regs + DC_FB_ST_OFFSET); -+ rmwl(0, par->dc_regs + DC_FB_ST_OFFSET); - - /* Line delta and line buffer length. */ -- writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH); -- writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, -- par->dc_regs + DC_LINE_SIZE); -+ rmwl(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH); -+ -+ rmwl(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, -+ par->dc_regs + DC_LINE_SIZE); - - - /* Enable graphics and video data and unmask address lines. */ -@@ -134,17 +152,16 @@ static void gx_set_mode(struct fb_info * - vblankend = vsyncend + info->var.upper_margin; - vtotal = vblankend; - -- writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING); -- writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING); -- writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING); -- -- writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING); -- writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING); -- writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING); -+ rmwl((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING); -+ rmwl((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING); -+ rmwl((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING); -+ rmwl((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING); -+ rmwl((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING); -+ rmwl((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING); - - /* Write final register values. */ -- writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); -- writel(gcfg, par->dc_regs + DC_GENERAL_CFG); -+ rmwl(dcfg, par->dc_regs + DC_DISPLAY_CFG); -+ rmwl(gcfg, par->dc_regs + DC_GENERAL_CFG); - - par->vid_ops->configure_display(info); - -Index: linux-2.6.24.7/drivers/video/geode/display_gx.h -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/display_gx.h -+++ linux-2.6.24.7/drivers/video/geode/display_gx.h -@@ -20,6 +20,9 @@ extern struct geode_dc_ops gx_dc_ops; - #define GLD_MSR_CONFIG 0xC0002001 - #define GLD_MSR_CONFIG_DM_FP 0x40 - -+/* Used for memory dection on the OLPC */ -+#define GLIU0_P2D_RO0 0x10000029 -+ - /* Display controller registers */ - - #define DC_UNLOCK 0x00 -Index: linux-2.6.24.7/drivers/video/geode/geodefb.h -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/geodefb.h -+++ linux-2.6.24.7/drivers/video/geode/geodefb.h -@@ -12,6 +12,10 @@ - #ifndef __GEODEFB_H__ - #define __GEODEFB_H__ - -+#define FB_POWER_STATE_OFF 0 -+#define FB_POWER_STATE_SUSPEND 1 -+#define FB_POWER_STATE_ON 2 -+ - struct geodefb_info; - - struct geode_dc_ops { -@@ -21,18 +25,24 @@ struct geode_dc_ops { - - struct geode_vid_ops { - void (*set_dclk)(struct fb_info *); -+ unsigned int (*get_dclk)(struct fb_info *); - void (*configure_display)(struct fb_info *); - int (*blank_display)(struct fb_info *, int blank_mode); - }; - - struct geodefb_par { - int enable_crt; -+ int fbactive; /* True if the current console is in KD_GRAPHICS mode */ - int panel_x; /* dimensions of an attached flat panel, non-zero => enable panel */ - int panel_y; -+ unsigned int curdclk; /* Used by GX to avoid unnessesary clock switching */ - void __iomem *dc_regs; - void __iomem *vid_regs; -+ void __iomem *gp_regs; - struct geode_dc_ops *dc_ops; - struct geode_vid_ops *vid_ops; -+ -+ int state; - }; - - #endif /* !__GEODEFB_H__ */ -Index: linux-2.6.24.7/drivers/video/geode/geode_regs.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/video/geode/geode_regs.h -@@ -0,0 +1,255 @@ -+/* This header file defines the registers and suspend/resume -+ structures for the Geode GX and LX. The lxfb driver defines -+ _GEODELX_ before including this file, which will unlock the -+ extra registers that are only valid for LX. -+*/ -+ -+#ifndef _GEODE_REGS_H_ -+#define _GEODE_REGS_H_ -+ -+/* MSRs */ -+ -+#define GX_VP_MSR_PAD_SELECT 0xC0002011 -+#define LX_VP_MSR_PAD_SELECT 0x48000011 -+ -+#define GEODE_MSR_GLCP_DOTPLL 0x4c000015 -+ -+#define GLCP_DOTPLL_RESET (1 << 0) -+#define GLCP_DOTPLL_BYPASS (1 << 15) -+#define GLCP_DOTPLL_HALFPIX (1 << 24) -+#define GLCP_DOTPLL_LOCK (1 << 25) -+ -+/* Registers */ -+#define VP_FP_START 0x400 -+ -+ -+#ifdef _GEODELX_ -+ -+#define GP_REG_SIZE 0x7C -+#define DC_REG_SIZE 0xF0 -+#define VP_REG_SIZE 0x158 -+#define FP_REG_SIZE 0x70 -+ -+#else -+ -+#define GP_REG_SIZE 0x50 -+#define DC_REG_SIZE 0x90 -+#define VP_REG_SIZE 0x138 -+#define FP_REG_SIZE 0x70 -+ -+#endif -+ -+#define DC_PAL_SIZE 0x105 -+#define VP_COEFF_COUNT 512 -+#define DC_HFILT_SIZE 256 -+#define DC_VFILT_SIZE 256 -+ -+struct geoderegs { -+ -+ struct { -+ u64 padsel; -+ u64 dotpll; -+ -+#ifdef _GEODELX_ -+ u64 dfglcfg; -+ u64 dcspare; -+#else -+ u64 rstpll; -+#endif -+ } msr; -+ -+ union { -+ unsigned char b[GP_REG_SIZE]; -+ struct { -+ u32 dst_offset; /* 0x00 */ -+ u32 src_offset; /* 0x04 */ -+ u32 stride; /* 0x08 */ -+ u32 wid_height; /* 0x0C */ -+ u32 src_color_fg; /* 0x10 */ -+ u32 src_color_bg; /* 0x14 */ -+ u32 pat_color_0; /* 0x18 */ -+ u32 pat_color_1; /* 0x1C */ -+ u32 pat_color_2; /* 0x20 */ -+ u32 pat_color_3; /* 0x24 */ -+ u32 pat_color_4; /* 0x28 */ -+ u32 pat_color_5; /* 0x2C */ -+ u32 pat_data_0; /* 0x30 */ -+ u32 pat_data_1; /* 0x34 */ -+ u32 raster_mode; /* 0x38 */ -+ u32 vector_mode; /* 0x3C */ -+ u32 blt_mode; /* 0x40 */ -+ u32 blit_status; /* 0x4C */ -+ u32 hst_src; /* 0x48 */ -+ u32 base_offset; /* 0x4C */ -+ -+#ifdef _GEODELX_ -+ u32 cmd_top; /* 0x50 */ -+ u32 cmd_bot; /* 0x54 */ -+ u32 cmd_read; /* 0x58 */ -+ u32 cmd_write; /* 0x5C */ -+ u32 ch3_offset; /* 0x60 */ -+ u32 ch3_mode_str; /* 0x64 */ -+ u32 ch3_width; /* 0x68 */ -+ u32 ch3_hsrc; /* 0x6C */ -+ u32 lut_index; /* 0x70 */ -+ u32 lut_data; /* 0x74 */ -+ u32 int_cntrl; /* 0x78 */ -+#endif -+ } r; -+ } gp; -+ -+ union { -+ unsigned char b[DC_REG_SIZE]; -+ -+ struct { -+ u32 unlock; /* 0x00 */ -+ u32 gcfg; /* 0x04 */ -+ u32 dcfg; /* 0x08 */ -+ u32 arb; /* 0x0C */ -+ u32 fb_st_offset; /* 0x10 */ -+ u32 cb_st_offset; /* 0x14 */ -+ u32 curs_st_offset; /* 0x18 */ -+ u32 icon_st_offset; /* 0x1C */ -+ u32 vid_y_st_offset; /* 0x20 */ -+ u32 vid_u_st_offset; /* 0x24 */ -+ u32 vid_v_st_offset; /* 0x28 */ -+ u32 dctop; /* 0x2c */ -+ u32 line_size; /* 0x30 */ -+ u32 gfx_pitch; /* 0x34 */ -+ u32 vid_yuv_pitch; /* 0x38 */ -+ u32 rsvd2; /* 0x3C */ -+ u32 h_active_timing; /* 0x40 */ -+ u32 h_blank_timing; /* 0x44 */ -+ u32 h_sync_timing; /* 0x48 */ -+ u32 rsvd3; /* 0x4C */ -+ u32 v_active_timing; /* 0x50 */ -+ u32 v_blank_timing; /* 0x54 */ -+ u32 v_sync_timing; /* 0x58 */ -+ u32 fbactive; /* 0x5C */ -+ u32 dc_cursor_x; /* 0x60 */ -+ u32 dc_cursor_y; /* 0x64 */ -+ u32 dc_icon_x; /* 0x68 */ -+ u32 dc_line_cnt; /* 0x6C */ -+ u32 rsvd5; /* 0x70 - palette address */ -+ u32 rsvd6; /* 0x74 - palette data */ -+ u32 dfifo_diag; /* 0x78 */ -+ u32 cfifo_diag; /* 0x7C */ -+ u32 dc_vid_ds_delta; /* 0x80 */ -+ u32 gliu0_mem_offset; /* 0x84 */ -+ u32 dv_ctl; /* 0x88 - added by LX */ -+ u32 dv_acc; /* 0x8C */ -+ -+#ifdef _GEODELX_ -+ u32 gfx_scale; -+ u32 irq_filt_ctl; -+ u32 filt_coeff1; -+ u32 filt_coeff2; -+ u32 vbi_event_ctl; -+ u32 vbi_odd_ctl; -+ u32 vbi_hor; -+ u32 vbi_ln_odd; -+ u32 vbi_ln_event; -+ u32 vbi_pitch; -+ u32 clr_key; -+ u32 clr_key_mask; -+ u32 clr_key_x; -+ u32 clr_key_y; -+ u32 irq; -+ u32 rsvd8; -+ u32 genlk_ctrl; -+ u32 vid_even_y_st_offset; /* 0xD8 */ -+ u32 vid_even_u_st_offset; /* 0xDC */ -+ u32 vid_even_v_st_offset; /* 0xE0 */ -+ u32 v_active_even_timing; /* 0xE4 */ -+ u32 v_blank_even_timing; /* 0xE8 */ -+ u32 v_sync_even_timing; /* 0xEC */ -+#endif -+ } r; -+ } dc; -+ -+ union { -+ unsigned char b[VP_REG_SIZE]; -+ -+ struct { -+ u64 vcfg; /* 0x00 */ -+ u64 dcfg; /* 0x08 */ -+ u64 vx; /* 0x10 */ -+ u64 vy; /* 0x18 */ -+ u64 vs; /* 0x20 */ -+ u64 vck; /* 0x28 */ -+ u64 vcm; /* 0x30 */ -+ u64 rsvd1; /* 0x38 - Gamma address*/ -+ u64 rsvd2; /* 0x40 - Gamma data*/ -+ u64 slr; /* 0x48 - LX only*/ -+ u64 misc; /* 0x50 */ -+ u64 ccs; /* 0x58 */ -+ u64 vys; /* 0x60 */ -+ u64 vxs; /* 0x68 */ -+ u64 rsvd4; /* 0x70 */ -+ u64 vdc; /* 0x78 */ -+ u64 vco; /* 0x80 */ -+ u64 crc; /* 0x88 */ -+ u64 crc32; /* 0x90 */ -+ u64 vde; /* 0x98 */ -+ u64 cck; /* 0xA0 */ -+ u64 ccm; /* 0xA8 */ -+ u64 cc1; /* 0xB0 */ -+ u64 cc2; /* 0xB8 */ -+ u64 a1x; /* 0xC0 */ -+ u64 a1y; /* 0xC8 */ -+ u64 a1c; /* 0xD0 */ -+ u64 a1t; /* 0xD8 */ -+ u64 a2x; /* 0xE0 */ -+ u64 a2y; /* 0xE8 */ -+ u64 a2c; /* 0xF0 */ -+ u64 a2t; /* 0xF8 */ -+ u64 a3x; /* 0x100 */ -+ u64 a3y; /* 0x108 */ -+ u64 a3c; /* 0x110 */ -+ u64 a3t; /* 0x118 */ -+ u64 vrr; /* 0x120 */ -+ u64 awt; /* 0x128 */ -+ u64 vtm; /* 0x130 */ -+#ifdef _GEODELX_ -+ u64 vye; /* 0x138 */ -+ u64 a1ye; /* 0x140 */ -+ u32 a2ye; /* 0x148 */ -+ u32 a3ye; /* 0x150 */ -+#endif -+ } r; -+ } vp; -+ -+ union { -+ unsigned char b[FP_REG_SIZE]; -+ -+ struct { -+ u64 pt1; /* 0x400 */ -+ u64 pt2; /* 0x408 */ -+ u64 pm; /* 0x410 */ -+ u64 dfc; /* 0x418 */ -+ u64 blfsr; /* 0x420 */ -+ u64 rlfsr; /* 0x428 */ -+ u64 fmi; /* 0x430 */ -+ u64 fmd; /* 0x438 */ -+ u64 rsvd; /* 0x440 */ -+ u64 dca; /* 0x448 */ -+ u64 dmd; /* 0x450 */ -+ u64 crc; /* 0x458 */ -+ u64 fbb; /* 0x460 */ -+ u64 crc32; /* 0x468 */ -+ } r; -+ } fp; -+ -+ u32 pal[DC_PAL_SIZE]; -+ u32 gamma[256]; -+ -+#ifdef _GEODELX_ -+ -+ u32 hcoeff[DC_HFILT_SIZE * 2]; -+ u32 vcoeff[DC_VFILT_SIZE]; -+ -+ u32 vp_coeff[VP_COEFF_COUNT]; -+#endif -+}; -+ -+#endif -Index: linux-2.6.24.7/drivers/video/geode/gxfb_core.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/gxfb_core.c -+++ linux-2.6.24.7/drivers/video/geode/gxfb_core.c -@@ -30,12 +30,31 @@ - #include - #include - #include -+#include -+#include -+#include -+#include -+#include - - #include "geodefb.h" - #include "display_gx.h" - #include "video_gx.h" - -+#define FBIOSGAMMA _IOW('F', 0x20, void *) -+#define FBIOGGAMMA _IOW('F', 0x21, void *) -+ -+#ifdef DEBUG -+ -+#define FBIODUMPGP _IOW('F', 0x22, void *) -+#define FBIODUMPDC _IOW('F', 0x23, void *) -+#define FBIODUMPVP _IOW('F', 0x24, void *) -+#define FBIODUMPFP _IOW('F', 0x25, void *) -+ -+#endif -+ - static char *mode_option; -+static int noclear; -+struct fb_info *gxfb_info; - - /* Modes relevant to the GX (taken from modedb.c) */ - static const struct fb_videomode gx_modedb[] __initdata = { -@@ -103,8 +122,20 @@ static const struct fb_videomode gx_mode - { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1200x900-75 - CRT timings for the OLPC mode */ -+ { NULL, 75, 1200, 900, 8049, 104, 240, 29, 54, 136, 3, -+ 0, FB_VMODE_NONINTERLACED, 0 } - }; - -+#ifdef CONFIG_OLPC -+static const struct fb_videomode gx_dcon_modedb[] __initdata = { -+ /* The only mode the DCON has is 1200x900 */ -+ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3, -+ 0, FB_VMODE_NONINTERLACED, 0 } -+}; -+#endif -+ -+ - static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) - { - if (var->xres > 1600 || var->yres > 1200) -@@ -137,7 +168,7 @@ static int gxfb_check_var(struct fb_var_ - return 0; - } - --static int gxfb_set_par(struct fb_info *info) -+int gxfb_set_par(struct fb_info *info) - { - struct geodefb_par *par = info->par; - -@@ -204,16 +235,26 @@ static int gxfb_blank(int blank_mode, st - return par->vid_ops->blank_display(info, blank_mode); - } - -+static int fbsize; -+ - static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev) - { - struct geodefb_par *par = info->par; -- int fb_len; - int ret; - - ret = pci_enable_device(dev); - if (ret < 0) - return ret; - -+ ret = pci_request_region(dev, 1, "gxfb (graphics processor)"); -+ if (ret < 0) -+ return ret; -+ -+ par->gp_regs = ioremap(pci_resource_start(dev, 1), -+ pci_resource_len(dev, 1)); -+ if (!par->gp_regs) -+ return -ENOMEM; -+ - ret = pci_request_region(dev, 3, "gxfb (video processor)"); - if (ret < 0) - return ret; -@@ -232,36 +273,118 @@ static int __init gxfb_map_video_memory( - ret = pci_request_region(dev, 0, "gxfb (framebuffer)"); - if (ret < 0) - return ret; -- if ((fb_len = gx_frame_buffer_size()) < 0) -- return -ENOMEM; -+ -+ /* If the fbsize wasn't specified then try to probe it */ -+ -+ if (!fbsize) { -+ fbsize = gx_frame_buffer_size(); -+ if (fbsize == 0) -+ return -ENOMEM; -+ } -+ - info->fix.smem_start = pci_resource_start(dev, 0); -- info->fix.smem_len = fb_len; -+ info->fix.smem_len = fbsize; - info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); - if (!info->screen_base) - return -ENOMEM; - -- /* Set the 16MB aligned base address of the graphics memory region -+ /* Set the 16MiB aligned base address of the graphics memory region - * in the display controller */ - - writel(info->fix.smem_start & 0xFF000000, - par->dc_regs + DC_GLIU0_MEM_OFFSET); - -- dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n", -+ dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n", - info->fix.smem_len / 1024, info->fix.smem_start); - - return 0; - } - -+static int gxfb_ioctl( struct fb_info *info, unsigned int cmd, -+ unsigned long arg) -+{ -+ unsigned int gamma[GXFB_GAMMA_DWORDS]; -+ int ret = -EINVAL; -+ struct geodefb_par *par = info->par; -+ int i; -+ -+ switch(cmd) { -+ case FBIOSGAMMA: -+ /* Read the gamma information from the user - 256 dwords */ -+ -+ if (copy_from_user(gamma, (void * __user) arg, GXFB_GAMMA_SIZE)) -+ return -EFAULT; -+ -+ writel(0, par->vid_regs + GX_GAR); -+ -+ /* Sequential writes to the data register will increment the -+ address automatically */ -+ -+ for(i = 0; i < GXFB_GAMMA_DWORDS; i++) -+ writel(gamma[i] & 0xFFFFFF, par->vid_regs + GX_GDR); -+ -+ writel(readl(par->vid_regs + GX_MISC) & ~GX_MISC_GAM_EN, -+ par->vid_regs + GX_MISC); -+ -+ ret = 0; -+ break; -+ -+ case FBIOGGAMMA: -+ if (readl(par->vid_regs + GX_MISC) & GX_MISC_GAM_EN) -+ return -EINVAL; -+ -+ memset(gamma, 0, GXFB_GAMMA_SIZE); -+ writel(0, par->vid_regs + GX_GAR); -+ -+ for(i = 0; i < GXFB_GAMMA_DWORDS;i++) -+ gamma[i] = readl(par->vid_regs + GX_GDR); -+ -+ if (copy_to_user((void * __user) arg, gamma, GXFB_GAMMA_SIZE)) -+ ret = -EFAULT; -+ else -+ ret = 0; -+ -+ break; -+ -+#ifdef DEBUG -+ case FBIODUMPGP: -+ ret = 0; -+ dump_regs(info, 0); -+ break; -+ -+ case FBIODUMPDC: -+ ret = 0; -+ dump_regs(info, 1); -+ break; -+ -+ case FBIODUMPVP: -+ ret = 0; -+ dump_regs(info, 2); -+ break; -+ -+ case FBIODUMPFP: -+ ret = 0; -+ dump_regs(info, 3); -+ break; -+#endif -+ } -+ -+ return ret; -+} -+ - static struct fb_ops gxfb_ops = { - .owner = THIS_MODULE, - .fb_check_var = gxfb_check_var, - .fb_set_par = gxfb_set_par, - .fb_setcolreg = gxfb_setcolreg, - .fb_blank = gxfb_blank, -+ .fb_ioctl = gxfb_ioctl, - /* No HW acceleration for now. */ - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, -+ .fb_powerdown = gxfb_powerdown, -+ .fb_powerup = gxfb_powerup, - }; - - static struct fb_info * __init gxfb_init_fbinfo(struct device *dev) -@@ -303,23 +426,86 @@ static struct fb_info * __init gxfb_init - return info; - } - --static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) -+static int gxfb_console_notify(struct notifier_block *self, -+ unsigned long action, void *data) -+{ -+ if (gxfb_info != NULL) { -+ struct geodefb_par *par = gxfb_info->par; -+ par->fbactive = (action == CONSOLE_EVENT_SWITCH_TEXT) ? 0 : 1; -+ } -+ -+ return NOTIFY_OK; -+} -+ -+static struct notifier_block gxfb_console_notifier = { -+ .notifier_call = gxfb_console_notify -+}; -+ -+#ifdef CONFIG_PM -+ -+static int gxfb_suspend(struct pci_dev *pdev, pm_message_t state) -+{ -+ struct fb_info *info = pci_get_drvdata(pdev); -+ struct geodefb_par *par = info->par; -+ -+ if (pdev->dev.power.power_state.event == state.event) -+ return 0; -+ -+ if (state.event == PM_EVENT_SUSPEND) { -+ -+ acquire_console_sem(); -+ gxfb_powerdown(info); -+ -+ par->state = FB_POWER_STATE_OFF; -+ fb_set_suspend(info, 1); -+ -+ release_console_sem(); -+ } -+ -+ pdev->dev.power.power_state = state; -+ return 0; -+} -+ -+static int gxfb_resume(struct pci_dev *pdev) -+{ -+ struct fb_info *info = pci_get_drvdata(pdev); -+ -+ acquire_console_sem(); -+ -+ /* Turn the engine completely on */ -+ -+ if (gxfb_powerup(info)) -+ printk(KERN_ERR "gxfb: Powerup failed\n"); -+ -+ fb_set_suspend(info, 0); -+ release_console_sem(); -+ -+ pdev->dev.power.power_state = PMSG_ON; -+ return 0; -+} -+#endif -+ -+static int __init gxfb_probe(struct pci_dev *pdev, -+ const struct pci_device_id *id) - { - struct geodefb_par *par; -- struct fb_info *info; - int ret; - unsigned long val; - -- info = gxfb_init_fbinfo(&pdev->dev); -- if (!info) -+ struct fb_videomode *modedb_ptr; -+ int modedb_size; -+ -+ gxfb_info = gxfb_init_fbinfo(&pdev->dev); -+ if (gxfb_info == NULL) - return -ENOMEM; -- par = info->par; -+ -+ par = gxfb_info->par; - - /* GX display controller and GX video device. */ - par->dc_ops = &gx_dc_ops; - par->vid_ops = &gx_vid_ops; - -- if ((ret = gxfb_map_video_memory(info, pdev)) < 0) { -+ if ((ret = gxfb_map_video_memory(gxfb_info, pdev)) < 0) { - dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n"); - goto err; - } -@@ -333,32 +519,60 @@ static int __init gxfb_probe(struct pci_ - else - par->enable_crt = 1; - -- ret = fb_find_mode(&info->var, info, mode_option, -- gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16); -+ /* Get the current dotclock */ -+ -+ par->curdclk = (par->vid_ops->get_dclk) ? par->vid_ops->get_dclk(gxfb_info) : 0; -+ -+ /* We need to determine a display mode right now, so we will -+ * check to see if the DCON was previously detected by the BIOS -+ * and use that to make our mode database decision. -+ */ -+ -+ modedb_ptr = (struct fb_videomode *) gx_modedb; -+ modedb_size = ARRAY_SIZE(gx_modedb); -+ -+#ifdef CONFIG_OLPC -+ if (olpc_has_dcon()) { -+ modedb_ptr = (struct fb_videomode *) gx_dcon_modedb; -+ modedb_size = ARRAY_SIZE(gx_dcon_modedb); -+ } -+#endif -+ -+ ret = fb_find_mode(&gxfb_info->var, gxfb_info, mode_option, -+ modedb_ptr, modedb_size, NULL, 16); -+ - if (ret == 0 || ret == 4) { - dev_err(&pdev->dev, "could not find valid video mode\n"); - ret = -EINVAL; - goto err; - } - -+ /* Clear the screen of garbage, unless noclear was specified, -+ * in which case we assume the user knows what he is doing */ -+ -+ if (!noclear) -+ memset_io(gxfb_info->screen_base, 0, gxfb_info->fix.smem_len); -+ -+ gxfb_check_var(&gxfb_info->var, gxfb_info); -+ gxfb_set_par(gxfb_info); -+ -+ /* We are powered up */ -+ par->state = FB_POWER_STATE_ON; - -- /* Clear the frame buffer of garbage. */ -- memset_io(info->screen_base, 0, info->fix.smem_len); - -- gxfb_check_var(&info->var, info); -- gxfb_set_par(info); -+ console_event_register(&gxfb_console_notifier); - -- if (register_framebuffer(info) < 0) { -+ if (register_framebuffer(gxfb_info) < 0) { - ret = -EINVAL; - goto err; - } -- pci_set_drvdata(pdev, info); -- printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); -+ pci_set_drvdata(pdev, gxfb_info); -+ printk(KERN_INFO "fb%d: %s frame buffer device\n", gxfb_info->node, gxfb_info->fix.id); - return 0; - - err: -- if (info->screen_base) { -- iounmap(info->screen_base); -+ if (gxfb_info->screen_base) { -+ iounmap(gxfb_info->screen_base); - pci_release_region(pdev, 0); - } - if (par->vid_regs) { -@@ -370,8 +584,9 @@ static int __init gxfb_probe(struct pci_ - pci_release_region(pdev, 2); - } - -- if (info) -- framebuffer_release(info); -+ if (gxfb_info) -+ framebuffer_release(gxfb_info); -+ - return ret; - } - -@@ -397,9 +612,7 @@ static void gxfb_remove(struct pci_dev * - } - - static struct pci_device_id gxfb_id_table[] = { -- { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO, -- PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, -- 0xff0000, 0 }, -+ { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) }, - { 0, } - }; - -@@ -410,22 +623,30 @@ static struct pci_driver gxfb_driver = { - .id_table = gxfb_id_table, - .probe = gxfb_probe, - .remove = gxfb_remove, -+#ifdef CONFIG_PM -+ .suspend = gxfb_suspend, -+ .resume = gxfb_resume -+#endif - }; - - #ifndef MODULE --static int __init gxfb_setup(char *options) --{ -+static int __init gxfb_setup(char *options) { - - char *opt; - - if (!options || !*options) - return 0; - -- while ((opt = strsep(&options, ",")) != NULL) { -+ while((opt = strsep(&options, ",")) != NULL) { - if (!*opt) - continue; - -- mode_option = opt; -+ if (!strncmp(opt, "fbsize:", 7)) -+ fbsize = simple_strtoul(opt+7, NULL, 0); -+ else if (!strcmp(opt, "noclear")) -+ noclear = 1; -+ else -+ mode_option = opt; - } - - return 0; -@@ -444,7 +665,6 @@ static int __init gxfb_init(void) - #endif - return pci_register_driver(&gxfb_driver); - } -- - static void __exit gxfb_cleanup(void) - { - pci_unregister_driver(&gxfb_driver); -@@ -456,5 +676,8 @@ module_exit(gxfb_cleanup); - module_param(mode_option, charp, 0); - MODULE_PARM_DESC(mode_option, "video mode (x[-][@])"); - -+module_param(fbsize, int, 0); -+MODULE_PARM_DESC(fbsize, "video memory size"); -+ - MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX"); - MODULE_LICENSE("GPL"); -Index: linux-2.6.24.7/drivers/video/geode/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/Kconfig -+++ linux-2.6.24.7/drivers/video/geode/Kconfig -@@ -38,26 +38,6 @@ config FB_GEODE_GX - - If unsure, say N. - --config FB_GEODE_GX_SET_FBSIZE -- bool "Manually specify the Geode GX framebuffer size" -- depends on FB_GEODE_GX -- default n -- ---help--- -- If you want to manually specify the size of your GX framebuffer, -- say Y here, otherwise say N to dynamically probe it. -- -- Say N unless you know what you are doing. -- --config FB_GEODE_GX_FBSIZE -- hex "Size of the GX framebuffer, in bytes" -- depends on FB_GEODE_GX_SET_FBSIZE -- default "0x1600000" -- ---help--- -- Specify the size of the GX framebuffer. Normally, you will -- want this to be MB aligned. Common values are 0x80000 (8MB) -- and 0x1600000 (16MB). Don't change this unless you know what -- you are doing -- - config FB_GEODE_GX1 - tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)" - depends on FB && FB_GEODE && EXPERIMENTAL -Index: linux-2.6.24.7/drivers/video/geode/lxfb_core.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/lxfb_core.c -+++ linux-2.6.24.7/drivers/video/geode/lxfb_core.c -@@ -21,7 +21,8 @@ - #include - #include - #include --#include -+#include -+#include - - #include "lxfb.h" - -@@ -35,186 +36,84 @@ static int fbsize; - */ - - const struct fb_videomode geode_modedb[] __initdata = { -- /* 640x480-60 */ -- { NULL, 60, 640, 480, 39682, 48, 8, 25, 2, 88, 2, -+ /* 640x480-60 VESA */ -+ { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, -+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 640x480-75 VESA */ -+ { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3, -+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 640x480-85 VESA */ -+ { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3, -+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 800x600-60 VESA */ -+ { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 800x600-75 VESA */ -+ { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 800x600-85 VESA */ -+ { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1024x768-60 VESA */ -+ { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6, -+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1024x768-75 VESA */ -+ { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1024x768-85 VESA */ -+ { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x960-60 VESA */ -+ { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x960-85 VESA */ -+ { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x1024-60 VESA */ -+ { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x1024-75 VESA */ -+ { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x1024-85 VESA */ -+ { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x400-70 */ -- { NULL, 70, 640, 400, 39770, 40, 8, 28, 5, 96, 2, -- FB_SYNC_HOR_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-70 */ -- { NULL, 70, 640, 480, 35014, 88, 24, 15, 2, 64, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-72 */ -- { NULL, 72, 640, 480, 32102, 120, 16, 20, 1, 40, 3, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-75 */ -- { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-85 */ -- { NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-90 */ -- { NULL, 90, 640, 480, 26392, 96, 32, 22, 1, 64, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-100 */ -- { NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-60 */ -- { NULL, 60, 640, 480, 39682, 48, 16, 25, 10, 88, 2, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-56 */ -- { NULL, 56, 800, 600, 27901, 128, 24, 22, 1, 72, 2, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-60 */ -- { NULL, 60, 800, 600, 25131, 72, 32, 23, 1, 136, 4, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-70 */ -- { NULL, 70, 800, 600, 21873, 120, 40, 21, 4, 80, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-72 */ -- { NULL, 72, 800, 600, 20052, 64, 56, 23, 37, 120, 6, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-75 */ -- { NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-85 */ -- { NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-90 */ -- { NULL, 90, 800, 600, 16648, 128, 40, 28, 1, 88, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-100 */ -- { NULL, 100, 800, 600, 14667, 136, 48, 27, 1, 88, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-60 */ -- { NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-60 */ -- { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-70 */ -- { NULL, 70, 1024, 768, 13346, 144, 24, 29, 3, 136, 6, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-72 */ -- { NULL, 72, 1024, 768, 12702, 168, 56, 29, 4, 112, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-75 */ -- { NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-85 */ -- { NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-90 */ -- { NULL, 90, 1024, 768, 9981, 176, 64, 37, 1, 112, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-100 */ -- { NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-60 */ -- { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-60 */ -- { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-70 */ -- { NULL, 70, 1152, 864, 10254, 192, 72, 32, 8, 120, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-72 */ -- { NULL, 72, 1152, 864, 9866, 200, 72, 33, 7, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-75 */ -- { NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-85 */ -- { NULL, 85, 1152, 864, 8357, 200, 72, 37, 3, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-90 */ -- { NULL, 90, 1152, 864, 7719, 208, 80, 42, 9, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-100 */ -- { NULL, 100, 1152, 864, 6947, 208, 80, 48, 3, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-60 */ -- { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-60 */ -- { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-70 */ -- { NULL, 70, 1280, 1024, 7719, 224, 88, 38, 6, 136, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-72 */ -- { NULL, 72, 1280, 1024, 7490, 224, 88, 39, 7, 136, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-75 */ -- { NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-85 */ -- { NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-90 */ -- { NULL, 90, 1280, 1024, 5791, 240, 96, 51, 12, 144, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-100 */ -- { NULL, 100, 1280, 1024, 5212, 240, 96, 57, 6, 144, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-60 */ -- { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-60 */ -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1600x1200-60 VESA */ - { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-70 */ -- { NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-72 */ -- { NULL, 72, 1600, 1200, 5053, 288, 112, 47, 13, 176, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-75 */ -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1600x1200-75 VESA */ - { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-85 */ -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1600x1200-85 VESA */ - { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-90 */ -- { NULL, 90, 1600, 1200, 3981, 304, 128, 60, 1, 176, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-100 */ -- { NULL, 100, 1600, 1200, 3563, 304, 128, 67, 1, 176, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-60 */ -- { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-60 */ -- { NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-70 */ -- { NULL, 70, 1920, 1440, 3593, 360, 152, 55, 8, 208, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-72 */ -- { NULL, 72, 1920, 1440, 3472, 360, 152, 68, 4, 208, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-75 */ -- { NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-85 */ -- { NULL, 85, 1920, 1440, 2929, 368, 152, 68, 1, 216, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1200x900-75 - CRT timings for the OLPC mode */ -+ { NULL, 75, 1200, 900, 8049, 104, 240, 29, 54, 136, 3, -+ 0, FB_VMODE_NONINTERLACED, 0 } - }; - -+#ifdef CONFIG_OLPC -+const struct fb_videomode olpc_dcon_modedb[] __initdata = { -+ /* The only mode the DCON has is 1200x900 */ -+ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, 0 } -+}; -+#endif -+ - static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) - { - if (var->xres > 1920 || var->yres > 1440) -@@ -255,8 +154,7 @@ static int lxfb_set_par(struct fb_info * - fb_alloc_cmap(&info->cmap, 1<var.bits_per_pixel, 0); - } - -- info->fix.line_length = lx_get_pitch(info->var.xres, -- info->var.bits_per_pixel); -+ info->fix.line_length = lx_get_pitch(info->var.xres, info->var.bits_per_pixel); - - lx_set_mode(info); - return 0; -@@ -371,24 +269,61 @@ static int __init lxfb_map_video_memory( - writel(info->fix.smem_start & 0xFF000000, - par->dc_regs + DC_PHY_MEM_OFFSET); - -- writel(0, par->dc_regs + DC_UNLOCK); -- - dev_info(&dev->dev, "%d KB of video memory at 0x%lx\n", - info->fix.smem_len / 1024, info->fix.smem_start); - - return 0; - } - -+static int lxfb_set_gamma(struct fb_info *info, void * __user data) -+{ -+ unsigned int gamma[LXFB_GAMMA_DWORDS]; -+ -+ if (copy_from_user(gamma, data, LXFB_GAMMA_SIZE)) -+ return -EFAULT; -+ -+ lx_set_gamma(info, gamma, LXFB_GAMMA_SIZE); -+ return 0; -+} -+ -+static int lxfb_get_gamma(struct fb_info *info, void * __user data) -+{ -+ unsigned int gamma[LXFB_GAMMA_DWORDS]; -+ memset(gamma, 0, sizeof(gamma)); -+ -+ lx_get_gamma(info, gamma, LXFB_GAMMA_DWORDS); -+ -+ return copy_to_user(data, gamma, LXFB_GAMMA_SIZE) ? -+ -EFAULT : 0; -+} -+ -+static int lxfb_ioctl( struct fb_info *info, unsigned int cmd, -+ unsigned long arg) -+{ -+ switch(cmd) { -+ case FBIOSGAMMA: -+ return lxfb_set_gamma(info, (void * __user) arg); -+ -+ case FBIOGGAMMA: -+ return lxfb_get_gamma(info, (void * __user) arg); -+ } -+ -+ return -ENOTTY; -+} -+ - static struct fb_ops lxfb_ops = { - .owner = THIS_MODULE, - .fb_check_var = lxfb_check_var, - .fb_set_par = lxfb_set_par, - .fb_setcolreg = lxfb_setcolreg, - .fb_blank = lxfb_blank, -+ .fb_ioctl = lxfb_ioctl, - /* No HW acceleration for now. */ - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, -+ .fb_powerdown = lx_shutdown, -+ .fb_powerup = lx_powerup, - }; - - static struct fb_info * __init lxfb_init_fbinfo(struct device *dev) -@@ -431,6 +366,45 @@ static struct fb_info * __init lxfb_init - return info; - } - -+#ifdef CONFIG_PM -+ -+static int lxfb_suspend(struct pci_dev *pdev, pm_message_t state) -+{ -+ struct fb_info *info = pci_get_drvdata(pdev); -+ -+ if (pdev->dev.power.power_state.event == state.event) -+ return 0; -+ -+ if (state.event == PM_EVENT_SUSPEND) { -+ -+ acquire_console_sem(); -+ lx_shutdown(info); -+ fb_set_suspend(info, 1); -+ release_console_sem(); -+ } -+ -+ pdev->dev.power.power_state = state; -+ return 0; -+} -+ -+static int lxfb_resume(struct pci_dev *pdev) -+{ -+ struct fb_info *info = pci_get_drvdata(pdev); -+ -+ acquire_console_sem(); -+ -+ /* Turn the engine completely on */ -+ -+ lx_powerup(info); -+ fb_set_suspend(info, 0); -+ release_console_sem(); -+ -+ pdev->dev.power.power_state = PMSG_ON; -+ return 0; -+} -+ -+#endif -+ - static int __init lxfb_probe(struct pci_dev *pdev, - const struct pci_device_id *id) - { -@@ -467,6 +441,13 @@ static int __init lxfb_probe(struct pci_ - modedb_ptr = (struct fb_videomode *) geode_modedb; - modedb_size = ARRAY_SIZE(geode_modedb); - -+#ifdef CONFIG_OLPC -+ if (olpc_has_dcon()) { -+ modedb_ptr = (struct fb_videomode *) olpc_dcon_modedb; -+ modedb_size = ARRAY_SIZE(olpc_dcon_modedb); -+ } -+#endif -+ - ret = fb_find_mode(&info->var, info, mode_option, - modedb_ptr, modedb_size, NULL, 16); - -@@ -556,6 +537,10 @@ static struct pci_driver lxfb_driver = { - .id_table = lxfb_id_table, - .probe = lxfb_probe, - .remove = lxfb_remove, -+#ifdef CONFIG_PM -+ .suspend = lxfb_suspend, -+ .resume = lxfb_resume -+#endif - }; - - #ifndef MODULE -Index: linux-2.6.24.7/drivers/video/geode/lxfb.h -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/lxfb.h -+++ linux-2.6.24.7/drivers/video/geode/lxfb.h -@@ -25,10 +25,23 @@ void lx_set_mode(struct fb_info *); - void lx_get_gamma(struct fb_info *, unsigned int *, int); - void lx_set_gamma(struct fb_info *, unsigned int *, int); - unsigned int lx_framebuffer_size(void); -+int lx_shutdown(struct fb_info *); -+int lx_powerup(struct fb_info *); - int lx_blank_display(struct fb_info *, int); - void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int, - unsigned int, unsigned int); - -+ -+ -+/* ioctl() defines */ -+ -+#define FBIOSGAMMA _IOW('F', 0x20, void *) -+#define FBIOGGAMMA _IOW('F', 0x21, void *) -+ -+/* General definitions */ -+#define LXFB_GAMMA_DWORDS 256 /* number of dwords in the gamma ram */ -+#define LXFB_GAMMA_SIZE (LXFB_GAMMA_DWORDS * sizeof(unsigned int)) -+ - /* MSRS */ - - #define MSR_LX_GLD_CONFIG 0x48002001 -@@ -127,7 +140,7 @@ void lx_set_palette_reg(struct fb_info * - - #define DC_GFX_SCALE 0x90 - #define DC_IRQ_FILT_CTL 0x94 -- -+#define DC_IRQFILT_H_FILT_SEL 0x00000400 - - #define DC_IRQ 0xC8 - #define DC_IRQ_MASK (1 << 0) -Index: linux-2.6.24.7/drivers/video/geode/lxfb_ops.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/lxfb_ops.c -+++ linux-2.6.24.7/drivers/video/geode/lxfb_ops.c -@@ -11,11 +11,15 @@ - #include - #include - #include --#include --#include -+#include -+#include -+#include - - #include "lxfb.h" - -+#define _GEODELX_ -+#include "geode_regs.h" -+ - /* TODO - * Support panel scaling - * Add acceleration -@@ -290,6 +294,19 @@ unsigned int lx_framebuffer_size(void) - { - unsigned int val; - -+#ifdef CONFIG_OLPC -+ if (machine_is_olpc() && !olpc_has_vsa()) { -+ u32 hi,lo; -+ rdmsr(MSR_LX_GLIU0_P2D_RO0, lo, hi); -+ -+ /* Top page number */ -+ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); -+ val -= (lo & 0x000fffff); /* Subtract bottom page number */ -+ val += 1; /* Adjust page count */ -+ return (val << 12); -+ } -+#endif -+ - /* The frame buffer size is reported by a VSM in VSA II */ - /* Virtual Register Class = 0x02 */ - /* VG_MEM_SIZE (1MB units) = 0x00 */ -@@ -301,6 +318,34 @@ unsigned int lx_framebuffer_size(void) - return (val << 20); - } - -+void lx_set_gamma(struct fb_info *info, unsigned int *gamma, int len) -+{ -+ int i; -+ struct lxfb_par *par = info->par; -+ -+ writel(0, par->df_regs + DF_PAR); -+ -+ /* Sequential writes to the data register will increment the -+ address automatically */ -+ -+ for(i = 0; i < len; i++) -+ writel(gamma[i] & 0xFFFFFF, par->df_regs + DF_PDR); -+ -+ writel(readl(par->df_regs + DF_MISC) & ~DF_MISC_GAM_BYPASS, -+ par->df_regs + DF_MISC); -+} -+ -+void lx_get_gamma(struct fb_info *info, unsigned int *gamma, int len) -+{ -+ int i; -+ struct lxfb_par *par = info->par; -+ -+ writel(0, par->df_regs + DF_PAR); -+ -+ for(i = 0; i < len;i++) -+ gamma[i] = readl(par->df_regs + DF_PDR); -+} -+ - void lx_set_mode(struct fb_info *info) - { - struct lxfb_par *par = info->par; -@@ -313,6 +358,7 @@ void lx_set_mode(struct fb_info *info) - int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; - - /* Unlock the DC registers */ -+ readl(par->dc_regs + DC_UNLOCK); - writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); - - lx_graphics_disable(info); -@@ -483,54 +529,408 @@ void lx_set_palette_reg(struct fb_info * - writel(val, par->dc_regs + DC_PAL_DATA); - } - -+static int lx_blank_mode = FB_BLANK_UNBLANK; -+ - int lx_blank_display(struct fb_info *info, int blank_mode) - { - struct lxfb_par *par = info->par; -- u32 dcfg, fp_pm; -- int blank, hsync, vsync; -+ u32 dcfg, val; -+ -+ if (blank_mode == lx_blank_mode) -+ return 0; -+ -+ writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); -+ -+ if (lx_blank_mode == FB_BLANK_POWERDOWN) { -+ val = readl(par->df_regs + DF_FP_PM); -+ writel(val | DF_FP_PM_P, par->df_regs + DF_FP_PM); -+ val = readl(par->df_regs + DF_MISC) & ~DF_MISC_DAC_PWRDN; -+ writel(val, par->df_regs + DF_MISC); -+ -+ val = readl(par->dc_regs + DC_GENERAL_CFG) | DC_GCFG_DFLE; -+ writel(val, par->dc_regs + DC_GENERAL_CFG); -+ -+ val = readl(par->dc_regs + DC_DISPLAY_CFG) | DC_DCFG_TGEN; -+ writel(val, par->dc_regs + DC_DISPLAY_CFG); -+ } -+ -+ dcfg = readl(par->df_regs + DF_DISPLAY_CFG); - - /* CRT power saving modes. */ - switch (blank_mode) { - case FB_BLANK_UNBLANK: -- blank = 0; hsync = 1; vsync = 1; -+ dcfg |= DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN; -+ dcfg |= DF_DCFG_DAC_BL_EN; - break; - case FB_BLANK_NORMAL: -- blank = 1; hsync = 1; vsync = 1; -+ dcfg |= DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN; -+ dcfg |= DF_DCFG_DAC_BL_EN; - break; - case FB_BLANK_VSYNC_SUSPEND: -- blank = 1; hsync = 1; vsync = 0; -+ dcfg |= DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | DF_DCFG_DAC_BL_EN; -+ dcfg &= ~DF_DCFG_VSYNC_EN; - break; - case FB_BLANK_HSYNC_SUSPEND: -- blank = 1; hsync = 0; vsync = 1; -+ dcfg |= DF_DCFG_CRT_EN | DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN; -+ dcfg &= ~DF_DCFG_HSYNC_EN; - break; - case FB_BLANK_POWERDOWN: -- blank = 1; hsync = 0; vsync = 0; -+ dcfg &= ~DF_DCFG_DAC_BL_EN; -+ dcfg &= ~(DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN); - break; - default: -+ writel(0, par->dc_regs + DC_UNLOCK); - return -EINVAL; - } - -- dcfg = readl(par->df_regs + DF_DISPLAY_CFG); -- dcfg &= ~(DF_DCFG_DAC_BL_EN -- | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN); -- if (!blank) -- dcfg |= DF_DCFG_DAC_BL_EN; -- if (hsync) -- dcfg |= DF_DCFG_HSYNC_EN; -- if (vsync) -- dcfg |= DF_DCFG_VSYNC_EN; -- writel(dcfg, par->df_regs + DF_DISPLAY_CFG); -+ /* Turn off the engine when we are in power down mode */ -+ if (blank_mode == FB_BLANK_POWERDOWN) { -+ val = readl(par->df_regs + DF_MISC) | DF_MISC_DAC_PWRDN; -+ writel(val, par->df_regs + DF_MISC); -+ -+ val = readl(par->dc_regs + DC_DISPLAY_CFG); -+ val &= ~DC_DCFG_TGEN; -+ writel(val, par->dc_regs + DC_DISPLAY_CFG); -+ -+ udelay(1000); -+ -+ val = readl(par->dc_regs + DC_GENERAL_CFG) & ~DC_GCFG_DFLE; -+ writel(val, par->dc_regs + DC_GENERAL_CFG); -+ -+ val = readl(par->df_regs + DF_FP_PM); -+ writel(val & ~DF_FP_PM_P, par->df_regs + DF_FP_PM); -+ } - -+ writel(0, par->dc_regs + DC_UNLOCK); -+ -+ lx_blank_mode = blank_mode; -+ return 0; -+} -+ -+static struct geoderegs saved_regs; -+ -+static void lx_save_regs(struct fb_info *info, struct geoderegs *regs) -+{ -+ struct lxfb_par *par = info->par; -+ int i; -+ u32 filt; -+ -+ /* Wait for the command buffer to empty */ -+ while(!(readl(par->gp_regs + 0x44) & (1 << 4))); -+ -+ /* Unlock the DC */ -+ writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); -+ -+ rdmsrl(MSR_LX_DF_PADSEL, regs->msr.padsel); -+ rdmsrl(MSR_LX_GLCP_DOTPLL, regs->msr.dotpll); -+ rdmsrl(MSR_LX_DF_GLCONFIG, regs->msr.dfglcfg); -+ rdmsrl(MSR_LX_DC_SPARE, regs->msr.dcspare); -+ -+ writel(0x4758, par->dc_regs + 0x00); -+ -+ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE); -+ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE); -+ memcpy(regs->vp.b, par->df_regs, VP_REG_SIZE); -+ memcpy(regs->fp.b, par->df_regs + VP_FP_START, FP_REG_SIZE); -+ -+ /* Save the palette */ -+ writel(0, par->dc_regs + 0x70); - /* Power on/off flat panel */ -+ for(i = 0; i < DC_PAL_SIZE; i++) -+ regs->pal[i] = readl(par->dc_regs + 0x74); - -- if (par->output & OUTPUT_PANEL) { -- fp_pm = readl(par->df_regs + DF_FP_PM); -- if (blank_mode == FB_BLANK_POWERDOWN) -- fp_pm &= ~DF_FP_PM_P; -- else -- fp_pm |= DF_FP_PM_P; -- writel(fp_pm, par->df_regs + DF_FP_PM); -+ /* save the filter coefficients */ -+ -+ filt = readl(par->dc_regs + 0x94); -+ filt |= DC_IRQFILT_H_FILT_SEL; -+ -+ for(i = 0; i < DC_HFILT_SIZE; i++) { -+ writel((filt & 0xFFFFFF00) | i, par->dc_regs + 0x94); -+ regs->hcoeff[i << 1] = readl(par->dc_regs + 0x98); -+ regs->hcoeff[(i << 1) + 1] = readl(par->dc_regs + 0x9c); -+ } -+ -+ filt &= ~DC_IRQFILT_H_FILT_SEL; -+ -+ for(i = 0; i < DC_VFILT_SIZE; i++) { -+ writel((filt & 0xFFFFFF00) | i, par->dc_regs + 0x94); -+ regs->vcoeff[i] = readl(par->dc_regs + 0x98); - } - -+ /* Save the vg filter coefficients */ -+ for(i = 0; i < VP_COEFF_COUNT; i++) -+ regs->vp_coeff[i] = -+ readl(par->df_regs + 0x1000 + (i << 2)); -+ -+ /* Save the VP gamma */ -+ -+ writel(0, par->df_regs + 0x38); -+ -+ for(i = 0; i <= 0xFF; i++) -+ regs->gamma[i] = readl(par->df_regs + 0x40); -+} -+ -+static void lx_restore_dc(struct lxfb_par *par, struct geoderegs *regs) -+{ -+ u32 filt; -+ int i; -+ -+ /* Unlock the registers */ -+ writel(DC_UNLOCK_CODE, par->dc_regs + 0x00); -+ -+ /* Restore the framebuffer offset */ -+ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84); -+ -+ /* Blank the configuration registers while we restore */ -+ writel(0, par->dc_regs + 0x04); -+ writel(0, par->dc_regs + 0x08); -+ -+ /* Restore the bulk of the registers */ -+ -+ writel(regs->dc.r.arb, par->dc_regs + 0x0C); -+ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10); -+ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14); -+ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18); -+ -+ /* skip 0x1c */ -+ -+ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20); -+ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24); -+ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28); -+ -+ writel(regs->dc.r.dctop, par->dc_regs + 0x2c); -+ writel(regs->dc.r.line_size, par->dc_regs + 0x30); -+ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34); -+ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38); -+ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40); -+ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44); -+ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48); -+ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50); -+ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54); -+ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58); -+ writel(regs->dc.r.fbactive, par->dc_regs + 0x5c); -+ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60); -+ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64); -+ -+ /* skip 0x68, 0x6c, 0x70, 0x74, 0x78, 0x7c */ -+ -+ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80); -+ -+ /* 0x84 was written above */ -+ -+ writel(regs->dc.r.dv_ctl | 0x01, par->dc_regs + 0x88); -+ writel(regs->dc.r.gfx_scale, par->dc_regs + 0x90); -+ writel(regs->dc.r.irq_filt_ctl, par->dc_regs + 0x94); -+ -+ /* skip 0x98, 0x9c */ -+ -+ writel(regs->dc.r.vbi_event_ctl, par->dc_regs + 0xA0); -+ writel(regs->dc.r.vbi_odd_ctl, par->dc_regs + 0xA4); -+ writel(regs->dc.r.vbi_hor, par->dc_regs + 0xA8); -+ writel(regs->dc.r.vbi_ln_odd, par->dc_regs + 0xAC); -+ writel(regs->dc.r.vbi_ln_event, par->dc_regs + 0xB0); -+ writel(regs->dc.r.vbi_pitch, par->dc_regs + 0xB4); -+ writel(regs->dc.r.clr_key, par->dc_regs + 0xB8); -+ writel(regs->dc.r.clr_key_mask, par->dc_regs + 0xBC); -+ writel(regs->dc.r.clr_key_x, par->dc_regs + 0xC0); -+ writel(regs->dc.r.clr_key_y, par->dc_regs + 0xC4); -+ writel(regs->dc.r.irq, par->dc_regs + 0xC8); -+ writel(regs->dc.r.genlk_ctrl, par->dc_regs + 0xD4); -+ writel(regs->dc.r.vid_even_y_st_offset, par->dc_regs + 0xD8); -+ writel(regs->dc.r.vid_even_u_st_offset, par->dc_regs + 0xDC); -+ writel(regs->dc.r.vid_even_v_st_offset, par->dc_regs + 0xE0); -+ writel(regs->dc.r.v_active_even_timing, par->dc_regs + 0xE4); -+ writel(regs->dc.r.v_blank_even_timing, par->dc_regs + 0xE8); -+ writel(regs->dc.r.v_sync_even_timing, par->dc_regs + 0xEC); -+ -+ /* Restore the palette */ -+ writel(0, par->dc_regs + 0x70); -+ -+ for(i = 0; i < DC_PAL_SIZE; i++) -+ writel(regs->pal[i], par->dc_regs + 0x74); -+ -+ /* Restore the horizontal filter coefficients */ -+ filt = readl(par->dc_regs + 0x94); -+ filt |= DC_IRQFILT_H_FILT_SEL; -+ -+ for(i = 0; i < DC_HFILT_SIZE; i++) { -+ writel(((filt & 0xFFFFFF00) | i), par->dc_regs + 0x94); -+ writel(regs->hcoeff[i << 1], par->dc_regs + 0x98); -+ writel(regs->hcoeff[(i << 1) + 1], par->dc_regs + 0x9c); -+ } -+ -+ filt &= ~DC_IRQFILT_H_FILT_SEL; -+ -+ for(i = 0; i < DC_VFILT_SIZE; i++) { -+ writel(((filt & 0xFFFFFF00) | i), par->dc_regs + 0x94); -+ writel(regs->vcoeff[i], par->dc_regs + 0x98); -+ } -+ -+ /* Turn on the dotpll */ -+ lx_set_dotpll((u32) (regs->msr.dotpll >> 32)); -+ -+ /* Restore MSRs */ -+ wrmsrl(MSR_LX_DC_SPARE, regs->msr.dcspare); -+ -+ /* Restore the configuration registers */ -+ -+ writel(regs->dc.r.dcfg, par->dc_regs + 0x08); -+ writel(regs->dc.r.gcfg, par->dc_regs + 0x04); -+ -+ /* Lock the DC again */ -+ writel(0, par->dc_regs + 0x00); -+} -+ -+static void lx_restore_vp(struct lxfb_par *par, struct geoderegs *regs) -+{ -+ u32 val; -+ int i; -+ -+ /* Restore MSRs */ -+ -+ wrmsrl(MSR_LX_DF_GLCONFIG, regs->msr.dfglcfg); -+ wrmsrl(MSR_LX_DF_PADSEL, regs->msr.padsel); -+ -+ /* Restore the registers */ -+ -+ writel((u32) regs->vp.r.vx, par->df_regs + 0x10); -+ writel((u32) regs->vp.r.vy, par->df_regs + 0x18); -+ writel((u32) regs->vp.r.vs, par->df_regs + 0x20); -+ writel((u32) regs->vp.r.vck, par->df_regs + 0x28); -+ writel((u32) regs->vp.r.vcm, par->df_regs + 0x30); -+ /* skip 0x38 and 0x40 */ -+ writel((u32) regs->vp.r.slr, par->df_regs + 0x48); -+ writel((u32) regs->vp.r.misc, par->df_regs + 0x50); -+ /* skip 0x58 */ -+ writel((u32) regs->vp.r.vys, par->df_regs + 0x60); -+ writel((u32) regs->vp.r.vxs, par->df_regs + 0x68); -+ writel((u32) regs->vp.r.vde, par->df_regs + 0x98); -+ writel((u32) regs->vp.r.cck, par->df_regs + 0xA0); -+ writel((u32) regs->vp.r.ccm, par->df_regs + 0xA8); -+ writel((u32) regs->vp.r.cc1, par->df_regs + 0xB0); -+ writel((u32) regs->vp.r.cc2, par->df_regs + 0xB8); -+ writel((u32) regs->vp.r.a1x, par->df_regs + 0xC0); -+ writel((u32) regs->vp.r.a1y, par->df_regs + 0xC8); -+ writel((u32) regs->vp.r.a1c, par->df_regs + 0xD0); -+ writel((u32) regs->vp.r.a1t, par->df_regs + 0xD8); -+ writel((u32) regs->vp.r.a2x, par->df_regs + 0xE0); -+ writel((u32) regs->vp.r.a2y, par->df_regs + 0xE8); -+ writel((u32) regs->vp.r.a2c, par->df_regs + 0xF0); -+ writel((u32) regs->vp.r.a2t, par->df_regs + 0xF8); -+ writel((u32) regs->vp.r.a3x, par->df_regs + 0x100); -+ writel((u32) regs->vp.r.a3y, par->df_regs + 0x108); -+ writel((u32) regs->vp.r.a3c, par->df_regs + 0x110); -+ writel((u32) regs->vp.r.a3t, par->df_regs + 0x118); -+ writel((u32) regs->vp.r.vrr, par->df_regs + 0x120); -+ writel((u32) regs->vp.r.vye, par->df_regs + 0x138); -+ writel((u32) regs->vp.r.a1ye, par->df_regs + 0x140); -+ writel((u32) regs->vp.r.a2ye, par->df_regs + 0x148); -+ writel((u32) regs->vp.r.a3ye, par->df_regs + 0x150); -+ -+ /* Panel */ -+ -+ writel((u32) regs->fp.r.pt1, par->df_regs + 0x400); -+ writel((u32) regs->fp.r.pt2, par->df_regs + 0x408); -+ writel((u32) regs->fp.r.dfc, par->df_regs + 0x418); -+ -+ /* Restore panel power */ -+ -+ val = readl(par->df_regs + 0x410); -+ -+ if (regs->fp.r.pm & (1 << 24)) { -+ if (!(val & 0x09)) -+ writel(regs->fp.r.pm, par->df_regs + 0x410); -+ } -+ else { -+ if (!(val & 0x05)) -+ writel(regs->fp.r.pm, par->df_regs + 0x410); -+ } -+ -+ /* Restore the vp palette */ -+ -+ writel(0, par->df_regs + 0x38); -+ -+ for(i = 0; i <= 0xFF; i++) -+ writel((u32) regs->gamma[i], par->df_regs + 0x40); -+ -+ /* Restore filter coefficients */ -+ -+ for(i = 0; i < VP_COEFF_COUNT; i++) -+ writel(regs->vp_coeff[i], -+ par->df_regs + 0x1000 + (i << 2)); -+ -+ /* Restore the configuration registers */ -+ -+ writel((u32) regs->vp.r.dcfg, par->df_regs + 0x08); -+ writel((u32) regs->vp.r.vcfg, par->df_regs + 0x00); -+} -+ -+static void lx_restore_gp(struct lxfb_par *par, struct geoderegs *regs) -+{ -+ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00); -+ writel(regs->gp.r.src_offset, par->gp_regs + 0x04); -+ writel(regs->gp.r.stride, par->gp_regs + 0x08); -+ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C); -+ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10); -+ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14); -+ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18); -+ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C); -+ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20); -+ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24); -+ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28); -+ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C); -+ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30); -+ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34); -+ -+ /* Writing to these registers would cause a blt to happen */ -+ /* 0x38, 0x3c, 0x40 */ -+ -+ /* Status register (0x44) is read only */ -+ -+ writel(regs->gp.r.hst_src, par->gp_regs + 0x48); -+ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c); -+ writel(regs->gp.r.cmd_top, par->gp_regs + 0x50); -+ writel(regs->gp.r.cmd_bot, par->gp_regs + 0x54); -+ writel(regs->gp.r.cmd_read, par->gp_regs + 0x58); -+ writel(regs->gp.r.cmd_write, par->gp_regs + 0x5C); -+ writel(regs->gp.r.ch3_offset, par->gp_regs + 0x60); -+ writel(regs->gp.r.ch3_mode_str, par->gp_regs + 0x64); -+ writel(regs->gp.r.ch3_width, par->gp_regs + 0x6C); -+ writel(regs->gp.r.ch3_hsrc, par->gp_regs + 0x70); -+ -+ writel(regs->gp.r.int_cntrl, par->gp_regs + 0x70); -+} -+ -+static void lx_restore_regs(struct fb_info *info, struct geoderegs *regs) -+{ -+ struct lxfb_par *par = info->par; -+ -+ lx_restore_gp(par, regs); -+ lx_restore_vp(par, regs); -+ lx_restore_dc(par, regs); -+} -+ -+static int lx_power_on = 1; -+ -+int lx_shutdown(struct fb_info *info) -+{ -+ if (lx_power_on == 0) -+ return 0; -+ -+ lx_save_regs(info, &saved_regs); -+ lx_graphics_disable(info); -+ -+ lx_power_on = 0; -+ return 0; -+} -+ -+int lx_powerup(struct fb_info *info) -+{ -+ if (lx_power_on == 1) -+ return 0; -+ -+ lx_restore_regs(info, &saved_regs); -+ -+ lx_power_on = 1; - return 0; - } -Index: linux-2.6.24.7/drivers/video/geode/Makefile -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/Makefile -+++ linux-2.6.24.7/drivers/video/geode/Makefile -@@ -5,5 +5,5 @@ obj-$(CONFIG_FB_GEODE_GX) += gxfb.o - obj-$(CONFIG_FB_GEODE_LX) += lxfb.o - - gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o --gxfb-objs := gxfb_core.o display_gx.o video_gx.o -+gxfb-objs := gxfb_core.o display_gx.o video_gx.o suspend_gx.o - lxfb-objs := lxfb_core.o lxfb_ops.o -Index: linux-2.6.24.7/drivers/video/geode/suspend_gx.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/video/geode/suspend_gx.c -@@ -0,0 +1,272 @@ -+#include -+#include -+#include -+ -+#include "geodefb.h" -+#include "video_gx.h" -+ -+void gx_set_dotpll(struct fb_info *info, struct geoderegs *regs) -+{ -+ int timeout = 1000; -+ -+ u64 rstpll, dotpll; -+ -+ rdmsrl(MSR_GLCP_SYS_RSTPLL, rstpll); -+ rdmsrl(MSR_GLCP_DOTPLL, dotpll); -+ -+ dotpll &= 0x00000000ffffffffull; -+ dotpll |= regs->msr.dotpll & 0xffffffff00000000ull; -+ -+ dotpll |= MSR_GLCP_DOTPLL_DOTRESET; -+ dotpll &= ~MSR_GLCP_DOTPLL_BYPASS; -+ -+ wrmsrl(MSR_GLCP_DOTPLL, dotpll); -+ -+ rstpll |= (regs->msr.rstpll & -+ ( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 | -+ MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 | -+ MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)); -+ -+ wrmsrl(MSR_GLCP_SYS_RSTPLL, rstpll); -+ dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET); -+ wrmsrl(MSR_GLCP_DOTPLL, dotpll); -+ -+ do { -+ rdmsrl(MSR_GLCP_DOTPLL, dotpll); -+ } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK)); -+} -+ -+/* FIXME: Make sure nothing is read to clear */ -+ -+void gx_save_regs(struct fb_info *info, struct geoderegs *regs) -+{ -+ struct geodefb_par *par = info->par; -+ int i; -+ -+ /* Wait for the BLT engine to stop being busy */ -+ while(readl(par->gp_regs + 0x44) & 0x05); -+ -+ rdmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel); -+ rdmsrl(MSR_GLCP_DOTPLL, regs->msr.dotpll); -+ rdmsrl(MSR_GLCP_SYS_RSTPLL, regs->msr.rstpll); -+ -+ writel(0x4758, par->dc_regs + 0x00); -+ -+ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE); -+ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE); -+ memcpy(regs->vp.b, par->vid_regs, VP_REG_SIZE); -+ memcpy(regs->fp.b, par->vid_regs + 0x400, FP_REG_SIZE); -+ -+ /* Save the palettes */ -+ writel(0, par->dc_regs + 0x70); -+ -+ for(i = 0; i < DC_PAL_SIZE; i++) -+ regs->pal[i] = readl(par->dc_regs + 0x74); -+ -+ writel(0, par->vid_regs + 0x38); -+ -+ for(i = 0; i < 0xFF; i++) -+ regs->gamma[i] = readl(par->vid_regs + 0x40); -+} -+ -+void gx_restore_regs(struct fb_info *info, struct geoderegs *regs) -+{ -+ struct geodefb_par *par = info->par; -+ u32 val, i; -+ -+ /* DOTPLL */ -+ gx_set_dotpll(info, regs); -+ -+ /* GP */ -+ -+ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00); -+ writel(regs->gp.r.src_offset, par->gp_regs + 0x04); -+ writel(regs->gp.r.stride, par->gp_regs + 0x08); -+ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C); -+ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10); -+ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14); -+ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18); -+ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C); -+ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20); -+ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24); -+ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28); -+ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C); -+ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30); -+ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34); -+ -+ /* Don't write the raster / vector / blt mode regs */ -+ /* status register is read only */ -+ -+ writel(regs->gp.r.hst_src, par->gp_regs + 0x48); -+ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c); -+ -+ /* DC */ -+ -+ /* Write the unlock value */ -+ writel(0x4758, par->dc_regs + 0x00); -+ -+ writel(0, par->dc_regs + 0x70); -+ -+ for(i = 0; i < DC_PAL_SIZE; i++) -+ writel(regs->pal[i], par->dc_regs + 0x74); -+ -+ /* Write the gcfg register without the enables */ -+ writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04); -+ -+ /* Write the vcfg register without the enables */ -+ writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08); -+ -+ /* Write the rest of the active registers */ -+ -+ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10); -+ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14); -+ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18); -+ writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C); -+ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20); -+ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24); -+ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28); -+ writel(regs->dc.r.line_size, par->dc_regs + 0x30); -+ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34); -+ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38); -+ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40); -+ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44); -+ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48); -+ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50); -+ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54); -+ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58); -+ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60); -+ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64); -+ writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68); -+ -+ /* Don't write the line_cnt or diag registers */ -+ -+ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80); -+ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84); -+ writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C); -+ -+ /* VP */ -+ -+ /* MSR */ -+ wrmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel); -+ -+ writel(0, par->vid_regs + 0x38); -+ -+ for(i = 0; i < 0xFF; i++) -+ writel((u32) regs->gamma[i], par->vid_regs + 0x40); -+ -+ /* Don't enable video yet */ -+ writel((u32) regs->vp.r.vcfg & ~0x01, par->vid_regs + 0x00); -+ -+ /* Don't enable the CRT yet */ -+ writel((u32) regs->vp.r.dcfg & ~0x0F, par->vid_regs + 0x08); -+ -+ /* Write the rest of the VP registers */ -+ -+ writel((u32) regs->vp.r.vx, par->vid_regs + 0x10); -+ writel((u32) regs->vp.r.vy, par->vid_regs + 0x18); -+ writel((u32) regs->vp.r.vs, par->vid_regs + 0x20); -+ writel((u32) regs->vp.r.vck, par->vid_regs + 0x28); -+ writel((u32) regs->vp.r.vcm, par->vid_regs + 0x30); -+ writel((u32) regs->vp.r.misc, par->vid_regs + 0x50); -+ writel((u32) regs->vp.r.ccs, par->vid_regs + 0x58); -+ writel((u32) regs->vp.r.vdc, par->vid_regs + 0x78); -+ writel((u32) regs->vp.r.vco, par->vid_regs + 0x80); -+ writel((u32) regs->vp.r.crc, par->vid_regs + 0x88); -+ writel((u32) regs->vp.r.vde, par->vid_regs + 0x98); -+ writel((u32) regs->vp.r.cck, par->vid_regs + 0xA0); -+ writel((u32) regs->vp.r.ccm, par->vid_regs + 0xA8); -+ writel((u32) regs->vp.r.cc1, par->vid_regs + 0xB0); -+ writel((u32) regs->vp.r.cc2, par->vid_regs + 0xB8); -+ writel((u32) regs->vp.r.a1x, par->vid_regs + 0xC0); -+ writel((u32) regs->vp.r.a1y, par->vid_regs + 0xC8); -+ writel((u32) regs->vp.r.a1c, par->vid_regs + 0xD0); -+ writel((u32) regs->vp.r.a1t, par->vid_regs + 0xD8); -+ writel((u32) regs->vp.r.a2x, par->vid_regs + 0xE0); -+ writel((u32) regs->vp.r.a2y, par->vid_regs + 0xE8); -+ writel((u32) regs->vp.r.a2c, par->vid_regs + 0xF0); -+ writel((u32) regs->vp.r.a2t, par->vid_regs + 0xF8); -+ writel((u32) regs->vp.r.a3x, par->vid_regs + 0x100); -+ writel((u32) regs->vp.r.a3y, par->vid_regs + 0x108); -+ writel((u32) regs->vp.r.a3c, par->vid_regs + 0x110); -+ writel((u32) regs->vp.r.a3t, par->vid_regs + 0x118); -+ writel((u32) regs->vp.r.vrr, par->vid_regs + 0x120); -+ -+ -+ /* FP registers */ -+ -+ writel((u32) regs->fp.r.pt1, par->vid_regs + 0x400); -+ writel((u32) regs->fp.r.pt2, par->vid_regs + 0x408); -+ -+ writel((u32) regs->fp.r.dfc, par->vid_regs + 0x418); -+ writel(regs->fp.r.blfsr, par->vid_regs + 0x420); -+ writel(regs->fp.r.rlfsr, par->vid_regs + 0x428); -+ writel(regs->fp.r.fmi, par->vid_regs + 0x430); -+ writel(regs->fp.r.fmd, par->vid_regs + 0x438); -+ writel(regs->fp.r.dca, par->vid_regs + 0x448); -+ writel(regs->fp.r.dmd, par->vid_regs + 0x450); -+ writel(regs->fp.r.crc, par->vid_regs + 0x458); -+ writel(regs->fp.r.fbb, par->vid_regs + 0x460); -+ -+ /* Final enables */ -+ -+ val = readl(par->vid_regs + 0x410); -+ -+ /* Control the panel */ -+ if (regs->fp.r.pm & (1 << 24)) { -+ -+ if (!(val & 0x09)) -+ writel(regs->fp.r.pm, par->vid_regs + 0x410); -+ } -+ else { -+ if (!(val & 0x05)) -+ writel(regs->fp.r.pm, par->vid_regs + 0x410); -+ } -+ -+ /* Turn everything on */ -+ -+ writel(regs->dc.r.gcfg, par->dc_regs + 0x04); -+ writel((u32) regs->vp.r.vcfg, par->vid_regs + 0x00); -+ writel((u32) regs->vp.r.dcfg, par->vid_regs + 0x08); -+ writel(regs->dc.r.dcfg, par->dc_regs + 0x08); -+} -+ -+ -+#ifdef DEBUG -+ -+void dump_regs(struct fb_info *info, int mode) { -+ -+ struct geodefb_par *par = info->par; -+ u32 val; -+ int i; -+ -+ if (mode == 0) { -+ for(i = 0; i < GP_REG_SIZE; i += 4) { -+ val = readl(par->gp_regs + i); -+ } -+ } -+ -+ if (mode == 1) { -+ writel(0x4758, par->dc_regs + 0x00); -+ -+ for(i = 0; i < DC_REG_SIZE; i += 4) { -+ val = readl(par->dc_regs + i); -+ printk("DC%x: %x\n", i, val); -+ } -+ } -+ -+ if (mode == 2) { -+ for(i = 0; i < VP_REG_SIZE; i += 8) { -+ val = readl(par->vid_regs + i); -+ printk("VP%x: %x\n", i, val); -+ } -+ } -+ -+ if (mode == 3) { -+ for(i = 0; i < FP_REG_SIZE; i += 8) { -+ val = readl(par->vid_regs + 0x400 + i); -+ printk("FP%x: %x\n", i, val); -+ } -+ } -+} -+ -+#endif -Index: linux-2.6.24.7/drivers/video/geode/video_gx.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/video_gx.c -+++ linux-2.6.24.7/drivers/video/geode/video_gx.c -@@ -16,10 +16,14 @@ - #include - #include - #include -+#include - - #include "geodefb.h" - #include "video_gx.h" -+#include "display_gx.h" - -+/* This structure is used to store the saved registers during suspend */ -+static struct geoderegs gx_saved_regs; - - /* - * Tables of register settings for various DOTCLKs. -@@ -58,7 +62,7 @@ static const struct gx_pll_entry gx_pll_ - { 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */ - { 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */ - { 13333, 0, 0x00000052 }, /* 75.0000 */ -- { 12698, 0, 0x00000056 }, /* 78.7500 */ -+ { 12698, 0, 0x00000056 }, /* 78.7500 */ - { 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */ - { 11135, PREMULT2, 0x00000262 }, /* 89.8000 */ - { 10582, 0, 0x000002D2 }, /* 94.5000 */ -@@ -117,8 +121,9 @@ static const struct gx_pll_entry gx_pll_ - { 4357, 0, 0x0000057D }, /* 229.5000 */ - }; - --static void gx_set_dclk_frequency(struct fb_info *info) -+void gx_set_dclk_frequency(struct fb_info *info) - { -+ struct geodefb_par *par = info->par; - const struct gx_pll_entry *pll_table; - int pll_table_len; - int i, best_i; -@@ -173,115 +178,169 @@ static void gx_set_dclk_frequency(struct - do { - rdmsrl(MSR_GLCP_DOTPLL, dotpll); - } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK)); -+ -+ par->curdclk = pll_table[best_i].dotpll_value; - } - --static void --gx_configure_tft(struct fb_info *info) -+/* Find out the current clock - we will use this information to avoid -+ re-programming it if we don't need to */ -+ -+unsigned int gx_get_dclk(struct fb_info *info) - { -- struct geodefb_par *par = info->par; -- unsigned long val; -- unsigned long fp; -+ const struct gx_pll_entry *pll_table; -+ int pll_table_len; -+ u64 dotpll; -+ int i; - -- /* Set up the DF pad select MSR */ -+ if (cpu_data(0).x86_mask == 1) { -+ pll_table = gx_pll_table_14MHz; -+ pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz); -+ } else { -+ pll_table = gx_pll_table_48MHz; -+ pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz); -+ } - -- rdmsrl(GX_VP_MSR_PAD_SELECT, val); -- val &= ~GX_VP_PAD_SELECT_MASK; -- val |= GX_VP_PAD_SELECT_TFT; -- wrmsrl(GX_VP_MSR_PAD_SELECT, val); -+ rdmsrl(MSR_GLCP_DOTPLL, dotpll); - -- /* Turn off the panel */ -+ for(i = 0; i < pll_table_len; i++) { -+ if (pll_table[i].dotpll_value == (u32) (dotpll >> 32)) -+ break; -+ } -+ -+ return (i == pll_table_len) ? 0 : pll_table[i].pixclock; -+} - -- fp = readl(par->vid_regs + GX_FP_PM); -- fp &= ~GX_FP_PM_P; -- writel(fp, par->vid_regs + GX_FP_PM); - -- /* Set timing 1 */ -+#define CMP(val, mask, res) (((val) & (mask)) == (res)) - -- fp = readl(par->vid_regs + GX_FP_PT1); -- fp &= GX_FP_PT1_VSIZE_MASK; -- fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT; -- writel(fp, par->vid_regs + GX_FP_PT1); -+static void -+gx_configure_tft(struct fb_info *info) { - -- /* Timing 2 */ -- /* Set bits that are always on for TFT */ -+ struct geodefb_par *par = info->par; -+ u32 val, fp = 0, fp1, fp2, sync = 0; - -- fp = 0x0F100000; -+ /* Set up the DF pad select MSR */ - -- /* Add sync polarity */ -+ rdmsrl(GX_VP_MSR_PAD_SELECT, val); -+ -+ if ((val & GX_VP_PAD_SELECT_MASK) != GX_VP_PAD_SELECT_TFT) { -+ val &= ~GX_VP_PAD_SELECT_MASK; -+ val |= GX_VP_PAD_SELECT_TFT; -+ wrmsrl(GX_VP_MSR_PAD_SELECT, val); -+ } - - if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) -- fp |= GX_FP_PT2_VSP; -+ sync |= GX_FP_PT2_VSP; - - if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) -- fp |= GX_FP_PT2_HSP; -+ sync |= GX_FP_PT2_HSP; - -- writel(fp, par->vid_regs + GX_FP_PT2); -+ /* We only need to turn off the panel if something changed */ - -- /* Set the dither control */ -- writel(0x70, par->vid_regs + GX_FP_DFC); -+ fp1 = readl(par->vid_regs + GX_FP_PT1); -+ fp2 = readl(par->vid_regs + GX_FP_PT2); -+ -+ if (!CMP(fp1, GX_FP_PT1_VSIZE_MASK, info->var.yres << GX_FP_PT1_VSIZE_SHIFT) || -+ (fp2 != (0x0F100000 | sync))) { -+ -+ /* Turn off the panel */ -+ -+#ifdef NOTUSED -+ /* Do we really need to turn off the panel? */ -+ /* Possibly - we have a glitch somewhere */ - -- /* Enable the FP data and power (in case the BIOS didn't) */ -+ fp = readl(par->vid_regs + GX_FP_PM); -+ fp &= ~GX_FP_PM_P; -+ writel(fp, par->vid_regs + GX_FP_PM); -+#endif - -- fp = readl(par->vid_regs + GX_DCFG); -- fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN; -- writel(fp, par->vid_regs + GX_DCFG); -+ /* Timing 1 */ -+ fp1 &= GX_FP_PT1_VSIZE_MASK; -+ fp1 |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT; -+ writel(fp, par->vid_regs + GX_FP_PT1); - -- /* Unblank the panel */ -+ /* Timing 2 */ -+ writel(0x0F100000 | sync, par->vid_regs + GX_FP_PT2); -+ } -+ -+ /* Set the dither control */ -+ if (readl(par->vid_regs + GX_FP_DFC) != 0x70) { -+ writel(0x70, par->vid_regs + GX_FP_DFC); -+ } -+ -+ /* Turn on the panel */ - - fp = readl(par->vid_regs + GX_FP_PM); -- fp |= GX_FP_PM_P; -- writel(fp, par->vid_regs + GX_FP_PM); -+ -+ if (!(fp & 0x09)) -+ writel(fp | GX_FP_PM_P, par->vid_regs + GX_FP_PM); - } - -+#define DCFG_DEFAULT_VAL GX_DCFG_CRT_SYNC_SKW_DFLT | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN | \ -+GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN -+ - static void gx_configure_display(struct fb_info *info) - { - struct geodefb_par *par = info->par; -- u32 dcfg, misc; -+ u32 dcfg, misc, sync = 0; - - /* Set up the MISC register */ -- - misc = readl(par->vid_regs + GX_MISC); - -- /* Power up the DAC */ -- misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); -+ /* We leave gamma enabled if it was already enabled. -+ Although the hardware enables it without setting -+ up the gamma table, the BIOS or bootloader ought -+ to have either disabled it or loaded a table by now */ - -- /* Disable gamma correction */ -- misc |= GX_MISC_GAM_EN; - -- writel(misc, par->vid_regs + GX_MISC); - -- /* Write the display configuration */ -- dcfg = readl(par->vid_regs + GX_DCFG); -+ if (par->enable_crt) { -+ /* Power up the CRT DACs */ -+ if (misc & ( GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN)) { -+ misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); -+ writel(misc, par->vid_regs + GX_MISC); -+ } - -- /* Disable hsync and vsync */ -- dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); -- writel(dcfg, par->vid_regs + GX_DCFG); -+ if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) -+ sync |= GX_DCFG_CRT_HSYNC_POL; - -- /* Clear bits from existing mode. */ -- dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK -- | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL -- | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); -+ if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) -+ sync |= GX_DCFG_CRT_VSYNC_POL; -+ } -+ else { -+ /* Turn off the CRT DACs in FP mode - we don't need them */ -+ if ((misc & (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN))) { -+ misc |= (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); -+ writel(misc, par->vid_regs + GX_MISC); -+ } -+ } - -- /* Set default sync skew. */ -- dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT; -+ /* Write the display configuration */ -+ dcfg = readl(par->vid_regs + GX_DCFG); - -- /* Enable hsync and vsync. */ -- dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN; -+ if (!CMP(dcfg, DCFG_DEFAULT_VAL | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL, -+ DCFG_DEFAULT_VAL | sync)) { - -- /* Sync polarities. */ -- if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) -- dcfg |= GX_DCFG_CRT_HSYNC_POL; -- if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) -- dcfg |= GX_DCFG_CRT_VSYNC_POL; -+ /* Disable hsync and vsync */ -+ dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); -+ writel(dcfg, par->vid_regs + GX_DCFG); - -- /* Enable the display logic */ -- /* Set up the DACS to blank normally */ -+ /* Clear bits from existing mode. */ -+ dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK -+ | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL -+ | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); - -- dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN; -+ /* Set default sync skew. */ -+ dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT; - -- /* Enable the external DAC VREF? */ -+ /* Enable hsync and vsync. */ -+ dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN; - -- writel(dcfg, par->vid_regs + GX_DCFG); -+ /* Enable the display logic */ -+ dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN; -+ -+ writel(dcfg, par->vid_regs + GX_DCFG); -+ } - - /* Set up the flat panel (if it is enabled) */ - -@@ -289,6 +348,100 @@ static void gx_configure_display(struct - gx_configure_tft(info); - } - -+int gxfb_powerdown(struct fb_info *info) -+{ -+ struct geodefb_par *par = info->par; -+ -+ /* We're already suspended */ -+ -+ if (par->state != FB_POWER_STATE_ON) -+ return 0; -+ -+ /* Save the registers */ -+ gx_save_regs(info, &gx_saved_regs); -+ -+ /* Shut down the engine */ -+ -+ writel(gx_saved_regs.vp.r.vcfg & ~0x01, par->vid_regs + GX_VCFG); -+ writel(gx_saved_regs.vp.r.dcfg & ~0x0F, par->vid_regs + GX_DCFG); -+ -+ /* Turn off the flat panel unless we are attached to a DCON */ -+ if (!olpc_has_dcon()) -+ writel(gx_saved_regs.fp.r.pm & ~GX_FP_PM_P, par->vid_regs + GX_FP_PM); -+ -+ writel(0x4758, par->dc_regs + DC_UNLOCK); -+ -+ writel(gx_saved_regs.dc.r.gcfg & ~0x0F, -+ par->dc_regs + DC_GENERAL_CFG); -+ -+ writel(gx_saved_regs.dc.r.dcfg & ~0x19, -+ par->dc_regs + DC_DISPLAY_CFG); -+ -+ par->state = FB_POWER_STATE_SUSPEND; -+ -+ return 0; -+} -+ -+int gxfb_powerup(struct fb_info *info) -+{ -+ struct geodefb_par *par = info->par; -+ u32 val; -+ -+ if (par->state == FB_POWER_STATE_SUSPEND) { -+ -+ writel(gx_saved_regs.dc.r.dcfg, -+ par->dc_regs + DC_DISPLAY_CFG); -+ -+ writel(gx_saved_regs.vp.r.vcfg, par->vid_regs + GX_VCFG); -+ writel(gx_saved_regs.vp.r.dcfg, par->vid_regs + GX_DCFG); -+ -+ val = readl(par->vid_regs + GX_FP_PM); -+ -+ /* power up the panel if it needs it; we don't always power it down */ -+ if (!(val & 0x09)) { -+ writel(gx_saved_regs.fp.r.pm, par->vid_regs + GX_FP_PM); -+ mdelay(64); -+ } -+ } -+ -+ /* If the panel is currently on its way up, then wait up to 100ms -+ for it */ -+ -+ if (readl(par->vid_regs + GX_FP_PM) & 0x08) { -+ int i; -+ -+ for(i = 0; i < 10; i++) { -+ if (readl(par->vid_regs + GX_FP_PM) & 0x01) -+ break; -+ -+ mdelay(10); -+ } -+ -+ if (i == 10) -+ printk(KERN_ERR "gxfb: Panel power up timed out\n"); -+ } -+ -+ if (par->state == FB_POWER_STATE_ON) -+ return 0; -+ -+ switch(par->state) { -+ case FB_POWER_STATE_OFF: -+ gx_restore_regs(info, &gx_saved_regs); -+ break; -+ -+ case FB_POWER_STATE_SUSPEND: -+ /* Do this because it will turn on the FIFO which will -+ start the line count */ -+ writel(gx_saved_regs.dc.r.gcfg, -+ par->dc_regs + DC_GENERAL_CFG); -+ writel(0x0, par->dc_regs + DC_UNLOCK); -+ break; -+ } -+ -+ par->state = FB_POWER_STATE_ON; -+ return 0; -+} -+ - static int gx_blank_display(struct fb_info *info, int blank_mode) - { - struct geodefb_par *par = info->par; -@@ -315,6 +468,7 @@ static int gx_blank_display(struct fb_in - default: - return -EINVAL; - } -+ - dcfg = readl(par->vid_regs + GX_DCFG); - dcfg &= ~(GX_DCFG_DAC_BL_EN - | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN); -@@ -326,7 +480,7 @@ static int gx_blank_display(struct fb_in - dcfg |= GX_DCFG_VSYNC_EN; - writel(dcfg, par->vid_regs + GX_DCFG); - -- /* Power on/off flat panel. */ -+ /* Power on/off flat panel */ - - if (par->enable_crt == 0) { - fp_pm = readl(par->vid_regs + GX_FP_PM); -@@ -340,8 +494,37 @@ static int gx_blank_display(struct fb_in - return 0; - } - -+extern struct fb_info *gxfb_info; -+ -+/* This function controls the flatpanel power sequencing - this is used -+ by the OLPC power management engine to enable the FP sequencing much -+ earlier in the resume process -+*/ -+ -+void gxfb_flatpanel_control(int state) -+{ -+ struct geodefb_par *par = gxfb_info->par; -+ u32 val, fp = readl(par->vid_regs + GX_FP_PM); -+ val = fp; -+ -+ /* Turn on the panel if it isn't aleady */ -+ -+ if (state) { -+ if (!(val & 0x01)) -+ val |= GX_FP_PM_P; -+ } -+ else { -+ if (!(val & 0x02)) -+ val &= ~GX_FP_PM_P; -+ } -+ -+ if (val != fp) -+ writel(val, par->vid_regs + GX_FP_PM); -+} -+ - struct geode_vid_ops gx_vid_ops = { - .set_dclk = gx_set_dclk_frequency, -+ .get_dclk = gx_get_dclk, - .configure_display = gx_configure_display, - .blank_display = gx_blank_display, - }; -Index: linux-2.6.24.7/drivers/video/geode/video_gx.h -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/geode/video_gx.h -+++ linux-2.6.24.7/drivers/video/geode/video_gx.h -@@ -11,6 +11,8 @@ - #ifndef __VIDEO_GX_H__ - #define __VIDEO_GX_H__ - -+#include "geode_regs.h" -+ - extern struct geode_vid_ops gx_vid_ops; - - /* GX Flatpanel control MSR */ -@@ -20,6 +22,8 @@ extern struct geode_vid_ops gx_vid_ops; - - /* Geode GX video processor registers */ - -+#define GX_VCFG 0x0000 -+ - #define GX_DCFG 0x0008 - # define GX_DCFG_CRT_EN 0x00000001 - # define GX_DCFG_HSYNC_EN 0x00000002 -@@ -42,6 +46,14 @@ extern struct geode_vid_ops gx_vid_ops; - #define GX_MISC_DAC_PWRDN 0x00000400 - #define GX_MISC_A_PWRDN 0x00000800 - -+/* Gamma correction RAM - address and data registers */ -+ -+#define GX_GAR 0x038 -+#define GX_GDR 0x040 -+ -+#define GXFB_GAMMA_DWORDS 256 /* number of dwords in the gamma ram */ -+#define GXFB_GAMMA_SIZE (GXFB_GAMMA_DWORDS * sizeof(unsigned int)) -+ - /* Geode GX flat panel display control registers */ - - #define GX_FP_PT1 0x0400 -@@ -69,4 +81,13 @@ extern struct geode_vid_ops gx_vid_ops; - # define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull) - # define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull) - -+int gxfb_powerdown(struct fb_info *info); -+int gxfb_powerup(struct fb_info *info); -+ -+void gx_set_dclk_frequency(struct fb_info *info); -+unsigned int gx_get_dclk(struct fb_info *info); -+ -+void gx_save_regs(struct fb_info *info, struct geoderegs *regs); -+void gx_restore_regs(struct fb_info *info, struct geoderegs *regs); -+ - #endif /* !__VIDEO_GX_H__ */ -Index: linux-2.6.24.7/drivers/video/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/Kconfig -+++ linux-2.6.24.7/drivers/video/Kconfig -@@ -1869,6 +1869,15 @@ config FB_PS3_DEFAULT_SIZE_M - The default value can be overridden on the kernel command line - using the "ps3fb" option (e.g. "ps3fb=9M"); - -+config FB_OLPC_DCON -+ tristate "One Laptop Per Child Display CONtroller support" -+ depends on OLPC -+ select I2C -+ ---help--- -+ Add support for the OLPC DCON controller. This controller is only -+ available on OLPC platforms. Unless you have one of these -+ platforms, you will want to say 'N'. -+ - config FB_XILINX - tristate "Xilinx frame buffer support" - depends on FB && XILINX_VIRTEX -Index: linux-2.6.24.7/drivers/video/Makefile -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/Makefile -+++ linux-2.6.24.7/drivers/video/Makefile -@@ -111,6 +111,7 @@ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx - obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o - obj-$(CONFIG_FB_PS3) += ps3fb.o - obj-$(CONFIG_FB_SM501) += sm501fb.o -+obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon.o - obj-$(CONFIG_FB_XILINX) += xilinxfb.o - obj-$(CONFIG_FB_OMAP) += omap/ - -Index: linux-2.6.24.7/drivers/video/modedb.c -=================================================================== ---- linux-2.6.24.7.orig/drivers/video/modedb.c -+++ linux-2.6.24.7/drivers/video/modedb.c -@@ -33,6 +33,8 @@ const char *fb_mode_option; - * Standard video mode definitions (taken from XFree86) - */ - -+#define DEFAULT_MODEDB_INDEX 0 -+ - static const struct fb_videomode modedb[] = { - { - /* 640x400 @ 70 Hz, 31.5 kHz hsync */ -@@ -508,7 +510,8 @@ int fb_find_mode(struct fb_var_screeninf - } - - if (!default_mode) -- default_mode = &db[0]; -+ default_mode = (db == modedb) ? -+ &modedb[DEFAULT_MODEDB_INDEX] : &db[0]; - - if (!default_bpp) - default_bpp = 8; -Index: linux-2.6.24.7/drivers/video/olpc_dcon.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/video/olpc_dcon.c -@@ -0,0 +1,946 @@ -+/* -+ * Mainly by David Woodhouse, somewhat modified by Jordan Crouse -+ * -+ * Copyright © 2006-2007 Red Hat, Inc. -+ * Copyright © 2006-2007 Advanced Micro Devices, Inc. -+ * -+ * This program is free software. You can redistribute it and/or -+ * modify it under the terms of version 2 of the GNU General Public -+ * License as published by the Free Software Foundation. -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "olpc_dcon.h" -+ -+/* Module definitions */ -+ -+static int resumeline = 898; -+module_param(resumeline, int, 0444); -+ -+static int noinit; -+module_param(noinit, int, 0444); -+ -+/* Default off since it doesn't work on DCON ASIC in B-test OLPC board */ -+static int useaa = 1; -+module_param(useaa, int, 0444); -+ -+/* I2C structures */ -+ -+static struct i2c_driver dcon_driver; -+static struct i2c_client *dcon_client; -+ -+/* Platform devices */ -+static struct platform_device *dcon_device; -+ -+/* Backlight device */ -+static struct backlight_device *dcon_bl_dev; -+ -+/* Base address of the GPIO registers */ -+static unsigned long gpio_base; -+ -+static struct fb_info *fbinfo; -+ -+/* Current source, initialized at probe time */ -+static int dcon_source; -+ -+/* Desired source */ -+static int dcon_pending; -+ -+/* Current output type */ -+static int dcon_output = DCON_OUTPUT_COLOR; -+ -+/* Current sleep status (not yet implemented) */ -+static int dcon_sleep_val = DCON_ACTIVE; -+ -+/* Shadow register for the DCON_REG_MODE register */ -+static unsigned short dcon_disp_mode; -+ -+/* Variables used during switches */ -+static int dcon_switched; -+ -+static DECLARE_WAIT_QUEUE_HEAD(dcon_wait_queue); -+ -+static unsigned short normal_i2c[] = { 0x0D, I2C_CLIENT_END }; -+I2C_CLIENT_INSMOD; -+ -+#define dcon_write(reg,val) i2c_smbus_write_word_data(dcon_client,reg,val) -+#define dcon_read(reg) i2c_smbus_read_word_data(dcon_client,reg) -+ -+/* The current backlight value - this saves us some smbus traffic */ -+static int bl_val = -1; -+ -+/* ===== API functions - these are called by a variety of users ==== */ -+ -+static int dcon_request_irq(void); -+ -+static int dcon_hw_init(struct i2c_client *client, int is_init) -+{ -+ uint16_t ver; -+ int rc = 0; -+ -+ ver = i2c_smbus_read_word_data(client, DCON_REG_ID); -+ if ((ver >> 8) != 0xDC) { -+ printk(KERN_ERR "olpc-dcon: DCON ID not 0xDCxx: 0x%04x " -+ "instead.\n", ver); -+ rc = -ENXIO; -+ goto err; -+ } -+ -+ if (is_init) { -+ printk(KERN_INFO "olpc-dcon: Discovered DCON version %x\n", -+ ver & 0xFF); -+ if ((rc = dcon_request_irq())) { -+ printk(KERN_ERR "olpc-dcon: Unable to grab IRQ.\n"); -+ goto err; -+ } -+ } -+ -+ if (ver < 0xdc02 && !noinit) { -+ /* Initialize the DCON registers */ -+ -+ /* Start with work-arounds for DCON ASIC */ -+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc); -+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc); -+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc); -+ i2c_smbus_write_word_data(client, 0x0b, 0x007a); -+ i2c_smbus_write_word_data(client, 0x36, 0x025c); -+ i2c_smbus_write_word_data(client, 0x37, 0x025e); -+ -+ /* Initialise SDRAM */ -+ -+ i2c_smbus_write_word_data(client, 0x3b, 0x002b); -+ i2c_smbus_write_word_data(client, 0x41, 0x0101); -+ i2c_smbus_write_word_data(client, 0x42, 0x0101); -+ } -+ else if (!noinit) { -+ /* SDRAM setup/hold time */ -+ i2c_smbus_write_word_data(client, 0x3a, 0xc040); -+ i2c_smbus_write_word_data(client, 0x41, 0x0000); -+ i2c_smbus_write_word_data(client, 0x41, 0x0101); -+ i2c_smbus_write_word_data(client, 0x42, 0x0101); -+ } -+ -+ /* Colour swizzle, AA, no passthrough, backlight */ -+ if (is_init) { -+ dcon_disp_mode = MODE_PASSTHRU | MODE_BL_ENABLE | MODE_CSWIZZLE; -+ if (useaa) -+ dcon_disp_mode |= MODE_COL_AA; -+ } -+ i2c_smbus_write_word_data(client, DCON_REG_MODE, dcon_disp_mode); -+ -+ -+ /* Set the scanline to interrupt on during resume */ -+ -+ i2c_smbus_write_word_data(client, DCON_REG_SCAN_INT, resumeline); -+ -+err: -+ return rc; -+} -+ -+/* -+ * The smbus doesn't always come back due to what is believed to be -+ * hardware (power rail) bugs. For older models where this is known to -+ * occur, our solution is to attempt to wait for the bus to stabilize; -+ * if it doesn't happen, cut power to the dcon, repower it, and wait -+ * for the bus to stabilize. Rinse, repeat until we have a working -+ * smbus. For newer models, we simply BUG(); we want to know if this -+ * still happens despite the power fixes that have been made! -+ */ -+static int dcon_bus_stabilize(struct i2c_client *client, int is_powered_down) -+{ -+ unsigned long timeout; -+ int x; -+ -+power_up: -+ if (is_powered_down) { -+ x = 1; -+ if ((x = olpc_ec_cmd(0x26, (unsigned char *) &x, 1, NULL, 0))) { -+ printk(KERN_WARNING "olpc-dcon: unable to force dcon " -+ "to power up: %d!\n", x); -+ return x; -+ } -+ msleep(10); /* we'll be conservative */ -+ } -+ -+ /* -+ * According to HiMax, when powering the DCON up we should hold -+ * SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON -+ * state machine to reset to a (sane) initial state. Mitch Bradley -+ * did some testing and discovered that holding for 16 SMB_CLK cycles -+ * worked a lot more reliably, so that's what we do here. -+ * -+ * According to the cs5536 spec, to set GPIO14 to SMB_CLK we must -+ * simultaneously set AUX1 IN/OUT to GPIO14; ditto for SMB_DATA and -+ * GPIO15. -+ */ -+ geode_gpio_set(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_VAL); -+ geode_gpio_set(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_ENABLE); -+ geode_gpio_clear(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1); -+ geode_gpio_clear(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX2); -+ geode_gpio_clear(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1); -+ -+ for (x = 0; x < 16; x++) { -+ udelay(5); -+ geode_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL); -+ udelay(5); -+ geode_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL); -+ } -+ udelay(5); -+ geode_gpio_set(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1); -+ geode_gpio_set(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1); -+ -+ for (x = -1, timeout = 50; timeout && x < 0; timeout--) { -+ msleep(1); -+ x = dcon_read(DCON_REG_ID); -+ } -+ if (x < 0) { -+ printk(KERN_ERR "olpc-dcon: unable to stabilize dcon's " -+ "smbus, reasserting power and praying.\n"); -+ BUG_ON(olpc_board_at_least(olpc_board(0xc2))); -+ x = 0; -+ olpc_ec_cmd(0x26, (unsigned char *) &x, 1, NULL, 0); -+ msleep(100); -+ is_powered_down = 1; -+ goto power_up; /* argh, stupid hardware.. */ -+ } -+ -+ if (is_powered_down) -+ return dcon_hw_init(client, 0); -+ return 0; -+} -+ -+ -+/* Backlight notes - turning off the backlight enable bit in the DCON -+ * doesn't save us any power over just pushing the BL to zero, so we -+ * don't use that bit in this code. -+ */ -+ -+static int dcon_get_backlight(void) -+{ -+ if (dcon_client == NULL) -+ return 0; -+ -+ if (bl_val == -1) -+ bl_val = dcon_read(DCON_REG_BRIGHT) & 0x0F; -+ -+ return bl_val; -+} -+ -+static void dcon_set_backlight(int level) -+{ -+ if (dcon_client == NULL) -+ return; -+ -+ if (bl_val == (level & 0x0F)) -+ return; -+ -+ bl_val = level & 0x0F; -+ dcon_write(DCON_REG_BRIGHT, bl_val); -+ -+ /* Purposely turn off the backlight when we go to level 0 */ -+ -+ if (bl_val == 0) { -+ dcon_disp_mode &= ~MODE_BL_ENABLE; -+ dcon_write(DCON_REG_MODE, dcon_disp_mode); -+ } -+ else if (!(dcon_disp_mode & MODE_BL_ENABLE)) { -+ dcon_disp_mode |= MODE_BL_ENABLE; -+ dcon_write(DCON_REG_MODE, dcon_disp_mode); -+ } -+} -+ -+/* Set the output type to either color or mono */ -+ -+static int dcon_set_output(int arg) -+{ -+ if (dcon_output == arg) -+ return 0; -+ -+ dcon_output = arg; -+ -+ if (arg == DCON_OUTPUT_MONO) { -+ dcon_disp_mode &= ~(MODE_CSWIZZLE | MODE_COL_AA); -+ dcon_disp_mode |= MODE_MONO_LUMA; -+ } -+ else { -+ dcon_disp_mode &= ~(MODE_MONO_LUMA); -+ dcon_disp_mode |= MODE_CSWIZZLE; -+ if (useaa) -+ dcon_disp_mode |= MODE_COL_AA; -+ } -+ -+ dcon_write(DCON_REG_MODE, dcon_disp_mode); -+ return 0; -+} -+ -+/* For now, this will be really stupid - we need to address how -+ * DCONLOAD works in a sleep and account for it accordingly -+ */ -+ -+static void dcon_sleep(int state) -+{ -+ int x; -+ -+ /* Turn off the backlight and put the DCON to sleep */ -+ -+ if (state == dcon_sleep_val) -+ return; -+ -+ if (!olpc_board_at_least(olpc_board(0xc2))) -+ return; -+ -+ if (state == DCON_SLEEP) { -+ x = 0; -+ if ((x = olpc_ec_cmd(0x26, (unsigned char *) &x, 1, NULL, 0))) -+ printk(KERN_WARNING "olpc-dcon: unable to force dcon " -+ "to power down: %d!\n", x); -+ else -+ dcon_sleep_val = state; -+ } -+ else { -+ /* Only re-enable the backlight if the backlight value is set */ -+ if (bl_val != 0) -+ dcon_disp_mode |= MODE_BL_ENABLE; -+ -+ if ((x=dcon_bus_stabilize(dcon_client, 1))) -+ printk(KERN_WARNING "olpc-dcon: unable to reinit dcon" -+ " hardware: %d!\n", x); -+ else -+ dcon_sleep_val = state; -+ } -+ -+ /* We should turn off some stuff in the framebuffer - but what? */ -+} -+ -+/* Set the source of the display (CPU or DCON) */ -+ -+static void dcon_source_switch(struct work_struct *work) -+{ -+ DECLARE_WAITQUEUE(wait, current); -+ int source = dcon_pending; -+ -+ if (dcon_source == source) -+ return; -+ -+ dcon_switched = 0; -+ -+ switch (source) { -+ case DCON_SOURCE_CPU: -+ -+ /* Enable the scanline interrupt bit */ -+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode | MODE_SCAN_INT)) -+ printk(KERN_ERR "olpc-dcon: couldn't enable scanline interrupt!\n"); -+ else { -+ /* Wait up to one second for the scanline interrupt */ -+ wait_event_timeout(dcon_wait_queue, dcon_switched == 1, HZ); -+ } -+ -+ if (!dcon_switched) -+ printk(KERN_ERR "olpc-dcon: Timeout entering CPU mode; expect a screen glitch.\n"); -+ -+ /* -+ * Ideally we'd like to disable interrupts here so that the -+ * fb unblanking and DCON turn on happen at a known time value; -+ * however, we can't do that right now with fb_blank -+ * messing with semaphores. -+ * -+ * For now, we just hope.. -+ */ -+ acquire_console_sem(); -+ if (fb_blank(fbinfo, FB_BLANK_UNBLANK)) { -+ release_console_sem(); -+ printk(KERN_ERR "olpc-dcon: Failed to enter CPU mode\n"); -+ dcon_pending = DCON_SOURCE_DCON; -+ return; -+ } -+ release_console_sem(); -+ -+ /* And turn off the DCON */ -+ outl(1<<11, gpio_base + GPIOx_OUT_VAL); -+ -+ /* Turn off the scanline interrupt */ -+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode)) -+ printk(KERN_ERR "olpc-dcon: couldn't disable scanline interrupt!\n"); -+ -+ printk(KERN_INFO "olpc-dcon: The CPU has control\n"); -+ break; -+ case DCON_SOURCE_DCON: -+ { -+ int t; -+ -+ add_wait_queue(&dcon_wait_queue, &wait); -+ set_current_state(TASK_UNINTERRUPTIBLE); -+ -+ /* Clear GPIO11 (DCONLOAD) - this implies that the DCON is in -+ control */ -+ -+ outl(1 << (11 + 16), gpio_base + GPIOx_OUT_VAL); -+ -+ t = schedule_timeout(HZ/2); -+ remove_wait_queue(&dcon_wait_queue, &wait); -+ set_current_state(TASK_RUNNING); -+ -+ if (!dcon_switched) -+ printk(KERN_ERR "olpc-dcon: Timeout entering DCON mode; expect a screen glitch.\n"); -+ -+ acquire_console_sem(); -+ if (fb_blank(fbinfo, FB_BLANK_POWERDOWN)) -+ printk(KERN_ERR "olpc-dcon: couldn't blank fb!\n"); -+ release_console_sem(); -+ -+ printk(KERN_INFO "olpc-dcon: The DCON has control\n"); -+ break; -+ } -+ default: -+ BUG(); -+ } -+ -+ dcon_source = source; -+} -+ -+static DECLARE_WORK(dcon_work, dcon_source_switch); -+ -+static int dcon_set_source(int arg) -+{ -+ if (arg != DCON_SOURCE_CPU && arg != DCON_SOURCE_DCON) -+ return -EINVAL; -+ -+ if (dcon_pending == arg) -+ return 0; -+ -+ dcon_pending = arg; -+ if ((dcon_source != arg) && !work_pending(&dcon_work)) -+ schedule_work(&dcon_work); -+ -+ return 0; -+} -+ -+static int dcon_set_source_sync(int arg) -+{ -+ int ret = dcon_set_source(arg); -+ if (!ret) -+ flush_scheduled_work(); -+ return ret; -+} -+ -+static int dconbl_set(struct backlight_device *dev) { -+ -+ int level = dev->props.brightness; -+ -+ if (dev->props.power != FB_BLANK_UNBLANK) -+ level = 0; -+ -+ dcon_set_backlight(level); -+ return 0; -+} -+ -+static int dconbl_get(struct backlight_device *dev) { -+ return dcon_get_backlight(); -+} -+ -+static ssize_t dcon_mode_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%4.4X\n", dcon_disp_mode); -+} -+ -+static ssize_t dcon_sleep_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", dcon_sleep_val); -+} -+ -+static ssize_t /* __deprecated */ dcon_source_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n"); -+ return sprintf(buf, "%d\n", dcon_source); -+} -+ -+static ssize_t dcon_freeze_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", dcon_source == DCON_SOURCE_DCON ? 1 : 0); -+} -+ -+static ssize_t dcon_output_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", dcon_output); -+} -+ -+static ssize_t dcon_resumeline_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", resumeline); -+} -+ -+static int _strtoul(const char *buf, int len, unsigned int *val) -+{ -+ -+ char *endp; -+ unsigned int output = simple_strtoul(buf, &endp, 0); -+ int size = endp - buf; -+ -+ if (*endp && isspace(*endp)) -+ size++; -+ -+ if (size != len) -+ return -EINVAL; -+ -+ *val = output; -+ return 0; -+} -+ -+static ssize_t dcon_output_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int output; -+ int rc = -EINVAL; -+ -+ if (_strtoul(buf, count, &output)) -+ return -EINVAL; -+ -+ if (output == DCON_OUTPUT_COLOR || output == DCON_OUTPUT_MONO) { -+ dcon_set_output(output); -+ rc = count; -+ } -+ -+ return rc; -+} -+ -+static ssize_t /* __deprecated */ dcon_source_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int output; -+ int rc = -EINVAL; -+ -+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n"); -+ if (_strtoul(buf, count, &output)) -+ return -EINVAL; -+ -+ dcon_set_source(output); -+ rc = count; -+ -+ return rc; -+} -+ -+static ssize_t dcon_freeze_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int output; -+ int rc = -EINVAL; -+ -+ if (_strtoul(buf, count, &output)) -+ return rc; -+ -+ dcon_set_source(output ? DCON_SOURCE_DCON : DCON_SOURCE_CPU); -+ rc = count; -+ -+ return rc; -+} -+ -+static ssize_t dcon_resumeline_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int rl; -+ int rc = -EINVAL; -+ -+ if (_strtoul(buf, count, &rl)) -+ return rc; -+ -+ resumeline = rl; -+ dcon_write(DCON_REG_SCAN_INT, resumeline); -+ rc = count; -+ -+ return rc; -+} -+ -+static ssize_t dcon_sleep_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int output; -+ -+ if (_strtoul(buf, count, &output)) -+ return -EINVAL; -+ -+ dcon_sleep(output ? DCON_SLEEP : DCON_ACTIVE); -+ return count; -+} -+ -+static struct device_attribute dcon_device_files[] = { -+ __ATTR(mode, 0444, dcon_mode_show, NULL), -+ __ATTR(sleep, 0644, dcon_sleep_show, dcon_sleep_store), -+ __ATTR(source, 0644, dcon_source_show, dcon_source_store), -+ __ATTR(freeze, 0644, dcon_freeze_show, dcon_freeze_store), -+ __ATTR(output, 0644, dcon_output_show, dcon_output_store), -+ __ATTR(resumeline, 0644, dcon_resumeline_show, dcon_resumeline_store), -+}; -+ -+static struct backlight_ops dcon_bl_ops = { -+ .get_brightness = dconbl_get, -+ .update_status = dconbl_set -+}; -+ -+/* List of GPIOs that we care about: -+ (in) GPIO12 -- DCONBLNK -+ (in) GPIO[56] -- DCONSTAT[01] -+ (out) GPIO11 -- DCONLOAD -+*/ -+ -+#define IN_GPIOS ((1<<5) | (1<<6) | (1<<7) | (1<<12)) -+#define OUT_GPIOS (1<<11) -+ -+static irqreturn_t dcon_interrupt(int, void *); -+ -+static int dcon_request_irq(void) -+{ -+ unsigned long lo, hi; -+ unsigned char lob; -+ -+ rdmsr(MSR_LBAR_GPIO, lo, hi); -+ -+ /* Check the mask and whether GPIO is enabled (sanity check) */ -+ if (hi != 0x0000f001) { -+ printk(KERN_ERR "GPIO not enabled -- cannot use DCON\n"); -+ return -ENODEV; -+ } -+ -+ /* Mask off the IO base address */ -+ gpio_base = lo & 0x0000ff00; -+ -+ /* Turn off the event enable for GPIO7 just to be safe */ -+ outl(1 << (16+7), gpio_base + GPIOx_EVNT_EN); -+ -+ /* Set the directions for the GPIO pins */ -+ outl(OUT_GPIOS | (IN_GPIOS << 16), gpio_base + GPIOx_OUT_EN); -+ outl(IN_GPIOS | (OUT_GPIOS << 16), gpio_base + GPIOx_IN_EN); -+ -+ /* Set up the interrupt mappings */ -+ -+ /* Set the IRQ to pair 2 */ -+ geode_gpio_event_irq(OLPC_GPIO_DCON_IRQ, 2); -+ -+ /* Enable group 2 to trigger the DCON interrupt */ -+ geode_gpio_set_irq(2, DCON_IRQ); -+ -+ /* Select edge level for interrupt (in PIC) */ -+ -+ lob = inb(0x4d0); -+ lob &= ~(1 << DCON_IRQ); -+ outb(lob, 0x4d0); -+ -+ /* Register the interupt handler */ -+ if (request_irq(DCON_IRQ, &dcon_interrupt, 0, "DCON", &dcon_driver)) -+ return -EIO; -+ -+ /* Clear INV_EN for GPIO7 (DCONIRQ) */ -+ outl((1<<(16+7)), gpio_base + GPIOx_INV_EN); -+ -+ /* Enable filter for GPIO12 (DCONBLANK) */ -+ outl(1<<(12), gpio_base + GPIOx_IN_FLTR_EN); -+ -+ /* Disable filter for GPIO7 */ -+ outl(1<<(16+7), gpio_base + GPIOx_IN_FLTR_EN); -+ -+ /* Disable event counter for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */ -+ -+ outl(1<<(16+7), gpio_base + GPIOx_EVNTCNT_EN); -+ outl(1<<(16+12), gpio_base + GPIOx_EVNTCNT_EN); -+ -+ /* Add GPIO12 to the Filter Event Pair #7 */ -+ outb(12, gpio_base + GPIO_FE7_SEL); -+ -+ /* Turn off negative Edge Enable for GPIO12 */ -+ outl(1<<(16+12), gpio_base + GPIOx_NEGEDGE_EN); -+ -+ /* Enable negative Edge Enable for GPIO7 */ -+ outl(1<<7, gpio_base + GPIOx_NEGEDGE_EN); -+ -+ /* Zero the filter amount for Filter Event Pair #7 */ -+ outw(0, gpio_base + GPIO_FLT7_AMNT); -+ -+ /* Clear the negative edge status for GPIO7 and GPIO12 */ -+ outl((1<<7) | (1<<12), gpio_base+0x4c); -+ -+ /* FIXME: Clear the posiitive status as well, just to be sure */ -+ outl((1<<7) | (1<<12), gpio_base+0x48); -+ -+ /* Enable events for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */ -+ outl((1<<(7))|(1<<12), gpio_base + GPIOx_EVNT_EN); -+ -+ /* Determine the current state by reading the GPIO bit */ -+ /* Earlier stages of the boot process have established the state */ -+ dcon_source = inl(gpio_base + GPIOx_OUT_VAL) & (1<<11) -+ ? DCON_SOURCE_CPU -+ : DCON_SOURCE_DCON; -+ dcon_pending = dcon_source; -+ -+ return 0; -+} -+ -+static int dcon_reboot_notify(struct notifier_block *nb, unsigned long foo, void *bar) -+{ -+ if (dcon_client == NULL) -+ return 0; -+ -+ /* Turn off the DCON. Entirely. */ -+ dcon_write(DCON_REG_MODE, 0x39); -+ dcon_write(DCON_REG_MODE, 0x32); -+ return 0; -+} -+ -+static int dcon_conswitch_notify(struct notifier_block *nb, -+ unsigned long mode, void *dummy) -+{ -+ if (mode == CONSOLE_EVENT_SWITCH_TEXT) -+ dcon_sleep(DCON_ACTIVE); -+ -+ return 0; -+} -+ -+static struct notifier_block dcon_nb = { -+ .notifier_call = dcon_reboot_notify, -+ .priority = -1, -+}; -+ -+static struct notifier_block dcon_console_nb = { -+ .notifier_call = dcon_conswitch_notify, -+ .priority = -1, -+}; -+ -+static int unfreeze_on_panic(struct notifier_block *nb, unsigned long e, void *p) -+{ -+ outl(1<<11, gpio_base + GPIOx_OUT_VAL); -+ return NOTIFY_DONE; -+} -+ -+static struct notifier_block dcon_panic_nb = { -+ .notifier_call = unfreeze_on_panic, -+}; -+ -+static int dcon_probe(struct i2c_adapter *adap, int addr, int kind) -+{ -+ struct i2c_client *client; -+ int rc, i; -+ -+ if (!olpc_has_dcon()) { -+ printk("olpc-dcon: No DCON is attached.\n"); -+ return -ENODEV; -+ } -+ -+ if (num_registered_fb >= 1) -+ fbinfo = registered_fb[0]; -+ -+ if (adap->id != I2C_HW_SMBUS_SCX200) { -+ printk(KERN_ERR "olpc-dcon: Invalid I2C bus (%d not %d)\n", -+ adap->id, I2C_HW_SMBUS_SCX200); -+ return -ENXIO; -+ } -+ -+ client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL); -+ if (client == NULL) -+ return -ENOMEM; -+ -+ strncpy(client->name, "OLPC-DCON", I2C_NAME_SIZE); -+ client->addr = addr; -+ client->adapter = adap; -+ client->driver = &dcon_driver; -+ -+ if ((rc = i2c_attach_client(client)) != 0) { -+ printk(KERN_ERR "olpc-dcon: Unable to attach the I2C client.\n"); -+ goto eclient; -+ } -+ -+ rc = dcon_hw_init(client, 1); -+ if (rc) -+ goto ei2c; -+ -+ /* Add the DCON device */ -+ -+ dcon_device = platform_device_alloc("dcon", -1); -+ -+ if (dcon_device == NULL) { -+ printk(KERN_ERR "dcon: Unable to create the DCON device\n"); -+ rc = -ENOMEM; -+ goto eirq; -+ } -+ -+ if ((rc = platform_device_add(dcon_device))) { -+ printk(KERN_ERR "dcon: Unable to add the DCON device\n"); -+ goto edev; -+ } -+ -+ for(i = 0; i < ARRAY_SIZE(dcon_device_files); i++) -+ device_create_file(&dcon_device->dev, &dcon_device_files[i]); -+ -+ /* Add the backlight device for the DCON */ -+ -+ dcon_client = client; -+ -+ dcon_bl_dev = backlight_device_register("dcon-bl", &dcon_device->dev, -+ NULL, &dcon_bl_ops); -+ -+ if (IS_ERR(dcon_bl_dev)) { -+ printk(KERN_INFO "Could not register the backlight device for the DCON (%ld)\n", PTR_ERR(dcon_bl_dev)); -+ dcon_bl_dev = NULL; -+ } -+ else { -+ dcon_bl_dev->props.max_brightness = 15; -+ dcon_bl_dev->props.power = FB_BLANK_UNBLANK; -+ dcon_bl_dev->props.brightness = dcon_get_backlight(); -+ -+ backlight_update_status(dcon_bl_dev); -+ } -+ -+ register_reboot_notifier(&dcon_nb); -+ console_event_register(&dcon_console_nb); -+ atomic_notifier_chain_register(&panic_notifier_list, &dcon_panic_nb); -+ -+ return 0; -+ -+ edev: -+ platform_device_unregister(dcon_device); -+ dcon_device = NULL; -+ eirq: -+ free_irq(DCON_IRQ, &dcon_driver); -+ ei2c: -+ i2c_detach_client(client); -+ eclient: -+ kfree(client); -+ -+ return rc; -+} -+ -+static int dcon_attach(struct i2c_adapter *adap) -+{ -+ int ret; -+ -+ ret = i2c_probe(adap, &addr_data, dcon_probe); -+ -+ if (dcon_client == NULL) -+ printk(KERN_ERR "olpc-dcon: No DCON found on SMBus\n"); -+ -+ return ret; -+} -+ -+static int dcon_detach(struct i2c_client *client) -+{ -+ int rc; -+ dcon_client = NULL; -+ -+ unregister_reboot_notifier(&dcon_nb); -+ console_event_unregister(&dcon_console_nb); -+ atomic_notifier_chain_unregister(&panic_notifier_list, &dcon_panic_nb); -+ -+ free_irq(DCON_IRQ, &dcon_driver); -+ -+ if ((rc = i2c_detach_client(client)) == 0) -+ kfree(i2c_get_clientdata(client)); -+ -+ if (dcon_bl_dev != NULL) -+ backlight_device_unregister(dcon_bl_dev); -+ -+ if (dcon_device != NULL) -+ platform_device_unregister(dcon_device); -+ cancel_work_sync(&dcon_work); -+ -+ return rc; -+} -+ -+ -+#ifdef CONFIG_PM -+static int dcon_suspend(struct i2c_client *client, pm_message_t state) -+{ -+ if (dcon_sleep_val != DCON_ACTIVE) -+ return 0; -+ -+ /* Set up the DCON to have the source */ -+ return dcon_set_source_sync(DCON_SOURCE_DCON); -+} -+ -+static int dcon_resume(struct i2c_client *client) -+{ -+ if (dcon_sleep_val != DCON_ACTIVE) -+ return 0; -+ -+ dcon_bus_stabilize(client, 0); -+ -+ return dcon_set_source(DCON_SOURCE_CPU); -+} -+ -+#endif -+ -+static irqreturn_t dcon_interrupt(int irq, void *id) -+{ -+ int status = inl(gpio_base + GPIOx_READ_BACK) >> 5; -+ -+ /* Clear the negative edge status for GPIO7 */ -+ outl(1 << 7, gpio_base + GPIOx_NEGEDGE_STS); -+ -+ switch (status & 3) { -+ case 3: -+ printk(KERN_DEBUG "olpc-dcon: DCONLOAD_MISSED interrupt\n"); -+ break; -+ case 2: /* switch to DCON mode */ -+ case 1: /* switch to CPU mode */ -+ dcon_switched = 1; -+ wake_up(&dcon_wait_queue); -+ break; -+ case 0: -+ printk(KERN_DEBUG "olpc-dcon: scanline interrupt w/CPU\n"); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static struct i2c_driver dcon_driver = { -+ .driver = { -+ .name = "OLPC-DCON", -+ }, -+ .id = I2C_DRIVERID_DCON, -+ .attach_adapter = dcon_attach, -+ .detach_client = dcon_detach, -+#ifdef CONFIG_PM -+ .suspend = dcon_suspend, -+ .resume = dcon_resume, -+#endif -+}; -+ -+ -+static int __init olpc_dcon_init(void) -+{ -+ i2c_add_driver(&dcon_driver); -+ return 0; -+} -+ -+static void __exit olpc_dcon_exit(void) -+{ -+ i2c_del_driver(&dcon_driver); -+} -+ -+module_init(olpc_dcon_init); -+module_exit(olpc_dcon_exit); -+ -+MODULE_LICENSE("GPL"); -Index: linux-2.6.24.7/drivers/video/olpc_dcon.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/drivers/video/olpc_dcon.h -@@ -0,0 +1,75 @@ -+#ifndef OLPC_DCON_H_ -+#define OLPC_DCON_H_ -+ -+/* DCON registers */ -+ -+#define DCON_REG_ID 0 -+#define DCON_REG_MODE 1 -+ -+#define MODE_PASSTHRU (1<<0) -+#define MODE_SLEEP (1<<1) -+#define MODE_SLEEP_AUTO (1<<2) -+#define MODE_BL_ENABLE (1<<3) -+#define MODE_BLANK (1<<4) -+#define MODE_CSWIZZLE (1<<5) -+#define MODE_COL_AA (1<<6) -+#define MODE_MONO_LUMA (1<<7) -+#define MODE_SCAN_INT (1<<8) -+#define MODE_CLOCKDIV (1<<9) -+#define MODE_DEBUG (1<<14) -+#define MODE_SELFTEST (1<<15) -+ -+#define DCON_REG_HRES 2 -+#define DCON_REG_HTOTAL 3 -+#define DCON_REG_HSYNC_WIDTH 4 -+#define DCON_REG_VRES 5 -+#define DCON_REG_VTOTAL 6 -+#define DCON_REG_VSYNC_WIDTH 7 -+#define DCON_REG_TIMEOUT 8 -+#define DCON_REG_SCAN_INT 9 -+#define DCON_REG_BRIGHT 10 -+ -+/* GPIO registers (CS5536) */ -+ -+#define MSR_LBAR_GPIO 0x5140000C -+ -+#define GPIOx_OUT_VAL 0x00 -+#define GPIOx_OUT_EN 0x04 -+#define GPIOx_IN_EN 0x20 -+#define GPIOx_INV_EN 0x24 -+#define GPIOx_IN_FLTR_EN 0x28 -+#define GPIOx_EVNTCNT_EN 0x2C -+#define GPIOx_READ_BACK 0x30 -+#define GPIOx_EVNT_EN 0x38 -+#define GPIOx_NEGEDGE_EN 0x44 -+#define GPIOx_NEGEDGE_STS 0x4C -+#define GPIO_FLT7_AMNT 0xD8 -+#define GPIO_MAP_X 0xE0 -+#define GPIO_MAP_Y 0xE4 -+#define GPIO_FE7_SEL 0xF7 -+ -+ -+/* Status values */ -+ -+#define DCONSTAT_SCANINT 0 -+#define DCONSTAT_SCANINT_DCON 1 -+#define DCONSTAT_DISPLAYLOAD 2 -+#define DCONSTAT_MISSED 3 -+ -+/* Source values */ -+ -+#define DCON_SOURCE_DCON 0 -+#define DCON_SOURCE_CPU 1 -+ -+/* Output values */ -+#define DCON_OUTPUT_COLOR 0 -+#define DCON_OUTPUT_MONO 1 -+ -+/* Sleep values */ -+#define DCON_ACTIVE 0 -+#define DCON_SLEEP 1 -+ -+/* Interrupt */ -+#define DCON_IRQ 6 -+ -+#endif -Index: linux-2.6.24.7/fs/jffs2/nodelist.h -=================================================================== ---- linux-2.6.24.7.orig/fs/jffs2/nodelist.h -+++ linux-2.6.24.7/fs/jffs2/nodelist.h -@@ -197,7 +197,7 @@ struct jffs2_inode_cache { - #define RAWNODE_CLASS_XATTR_DATUM 1 - #define RAWNODE_CLASS_XATTR_REF 2 - --#define INOCACHE_HASHSIZE 128 -+#define INOCACHE_HASHSIZE 1024 - - #define write_ofs(c) ((c)->nextblock->offset + (c)->sector_size - (c)->nextblock->free_size) - -Index: linux-2.6.24.7/fs/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/fs/Kconfig -+++ linux-2.6.24.7/fs/Kconfig -@@ -1031,6 +1031,37 @@ config HUGETLBFS - config HUGETLB_PAGE - def_bool HUGETLBFS - -+config PROMFS_FS -+ tristate "PromFS IEEE 1275 file system support" -+ depends on SPARC || PPC || OLPC -+ help -+ PromFS is a file system interface to various IEEE-1275 compatible -+ firmwares. If you have such a firmware (Sparc64, PowerPC, and -+ some other architectures and embedded systems have such firmwares, -+ with names like "OpenBoot (tm)" and "OpenFirmware"), say Y here -+ to be able to access the firmware's device-tree from Linux. -+ -+ The firmware device-tree is available as a virtual file system, -+ can be mounted under /prom with the command "mount -t promfs -+ none /prom". -+ -+ To compile PromFS support as a module, choose M here; the module -+ will be called promfs. If unsure, choose M. -+ -+config RAMFS -+ bool -+ default y -+ ---help--- -+ Ramfs is a file system which keeps all files in RAM. It allows -+ read and write access. -+ -+ It is more of an programming example than a useable file system. If -+ you need a file system which lives in RAM with limit checking use -+ tmpfs. -+ -+ To compile this as a module, choose M here: the module will be called -+ ramfs. -+ - config CONFIGFS_FS - tristate "Userspace-driven configuration filesystem (EXPERIMENTAL)" - depends on SYSFS && EXPERIMENTAL -Index: linux-2.6.24.7/fs/Makefile -=================================================================== ---- linux-2.6.24.7.orig/fs/Makefile -+++ linux-2.6.24.7/fs/Makefile -@@ -110,6 +110,7 @@ obj-$(CONFIG_ADFS_FS) += adfs/ - obj-$(CONFIG_FUSE_FS) += fuse/ - obj-$(CONFIG_UDF_FS) += udf/ - obj-$(CONFIG_SUN_OPENPROMFS) += openpromfs/ -+obj-$(CONFIG_PROMFS_FS) += promfs/ - obj-$(CONFIG_JFS_FS) += jfs/ - obj-$(CONFIG_XFS_FS) += xfs/ - obj-$(CONFIG_9P_FS) += 9p/ -Index: linux-2.6.24.7/fs/promfs/Makefile -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/fs/promfs/Makefile -@@ -0,0 +1 @@ -+obj-$(CONFIG_PROMFS_FS) += promfs.o -Index: linux-2.6.24.7/fs/promfs/promfs.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/fs/promfs/promfs.c -@@ -0,0 +1,295 @@ -+/* -+ * promfs.c - generic inode/dentry functions for IEEE 1275-based filesystems. -+ * -+ * This is based heavily upon prior ieee1275 and other virtual filesystems -+ * implementations; openpromfs, proc_devtree.c, oprofilefs, procfs, ... -+ * -+ * Copyright (C) 2007 Andres Salomon -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+#include -+#include -+#include -+#include -+//#include -+#include -+ -+#define PROMFS_MAGIC 0x1f2f3fff -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Andres Salomon"); -+ -+struct promfs_inode -+{ -+ struct inode ino; -+ struct property *prop; -+}; -+ -+static inline struct promfs_inode *to_promfs_inode(struct inode *inode) -+{ -+ return container_of(inode, struct promfs_inode, ino); -+} -+ -+#if 0 -+static DEFINE_SPINLOCK(promfs_lock); -+ -+static struct of_node *of_tree = NULL; -+static DEFINE_RWLOCK(of_tree_lock); -+ -+void __init of_build_tree(void) -+{ -+ -+ -+} -+#endif -+ -+static int promfs_open_file(struct inode *inode, struct file *file) -+{ -+ struct promfs_inode *ino; -+ -+ ino = to_promfs_inode(inode); -+ if (!ino->prop) -+ return -EIO; -+ file->private_data = ino->prop; -+ -+ return 0; -+} -+ -+static ssize_t promfs_read_file(struct file *file, char __user *data, -+ size_t len, loff_t *ppos) -+{ -+ struct property *prop = (struct property *) file->private_data; -+ return simple_read_from_buffer(data, len, ppos, prop->value, -+ prop->length); -+} -+ -+static ssize_t promfs_write_file(struct file *file, char const __user *buf, -+ size_t count, loff_t * offset) -+{ -+ /* TODO.... 'cause, y'know, it would be nice. */ -+ return -EIO; -+} -+ -+static struct file_operations promfs_file_ops = { -+ .open = promfs_open_file, -+ .read = promfs_read_file, -+ .write = promfs_write_file, -+}; -+ -+static struct kmem_cache *promfs_inode_cachep; -+ -+static struct inode *promfs_alloc_inode(struct super_block *sb) -+{ -+ struct promfs_inode *pr_ino; -+ -+ pr_ino = kmem_cache_alloc(promfs_inode_cachep, GFP_KERNEL); -+ if (!pr_ino) -+ return NULL; -+ pr_ino->prop = NULL; -+ -+ return &pr_ino->ino; -+} -+ -+static void promfs_destroy_inode(struct inode *inode) -+{ -+ kmem_cache_free(promfs_inode_cachep, to_promfs_inode(inode)); -+} -+ -+static void promfs_read_inode(struct inode *inode) -+{ -+ inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME; -+} -+ -+static int promfs_remount(struct super_block *sb, int *flags, char *data) -+{ -+ *flags |= MS_NOATIME; -+ return 0; -+} -+ -+static struct super_operations promfs_s_ops = { -+ .alloc_inode = promfs_alloc_inode, -+ .destroy_inode = promfs_destroy_inode, -+ .read_inode = promfs_read_inode, -+ .statfs = simple_statfs, -+ .drop_inode = generic_delete_inode, -+ .remount_fs = promfs_remount, -+}; -+ -+static struct inode *promfs_get_inode(struct super_block *sb, int mode) -+{ -+ struct inode *inode = new_inode(sb); -+ -+ if (inode) { -+ inode->i_mode = mode; -+ inode->i_uid = 0; -+ inode->i_gid = 0; -+ inode->i_blocks = 0; -+ inode->i_atime = inode->i_mtime = inode->i_ctime = CURRENT_TIME; -+ } -+ -+ return inode; -+} -+ -+static int promfs_create_file(struct super_block *sb, struct dentry *root, -+ struct property *prop, const struct file_operations *fops) -+{ -+ struct dentry *dentry; -+ struct inode *inode; -+ struct promfs_inode *ino; -+ -+ dentry = d_alloc_name(root, prop->name); -+ if (!dentry) -+ goto err; -+ -+ inode = promfs_get_inode(sb, S_IFREG | 0644); -+ if (!inode) -+ goto err_dput; -+ inode->i_fop = fops; -+ ino = to_promfs_inode(inode); -+ ino->prop = prop; -+ d_add(dentry, inode); -+ -+ return 0; -+ -+err_dput: -+ dput(dentry); -+err: -+ return -EFAULT; -+} -+ -+struct dentry *promfs_create_dir(struct super_block *sb, struct dentry *root, -+ char const *name) -+{ -+ struct dentry *dentry; -+ struct inode *inode; -+ -+ dentry = d_alloc_name(root, name); -+ if (!dentry) -+ goto err; -+ -+ inode = promfs_get_inode(sb, S_IFDIR | 0755); -+ if (!inode) -+ goto err_dput; -+ inode->i_op = &simple_dir_inode_operations; -+ inode->i_fop = &simple_dir_operations; -+ d_add(dentry, inode); -+ return dentry; -+ -+err_dput: -+ dput(dentry); -+err: -+ return NULL; -+} -+ -+void promfs_populate(struct super_block *sb, struct dentry *root, -+ struct device_node *node) -+{ -+ struct dentry *dentry; -+ struct device_node *child; -+ struct property *prop; -+ -+ if (!node) -+ return; -+ -+ for (child = node->child; child; child = child->sibling) { -+ dentry = promfs_create_dir(sb, root, child->path_component_name); -+ promfs_populate(sb, dentry, child); -+ } -+ for (prop = node->properties; prop; prop = prop->next) -+ promfs_create_file(sb, root, prop, &promfs_file_ops); -+} -+ -+static int promfs_fill_super(struct super_block *sb, void *data, int silent) -+{ -+ struct inode *root_inode; -+ struct dentry *root_dentry; -+ struct promfs_inode *inode; -+ -+ sb->s_blocksize = PAGE_CACHE_SIZE; -+ sb->s_blocksize_bits = PAGE_CACHE_SHIFT; -+ sb->s_magic = PROMFS_MAGIC; -+ sb->s_op = &promfs_s_ops; -+ sb->s_time_gran = 1; -+ sb->s_flags |= MS_NOATIME; -+ -+ root_inode = promfs_get_inode(sb, S_IFDIR | 0755); -+ if (!root_inode) -+ goto err; -+ root_inode->i_op = &simple_dir_inode_operations; -+ root_inode->i_fop = &simple_dir_operations; -+ -+ inode = to_promfs_inode(root_inode); -+ -+ root_dentry = d_alloc_root(root_inode); -+ if (!root_dentry) -+ goto err_iput; -+ sb->s_root = root_dentry; -+ -+ promfs_populate(sb, root_dentry, of_find_node_by_path("/")); -+ return 0; -+ -+err_iput: -+ iput(root_inode); -+err: -+ return -ENOMEM; -+} -+ -+static int promfs_get_sb(struct file_system_type *fs_type, int flags, -+ const char *dev_name, void *data, struct vfsmount *mnt) -+{ -+ return get_sb_single(fs_type, flags, data, promfs_fill_super, mnt); -+} -+ -+static struct file_system_type promfs_fs_type = { -+ .owner = THIS_MODULE, -+ .name = "promfs", -+ .get_sb = promfs_get_sb, -+ .kill_sb = kill_litter_super, -+}; -+ -+static void init_once(void *i, struct kmem_cache *cachep, unsigned long fl) -+{ -+ struct promfs_inode *inode = (struct promfs_inode *) i; -+ inode_init_once(&inode->ino); -+} -+ -+static int __init init_promfs(void) -+{ -+ int err; -+ -+ prom_build_devicetree(); -+ promfs_inode_cachep = kmem_cache_create("promfs_inode_cache", -+ sizeof(struct promfs_inode), 0, -+ SLAB_RECLAIM_ACCOUNT|SLAB_MEM_SPREAD, init_once, NULL); -+ if (!promfs_inode_cachep) -+ return -ENOMEM; -+ -+ err = register_filesystem(&promfs_fs_type); -+ if (err) -+ kmem_cache_destroy(promfs_inode_cachep); -+ -+ return err; -+} -+ -+static void __exit exit_promfs(void) -+{ -+ unregister_filesystem(&promfs_fs_type); -+ kmem_cache_destroy(promfs_inode_cachep); -+} -+ -+module_init(init_promfs); -+module_exit(exit_promfs); -Index: linux-2.6.24.7/include/asm-x86/ofw.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/include/asm-x86/ofw.h -@@ -0,0 +1,16 @@ -+/* -+ * Definitions for Open Firmware client interface on 32-bit system. -+ * OF Cell size is 4. Integer properties are encoded big endian, -+ * as with all OF implementations. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+#ifndef _OFW_H -+#define _OFW_H -+ -+extern int ofw(char *, int, int, ...); -+ -+#endif -Index: linux-2.6.24.7/include/asm-x86/olpc.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/include/asm-x86/olpc.h -@@ -0,0 +1,107 @@ -+/* OLPC machine specific definitions */ -+ -+#ifndef ASM_OLPC_H_ -+#define ASM_OLPC_H_ -+ -+#include -+ -+struct olpc_platform_t { -+ int flags; -+ u32 boardrev; -+ int ecver; -+}; -+ -+#define OLPC_F_PRESENT 0x01 -+#define OLPC_F_DCON 0x02 -+#define OLPC_F_VSA 0x04 -+ -+/* -+ * OLPC board IDs contain the major build number within the mask 0x0ff0, -+ * and the minor build number withing 0x000f. Pre-builds have a minor -+ * number less than 8, and normal builds start at 8. For example, 0x0B10 -+ * is a PreB1, and 0x0C18 is a C1. -+ */ -+ -+static inline u32 olpc_board(u8 id) -+{ -+ return (id << 4) | 0x8; -+} -+ -+static inline u32 olpc_board_pre(u8 id) -+{ -+ return id << 4; -+} -+ -+#ifndef CONFIG_OLPC -+ -+static inline int machine_is_olpc(void) { return 0; } -+static inline int olpc_has_dcon(void) { return 0; } -+static inline int olpc_has_vsa(void) { return 0; } -+ -+#else -+ -+extern struct olpc_platform_t olpc_platform_info; -+ -+static inline int -+machine_is_olpc(void) -+{ -+ return (olpc_platform_info.flags & OLPC_F_PRESENT) ? 1 : 0; -+} -+ -+static inline int -+olpc_has_dcon(void) -+{ -+ return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0; -+} -+ -+static inline int -+olpc_has_vsa(void) -+{ -+ return (olpc_platform_info.flags & OLPC_F_VSA) ? 1 : 0; -+} -+ -+static inline int olpc_board_at_least(u32 rev) -+{ -+ return olpc_platform_info.boardrev >= rev; -+} -+ -+#endif -+ -+/* EC functions */ -+ -+int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen, -+ unsigned char *outbuf, size_t outlen); -+ -+void olpc_register_battery_callback(void (*f)(unsigned long)); -+void olpc_deregister_battery_callback(void); -+ -+/* EC commands and responses */ -+ -+/* SCI source values */ -+ -+#define EC_SCI_SRC_EMPTY 0x00 -+#define EC_SCI_SRC_GAME 0x01 -+#define EC_SCI_SRC_BATTERY 0x02 -+#define EC_SCI_SRC_BATSOC 0x04 -+#define EC_SCI_SRC_BATERR 0x08 -+#define EC_SCI_SRC_EBOOK 0x10 -+#define EC_SCI_SRC_WLAN 0x20 -+#define EC_SCI_SRC_ACPWR 0x40 -+#define EC_SCI_SRC_ALL 0x7F -+ -+int olpc_ec_mask_set(u8 bits); -+int olpc_ec_mask_unset(u8 bits); -+ -+/* GPIO assignments */ -+ -+#define OLPC_GPIO_MIC_AC (1 << 1) -+#define OLPC_GPIO_DCON_IRQ (1 << 7) -+#define OLPC_GPIO_THRM_ALRM (1 << 10) -+#define OLPC_GPIO_SMB_CLK (1 << 14) -+#define OLPC_GPIO_SMB_DATA (1 << 15) -+#define OLPC_GPIO_WORKAUX (1 << 24) -+#define OLPC_GPIO_LID (1 << 26) -+#define OLPC_GPIO_ECSCI (1 << 27) -+ -+#endif -+ -Index: linux-2.6.24.7/include/asm-x86/prom.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/include/asm-x86/prom.h -@@ -0,0 +1,108 @@ -+#ifndef _I386_PROM_H -+#define _I386_PROM_H -+#ifdef __KERNEL__ -+ -+ -+/* -+ * Definitions for talking to the Open Firmware PROM on -+ * Power Macintosh computers. -+ * -+ * Copyright (C) 1996-2005 Paul Mackerras. -+ * -+ * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp. -+ * Updates for SPARC64 by David S. Miller -+ * Updates for i386/OLPC by Andres Salomon -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+ -+typedef u32 phandle; -+typedef u32 ihandle; -+ -+struct property { -+ char *name; -+ int length; -+ void *value; -+ struct property *next; -+}; -+ -+struct device_node { -+ const char *name; -+ const char *type; -+ phandle node; -+// phandle linux_phandle; -+ char *path_component_name; -+ char *full_name; -+ -+ struct property *properties; -+ struct property *deadprops; /* removed properties */ -+ struct device_node *parent; -+ struct device_node *child; -+ struct device_node *sibling; -+ struct device_node *next; /* next device of same type */ -+ struct device_node *allnext; /* next in list of all nodes */ -+ struct proc_dir_entry *pde; /* this node's proc directory */ -+ struct kref kref; -+ unsigned long _flags; -+ void *data; -+}; -+ -+/* flag descriptions */ -+#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */ -+ -+#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags) -+#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags) -+ -+#define OF_BAD_ADDR ((u64)-1) -+ -+static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de) -+{ -+ dn->pde = de; -+} -+ -+extern struct device_node *of_find_node_by_name(struct device_node *from, -+ const char *name); -+#define for_each_node_by_name(dn, name) \ -+ for (dn = of_find_node_by_name(NULL, name); dn; \ -+ dn = of_find_node_by_name(dn, name)) -+extern struct device_node *of_find_node_by_type(struct device_node *from, -+ const char *type); -+#define for_each_node_by_type(dn, type) \ -+ for (dn = of_find_node_by_type(NULL, type); dn; \ -+ dn = of_find_node_by_type(dn, type)) -+extern struct device_node *of_find_compatible_node(struct device_node *from, -+ const char *type, const char *compat); -+extern struct device_node *of_find_node_by_path(const char *path); -+extern struct device_node *of_find_node_by_phandle(phandle handle); -+extern struct device_node *of_get_parent(const struct device_node *node); -+extern struct device_node *of_get_next_child(const struct device_node *node, -+ struct device_node *prev); -+extern struct property *of_find_property(const struct device_node *np, -+ const char *name, -+ int *lenp); -+//extern struct device_node *of_node_get(struct device_node *node); -+//extern void of_node_put(struct device_node *node); -+extern int of_device_is_compatible(const struct device_node *device, -+ const char *); -+extern const void *of_get_property(const struct device_node *node, -+ const char *name, -+ int *lenp); -+#define get_property(node,name,lenp) of_get_property(node,name,lenp) -+extern int of_set_property(struct device_node *node, const char *name, void *val, int len); -+extern int of_getintprop_default(struct device_node *np, -+ const char *name, -+ int def); -+extern int of_n_addr_cells(struct device_node *np); -+extern int of_n_size_cells(struct device_node *np); -+ -+extern void prom_build_devicetree(void); -+ -+#endif /* __KERNEL__ */ -+#endif -Index: linux-2.6.24.7/include/linux/battery.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/include/linux/battery.h -@@ -0,0 +1,101 @@ -+/* -+ * Driver model for batteries -+ * -+ * © 2006 David Woodhouse -+ * -+ * Based on LED Class support, by John Lenz and Richard Purdie: -+ * -+ * © 2005 John Lenz -+ * © 2005-2006 Richard Purdie -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#ifndef __LINUX_BATTERY_H__ -+#define __LINUX_BATTERY_H__ -+ -+struct device; -+struct class_device; -+ -+/* -+ * Battery Core -+ */ -+#define PWRDEV_TYPE_BATTERY 0 -+#define PWRDEV_TYPE_AC 1 -+ -+#define BAT_STAT_PRESENT (1<<0) -+#define BAT_STAT_LOW (1<<1) -+#define BAT_STAT_FULL (1<<2) -+#define BAT_STAT_CHARGING (1<<3) -+#define BAT_STAT_DISCHARGING (1<<4) -+#define BAT_STAT_OVERTEMP (1<<5) -+#define BAT_STAT_CRITICAL (1<<6) -+#define BAT_STAT_FIRE (1<<7) -+#define BAT_STAT_CHARGE_DONE (1<<8) -+ -+/* Thou shalt not export any attributes in sysfs except these, and -+ with these units: */ -+#define BAT_INFO_STATUS "status" /* Not free-form. Use -+ provided function */ -+#define BAT_INFO_TEMP1 "temp1" /* °C/1000 */ -+#define BAT_INFO_TEMP1_NAME "temp1_name" /* string */ -+ -+#define BAT_INFO_TEMP2 "temp2" /* °C/1000 */ -+#define BAT_INFO_TEMP2_NAME "temp2_name" /* string */ -+ -+#define BAT_INFO_VOLTAGE "voltage" /* mV */ -+#define BAT_INFO_VOLTAGE_DESIGN "voltage_design" /* mV */ -+ -+#define BAT_INFO_CURRENT "current" /* mA */ -+#define BAT_INFO_CURRENT_NOW "current_now" /* mA */ -+ -+#define BAT_INFO_POWER "power" /* mW */ -+#define BAT_INFO_POWER_NOW "power_now" /* mW */ -+ -+/* The following capacity/charge properties are represented in either -+ mA or mW. The CAP_UNITS property MUST be provided if any of these are. */ -+#define BAT_INFO_RATE "rate" /* CAP_UNITS */ -+#define BAT_INFO_CAP_LEFT "capacity_left" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_DESIGN "capacity_design" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_LAST_FULL "capacity_last_full" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_LOW "capacity_low_thresh" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_WARN "capacity_warn_thresh" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_UNITS "capacity_units" /* string: must be -+ either mA or mW */ -+ -+#define BAT_INFO_CAP_PCT "capacity_percentage" /* integer */ -+ -+#define BAT_INFO_TIME_EMPTY "time_to_empty" /* seconds */ -+#define BAT_INFO_TIME_EMPTY_NOW "time_to_empty_now" /* seconds */ -+#define BAT_INFO_TIME_FULL "time_to_full" /* seconds */ -+#define BAT_INFO_TIME_FULL_NOW "time_to_full_now" /* seconds */ -+ -+#define BAT_INFO_MANUFACTURER "manufacturer" /* string */ -+#define BAT_INFO_TECHNOLOGY "technology" /* string */ -+#define BAT_INFO_MODEL "model" /* string */ -+#define BAT_INFO_SERIAL "serial" /* string */ -+#define BAT_INFO_OEM_INFO "oem_info" /* string */ -+ -+#define BAT_INFO_CYCLE_COUNT "cycle_count" /* integer */ -+#define BAT_INFO_DATE_MFR "date_manufactured" /* YYYY[-MM[-DD]] */ -+#define BAT_INFO_DATE_FIRST_USE "date_first_use" /* YYYY[-MM[-DD]] */ -+ -+struct battery_dev { -+ int status_cap; -+ int id; -+ int type; -+ const char *name; -+ -+ struct device *dev; -+}; -+ -+int battery_device_register(struct device *parent, -+ struct battery_dev *battery_cdev); -+void battery_device_unregister(struct battery_dev *battery_cdev); -+ -+ -+ssize_t battery_attribute_show_status(char *buf, unsigned long status); -+ssize_t battery_attribute_show_ac_status(char *buf, unsigned long status); -+#endif /* __LINUX_BATTERY_H__ */ -Index: linux-2.6.24.7/include/linux/fb.h -=================================================================== ---- linux-2.6.24.7.orig/include/linux/fb.h -+++ linux-2.6.24.7/include/linux/fb.h -@@ -666,6 +666,12 @@ struct fb_ops { - /* restore saved state */ - void (*fb_restore_state)(struct fb_info *info); - -+ /* Shut down the graphics engine to save power */ -+ int (*fb_powerdown)(struct fb_info *info); -+ -+ /* Power it back up */ -+ int (*fb_powerup)(struct fb_info *info); -+ - /* get capability given var */ - void (*fb_get_caps)(struct fb_info *info, struct fb_blit_caps *caps, - struct fb_var_screeninfo *var); -@@ -945,6 +951,9 @@ extern int fb_get_color_depth(struct fb_ - extern int fb_get_options(char *name, char **option); - extern int fb_new_modelist(struct fb_info *info); - -+extern int fb_powerdown(struct fb_info *info); -+extern int fb_powerup(struct fb_info *info); -+ - extern struct fb_info *registered_fb[FB_MAX]; - extern int num_registered_fb; - extern struct class *fb_class; -Index: linux-2.6.24.7/include/linux/i2c-id.h -=================================================================== ---- linux-2.6.24.7.orig/include/linux/i2c-id.h -+++ linux-2.6.24.7/include/linux/i2c-id.h -@@ -125,6 +125,7 @@ - #define I2C_DRIVERID_LM4857 92 /* LM4857 Audio Amplifier */ - #define I2C_DRIVERID_VP27SMPX 93 /* Panasonic VP27s tuner internal MPX */ - #define I2C_DRIVERID_CS4270 94 /* Cirrus Logic 4270 audio codec */ -+#define I2C_DRIVERID_DCON 95 - - #define I2C_DRIVERID_I2CDEV 900 - #define I2C_DRIVERID_ARP 902 /* SMBus ARP Client */ -Index: linux-2.6.24.7/include/linux/isl_38xx.h -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/include/linux/isl_38xx.h -@@ -0,0 +1,127 @@ -+/* -+ * Copyright (C) 2002 Intersil Americas Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _LINUX_ISL_38XX_H -+#define _LINUX_ISL_38XX_H -+ -+#include -+ -+#define ISL38XX_CB_RX_QSIZE 8 -+#define ISL38XX_CB_TX_QSIZE 32 -+ -+/* ISL38XX Access Point Specific definitions */ -+#define ISL38XX_MAX_WDS_LINKS 8 -+ -+/* ISL38xx Client Specific definitions */ -+#define ISL38XX_PSM_ACTIVE_STATE 0 -+#define ISL38XX_PSM_POWERSAVE_STATE 1 -+ -+/* ISL38XX Host Interface Definitions */ -+#define ISL38XX_PCI_MEM_SIZE 0x02000 -+#define ISL38XX_MEMORY_WINDOW_SIZE 0x01000 -+#define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000 -+#define ISL38XX_WRITEIO_DELAY 10 /* in us */ -+#define ISL38XX_RESET_DELAY 50 /* in ms */ -+#define ISL38XX_WAIT_CYCLE 10 /* in 10ms */ -+#define ISL38XX_MAX_WAIT_CYCLES 10 -+ -+/* PCI Memory Area */ -+#define ISL38XX_HARDWARE_REG 0x0000 -+#define ISL38XX_CARDBUS_CIS 0x0800 -+#define ISL38XX_DIRECT_MEM_WIN 0x1000 -+ -+/* Hardware registers */ -+#define ISL38XX_DEV_INT_REG 0x0000 -+#define ISL38XX_INT_IDENT_REG 0x0010 -+#define ISL38XX_INT_ACK_REG 0x0014 -+#define ISL38XX_INT_EN_REG 0x0018 -+#define ISL38XX_GEN_PURP_COM_REG_1 0x0020 -+#define ISL38XX_GEN_PURP_COM_REG_2 0x0024 -+#define ISL38XX_CTRL_BLK_BASE_REG ISL38XX_GEN_PURP_COM_REG_1 -+#define ISL38XX_DIR_MEM_BASE_REG 0x0030 -+#define ISL38XX_CTRL_STAT_REG 0x0078 -+ -+/* High end mobos queue up pci writes, the following -+ * is used to "read" from after a write to force flush */ -+#define ISL38XX_PCI_POSTING_FLUSH ISL38XX_INT_EN_REG -+ -+/** -+ * isl38xx_w32_flush - PCI iomem write helper -+ * @base: (host) memory base address of the device -+ * @val: 32bit value (host order) to write -+ * @offset: byte offset into @base to write value to -+ * -+ * This helper takes care of writing a 32bit datum to the -+ * specified offset into the device's pci memory space, and making sure -+ * the pci memory buffers get flushed by performing one harmless read -+ * from the %ISL38XX_PCI_POSTING_FLUSH offset. -+ */ -+static inline void -+isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset) -+{ -+ writel(val, base + offset); -+ (void) readl(base + ISL38XX_PCI_POSTING_FLUSH); -+} -+ -+/* Device Interrupt register bits */ -+#define ISL38XX_DEV_INT_RESET 0x0001 -+#define ISL38XX_DEV_INT_UPDATE 0x0002 -+#define ISL38XX_DEV_INT_WAKEUP 0x0008 -+#define ISL38XX_DEV_INT_SLEEP 0x0010 -+#define ISL38XX_DEV_INT_ABORT 0x0020 -+/* thos two only used in USB */ -+#define ISL38XX_DEV_INT_DATA 0x0040 -+#define ISL38XX_DEV_INT_MGMT 0x0080 -+ -+#define ISL38XX_DEV_INT_PCIUART_CTS 0x4000 -+#define ISL38XX_DEV_INT_PCIUART_DR 0x8000 -+ -+/* Interrupt Identification/Acknowledge/Enable register bits */ -+#define ISL38XX_INT_IDENT_UPDATE 0x0002 -+#define ISL38XX_INT_IDENT_INIT 0x0004 -+#define ISL38XX_INT_IDENT_WAKEUP 0x0008 -+#define ISL38XX_INT_IDENT_SLEEP 0x0010 -+#define ISL38XX_INT_IDENT_PCIUART_CTS 0x4000 -+#define ISL38XX_INT_IDENT_PCIUART_DR 0x8000 -+ -+#define ISL38XX_INT_SOURCES (ISL38XX_INT_IDENT_UPDATE | \ -+ ISL38XX_INT_IDENT_INIT | \ -+ ISL38XX_INT_IDENT_WAKEUP | \ -+ ISL38XX_INT_IDENT_SLEEP | \ -+ ISL38XX_INT_IDENT_PCIUART_CTS | \ -+ ISL38XX_INT_IDENT_PCIUART_DR) -+ -+/* Control/Status register bits */ -+/* Looks like there are other meaningful bits -+ 0x20004400 seen in normal operation, -+ 0x200044db at 'timeout waiting for mgmt response' -+*/ -+#define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200 -+#define ISL38XX_CTRL_STAT_CLKRUN 0x00800000 -+#define ISL38XX_CTRL_STAT_RESET 0x10000000 -+#define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000 -+#define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000 -+#define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000 -+ -+/* Some flags for the isl hardware registers controlling DMA inside the -+ * chip */ -+#define ISL38XX_DMA_STATUS_DONE 0x00000001 -+#define ISL38XX_DMA_STATUS_READY 0x00000002 -+#define NET2280_EPA_FIFO_PCI_ADDR 0x20000000 -+#define ISL38XX_DMA_MASTER_CONTROL_TRIGGER 0x00000004 -+ -+#endif /* _LINUX_ISL_38XX_H */ -Index: linux-2.6.24.7/include/linux/pm.h -=================================================================== ---- linux-2.6.24.7.orig/include/linux/pm.h -+++ linux-2.6.24.7/include/linux/pm.h -@@ -178,6 +178,9 @@ struct dev_pm_info { - unsigned can_wakeup:1; - #ifdef CONFIG_PM_SLEEP - unsigned should_wakeup:1; -+ pm_message_t prev_state; -+ void * saved_state; -+ struct device * pm_parent; - struct list_head entry; - #endif - }; -Index: linux-2.6.24.7/include/linux/power_supply.h -=================================================================== ---- linux-2.6.24.7.orig/include/linux/power_supply.h -+++ linux-2.6.24.7/include/linux/power_supply.h -@@ -98,9 +98,11 @@ enum power_supply_property { - POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG, - POWER_SUPPLY_PROP_TIME_TO_FULL_NOW, - POWER_SUPPLY_PROP_TIME_TO_FULL_AVG, -+ POWER_SUPPLY_PROP_ACCUM_CURRENT, - /* Properties of type `const char *' */ - POWER_SUPPLY_PROP_MODEL_NAME, - POWER_SUPPLY_PROP_MANUFACTURER, -+ POWER_SUPPLY_PROP_SERIAL_NUMBER, - }; - - enum power_supply_type { -@@ -169,9 +171,10 @@ struct power_supply_info { - - extern void power_supply_changed(struct power_supply *psy); - extern int power_supply_am_i_supplied(struct power_supply *psy); -+extern void power_supply_status_changed(struct power_supply *psy); - - extern int power_supply_register(struct device *parent, -- struct power_supply *psy); -+ struct power_supply *psy); - extern void power_supply_unregister(struct power_supply *psy); - - /* For APM emulation, think legacy userspace. */ -Index: linux-2.6.24.7/include/linux/vt_kern.h -=================================================================== ---- linux-2.6.24.7.orig/include/linux/vt_kern.h -+++ linux-2.6.24.7/include/linux/vt_kern.h -@@ -96,4 +96,23 @@ struct vt_spawn_console { - }; - extern struct vt_spawn_console vt_spawn_con; - -+/* A notifier list for console events */ -+extern struct raw_notifier_head console_notifier_list; -+ -+/* Called when the FG console switches to KD_TEXT mode */ -+#define CONSOLE_EVENT_SWITCH_TEXT 0x01 -+ -+/* Called when the FG console switches to KD_GRAPHICS mode */ -+#define CONSOLE_EVENT_SWITCH_GRAPHICS 0x02 -+ -+static inline int console_event_register(struct notifier_block *n) -+{ -+ return raw_notifier_chain_register(&console_notifier_list, n); -+} -+ -+static inline int console_event_unregister(struct notifier_block *n) -+{ -+ return raw_notifier_chain_unregister(&console_notifier_list, n); -+} -+ - #endif /* _VT_KERN_H */ -Index: linux-2.6.24.7/include/sound/ac97_codec.h -=================================================================== ---- linux-2.6.24.7.orig/include/sound/ac97_codec.h -+++ linux-2.6.24.7/include/sound/ac97_codec.h -@@ -281,10 +281,12 @@ - /* specific - Analog Devices */ - #define AC97_AD_TEST 0x5a /* test register */ - #define AC97_AD_TEST2 0x5c /* undocumented test register 2 */ -+#define AC97_AD_HPFD_SHIFT 12 /* High Pass Filter Disable */ - #define AC97_AD_CODEC_CFG 0x70 /* codec configuration */ - #define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */ - #define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */ - #define AC97_AD_MISC 0x76 /* Misc Control Bits */ -+#define AC97_AD_VREFD_SHIFT 2 /* V_REFOUT Disable (AD1888) */ - - /* specific - Cirrus Logic */ - #define AC97_CSR_ACMODE 0x5e /* AC Mode Register */ -Index: linux-2.6.24.7/kernel/power/console.c -=================================================================== ---- linux-2.6.24.7.orig/kernel/power/console.c -+++ linux-2.6.24.7/kernel/power/console.c -@@ -9,7 +9,7 @@ - #include - #include "power.h" - --#if defined(CONFIG_VT) && defined(CONFIG_VT_CONSOLE) -+#if defined(CONFIG_VT) && defined(CONFIG_VT_CONSOLE) && !defined(CONFIG_DISABLE_SUSPEND_VT_SWITCH) - #define SUSPEND_CONSOLE (MAX_NR_CONSOLES-1) - - static int orig_fgconsole, orig_kmsg; -Index: linux-2.6.24.7/kernel/power/Kconfig -=================================================================== ---- linux-2.6.24.7.orig/kernel/power/Kconfig -+++ linux-2.6.24.7/kernel/power/Kconfig -@@ -37,9 +37,22 @@ config PM_DEBUG - code. This is helpful when debugging and reporting PM bugs, like - suspend support. - -+config DISABLE_SUSPEND_VT_SWITCH -+ bool "Disable the console switch prior to suspend (DANGEROUS)" -+ depends on PM_DEBUG -+ default n -+ ---help--- -+ This option disables the automatic switch to VT console that happens -+ prior to Linux going into a suspend/sleep. Your video card/framebuffer -+ must be able to properly restore the display (even if X is doing -+ something crazy!) in this scenario. This is useful for saving -+ precious milliseconds during suspend and resume. -+ -+ If unsure, say N. -+ - config PM_VERBOSE - bool "Verbose Power Management debugging" -- depends on PM_DEBUG -+ depends on VT_CONSOLE && PM && EXPERIMENTAL - default n - ---help--- - This option enables verbose messages from the Power Management code. -Index: linux-2.6.24.7/kernel/power/main.c -=================================================================== ---- linux-2.6.24.7.orig/kernel/power/main.c -+++ linux-2.6.24.7/kernel/power/main.c -@@ -76,11 +76,13 @@ static int suspend_prepare(void) - if (!suspend_ops || !suspend_ops->enter) - return -EPERM; - -+#ifndef CONFIG_OLPC_PM - error = pm_notifier_call_chain(PM_SUSPEND_PREPARE); - if (error) - goto Finish; - - pm_prepare_console(); -+#endif - - if (freeze_processes()) { - error = -EAGAIN; -Index: linux-2.6.24.7/scripts/kconfig/conf.c -=================================================================== ---- linux-2.6.24.7.orig/scripts/kconfig/conf.c -+++ linux-2.6.24.7/scripts/kconfig/conf.c -@@ -22,6 +22,7 @@ enum { - ask_new, - ask_silent, - set_default, -+ set_silentdefault, - set_yes, - set_mod, - set_no, -@@ -64,10 +65,11 @@ static void strip(char *str) - - static void check_stdin(void) - { -- if (!valid_stdin && input_mode == ask_silent) { -+ if (!valid_stdin && (input_mode == ask_silent || -+ input_mode == set_silentdefault)) { - printf(_("aborted!\n\n")); - printf(_("Console input/output is redirected. ")); -- printf(_("Run 'make oldconfig' to update configuration.\n\n")); -+ printf(_("Configuration file needs to be updated.\n\n")); - exit(1); - } - } -@@ -102,6 +104,7 @@ static int conf_askvalue(struct symbol * - break; - case ask_new: - case ask_silent: -+ case set_silentdefault: - if (sym_has_value(sym)) { - printf("%s\n", def); - return 0; -@@ -352,6 +355,7 @@ static int conf_choice(struct menu *menu - switch (input_mode) { - case ask_new: - case ask_silent: -+ case set_silentdefault: - if (!is_new) { - cnt = def; - printf("%d\n", cnt); -@@ -424,7 +428,9 @@ static void conf(struct menu *menu) - - switch (prop->type) { - case P_MENU: -- if (input_mode == ask_silent && rootEntry != menu) { -+ if ((input_mode == ask_silent || -+ input_mode == set_silentdefault) && -+ rootEntry != menu) { - check_conf(menu); - return; - } -@@ -508,6 +514,16 @@ int main(int ac, char **av) - input_mode = ask_silent; - valid_stdin = isatty(0) && isatty(1) && isatty(2); - break; -+ case 'S': -+ input_mode = set_silentdefault; -+ valid_stdin = isatty(0) && isatty(1) && isatty(2); -+ defconfig_file = av[i++]; -+ if (!defconfig_file) { -+ printf("%s: No default config file specified\n", -+ av[0]); -+ exit(1); -+ } -+ break; - case 'd': - input_mode = set_default; - break; -@@ -557,6 +573,14 @@ int main(int ac, char **av) - exit(1); - } - break; -+ case set_silentdefault: -+ if (conf_read(defconfig_file)) { -+ printf("***\n" -+ "*** Can't find default configuration \"%s\"!\n" -+ "***\n", defconfig_file); -+ exit(1); -+ } -+ break; - case ask_silent: - if (stat(".config", &tmpstat)) { - printf(_("***\n" -@@ -597,7 +621,7 @@ int main(int ac, char **av) - break; - } - -- if (input_mode != ask_silent) { -+ if (input_mode != ask_silent && input_mode != set_silentdefault) { - rootEntry = &rootmenu; - conf(&rootmenu); - if (input_mode == ask_all) { -@@ -610,19 +634,21 @@ int main(int ac, char **av) - fprintf(stderr, _("\n*** Kernel configuration requires explicit update.\n\n")); - return 1; - } -- } else -+ } else if (input_mode != set_silentdefault) - goto skip_check; - - do { - conf_cnt = 0; - check_conf(&rootmenu); - } while (conf_cnt); -- if (conf_write(NULL)) { -+ if (conf_write(NULL, input_mode == ask_silent || -+ input_mode == set_silentdefault)) { - fprintf(stderr, _("\n*** Error during writing of the kernel configuration.\n\n")); - return 1; - } - skip_check: -- if (input_mode == ask_silent && conf_write_autoconf()) { -+ if ((input_mode == ask_silent || input_mode == set_silentdefault) && -+ conf_write_autoconf()) { - fprintf(stderr, _("\n*** Error during writing of the kernel configuration.\n\n")); - return 1; - } -Index: linux-2.6.24.7/scripts/kconfig/confdata.c -=================================================================== ---- linux-2.6.24.7.orig/scripts/kconfig/confdata.c -+++ linux-2.6.24.7/scripts/kconfig/confdata.c -@@ -393,7 +393,7 @@ int conf_read(const char *name) - return 0; - } - --int conf_write(const char *name) -+int conf_write(const char *name, int quiet) - { - FILE *out; - struct symbol *sym; -@@ -548,9 +548,10 @@ int conf_write(const char *name) - return 1; - } - -- printf(_("#\n" -- "# configuration written to %s\n" -- "#\n"), newname); -+ if (!quiet) -+ printf("#\n" -+ "# configuration written to %s\n" -+ "#\n", newname); - - sym_set_change_count(0); - -Index: linux-2.6.24.7/scripts/kconfig/gconf.c -=================================================================== ---- linux-2.6.24.7.orig/scripts/kconfig/gconf.c -+++ linux-2.6.24.7/scripts/kconfig/gconf.c -@@ -621,7 +621,7 @@ void on_load1_activate(GtkMenuItem * men - - void on_save_activate(GtkMenuItem * menuitem, gpointer user_data) - { -- if (conf_write(NULL)) -+ if (conf_write(NULL, 0)) - text_insert_msg(_("Error"), _("Unable to save configuration !")); - } - -@@ -634,7 +634,7 @@ store_filename(GtkFileSelection * file_s - fn = gtk_file_selection_get_filename(GTK_FILE_SELECTION - (user_data)); - -- if (conf_write(fn)) -+ if (conf_write(fn, 0)) - text_insert_msg(_("Error"), _("Unable to save configuration !")); - - gtk_widget_destroy(GTK_WIDGET(user_data)); -Index: linux-2.6.24.7/scripts/kconfig/lkc_proto.h -=================================================================== ---- linux-2.6.24.7.orig/scripts/kconfig/lkc_proto.h -+++ linux-2.6.24.7/scripts/kconfig/lkc_proto.h -@@ -3,7 +3,7 @@ - P(conf_parse,void,(const char *name)); - P(conf_read,int,(const char *name)); - P(conf_read_simple,int,(const char *name, int)); --P(conf_write,int,(const char *name)); -+P(conf_write,int,(const char *name, int)); - P(conf_write_autoconf,int,(void)); - P(conf_get_changed,bool,(void)); - P(conf_set_changed_callback, void,(void (*fn)(void))); -Index: linux-2.6.24.7/scripts/kconfig/Makefile -=================================================================== ---- linux-2.6.24.7.orig/scripts/kconfig/Makefile -+++ linux-2.6.24.7/scripts/kconfig/Makefile -@@ -69,6 +69,9 @@ endif - %_defconfig: $(obj)/conf - $(Q)$< -D arch/$(SRCARCH)/configs/$@ $(Kconfig) - -+%_silentdefconfig: $(obj)/conf -+ $(Q)$< -S arch/$(ARCH)/configs/$(subst _silentdefconfig,_defconfig,$@) arch/$(ARCH)/Kconfig -+ - # Help text used by make help - help: - @echo ' config - Update current config utilising a line-oriented program' -Index: linux-2.6.24.7/scripts/kconfig/mconf.c -=================================================================== ---- linux-2.6.24.7.orig/scripts/kconfig/mconf.c -+++ linux-2.6.24.7/scripts/kconfig/mconf.c -@@ -885,7 +885,7 @@ static void conf_save(void) - case 0: - if (!dialog_input_result[0]) - return; -- if (!conf_write(dialog_input_result)) { -+ if (!conf_write(dialog_input_result, 0)) { - set_config_filename(dialog_input_result); - return; - } -@@ -945,7 +945,7 @@ int main(int ac, char **av) - - switch (res) { - case 0: -- if (conf_write(filename)) { -+ if (conf_write(filename, 0)) { - fprintf(stderr, _("\n\n" - "Error during writing of the kernel configuration.\n" - "Your kernel configuration changes were NOT saved." -Index: linux-2.6.24.7/scripts/kconfig/qconf.cc -=================================================================== ---- linux-2.6.24.7.orig/scripts/kconfig/qconf.cc -+++ linux-2.6.24.7/scripts/kconfig/qconf.cc -@@ -1458,7 +1458,7 @@ void ConfigMainWindow::loadConfig(void) - - void ConfigMainWindow::saveConfig(void) - { -- if (conf_write(NULL)) -+ if (conf_write(NULL, 0)) - QMessageBox::information(this, "qconf", "Unable to save configuration!"); - } - -@@ -1467,7 +1467,7 @@ void ConfigMainWindow::saveConfigAs(void - QString s = QFileDialog::getSaveFileName(".config", NULL, this); - if (s.isNull()) - return; -- if (conf_write(QFile::encodeName(s))) -+ if (conf_write(QFile::encodeName(s), 0)) - QMessageBox::information(this, "qconf", "Unable to save configuration!"); - } - -@@ -1619,7 +1619,7 @@ void ConfigMainWindow::closeEvent(QClose - mb.setButtonText(QMessageBox::Cancel, "Cancel Exit"); - switch (mb.exec()) { - case QMessageBox::Yes: -- conf_write(NULL); -+ conf_write(NULL, 0); - case QMessageBox::No: - e->accept(); - break; -Index: linux-2.6.24.7/sound/pci/ac97/ac97_patch.c -=================================================================== ---- linux-2.6.24.7.orig/sound/pci/ac97/ac97_patch.c -+++ linux-2.6.24.7/sound/pci/ac97/ac97_patch.c -@@ -2029,8 +2029,9 @@ static const struct snd_kcontrol_new snd - .get = snd_ac97_ad1888_lohpsel_get, - .put = snd_ac97_ad1888_lohpsel_put - }, -- AC97_SINGLE("V_REFOUT Enable", AC97_AD_MISC, 2, 1, 1), -- AC97_SINGLE("High Pass Filter Enable", AC97_AD_TEST2, 12, 1, 1), -+ AC97_SINGLE("V_REFOUT Enable", AC97_AD_MISC, AC97_AD_VREFD_SHIFT, 1, 1), -+ AC97_SINGLE("High Pass Filter Enable", AC97_AD_TEST2, -+ AC97_AD_HPFD_SHIFT, 1, 1), - AC97_SINGLE("Spread Front to Surround and Center/LFE", AC97_AD_MISC, 7, 1, 0), - { - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, -Index: linux-2.6.24.7/sound/pci/cs5535audio/cs5535audio.c -=================================================================== ---- linux-2.6.24.7.orig/sound/pci/cs5535audio/cs5535audio.c -+++ linux-2.6.24.7/sound/pci/cs5535audio/cs5535audio.c -@@ -145,7 +145,7 @@ static unsigned short snd_cs5535audio_ac - return snd_cs5535audio_codec_read(cs5535au, reg); - } - --static int snd_cs5535audio_mixer(struct cs5535audio *cs5535au) -+static int __devinit snd_cs5535audio_mixer(struct cs5535audio *cs5535au) - { - struct snd_card *card = cs5535au->card; - struct snd_ac97_bus *pbus; -@@ -160,10 +160,14 @@ static int snd_cs5535audio_mixer(struct - return err; - - memset(&ac97, 0, sizeof(ac97)); -- ac97.scaps = AC97_SCAP_AUDIO|AC97_SCAP_SKIP_MODEM; -+ ac97.scaps = AC97_SCAP_AUDIO | AC97_SCAP_SKIP_MODEM -+ | AC97_SCAP_POWER_SAVE; - ac97.private_data = cs5535au; - ac97.pci = cs5535au->pci; - -+ /* olpc_prequirks is dummied out if not olpc */ -+ olpc_prequirks(card, &ac97); -+ - if ((err = snd_ac97_mixer(pbus, &ac97, &cs5535au->ac97)) < 0) { - snd_printk(KERN_ERR "mixer failed\n"); - return err; -@@ -171,6 +175,12 @@ static int snd_cs5535audio_mixer(struct - - snd_ac97_tune_hardware(cs5535au->ac97, ac97_quirks, ac97_quirk); - -+ /* olpc_quirks is dummied out if not olpc */ -+ if (( err = olpc_quirks(card, cs5535au->ac97)) < 0) { -+ snd_printk(KERN_ERR "olpc quirks failed\n"); -+ return err; -+ } -+ - return 0; - } - -Index: linux-2.6.24.7/sound/pci/cs5535audio/cs5535audio.h -=================================================================== ---- linux-2.6.24.7.orig/sound/pci/cs5535audio/cs5535audio.h -+++ linux-2.6.24.7/sound/pci/cs5535audio/cs5535audio.h -@@ -78,6 +78,7 @@ struct cs5535audio_dma { - unsigned int buf_addr, buf_bytes; - unsigned int period_bytes, periods; - u32 saved_prd; -+ int pcm_open_flag; - }; - - struct cs5535audio { -@@ -93,8 +94,21 @@ struct cs5535audio { - struct cs5535audio_dma dmas[NUM_CS5535AUDIO_DMAS]; - }; - -+#ifdef CONFIG_PM - int snd_cs5535audio_suspend(struct pci_dev *pci, pm_message_t state); - int snd_cs5535audio_resume(struct pci_dev *pci); -+#endif -+ -+#ifdef CONFIG_OLPC -+void olpc_prequirks(struct snd_card *card, struct snd_ac97_template *ac97) __devinit; -+int olpc_quirks(struct snd_card *card, struct snd_ac97 *ac97) __devinit; -+int olpc_ai_enable(struct snd_ac97 *ac97, u8 val); -+#else -+#define olpc_prequirks(arg,arg2) do {} while (0) -+#define olpc_quirks(arg,arg2) (0) -+#define olpc_ai_enable(a, v) (0) -+#endif -+ - int __devinit snd_cs5535audio_pcm(struct cs5535audio *cs5535audio); - - #endif /* __SOUND_CS5535AUDIO_H */ -Index: linux-2.6.24.7/sound/pci/cs5535audio/cs5535audio_olpc.c -=================================================================== ---- /dev/null -+++ linux-2.6.24.7/sound/pci/cs5535audio/cs5535audio_olpc.c -@@ -0,0 +1,110 @@ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "cs5535audio.h" -+ -+/* -+ * OLPC has an additional feature on top of the regular AD1888 codec features. -+ * It has an Analog Input mode that is switched into (after disabling the -+ * High Pass Filter) via GPIO. It is only supported on B2 and later models. -+ */ -+ -+int olpc_ai_enable(struct snd_ac97 *ac97, u8 val) -+{ -+ int err; -+ -+ /* -+ * update the High Pass Filter (via AC97_AD_TEST2), and then set -+ * Analog Input mode through a GPIO. -+ */ -+ -+ if (val) { -+ err = snd_ac97_update_bits(ac97, AC97_AD_TEST2, -+ 1<type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; -+ uinfo->count = 1; -+ uinfo->value.integer.min = 0; -+ uinfo->value.integer.max = 1; -+ return 0; -+} -+ -+static int snd_cs5535audio_ai_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ ucontrol->value.integer.value[0] = geode_gpio_isset(OLPC_GPIO_MIC_AC, -+ GPIO_OUTPUT_VAL); -+ return 0; -+} -+ -+static int snd_cs5535audio_ai_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct cs5535audio *cs5535au = snd_kcontrol_chip(kcontrol); -+ struct snd_ac97 *ac97 = cs5535au->ac97; -+ -+ olpc_ai_enable(ac97, ucontrol->value.integer.value[0]); -+ -+ return 1; -+} -+ -+static struct snd_kcontrol_new snd_cs5535audio_controls __devinitdata = -+{ -+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, -+ .name = "DC Mode Enable", -+ .info = snd_cs5535audio_ai_info, -+ .get = snd_cs5535audio_ai_get, -+ .put = snd_cs5535audio_ai_put, -+ .private_value = 0 -+}; -+ -+void __devinit olpc_prequirks(struct snd_card *card, -+ struct snd_ac97_template *ac97) -+{ -+ /* Bail if this isn't an OLPC platform */ -+ if (!machine_is_olpc()) -+ return; -+ -+ /* If on an OLPC B3 or higher, invert EAPD. */ -+ if (olpc_board_at_least(olpc_board_pre(0xb3))) -+ ac97->scaps |= AC97_SCAP_INV_EAPD; -+} -+ -+int __devinit olpc_quirks(struct snd_card *card, struct snd_ac97 *ac97) -+{ -+ struct snd_ctl_elem_id elem; -+ -+ /* Bail if this isn't an OLPC platform */ -+ if (!machine_is_olpc()) -+ return 0; -+ -+ /* drop the original ad1888 HPF control */ -+ memset(&elem, 0, sizeof(elem)); -+ elem.iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ strcpy(elem.name, "High Pass Filter Enable"); -+ snd_ctl_remove_id(card, &elem); -+ -+ /* add the override for OLPC's HPF */ -+ return snd_ctl_add(card, snd_ctl_new1(&snd_cs5535audio_controls, -+ ac97->private_data)); -+} -Index: linux-2.6.24.7/sound/pci/cs5535audio/cs5535audio_pcm.c -=================================================================== ---- linux-2.6.24.7.orig/sound/pci/cs5535audio/cs5535audio_pcm.c -+++ linux-2.6.24.7/sound/pci/cs5535audio/cs5535audio_pcm.c -@@ -259,6 +259,9 @@ static int snd_cs5535audio_hw_params(str - err = cs5535audio_build_dma_packets(cs5535au, dma, substream, - params_periods(hw_params), - params_period_bytes(hw_params)); -+ if (!err) -+ dma->pcm_open_flag = 1; -+ - return err; - } - -@@ -267,6 +270,15 @@ static int snd_cs5535audio_hw_free(struc - struct cs5535audio *cs5535au = snd_pcm_substream_chip(substream); - struct cs5535audio_dma *dma = substream->runtime->private_data; - -+ if (dma->pcm_open_flag) { -+ if (substream == cs5535au->playback_substream) -+ snd_ac97_update_power(cs5535au->ac97, -+ AC97_PCM_FRONT_DAC_RATE, 0); -+ else -+ snd_ac97_update_power(cs5535au->ac97, -+ AC97_PCM_LR_ADC_RATE, 0); -+ dma->pcm_open_flag = 0; -+ } - cs5535audio_clear_dma_packets(cs5535au, dma, substream); - return snd_pcm_lib_free_pages(substream); - } -@@ -341,6 +353,7 @@ static int snd_cs5535audio_capture_open( - int err; - struct cs5535audio *cs5535au = snd_pcm_substream_chip(substream); - struct snd_pcm_runtime *runtime = substream->runtime; -+ struct snd_ac97 *ac97 = cs5535au->ac97; - - runtime->hw = snd_cs5535audio_capture; - cs5535au->capture_substream = substream; -@@ -348,11 +361,29 @@ static int snd_cs5535audio_capture_open( - if ((err = snd_pcm_hw_constraint_integer(runtime, - SNDRV_PCM_HW_PARAM_PERIODS)) < 0) - return err; -- return 0; -+ -+#ifdef CONFIG_OLPC -+ /* Disable Analog Input */ -+ olpc_ai_enable(ac97, 0); -+ /* Enable V_ref bias while recording. */ -+ snd_ac97_update_bits(ac97, AC97_AD_MISC, 1<ac97; -+ -+ /* Disable Analog Input */ -+ olpc_ai_enable(ac97, 0); -+ /* Disable V_ref bias. */ -+ snd_ac97_update_bits(ac97, AC97_AD_MISC, 1< - #include - #include -+#include -+#include - - #define VERSION "$Revision: 1.30 $" - -@@ -27,6 +29,12 @@ - #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args) - #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args) - -+struct retry { -+ struct list_head list; -+ const char *val; -+}; -+ -+static LIST_HEAD(retry_list); - - /* Info for the block device */ - struct block2mtd_dev { -@@ -38,10 +46,34 @@ - char devname[0]; - }; - -+static int block2mtd_setup2(const char *val); - - /* Static info about the MTD, used in cleanup_module */ - static LIST_HEAD(blkmtd_device_list); - -+static int add_retry(const char *val) { -+ struct retry *r = kmalloc(sizeof(struct retry), GFP_KERNEL); -+ -+ INIT_LIST_HEAD(&r->list); -+ r->val = val; -+ list_add(&r->list, &retry_list); -+ -+ return 0; -+} -+ -+static int __init process_retries(void) { -+ struct list_head *p, *tmp; -+ -+ list_for_each_safe(p, tmp, &retry_list) { -+ struct retry *r = list_entry(p, struct retry, list); -+ block2mtd_setup2(r->val); -+ msleep(100); -+ list_del(p); -+ kfree(r); -+ } -+ return 0; -+} -+rootfs_initcall(process_retries); - - static struct page *page_read(struct address_space *mapping, int index) - { -@@ -517,7 +549,9 @@ - if (token[2] && (strlen(token[2]) + 1 > 80)) - parse_err("mtd device name too long"); - -- add_device(name, erase_size, token[2]); -+ if (add_device(name, erase_size, token[2]) == NULL) { -+ add_retry(val); -+ } - - return 0; - } -diff -urN linux-2.6.26.orig/include/asm-generic/vmlinux.lds.h linux-2.6.26/include/asm-generic/vmlinux.lds.h ---- linux-2.6.26.orig/include/asm-generic/vmlinux.lds.h 2008-08-13 03:51:08.000000000 +0200 -+++ linux-2.6.26/include/asm-generic/vmlinux.lds.h 2008-08-13 04:09:04.000000000 +0200 -@@ -338,12 +338,14 @@ - *(.initcall4s.init) \ - *(.initcall5.init) \ - *(.initcall5s.init) \ -- *(.initcallrootfs.init) \ - *(.initcall6.init) \ - *(.initcall6s.init) \ - *(.initcall7.init) \ - *(.initcall7s.init) - -+#define INITCALLS_ROOT \ -+ *(.initcallrootfs.init) -+ - #define PERCPU(align) \ - . = ALIGN(align); \ - __per_cpu_start = .; \ -diff -urN linux-2.6.26.orig/init/do_mounts.c linux-2.6.26/init/do_mounts.c ---- linux-2.6.26.orig/init/do_mounts.c 2008-08-13 03:51:11.000000000 +0200 -+++ linux-2.6.26/init/do_mounts.c 2008-08-13 04:00:22.000000000 +0200 -@@ -173,16 +173,8 @@ - return 1; - } - --static unsigned int __initdata root_delay; --static int __init root_delay_setup(char *str) --{ -- root_delay = simple_strtoul(str, NULL, 0); -- return 1; --} -- - __setup("rootflags=", root_data_setup); - __setup("rootfstype=", fs_names_setup); --__setup("rootdelay=", root_delay_setup); - - static void __init get_fs_names(char *page) - { -@@ -358,18 +350,6 @@ - { - int is_floppy; - -- if (root_delay) { -- printk(KERN_INFO "Waiting %dsec before mounting root device...\n", -- root_delay); -- ssleep(root_delay); -- } -- -- /* wait for the known devices to complete their probing */ -- while (driver_probe_done() != 0) -- msleep(100); -- -- md_run_setup(); -- - if (saved_root_name[0]) { - root_device_name = saved_root_name; - if (!strncmp(root_device_name, "mtd", 3)) { -diff -urN linux-2.6.26.orig/init/main.c linux-2.6.26/init/main.c ---- linux-2.6.26.orig/init/main.c 2008-08-13 03:51:11.000000000 +0200 -+++ linux-2.6.26/init/main.c 2008-08-13 04:06:01.000000000 +0200 -@@ -70,6 +70,7 @@ - #ifdef CONFIG_X86_LOCAL_APIC - #include - #endif -+#include "do_mounts.h" - - /* - * This is one of the first .c files built. Error out early if we have compiler -@@ -737,12 +738,13 @@ - - - extern initcall_t __initcall_start[], __initcall_end[]; -+extern initcall_t __root_initcall_start[], __root_initcall_end[]; - --static void __init do_initcalls(void) -+static void __init do_initcalls(initcall_t *start, initcall_t *end) - { - initcall_t *call; - -- for (call = __initcall_start; call < __initcall_end; call++) -+ for (call = start; call < end; call++) - do_one_initcall(*call); - - /* Make sure there is no pending stuff from the initcall sequence */ -@@ -763,7 +765,7 @@ - usermodehelper_init(); - driver_init(); - init_irq_proc(); -- do_initcalls(); -+ do_initcalls(__initcall_start, __initcall_end); - } - - static int __initdata nosoftlockup; -@@ -835,6 +837,13 @@ - panic("No init found. Try passing init= option to kernel."); - } - -+static unsigned int __initdata root_delay; -+static int __init root_delay_setup(char *str) -+{ -+ root_delay = simple_strtoul(str, NULL, 0); -+ return 1; -+} -+__setup("rootdelay=", root_delay_setup); - static int __init kernel_init(void * unused) - { - lock_kernel(); -@@ -875,7 +884,16 @@ - - if (sys_access((const char __user *) ramdisk_execute_command, 0) != 0) { - ramdisk_execute_command = NULL; -- prepare_namespace(); -+ if (root_delay) { -+ printk(KERN_INFO "Waiting %desc before mounting root device...\n", -+ root_delay); -+ ssleep(root_delay); -+ } -+ while (driver_probe_done() != 0) -+ msleep(100); -+ md_run_setup(); -+ do_initcalls(__root_initcall_start, __root_initcall_end); -+ prepare_namespace(); - } - - /* diff --git a/target/linux/orion/Makefile b/target/linux/orion/Makefile deleted file mode 100644 index 0f7064ae14..0000000000 --- a/target/linux/orion/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=orion -BOARDNAME:=Marvell Orion -FEATURES:=squashfs - -LINUX_VERSION:=2.6.26.5 - -include $(INCLUDE_DIR)/target.mk - -KERNELNAME:="uImage" - -DEFAULT_PACKAGES += kmod-madwifi - -define Kernel/Configure - $(call Kernel/Configure/Default) - $(SED) 's,.*CONFIG_AEABI.*,$(if $(CONFIG_EABI_SUPPORT),CONFIG_AEABI=y,# CONFIG_AEABI is not set),' $(LINUX_DIR)/.config - $(if $(CONFIG_EABI_SUPPORT),echo '# CONFIG_OABI_COMPAT is not set' >> $(LINUX_DIR)/.config) -endef - -$(eval $(call BuildTarget)) diff --git a/target/linux/orion/config-default b/target/linux/orion/config-default deleted file mode 100644 index 58729debd2..0000000000 --- a/target/linux/orion/config-default +++ /dev/null @@ -1,382 +0,0 @@ -# CONFIG_8139TOO is not set -# CONFIG_AEABI is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MSM7X00A is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_OMAP is not set -CONFIG_ARCH_ORION5X=y -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_SHARK is not set -CONFIG_ARCH_SUPPORTS_AOUT=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ARCH_VERSATILE is not set -CONFIG_ARM=y -# CONFIG_ARM_THUMB is not set -# CONFIG_ARPD is not set -# CONFIG_ARTHUR is not set -CONFIG_ATA=m -# CONFIG_ATA_NONSTANDARD is not set -# CONFIG_ATA_PIIX is not set -CONFIG_ATA_SFF=y -# CONFIG_ATM is not set -# CONFIG_ATMEL is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BINFMT_AOUT is not set -CONFIG_BITREVERSE=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BONDING is not set -CONFIG_BOUNCE=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_BT is not set -# CONFIG_CIFS_STATS is not set -CONFIG_CLASSIC_RCU=y -CONFIG_CMDLINE="root=/dev/mtdblock1 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200 init=/etc/preinit" -# CONFIG_CONFIGFS_FS is not set -CONFIG_CPU_32=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_FEROCEON=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_DISABLE is not set -CONFIG_CPU_FEROCEON=y -CONFIG_CPU_FEROCEON_OLD_ID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_NOIFAR=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CRC16=y -# CONFIG_CRC_CCITT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_USER is not set -CONFIG_DEFAULT_TCP_CONG="westwood" -# CONFIG_DEFAULT_VEGAS is not set -CONFIG_DEFAULT_WESTWOOD=y -CONFIG_DEVPORT=y -CONFIG_DLCI=m -CONFIG_DLCI_MAX=8 -# CONFIG_DM9000 is not set -CONFIG_DNOTIFY=y -# CONFIG_DSCC4 is not set -# CONFIG_E100 is not set -# CONFIG_E1000E_ENABLED is not set -# CONFIG_FARSYNC is not set -# CONFIG_FPE_FASTFPE is not set -# CONFIG_FPE_NWFPE is not set -CONFIG_FRAME_POINTER=y -CONFIG_FS_POSIX_ACL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set -CONFIG_GENERIC_GPIO=y -# CONFIG_HAMRADIO is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_HAVE_IDE=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HDLC=m -CONFIG_HDLC_CISCO=m -CONFIG_HDLC_FR=m -CONFIG_HDLC_PPP=m -CONFIG_HDLC_RAW=m -# CONFIG_HDLC_RAW_ETH is not set -# CONFIG_HERMES is not set -CONFIG_HWMON=y -# CONFIG_HWMON_DEBUG_CHIP is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MV64XXX=y -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IDE is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IP6_NF_MANGLE is not set -# CONFIG_IP6_NF_MATCH_EUI64 is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_TARGET_LOG is not set -# CONFIG_IPV6_MROUTE is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_MROUTE=y -# CONFIG_IP_NF_ARPTABLES is not set -# CONFIG_IP_NF_MATCH_ADDRTYPE is not set -# CONFIG_IP_NF_MATCH_ECN is not set -# CONFIG_IP_NF_MATCH_RECENT is not set -# CONFIG_IP_NF_MATCH_TIME is not set -# CONFIG_IP_NF_SET is not set -# CONFIG_IP_NF_TARGET_ECN is not set -# CONFIG_IP_NF_TARGET_LOG is not set -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_NF_TARGET_TTL is not set -# CONFIG_IP_NF_TARGET_ULOG is not set -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -# CONFIG_IWLWIFI_LEDS is not set -# CONFIG_LANMEDIA is not set -# CONFIG_LATENCYTOP is not set -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_LLC2 is not set -CONFIG_LZO_COMPRESS=m -CONFIG_LZO_DECOMPRESS=m -# CONFIG_MACH_DB88F5281 is not set -# CONFIG_MACH_DNS323 is not set -# CONFIG_MACH_KUROBOX_PRO is not set -# CONFIG_MACH_LINKSTATION_PRO is not set -# CONFIG_MACH_MV2120 is not set -# CONFIG_MACH_MSS2 is not set -# CONFIG_MACH_RD88F5182 is not set -# CONFIG_MACH_TS209 is not set -# CONFIG_MACH_TS409 is not set -# CONFIG_MACH_TS78XX is not set -CONFIG_MACH_WNR854T=y -CONFIG_MACH_WRT350N_V2=y -# CONFIG_MAC_PARTITION is not set -CONFIG_MEDIA_TUNER=m -# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -# CONFIG_MINIX_FS is not set -# CONFIG_MMC_TEST is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_ONENAND is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PCI is not set -# CONFIG_MTD_PHRAM is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_BANKWIDTH=1 -CONFIG_MTD_PHYSMAP_LEN=0 -CONFIG_MTD_PHYSMAP_START=0xf0000000 -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SLRAM is not set -CONFIG_MV643XX_ETH=y -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NET_CLS_ACT is not set -# CONFIG_NET_CLS_IND is not set -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_NVRAM is not set -# CONFIG_OABI_COMPAT is not set -# CONFIG_OUTER_CACHE is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PATA_ARTOP=m -# CONFIG_PATA_SCH is not set -# CONFIG_PC300 is not set -CONFIG_PCI=y -# CONFIG_PCI200SYN is not set -# CONFIG_PCIPCWATCHDOG is not set -CONFIG_PCI_SYSCALL=y -CONFIG_PLAT_ORION=y -# CONFIG_PPP is not set -# CONFIG_PRISM54 is not set -# CONFIG_R6040 is not set -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DEBUG is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_TEST is not set -# CONFIG_RTC_DRV_V3020 is not set -# CONFIG_RTC_DRV_X1205 is not set -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_SATA_PMP=y -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_WAIT_SCAN=m -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SERIAL_8250_EXTENDED is not set -# CONFIG_SHMEM is not set -CONFIG_SLABINFO=y -# CONFIG_SMC91X is not set -# CONFIG_SND_AW2 is not set -# CONFIG_SOC_CAMERA is not set -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SOUND is not set -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -CONFIG_SSB_POSSIBLE=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TCP_CONG_HSTCP is not set -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_LP is not set -# CONFIG_TCP_CONG_SCALABLE is not set -CONFIG_TCP_CONG_VEGAS=m -# CONFIG_TCP_CONG_VENO is not set -CONFIG_TCP_CONG_WESTWOOD=y -CONFIG_TICK_ONESHOT=y -CONFIG_TINY_SHMEM=y -# CONFIG_TUN is not set -CONFIG_UID16=y -CONFIG_USB=m -# CONFIG_USBPCWATCHDOG is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_CATC is not set -CONFIG_USB_EHCI_HCD=m -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_HCD=m -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_USBAT is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_UHCI_HCD=m -# CONFIG_USB_USBNET is not set -# CONFIG_USB_WDM is not set -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VFP is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIA_RHINE is not set -CONFIG_VIDEO_MEDIA=m -CONFIG_VIDEO_V4L1=m -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_USB_VIDEO_CLASS is not set -CONFIG_WAN=y -# CONFIG_WANXL is not set -# CONFIG_XFS_FS is not set -# CONFIG_XIP_KERNEL is not set -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/orion/image/Makefile b/target/linux/orion/image/Makefile deleted file mode 100644 index 0ca37678ef..0000000000 --- a/target/linux/orion/image/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Image/Prepare - cp $(LINUX_DIR)/arch/arm/boot/uImage $(KDIR)/uImage -endef - -define Image/BuildKernel -# WRT350N v2: mach id 1633 (0x661) - echo -en "\x06\x1c\xa0\xe3\x61\x10\x81\xe3" > $(KDIR)/wrt350nv2-zImage - cat $(LINUX_DIR)/arch/arm/boot/zImage >> $(KDIR)/wrt350nv2-zImage - $(STAGING_DIR_HOST)/bin/mkimage -A arm -O linux -T kernel \ - -C none -a 0x00008000 -e 0x00008000 -n 'Linux-$(LINUX_VERSION)' \ - -d $(KDIR)/wrt350nv2-zImage $(KDIR)/wrt350nv2-uImage - cp $(KDIR)/wrt350nv2-uImage $(BIN_DIR)/openwrt-wrt350nv2-uImage -# WNR854T: mach id 1801 (0x709) - echo -en "\x07\x1c\xa0\xe3\x09\x10\x81\xe3" > $(KDIR)/wnr854t-zImage - cat $(LINUX_DIR)/arch/arm/boot/zImage >> $(KDIR)/wnr854t-zImage - $(STAGING_DIR_HOST)/bin/mkimage -A arm -O linux -T kernel \ - -C none -a 0x00008000 -e 0x00008000 -n 'Linux-$(LINUX_VERSION)' \ - -d $(KDIR)/wnr854t-zImage $(KDIR)/wnr854t-uImage - cp $(KDIR)/wnr854t-uImage $(BIN_DIR)/openwrt-wnr854t-uImage -endef - -define Image/Build/Netgear - mkdir $(KDIR)/netgear_image - cp $(KDIR)/wnr854t-uImage $(KDIR)/netgear_image/uImage - $(STAGING_DIR_HOST)/bin/mkfs.jffs2 -m none -p -l -q -e 128KiB -o $(KDIR)/wnr854t-uImage.jffs2 -d $(KDIR)/netgear_image - rm -rf $(KDIR)/netgear_image - ( \ - dd if=$(KDIR)/wnr854t-uImage.jffs2 bs=1024k conv=sync; \ - dd if=$(KDIR)/root.$(1) bs=128k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(2)-$(1).img - $(STAGING_DIR_HOST)/bin/add_header $(3) $(BIN_DIR)/openwrt-$(2)-$(1).img $(BIN_DIR)/openwrt-$(2)-$(1)-webupgrade.img -endef - -define Image/Build/Linksys -# placeholder for the WRT350N v2 -endef - -define Image/Build - $(call Image/Build/$(1),$(1)) - $(call Image/Build/Netgear,$(1),wnr854t,NG_WNR854T,$(1)) - $(call Image/Build/Linksys,$(1),wrt350nv2,WNR350Nv2,$(1)) -endef - -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) - ( \ - dd if=$(KDIR)/uImage bs=1024k conv=sync; \ - dd if=$(KDIR)/root.$(1) bs=128k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(BOARD)-$(1).img -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/orion/patches/000-orion_git_sync.patch b/target/linux/orion/patches/000-orion_git_sync.patch deleted file mode 100644 index 4daef75d5b..0000000000 --- a/target/linux/orion/patches/000-orion_git_sync.patch +++ /dev/null @@ -1,19752 +0,0 @@ ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -2691,12 +2691,10 @@ - S: Maintained - - MARVELL MV643XX ETHERNET DRIVER --P: Dale Farnsworth --M: dale@farnsworth.org --P: Manish Lachwani --M: mlachwani@mvista.com -+P: Lennert Buytenhek -+M: buytenh@marvell.com - L: netdev@vger.kernel.org --S: Odd Fixes for 2.4; Maintained for 2.6. -+S: Supported - - MATROX FRAMEBUFFER DRIVER - P: Petr Vandrovec ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -84,6 +84,11 @@ - bool - default y - -+config HAVE_LATENCYTOP_SUPPORT -+ bool -+ depends on !SMP -+ default y -+ - config LOCKDEP_SUPPORT - bool - default y -@@ -347,6 +352,16 @@ - If you have any questions or comments about the Linux kernel port - to this board, send e-mail to . - -+config ARCH_KIRKWOOD -+ bool "Marvell Kirkwood" -+ select PCI -+ select GENERIC_TIME -+ select GENERIC_CLOCKEVENTS -+ select PLAT_ORION -+ help -+ Support for the following Marvell Kirkwood series SoCs: -+ 88F6180, 88F6192 and 88F6281. -+ - config ARCH_KS8695 - bool "Micrel/Kendin KS8695" - select GENERIC_GPIO -@@ -365,6 +380,24 @@ - - - -+config ARCH_LOKI -+ bool "Marvell Loki (88RC8480)" -+ select GENERIC_TIME -+ select GENERIC_CLOCKEVENTS -+ select PLAT_ORION -+ help -+ Support for the Marvell Loki (88RC8480) SoC. -+ -+config ARCH_MV78XX0 -+ bool "Marvell MV78xx0" -+ select PCI -+ select GENERIC_TIME -+ select GENERIC_CLOCKEVENTS -+ select PLAT_ORION -+ help -+ Support for the following Marvell MV78xx0 series SoCs: -+ MV781x0, MV782x0. -+ - config ARCH_MXC - bool "Freescale MXC/iMX-based" - select ARCH_MTD_XIP -@@ -381,7 +414,8 @@ - select PLAT_ORION - help - Support for the following Marvell Orion 5x series SoCs: -- Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) -+ Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), -+ Orion-2 (5281). - - config ARCH_PNX4008 - bool "Philips Nexperia PNX4008 Mobile" -@@ -502,6 +536,10 @@ - - source "arch/arm/mach-ixp23xx/Kconfig" - -+source "arch/arm/mach-loki/Kconfig" -+ -+source "arch/arm/mach-mv78xx0/Kconfig" -+ - source "arch/arm/mach-pxa/Kconfig" - - source "arch/arm/mach-sa1100/Kconfig" -@@ -514,6 +552,8 @@ - - source "arch/arm/mach-orion5x/Kconfig" - -+source "arch/arm/mach-kirkwood/Kconfig" -+ - source "arch/arm/plat-s3c24xx/Kconfig" - source "arch/arm/plat-s3c/Kconfig" - ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -135,11 +135,14 @@ - machine-$(CONFIG_ARCH_NETX) := netx - machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx - machine-$(CONFIG_ARCH_DAVINCI) := davinci -+ machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood - machine-$(CONFIG_ARCH_KS8695) := ks8695 - incdir-$(CONFIG_ARCH_MXC) := mxc - machine-$(CONFIG_ARCH_MX3) := mx3 - machine-$(CONFIG_ARCH_ORION5X) := orion5x - machine-$(CONFIG_ARCH_MSM7X00A) := msm -+ machine-$(CONFIG_ARCH_LOKI) := loki -+ machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 - - ifeq ($(CONFIG_ARCH_EBSA110),y) - # This is what happens if you forget the IOCS16 line. ---- a/arch/arm/boot/compressed/head.S -+++ b/arch/arm/boot/compressed/head.S -@@ -623,8 +623,8 @@ - b __armv4_mmu_cache_off - b __armv4_mmu_cache_flush - -- .word 0x56055310 @ Feroceon -- .word 0xfffffff0 -+ .word 0x56050000 @ Feroceon -+ .word 0xff0f0000 - b __armv4_mmu_cache_on - b __armv4_mmu_cache_off - b __armv5tej_mmu_cache_flush ---- /dev/null -+++ b/arch/arm/configs/kirkwood_defconfig -@@ -0,0 +1,1426 @@ -+# -+# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.26-rc5 -+# Sun Jun 22 15:51:25 2008 -+# -+CONFIG_ARM=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+CONFIG_GENERIC_GPIO=y -+CONFIG_GENERIC_TIME=y -+CONFIG_GENERIC_CLOCKEVENTS=y -+CONFIG_MMU=y -+# CONFIG_NO_IOPORT is not set -+CONFIG_GENERIC_HARDIRQS=y -+CONFIG_STACKTRACE_SUPPORT=y -+CONFIG_HAVE_LATENCYTOP_SUPPORT=y -+CONFIG_LOCKDEP_SUPPORT=y -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_HARDIRQS_SW_RESEND=y -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_RWSEM_GENERIC_SPINLOCK=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ARCH_SUPPORTS_AOUT=y -+CONFIG_ZONE_DMA=y -+CONFIG_VECTORS_BASE=0xffff0000 -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+ -+# -+# General setup -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_BROKEN_ON_SMP=y -+CONFIG_LOCK_KERNEL=y -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+CONFIG_LOCALVERSION="" -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+CONFIG_SYSVIPC_SYSCTL=y -+# CONFIG_POSIX_MQUEUE is not set -+# CONFIG_BSD_PROCESS_ACCT is not set -+# CONFIG_TASKSTATS is not set -+# CONFIG_AUDIT is not set -+# CONFIG_IKCONFIG is not set -+CONFIG_LOG_BUF_SHIFT=14 -+# CONFIG_CGROUPS is not set -+# CONFIG_GROUP_SCHED is not set -+# CONFIG_SYSFS_DEPRECATED_V2 is not set -+# CONFIG_RELAY is not set -+# CONFIG_NAMESPACES is not set -+# CONFIG_BLK_DEV_INITRD is not set -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_SYSCTL=y -+CONFIG_EMBEDDED=y -+CONFIG_UID16=y -+CONFIG_SYSCTL_SYSCALL=y -+CONFIG_SYSCTL_SYSCALL_CHECK=y -+CONFIG_KALLSYMS=y -+# CONFIG_KALLSYMS_ALL is not set -+# CONFIG_KALLSYMS_EXTRA_PASS is not set -+CONFIG_HOTPLUG=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+CONFIG_COMPAT_BRK=y -+CONFIG_BASE_FULL=y -+CONFIG_FUTEX=y -+CONFIG_ANON_INODES=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_TIMERFD=y -+CONFIG_EVENTFD=y -+CONFIG_SHMEM=y -+CONFIG_VM_EVENT_COUNTERS=y -+CONFIG_SLAB=y -+# CONFIG_SLUB is not set -+# CONFIG_SLOB is not set -+CONFIG_PROFILING=y -+# CONFIG_MARKERS is not set -+CONFIG_OPROFILE=y -+CONFIG_HAVE_OPROFILE=y -+CONFIG_KPROBES=y -+CONFIG_KRETPROBES=y -+CONFIG_HAVE_KPROBES=y -+CONFIG_HAVE_KRETPROBES=y -+# CONFIG_HAVE_DMA_ATTRS is not set -+CONFIG_PROC_PAGE_MONITOR=y -+CONFIG_SLABINFO=y -+CONFIG_RT_MUTEXES=y -+# CONFIG_TINY_SHMEM is not set -+CONFIG_BASE_SMALL=0 -+CONFIG_MODULES=y -+# CONFIG_MODULE_FORCE_LOAD is not set -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_MODULE_FORCE_UNLOAD is not set -+# CONFIG_MODVERSIONS is not set -+# CONFIG_MODULE_SRCVERSION_ALL is not set -+# CONFIG_KMOD is not set -+CONFIG_BLOCK=y -+# CONFIG_LBD is not set -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set -+# CONFIG_BLK_DEV_BSG is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_AS=y -+CONFIG_IOSCHED_DEADLINE=y -+CONFIG_IOSCHED_CFQ=y -+# CONFIG_DEFAULT_AS is not set -+# CONFIG_DEFAULT_DEADLINE is not set -+CONFIG_DEFAULT_CFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="cfq" -+CONFIG_CLASSIC_RCU=y -+ -+# -+# System Type -+# -+# CONFIG_ARCH_AAEC2000 is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_REALVIEW is not set -+# CONFIG_ARCH_VERSATILE is not set -+# CONFIG_ARCH_AT91 is not set -+# CONFIG_ARCH_CLPS7500 is not set -+# CONFIG_ARCH_CLPS711X is not set -+# CONFIG_ARCH_CO285 is not set -+# CONFIG_ARCH_EBSA110 is not set -+# CONFIG_ARCH_EP93XX is not set -+# CONFIG_ARCH_FOOTBRIDGE is not set -+# CONFIG_ARCH_NETX is not set -+# CONFIG_ARCH_H720X is not set -+# CONFIG_ARCH_IMX is not set -+# CONFIG_ARCH_IOP13XX is not set -+# CONFIG_ARCH_IOP32X is not set -+# CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IXP23XX is not set -+# CONFIG_ARCH_IXP2000 is not set -+# CONFIG_ARCH_IXP4XX is not set -+# CONFIG_ARCH_L7200 is not set -+CONFIG_ARCH_KIRKWOOD=y -+# CONFIG_ARCH_KS8695 is not set -+# CONFIG_ARCH_NS9XXX is not set -+# CONFIG_ARCH_LOKI is not set -+# CONFIG_ARCH_MV78XX0 is not set -+# CONFIG_ARCH_MXC is not set -+# CONFIG_ARCH_ORION5X is not set -+# CONFIG_ARCH_PNX4008 is not set -+# CONFIG_ARCH_PXA is not set -+# CONFIG_ARCH_RPC is not set -+# CONFIG_ARCH_SA1100 is not set -+# CONFIG_ARCH_S3C2410 is not set -+# CONFIG_ARCH_SHARK is not set -+# CONFIG_ARCH_LH7A40X is not set -+# CONFIG_ARCH_DAVINCI is not set -+# CONFIG_ARCH_OMAP is not set -+# CONFIG_ARCH_MSM7X00A is not set -+ -+# -+# Marvell Kirkwood Implementations -+# -+CONFIG_MACH_DB88F6281_BP=y -+CONFIG_MACH_RD88F6192_NAS=y -+CONFIG_MACH_RD88F6281=y -+ -+# -+# Boot options -+# -+ -+# -+# Power management -+# -+CONFIG_PLAT_ORION=y -+ -+# -+# Processor Type -+# -+CONFIG_CPU_32=y -+CONFIG_CPU_FEROCEON=y -+# CONFIG_CPU_FEROCEON_OLD_ID is not set -+CONFIG_CPU_32v5=y -+CONFIG_CPU_ABRT_EV5T=y -+CONFIG_CPU_PABRT_NOIFAR=y -+CONFIG_CPU_CACHE_VIVT=y -+CONFIG_CPU_COPY_FEROCEON=y -+CONFIG_CPU_TLB_FEROCEON=y -+CONFIG_CPU_CP15=y -+CONFIG_CPU_CP15_MMU=y -+ -+# -+# Processor Features -+# -+CONFIG_ARM_THUMB=y -+# CONFIG_CPU_ICACHE_DISABLE is not set -+# CONFIG_CPU_DCACHE_DISABLE is not set -+CONFIG_OUTER_CACHE=y -+CONFIG_CACHE_FEROCEON_L2=y -+ -+# -+# Bus support -+# -+CONFIG_PCI=y -+CONFIG_PCI_SYSCALL=y -+# CONFIG_ARCH_SUPPORTS_MSI is not set -+CONFIG_PCI_LEGACY=y -+# CONFIG_PCI_DEBUG is not set -+# CONFIG_PCCARD is not set -+ -+# -+# Kernel Features -+# -+CONFIG_TICK_ONESHOT=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -+CONFIG_PREEMPT=y -+CONFIG_HZ=100 -+CONFIG_AEABI=y -+# CONFIG_OABI_COMPAT is not set -+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+# CONFIG_SPARSEMEM_STATIC is not set -+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -+CONFIG_PAGEFLAGS_EXTENDED=y -+CONFIG_SPLIT_PTLOCK_CPUS=4096 -+# CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 -+CONFIG_BOUNCE=y -+CONFIG_VIRT_TO_BUS=y -+CONFIG_ALIGNMENT_TRAP=y -+ -+# -+# Boot options -+# -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CMDLINE="" -+# CONFIG_XIP_KERNEL is not set -+# CONFIG_KEXEC is not set -+ -+# -+# Floating point emulation -+# -+ -+# -+# At least one emulation must be selected -+# -+# CONFIG_VFP is not set -+ -+# -+# Userspace binary formats -+# -+CONFIG_BINFMT_ELF=y -+# CONFIG_BINFMT_AOUT is not set -+# CONFIG_BINFMT_MISC is not set -+ -+# -+# Power management options -+# -+# CONFIG_PM is not set -+CONFIG_ARCH_SUSPEND_POSSIBLE=y -+ -+# -+# Networking -+# -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+CONFIG_PACKET_MMAP=y -+CONFIG_UNIX=y -+CONFIG_XFRM=y -+# CONFIG_XFRM_USER is not set -+# CONFIG_XFRM_SUB_POLICY is not set -+# CONFIG_XFRM_MIGRATE is not set -+# CONFIG_XFRM_STATISTICS is not set -+# CONFIG_NET_KEY is not set -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+# CONFIG_IP_ADVANCED_ROUTER is not set -+CONFIG_IP_FIB_HASH=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+# CONFIG_IP_PNP_RARP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_IP_MROUTE is not set -+# CONFIG_ARPD is not set -+# CONFIG_SYN_COOKIES is not set -+# CONFIG_INET_AH is not set -+# CONFIG_INET_ESP is not set -+# CONFIG_INET_IPCOMP is not set -+# CONFIG_INET_XFRM_TUNNEL is not set -+# CONFIG_INET_TUNNEL is not set -+CONFIG_INET_XFRM_MODE_TRANSPORT=y -+CONFIG_INET_XFRM_MODE_TUNNEL=y -+CONFIG_INET_XFRM_MODE_BEET=y -+# CONFIG_INET_LRO is not set -+CONFIG_INET_DIAG=y -+CONFIG_INET_TCP_DIAG=y -+# CONFIG_TCP_CONG_ADVANCED is not set -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set -+# CONFIG_IPV6 is not set -+# CONFIG_NETWORK_SECMARK is not set -+# CONFIG_NETFILTER is not set -+# CONFIG_IP_DCCP is not set -+# CONFIG_IP_SCTP is not set -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+# CONFIG_NET_SCHED is not set -+ -+# -+# Network testing -+# -+CONFIG_NET_PKTGEN=m -+# CONFIG_NET_TCPPROBE is not set -+# CONFIG_HAMRADIO is not set -+# CONFIG_CAN is not set -+# CONFIG_IRDA is not set -+# CONFIG_BT is not set -+# CONFIG_AF_RXRPC is not set -+ -+# -+# Wireless -+# -+# CONFIG_CFG80211 is not set -+CONFIG_WIRELESS_EXT=y -+# CONFIG_MAC80211 is not set -+# CONFIG_IEEE80211 is not set -+# CONFIG_RFKILL is not set -+# CONFIG_NET_9P is not set -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+CONFIG_FW_LOADER=y -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set -+# CONFIG_SYS_HYPERVISOR is not set -+# CONFIG_CONNECTOR is not set -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+# CONFIG_MTD_CONCAT is not set -+CONFIG_MTD_PARTITIONS=y -+# CONFIG_MTD_REDBOOT_PARTS is not set -+CONFIG_MTD_CMDLINE_PARTS=y -+# CONFIG_MTD_AFS_PARTS is not set -+# CONFIG_MTD_AR7_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLKDEVS=y -+CONFIG_MTD_BLOCK=y -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+# CONFIG_MTD_OOPS is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+CONFIG_MTD_CFI=y -+CONFIG_MTD_JEDECPROBE=y -+CONFIG_MTD_GEN_PROBE=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_NOSWAP=y -+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -+CONFIG_MTD_CFI_GEOMETRY=y -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+# CONFIG_MTD_OTP is not set -+CONFIG_MTD_CFI_INTELEXT=y -+# CONFIG_MTD_CFI_AMDSTD is not set -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_CFI_UTIL=y -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+ -+# -+# Mapping drivers for chip access -+# -+# CONFIG_MTD_COMPLEX_MAPPINGS is not set -+CONFIG_MTD_PHYSMAP=y -+CONFIG_MTD_PHYSMAP_START=0x0 -+CONFIG_MTD_PHYSMAP_LEN=0x0 -+CONFIG_MTD_PHYSMAP_BANKWIDTH=0 -+# CONFIG_MTD_ARM_INTEGRATOR is not set -+# CONFIG_MTD_IMPA7 is not set -+# CONFIG_MTD_INTEL_VR_NOR is not set -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_PMC551 is not set -+# CONFIG_MTD_DATAFLASH is not set -+CONFIG_MTD_M25P80=y -+CONFIG_M25PXX_USE_FAST_READ=y -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+CONFIG_MTD_NAND=y -+CONFIG_MTD_NAND_VERIFY_WRITE=y -+# CONFIG_MTD_NAND_ECC_SMC is not set -+# CONFIG_MTD_NAND_MUSEUM_IDS is not set -+CONFIG_MTD_NAND_IDS=y -+# CONFIG_MTD_NAND_DISKONCHIP is not set -+# CONFIG_MTD_NAND_CAFE is not set -+# CONFIG_MTD_NAND_NANDSIM is not set -+# CONFIG_MTD_NAND_PLATFORM is not set -+# CONFIG_MTD_ALAUDA is not set -+CONFIG_MTD_NAND_ORION=y -+# CONFIG_MTD_ONENAND is not set -+ -+# -+# UBI - Unsorted block images -+# -+# CONFIG_MTD_UBI is not set -+# CONFIG_PARPORT is not set -+CONFIG_BLK_DEV=y -+# CONFIG_BLK_CPQ_DA is not set -+# CONFIG_BLK_CPQ_CISS_DA is not set -+# CONFIG_BLK_DEV_DAC960 is not set -+# CONFIG_BLK_DEV_UMEM is not set -+# CONFIG_BLK_DEV_COW_COMMON is not set -+CONFIG_BLK_DEV_LOOP=y -+# CONFIG_BLK_DEV_CRYPTOLOOP is not set -+# CONFIG_BLK_DEV_NBD is not set -+# CONFIG_BLK_DEV_SX8 is not set -+# CONFIG_BLK_DEV_UB is not set -+# CONFIG_BLK_DEV_RAM is not set -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+# CONFIG_MISC_DEVICES is not set -+CONFIG_HAVE_IDE=y -+# CONFIG_IDE is not set -+ -+# -+# SCSI device support -+# -+# CONFIG_RAID_ATTRS is not set -+CONFIG_SCSI=y -+CONFIG_SCSI_DMA=y -+# CONFIG_SCSI_TGT is not set -+# CONFIG_SCSI_NETLINK is not set -+# CONFIG_SCSI_PROC_FS is not set -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+# CONFIG_CHR_DEV_OSST is not set -+CONFIG_BLK_DEV_SR=m -+# CONFIG_BLK_DEV_SR_VENDOR is not set -+CONFIG_CHR_DEV_SG=m -+# CONFIG_CHR_DEV_SCH is not set -+ -+# -+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -+# -+# CONFIG_SCSI_MULTI_LUN is not set -+# CONFIG_SCSI_CONSTANTS is not set -+# CONFIG_SCSI_LOGGING is not set -+# CONFIG_SCSI_SCAN_ASYNC is not set -+CONFIG_SCSI_WAIT_SCAN=m -+ -+# -+# SCSI Transports -+# -+# CONFIG_SCSI_SPI_ATTRS is not set -+# CONFIG_SCSI_FC_ATTRS is not set -+# CONFIG_SCSI_ISCSI_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+# CONFIG_SCSI_SRP_ATTRS is not set -+CONFIG_SCSI_LOWLEVEL=y -+# CONFIG_ISCSI_TCP is not set -+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -+# CONFIG_SCSI_3W_9XXX is not set -+# CONFIG_SCSI_ACARD is not set -+# CONFIG_SCSI_AACRAID is not set -+# CONFIG_SCSI_AIC7XXX is not set -+# CONFIG_SCSI_AIC7XXX_OLD is not set -+# CONFIG_SCSI_AIC79XX is not set -+# CONFIG_SCSI_AIC94XX is not set -+# CONFIG_SCSI_DPT_I2O is not set -+# CONFIG_SCSI_ADVANSYS is not set -+# CONFIG_SCSI_ARCMSR is not set -+# CONFIG_MEGARAID_NEWGEN is not set -+# CONFIG_MEGARAID_LEGACY is not set -+# CONFIG_MEGARAID_SAS is not set -+# CONFIG_SCSI_HPTIOP is not set -+# CONFIG_SCSI_DMX3191D is not set -+# CONFIG_SCSI_FUTURE_DOMAIN is not set -+# CONFIG_SCSI_IPS is not set -+# CONFIG_SCSI_INITIO is not set -+# CONFIG_SCSI_INIA100 is not set -+# CONFIG_SCSI_MVSAS is not set -+# CONFIG_SCSI_STEX is not set -+# CONFIG_SCSI_SYM53C8XX_2 is not set -+# CONFIG_SCSI_IPR is not set -+# CONFIG_SCSI_QLOGIC_1280 is not set -+# CONFIG_SCSI_QLA_FC is not set -+# CONFIG_SCSI_QLA_ISCSI is not set -+# CONFIG_SCSI_LPFC is not set -+# CONFIG_SCSI_DC395x is not set -+# CONFIG_SCSI_DC390T is not set -+# CONFIG_SCSI_NSP32 is not set -+# CONFIG_SCSI_DEBUG is not set -+# CONFIG_SCSI_SRP is not set -+CONFIG_ATA=y -+# CONFIG_ATA_NONSTANDARD is not set -+CONFIG_SATA_PMP=y -+# CONFIG_SATA_AHCI is not set -+# CONFIG_SATA_SIL24 is not set -+CONFIG_ATA_SFF=y -+# CONFIG_SATA_SVW is not set -+# CONFIG_ATA_PIIX is not set -+CONFIG_SATA_MV=y -+# CONFIG_SATA_NV is not set -+# CONFIG_PDC_ADMA is not set -+# CONFIG_SATA_QSTOR is not set -+# CONFIG_SATA_PROMISE is not set -+# CONFIG_SATA_SX4 is not set -+# CONFIG_SATA_SIL is not set -+# CONFIG_SATA_SIS is not set -+# CONFIG_SATA_ULI is not set -+# CONFIG_SATA_VIA is not set -+# CONFIG_SATA_VITESSE is not set -+# CONFIG_SATA_INIC162X is not set -+# CONFIG_PATA_ALI is not set -+# CONFIG_PATA_AMD is not set -+# CONFIG_PATA_ARTOP is not set -+# CONFIG_PATA_ATIIXP is not set -+# CONFIG_PATA_CMD640_PCI is not set -+# CONFIG_PATA_CMD64X is not set -+# CONFIG_PATA_CS5520 is not set -+# CONFIG_PATA_CS5530 is not set -+# CONFIG_PATA_CYPRESS is not set -+# CONFIG_PATA_EFAR is not set -+# CONFIG_ATA_GENERIC is not set -+# CONFIG_PATA_HPT366 is not set -+# CONFIG_PATA_HPT37X is not set -+# CONFIG_PATA_HPT3X2N is not set -+# CONFIG_PATA_HPT3X3 is not set -+# CONFIG_PATA_IT821X is not set -+# CONFIG_PATA_IT8213 is not set -+# CONFIG_PATA_JMICRON is not set -+# CONFIG_PATA_TRIFLEX is not set -+# CONFIG_PATA_MARVELL is not set -+# CONFIG_PATA_MPIIX is not set -+# CONFIG_PATA_OLDPIIX is not set -+# CONFIG_PATA_NETCELL is not set -+# CONFIG_PATA_NINJA32 is not set -+# CONFIG_PATA_NS87410 is not set -+# CONFIG_PATA_NS87415 is not set -+# CONFIG_PATA_OPTI is not set -+# CONFIG_PATA_OPTIDMA is not set -+# CONFIG_PATA_PDC_OLD is not set -+# CONFIG_PATA_RADISYS is not set -+# CONFIG_PATA_RZ1000 is not set -+# CONFIG_PATA_SC1200 is not set -+# CONFIG_PATA_SERVERWORKS is not set -+# CONFIG_PATA_PDC2027X is not set -+# CONFIG_PATA_SIL680 is not set -+# CONFIG_PATA_SIS is not set -+# CONFIG_PATA_VIA is not set -+# CONFIG_PATA_WINBOND is not set -+# CONFIG_PATA_PLATFORM is not set -+# CONFIG_PATA_SCH is not set -+# CONFIG_MD is not set -+# CONFIG_FUSION is not set -+ -+# -+# IEEE 1394 (FireWire) support -+# -+# CONFIG_FIREWIRE is not set -+# CONFIG_IEEE1394 is not set -+# CONFIG_I2O is not set -+CONFIG_NETDEVICES=y -+# CONFIG_NETDEVICES_MULTIQUEUE is not set -+# CONFIG_DUMMY is not set -+# CONFIG_BONDING is not set -+# CONFIG_MACVLAN is not set -+# CONFIG_EQUALIZER is not set -+# CONFIG_TUN is not set -+# CONFIG_VETH is not set -+# CONFIG_ARCNET is not set -+# CONFIG_PHYLIB is not set -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=y -+# CONFIG_AX88796 is not set -+# CONFIG_HAPPYMEAL is not set -+# CONFIG_SUNGEM is not set -+# CONFIG_CASSINI is not set -+# CONFIG_NET_VENDOR_3COM is not set -+# CONFIG_SMC91X is not set -+# CONFIG_DM9000 is not set -+# CONFIG_ENC28J60 is not set -+# CONFIG_NET_TULIP is not set -+# CONFIG_HP100 is not set -+# CONFIG_IBM_NEW_EMAC_ZMII is not set -+# CONFIG_IBM_NEW_EMAC_RGMII is not set -+# CONFIG_IBM_NEW_EMAC_TAH is not set -+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -+CONFIG_NET_PCI=y -+# CONFIG_PCNET32 is not set -+# CONFIG_AMD8111_ETH is not set -+# CONFIG_ADAPTEC_STARFIRE is not set -+# CONFIG_B44 is not set -+# CONFIG_FORCEDETH is not set -+# CONFIG_EEPRO100 is not set -+# CONFIG_E100 is not set -+# CONFIG_FEALNX is not set -+# CONFIG_NATSEMI is not set -+# CONFIG_NE2K_PCI is not set -+# CONFIG_8139CP is not set -+# CONFIG_8139TOO is not set -+# CONFIG_R6040 is not set -+# CONFIG_SIS900 is not set -+# CONFIG_EPIC100 is not set -+# CONFIG_SUNDANCE is not set -+# CONFIG_TLAN is not set -+# CONFIG_VIA_RHINE is not set -+# CONFIG_SC92031 is not set -+CONFIG_NETDEV_1000=y -+# CONFIG_ACENIC is not set -+# CONFIG_DL2K is not set -+CONFIG_E1000=y -+CONFIG_E1000_NAPI=y -+# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set -+# CONFIG_E1000E is not set -+# CONFIG_E1000E_ENABLED is not set -+# CONFIG_IP1000 is not set -+# CONFIG_IGB is not set -+# CONFIG_NS83820 is not set -+# CONFIG_HAMACHI is not set -+# CONFIG_YELLOWFIN is not set -+# CONFIG_R8169 is not set -+# CONFIG_SIS190 is not set -+# CONFIG_SKGE is not set -+# CONFIG_SKY2 is not set -+# CONFIG_VIA_VELOCITY is not set -+# CONFIG_TIGON3 is not set -+# CONFIG_BNX2 is not set -+CONFIG_MV643XX_ETH=y -+# CONFIG_QLA3XXX is not set -+# CONFIG_ATL1 is not set -+# CONFIG_NETDEV_10000 is not set -+# CONFIG_TR is not set -+ -+# -+# Wireless LAN -+# -+# CONFIG_WLAN_PRE80211 is not set -+# CONFIG_WLAN_80211 is not set -+# CONFIG_IWLWIFI_LEDS is not set -+ -+# -+# USB Network Adapters -+# -+# CONFIG_USB_CATC is not set -+# CONFIG_USB_KAWETH is not set -+# CONFIG_USB_PEGASUS is not set -+# CONFIG_USB_RTL8150 is not set -+# CONFIG_USB_USBNET is not set -+# CONFIG_WAN is not set -+# CONFIG_FDDI is not set -+# CONFIG_HIPPI is not set -+# CONFIG_PPP is not set -+# CONFIG_SLIP is not set -+# CONFIG_NET_FC is not set -+# CONFIG_NETCONSOLE is not set -+# CONFIG_NETPOLL is not set -+# CONFIG_NET_POLL_CONTROLLER is not set -+# CONFIG_ISDN is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+# CONFIG_INPUT_FF_MEMLESS is not set -+# CONFIG_INPUT_POLLDEV is not set -+ -+# -+# Userland interfaces -+# -+CONFIG_INPUT_MOUSEDEV=y -+CONFIG_INPUT_MOUSEDEV_PSAUX=y -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+# CONFIG_INPUT_JOYDEV is not set -+# CONFIG_INPUT_EVDEV is not set -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+# CONFIG_INPUT_KEYBOARD is not set -+# CONFIG_INPUT_MOUSE is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TABLET is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+# CONFIG_INPUT_MISC is not set -+ -+# -+# Hardware I/O ports -+# -+# CONFIG_SERIO is not set -+# CONFIG_GAMEPORT is not set -+ -+# -+# Character devices -+# -+# CONFIG_VT is not set -+# CONFIG_DEVKMEM is not set -+# CONFIG_SERIAL_NONSTANDARD is not set -+# CONFIG_NOZOMI is not set -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+# CONFIG_SERIAL_8250_PCI is not set -+CONFIG_SERIAL_8250_NR_UARTS=4 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -+# CONFIG_SERIAL_8250_EXTENDED is not set -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+# CONFIG_SERIAL_JSM is not set -+CONFIG_UNIX98_PTYS=y -+CONFIG_LEGACY_PTYS=y -+CONFIG_LEGACY_PTY_COUNT=16 -+# CONFIG_IPMI_HANDLER is not set -+# CONFIG_HW_RANDOM is not set -+# CONFIG_NVRAM is not set -+# CONFIG_R3964 is not set -+# CONFIG_APPLICOM is not set -+# CONFIG_RAW_DRIVER is not set -+# CONFIG_TCG_TPM is not set -+CONFIG_DEVPORT=y -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_CHARDEV=y -+ -+# -+# I2C Hardware Bus support -+# -+# CONFIG_I2C_ALI1535 is not set -+# CONFIG_I2C_ALI1563 is not set -+# CONFIG_I2C_ALI15X3 is not set -+# CONFIG_I2C_AMD756 is not set -+# CONFIG_I2C_AMD8111 is not set -+# CONFIG_I2C_GPIO is not set -+# CONFIG_I2C_I801 is not set -+# CONFIG_I2C_I810 is not set -+# CONFIG_I2C_PIIX4 is not set -+# CONFIG_I2C_NFORCE2 is not set -+# CONFIG_I2C_OCORES is not set -+# CONFIG_I2C_PARPORT_LIGHT is not set -+# CONFIG_I2C_PROSAVAGE is not set -+# CONFIG_I2C_SAVAGE4 is not set -+# CONFIG_I2C_SIMTEC is not set -+# CONFIG_I2C_SIS5595 is not set -+# CONFIG_I2C_SIS630 is not set -+# CONFIG_I2C_SIS96X is not set -+# CONFIG_I2C_TAOS_EVM is not set -+# CONFIG_I2C_STUB is not set -+# CONFIG_I2C_TINY_USB is not set -+# CONFIG_I2C_VIA is not set -+# CONFIG_I2C_VIAPRO is not set -+# CONFIG_I2C_VOODOO3 is not set -+# CONFIG_I2C_PCA_PLATFORM is not set -+CONFIG_I2C_MV64XXX=y -+ -+# -+# Miscellaneous I2C Chip support -+# -+# CONFIG_DS1682 is not set -+# CONFIG_SENSORS_EEPROM is not set -+# CONFIG_SENSORS_PCF8574 is not set -+# CONFIG_PCF8575 is not set -+# CONFIG_SENSORS_PCF8591 is not set -+# CONFIG_SENSORS_MAX6875 is not set -+# CONFIG_SENSORS_TSL2550 is not set -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_ALGO is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+# CONFIG_I2C_DEBUG_CHIP is not set -+CONFIG_SPI=y -+# CONFIG_SPI_DEBUG is not set -+CONFIG_SPI_MASTER=y -+ -+# -+# SPI Master Controller Drivers -+# -+# CONFIG_SPI_BITBANG is not set -+CONFIG_SPI_ORION=y -+ -+# -+# SPI Protocol Masters -+# -+# CONFIG_SPI_AT25 is not set -+# CONFIG_SPI_SPIDEV is not set -+# CONFIG_SPI_TLE62X0 is not set -+# CONFIG_W1 is not set -+# CONFIG_POWER_SUPPLY is not set -+# CONFIG_HWMON is not set -+# CONFIG_WATCHDOG is not set -+ -+# -+# Sonics Silicon Backplane -+# -+CONFIG_SSB_POSSIBLE=y -+# CONFIG_SSB is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set -+# CONFIG_MFD_ASIC3 is not set -+# CONFIG_HTC_PASIC3 is not set -+ -+# -+# Multimedia devices -+# -+ -+# -+# Multimedia core support -+# -+# CONFIG_VIDEO_DEV is not set -+# CONFIG_DVB_CORE is not set -+# CONFIG_VIDEO_MEDIA is not set -+ -+# -+# Multimedia drivers -+# -+# CONFIG_DAB is not set -+ -+# -+# Graphics support -+# -+# CONFIG_DRM is not set -+# CONFIG_VGASTATE is not set -+# CONFIG_VIDEO_OUTPUT_CONTROL is not set -+# CONFIG_FB is not set -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -+ -+# -+# Display device support -+# -+# CONFIG_DISPLAY_SUPPORT is not set -+ -+# -+# Sound -+# -+# CONFIG_SOUND is not set -+CONFIG_HID_SUPPORT=y -+CONFIG_HID=y -+# CONFIG_HID_DEBUG is not set -+# CONFIG_HIDRAW is not set -+ -+# -+# USB Input Devices -+# -+CONFIG_USB_HID=y -+# CONFIG_USB_HIDINPUT_POWERBOOK is not set -+# CONFIG_HID_FF is not set -+# CONFIG_USB_HIDDEV is not set -+CONFIG_USB_SUPPORT=y -+CONFIG_USB_ARCH_HAS_HCD=y -+CONFIG_USB_ARCH_HAS_OHCI=y -+CONFIG_USB_ARCH_HAS_EHCI=y -+CONFIG_USB=y -+# CONFIG_USB_DEBUG is not set -+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set -+ -+# -+# Miscellaneous USB options -+# -+CONFIG_USB_DEVICEFS=y -+CONFIG_USB_DEVICE_CLASS=y -+# CONFIG_USB_DYNAMIC_MINORS is not set -+# CONFIG_USB_OTG is not set -+# CONFIG_USB_OTG_WHITELIST is not set -+# CONFIG_USB_OTG_BLACKLIST_HUB is not set -+ -+# -+# USB Host Controller Drivers -+# -+# CONFIG_USB_C67X00_HCD is not set -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_ROOT_HUB_TT=y -+CONFIG_USB_EHCI_TT_NEWSCHED=y -+# CONFIG_USB_ISP116X_HCD is not set -+# CONFIG_USB_ISP1760_HCD is not set -+# CONFIG_USB_OHCI_HCD is not set -+# CONFIG_USB_UHCI_HCD is not set -+# CONFIG_USB_SL811_HCD is not set -+# CONFIG_USB_R8A66597_HCD is not set -+ -+# -+# USB Device Class drivers -+# -+# CONFIG_USB_ACM is not set -+CONFIG_USB_PRINTER=y -+# CONFIG_USB_WDM is not set -+ -+# -+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -+# -+ -+# -+# may also be needed; see USB_STORAGE Help for more information -+# -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+CONFIG_USB_STORAGE_DATAFAB=y -+CONFIG_USB_STORAGE_FREECOM=y -+# CONFIG_USB_STORAGE_ISD200 is not set -+CONFIG_USB_STORAGE_DPCM=y -+# CONFIG_USB_STORAGE_USBAT is not set -+CONFIG_USB_STORAGE_SDDR09=y -+CONFIG_USB_STORAGE_SDDR55=y -+CONFIG_USB_STORAGE_JUMPSHOT=y -+# CONFIG_USB_STORAGE_ALAUDA is not set -+# CONFIG_USB_STORAGE_ONETOUCH is not set -+# CONFIG_USB_STORAGE_KARMA is not set -+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -+# CONFIG_USB_LIBUSUAL is not set -+ -+# -+# USB Imaging devices -+# -+# CONFIG_USB_MDC800 is not set -+# CONFIG_USB_MICROTEK is not set -+# CONFIG_USB_MON is not set -+ -+# -+# USB port drivers -+# -+# CONFIG_USB_SERIAL is not set -+ -+# -+# USB Miscellaneous drivers -+# -+# CONFIG_USB_EMI62 is not set -+# CONFIG_USB_EMI26 is not set -+# CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_AUERSWALD is not set -+# CONFIG_USB_RIO500 is not set -+# CONFIG_USB_LEGOTOWER is not set -+# CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set -+# CONFIG_USB_LED is not set -+# CONFIG_USB_CYPRESS_CY7C63 is not set -+# CONFIG_USB_CYTHERM is not set -+# CONFIG_USB_PHIDGET is not set -+# CONFIG_USB_IDMOUSE is not set -+# CONFIG_USB_FTDI_ELAN is not set -+# CONFIG_USB_APPLEDISPLAY is not set -+# CONFIG_USB_SISUSBVGA is not set -+# CONFIG_USB_LD is not set -+# CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set -+# CONFIG_USB_TEST is not set -+# CONFIG_USB_ISIGHTFW is not set -+# CONFIG_USB_GADGET is not set -+# CONFIG_MMC is not set -+CONFIG_NEW_LEDS=y -+# CONFIG_LEDS_CLASS is not set -+ -+# -+# LED drivers -+# -+ -+# -+# LED Triggers -+# -+# CONFIG_LEDS_TRIGGERS is not set -+CONFIG_RTC_LIB=y -+CONFIG_RTC_CLASS=y -+# CONFIG_RTC_DEBUG is not set -+ -+# -+# RTC interfaces -+# -+CONFIG_RTC_INTF_SYSFS=y -+CONFIG_RTC_INTF_PROC=y -+CONFIG_RTC_INTF_DEV=y -+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -+# CONFIG_RTC_DRV_TEST is not set -+ -+# -+# I2C RTC drivers -+# -+# CONFIG_RTC_DRV_DS1307 is not set -+# CONFIG_RTC_DRV_DS1374 is not set -+# CONFIG_RTC_DRV_DS1672 is not set -+# CONFIG_RTC_DRV_MAX6900 is not set -+CONFIG_RTC_DRV_MV=y -+# CONFIG_RTC_DRV_RS5C372 is not set -+# CONFIG_RTC_DRV_ISL1208 is not set -+# CONFIG_RTC_DRV_X1205 is not set -+# CONFIG_RTC_DRV_PCF8563 is not set -+# CONFIG_RTC_DRV_PCF8583 is not set -+# CONFIG_RTC_DRV_M41T80 is not set -+# CONFIG_RTC_DRV_S35390A is not set -+ -+# -+# SPI RTC drivers -+# -+# CONFIG_RTC_DRV_MAX6902 is not set -+# CONFIG_RTC_DRV_R9701 is not set -+# CONFIG_RTC_DRV_RS5C348 is not set -+ -+# -+# Platform RTC drivers -+# -+# CONFIG_RTC_DRV_CMOS is not set -+# CONFIG_RTC_DRV_DS1511 is not set -+# CONFIG_RTC_DRV_DS1553 is not set -+# CONFIG_RTC_DRV_DS1742 is not set -+# CONFIG_RTC_DRV_STK17TA8 is not set -+# CONFIG_RTC_DRV_M48T86 is not set -+# CONFIG_RTC_DRV_M48T59 is not set -+# CONFIG_RTC_DRV_V3020 is not set -+ -+# -+# on-CPU RTC drivers -+# -+CONFIG_DMADEVICES=y -+ -+# -+# DMA Devices -+# -+CONFIG_MV_XOR=y -+CONFIG_DMA_ENGINE=y -+ -+# -+# DMA Clients -+# -+# CONFIG_NET_DMA is not set -+# CONFIG_UIO is not set -+ -+# -+# File systems -+# -+CONFIG_EXT2_FS=y -+# CONFIG_EXT2_FS_XATTR is not set -+# CONFIG_EXT2_FS_XIP is not set -+CONFIG_EXT3_FS=y -+# CONFIG_EXT3_FS_XATTR is not set -+# CONFIG_EXT4DEV_FS is not set -+CONFIG_JBD=y -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+# CONFIG_FS_POSIX_ACL is not set -+CONFIG_XFS_FS=y -+# CONFIG_XFS_QUOTA is not set -+# CONFIG_XFS_POSIX_ACL is not set -+# CONFIG_XFS_RT is not set -+# CONFIG_XFS_DEBUG is not set -+# CONFIG_OCFS2_FS is not set -+CONFIG_DNOTIFY=y -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+# CONFIG_QUOTA is not set -+# CONFIG_AUTOFS_FS is not set -+# CONFIG_AUTOFS4_FS is not set -+# CONFIG_FUSE_FS is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+CONFIG_ISO9660_FS=y -+CONFIG_JOLIET=y -+# CONFIG_ZISOFS is not set -+CONFIG_UDF_FS=m -+CONFIG_UDF_NLS=y -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+# CONFIG_NTFS_FS is not set -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_SYSCTL=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+# CONFIG_TMPFS_POSIX_ACL is not set -+# CONFIG_HUGETLB_PAGE is not set -+# CONFIG_CONFIGFS_FS is not set -+ -+# -+# Miscellaneous filesystems -+# -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -+# CONFIG_JFFS2_SUMMARY is not set -+# CONFIG_JFFS2_FS_XATTR is not set -+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_ZLIB=y -+# CONFIG_JFFS2_LZO is not set -+CONFIG_JFFS2_RTIME=y -+# CONFIG_JFFS2_RUBIN is not set -+CONFIG_CRAMFS=y -+# CONFIG_VXFS_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_ROMFS_FS is not set -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+CONFIG_NETWORK_FILESYSTEMS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3=y -+# CONFIG_NFS_V3_ACL is not set -+# CONFIG_NFS_V4 is not set -+# CONFIG_NFSD is not set -+CONFIG_ROOT_NFS=y -+CONFIG_LOCKD=y -+CONFIG_LOCKD_V4=y -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=y -+# CONFIG_SUNRPC_BIND34 is not set -+# CONFIG_RPCSEC_GSS_KRB5 is not set -+# CONFIG_RPCSEC_GSS_SPKM3 is not set -+# CONFIG_SMB_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_NCP_FS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+# CONFIG_MAC_PARTITION is not set -+CONFIG_MSDOS_PARTITION=y -+# CONFIG_BSD_DISKLABEL is not set -+# CONFIG_MINIX_SUBPARTITION is not set -+# CONFIG_SOLARIS_X86_PARTITION is not set -+# CONFIG_UNIXWARE_DISKLABEL is not set -+# CONFIG_LDM_PARTITION is not set -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_SUN_PARTITION is not set -+# CONFIG_KARMA_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_SYSV68_PARTITION is not set -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="iso8859-1" -+CONFIG_NLS_CODEPAGE_437=y -+# CONFIG_NLS_CODEPAGE_737 is not set -+# CONFIG_NLS_CODEPAGE_775 is not set -+CONFIG_NLS_CODEPAGE_850=y -+# CONFIG_NLS_CODEPAGE_852 is not set -+# CONFIG_NLS_CODEPAGE_855 is not set -+# CONFIG_NLS_CODEPAGE_857 is not set -+# CONFIG_NLS_CODEPAGE_860 is not set -+# CONFIG_NLS_CODEPAGE_861 is not set -+# CONFIG_NLS_CODEPAGE_862 is not set -+# CONFIG_NLS_CODEPAGE_863 is not set -+# CONFIG_NLS_CODEPAGE_864 is not set -+# CONFIG_NLS_CODEPAGE_865 is not set -+# CONFIG_NLS_CODEPAGE_866 is not set -+# CONFIG_NLS_CODEPAGE_869 is not set -+# CONFIG_NLS_CODEPAGE_936 is not set -+# CONFIG_NLS_CODEPAGE_950 is not set -+# CONFIG_NLS_CODEPAGE_932 is not set -+# CONFIG_NLS_CODEPAGE_949 is not set -+# CONFIG_NLS_CODEPAGE_874 is not set -+# CONFIG_NLS_ISO8859_8 is not set -+# CONFIG_NLS_CODEPAGE_1250 is not set -+# CONFIG_NLS_CODEPAGE_1251 is not set -+# CONFIG_NLS_ASCII is not set -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_2=y -+# CONFIG_NLS_ISO8859_3 is not set -+# CONFIG_NLS_ISO8859_4 is not set -+# CONFIG_NLS_ISO8859_5 is not set -+# CONFIG_NLS_ISO8859_6 is not set -+# CONFIG_NLS_ISO8859_7 is not set -+# CONFIG_NLS_ISO8859_9 is not set -+# CONFIG_NLS_ISO8859_13 is not set -+# CONFIG_NLS_ISO8859_14 is not set -+# CONFIG_NLS_ISO8859_15 is not set -+# CONFIG_NLS_KOI8_R is not set -+# CONFIG_NLS_KOI8_U is not set -+CONFIG_NLS_UTF8=y -+# CONFIG_DLM is not set -+ -+# -+# Kernel hacking -+# -+# CONFIG_PRINTK_TIME is not set -+CONFIG_ENABLE_WARN_DEPRECATED=y -+CONFIG_ENABLE_MUST_CHECK=y -+CONFIG_FRAME_WARN=1024 -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_DEBUG_FS is not set -+# CONFIG_HEADERS_CHECK is not set -+CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set -+CONFIG_DETECT_SOFTLOCKUP=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_SCHEDSTATS is not set -+# CONFIG_TIMER_STATS is not set -+# CONFIG_DEBUG_OBJECTS is not set -+# CONFIG_DEBUG_SLAB is not set -+# CONFIG_DEBUG_PREEMPT is not set -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+# CONFIG_DEBUG_SPINLOCK is not set -+# CONFIG_DEBUG_MUTEXES is not set -+# CONFIG_DEBUG_LOCK_ALLOC is not set -+# CONFIG_PROVE_LOCKING is not set -+# CONFIG_LOCK_STAT is not set -+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_DEBUG_KOBJECT is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+CONFIG_DEBUG_INFO=y -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_WRITECOUNT is not set -+# CONFIG_DEBUG_LIST is not set -+# CONFIG_DEBUG_SG is not set -+CONFIG_FRAME_POINTER=y -+# CONFIG_BOOT_PRINTK_DELAY is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_KPROBES_SANITY_TEST is not set -+# CONFIG_BACKTRACE_SELF_TEST is not set -+# CONFIG_LKDTM is not set -+# CONFIG_FAULT_INJECTION is not set -+# CONFIG_LATENCYTOP is not set -+# CONFIG_SAMPLES is not set -+CONFIG_DEBUG_USER=y -+CONFIG_DEBUG_ERRORS=y -+# CONFIG_DEBUG_STACK_USAGE is not set -+CONFIG_DEBUG_LL=y -+# CONFIG_DEBUG_ICEDCC is not set -+ -+# -+# Security options -+# -+# CONFIG_KEYS is not set -+# CONFIG_SECURITY is not set -+# CONFIG_SECURITY_FILE_CAPABILITIES is not set -+CONFIG_ASYNC_CORE=y -+CONFIG_CRYPTO=y -+ -+# -+# Crypto core or helper -+# -+CONFIG_CRYPTO_ALGAPI=m -+CONFIG_CRYPTO_BLKCIPHER=m -+CONFIG_CRYPTO_MANAGER=m -+# CONFIG_CRYPTO_GF128MUL is not set -+# CONFIG_CRYPTO_NULL is not set -+# CONFIG_CRYPTO_CRYPTD is not set -+# CONFIG_CRYPTO_AUTHENC is not set -+# CONFIG_CRYPTO_TEST is not set -+ -+# -+# Authenticated Encryption with Associated Data -+# -+# CONFIG_CRYPTO_CCM is not set -+# CONFIG_CRYPTO_GCM is not set -+# CONFIG_CRYPTO_SEQIV is not set -+ -+# -+# Block modes -+# -+CONFIG_CRYPTO_CBC=m -+# CONFIG_CRYPTO_CTR is not set -+# CONFIG_CRYPTO_CTS is not set -+CONFIG_CRYPTO_ECB=m -+# CONFIG_CRYPTO_LRW is not set -+CONFIG_CRYPTO_PCBC=m -+# CONFIG_CRYPTO_XTS is not set -+ -+# -+# Hash modes -+# -+# CONFIG_CRYPTO_HMAC is not set -+# CONFIG_CRYPTO_XCBC is not set -+ -+# -+# Digest -+# -+# CONFIG_CRYPTO_CRC32C is not set -+# CONFIG_CRYPTO_MD4 is not set -+# CONFIG_CRYPTO_MD5 is not set -+# CONFIG_CRYPTO_MICHAEL_MIC is not set -+# CONFIG_CRYPTO_SHA1 is not set -+# CONFIG_CRYPTO_SHA256 is not set -+# CONFIG_CRYPTO_SHA512 is not set -+# CONFIG_CRYPTO_TGR192 is not set -+# CONFIG_CRYPTO_WP512 is not set -+ -+# -+# Ciphers -+# -+# CONFIG_CRYPTO_AES is not set -+# CONFIG_CRYPTO_ANUBIS is not set -+# CONFIG_CRYPTO_ARC4 is not set -+# CONFIG_CRYPTO_BLOWFISH is not set -+# CONFIG_CRYPTO_CAMELLIA is not set -+# CONFIG_CRYPTO_CAST5 is not set -+# CONFIG_CRYPTO_CAST6 is not set -+# CONFIG_CRYPTO_DES is not set -+# CONFIG_CRYPTO_FCRYPT is not set -+# CONFIG_CRYPTO_KHAZAD is not set -+# CONFIG_CRYPTO_SALSA20 is not set -+# CONFIG_CRYPTO_SEED is not set -+# CONFIG_CRYPTO_SERPENT is not set -+# CONFIG_CRYPTO_TEA is not set -+# CONFIG_CRYPTO_TWOFISH is not set -+ -+# -+# Compression -+# -+# CONFIG_CRYPTO_DEFLATE is not set -+# CONFIG_CRYPTO_LZO is not set -+CONFIG_CRYPTO_HW=y -+# CONFIG_CRYPTO_DEV_HIFN_795X is not set -+ -+# -+# Library routines -+# -+CONFIG_BITREVERSE=y -+# CONFIG_GENERIC_FIND_FIRST_BIT is not set -+# CONFIG_GENERIC_FIND_NEXT_BIT is not set -+CONFIG_CRC_CCITT=y -+CONFIG_CRC16=y -+CONFIG_CRC_ITU_T=m -+CONFIG_CRC32=y -+# CONFIG_CRC7 is not set -+CONFIG_LIBCRC32C=y -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_PLIST=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -+CONFIG_HAS_DMA=y ---- /dev/null -+++ b/arch/arm/configs/loki_defconfig -@@ -0,0 +1,1147 @@ -+# -+# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.26-rc5 -+# Fri Jun 13 03:07:49 2008 -+# -+CONFIG_ARM=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+# CONFIG_GENERIC_GPIO is not set -+CONFIG_GENERIC_TIME=y -+CONFIG_GENERIC_CLOCKEVENTS=y -+CONFIG_MMU=y -+# CONFIG_NO_IOPORT is not set -+CONFIG_GENERIC_HARDIRQS=y -+CONFIG_STACKTRACE_SUPPORT=y -+CONFIG_HAVE_LATENCYTOP_SUPPORT=y -+CONFIG_LOCKDEP_SUPPORT=y -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_HARDIRQS_SW_RESEND=y -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_RWSEM_GENERIC_SPINLOCK=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ARCH_SUPPORTS_AOUT=y -+CONFIG_ZONE_DMA=y -+CONFIG_VECTORS_BASE=0xffff0000 -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+ -+# -+# General setup -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_BROKEN_ON_SMP=y -+CONFIG_LOCK_KERNEL=y -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+CONFIG_LOCALVERSION="" -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+CONFIG_SYSVIPC_SYSCTL=y -+# CONFIG_POSIX_MQUEUE is not set -+# CONFIG_BSD_PROCESS_ACCT is not set -+# CONFIG_TASKSTATS is not set -+# CONFIG_AUDIT is not set -+# CONFIG_IKCONFIG is not set -+CONFIG_LOG_BUF_SHIFT=14 -+# CONFIG_CGROUPS is not set -+# CONFIG_GROUP_SCHED is not set -+# CONFIG_SYSFS_DEPRECATED_V2 is not set -+# CONFIG_RELAY is not set -+# CONFIG_NAMESPACES is not set -+# CONFIG_BLK_DEV_INITRD is not set -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_SYSCTL=y -+CONFIG_EMBEDDED=y -+CONFIG_UID16=y -+CONFIG_SYSCTL_SYSCALL=y -+CONFIG_SYSCTL_SYSCALL_CHECK=y -+CONFIG_KALLSYMS=y -+# CONFIG_KALLSYMS_EXTRA_PASS is not set -+CONFIG_HOTPLUG=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+CONFIG_COMPAT_BRK=y -+CONFIG_BASE_FULL=y -+CONFIG_FUTEX=y -+CONFIG_ANON_INODES=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_TIMERFD=y -+CONFIG_EVENTFD=y -+CONFIG_SHMEM=y -+CONFIG_VM_EVENT_COUNTERS=y -+CONFIG_SLAB=y -+# CONFIG_SLUB is not set -+# CONFIG_SLOB is not set -+# CONFIG_PROFILING is not set -+# CONFIG_MARKERS is not set -+CONFIG_HAVE_OPROFILE=y -+# CONFIG_KPROBES is not set -+CONFIG_HAVE_KPROBES=y -+CONFIG_HAVE_KRETPROBES=y -+# CONFIG_HAVE_DMA_ATTRS is not set -+CONFIG_PROC_PAGE_MONITOR=y -+CONFIG_SLABINFO=y -+CONFIG_RT_MUTEXES=y -+# CONFIG_TINY_SHMEM is not set -+CONFIG_BASE_SMALL=0 -+CONFIG_MODULES=y -+# CONFIG_MODULE_FORCE_LOAD is not set -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_MODULE_FORCE_UNLOAD is not set -+# CONFIG_MODVERSIONS is not set -+# CONFIG_MODULE_SRCVERSION_ALL is not set -+# CONFIG_KMOD is not set -+CONFIG_BLOCK=y -+# CONFIG_LBD is not set -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set -+# CONFIG_BLK_DEV_BSG is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_AS=y -+CONFIG_IOSCHED_DEADLINE=y -+CONFIG_IOSCHED_CFQ=y -+# CONFIG_DEFAULT_AS is not set -+# CONFIG_DEFAULT_DEADLINE is not set -+CONFIG_DEFAULT_CFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="cfq" -+CONFIG_CLASSIC_RCU=y -+ -+# -+# System Type -+# -+# CONFIG_ARCH_AAEC2000 is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_REALVIEW is not set -+# CONFIG_ARCH_VERSATILE is not set -+# CONFIG_ARCH_AT91 is not set -+# CONFIG_ARCH_CLPS7500 is not set -+# CONFIG_ARCH_CLPS711X is not set -+# CONFIG_ARCH_CO285 is not set -+# CONFIG_ARCH_EBSA110 is not set -+# CONFIG_ARCH_EP93XX is not set -+# CONFIG_ARCH_FOOTBRIDGE is not set -+# CONFIG_ARCH_NETX is not set -+# CONFIG_ARCH_H720X is not set -+# CONFIG_ARCH_IMX is not set -+# CONFIG_ARCH_IOP13XX is not set -+# CONFIG_ARCH_IOP32X is not set -+# CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IXP23XX is not set -+# CONFIG_ARCH_IXP2000 is not set -+# CONFIG_ARCH_IXP4XX is not set -+# CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_KIRKWOOD is not set -+# CONFIG_ARCH_KS8695 is not set -+# CONFIG_ARCH_NS9XXX is not set -+CONFIG_ARCH_LOKI=y -+# CONFIG_ARCH_MV78XX0 is not set -+# CONFIG_ARCH_MXC is not set -+# CONFIG_ARCH_ORION5X is not set -+# CONFIG_ARCH_PNX4008 is not set -+# CONFIG_ARCH_PXA is not set -+# CONFIG_ARCH_RPC is not set -+# CONFIG_ARCH_SA1100 is not set -+# CONFIG_ARCH_S3C2410 is not set -+# CONFIG_ARCH_SHARK is not set -+# CONFIG_ARCH_LH7A40X is not set -+# CONFIG_ARCH_DAVINCI is not set -+# CONFIG_ARCH_OMAP is not set -+# CONFIG_ARCH_MSM7X00A is not set -+ -+# -+# Marvell Loki (88RC8480) Implementations -+# -+CONFIG_MACH_LB88RC8480=y -+ -+# -+# Boot options -+# -+ -+# -+# Power management -+# -+CONFIG_PLAT_ORION=y -+ -+# -+# Processor Type -+# -+CONFIG_CPU_32=y -+CONFIG_CPU_FEROCEON=y -+# CONFIG_CPU_FEROCEON_OLD_ID is not set -+CONFIG_CPU_32v5=y -+CONFIG_CPU_ABRT_EV5T=y -+CONFIG_CPU_PABRT_NOIFAR=y -+CONFIG_CPU_CACHE_VIVT=y -+CONFIG_CPU_COPY_FEROCEON=y -+CONFIG_CPU_TLB_FEROCEON=y -+CONFIG_CPU_CP15=y -+CONFIG_CPU_CP15_MMU=y -+ -+# -+# Processor Features -+# -+CONFIG_ARM_THUMB=y -+# CONFIG_CPU_ICACHE_DISABLE is not set -+# CONFIG_CPU_DCACHE_DISABLE is not set -+# CONFIG_OUTER_CACHE is not set -+ -+# -+# Bus support -+# -+# CONFIG_PCI_SYSCALL is not set -+# CONFIG_ARCH_SUPPORTS_MSI is not set -+# CONFIG_PCCARD is not set -+ -+# -+# Kernel Features -+# -+CONFIG_TICK_ONESHOT=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -+CONFIG_PREEMPT=y -+CONFIG_HZ=100 -+CONFIG_AEABI=y -+CONFIG_OABI_COMPAT=y -+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+# CONFIG_SPARSEMEM_STATIC is not set -+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -+CONFIG_PAGEFLAGS_EXTENDED=y -+CONFIG_SPLIT_PTLOCK_CPUS=4096 -+# CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 -+CONFIG_BOUNCE=y -+CONFIG_VIRT_TO_BUS=y -+CONFIG_ALIGNMENT_TRAP=y -+ -+# -+# Boot options -+# -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CMDLINE="" -+# CONFIG_XIP_KERNEL is not set -+# CONFIG_KEXEC is not set -+ -+# -+# Floating point emulation -+# -+ -+# -+# At least one emulation must be selected -+# -+# CONFIG_FPE_NWFPE is not set -+# CONFIG_FPE_FASTFPE is not set -+# CONFIG_VFP is not set -+ -+# -+# Userspace binary formats -+# -+CONFIG_BINFMT_ELF=y -+# CONFIG_BINFMT_AOUT is not set -+# CONFIG_BINFMT_MISC is not set -+ -+# -+# Power management options -+# -+# CONFIG_PM is not set -+CONFIG_ARCH_SUSPEND_POSSIBLE=y -+ -+# -+# Networking -+# -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+CONFIG_PACKET_MMAP=y -+CONFIG_UNIX=y -+CONFIG_XFRM=y -+# CONFIG_XFRM_USER is not set -+# CONFIG_XFRM_SUB_POLICY is not set -+# CONFIG_XFRM_MIGRATE is not set -+# CONFIG_XFRM_STATISTICS is not set -+# CONFIG_NET_KEY is not set -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+# CONFIG_IP_ADVANCED_ROUTER is not set -+CONFIG_IP_FIB_HASH=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+# CONFIG_IP_PNP_RARP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_IP_MROUTE is not set -+# CONFIG_ARPD is not set -+# CONFIG_SYN_COOKIES is not set -+# CONFIG_INET_AH is not set -+# CONFIG_INET_ESP is not set -+# CONFIG_INET_IPCOMP is not set -+# CONFIG_INET_XFRM_TUNNEL is not set -+# CONFIG_INET_TUNNEL is not set -+CONFIG_INET_XFRM_MODE_TRANSPORT=y -+CONFIG_INET_XFRM_MODE_TUNNEL=y -+CONFIG_INET_XFRM_MODE_BEET=y -+# CONFIG_INET_LRO is not set -+CONFIG_INET_DIAG=y -+CONFIG_INET_TCP_DIAG=y -+# CONFIG_TCP_CONG_ADVANCED is not set -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set -+# CONFIG_IPV6 is not set -+# CONFIG_NETWORK_SECMARK is not set -+# CONFIG_NETFILTER is not set -+# CONFIG_IP_DCCP is not set -+# CONFIG_IP_SCTP is not set -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+# CONFIG_NET_SCHED is not set -+ -+# -+# Network testing -+# -+CONFIG_NET_PKTGEN=m -+# CONFIG_HAMRADIO is not set -+# CONFIG_CAN is not set -+# CONFIG_IRDA is not set -+# CONFIG_BT is not set -+# CONFIG_AF_RXRPC is not set -+ -+# -+# Wireless -+# -+# CONFIG_CFG80211 is not set -+CONFIG_WIRELESS_EXT=y -+# CONFIG_MAC80211 is not set -+# CONFIG_IEEE80211 is not set -+# CONFIG_RFKILL is not set -+# CONFIG_NET_9P is not set -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+CONFIG_FW_LOADER=y -+# CONFIG_SYS_HYPERVISOR is not set -+# CONFIG_CONNECTOR is not set -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+# CONFIG_MTD_CONCAT is not set -+CONFIG_MTD_PARTITIONS=y -+# CONFIG_MTD_REDBOOT_PARTS is not set -+CONFIG_MTD_CMDLINE_PARTS=y -+# CONFIG_MTD_AFS_PARTS is not set -+# CONFIG_MTD_AR7_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLKDEVS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_FTL=y -+CONFIG_NFTL=y -+# CONFIG_NFTL_RW is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+# CONFIG_MTD_OOPS is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+CONFIG_MTD_CFI=y -+CONFIG_MTD_JEDECPROBE=y -+CONFIG_MTD_GEN_PROBE=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_NOSWAP=y -+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -+CONFIG_MTD_CFI_GEOMETRY=y -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+CONFIG_MTD_CFI_I4=y -+# CONFIG_MTD_CFI_I8 is not set -+# CONFIG_MTD_OTP is not set -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_CFI_UTIL=y -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+ -+# -+# Mapping drivers for chip access -+# -+# CONFIG_MTD_COMPLEX_MAPPINGS is not set -+CONFIG_MTD_PHYSMAP=y -+CONFIG_MTD_PHYSMAP_START=0x0 -+CONFIG_MTD_PHYSMAP_LEN=0x0 -+CONFIG_MTD_PHYSMAP_BANKWIDTH=0 -+# CONFIG_MTD_ARM_INTEGRATOR is not set -+# CONFIG_MTD_IMPA7 is not set -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_DATAFLASH is not set -+CONFIG_MTD_M25P80=y -+CONFIG_M25PXX_USE_FAST_READ=y -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+CONFIG_MTD_NAND=y -+CONFIG_MTD_NAND_VERIFY_WRITE=y -+# CONFIG_MTD_NAND_ECC_SMC is not set -+# CONFIG_MTD_NAND_MUSEUM_IDS is not set -+CONFIG_MTD_NAND_IDS=y -+# CONFIG_MTD_NAND_DISKONCHIP is not set -+# CONFIG_MTD_NAND_NANDSIM is not set -+# CONFIG_MTD_NAND_PLATFORM is not set -+# CONFIG_MTD_ALAUDA is not set -+CONFIG_MTD_NAND_ORION=y -+# CONFIG_MTD_ONENAND is not set -+ -+# -+# UBI - Unsorted block images -+# -+# CONFIG_MTD_UBI is not set -+# CONFIG_PARPORT is not set -+CONFIG_BLK_DEV=y -+# CONFIG_BLK_DEV_COW_COMMON is not set -+CONFIG_BLK_DEV_LOOP=y -+# CONFIG_BLK_DEV_CRYPTOLOOP is not set -+# CONFIG_BLK_DEV_NBD is not set -+# CONFIG_BLK_DEV_UB is not set -+# CONFIG_BLK_DEV_RAM is not set -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+# CONFIG_MISC_DEVICES is not set -+CONFIG_HAVE_IDE=y -+# CONFIG_IDE is not set -+ -+# -+# SCSI device support -+# -+# CONFIG_RAID_ATTRS is not set -+CONFIG_SCSI=y -+CONFIG_SCSI_DMA=y -+# CONFIG_SCSI_TGT is not set -+# CONFIG_SCSI_NETLINK is not set -+# CONFIG_SCSI_PROC_FS is not set -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+# CONFIG_CHR_DEV_OSST is not set -+CONFIG_BLK_DEV_SR=m -+# CONFIG_BLK_DEV_SR_VENDOR is not set -+CONFIG_CHR_DEV_SG=m -+# CONFIG_CHR_DEV_SCH is not set -+ -+# -+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -+# -+# CONFIG_SCSI_MULTI_LUN is not set -+# CONFIG_SCSI_CONSTANTS is not set -+# CONFIG_SCSI_LOGGING is not set -+# CONFIG_SCSI_SCAN_ASYNC is not set -+CONFIG_SCSI_WAIT_SCAN=m -+ -+# -+# SCSI Transports -+# -+# CONFIG_SCSI_SPI_ATTRS is not set -+# CONFIG_SCSI_FC_ATTRS is not set -+# CONFIG_SCSI_ISCSI_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+# CONFIG_SCSI_SRP_ATTRS is not set -+CONFIG_SCSI_LOWLEVEL=y -+# CONFIG_ISCSI_TCP is not set -+# CONFIG_SCSI_DEBUG is not set -+CONFIG_ATA=y -+# CONFIG_ATA_NONSTANDARD is not set -+CONFIG_SATA_PMP=y -+CONFIG_ATA_SFF=y -+CONFIG_SATA_MV=y -+# CONFIG_PATA_PLATFORM is not set -+# CONFIG_MD is not set -+CONFIG_NETDEVICES=y -+# CONFIG_NETDEVICES_MULTIQUEUE is not set -+# CONFIG_DUMMY is not set -+# CONFIG_BONDING is not set -+# CONFIG_MACVLAN is not set -+# CONFIG_EQUALIZER is not set -+# CONFIG_TUN is not set -+# CONFIG_VETH is not set -+# CONFIG_PHYLIB is not set -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=y -+# CONFIG_AX88796 is not set -+# CONFIG_SMC91X is not set -+# CONFIG_DM9000 is not set -+# CONFIG_ENC28J60 is not set -+# CONFIG_IBM_NEW_EMAC_ZMII is not set -+# CONFIG_IBM_NEW_EMAC_RGMII is not set -+# CONFIG_IBM_NEW_EMAC_TAH is not set -+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -+# CONFIG_B44 is not set -+CONFIG_NETDEV_1000=y -+# CONFIG_E1000E_ENABLED is not set -+CONFIG_MV643XX_ETH=y -+# CONFIG_NETDEV_10000 is not set -+ -+# -+# Wireless LAN -+# -+# CONFIG_WLAN_PRE80211 is not set -+# CONFIG_WLAN_80211 is not set -+# CONFIG_IWLWIFI_LEDS is not set -+ -+# -+# USB Network Adapters -+# -+# CONFIG_USB_CATC is not set -+# CONFIG_USB_KAWETH is not set -+# CONFIG_USB_PEGASUS is not set -+# CONFIG_USB_RTL8150 is not set -+# CONFIG_USB_USBNET is not set -+# CONFIG_WAN is not set -+# CONFIG_PPP is not set -+# CONFIG_SLIP is not set -+# CONFIG_NETCONSOLE is not set -+# CONFIG_NETPOLL is not set -+# CONFIG_NET_POLL_CONTROLLER is not set -+# CONFIG_ISDN is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+# CONFIG_INPUT_FF_MEMLESS is not set -+# CONFIG_INPUT_POLLDEV is not set -+ -+# -+# Userland interfaces -+# -+CONFIG_INPUT_MOUSEDEV=y -+CONFIG_INPUT_MOUSEDEV_PSAUX=y -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+# CONFIG_INPUT_JOYDEV is not set -+# CONFIG_INPUT_EVDEV is not set -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+# CONFIG_INPUT_KEYBOARD is not set -+# CONFIG_INPUT_MOUSE is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TABLET is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+# CONFIG_INPUT_MISC is not set -+ -+# -+# Hardware I/O ports -+# -+# CONFIG_SERIO is not set -+# CONFIG_GAMEPORT is not set -+ -+# -+# Character devices -+# -+CONFIG_VT=y -+CONFIG_VT_CONSOLE=y -+CONFIG_HW_CONSOLE=y -+# CONFIG_VT_HW_CONSOLE_BINDING is not set -+CONFIG_DEVKMEM=y -+# CONFIG_SERIAL_NONSTANDARD is not set -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_NR_UARTS=4 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -+# CONFIG_SERIAL_8250_EXTENDED is not set -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+CONFIG_UNIX98_PTYS=y -+CONFIG_LEGACY_PTYS=y -+CONFIG_LEGACY_PTY_COUNT=16 -+# CONFIG_IPMI_HANDLER is not set -+CONFIG_HW_RANDOM=m -+# CONFIG_NVRAM is not set -+# CONFIG_R3964 is not set -+# CONFIG_RAW_DRIVER is not set -+# CONFIG_TCG_TPM is not set -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_CHARDEV=y -+ -+# -+# I2C Hardware Bus support -+# -+# CONFIG_I2C_OCORES is not set -+# CONFIG_I2C_PARPORT_LIGHT is not set -+# CONFIG_I2C_SIMTEC is not set -+# CONFIG_I2C_TAOS_EVM is not set -+# CONFIG_I2C_STUB is not set -+# CONFIG_I2C_TINY_USB is not set -+# CONFIG_I2C_PCA_PLATFORM is not set -+CONFIG_I2C_MV64XXX=y -+ -+# -+# Miscellaneous I2C Chip support -+# -+# CONFIG_DS1682 is not set -+# CONFIG_SENSORS_EEPROM is not set -+# CONFIG_SENSORS_PCF8574 is not set -+# CONFIG_PCF8575 is not set -+# CONFIG_SENSORS_PCF8591 is not set -+# CONFIG_SENSORS_MAX6875 is not set -+# CONFIG_SENSORS_TSL2550 is not set -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_ALGO is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+# CONFIG_I2C_DEBUG_CHIP is not set -+CONFIG_SPI=y -+CONFIG_SPI_MASTER=y -+ -+# -+# SPI Master Controller Drivers -+# -+# CONFIG_SPI_BITBANG is not set -+ -+# -+# SPI Protocol Masters -+# -+# CONFIG_SPI_AT25 is not set -+# CONFIG_SPI_SPIDEV is not set -+# CONFIG_SPI_TLE62X0 is not set -+# CONFIG_W1 is not set -+# CONFIG_POWER_SUPPLY is not set -+# CONFIG_HWMON is not set -+# CONFIG_WATCHDOG is not set -+ -+# -+# Sonics Silicon Backplane -+# -+CONFIG_SSB_POSSIBLE=y -+# CONFIG_SSB is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set -+# CONFIG_MFD_ASIC3 is not set -+# CONFIG_HTC_PASIC3 is not set -+ -+# -+# Multimedia devices -+# -+ -+# -+# Multimedia core support -+# -+# CONFIG_VIDEO_DEV is not set -+# CONFIG_DVB_CORE is not set -+# CONFIG_VIDEO_MEDIA is not set -+ -+# -+# Multimedia drivers -+# -+# CONFIG_DAB is not set -+ -+# -+# Graphics support -+# -+# CONFIG_VGASTATE is not set -+# CONFIG_VIDEO_OUTPUT_CONTROL is not set -+# CONFIG_FB is not set -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -+ -+# -+# Display device support -+# -+# CONFIG_DISPLAY_SUPPORT is not set -+ -+# -+# Console display driver support -+# -+# CONFIG_VGA_CONSOLE is not set -+CONFIG_DUMMY_CONSOLE=y -+ -+# -+# Sound -+# -+# CONFIG_SOUND is not set -+CONFIG_HID_SUPPORT=y -+CONFIG_HID=y -+# CONFIG_HID_DEBUG is not set -+# CONFIG_HIDRAW is not set -+ -+# -+# USB Input Devices -+# -+CONFIG_USB_HID=y -+# CONFIG_USB_HIDINPUT_POWERBOOK is not set -+# CONFIG_HID_FF is not set -+# CONFIG_USB_HIDDEV is not set -+CONFIG_USB_SUPPORT=y -+CONFIG_USB_ARCH_HAS_HCD=y -+# CONFIG_USB_ARCH_HAS_OHCI is not set -+# CONFIG_USB_ARCH_HAS_EHCI is not set -+CONFIG_USB=y -+# CONFIG_USB_DEBUG is not set -+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set -+ -+# -+# Miscellaneous USB options -+# -+CONFIG_USB_DEVICEFS=y -+CONFIG_USB_DEVICE_CLASS=y -+# CONFIG_USB_DYNAMIC_MINORS is not set -+# CONFIG_USB_OTG is not set -+# CONFIG_USB_OTG_WHITELIST is not set -+# CONFIG_USB_OTG_BLACKLIST_HUB is not set -+ -+# -+# USB Host Controller Drivers -+# -+# CONFIG_USB_C67X00_HCD is not set -+# CONFIG_USB_ISP116X_HCD is not set -+# CONFIG_USB_ISP1760_HCD is not set -+# CONFIG_USB_SL811_HCD is not set -+# CONFIG_USB_R8A66597_HCD is not set -+ -+# -+# USB Device Class drivers -+# -+# CONFIG_USB_ACM is not set -+CONFIG_USB_PRINTER=y -+# CONFIG_USB_WDM is not set -+ -+# -+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -+# -+ -+# -+# may also be needed; see USB_STORAGE Help for more information -+# -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+CONFIG_USB_STORAGE_DATAFAB=y -+CONFIG_USB_STORAGE_FREECOM=y -+# CONFIG_USB_STORAGE_ISD200 is not set -+CONFIG_USB_STORAGE_DPCM=y -+# CONFIG_USB_STORAGE_USBAT is not set -+CONFIG_USB_STORAGE_SDDR09=y -+CONFIG_USB_STORAGE_SDDR55=y -+CONFIG_USB_STORAGE_JUMPSHOT=y -+# CONFIG_USB_STORAGE_ALAUDA is not set -+# CONFIG_USB_STORAGE_ONETOUCH is not set -+# CONFIG_USB_STORAGE_KARMA is not set -+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -+# CONFIG_USB_LIBUSUAL is not set -+ -+# -+# USB Imaging devices -+# -+# CONFIG_USB_MDC800 is not set -+# CONFIG_USB_MICROTEK is not set -+# CONFIG_USB_MON is not set -+ -+# -+# USB port drivers -+# -+# CONFIG_USB_SERIAL is not set -+ -+# -+# USB Miscellaneous drivers -+# -+# CONFIG_USB_EMI62 is not set -+# CONFIG_USB_EMI26 is not set -+# CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_AUERSWALD is not set -+# CONFIG_USB_RIO500 is not set -+# CONFIG_USB_LEGOTOWER is not set -+# CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set -+# CONFIG_USB_LED is not set -+# CONFIG_USB_CYPRESS_CY7C63 is not set -+# CONFIG_USB_CYTHERM is not set -+# CONFIG_USB_PHIDGET is not set -+# CONFIG_USB_IDMOUSE is not set -+# CONFIG_USB_FTDI_ELAN is not set -+# CONFIG_USB_APPLEDISPLAY is not set -+# CONFIG_USB_LD is not set -+# CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set -+# CONFIG_USB_TEST is not set -+# CONFIG_USB_ISIGHTFW is not set -+# CONFIG_USB_GADGET is not set -+# CONFIG_MMC is not set -+CONFIG_NEW_LEDS=y -+# CONFIG_LEDS_CLASS is not set -+ -+# -+# LED drivers -+# -+ -+# -+# LED Triggers -+# -+# CONFIG_LEDS_TRIGGERS is not set -+CONFIG_RTC_LIB=y -+# CONFIG_RTC_CLASS is not set -+# CONFIG_UIO is not set -+ -+# -+# File systems -+# -+CONFIG_EXT2_FS=y -+# CONFIG_EXT2_FS_XATTR is not set -+# CONFIG_EXT2_FS_XIP is not set -+CONFIG_EXT3_FS=y -+# CONFIG_EXT3_FS_XATTR is not set -+# CONFIG_EXT4DEV_FS is not set -+CONFIG_JBD=y -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+# CONFIG_FS_POSIX_ACL is not set -+CONFIG_XFS_FS=y -+# CONFIG_XFS_QUOTA is not set -+# CONFIG_XFS_POSIX_ACL is not set -+# CONFIG_XFS_RT is not set -+# CONFIG_XFS_DEBUG is not set -+# CONFIG_OCFS2_FS is not set -+CONFIG_DNOTIFY=y -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+# CONFIG_QUOTA is not set -+# CONFIG_AUTOFS_FS is not set -+# CONFIG_AUTOFS4_FS is not set -+# CONFIG_FUSE_FS is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+CONFIG_ISO9660_FS=y -+# CONFIG_JOLIET is not set -+# CONFIG_ZISOFS is not set -+CONFIG_UDF_FS=m -+CONFIG_UDF_NLS=y -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+# CONFIG_NTFS_FS is not set -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_SYSCTL=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+# CONFIG_TMPFS_POSIX_ACL is not set -+# CONFIG_HUGETLB_PAGE is not set -+# CONFIG_CONFIGFS_FS is not set -+ -+# -+# Miscellaneous filesystems -+# -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -+# CONFIG_JFFS2_SUMMARY is not set -+# CONFIG_JFFS2_FS_XATTR is not set -+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_ZLIB=y -+# CONFIG_JFFS2_LZO is not set -+CONFIG_JFFS2_RTIME=y -+# CONFIG_JFFS2_RUBIN is not set -+CONFIG_CRAMFS=y -+# CONFIG_VXFS_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_ROMFS_FS is not set -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+CONFIG_NETWORK_FILESYSTEMS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3=y -+# CONFIG_NFS_V3_ACL is not set -+# CONFIG_NFS_V4 is not set -+# CONFIG_NFSD is not set -+CONFIG_ROOT_NFS=y -+CONFIG_LOCKD=y -+CONFIG_LOCKD_V4=y -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=y -+# CONFIG_SUNRPC_BIND34 is not set -+# CONFIG_RPCSEC_GSS_KRB5 is not set -+# CONFIG_RPCSEC_GSS_SPKM3 is not set -+# CONFIG_SMB_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_NCP_FS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+# CONFIG_MAC_PARTITION is not set -+CONFIG_MSDOS_PARTITION=y -+CONFIG_BSD_DISKLABEL=y -+CONFIG_MINIX_SUBPARTITION=y -+CONFIG_SOLARIS_X86_PARTITION=y -+CONFIG_UNIXWARE_DISKLABEL=y -+CONFIG_LDM_PARTITION=y -+CONFIG_LDM_DEBUG=y -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+CONFIG_SUN_PARTITION=y -+# CONFIG_KARMA_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_SYSV68_PARTITION is not set -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="iso8859-1" -+CONFIG_NLS_CODEPAGE_437=y -+# CONFIG_NLS_CODEPAGE_737 is not set -+# CONFIG_NLS_CODEPAGE_775 is not set -+CONFIG_NLS_CODEPAGE_850=y -+# CONFIG_NLS_CODEPAGE_852 is not set -+# CONFIG_NLS_CODEPAGE_855 is not set -+# CONFIG_NLS_CODEPAGE_857 is not set -+# CONFIG_NLS_CODEPAGE_860 is not set -+# CONFIG_NLS_CODEPAGE_861 is not set -+# CONFIG_NLS_CODEPAGE_862 is not set -+# CONFIG_NLS_CODEPAGE_863 is not set -+# CONFIG_NLS_CODEPAGE_864 is not set -+# CONFIG_NLS_CODEPAGE_865 is not set -+# CONFIG_NLS_CODEPAGE_866 is not set -+# CONFIG_NLS_CODEPAGE_869 is not set -+# CONFIG_NLS_CODEPAGE_936 is not set -+# CONFIG_NLS_CODEPAGE_950 is not set -+# CONFIG_NLS_CODEPAGE_932 is not set -+# CONFIG_NLS_CODEPAGE_949 is not set -+# CONFIG_NLS_CODEPAGE_874 is not set -+# CONFIG_NLS_ISO8859_8 is not set -+# CONFIG_NLS_CODEPAGE_1250 is not set -+# CONFIG_NLS_CODEPAGE_1251 is not set -+# CONFIG_NLS_ASCII is not set -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_2=y -+# CONFIG_NLS_ISO8859_3 is not set -+# CONFIG_NLS_ISO8859_4 is not set -+# CONFIG_NLS_ISO8859_5 is not set -+# CONFIG_NLS_ISO8859_6 is not set -+# CONFIG_NLS_ISO8859_7 is not set -+# CONFIG_NLS_ISO8859_9 is not set -+# CONFIG_NLS_ISO8859_13 is not set -+# CONFIG_NLS_ISO8859_14 is not set -+# CONFIG_NLS_ISO8859_15 is not set -+# CONFIG_NLS_KOI8_R is not set -+# CONFIG_NLS_KOI8_U is not set -+# CONFIG_NLS_UTF8 is not set -+# CONFIG_DLM is not set -+ -+# -+# Kernel hacking -+# -+# CONFIG_PRINTK_TIME is not set -+CONFIG_ENABLE_WARN_DEPRECATED=y -+CONFIG_ENABLE_MUST_CHECK=y -+CONFIG_FRAME_WARN=1024 -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_DEBUG_FS is not set -+# CONFIG_HEADERS_CHECK is not set -+# CONFIG_DEBUG_KERNEL is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+CONFIG_FRAME_POINTER=y -+# CONFIG_LATENCYTOP is not set -+# CONFIG_SAMPLES is not set -+CONFIG_DEBUG_USER=y -+ -+# -+# Security options -+# -+# CONFIG_KEYS is not set -+# CONFIG_SECURITY is not set -+# CONFIG_SECURITY_FILE_CAPABILITIES is not set -+CONFIG_CRYPTO=y -+ -+# -+# Crypto core or helper -+# -+CONFIG_CRYPTO_ALGAPI=m -+CONFIG_CRYPTO_BLKCIPHER=m -+CONFIG_CRYPTO_MANAGER=m -+# CONFIG_CRYPTO_GF128MUL is not set -+# CONFIG_CRYPTO_NULL is not set -+# CONFIG_CRYPTO_CRYPTD is not set -+# CONFIG_CRYPTO_AUTHENC is not set -+# CONFIG_CRYPTO_TEST is not set -+ -+# -+# Authenticated Encryption with Associated Data -+# -+# CONFIG_CRYPTO_CCM is not set -+# CONFIG_CRYPTO_GCM is not set -+# CONFIG_CRYPTO_SEQIV is not set -+ -+# -+# Block modes -+# -+CONFIG_CRYPTO_CBC=m -+# CONFIG_CRYPTO_CTR is not set -+# CONFIG_CRYPTO_CTS is not set -+CONFIG_CRYPTO_ECB=m -+# CONFIG_CRYPTO_LRW is not set -+CONFIG_CRYPTO_PCBC=m -+# CONFIG_CRYPTO_XTS is not set -+ -+# -+# Hash modes -+# -+# CONFIG_CRYPTO_HMAC is not set -+# CONFIG_CRYPTO_XCBC is not set -+ -+# -+# Digest -+# -+# CONFIG_CRYPTO_CRC32C is not set -+# CONFIG_CRYPTO_MD4 is not set -+# CONFIG_CRYPTO_MD5 is not set -+# CONFIG_CRYPTO_MICHAEL_MIC is not set -+# CONFIG_CRYPTO_SHA1 is not set -+# CONFIG_CRYPTO_SHA256 is not set -+# CONFIG_CRYPTO_SHA512 is not set -+# CONFIG_CRYPTO_TGR192 is not set -+# CONFIG_CRYPTO_WP512 is not set -+ -+# -+# Ciphers -+# -+# CONFIG_CRYPTO_AES is not set -+# CONFIG_CRYPTO_ANUBIS is not set -+# CONFIG_CRYPTO_ARC4 is not set -+# CONFIG_CRYPTO_BLOWFISH is not set -+# CONFIG_CRYPTO_CAMELLIA is not set -+# CONFIG_CRYPTO_CAST5 is not set -+# CONFIG_CRYPTO_CAST6 is not set -+# CONFIG_CRYPTO_DES is not set -+# CONFIG_CRYPTO_FCRYPT is not set -+# CONFIG_CRYPTO_KHAZAD is not set -+# CONFIG_CRYPTO_SALSA20 is not set -+# CONFIG_CRYPTO_SEED is not set -+# CONFIG_CRYPTO_SERPENT is not set -+# CONFIG_CRYPTO_TEA is not set -+# CONFIG_CRYPTO_TWOFISH is not set -+ -+# -+# Compression -+# -+# CONFIG_CRYPTO_DEFLATE is not set -+# CONFIG_CRYPTO_LZO is not set -+CONFIG_CRYPTO_HW=y -+ -+# -+# Library routines -+# -+CONFIG_BITREVERSE=y -+# CONFIG_GENERIC_FIND_FIRST_BIT is not set -+# CONFIG_GENERIC_FIND_NEXT_BIT is not set -+CONFIG_CRC_CCITT=y -+CONFIG_CRC16=y -+CONFIG_CRC_ITU_T=m -+CONFIG_CRC32=y -+# CONFIG_CRC7 is not set -+CONFIG_LIBCRC32C=y -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_PLIST=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -+CONFIG_HAS_DMA=y ---- /dev/null -+++ b/arch/arm/configs/mv78xx0_defconfig -@@ -0,0 +1,1445 @@ -+# -+# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.26-rc5 -+# Fri Jun 13 02:57:32 2008 -+# -+CONFIG_ARM=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+# CONFIG_GENERIC_GPIO is not set -+CONFIG_GENERIC_TIME=y -+CONFIG_GENERIC_CLOCKEVENTS=y -+CONFIG_MMU=y -+# CONFIG_NO_IOPORT is not set -+CONFIG_GENERIC_HARDIRQS=y -+CONFIG_STACKTRACE_SUPPORT=y -+CONFIG_HAVE_LATENCYTOP_SUPPORT=y -+CONFIG_LOCKDEP_SUPPORT=y -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_HARDIRQS_SW_RESEND=y -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_RWSEM_GENERIC_SPINLOCK=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ARCH_SUPPORTS_AOUT=y -+CONFIG_ZONE_DMA=y -+CONFIG_VECTORS_BASE=0xffff0000 -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+ -+# -+# General setup -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_BROKEN_ON_SMP=y -+CONFIG_LOCK_KERNEL=y -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+CONFIG_LOCALVERSION="" -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+CONFIG_SYSVIPC_SYSCTL=y -+# CONFIG_POSIX_MQUEUE is not set -+# CONFIG_BSD_PROCESS_ACCT is not set -+# CONFIG_TASKSTATS is not set -+# CONFIG_AUDIT is not set -+# CONFIG_IKCONFIG is not set -+CONFIG_LOG_BUF_SHIFT=14 -+# CONFIG_CGROUPS is not set -+# CONFIG_GROUP_SCHED is not set -+CONFIG_SYSFS_DEPRECATED=y -+CONFIG_SYSFS_DEPRECATED_V2=y -+# CONFIG_RELAY is not set -+# CONFIG_NAMESPACES is not set -+# CONFIG_BLK_DEV_INITRD is not set -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_SYSCTL=y -+CONFIG_EMBEDDED=y -+CONFIG_UID16=y -+CONFIG_SYSCTL_SYSCALL=y -+CONFIG_SYSCTL_SYSCALL_CHECK=y -+CONFIG_KALLSYMS=y -+CONFIG_KALLSYMS_ALL=y -+# CONFIG_KALLSYMS_EXTRA_PASS is not set -+CONFIG_HOTPLUG=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+CONFIG_COMPAT_BRK=y -+CONFIG_BASE_FULL=y -+CONFIG_FUTEX=y -+CONFIG_ANON_INODES=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_TIMERFD=y -+CONFIG_EVENTFD=y -+CONFIG_SHMEM=y -+CONFIG_VM_EVENT_COUNTERS=y -+# CONFIG_SLUB_DEBUG is not set -+# CONFIG_SLAB is not set -+CONFIG_SLUB=y -+# CONFIG_SLOB is not set -+CONFIG_PROFILING=y -+# CONFIG_MARKERS is not set -+CONFIG_OPROFILE=y -+CONFIG_HAVE_OPROFILE=y -+CONFIG_KPROBES=y -+CONFIG_KRETPROBES=y -+CONFIG_HAVE_KPROBES=y -+CONFIG_HAVE_KRETPROBES=y -+# CONFIG_HAVE_DMA_ATTRS is not set -+CONFIG_PROC_PAGE_MONITOR=y -+CONFIG_RT_MUTEXES=y -+# CONFIG_TINY_SHMEM is not set -+CONFIG_BASE_SMALL=0 -+CONFIG_MODULES=y -+# CONFIG_MODULE_FORCE_LOAD is not set -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_MODULE_FORCE_UNLOAD is not set -+# CONFIG_MODVERSIONS is not set -+# CONFIG_MODULE_SRCVERSION_ALL is not set -+# CONFIG_KMOD is not set -+CONFIG_BLOCK=y -+# CONFIG_LBD is not set -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set -+# CONFIG_BLK_DEV_BSG is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_AS=y -+CONFIG_IOSCHED_DEADLINE=y -+CONFIG_IOSCHED_CFQ=y -+# CONFIG_DEFAULT_AS is not set -+# CONFIG_DEFAULT_DEADLINE is not set -+CONFIG_DEFAULT_CFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="cfq" -+CONFIG_CLASSIC_RCU=y -+ -+# -+# System Type -+# -+# CONFIG_ARCH_AAEC2000 is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_REALVIEW is not set -+# CONFIG_ARCH_VERSATILE is not set -+# CONFIG_ARCH_AT91 is not set -+# CONFIG_ARCH_CLPS7500 is not set -+# CONFIG_ARCH_CLPS711X is not set -+# CONFIG_ARCH_CO285 is not set -+# CONFIG_ARCH_EBSA110 is not set -+# CONFIG_ARCH_EP93XX is not set -+# CONFIG_ARCH_FOOTBRIDGE is not set -+# CONFIG_ARCH_NETX is not set -+# CONFIG_ARCH_H720X is not set -+# CONFIG_ARCH_IMX is not set -+# CONFIG_ARCH_IOP13XX is not set -+# CONFIG_ARCH_IOP32X is not set -+# CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IXP23XX is not set -+# CONFIG_ARCH_IXP2000 is not set -+# CONFIG_ARCH_IXP4XX is not set -+# CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_KIRKWOOD is not set -+# CONFIG_ARCH_KS8695 is not set -+# CONFIG_ARCH_NS9XXX is not set -+# CONFIG_ARCH_LOKI is not set -+CONFIG_ARCH_MV78XX0=y -+# CONFIG_ARCH_MXC is not set -+# CONFIG_ARCH_ORION5X is not set -+# CONFIG_ARCH_PNX4008 is not set -+# CONFIG_ARCH_PXA is not set -+# CONFIG_ARCH_RPC is not set -+# CONFIG_ARCH_SA1100 is not set -+# CONFIG_ARCH_S3C2410 is not set -+# CONFIG_ARCH_SHARK is not set -+# CONFIG_ARCH_LH7A40X is not set -+# CONFIG_ARCH_DAVINCI is not set -+# CONFIG_ARCH_OMAP is not set -+# CONFIG_ARCH_MSM7X00A is not set -+ -+# -+# Marvell MV78xx0 Implementations -+# -+CONFIG_MACH_DB78X00_BP=y -+ -+# -+# Boot options -+# -+ -+# -+# Power management -+# -+CONFIG_PLAT_ORION=y -+ -+# -+# Processor Type -+# -+CONFIG_CPU_32=y -+CONFIG_CPU_FEROCEON=y -+CONFIG_CPU_FEROCEON_OLD_ID=y -+CONFIG_CPU_32v5=y -+CONFIG_CPU_ABRT_EV5T=y -+CONFIG_CPU_PABRT_NOIFAR=y -+CONFIG_CPU_CACHE_VIVT=y -+CONFIG_CPU_COPY_FEROCEON=y -+CONFIG_CPU_TLB_FEROCEON=y -+CONFIG_CPU_CP15=y -+CONFIG_CPU_CP15_MMU=y -+ -+# -+# Processor Features -+# -+CONFIG_ARM_THUMB=y -+# CONFIG_CPU_ICACHE_DISABLE is not set -+# CONFIG_CPU_DCACHE_DISABLE is not set -+CONFIG_OUTER_CACHE=y -+CONFIG_CACHE_FEROCEON_L2=y -+ -+# -+# Bus support -+# -+CONFIG_PCI=y -+CONFIG_PCI_SYSCALL=y -+# CONFIG_ARCH_SUPPORTS_MSI is not set -+CONFIG_PCI_LEGACY=y -+# CONFIG_PCI_DEBUG is not set -+# CONFIG_PCCARD is not set -+ -+# -+# Kernel Features -+# -+CONFIG_TICK_ONESHOT=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -+CONFIG_PREEMPT=y -+CONFIG_HZ=100 -+CONFIG_AEABI=y -+CONFIG_OABI_COMPAT=y -+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+# CONFIG_SPARSEMEM_STATIC is not set -+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -+CONFIG_PAGEFLAGS_EXTENDED=y -+CONFIG_SPLIT_PTLOCK_CPUS=4096 -+# CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 -+CONFIG_BOUNCE=y -+CONFIG_VIRT_TO_BUS=y -+CONFIG_ALIGNMENT_TRAP=y -+ -+# -+# Boot options -+# -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CMDLINE="" -+# CONFIG_XIP_KERNEL is not set -+# CONFIG_KEXEC is not set -+ -+# -+# Floating point emulation -+# -+ -+# -+# At least one emulation must be selected -+# -+CONFIG_FPE_NWFPE=y -+# CONFIG_FPE_NWFPE_XP is not set -+# CONFIG_FPE_FASTFPE is not set -+CONFIG_VFP=y -+ -+# -+# Userspace binary formats -+# -+CONFIG_BINFMT_ELF=y -+# CONFIG_BINFMT_AOUT is not set -+# CONFIG_BINFMT_MISC is not set -+ -+# -+# Power management options -+# -+# CONFIG_PM is not set -+CONFIG_ARCH_SUSPEND_POSSIBLE=y -+ -+# -+# Networking -+# -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+CONFIG_PACKET_MMAP=y -+CONFIG_UNIX=y -+CONFIG_XFRM=y -+# CONFIG_XFRM_USER is not set -+# CONFIG_XFRM_SUB_POLICY is not set -+# CONFIG_XFRM_MIGRATE is not set -+# CONFIG_XFRM_STATISTICS is not set -+# CONFIG_NET_KEY is not set -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+# CONFIG_IP_ADVANCED_ROUTER is not set -+CONFIG_IP_FIB_HASH=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+# CONFIG_IP_PNP_RARP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_IP_MROUTE is not set -+# CONFIG_ARPD is not set -+# CONFIG_SYN_COOKIES is not set -+# CONFIG_INET_AH is not set -+# CONFIG_INET_ESP is not set -+# CONFIG_INET_IPCOMP is not set -+# CONFIG_INET_XFRM_TUNNEL is not set -+# CONFIG_INET_TUNNEL is not set -+CONFIG_INET_XFRM_MODE_TRANSPORT=y -+CONFIG_INET_XFRM_MODE_TUNNEL=y -+CONFIG_INET_XFRM_MODE_BEET=y -+# CONFIG_INET_LRO is not set -+CONFIG_INET_DIAG=y -+CONFIG_INET_TCP_DIAG=y -+# CONFIG_TCP_CONG_ADVANCED is not set -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set -+# CONFIG_IPV6 is not set -+# CONFIG_NETWORK_SECMARK is not set -+# CONFIG_NETFILTER is not set -+# CONFIG_IP_DCCP is not set -+# CONFIG_IP_SCTP is not set -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+# CONFIG_NET_SCHED is not set -+ -+# -+# Network testing -+# -+CONFIG_NET_PKTGEN=m -+# CONFIG_NET_TCPPROBE is not set -+# CONFIG_HAMRADIO is not set -+# CONFIG_CAN is not set -+# CONFIG_IRDA is not set -+# CONFIG_BT is not set -+# CONFIG_AF_RXRPC is not set -+ -+# -+# Wireless -+# -+# CONFIG_CFG80211 is not set -+CONFIG_WIRELESS_EXT=y -+# CONFIG_MAC80211 is not set -+# CONFIG_IEEE80211 is not set -+# CONFIG_RFKILL is not set -+# CONFIG_NET_9P is not set -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+CONFIG_FW_LOADER=y -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set -+# CONFIG_SYS_HYPERVISOR is not set -+# CONFIG_CONNECTOR is not set -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+# CONFIG_MTD_CONCAT is not set -+CONFIG_MTD_PARTITIONS=y -+# CONFIG_MTD_REDBOOT_PARTS is not set -+CONFIG_MTD_CMDLINE_PARTS=y -+# CONFIG_MTD_AFS_PARTS is not set -+# CONFIG_MTD_AR7_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLKDEVS=y -+CONFIG_MTD_BLOCK=y -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+# CONFIG_MTD_OOPS is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+CONFIG_MTD_CFI=y -+CONFIG_MTD_JEDECPROBE=y -+CONFIG_MTD_GEN_PROBE=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_NOSWAP=y -+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -+CONFIG_MTD_CFI_GEOMETRY=y -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+# CONFIG_MTD_OTP is not set -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+# CONFIG_MTD_CFI_STAA is not set -+CONFIG_MTD_CFI_UTIL=y -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+ -+# -+# Mapping drivers for chip access -+# -+# CONFIG_MTD_COMPLEX_MAPPINGS is not set -+CONFIG_MTD_PHYSMAP=y -+CONFIG_MTD_PHYSMAP_START=0x0 -+CONFIG_MTD_PHYSMAP_LEN=0x0 -+CONFIG_MTD_PHYSMAP_BANKWIDTH=0 -+# CONFIG_MTD_ARM_INTEGRATOR is not set -+# CONFIG_MTD_IMPA7 is not set -+# CONFIG_MTD_INTEL_VR_NOR is not set -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_PMC551 is not set -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+CONFIG_MTD_NAND=y -+CONFIG_MTD_NAND_VERIFY_WRITE=y -+# CONFIG_MTD_NAND_ECC_SMC is not set -+# CONFIG_MTD_NAND_MUSEUM_IDS is not set -+CONFIG_MTD_NAND_IDS=y -+# CONFIG_MTD_NAND_DISKONCHIP is not set -+# CONFIG_MTD_NAND_CAFE is not set -+# CONFIG_MTD_NAND_NANDSIM is not set -+# CONFIG_MTD_NAND_PLATFORM is not set -+# CONFIG_MTD_ALAUDA is not set -+CONFIG_MTD_NAND_ORION=y -+# CONFIG_MTD_ONENAND is not set -+ -+# -+# UBI - Unsorted block images -+# -+# CONFIG_MTD_UBI is not set -+# CONFIG_PARPORT is not set -+CONFIG_BLK_DEV=y -+# CONFIG_BLK_CPQ_DA is not set -+# CONFIG_BLK_CPQ_CISS_DA is not set -+# CONFIG_BLK_DEV_DAC960 is not set -+# CONFIG_BLK_DEV_UMEM is not set -+# CONFIG_BLK_DEV_COW_COMMON is not set -+CONFIG_BLK_DEV_LOOP=y -+# CONFIG_BLK_DEV_CRYPTOLOOP is not set -+# CONFIG_BLK_DEV_NBD is not set -+# CONFIG_BLK_DEV_SX8 is not set -+# CONFIG_BLK_DEV_UB is not set -+# CONFIG_BLK_DEV_RAM is not set -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+CONFIG_MISC_DEVICES=y -+# CONFIG_PHANTOM is not set -+# CONFIG_EEPROM_93CX6 is not set -+# CONFIG_SGI_IOC4 is not set -+# CONFIG_TIFM_CORE is not set -+# CONFIG_ENCLOSURE_SERVICES is not set -+CONFIG_HAVE_IDE=y -+# CONFIG_IDE is not set -+ -+# -+# SCSI device support -+# -+# CONFIG_RAID_ATTRS is not set -+CONFIG_SCSI=y -+CONFIG_SCSI_DMA=y -+# CONFIG_SCSI_TGT is not set -+# CONFIG_SCSI_NETLINK is not set -+# CONFIG_SCSI_PROC_FS is not set -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+# CONFIG_CHR_DEV_OSST is not set -+CONFIG_BLK_DEV_SR=m -+# CONFIG_BLK_DEV_SR_VENDOR is not set -+CONFIG_CHR_DEV_SG=m -+# CONFIG_CHR_DEV_SCH is not set -+ -+# -+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -+# -+# CONFIG_SCSI_MULTI_LUN is not set -+# CONFIG_SCSI_CONSTANTS is not set -+# CONFIG_SCSI_LOGGING is not set -+# CONFIG_SCSI_SCAN_ASYNC is not set -+CONFIG_SCSI_WAIT_SCAN=m -+ -+# -+# SCSI Transports -+# -+# CONFIG_SCSI_SPI_ATTRS is not set -+# CONFIG_SCSI_FC_ATTRS is not set -+# CONFIG_SCSI_ISCSI_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+# CONFIG_SCSI_SRP_ATTRS is not set -+CONFIG_SCSI_LOWLEVEL=y -+# CONFIG_ISCSI_TCP is not set -+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -+# CONFIG_SCSI_3W_9XXX is not set -+# CONFIG_SCSI_ACARD is not set -+# CONFIG_SCSI_AACRAID is not set -+# CONFIG_SCSI_AIC7XXX is not set -+# CONFIG_SCSI_AIC7XXX_OLD is not set -+# CONFIG_SCSI_AIC79XX is not set -+# CONFIG_SCSI_AIC94XX is not set -+# CONFIG_SCSI_DPT_I2O is not set -+# CONFIG_SCSI_ADVANSYS is not set -+# CONFIG_SCSI_ARCMSR is not set -+# CONFIG_MEGARAID_NEWGEN is not set -+# CONFIG_MEGARAID_LEGACY is not set -+# CONFIG_MEGARAID_SAS is not set -+# CONFIG_SCSI_HPTIOP is not set -+# CONFIG_SCSI_DMX3191D is not set -+# CONFIG_SCSI_FUTURE_DOMAIN is not set -+# CONFIG_SCSI_IPS is not set -+# CONFIG_SCSI_INITIO is not set -+# CONFIG_SCSI_INIA100 is not set -+# CONFIG_SCSI_MVSAS is not set -+# CONFIG_SCSI_STEX is not set -+# CONFIG_SCSI_SYM53C8XX_2 is not set -+# CONFIG_SCSI_IPR is not set -+# CONFIG_SCSI_QLOGIC_1280 is not set -+# CONFIG_SCSI_QLA_FC is not set -+# CONFIG_SCSI_QLA_ISCSI is not set -+# CONFIG_SCSI_LPFC is not set -+# CONFIG_SCSI_DC395x is not set -+# CONFIG_SCSI_DC390T is not set -+# CONFIG_SCSI_NSP32 is not set -+# CONFIG_SCSI_DEBUG is not set -+# CONFIG_SCSI_SRP is not set -+CONFIG_ATA=y -+# CONFIG_ATA_NONSTANDARD is not set -+CONFIG_SATA_PMP=y -+# CONFIG_SATA_AHCI is not set -+# CONFIG_SATA_SIL24 is not set -+CONFIG_ATA_SFF=y -+# CONFIG_SATA_SVW is not set -+# CONFIG_ATA_PIIX is not set -+CONFIG_SATA_MV=y -+# CONFIG_SATA_NV is not set -+# CONFIG_PDC_ADMA is not set -+# CONFIG_SATA_QSTOR is not set -+# CONFIG_SATA_PROMISE is not set -+# CONFIG_SATA_SX4 is not set -+# CONFIG_SATA_SIL is not set -+# CONFIG_SATA_SIS is not set -+# CONFIG_SATA_ULI is not set -+# CONFIG_SATA_VIA is not set -+# CONFIG_SATA_VITESSE is not set -+# CONFIG_SATA_INIC162X is not set -+# CONFIG_PATA_ALI is not set -+# CONFIG_PATA_AMD is not set -+# CONFIG_PATA_ARTOP is not set -+# CONFIG_PATA_ATIIXP is not set -+# CONFIG_PATA_CMD640_PCI is not set -+# CONFIG_PATA_CMD64X is not set -+# CONFIG_PATA_CS5520 is not set -+# CONFIG_PATA_CS5530 is not set -+# CONFIG_PATA_CYPRESS is not set -+# CONFIG_PATA_EFAR is not set -+# CONFIG_ATA_GENERIC is not set -+# CONFIG_PATA_HPT366 is not set -+# CONFIG_PATA_HPT37X is not set -+# CONFIG_PATA_HPT3X2N is not set -+# CONFIG_PATA_HPT3X3 is not set -+# CONFIG_PATA_IT821X is not set -+# CONFIG_PATA_IT8213 is not set -+# CONFIG_PATA_JMICRON is not set -+# CONFIG_PATA_TRIFLEX is not set -+# CONFIG_PATA_MARVELL is not set -+# CONFIG_PATA_MPIIX is not set -+# CONFIG_PATA_OLDPIIX is not set -+# CONFIG_PATA_NETCELL is not set -+# CONFIG_PATA_NINJA32 is not set -+# CONFIG_PATA_NS87410 is not set -+# CONFIG_PATA_NS87415 is not set -+# CONFIG_PATA_OPTI is not set -+# CONFIG_PATA_OPTIDMA is not set -+# CONFIG_PATA_PDC_OLD is not set -+# CONFIG_PATA_RADISYS is not set -+# CONFIG_PATA_RZ1000 is not set -+# CONFIG_PATA_SC1200 is not set -+# CONFIG_PATA_SERVERWORKS is not set -+# CONFIG_PATA_PDC2027X is not set -+# CONFIG_PATA_SIL680 is not set -+# CONFIG_PATA_SIS is not set -+# CONFIG_PATA_VIA is not set -+# CONFIG_PATA_WINBOND is not set -+# CONFIG_PATA_PLATFORM is not set -+# CONFIG_PATA_SCH is not set -+# CONFIG_MD is not set -+# CONFIG_FUSION is not set -+ -+# -+# IEEE 1394 (FireWire) support -+# -+# CONFIG_FIREWIRE is not set -+# CONFIG_IEEE1394 is not set -+# CONFIG_I2O is not set -+CONFIG_NETDEVICES=y -+# CONFIG_NETDEVICES_MULTIQUEUE is not set -+# CONFIG_DUMMY is not set -+# CONFIG_BONDING is not set -+# CONFIG_MACVLAN is not set -+# CONFIG_EQUALIZER is not set -+# CONFIG_TUN is not set -+# CONFIG_VETH is not set -+# CONFIG_ARCNET is not set -+# CONFIG_PHYLIB is not set -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=y -+# CONFIG_AX88796 is not set -+# CONFIG_HAPPYMEAL is not set -+# CONFIG_SUNGEM is not set -+# CONFIG_CASSINI is not set -+# CONFIG_NET_VENDOR_3COM is not set -+# CONFIG_SMC91X is not set -+# CONFIG_DM9000 is not set -+# CONFIG_NET_TULIP is not set -+# CONFIG_HP100 is not set -+# CONFIG_IBM_NEW_EMAC_ZMII is not set -+# CONFIG_IBM_NEW_EMAC_RGMII is not set -+# CONFIG_IBM_NEW_EMAC_TAH is not set -+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -+CONFIG_NET_PCI=y -+# CONFIG_PCNET32 is not set -+# CONFIG_AMD8111_ETH is not set -+# CONFIG_ADAPTEC_STARFIRE is not set -+# CONFIG_B44 is not set -+# CONFIG_FORCEDETH is not set -+# CONFIG_EEPRO100 is not set -+# CONFIG_E100 is not set -+# CONFIG_FEALNX is not set -+# CONFIG_NATSEMI is not set -+# CONFIG_NE2K_PCI is not set -+# CONFIG_8139CP is not set -+# CONFIG_8139TOO is not set -+# CONFIG_R6040 is not set -+# CONFIG_SIS900 is not set -+# CONFIG_EPIC100 is not set -+# CONFIG_SUNDANCE is not set -+# CONFIG_TLAN is not set -+# CONFIG_VIA_RHINE is not set -+# CONFIG_SC92031 is not set -+CONFIG_NETDEV_1000=y -+# CONFIG_ACENIC is not set -+# CONFIG_DL2K is not set -+# CONFIG_E1000 is not set -+# CONFIG_E1000E is not set -+# CONFIG_E1000E_ENABLED is not set -+# CONFIG_IP1000 is not set -+# CONFIG_IGB is not set -+# CONFIG_NS83820 is not set -+# CONFIG_HAMACHI is not set -+# CONFIG_YELLOWFIN is not set -+# CONFIG_R8169 is not set -+# CONFIG_SIS190 is not set -+# CONFIG_SKGE is not set -+# CONFIG_SKY2 is not set -+# CONFIG_VIA_VELOCITY is not set -+# CONFIG_TIGON3 is not set -+# CONFIG_BNX2 is not set -+CONFIG_MV643XX_ETH=y -+# CONFIG_QLA3XXX is not set -+# CONFIG_ATL1 is not set -+# CONFIG_NETDEV_10000 is not set -+# CONFIG_TR is not set -+ -+# -+# Wireless LAN -+# -+# CONFIG_WLAN_PRE80211 is not set -+# CONFIG_WLAN_80211 is not set -+# CONFIG_IWLWIFI_LEDS is not set -+ -+# -+# USB Network Adapters -+# -+# CONFIG_USB_CATC is not set -+# CONFIG_USB_KAWETH is not set -+# CONFIG_USB_PEGASUS is not set -+# CONFIG_USB_RTL8150 is not set -+# CONFIG_USB_USBNET is not set -+# CONFIG_WAN is not set -+# CONFIG_FDDI is not set -+# CONFIG_HIPPI is not set -+# CONFIG_PPP is not set -+# CONFIG_SLIP is not set -+# CONFIG_NET_FC is not set -+# CONFIG_NETCONSOLE is not set -+# CONFIG_NETPOLL is not set -+# CONFIG_NET_POLL_CONTROLLER is not set -+# CONFIG_ISDN is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+# CONFIG_INPUT_FF_MEMLESS is not set -+# CONFIG_INPUT_POLLDEV is not set -+ -+# -+# Userland interfaces -+# -+# CONFIG_INPUT_MOUSEDEV is not set -+# CONFIG_INPUT_JOYDEV is not set -+CONFIG_INPUT_EVDEV=y -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+# CONFIG_INPUT_KEYBOARD is not set -+# CONFIG_INPUT_MOUSE is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TABLET is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+# CONFIG_INPUT_MISC is not set -+ -+# -+# Hardware I/O ports -+# -+# CONFIG_SERIO is not set -+# CONFIG_GAMEPORT is not set -+ -+# -+# Character devices -+# -+# CONFIG_VT is not set -+CONFIG_DEVKMEM=y -+# CONFIG_SERIAL_NONSTANDARD is not set -+# CONFIG_NOZOMI is not set -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+# CONFIG_SERIAL_8250_PCI is not set -+CONFIG_SERIAL_8250_NR_UARTS=4 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -+# CONFIG_SERIAL_8250_EXTENDED is not set -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+# CONFIG_SERIAL_JSM is not set -+CONFIG_UNIX98_PTYS=y -+CONFIG_LEGACY_PTYS=y -+CONFIG_LEGACY_PTY_COUNT=16 -+# CONFIG_IPMI_HANDLER is not set -+# CONFIG_HW_RANDOM is not set -+# CONFIG_NVRAM is not set -+# CONFIG_R3964 is not set -+# CONFIG_APPLICOM is not set -+# CONFIG_RAW_DRIVER is not set -+# CONFIG_TCG_TPM is not set -+CONFIG_DEVPORT=y -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_CHARDEV=y -+ -+# -+# I2C Hardware Bus support -+# -+# CONFIG_I2C_ALI1535 is not set -+# CONFIG_I2C_ALI1563 is not set -+# CONFIG_I2C_ALI15X3 is not set -+# CONFIG_I2C_AMD756 is not set -+# CONFIG_I2C_AMD8111 is not set -+# CONFIG_I2C_I801 is not set -+# CONFIG_I2C_I810 is not set -+# CONFIG_I2C_PIIX4 is not set -+# CONFIG_I2C_NFORCE2 is not set -+# CONFIG_I2C_OCORES is not set -+# CONFIG_I2C_PARPORT_LIGHT is not set -+# CONFIG_I2C_PROSAVAGE is not set -+# CONFIG_I2C_SAVAGE4 is not set -+# CONFIG_I2C_SIMTEC is not set -+# CONFIG_I2C_SIS5595 is not set -+# CONFIG_I2C_SIS630 is not set -+# CONFIG_I2C_SIS96X is not set -+# CONFIG_I2C_TAOS_EVM is not set -+# CONFIG_I2C_STUB is not set -+# CONFIG_I2C_TINY_USB is not set -+# CONFIG_I2C_VIA is not set -+# CONFIG_I2C_VIAPRO is not set -+# CONFIG_I2C_VOODOO3 is not set -+# CONFIG_I2C_PCA_PLATFORM is not set -+CONFIG_I2C_MV64XXX=y -+ -+# -+# Miscellaneous I2C Chip support -+# -+# CONFIG_DS1682 is not set -+# CONFIG_SENSORS_EEPROM is not set -+# CONFIG_SENSORS_PCF8574 is not set -+# CONFIG_PCF8575 is not set -+# CONFIG_SENSORS_PCF8591 is not set -+# CONFIG_SENSORS_MAX6875 is not set -+# CONFIG_SENSORS_TSL2550 is not set -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_ALGO is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+# CONFIG_I2C_DEBUG_CHIP is not set -+# CONFIG_SPI is not set -+# CONFIG_W1 is not set -+# CONFIG_POWER_SUPPLY is not set -+CONFIG_HWMON=y -+# CONFIG_HWMON_VID is not set -+# CONFIG_SENSORS_AD7418 is not set -+# CONFIG_SENSORS_ADM1021 is not set -+# CONFIG_SENSORS_ADM1025 is not set -+# CONFIG_SENSORS_ADM1026 is not set -+# CONFIG_SENSORS_ADM1029 is not set -+# CONFIG_SENSORS_ADM1031 is not set -+# CONFIG_SENSORS_ADM9240 is not set -+# CONFIG_SENSORS_ADT7470 is not set -+# CONFIG_SENSORS_ADT7473 is not set -+# CONFIG_SENSORS_ATXP1 is not set -+# CONFIG_SENSORS_DS1621 is not set -+# CONFIG_SENSORS_I5K_AMB is not set -+# CONFIG_SENSORS_F71805F is not set -+# CONFIG_SENSORS_F71882FG is not set -+# CONFIG_SENSORS_F75375S is not set -+# CONFIG_SENSORS_GL518SM is not set -+# CONFIG_SENSORS_GL520SM is not set -+# CONFIG_SENSORS_IT87 is not set -+# CONFIG_SENSORS_LM63 is not set -+# CONFIG_SENSORS_LM75 is not set -+# CONFIG_SENSORS_LM77 is not set -+# CONFIG_SENSORS_LM78 is not set -+# CONFIG_SENSORS_LM80 is not set -+# CONFIG_SENSORS_LM83 is not set -+# CONFIG_SENSORS_LM85 is not set -+# CONFIG_SENSORS_LM87 is not set -+# CONFIG_SENSORS_LM90 is not set -+# CONFIG_SENSORS_LM92 is not set -+# CONFIG_SENSORS_LM93 is not set -+# CONFIG_SENSORS_MAX1619 is not set -+# CONFIG_SENSORS_MAX6650 is not set -+# CONFIG_SENSORS_PC87360 is not set -+# CONFIG_SENSORS_PC87427 is not set -+# CONFIG_SENSORS_SIS5595 is not set -+# CONFIG_SENSORS_DME1737 is not set -+# CONFIG_SENSORS_SMSC47M1 is not set -+# CONFIG_SENSORS_SMSC47M192 is not set -+# CONFIG_SENSORS_SMSC47B397 is not set -+# CONFIG_SENSORS_ADS7828 is not set -+# CONFIG_SENSORS_THMC50 is not set -+# CONFIG_SENSORS_VIA686A is not set -+# CONFIG_SENSORS_VT1211 is not set -+# CONFIG_SENSORS_VT8231 is not set -+# CONFIG_SENSORS_W83781D is not set -+# CONFIG_SENSORS_W83791D is not set -+# CONFIG_SENSORS_W83792D is not set -+# CONFIG_SENSORS_W83793 is not set -+# CONFIG_SENSORS_W83L785TS is not set -+# CONFIG_SENSORS_W83L786NG is not set -+# CONFIG_SENSORS_W83627HF is not set -+# CONFIG_SENSORS_W83627EHF is not set -+# CONFIG_HWMON_DEBUG_CHIP is not set -+# CONFIG_WATCHDOG is not set -+ -+# -+# Sonics Silicon Backplane -+# -+CONFIG_SSB_POSSIBLE=y -+# CONFIG_SSB is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set -+# CONFIG_MFD_ASIC3 is not set -+# CONFIG_HTC_PASIC3 is not set -+ -+# -+# Multimedia devices -+# -+ -+# -+# Multimedia core support -+# -+# CONFIG_VIDEO_DEV is not set -+# CONFIG_DVB_CORE is not set -+# CONFIG_VIDEO_MEDIA is not set -+ -+# -+# Multimedia drivers -+# -+# CONFIG_DAB is not set -+ -+# -+# Graphics support -+# -+# CONFIG_DRM is not set -+# CONFIG_VGASTATE is not set -+# CONFIG_VIDEO_OUTPUT_CONTROL is not set -+# CONFIG_FB is not set -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -+ -+# -+# Display device support -+# -+# CONFIG_DISPLAY_SUPPORT is not set -+ -+# -+# Sound -+# -+# CONFIG_SOUND is not set -+CONFIG_HID_SUPPORT=y -+CONFIG_HID=y -+# CONFIG_HID_DEBUG is not set -+# CONFIG_HIDRAW is not set -+ -+# -+# USB Input Devices -+# -+CONFIG_USB_HID=y -+# CONFIG_USB_HIDINPUT_POWERBOOK is not set -+# CONFIG_HID_FF is not set -+# CONFIG_USB_HIDDEV is not set -+CONFIG_USB_SUPPORT=y -+CONFIG_USB_ARCH_HAS_HCD=y -+CONFIG_USB_ARCH_HAS_OHCI=y -+CONFIG_USB_ARCH_HAS_EHCI=y -+CONFIG_USB=y -+# CONFIG_USB_DEBUG is not set -+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set -+ -+# -+# Miscellaneous USB options -+# -+CONFIG_USB_DEVICEFS=y -+CONFIG_USB_DEVICE_CLASS=y -+# CONFIG_USB_DYNAMIC_MINORS is not set -+# CONFIG_USB_OTG is not set -+# CONFIG_USB_OTG_WHITELIST is not set -+# CONFIG_USB_OTG_BLACKLIST_HUB is not set -+ -+# -+# USB Host Controller Drivers -+# -+# CONFIG_USB_C67X00_HCD is not set -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_ROOT_HUB_TT=y -+CONFIG_USB_EHCI_TT_NEWSCHED=y -+# CONFIG_USB_ISP116X_HCD is not set -+# CONFIG_USB_ISP1760_HCD is not set -+# CONFIG_USB_OHCI_HCD is not set -+# CONFIG_USB_UHCI_HCD is not set -+# CONFIG_USB_SL811_HCD is not set -+# CONFIG_USB_R8A66597_HCD is not set -+ -+# -+# USB Device Class drivers -+# -+# CONFIG_USB_ACM is not set -+CONFIG_USB_PRINTER=y -+# CONFIG_USB_WDM is not set -+ -+# -+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -+# -+ -+# -+# may also be needed; see USB_STORAGE Help for more information -+# -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+CONFIG_USB_STORAGE_DATAFAB=y -+CONFIG_USB_STORAGE_FREECOM=y -+# CONFIG_USB_STORAGE_ISD200 is not set -+CONFIG_USB_STORAGE_DPCM=y -+# CONFIG_USB_STORAGE_USBAT is not set -+CONFIG_USB_STORAGE_SDDR09=y -+CONFIG_USB_STORAGE_SDDR55=y -+CONFIG_USB_STORAGE_JUMPSHOT=y -+# CONFIG_USB_STORAGE_ALAUDA is not set -+# CONFIG_USB_STORAGE_ONETOUCH is not set -+# CONFIG_USB_STORAGE_KARMA is not set -+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -+# CONFIG_USB_LIBUSUAL is not set -+ -+# -+# USB Imaging devices -+# -+# CONFIG_USB_MDC800 is not set -+# CONFIG_USB_MICROTEK is not set -+# CONFIG_USB_MON is not set -+ -+# -+# USB port drivers -+# -+# CONFIG_USB_SERIAL is not set -+ -+# -+# USB Miscellaneous drivers -+# -+# CONFIG_USB_EMI62 is not set -+# CONFIG_USB_EMI26 is not set -+# CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_AUERSWALD is not set -+# CONFIG_USB_RIO500 is not set -+# CONFIG_USB_LEGOTOWER is not set -+# CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set -+# CONFIG_USB_LED is not set -+# CONFIG_USB_CYPRESS_CY7C63 is not set -+# CONFIG_USB_CYTHERM is not set -+# CONFIG_USB_PHIDGET is not set -+# CONFIG_USB_IDMOUSE is not set -+# CONFIG_USB_FTDI_ELAN is not set -+# CONFIG_USB_APPLEDISPLAY is not set -+# CONFIG_USB_SISUSBVGA is not set -+# CONFIG_USB_LD is not set -+# CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set -+# CONFIG_USB_TEST is not set -+# CONFIG_USB_ISIGHTFW is not set -+# CONFIG_USB_GADGET is not set -+# CONFIG_MMC is not set -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+ -+# -+# LED drivers -+# -+ -+# -+# LED Triggers -+# -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_TIMER=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set -+CONFIG_RTC_LIB=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_HCTOSYS=y -+CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -+# CONFIG_RTC_DEBUG is not set -+ -+# -+# RTC interfaces -+# -+CONFIG_RTC_INTF_SYSFS=y -+CONFIG_RTC_INTF_PROC=y -+CONFIG_RTC_INTF_DEV=y -+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -+# CONFIG_RTC_DRV_TEST is not set -+ -+# -+# I2C RTC drivers -+# -+CONFIG_RTC_DRV_DS1307=y -+# CONFIG_RTC_DRV_DS1374 is not set -+# CONFIG_RTC_DRV_DS1672 is not set -+# CONFIG_RTC_DRV_MAX6900 is not set -+CONFIG_RTC_DRV_RS5C372=y -+# CONFIG_RTC_DRV_ISL1208 is not set -+# CONFIG_RTC_DRV_X1205 is not set -+# CONFIG_RTC_DRV_PCF8563 is not set -+# CONFIG_RTC_DRV_PCF8583 is not set -+CONFIG_RTC_DRV_M41T80=y -+# CONFIG_RTC_DRV_M41T80_WDT is not set -+# CONFIG_RTC_DRV_S35390A is not set -+ -+# -+# SPI RTC drivers -+# -+ -+# -+# Platform RTC drivers -+# -+# CONFIG_RTC_DRV_CMOS is not set -+# CONFIG_RTC_DRV_DS1511 is not set -+# CONFIG_RTC_DRV_DS1553 is not set -+# CONFIG_RTC_DRV_DS1742 is not set -+# CONFIG_RTC_DRV_STK17TA8 is not set -+# CONFIG_RTC_DRV_M48T86 is not set -+# CONFIG_RTC_DRV_M48T59 is not set -+# CONFIG_RTC_DRV_V3020 is not set -+ -+# -+# on-CPU RTC drivers -+# -+# CONFIG_UIO is not set -+ -+# -+# File systems -+# -+CONFIG_EXT2_FS=y -+# CONFIG_EXT2_FS_XATTR is not set -+# CONFIG_EXT2_FS_XIP is not set -+CONFIG_EXT3_FS=y -+# CONFIG_EXT3_FS_XATTR is not set -+# CONFIG_EXT4DEV_FS is not set -+CONFIG_JBD=y -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+# CONFIG_FS_POSIX_ACL is not set -+# CONFIG_XFS_FS is not set -+# CONFIG_OCFS2_FS is not set -+CONFIG_DNOTIFY=y -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+# CONFIG_QUOTA is not set -+# CONFIG_AUTOFS_FS is not set -+# CONFIG_AUTOFS4_FS is not set -+# CONFIG_FUSE_FS is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+# CONFIG_ZISOFS is not set -+CONFIG_UDF_FS=m -+CONFIG_UDF_NLS=y -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+# CONFIG_NTFS_FS is not set -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_SYSCTL=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+# CONFIG_TMPFS_POSIX_ACL is not set -+# CONFIG_HUGETLB_PAGE is not set -+# CONFIG_CONFIGFS_FS is not set -+ -+# -+# Miscellaneous filesystems -+# -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -+# CONFIG_JFFS2_SUMMARY is not set -+# CONFIG_JFFS2_FS_XATTR is not set -+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_ZLIB=y -+# CONFIG_JFFS2_LZO is not set -+CONFIG_JFFS2_RTIME=y -+# CONFIG_JFFS2_RUBIN is not set -+CONFIG_CRAMFS=y -+# CONFIG_VXFS_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_ROMFS_FS is not set -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+CONFIG_NETWORK_FILESYSTEMS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3=y -+# CONFIG_NFS_V3_ACL is not set -+# CONFIG_NFS_V4 is not set -+# CONFIG_NFSD is not set -+CONFIG_ROOT_NFS=y -+CONFIG_LOCKD=y -+CONFIG_LOCKD_V4=y -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=y -+# CONFIG_SUNRPC_BIND34 is not set -+# CONFIG_RPCSEC_GSS_KRB5 is not set -+# CONFIG_RPCSEC_GSS_SPKM3 is not set -+# CONFIG_SMB_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_NCP_FS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+# CONFIG_MAC_PARTITION is not set -+CONFIG_MSDOS_PARTITION=y -+CONFIG_BSD_DISKLABEL=y -+# CONFIG_MINIX_SUBPARTITION is not set -+# CONFIG_SOLARIS_X86_PARTITION is not set -+# CONFIG_UNIXWARE_DISKLABEL is not set -+# CONFIG_LDM_PARTITION is not set -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_SUN_PARTITION is not set -+# CONFIG_KARMA_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_SYSV68_PARTITION is not set -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="iso8859-1" -+CONFIG_NLS_CODEPAGE_437=y -+# CONFIG_NLS_CODEPAGE_737 is not set -+# CONFIG_NLS_CODEPAGE_775 is not set -+CONFIG_NLS_CODEPAGE_850=y -+# CONFIG_NLS_CODEPAGE_852 is not set -+# CONFIG_NLS_CODEPAGE_855 is not set -+# CONFIG_NLS_CODEPAGE_857 is not set -+# CONFIG_NLS_CODEPAGE_860 is not set -+# CONFIG_NLS_CODEPAGE_861 is not set -+# CONFIG_NLS_CODEPAGE_862 is not set -+# CONFIG_NLS_CODEPAGE_863 is not set -+# CONFIG_NLS_CODEPAGE_864 is not set -+# CONFIG_NLS_CODEPAGE_865 is not set -+# CONFIG_NLS_CODEPAGE_866 is not set -+# CONFIG_NLS_CODEPAGE_869 is not set -+# CONFIG_NLS_CODEPAGE_936 is not set -+# CONFIG_NLS_CODEPAGE_950 is not set -+# CONFIG_NLS_CODEPAGE_932 is not set -+# CONFIG_NLS_CODEPAGE_949 is not set -+# CONFIG_NLS_CODEPAGE_874 is not set -+# CONFIG_NLS_ISO8859_8 is not set -+# CONFIG_NLS_CODEPAGE_1250 is not set -+# CONFIG_NLS_CODEPAGE_1251 is not set -+# CONFIG_NLS_ASCII is not set -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_2=y -+# CONFIG_NLS_ISO8859_3 is not set -+# CONFIG_NLS_ISO8859_4 is not set -+# CONFIG_NLS_ISO8859_5 is not set -+# CONFIG_NLS_ISO8859_6 is not set -+# CONFIG_NLS_ISO8859_7 is not set -+# CONFIG_NLS_ISO8859_9 is not set -+# CONFIG_NLS_ISO8859_13 is not set -+# CONFIG_NLS_ISO8859_14 is not set -+# CONFIG_NLS_ISO8859_15 is not set -+# CONFIG_NLS_KOI8_R is not set -+# CONFIG_NLS_KOI8_U is not set -+# CONFIG_NLS_UTF8 is not set -+# CONFIG_DLM is not set -+ -+# -+# Kernel hacking -+# -+# CONFIG_PRINTK_TIME is not set -+CONFIG_ENABLE_WARN_DEPRECATED=y -+CONFIG_ENABLE_MUST_CHECK=y -+CONFIG_FRAME_WARN=1024 -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_DEBUG_FS is not set -+# CONFIG_HEADERS_CHECK is not set -+CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set -+CONFIG_DETECT_SOFTLOCKUP=y -+CONFIG_SCHED_DEBUG=y -+CONFIG_SCHEDSTATS=y -+# CONFIG_TIMER_STATS is not set -+# CONFIG_DEBUG_OBJECTS is not set -+CONFIG_DEBUG_PREEMPT=y -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+# CONFIG_DEBUG_SPINLOCK is not set -+# CONFIG_DEBUG_MUTEXES is not set -+# CONFIG_DEBUG_LOCK_ALLOC is not set -+# CONFIG_PROVE_LOCKING is not set -+# CONFIG_LOCK_STAT is not set -+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_DEBUG_KOBJECT is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+CONFIG_DEBUG_INFO=y -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_WRITECOUNT is not set -+# CONFIG_DEBUG_LIST is not set -+# CONFIG_DEBUG_SG is not set -+CONFIG_FRAME_POINTER=y -+# CONFIG_BOOT_PRINTK_DELAY is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_KPROBES_SANITY_TEST is not set -+# CONFIG_BACKTRACE_SELF_TEST is not set -+# CONFIG_LKDTM is not set -+# CONFIG_FAULT_INJECTION is not set -+# CONFIG_LATENCYTOP is not set -+# CONFIG_SAMPLES is not set -+CONFIG_DEBUG_USER=y -+CONFIG_DEBUG_ERRORS=y -+# CONFIG_DEBUG_STACK_USAGE is not set -+CONFIG_DEBUG_LL=y -+# CONFIG_DEBUG_ICEDCC is not set -+ -+# -+# Security options -+# -+# CONFIG_KEYS is not set -+# CONFIG_SECURITY is not set -+# CONFIG_SECURITY_FILE_CAPABILITIES is not set -+CONFIG_CRYPTO=y -+ -+# -+# Crypto core or helper -+# -+CONFIG_CRYPTO_ALGAPI=m -+CONFIG_CRYPTO_BLKCIPHER=m -+CONFIG_CRYPTO_MANAGER=m -+# CONFIG_CRYPTO_GF128MUL is not set -+# CONFIG_CRYPTO_NULL is not set -+# CONFIG_CRYPTO_CRYPTD is not set -+# CONFIG_CRYPTO_AUTHENC is not set -+# CONFIG_CRYPTO_TEST is not set -+ -+# -+# Authenticated Encryption with Associated Data -+# -+# CONFIG_CRYPTO_CCM is not set -+# CONFIG_CRYPTO_GCM is not set -+# CONFIG_CRYPTO_SEQIV is not set -+ -+# -+# Block modes -+# -+CONFIG_CRYPTO_CBC=m -+# CONFIG_CRYPTO_CTR is not set -+# CONFIG_CRYPTO_CTS is not set -+CONFIG_CRYPTO_ECB=m -+# CONFIG_CRYPTO_LRW is not set -+CONFIG_CRYPTO_PCBC=m -+# CONFIG_CRYPTO_XTS is not set -+ -+# -+# Hash modes -+# -+# CONFIG_CRYPTO_HMAC is not set -+# CONFIG_CRYPTO_XCBC is not set -+ -+# -+# Digest -+# -+# CONFIG_CRYPTO_CRC32C is not set -+# CONFIG_CRYPTO_MD4 is not set -+# CONFIG_CRYPTO_MD5 is not set -+# CONFIG_CRYPTO_MICHAEL_MIC is not set -+# CONFIG_CRYPTO_SHA1 is not set -+# CONFIG_CRYPTO_SHA256 is not set -+# CONFIG_CRYPTO_SHA512 is not set -+# CONFIG_CRYPTO_TGR192 is not set -+# CONFIG_CRYPTO_WP512 is not set -+ -+# -+# Ciphers -+# -+# CONFIG_CRYPTO_AES is not set -+# CONFIG_CRYPTO_ANUBIS is not set -+# CONFIG_CRYPTO_ARC4 is not set -+# CONFIG_CRYPTO_BLOWFISH is not set -+# CONFIG_CRYPTO_CAMELLIA is not set -+# CONFIG_CRYPTO_CAST5 is not set -+# CONFIG_CRYPTO_CAST6 is not set -+# CONFIG_CRYPTO_DES is not set -+# CONFIG_CRYPTO_FCRYPT is not set -+# CONFIG_CRYPTO_KHAZAD is not set -+# CONFIG_CRYPTO_SALSA20 is not set -+# CONFIG_CRYPTO_SEED is not set -+# CONFIG_CRYPTO_SERPENT is not set -+# CONFIG_CRYPTO_TEA is not set -+# CONFIG_CRYPTO_TWOFISH is not set -+ -+# -+# Compression -+# -+# CONFIG_CRYPTO_DEFLATE is not set -+# CONFIG_CRYPTO_LZO is not set -+CONFIG_CRYPTO_HW=y -+# CONFIG_CRYPTO_DEV_HIFN_795X is not set -+ -+# -+# Library routines -+# -+CONFIG_BITREVERSE=y -+# CONFIG_GENERIC_FIND_FIRST_BIT is not set -+# CONFIG_GENERIC_FIND_NEXT_BIT is not set -+# CONFIG_CRC_CCITT is not set -+# CONFIG_CRC16 is not set -+CONFIG_CRC_ITU_T=m -+CONFIG_CRC32=y -+# CONFIG_CRC7 is not set -+# CONFIG_LIBCRC32C is not set -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_PLIST=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -+CONFIG_HAS_DMA=y ---- a/arch/arm/configs/orion5x_defconfig -+++ b/arch/arm/configs/orion5x_defconfig -@@ -1,7 +1,7 @@ - # - # Automatically generated make config: don't edit --# Linux kernel version: 2.6.24 --# Thu Feb 7 14:10:30 2008 -+# Linux kernel version: 2.6.26-rc4 -+# Mon Jun 2 23:54:48 2008 - # - CONFIG_ARM=y - CONFIG_SYS_SUPPORTS_APM_EMULATION=y -@@ -21,6 +21,7 @@ - # CONFIG_ARCH_HAS_ILOG2_U64 is not set - CONFIG_GENERIC_HWEIGHT=y - CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ARCH_SUPPORTS_AOUT=y - CONFIG_ZONE_DMA=y - CONFIG_VECTORS_BASE=0xffff0000 - CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -@@ -40,24 +41,24 @@ - # CONFIG_POSIX_MQUEUE is not set - # CONFIG_BSD_PROCESS_ACCT is not set - # CONFIG_TASKSTATS is not set --# CONFIG_USER_NS is not set --# CONFIG_PID_NS is not set - # CONFIG_AUDIT is not set - # CONFIG_IKCONFIG is not set - CONFIG_LOG_BUF_SHIFT=14 - # CONFIG_CGROUPS is not set --CONFIG_FAIR_GROUP_SCHED=y --CONFIG_FAIR_USER_SCHED=y --# CONFIG_FAIR_CGROUP_SCHED is not set -+# CONFIG_GROUP_SCHED is not set - CONFIG_SYSFS_DEPRECATED=y -+CONFIG_SYSFS_DEPRECATED_V2=y - # CONFIG_RELAY is not set -+# CONFIG_NAMESPACES is not set - # CONFIG_BLK_DEV_INITRD is not set - CONFIG_CC_OPTIMIZE_FOR_SIZE=y - CONFIG_SYSCTL=y - CONFIG_EMBEDDED=y - CONFIG_UID16=y - CONFIG_SYSCTL_SYSCALL=y -+CONFIG_SYSCTL_SYSCALL_CHECK=y - CONFIG_KALLSYMS=y -+CONFIG_KALLSYMS_ALL=y - # CONFIG_KALLSYMS_EXTRA_PASS is not set - CONFIG_HOTPLUG=y - CONFIG_PRINTK=y -@@ -73,20 +74,25 @@ - CONFIG_EVENTFD=y - CONFIG_SHMEM=y - CONFIG_VM_EVENT_COUNTERS=y --CONFIG_SLAB=y --# CONFIG_SLUB is not set -+# CONFIG_SLUB_DEBUG is not set -+# CONFIG_SLAB is not set -+CONFIG_SLUB=y - # CONFIG_SLOB is not set --# CONFIG_PROFILING is not set -+CONFIG_PROFILING=y - # CONFIG_MARKERS is not set -+CONFIG_OPROFILE=y - CONFIG_HAVE_OPROFILE=y --# CONFIG_KPROBES is not set -+CONFIG_KPROBES=y -+CONFIG_KRETPROBES=y - CONFIG_HAVE_KPROBES=y -+CONFIG_HAVE_KRETPROBES=y -+# CONFIG_HAVE_DMA_ATTRS is not set - CONFIG_PROC_PAGE_MONITOR=y --CONFIG_SLABINFO=y - CONFIG_RT_MUTEXES=y - # CONFIG_TINY_SHMEM is not set - CONFIG_BASE_SMALL=0 - CONFIG_MODULES=y -+# CONFIG_MODULE_FORCE_LOAD is not set - CONFIG_MODULE_UNLOAD=y - # CONFIG_MODULE_FORCE_UNLOAD is not set - # CONFIG_MODVERSIONS is not set -@@ -111,7 +117,6 @@ - # CONFIG_DEFAULT_NOOP is not set - CONFIG_DEFAULT_IOSCHED="cfq" - CONFIG_CLASSIC_RCU=y --# CONFIG_PREEMPT_RCU is not set - - # - # System Type -@@ -160,6 +165,7 @@ - CONFIG_MACH_KUROBOX_PRO=y - CONFIG_MACH_DNS323=y - CONFIG_MACH_TS209=y -+CONFIG_MACH_LINKSTATION_PRO=y - - # - # Boot options -@@ -168,6 +174,7 @@ - # - # Power management - # -+CONFIG_PLAT_ORION=y - - # - # Processor Type -@@ -177,8 +184,9 @@ - CONFIG_CPU_FEROCEON_OLD_ID=y - CONFIG_CPU_32v5=y - CONFIG_CPU_ABRT_EV5T=y -+CONFIG_CPU_PABRT_NOIFAR=y - CONFIG_CPU_CACHE_VIVT=y --CONFIG_CPU_COPY_V4WB=y -+CONFIG_CPU_COPY_FEROCEON=y - CONFIG_CPU_TLB_V4WBI=y - CONFIG_CPU_CP15=y - CONFIG_CPU_CP15_MMU=y -@@ -189,7 +197,6 @@ - CONFIG_ARM_THUMB=y - # CONFIG_CPU_ICACHE_DISABLE is not set - # CONFIG_CPU_DCACHE_DISABLE is not set --# CONFIG_CPU_DCACHE_WRITETHROUGH is not set - # CONFIG_OUTER_CACHE is not set - - # -@@ -199,6 +206,7 @@ - CONFIG_PCI_SYSCALL=y - # CONFIG_ARCH_SUPPORTS_MSI is not set - CONFIG_PCI_LEGACY=y -+# CONFIG_PCI_DEBUG is not set - # CONFIG_PCCARD is not set - - # -@@ -221,6 +229,7 @@ - CONFIG_FLAT_NODE_MEM_MAP=y - # CONFIG_SPARSEMEM_STATIC is not set - # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -+CONFIG_PAGEFLAGS_EXTENDED=y - CONFIG_SPLIT_PTLOCK_CPUS=4096 - # CONFIG_RESOURCES_64BIT is not set - CONFIG_ZONE_DMA_FLAG=1 -@@ -238,7 +247,6 @@ - CONFIG_CMDLINE="" - # CONFIG_XIP_KERNEL is not set - # CONFIG_KEXEC is not set --# CONFIG_ATAGS_PROC is not set - - # - # Floating point emulation -@@ -311,8 +319,6 @@ - CONFIG_DEFAULT_TCP_CONG="cubic" - # CONFIG_TCP_MD5SIG is not set - # CONFIG_IPV6 is not set --# CONFIG_INET6_XFRM_TUNNEL is not set --# CONFIG_INET6_TUNNEL is not set - # CONFIG_NETWORK_SECMARK is not set - # CONFIG_NETFILTER is not set - # CONFIG_IP_DCCP is not set -@@ -335,6 +341,7 @@ - # Network testing - # - CONFIG_NET_PKTGEN=m -+# CONFIG_NET_TCPPROBE is not set - # CONFIG_HAMRADIO is not set - # CONFIG_CAN is not set - # CONFIG_IRDA is not set -@@ -362,6 +369,8 @@ - CONFIG_STANDALONE=y - CONFIG_PREVENT_FIRMWARE_BUILD=y - CONFIG_FW_LOADER=y -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set - # CONFIG_SYS_HYPERVISOR is not set - # CONFIG_CONNECTOR is not set - CONFIG_MTD=y -@@ -371,6 +380,7 @@ - # CONFIG_MTD_REDBOOT_PARTS is not set - CONFIG_MTD_CMDLINE_PARTS=y - # CONFIG_MTD_AFS_PARTS is not set -+# CONFIG_MTD_AR7_PARTS is not set - - # - # User Modules And Translation Layers -@@ -378,9 +388,8 @@ - CONFIG_MTD_CHAR=y - CONFIG_MTD_BLKDEVS=y - CONFIG_MTD_BLOCK=y --CONFIG_FTL=y --CONFIG_NFTL=y --# CONFIG_NFTL_RW is not set -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set - # CONFIG_INFTL is not set - # CONFIG_RFD_FTL is not set - # CONFIG_SSFDC is not set -@@ -405,12 +414,12 @@ - # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set - CONFIG_MTD_CFI_I1=y - CONFIG_MTD_CFI_I2=y --CONFIG_MTD_CFI_I4=y -+# CONFIG_MTD_CFI_I4 is not set - # CONFIG_MTD_CFI_I8 is not set - # CONFIG_MTD_OTP is not set - CONFIG_MTD_CFI_INTELEXT=y - CONFIG_MTD_CFI_AMDSTD=y --CONFIG_MTD_CFI_STAA=y -+# CONFIG_MTD_CFI_STAA is not set - CONFIG_MTD_CFI_UTIL=y - # CONFIG_MTD_RAM is not set - # CONFIG_MTD_ROM is not set -@@ -481,6 +490,9 @@ - # CONFIG_EEPROM_93CX6 is not set - # CONFIG_SGI_IOC4 is not set - # CONFIG_TIFM_CORE is not set -+# CONFIG_ENCLOSURE_SERVICES is not set -+CONFIG_HAVE_IDE=y -+# CONFIG_IDE is not set - - # - # SCSI device support -@@ -542,6 +554,7 @@ - # CONFIG_SCSI_IPS is not set - # CONFIG_SCSI_INITIO is not set - # CONFIG_SCSI_INIA100 is not set -+# CONFIG_SCSI_MVSAS is not set - # CONFIG_SCSI_STEX is not set - # CONFIG_SCSI_SYM53C8XX_2 is not set - # CONFIG_SCSI_IPR is not set -@@ -556,7 +569,10 @@ - # CONFIG_SCSI_SRP is not set - CONFIG_ATA=y - # CONFIG_ATA_NONSTANDARD is not set -+CONFIG_SATA_PMP=y - # CONFIG_SATA_AHCI is not set -+# CONFIG_SATA_SIL24 is not set -+CONFIG_ATA_SFF=y - # CONFIG_SATA_SVW is not set - # CONFIG_ATA_PIIX is not set - CONFIG_SATA_MV=y -@@ -566,7 +582,6 @@ - # CONFIG_SATA_PROMISE is not set - # CONFIG_SATA_SX4 is not set - # CONFIG_SATA_SIL is not set --# CONFIG_SATA_SIL24 is not set - # CONFIG_SATA_SIS is not set - # CONFIG_SATA_ULI is not set - # CONFIG_SATA_VIA is not set -@@ -611,6 +626,7 @@ - # CONFIG_PATA_VIA is not set - # CONFIG_PATA_WINBOND is not set - # CONFIG_PATA_PLATFORM is not set -+# CONFIG_PATA_SCH is not set - # CONFIG_MD is not set - # CONFIG_FUSION is not set - -@@ -652,7 +668,7 @@ - # CONFIG_B44 is not set - # CONFIG_FORCEDETH is not set - # CONFIG_EEPRO100 is not set --CONFIG_E100=y -+# CONFIG_E100 is not set - # CONFIG_FEALNX is not set - # CONFIG_NATSEMI is not set - # CONFIG_NE2K_PCI is not set -@@ -668,9 +684,7 @@ - CONFIG_NETDEV_1000=y - # CONFIG_ACENIC is not set - # CONFIG_DL2K is not set --CONFIG_E1000=y --CONFIG_E1000_NAPI=y --# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set -+# CONFIG_E1000 is not set - # CONFIG_E1000E is not set - # CONFIG_E1000E_ENABLED is not set - # CONFIG_IP1000 is not set -@@ -680,27 +694,15 @@ - # CONFIG_YELLOWFIN is not set - # CONFIG_R8169 is not set - # CONFIG_SIS190 is not set --CONFIG_SKGE=y --CONFIG_SKY2=y --# CONFIG_SK98LIN is not set -+# CONFIG_SKGE is not set -+# CONFIG_SKY2 is not set - # CONFIG_VIA_VELOCITY is not set --CONFIG_TIGON3=y -+# CONFIG_TIGON3 is not set - # CONFIG_BNX2 is not set - CONFIG_MV643XX_ETH=y - # CONFIG_QLA3XXX is not set - # CONFIG_ATL1 is not set --CONFIG_NETDEV_10000=y --# CONFIG_CHELSIO_T1 is not set --# CONFIG_CHELSIO_T3 is not set --# CONFIG_IXGBE is not set --# CONFIG_IXGB is not set --# CONFIG_S2IO is not set --# CONFIG_MYRI10GE is not set --# CONFIG_NETXEN_NIC is not set --# CONFIG_NIU is not set --# CONFIG_MLX4_CORE is not set --# CONFIG_TEHUTI is not set --# CONFIG_BNX2X is not set -+# CONFIG_NETDEV_10000 is not set - # CONFIG_TR is not set - - # -@@ -708,6 +710,7 @@ - # - # CONFIG_WLAN_PRE80211 is not set - # CONFIG_WLAN_80211 is not set -+# CONFIG_IWLWIFI_LEDS is not set - - # - # USB Network Adapters -@@ -738,12 +741,9 @@ - # - # Userland interfaces - # --CONFIG_INPUT_MOUSEDEV=y --CONFIG_INPUT_MOUSEDEV_PSAUX=y --CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 --CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+# CONFIG_INPUT_MOUSEDEV is not set - # CONFIG_INPUT_JOYDEV is not set --# CONFIG_INPUT_EVDEV is not set -+CONFIG_INPUT_EVDEV=y - # CONFIG_INPUT_EVBUG is not set - - # -@@ -765,10 +765,8 @@ - # - # Character devices - # --CONFIG_VT=y --CONFIG_VT_CONSOLE=y --CONFIG_HW_CONSOLE=y --# CONFIG_VT_HW_CONSOLE_BINDING is not set -+# CONFIG_VT is not set -+CONFIG_DEVKMEM=y - # CONFIG_SERIAL_NONSTANDARD is not set - # CONFIG_NOZOMI is not set - -@@ -777,7 +775,7 @@ - # - CONFIG_SERIAL_8250=y - CONFIG_SERIAL_8250_CONSOLE=y --CONFIG_SERIAL_8250_PCI=y -+# CONFIG_SERIAL_8250_PCI is not set - CONFIG_SERIAL_8250_NR_UARTS=4 - CONFIG_SERIAL_8250_RUNTIME_UARTS=2 - # CONFIG_SERIAL_8250_EXTENDED is not set -@@ -792,7 +790,7 @@ - CONFIG_LEGACY_PTYS=y - CONFIG_LEGACY_PTY_COUNT=16 - # CONFIG_IPMI_HANDLER is not set --CONFIG_HW_RANDOM=m -+# CONFIG_HW_RANDOM is not set - # CONFIG_NVRAM is not set - # CONFIG_R3964 is not set - # CONFIG_APPLICOM is not set -@@ -804,13 +802,6 @@ - CONFIG_I2C_CHARDEV=y - - # --# I2C Algorithms --# --# CONFIG_I2C_ALGOBIT is not set --# CONFIG_I2C_ALGOPCF is not set --# CONFIG_I2C_ALGOPCA is not set -- --# - # I2C Hardware Bus support - # - # CONFIG_I2C_ALI1535 is not set -@@ -837,6 +828,7 @@ - # CONFIG_I2C_VIA is not set - # CONFIG_I2C_VIAPRO is not set - # CONFIG_I2C_VOODOO3 is not set -+# CONFIG_I2C_PCA_PLATFORM is not set - CONFIG_I2C_MV64XXX=y - - # -@@ -847,19 +839,13 @@ - # CONFIG_SENSORS_PCF8574 is not set - # CONFIG_PCF8575 is not set - # CONFIG_SENSORS_PCF8591 is not set --# CONFIG_TPS65010 is not set - # CONFIG_SENSORS_MAX6875 is not set - # CONFIG_SENSORS_TSL2550 is not set - # CONFIG_I2C_DEBUG_CORE is not set - # CONFIG_I2C_DEBUG_ALGO is not set - # CONFIG_I2C_DEBUG_BUS is not set - # CONFIG_I2C_DEBUG_CHIP is not set -- --# --# SPI support --# - # CONFIG_SPI is not set --# CONFIG_SPI_MASTER is not set - # CONFIG_W1 is not set - # CONFIG_POWER_SUPPLY is not set - CONFIG_HWMON=y -@@ -872,6 +858,7 @@ - # CONFIG_SENSORS_ADM1031 is not set - # CONFIG_SENSORS_ADM9240 is not set - # CONFIG_SENSORS_ADT7470 is not set -+# CONFIG_SENSORS_ADT7473 is not set - # CONFIG_SENSORS_ATXP1 is not set - # CONFIG_SENSORS_DS1621 is not set - # CONFIG_SENSORS_I5K_AMB is not set -@@ -901,6 +888,7 @@ - # CONFIG_SENSORS_SMSC47M1 is not set - # CONFIG_SENSORS_SMSC47M192 is not set - # CONFIG_SENSORS_SMSC47B397 is not set -+# CONFIG_SENSORS_ADS7828 is not set - # CONFIG_SENSORS_THMC50 is not set - # CONFIG_SENSORS_VIA686A is not set - # CONFIG_SENSORS_VT1211 is not set -@@ -910,6 +898,7 @@ - # CONFIG_SENSORS_W83792D is not set - # CONFIG_SENSORS_W83793 is not set - # CONFIG_SENSORS_W83L785TS is not set -+# CONFIG_SENSORS_W83L786NG is not set - # CONFIG_SENSORS_W83627HF is not set - # CONFIG_SENSORS_W83627EHF is not set - # CONFIG_HWMON_DEBUG_CHIP is not set -@@ -925,14 +914,24 @@ - # Multifunction device drivers - # - # CONFIG_MFD_SM501 is not set -+# CONFIG_MFD_ASIC3 is not set -+# CONFIG_HTC_PASIC3 is not set - - # - # Multimedia devices - # -+ -+# -+# Multimedia core support -+# - # CONFIG_VIDEO_DEV is not set - # CONFIG_DVB_CORE is not set --CONFIG_DAB=y --# CONFIG_USB_DABUSB is not set -+# CONFIG_VIDEO_MEDIA is not set -+ -+# -+# Multimedia drivers -+# -+# CONFIG_DAB is not set - - # - # Graphics support -@@ -949,12 +948,6 @@ - # CONFIG_DISPLAY_SUPPORT is not set - - # --# Console display driver support --# --# CONFIG_VGA_CONSOLE is not set --CONFIG_DUMMY_CONSOLE=y -- --# - # Sound - # - # CONFIG_SOUND is not set -@@ -985,14 +978,18 @@ - CONFIG_USB_DEVICE_CLASS=y - # CONFIG_USB_DYNAMIC_MINORS is not set - # CONFIG_USB_OTG is not set -+# CONFIG_USB_OTG_WHITELIST is not set -+# CONFIG_USB_OTG_BLACKLIST_HUB is not set - - # - # USB Host Controller Drivers - # -+# CONFIG_USB_C67X00_HCD is not set - CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_ROOT_HUB_TT=y - CONFIG_USB_EHCI_TT_NEWSCHED=y - # CONFIG_USB_ISP116X_HCD is not set -+# CONFIG_USB_ISP1760_HCD is not set - # CONFIG_USB_OHCI_HCD is not set - # CONFIG_USB_UHCI_HCD is not set - # CONFIG_USB_SL811_HCD is not set -@@ -1003,6 +1000,7 @@ - # - # CONFIG_USB_ACM is not set - CONFIG_USB_PRINTER=y -+# CONFIG_USB_WDM is not set - - # - # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -@@ -1022,7 +1020,9 @@ - CONFIG_USB_STORAGE_SDDR55=y - CONFIG_USB_STORAGE_JUMPSHOT=y - # CONFIG_USB_STORAGE_ALAUDA is not set -+# CONFIG_USB_STORAGE_ONETOUCH is not set - # CONFIG_USB_STORAGE_KARMA is not set -+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set - # CONFIG_USB_LIBUSUAL is not set - - # -@@ -1060,6 +1060,7 @@ - # CONFIG_USB_TRANCEVIBRATOR is not set - # CONFIG_USB_IOWARRIOR is not set - # CONFIG_USB_TEST is not set -+# CONFIG_USB_ISIGHTFW is not set - # CONFIG_USB_GADGET is not set - # CONFIG_MMC is not set - CONFIG_NEW_LEDS=y -@@ -1076,6 +1077,7 @@ - CONFIG_LEDS_TRIGGERS=y - CONFIG_LEDS_TRIGGER_TIMER=y - CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set - CONFIG_RTC_LIB=y - CONFIG_RTC_CLASS=y - CONFIG_RTC_HCTOSYS=y -@@ -1105,6 +1107,7 @@ - # CONFIG_RTC_DRV_PCF8583 is not set - CONFIG_RTC_DRV_M41T80=y - # CONFIG_RTC_DRV_M41T80_WDT is not set -+# CONFIG_RTC_DRV_S35390A is not set - - # - # SPI RTC drivers -@@ -1125,6 +1128,7 @@ - # - # on-CPU RTC drivers - # -+# CONFIG_UIO is not set - - # - # File systems -@@ -1140,14 +1144,11 @@ - # CONFIG_JFS_FS is not set - # CONFIG_FS_POSIX_ACL is not set - # CONFIG_XFS_FS is not set --# CONFIG_GFS2_FS is not set - # CONFIG_OCFS2_FS is not set --# CONFIG_MINIX_FS is not set --# CONFIG_ROMFS_FS is not set -+CONFIG_DNOTIFY=y - CONFIG_INOTIFY=y - CONFIG_INOTIFY_USER=y - # CONFIG_QUOTA is not set --CONFIG_DNOTIFY=y - # CONFIG_AUTOFS_FS is not set - # CONFIG_AUTOFS4_FS is not set - # CONFIG_FUSE_FS is not set -@@ -1155,8 +1156,8 @@ - # - # CD-ROM/DVD Filesystems - # --CONFIG_ISO9660_FS=y --# CONFIG_JOLIET is not set -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y - # CONFIG_ZISOFS is not set - CONFIG_UDF_FS=m - CONFIG_UDF_NLS=y -@@ -1205,8 +1206,10 @@ - # CONFIG_JFFS2_RUBIN is not set - CONFIG_CRAMFS=y - # CONFIG_VXFS_FS is not set -+# CONFIG_MINIX_FS is not set - # CONFIG_HPFS_FS is not set - # CONFIG_QNX4FS_FS is not set -+# CONFIG_ROMFS_FS is not set - # CONFIG_SYSV_FS is not set - # CONFIG_UFS_FS is not set - CONFIG_NETWORK_FILESYSTEMS=y -@@ -1214,7 +1217,6 @@ - CONFIG_NFS_V3=y - # CONFIG_NFS_V3_ACL is not set - # CONFIG_NFS_V4 is not set --# CONFIG_NFS_DIRECTIO is not set - # CONFIG_NFSD is not set - CONFIG_ROOT_NFS=y - CONFIG_LOCKD=y -@@ -1241,14 +1243,13 @@ - # CONFIG_MAC_PARTITION is not set - CONFIG_MSDOS_PARTITION=y - CONFIG_BSD_DISKLABEL=y --CONFIG_MINIX_SUBPARTITION=y --CONFIG_SOLARIS_X86_PARTITION=y --CONFIG_UNIXWARE_DISKLABEL=y --CONFIG_LDM_PARTITION=y --CONFIG_LDM_DEBUG=y -+# CONFIG_MINIX_SUBPARTITION is not set -+# CONFIG_SOLARIS_X86_PARTITION is not set -+# CONFIG_UNIXWARE_DISKLABEL is not set -+# CONFIG_LDM_PARTITION is not set - # CONFIG_SGI_PARTITION is not set - # CONFIG_ULTRIX_PARTITION is not set --CONFIG_SUN_PARTITION=y -+# CONFIG_SUN_PARTITION is not set - # CONFIG_KARMA_PARTITION is not set - # CONFIG_EFI_PARTITION is not set - # CONFIG_SYSV68_PARTITION is not set -@@ -1300,15 +1301,48 @@ - # CONFIG_PRINTK_TIME is not set - CONFIG_ENABLE_WARN_DEPRECATED=y - CONFIG_ENABLE_MUST_CHECK=y --# CONFIG_MAGIC_SYSRQ is not set -+CONFIG_FRAME_WARN=1024 -+CONFIG_MAGIC_SYSRQ=y - # CONFIG_UNUSED_SYMBOLS is not set - # CONFIG_DEBUG_FS is not set - # CONFIG_HEADERS_CHECK is not set --# CONFIG_DEBUG_KERNEL is not set -+CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set -+CONFIG_DETECT_SOFTLOCKUP=y -+CONFIG_SCHED_DEBUG=y -+CONFIG_SCHEDSTATS=y -+# CONFIG_TIMER_STATS is not set -+# CONFIG_DEBUG_OBJECTS is not set -+CONFIG_DEBUG_PREEMPT=y -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+# CONFIG_DEBUG_SPINLOCK is not set -+# CONFIG_DEBUG_MUTEXES is not set -+# CONFIG_DEBUG_LOCK_ALLOC is not set -+# CONFIG_PROVE_LOCKING is not set -+# CONFIG_LOCK_STAT is not set -+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_DEBUG_KOBJECT is not set - # CONFIG_DEBUG_BUGVERBOSE is not set -+CONFIG_DEBUG_INFO=y -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_WRITECOUNT is not set -+# CONFIG_DEBUG_LIST is not set -+# CONFIG_DEBUG_SG is not set - CONFIG_FRAME_POINTER=y -+# CONFIG_BOOT_PRINTK_DELAY is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_KPROBES_SANITY_TEST is not set -+# CONFIG_BACKTRACE_SELF_TEST is not set -+# CONFIG_LKDTM is not set -+# CONFIG_FAULT_INJECTION is not set - # CONFIG_SAMPLES is not set - CONFIG_DEBUG_USER=y -+CONFIG_DEBUG_ERRORS=y -+# CONFIG_DEBUG_STACK_USAGE is not set -+CONFIG_DEBUG_LL=y -+# CONFIG_DEBUG_ICEDCC is not set - - # - # Security options -@@ -1317,50 +1351,79 @@ - # CONFIG_SECURITY is not set - # CONFIG_SECURITY_FILE_CAPABILITIES is not set - CONFIG_CRYPTO=y -+ -+# -+# Crypto core or helper -+# - CONFIG_CRYPTO_ALGAPI=m - CONFIG_CRYPTO_BLKCIPHER=m --# CONFIG_CRYPTO_SEQIV is not set - CONFIG_CRYPTO_MANAGER=m -+# CONFIG_CRYPTO_GF128MUL is not set -+# CONFIG_CRYPTO_NULL is not set -+# CONFIG_CRYPTO_CRYPTD is not set -+# CONFIG_CRYPTO_AUTHENC is not set -+# CONFIG_CRYPTO_TEST is not set -+ -+# -+# Authenticated Encryption with Associated Data -+# -+# CONFIG_CRYPTO_CCM is not set -+# CONFIG_CRYPTO_GCM is not set -+# CONFIG_CRYPTO_SEQIV is not set -+ -+# -+# Block modes -+# -+CONFIG_CRYPTO_CBC=m -+# CONFIG_CRYPTO_CTR is not set -+# CONFIG_CRYPTO_CTS is not set -+CONFIG_CRYPTO_ECB=m -+# CONFIG_CRYPTO_LRW is not set -+CONFIG_CRYPTO_PCBC=m -+# CONFIG_CRYPTO_XTS is not set -+ -+# -+# Hash modes -+# - # CONFIG_CRYPTO_HMAC is not set - # CONFIG_CRYPTO_XCBC is not set --# CONFIG_CRYPTO_NULL is not set -+ -+# -+# Digest -+# -+# CONFIG_CRYPTO_CRC32C is not set - # CONFIG_CRYPTO_MD4 is not set - # CONFIG_CRYPTO_MD5 is not set -+# CONFIG_CRYPTO_MICHAEL_MIC is not set - # CONFIG_CRYPTO_SHA1 is not set - # CONFIG_CRYPTO_SHA256 is not set - # CONFIG_CRYPTO_SHA512 is not set --# CONFIG_CRYPTO_WP512 is not set - # CONFIG_CRYPTO_TGR192 is not set --# CONFIG_CRYPTO_GF128MUL is not set --CONFIG_CRYPTO_ECB=m --CONFIG_CRYPTO_CBC=m --CONFIG_CRYPTO_PCBC=m --# CONFIG_CRYPTO_LRW is not set --# CONFIG_CRYPTO_XTS is not set --# CONFIG_CRYPTO_CTR is not set --# CONFIG_CRYPTO_GCM is not set --# CONFIG_CRYPTO_CCM is not set --# CONFIG_CRYPTO_CRYPTD is not set --# CONFIG_CRYPTO_DES is not set --# CONFIG_CRYPTO_FCRYPT is not set --# CONFIG_CRYPTO_BLOWFISH is not set --# CONFIG_CRYPTO_TWOFISH is not set --# CONFIG_CRYPTO_SERPENT is not set -+# CONFIG_CRYPTO_WP512 is not set -+ -+# -+# Ciphers -+# - # CONFIG_CRYPTO_AES is not set -+# CONFIG_CRYPTO_ANUBIS is not set -+# CONFIG_CRYPTO_ARC4 is not set -+# CONFIG_CRYPTO_BLOWFISH is not set -+# CONFIG_CRYPTO_CAMELLIA is not set - # CONFIG_CRYPTO_CAST5 is not set - # CONFIG_CRYPTO_CAST6 is not set --# CONFIG_CRYPTO_TEA is not set --# CONFIG_CRYPTO_ARC4 is not set -+# CONFIG_CRYPTO_DES is not set -+# CONFIG_CRYPTO_FCRYPT is not set - # CONFIG_CRYPTO_KHAZAD is not set --# CONFIG_CRYPTO_ANUBIS is not set --# CONFIG_CRYPTO_SEED is not set - # CONFIG_CRYPTO_SALSA20 is not set -+# CONFIG_CRYPTO_SEED is not set -+# CONFIG_CRYPTO_SERPENT is not set -+# CONFIG_CRYPTO_TEA is not set -+# CONFIG_CRYPTO_TWOFISH is not set -+ -+# -+# Compression -+# - # CONFIG_CRYPTO_DEFLATE is not set --# CONFIG_CRYPTO_MICHAEL_MIC is not set --# CONFIG_CRYPTO_CRC32C is not set --# CONFIG_CRYPTO_CAMELLIA is not set --# CONFIG_CRYPTO_TEST is not set --# CONFIG_CRYPTO_AUTHENC is not set - # CONFIG_CRYPTO_LZO is not set - CONFIG_CRYPTO_HW=y - # CONFIG_CRYPTO_DEV_HIFN_795X is not set -@@ -1369,12 +1432,14 @@ - # Library routines - # - CONFIG_BITREVERSE=y --CONFIG_CRC_CCITT=y --CONFIG_CRC16=y --# CONFIG_CRC_ITU_T is not set -+# CONFIG_GENERIC_FIND_FIRST_BIT is not set -+# CONFIG_GENERIC_FIND_NEXT_BIT is not set -+# CONFIG_CRC_CCITT is not set -+# CONFIG_CRC16 is not set -+CONFIG_CRC_ITU_T=m - CONFIG_CRC32=y - # CONFIG_CRC7 is not set --CONFIG_LIBCRC32C=y -+# CONFIG_LIBCRC32C is not set - CONFIG_ZLIB_INFLATE=y - CONFIG_ZLIB_DEFLATE=y - CONFIG_PLIST=y ---- a/arch/arm/kernel/stacktrace.c -+++ b/arch/arm/kernel/stacktrace.c -@@ -36,6 +36,7 @@ - #ifdef CONFIG_STACKTRACE - struct stack_trace_data { - struct stack_trace *trace; -+ unsigned int no_sched_functions; - unsigned int skip; - }; - -@@ -43,27 +44,52 @@ - { - struct stack_trace_data *data = d; - struct stack_trace *trace = data->trace; -+ unsigned long addr = frame->lr; - -+ if (data->no_sched_functions && in_sched_functions(addr)) -+ return 0; - if (data->skip) { - data->skip--; - return 0; - } - -- trace->entries[trace->nr_entries++] = frame->lr; -+ trace->entries[trace->nr_entries++] = addr; - - return trace->nr_entries >= trace->max_entries; - } - --void save_stack_trace(struct stack_trace *trace) -+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) - { - struct stack_trace_data data; - unsigned long fp, base; - - data.trace = trace; - data.skip = trace->skip; -- base = (unsigned long)task_stack_page(current); -- asm("mov %0, fp" : "=r" (fp)); -+ base = (unsigned long)task_stack_page(tsk); -+ -+ if (tsk != current) { -+#ifdef CONFIG_SMP -+ /* -+ * What guarantees do we have here that 'tsk' -+ * is not running on another CPU? -+ */ -+ BUG(); -+#else -+ data.no_sched_functions = 1; -+ fp = thread_saved_fp(tsk); -+#endif -+ } else { -+ data.no_sched_functions = 0; -+ asm("mov %0, fp" : "=r" (fp)); -+ } - - walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data); -+ if (trace->nr_entries < trace->max_entries) -+ trace->entries[trace->nr_entries++] = ULONG_MAX; -+} -+ -+void save_stack_trace(struct stack_trace *trace) -+{ -+ save_stack_trace_tsk(current, trace); - } - #endif ---- a/arch/arm/lib/copy_template.S -+++ b/arch/arm/lib/copy_template.S -@@ -13,14 +13,6 @@ - */ - - /* -- * This can be used to enable code to cacheline align the source pointer. -- * Experiments on tested architectures (StrongARM and XScale) didn't show -- * this a worthwhile thing to do. That might be different in the future. -- */ --//#define CALGN(code...) code --#define CALGN(code...) -- --/* - * Theory of operation - * ------------------- - * -@@ -82,7 +74,7 @@ - stmfd sp!, {r5 - r8} - blt 5f - -- CALGN( ands ip, r1, #31 ) -+ CALGN( ands ip, r0, #31 ) - CALGN( rsb r3, ip, #32 ) - CALGN( sbcnes r4, r3, r2 ) @ C is always set here - CALGN( bcs 2f ) -@@ -168,7 +160,7 @@ - subs r2, r2, #28 - blt 14f - -- CALGN( ands ip, r1, #31 ) -+ CALGN( ands ip, r0, #31 ) - CALGN( rsb ip, ip, #32 ) - CALGN( sbcnes r4, ip, r2 ) @ C is always set here - CALGN( subcc r2, r2, ip ) ---- a/arch/arm/lib/memmove.S -+++ b/arch/arm/lib/memmove.S -@@ -13,14 +13,6 @@ - #include - #include - --/* -- * This can be used to enable code to cacheline align the source pointer. -- * Experiments on tested architectures (StrongARM and XScale) didn't show -- * this a worthwhile thing to do. That might be different in the future. -- */ --//#define CALGN(code...) code --#define CALGN(code...) -- - .text - - /* -@@ -55,11 +47,12 @@ - stmfd sp!, {r5 - r8} - blt 5f - -- CALGN( ands ip, r1, #31 ) -+ CALGN( ands ip, r0, #31 ) - CALGN( sbcnes r4, ip, r2 ) @ C is always set here - CALGN( bcs 2f ) - CALGN( adr r4, 6f ) - CALGN( subs r2, r2, ip ) @ C is set here -+ CALGN( rsb ip, ip, #32 ) - CALGN( add pc, r4, ip ) - - PLD( pld [r1, #-4] ) -@@ -138,8 +131,7 @@ - subs r2, r2, #28 - blt 14f - -- CALGN( ands ip, r1, #31 ) -- CALGN( rsb ip, ip, #32 ) -+ CALGN( ands ip, r0, #31 ) - CALGN( sbcnes r4, ip, r2 ) @ C is always set here - CALGN( subcc r2, r2, ip ) - CALGN( bcc 15f ) ---- a/arch/arm/lib/memset.S -+++ b/arch/arm/lib/memset.S -@@ -39,6 +39,9 @@ - mov r3, r1 - cmp r2, #16 - blt 4f -+ -+#if ! CALGN(1)+0 -+ - /* - * We need an extra register for this loop - save the return address and - * use the LR -@@ -64,6 +67,49 @@ - stmneia r0!, {r1, r3, ip, lr} - ldr lr, [sp], #4 - -+#else -+ -+/* -+ * This version aligns the destination pointer in order to write -+ * whole cache lines at once. -+ */ -+ -+ stmfd sp!, {r4-r7, lr} -+ mov r4, r1 -+ mov r5, r1 -+ mov r6, r1 -+ mov r7, r1 -+ mov ip, r1 -+ mov lr, r1 -+ -+ cmp r2, #96 -+ tstgt r0, #31 -+ ble 3f -+ -+ and ip, r0, #31 -+ rsb ip, ip, #32 -+ sub r2, r2, ip -+ movs ip, ip, lsl #(32 - 4) -+ stmcsia r0!, {r4, r5, r6, r7} -+ stmmiia r0!, {r4, r5} -+ tst ip, #(1 << 30) -+ mov ip, r1 -+ strne r1, [r0], #4 -+ -+3: subs r2, r2, #64 -+ stmgeia r0!, {r1, r3-r7, ip, lr} -+ stmgeia r0!, {r1, r3-r7, ip, lr} -+ bgt 3b -+ ldmeqfd sp!, {r4-r7, pc} -+ -+ tst r2, #32 -+ stmneia r0!, {r1, r3-r7, ip, lr} -+ tst r2, #16 -+ stmneia r0!, {r4-r7} -+ ldmfd sp!, {r4-r7, lr} -+ -+#endif -+ - 4: tst r2, #8 - stmneia r0!, {r1, r3} - tst r2, #4 ---- a/arch/arm/lib/memzero.S -+++ b/arch/arm/lib/memzero.S -@@ -39,6 +39,9 @@ - */ - cmp r1, #16 @ 1 we can skip this chunk if we - blt 4f @ 1 have < 16 bytes -+ -+#if ! CALGN(1)+0 -+ - /* - * We need an extra register for this loop - save the return address and - * use the LR -@@ -64,6 +67,47 @@ - stmneia r0!, {r2, r3, ip, lr} @ 4 - ldr lr, [sp], #4 @ 1 - -+#else -+ -+/* -+ * This version aligns the destination pointer in order to write -+ * whole cache lines at once. -+ */ -+ -+ stmfd sp!, {r4-r7, lr} -+ mov r4, r2 -+ mov r5, r2 -+ mov r6, r2 -+ mov r7, r2 -+ mov ip, r2 -+ mov lr, r2 -+ -+ cmp r1, #96 -+ andgts ip, r0, #31 -+ ble 3f -+ -+ rsb ip, ip, #32 -+ sub r1, r1, ip -+ movs ip, ip, lsl #(32 - 4) -+ stmcsia r0!, {r4, r5, r6, r7} -+ stmmiia r0!, {r4, r5} -+ movs ip, ip, lsl #2 -+ strcs r2, [r0], #4 -+ -+3: subs r1, r1, #64 -+ stmgeia r0!, {r2-r7, ip, lr} -+ stmgeia r0!, {r2-r7, ip, lr} -+ bgt 3b -+ ldmeqfd sp!, {r4-r7, pc} -+ -+ tst r1, #32 -+ stmneia r0!, {r2-r7, ip, lr} -+ tst r1, #16 -+ stmneia r0!, {r4-r7} -+ ldmfd sp!, {r4-r7, lr} -+ -+#endif -+ - 4: tst r1, #8 @ 1 8 bytes or more? - stmneia r0!, {r2, r3} @ 2 - tst r1, #4 @ 1 4 bytes or more? ---- /dev/null -+++ b/arch/arm/mach-kirkwood/Kconfig -@@ -0,0 +1,25 @@ -+if ARCH_KIRKWOOD -+ -+menu "Marvell Kirkwood Implementations" -+ -+config MACH_DB88F6281_BP -+ bool "Marvell DB-88F6281-BP Development Board" -+ help -+ Say 'Y' here if you want your kernel to support the -+ Marvell DB-88F6281-BP Development Board. -+ -+config MACH_RD88F6192_NAS -+ bool "Marvell RD-88F6192-NAS Reference Board" -+ help -+ Say 'Y' here if you want your kernel to support the -+ Marvell RD-88F6192-NAS Reference Board. -+ -+config MACH_RD88F6281 -+ bool "Marvell RD-88F6281 Reference Board" -+ help -+ Say 'Y' here if you want your kernel to support the -+ Marvell RD-88F6281 Reference Board. -+ -+endmenu -+ -+endif ---- /dev/null -+++ b/arch/arm/mach-kirkwood/Makefile -@@ -0,0 +1,5 @@ -+obj-y += common.o addr-map.o irq.o pcie.o -+ -+obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o -+obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o -+obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6281-setup.o ---- /dev/null -+++ b/arch/arm/mach-kirkwood/Makefile.boot -@@ -0,0 +1,3 @@ -+ zreladdr-y := 0x00008000 -+params_phys-y := 0x00000100 -+initrd_phys-y := 0x00800000 ---- /dev/null -+++ b/arch/arm/mach-kirkwood/addr-map.c -@@ -0,0 +1,139 @@ -+/* -+ * arch/arm/mach-kirkwood/addr-map.c -+ * -+ * Address map functions for Marvell Kirkwood SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+/* -+ * Generic Address Decode Windows bit settings -+ */ -+#define TARGET_DDR 0 -+#define TARGET_DEV_BUS 1 -+#define TARGET_PCIE 4 -+#define ATTR_DEV_SPI_ROM 0x1e -+#define ATTR_DEV_BOOT 0x1d -+#define ATTR_DEV_NAND 0x2f -+#define ATTR_DEV_CS3 0x37 -+#define ATTR_DEV_CS2 0x3b -+#define ATTR_DEV_CS1 0x3d -+#define ATTR_DEV_CS0 0x3e -+#define ATTR_PCIE_IO 0xe0 -+#define ATTR_PCIE_MEM 0xe8 -+ -+/* -+ * Helpers to get DDR bank info -+ */ -+#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -+#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) -+ -+/* -+ * CPU Address Decode Windows registers -+ */ -+#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) -+#define WIN_CTRL_OFF 0x0000 -+#define WIN_BASE_OFF 0x0004 -+#define WIN_REMAP_LO_OFF 0x0008 -+#define WIN_REMAP_HI_OFF 0x000c -+ -+ -+struct mbus_dram_target_info kirkwood_mbus_dram_info; -+ -+static int __init cpu_win_can_remap(int win) -+{ -+ if (win < 4) -+ return 1; -+ -+ return 0; -+} -+ -+static void __init setup_cpu_win(int win, u32 base, u32 size, -+ u8 target, u8 attr, int remap) -+{ -+ void __iomem *addr = (void __iomem *)WIN_OFF(win); -+ u32 ctrl; -+ -+ base &= 0xffff0000; -+ ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; -+ -+ writel(base, addr + WIN_BASE_OFF); -+ writel(ctrl, addr + WIN_CTRL_OFF); -+ if (cpu_win_can_remap(win)) { -+ if (remap < 0) -+ remap = base; -+ -+ writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); -+ writel(0, addr + WIN_REMAP_HI_OFF); -+ } -+} -+ -+void __init kirkwood_setup_cpu_mbus(void) -+{ -+ void __iomem *addr; -+ int i; -+ int cs; -+ -+ /* -+ * First, disable and clear windows. -+ */ -+ for (i = 0; i < 8; i++) { -+ addr = (void __iomem *)WIN_OFF(i); -+ -+ writel(0, addr + WIN_BASE_OFF); -+ writel(0, addr + WIN_CTRL_OFF); -+ if (cpu_win_can_remap(i)) { -+ writel(0, addr + WIN_REMAP_LO_OFF); -+ writel(0, addr + WIN_REMAP_HI_OFF); -+ } -+ } -+ -+ /* -+ * Setup windows for PCIe IO+MEM space. -+ */ -+ setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, -+ TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); -+ setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, -+ TARGET_PCIE, ATTR_PCIE_MEM, -1); -+ -+ /* -+ * Setup window for NAND controller. -+ */ -+ setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, -+ TARGET_DEV_BUS, ATTR_DEV_NAND, -1); -+ -+ /* -+ * Setup MBUS dram target info. -+ */ -+ kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; -+ -+ addr = (void __iomem *)DDR_WINDOW_CPU_BASE; -+ -+ for (i = 0, cs = 0; i < 4; i++) { -+ u32 base = readl(addr + DDR_BASE_CS_OFF(i)); -+ u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); -+ -+ /* -+ * Chip select enabled? -+ */ -+ if (size & 1) { -+ struct mbus_dram_window *w; -+ -+ w = &kirkwood_mbus_dram_info.cs[cs++]; -+ w->cs_index = i; -+ w->mbus_attr = 0xf & ~(1 << i); -+ w->base = base & 0xffff0000; -+ w->size = (size | 0x0000ffff) + 1; -+ } -+ } -+ kirkwood_mbus_dram_info.num_cs = cs; -+} ---- /dev/null -+++ b/arch/arm/mach-kirkwood/common.c -@@ -0,0 +1,326 @@ -+/* -+ * arch/arm/mach-kirkwood/common.c -+ * -+ * Core functions for Marvell Kirkwood SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+/***************************************************************************** -+ * I/O Address Mapping -+ ****************************************************************************/ -+static struct map_desc kirkwood_io_desc[] __initdata = { -+ { -+ .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, -+ .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), -+ .length = KIRKWOOD_PCIE_IO_SIZE, -+ .type = MT_DEVICE, -+ }, { -+ .virtual = KIRKWOOD_REGS_VIRT_BASE, -+ .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), -+ .length = KIRKWOOD_REGS_SIZE, -+ .type = MT_DEVICE, -+ }, -+}; -+ -+void __init kirkwood_map_io(void) -+{ -+ iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); -+} -+ -+ -+/***************************************************************************** -+ * EHCI -+ ****************************************************************************/ -+static struct orion_ehci_data kirkwood_ehci_data = { -+ .dram = &kirkwood_mbus_dram_info, -+}; -+ -+static u64 ehci_dmamask = 0xffffffffUL; -+ -+ -+/***************************************************************************** -+ * EHCI0 -+ ****************************************************************************/ -+static struct resource kirkwood_ehci_resources[] = { -+ { -+ .start = USB_PHYS_BASE, -+ .end = USB_PHYS_BASE + 0x0fff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_KIRKWOOD_USB, -+ .end = IRQ_KIRKWOOD_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device kirkwood_ehci = { -+ .name = "orion-ehci", -+ .id = 0, -+ .dev = { -+ .dma_mask = &ehci_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &kirkwood_ehci_data, -+ }, -+ .resource = kirkwood_ehci_resources, -+ .num_resources = ARRAY_SIZE(kirkwood_ehci_resources), -+}; -+ -+void __init kirkwood_ehci_init(void) -+{ -+ platform_device_register(&kirkwood_ehci); -+} -+ -+ -+/***************************************************************************** -+ * GE00 -+ ****************************************************************************/ -+struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = { -+ .t_clk = KIRKWOOD_TCLK, -+ .dram = &kirkwood_mbus_dram_info, -+}; -+ -+static struct resource kirkwood_ge00_shared_resources[] = { -+ { -+ .name = "ge00 base", -+ .start = GE00_PHYS_BASE + 0x2000, -+ .end = GE00_PHYS_BASE + 0x3fff, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device kirkwood_ge00_shared = { -+ .name = MV643XX_ETH_SHARED_NAME, -+ .id = 0, -+ .dev = { -+ .platform_data = &kirkwood_ge00_shared_data, -+ }, -+ .num_resources = 1, -+ .resource = kirkwood_ge00_shared_resources, -+}; -+ -+static struct resource kirkwood_ge00_resources[] = { -+ { -+ .name = "ge00 irq", -+ .start = IRQ_KIRKWOOD_GE00_SUM, -+ .end = IRQ_KIRKWOOD_GE00_SUM, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device kirkwood_ge00 = { -+ .name = MV643XX_ETH_NAME, -+ .id = 0, -+ .num_resources = 1, -+ .resource = kirkwood_ge00_resources, -+}; -+ -+void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) -+{ -+ eth_data->shared = &kirkwood_ge00_shared; -+ kirkwood_ge00.dev.platform_data = eth_data; -+ -+ platform_device_register(&kirkwood_ge00_shared); -+ platform_device_register(&kirkwood_ge00); -+} -+ -+ -+/***************************************************************************** -+ * SoC RTC -+ ****************************************************************************/ -+static struct resource kirkwood_rtc_resource = { -+ .start = RTC_PHYS_BASE, -+ .end = RTC_PHYS_BASE + SZ_16 - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+void __init kirkwood_rtc_init(void) -+{ -+ platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); -+} -+ -+ -+/***************************************************************************** -+ * SATA -+ ****************************************************************************/ -+static struct resource kirkwood_sata_resources[] = { -+ { -+ .name = "sata base", -+ .start = SATA_PHYS_BASE, -+ .end = SATA_PHYS_BASE + 0x5000 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .name = "sata irq", -+ .start = IRQ_KIRKWOOD_SATA, -+ .end = IRQ_KIRKWOOD_SATA, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device kirkwood_sata = { -+ .name = "sata_mv", -+ .id = 0, -+ .dev = { -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .num_resources = ARRAY_SIZE(kirkwood_sata_resources), -+ .resource = kirkwood_sata_resources, -+}; -+ -+void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) -+{ -+ sata_data->dram = &kirkwood_mbus_dram_info; -+ kirkwood_sata.dev.platform_data = sata_data; -+ platform_device_register(&kirkwood_sata); -+} -+ -+ -+/***************************************************************************** -+ * UART0 -+ ****************************************************************************/ -+static struct plat_serial8250_port kirkwood_uart0_data[] = { -+ { -+ .mapbase = UART0_PHYS_BASE, -+ .membase = (char *)UART0_VIRT_BASE, -+ .irq = IRQ_KIRKWOOD_UART_0, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = KIRKWOOD_TCLK, -+ }, { -+ }, -+}; -+ -+static struct resource kirkwood_uart0_resources[] = { -+ { -+ .start = UART0_PHYS_BASE, -+ .end = UART0_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_KIRKWOOD_UART_0, -+ .end = IRQ_KIRKWOOD_UART_0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device kirkwood_uart0 = { -+ .name = "serial8250", -+ .id = 0, -+ .dev = { -+ .platform_data = kirkwood_uart0_data, -+ }, -+ .resource = kirkwood_uart0_resources, -+ .num_resources = ARRAY_SIZE(kirkwood_uart0_resources), -+}; -+ -+void __init kirkwood_uart0_init(void) -+{ -+ platform_device_register(&kirkwood_uart0); -+} -+ -+ -+/***************************************************************************** -+ * UART1 -+ ****************************************************************************/ -+static struct plat_serial8250_port kirkwood_uart1_data[] = { -+ { -+ .mapbase = UART1_PHYS_BASE, -+ .membase = (char *)UART1_VIRT_BASE, -+ .irq = IRQ_KIRKWOOD_UART_1, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = KIRKWOOD_TCLK, -+ }, { -+ }, -+}; -+ -+static struct resource kirkwood_uart1_resources[] = { -+ { -+ .start = UART1_PHYS_BASE, -+ .end = UART1_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_KIRKWOOD_UART_1, -+ .end = IRQ_KIRKWOOD_UART_1, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device kirkwood_uart1 = { -+ .name = "serial8250", -+ .id = 1, -+ .dev = { -+ .platform_data = kirkwood_uart1_data, -+ }, -+ .resource = kirkwood_uart1_resources, -+ .num_resources = ARRAY_SIZE(kirkwood_uart1_resources), -+}; -+ -+void __init kirkwood_uart1_init(void) -+{ -+ platform_device_register(&kirkwood_uart1); -+} -+ -+ -+/***************************************************************************** -+ * Time handling -+ ****************************************************************************/ -+static void kirkwood_timer_init(void) -+{ -+ orion_time_init(IRQ_KIRKWOOD_BRIDGE, KIRKWOOD_TCLK); -+} -+ -+struct sys_timer kirkwood_timer = { -+ .init = kirkwood_timer_init, -+}; -+ -+ -+/***************************************************************************** -+ * General -+ ****************************************************************************/ -+static char * __init kirkwood_id(void) -+{ -+ switch (readl(DEVICE_ID) & 0x3) { -+ case 0: -+ return "88F6180"; -+ case 1: -+ return "88F6192"; -+ case 2: -+ return "88F6281"; -+ } -+ -+ return "unknown 88F6000 variant"; -+} -+ -+void __init kirkwood_init(void) -+{ -+ printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", -+ kirkwood_id(), KIRKWOOD_TCLK); -+ -+ kirkwood_setup_cpu_mbus(); -+ -+#ifdef CONFIG_CACHE_FEROCEON_L2 -+ feroceon_l2_init(1); -+#endif -+} ---- /dev/null -+++ b/arch/arm/mach-kirkwood/common.h -@@ -0,0 +1,42 @@ -+/* -+ * arch/arm/mach-kirkwood/common.h -+ * -+ * Core functions for Marvell Kirkwood SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ARCH_KIRKWOOD_COMMON_H -+#define __ARCH_KIRKWOOD_COMMON_H -+ -+struct mv643xx_eth_platform_data; -+struct mv_sata_platform_data; -+ -+/* -+ * Basic Kirkwood init functions used early by machine-setup. -+ */ -+void kirkwood_map_io(void); -+void kirkwood_init(void); -+void kirkwood_init_irq(void); -+ -+extern struct mbus_dram_target_info kirkwood_mbus_dram_info; -+void kirkwood_setup_cpu_mbus(void); -+void kirkwood_setup_pcie_io_win(int window, u32 base, u32 size, -+ int maj, int min); -+void kirkwood_setup_pcie_mem_win(int window, u32 base, u32 size, -+ int maj, int min); -+ -+void kirkwood_ehci_init(void); -+void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); -+void kirkwood_pcie_init(void); -+void kirkwood_rtc_init(void); -+void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); -+void kirkwood_uart0_init(void); -+void kirkwood_uart1_init(void); -+ -+extern struct sys_timer kirkwood_timer; -+ -+ -+#endif ---- /dev/null -+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c -@@ -0,0 +1,68 @@ -+/* -+ * arch/arm/mach-kirkwood/db88f6281-bp-setup.c -+ * -+ * Marvell DB-88F6281-BP Development Board Setup -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+static struct mv643xx_eth_platform_data db88f6281_ge00_data = { -+ .phy_addr = 8, -+}; -+ -+static struct mv_sata_platform_data db88f6281_sata_data = { -+ .n_ports = 2, -+}; -+ -+static void __init db88f6281_init(void) -+{ -+ /* -+ * Basic setup. Needs to be called early. -+ */ -+ kirkwood_init(); -+ -+ kirkwood_ehci_init(); -+ kirkwood_ge00_init(&db88f6281_ge00_data); -+ kirkwood_rtc_init(); -+ kirkwood_sata_init(&db88f6281_sata_data); -+ kirkwood_uart0_init(); -+ kirkwood_uart1_init(); -+} -+ -+static int __init db88f6281_pci_init(void) -+{ -+ if (machine_is_db88f6281_bp()) -+ kirkwood_pcie_init(); -+ -+ return 0; -+} -+subsys_initcall(db88f6281_pci_init); -+ -+MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board") -+ /* Maintainer: Saeed Bishara */ -+ .phys_io = KIRKWOOD_REGS_PHYS_BASE, -+ .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, -+ .boot_params = 0x00000100, -+ .init_machine = db88f6281_init, -+ .map_io = kirkwood_map_io, -+ .init_irq = kirkwood_init_irq, -+ .timer = &kirkwood_timer, -+MACHINE_END ---- /dev/null -+++ b/arch/arm/mach-kirkwood/irq.c -@@ -0,0 +1,22 @@ -+/* -+ * arch/arm/mach-kirkwood/irq.c -+ * -+ * Kirkwood IRQ handling. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+void __init kirkwood_init_irq(void) -+{ -+ orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); -+ orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); -+} ---- /dev/null -+++ b/arch/arm/mach-kirkwood/pcie.c -@@ -0,0 +1,180 @@ -+/* -+ * arch/arm/mach-kirkwood/pcie.c -+ * -+ * PCIe functions for Marvell Kirkwood SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+ -+#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE) -+ -+static int pcie_valid_config(int bus, int dev) -+{ -+ /* -+ * Don't go out when trying to access -- -+ * 1. nonexisting device on local bus -+ * 2. where there's no device connected (no link) -+ */ -+ if (bus == 0 && dev == 0) -+ return 1; -+ -+ if (!orion_pcie_link_up(PCIE_BASE)) -+ return 0; -+ -+ if (bus == 0 && dev != 1) -+ return 0; -+ -+ return 1; -+} -+ -+ -+/* -+ * PCIe config cycles are done by programming the PCIE_CONF_ADDR register -+ * and then reading the PCIE_CONF_DATA register. Need to make sure these -+ * transactions are atomic. -+ */ -+static DEFINE_SPINLOCK(kirkwood_pcie_lock); -+ -+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, -+ int size, u32 *val) -+{ -+ unsigned long flags; -+ int ret; -+ -+ if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { -+ *val = 0xffffffff; -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ } -+ -+ spin_lock_irqsave(&kirkwood_pcie_lock, flags); -+ ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); -+ spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); -+ -+ return ret; -+} -+ -+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, -+ int where, int size, u32 val) -+{ -+ unsigned long flags; -+ int ret; -+ -+ if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ spin_lock_irqsave(&kirkwood_pcie_lock, flags); -+ ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); -+ spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); -+ -+ return ret; -+} -+ -+static struct pci_ops pcie_ops = { -+ .read = pcie_rd_conf, -+ .write = pcie_wr_conf, -+}; -+ -+ -+static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) -+{ -+ struct resource *res; -+ -+ /* -+ * Generic PCIe unit setup. -+ */ -+ orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info); -+ -+ /* -+ * Request resources. -+ */ -+ res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); -+ if (!res) -+ panic("pcie_setup unable to alloc resources"); -+ -+ /* -+ * IORESOURCE_IO -+ */ -+ res[0].name = "PCIe I/O Space"; -+ res[0].flags = IORESOURCE_IO; -+ res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE; -+ res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; -+ if (request_resource(&ioport_resource, &res[0])) -+ panic("Request PCIe IO resource failed\n"); -+ sys->resource[0] = &res[0]; -+ -+ /* -+ * IORESOURCE_MEM -+ */ -+ res[1].name = "PCIe Memory Space"; -+ res[1].flags = IORESOURCE_MEM; -+ res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; -+ res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; -+ if (request_resource(&iomem_resource, &res[1])) -+ panic("Request PCIe Memory resource failed\n"); -+ sys->resource[1] = &res[1]; -+ -+ sys->resource[2] = NULL; -+ sys->io_offset = 0; -+ -+ return 1; -+} -+ -+static void __devinit rc_pci_fixup(struct pci_dev *dev) -+{ -+ /* -+ * Prevent enumeration of root complex. -+ */ -+ if (dev->bus->parent == NULL && dev->devfn == 0) { -+ int i; -+ -+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { -+ dev->resource[i].start = 0; -+ dev->resource[i].end = 0; -+ dev->resource[i].flags = 0; -+ } -+ } -+} -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); -+ -+static struct pci_bus __init * -+kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) -+{ -+ struct pci_bus *bus; -+ -+ if (nr == 0) { -+ bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); -+ } else { -+ bus = NULL; -+ BUG(); -+ } -+ -+ return bus; -+} -+ -+static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ return IRQ_KIRKWOOD_PCIE; -+} -+ -+static struct hw_pci kirkwood_pci __initdata = { -+ .nr_controllers = 1, -+ .swizzle = pci_std_swizzle, -+ .setup = kirkwood_pcie_setup, -+ .scan = kirkwood_pcie_scan_bus, -+ .map_irq = kirkwood_pcie_map_irq, -+}; -+ -+void __init kirkwood_pcie_init(void) -+{ -+ pci_common_init(&kirkwood_pci); -+} ---- /dev/null -+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c -@@ -0,0 +1,69 @@ -+/* -+ * arch/arm/mach-kirkwood/rd88f6192-nas-setup.c -+ * -+ * Marvell RD-88F6192-NAS Reference Board Setup -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+#define RD88F6192_GPIO_USB_VBUS 10 -+ -+static struct mv643xx_eth_platform_data rd88f6192_ge00_data = { -+ .phy_addr = 8, -+}; -+ -+static struct mv_sata_platform_data rd88f6192_sata_data = { -+ .n_ports = 2, -+}; -+ -+static void __init rd88f6192_init(void) -+{ -+ /* -+ * Basic setup. Needs to be called early. -+ */ -+ kirkwood_init(); -+ -+ kirkwood_ehci_init(); -+ kirkwood_ge00_init(&rd88f6192_ge00_data); -+ kirkwood_rtc_init(); -+ kirkwood_sata_init(&rd88f6192_sata_data); -+ kirkwood_uart0_init(); -+} -+ -+static int __init rd88f6192_pci_init(void) -+{ -+ if (machine_is_rd88f6192_nas()) -+ kirkwood_pcie_init(); -+ -+ return 0; -+} -+subsys_initcall(rd88f6192_pci_init); -+ -+MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board") -+ /* Maintainer: Saeed Bishara */ -+ .phys_io = KIRKWOOD_REGS_PHYS_BASE, -+ .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, -+ .boot_params = 0x00000100, -+ .init_machine = rd88f6192_init, -+ .map_io = kirkwood_map_io, -+ .init_irq = kirkwood_init_irq, -+ .timer = &kirkwood_timer, -+MACHINE_END ---- /dev/null -+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c -@@ -0,0 +1,112 @@ -+/* -+ * arch/arm/mach-kirkwood/rd88f6281-setup.c -+ * -+ * Marvell RD-88F6281 Reference Board Setup -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+static struct mtd_partition rd88f6281_nand_parts[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = SZ_1M -+ }, { -+ .name = "uImage", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = SZ_2M -+ }, { -+ .name = "root", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL -+ }, -+}; -+ -+static struct resource rd88f6281_nand_resource = { -+ .flags = IORESOURCE_MEM, -+ .start = KIRKWOOD_NAND_MEM_PHYS_BASE, -+ .end = KIRKWOOD_NAND_MEM_PHYS_BASE + -+ KIRKWOOD_NAND_MEM_SIZE - 1, -+}; -+ -+static struct orion_nand_data rd88f6281_nand_data = { -+ .parts = rd88f6281_nand_parts, -+ .nr_parts = ARRAY_SIZE(rd88f6281_nand_parts), -+ .cle = 0, -+ .ale = 1, -+ .width = 8, -+}; -+ -+static struct platform_device rd88f6281_nand_flash = { -+ .name = "orion_nand", -+ .id = -1, -+ .dev = { -+ .platform_data = &rd88f6281_nand_data, -+ }, -+ .resource = &rd88f6281_nand_resource, -+ .num_resources = 1, -+}; -+ -+static struct mv643xx_eth_platform_data rd88f6281_ge00_data = { -+ .phy_addr = -1, -+}; -+ -+static struct mv_sata_platform_data rd88f6281_sata_data = { -+ .n_ports = 2, -+}; -+ -+static void __init rd88f6281_init(void) -+{ -+ /* -+ * Basic setup. Needs to be called early. -+ */ -+ kirkwood_init(); -+ -+ kirkwood_ehci_init(); -+ kirkwood_ge00_init(&rd88f6281_ge00_data); -+ kirkwood_rtc_init(); -+ kirkwood_sata_init(&rd88f6281_sata_data); -+ kirkwood_uart0_init(); -+ kirkwood_uart1_init(); -+ -+ platform_device_register(&rd88f6281_nand_flash); -+} -+ -+static int __init rd88f6281_pci_init(void) -+{ -+ if (machine_is_rd88f6281()) -+ kirkwood_pcie_init(); -+ -+ return 0; -+} -+subsys_initcall(rd88f6281_pci_init); -+ -+MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board") -+ /* Maintainer: Saeed Bishara */ -+ .phys_io = KIRKWOOD_REGS_PHYS_BASE, -+ .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, -+ .boot_params = 0x00000100, -+ .init_machine = rd88f6281_init, -+ .map_io = kirkwood_map_io, -+ .init_irq = kirkwood_init_irq, -+ .timer = &kirkwood_timer, -+MACHINE_END ---- /dev/null -+++ b/arch/arm/mach-loki/Kconfig -@@ -0,0 +1,13 @@ -+if ARCH_LOKI -+ -+menu "Marvell Loki (88RC8480) Implementations" -+ -+config MACH_LB88RC8480 -+ bool "Marvell LB88RC8480 Development Board" -+ help -+ Say 'Y' here if you want your kernel to support the -+ Marvell LB88RC8480 Development Board. -+ -+endmenu -+ -+endif ---- /dev/null -+++ b/arch/arm/mach-loki/Makefile -@@ -0,0 +1,3 @@ -+obj-y += common.o addr-map.o irq.o -+ -+obj-$(CONFIG_MACH_LB88RC8480) += lb88rc8480-setup.o ---- /dev/null -+++ b/arch/arm/mach-loki/Makefile.boot -@@ -0,0 +1,3 @@ -+ zreladdr-y := 0x00008000 -+params_phys-y := 0x00000100 -+initrd_phys-y := 0x00800000 ---- /dev/null -+++ b/arch/arm/mach-loki/addr-map.c -@@ -0,0 +1,121 @@ -+/* -+ * arch/arm/mach-loki/addr-map.c -+ * -+ * Address map functions for Marvell Loki (88RC8480) SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+/* -+ * Generic Address Decode Windows bit settings -+ */ -+#define TARGET_DDR 0 -+#define TARGET_DEV_BUS 1 -+#define TARGET_PCIE0 3 -+#define TARGET_PCIE1 4 -+#define ATTR_DEV_BOOT 0x0f -+#define ATTR_DEV_CS2 0x1b -+#define ATTR_DEV_CS1 0x1d -+#define ATTR_DEV_CS0 0x1e -+#define ATTR_PCIE_IO 0x51 -+#define ATTR_PCIE_MEM 0x59 -+ -+/* -+ * Helpers to get DDR bank info -+ */ -+#define DDR_SIZE_CS(n) DDR_REG(0x1500 + ((n) << 3)) -+#define DDR_BASE_CS(n) DDR_REG(0x1504 + ((n) << 3)) -+ -+/* -+ * CPU Address Decode Windows registers -+ */ -+#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4)) -+#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4)) -+#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4)) -+#define CPU_WIN_REMAP_HI(n) BRIDGE_REG(0x00c | ((n) << 4)) -+ -+ -+struct mbus_dram_target_info loki_mbus_dram_info; -+ -+static void __init setup_cpu_win(int win, u32 base, u32 size, -+ u8 target, u8 attr, int remap) -+{ -+ u32 ctrl; -+ -+ base &= 0xffff0000; -+ ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target; -+ -+ writel(base, CPU_WIN_BASE(win)); -+ writel(ctrl, CPU_WIN_CTRL(win)); -+ if (win < 2) { -+ if (remap < 0) -+ remap = base; -+ -+ writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); -+ writel(0, CPU_WIN_REMAP_HI(win)); -+ } -+} -+ -+void __init loki_setup_cpu_mbus(void) -+{ -+ int i; -+ int cs; -+ -+ /* -+ * First, disable and clear windows. -+ */ -+ for (i = 0; i < 8; i++) { -+ writel(0, CPU_WIN_BASE(i)); -+ writel(0, CPU_WIN_CTRL(i)); -+ if (i < 2) { -+ writel(0, CPU_WIN_REMAP_LO(i)); -+ writel(0, CPU_WIN_REMAP_HI(i)); -+ } -+ } -+ -+ /* -+ * Setup windows for PCIe IO+MEM space. -+ */ -+ setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE, -+ TARGET_PCIE0, ATTR_PCIE_MEM, -1); -+ setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE, -+ TARGET_PCIE1, ATTR_PCIE_MEM, -1); -+ -+ /* -+ * Setup MBUS dram target info. -+ */ -+ loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; -+ -+ for (i = 0, cs = 0; i < 4; i++) { -+ u32 base = readl(DDR_BASE_CS(i)); -+ u32 size = readl(DDR_SIZE_CS(i)); -+ -+ /* -+ * Chip select enabled? -+ */ -+ if (size & 1) { -+ struct mbus_dram_window *w; -+ -+ w = &loki_mbus_dram_info.cs[cs++]; -+ w->cs_index = i; -+ w->mbus_attr = 0xf & ~(1 << i); -+ w->base = base & 0xffff0000; -+ w->size = (size | 0x0000ffff) + 1; -+ } -+ } -+ loki_mbus_dram_info.num_cs = cs; -+} -+ -+void __init loki_setup_dev_boot_win(u32 base, u32 size) -+{ -+ setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); -+} ---- /dev/null -+++ b/arch/arm/mach-loki/common.c -@@ -0,0 +1,305 @@ -+/* -+ * arch/arm/mach-loki/common.c -+ * -+ * Core functions for Marvell Loki (88RC8480) SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+/***************************************************************************** -+ * I/O Address Mapping -+ ****************************************************************************/ -+static struct map_desc loki_io_desc[] __initdata = { -+ { -+ .virtual = LOKI_REGS_VIRT_BASE, -+ .pfn = __phys_to_pfn(LOKI_REGS_PHYS_BASE), -+ .length = LOKI_REGS_SIZE, -+ .type = MT_DEVICE, -+ }, -+}; -+ -+void __init loki_map_io(void) -+{ -+ iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc)); -+} -+ -+ -+/***************************************************************************** -+ * GE0 -+ ****************************************************************************/ -+struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = { -+ .t_clk = LOKI_TCLK, -+ .dram = &loki_mbus_dram_info, -+}; -+ -+static struct resource loki_ge0_shared_resources[] = { -+ { -+ .name = "ge0 base", -+ .start = GE0_PHYS_BASE + 0x2000, -+ .end = GE0_PHYS_BASE + 0x3fff, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device loki_ge0_shared = { -+ .name = MV643XX_ETH_SHARED_NAME, -+ .id = 0, -+ .dev = { -+ .platform_data = &loki_ge0_shared_data, -+ }, -+ .num_resources = 1, -+ .resource = loki_ge0_shared_resources, -+}; -+ -+static struct resource loki_ge0_resources[] = { -+ { -+ .name = "ge0 irq", -+ .start = IRQ_LOKI_GBE_A_INT, -+ .end = IRQ_LOKI_GBE_A_INT, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device loki_ge0 = { -+ .name = MV643XX_ETH_NAME, -+ .id = 0, -+ .num_resources = 1, -+ .resource = loki_ge0_resources, -+}; -+ -+void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data) -+{ -+ eth_data->shared = &loki_ge0_shared; -+ loki_ge0.dev.platform_data = eth_data; -+ -+ writel(0x00079220, GE0_VIRT_BASE + 0x20b0); -+ platform_device_register(&loki_ge0_shared); -+ platform_device_register(&loki_ge0); -+} -+ -+ -+/***************************************************************************** -+ * GE1 -+ ****************************************************************************/ -+struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = { -+ .t_clk = LOKI_TCLK, -+ .dram = &loki_mbus_dram_info, -+}; -+ -+static struct resource loki_ge1_shared_resources[] = { -+ { -+ .name = "ge1 base", -+ .start = GE1_PHYS_BASE + 0x2000, -+ .end = GE1_PHYS_BASE + 0x3fff, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device loki_ge1_shared = { -+ .name = MV643XX_ETH_SHARED_NAME, -+ .id = 1, -+ .dev = { -+ .platform_data = &loki_ge1_shared_data, -+ }, -+ .num_resources = 1, -+ .resource = loki_ge1_shared_resources, -+}; -+ -+static struct resource loki_ge1_resources[] = { -+ { -+ .name = "ge1 irq", -+ .start = IRQ_LOKI_GBE_B_INT, -+ .end = IRQ_LOKI_GBE_B_INT, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device loki_ge1 = { -+ .name = MV643XX_ETH_NAME, -+ .id = 1, -+ .num_resources = 1, -+ .resource = loki_ge1_resources, -+}; -+ -+void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data) -+{ -+ eth_data->shared = &loki_ge1_shared; -+ loki_ge1.dev.platform_data = eth_data; -+ -+ writel(0x00079220, GE1_VIRT_BASE + 0x20b0); -+ platform_device_register(&loki_ge1_shared); -+ platform_device_register(&loki_ge1); -+} -+ -+ -+/***************************************************************************** -+ * SAS/SATA -+ ****************************************************************************/ -+static struct resource loki_sas_resources[] = { -+ { -+ .name = "mvsas0 mem", -+ .start = SAS0_PHYS_BASE, -+ .end = SAS0_PHYS_BASE + 0x01ff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .name = "mvsas0 irq", -+ .start = IRQ_LOKI_SAS_A, -+ .end = IRQ_LOKI_SAS_A, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .name = "mvsas1 mem", -+ .start = SAS1_PHYS_BASE, -+ .end = SAS1_PHYS_BASE + 0x01ff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .name = "mvsas1 irq", -+ .start = IRQ_LOKI_SAS_B, -+ .end = IRQ_LOKI_SAS_B, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device loki_sas = { -+ .name = "mvsas", -+ .id = 0, -+ .dev = { -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .num_resources = ARRAY_SIZE(loki_sas_resources), -+ .resource = loki_sas_resources, -+}; -+ -+void __init loki_sas_init(void) -+{ -+ writel(0x8300f707, DDR_REG(0x1424)); -+ platform_device_register(&loki_sas); -+} -+ -+ -+/***************************************************************************** -+ * UART0 -+ ****************************************************************************/ -+static struct plat_serial8250_port loki_uart0_data[] = { -+ { -+ .mapbase = UART0_PHYS_BASE, -+ .membase = (char *)UART0_VIRT_BASE, -+ .irq = IRQ_LOKI_UART0, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = LOKI_TCLK, -+ }, { -+ }, -+}; -+ -+static struct resource loki_uart0_resources[] = { -+ { -+ .start = UART0_PHYS_BASE, -+ .end = UART0_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_LOKI_UART0, -+ .end = IRQ_LOKI_UART0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device loki_uart0 = { -+ .name = "serial8250", -+ .id = 0, -+ .dev = { -+ .platform_data = loki_uart0_data, -+ }, -+ .resource = loki_uart0_resources, -+ .num_resources = ARRAY_SIZE(loki_uart0_resources), -+}; -+ -+void __init loki_uart0_init(void) -+{ -+ platform_device_register(&loki_uart0); -+} -+ -+ -+/***************************************************************************** -+ * UART1 -+ ****************************************************************************/ -+static struct plat_serial8250_port loki_uart1_data[] = { -+ { -+ .mapbase = UART1_PHYS_BASE, -+ .membase = (char *)UART1_VIRT_BASE, -+ .irq = IRQ_LOKI_UART1, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = LOKI_TCLK, -+ }, { -+ }, -+}; -+ -+static struct resource loki_uart1_resources[] = { -+ { -+ .start = UART1_PHYS_BASE, -+ .end = UART1_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_LOKI_UART1, -+ .end = IRQ_LOKI_UART1, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device loki_uart1 = { -+ .name = "serial8250", -+ .id = 1, -+ .dev = { -+ .platform_data = loki_uart1_data, -+ }, -+ .resource = loki_uart1_resources, -+ .num_resources = ARRAY_SIZE(loki_uart1_resources), -+}; -+ -+void __init loki_uart1_init(void) -+{ -+ platform_device_register(&loki_uart1); -+} -+ -+ -+/***************************************************************************** -+ * Time handling -+ ****************************************************************************/ -+static void loki_timer_init(void) -+{ -+ orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK); -+} -+ -+struct sys_timer loki_timer = { -+ .init = loki_timer_init, -+}; -+ -+ -+/***************************************************************************** -+ * General -+ ****************************************************************************/ -+void __init loki_init(void) -+{ -+ printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK); -+ -+ loki_setup_cpu_mbus(); -+} ---- /dev/null -+++ b/arch/arm/mach-loki/common.h -@@ -0,0 +1,36 @@ -+/* -+ * arch/arm/mach-loki/common.h -+ * -+ * Core functions for Marvell Loki (88RC8480) SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ARCH_LOKI_COMMON_H -+#define __ARCH_LOKI_COMMON_H -+ -+struct mv643xx_eth_platform_data; -+ -+/* -+ * Basic Loki init functions used early by machine-setup. -+ */ -+void loki_map_io(void); -+void loki_init(void); -+void loki_init_irq(void); -+ -+extern struct mbus_dram_target_info loki_mbus_dram_info; -+void loki_setup_cpu_mbus(void); -+void loki_setup_dev_boot_win(u32 base, u32 size); -+ -+void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data); -+void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data); -+void loki_sas_init(void); -+void loki_uart0_init(void); -+void loki_uart1_init(void); -+ -+extern struct sys_timer loki_timer; -+ -+ -+#endif ---- /dev/null -+++ b/arch/arm/mach-loki/irq.c -@@ -0,0 +1,21 @@ -+/* -+ * arch/arm/mach-loki/irq.c -+ * -+ * Marvell Loki (88RC8480) IRQ handling. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+void __init loki_init_irq(void) -+{ -+ orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF)); -+} ---- /dev/null -+++ b/arch/arm/mach-loki/lb88rc8480-setup.c -@@ -0,0 +1,100 @@ -+/* -+ * arch/arm/mach-loki/lb88rc8480-setup.c -+ * -+ * Marvell LB88RC8480 Development Board Setup -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+#define LB88RC8480_FLASH_BOOT_CS_BASE 0xf8000000 -+#define LB88RC8480_FLASH_BOOT_CS_SIZE SZ_128M -+ -+#define LB88RC8480_NOR_BOOT_BASE 0xff000000 -+#define LB88RC8480_NOR_BOOT_SIZE SZ_16M -+ -+static struct mtd_partition lb88rc8480_boot_flash_parts[] = { -+ { -+ .name = "kernel", -+ .offset = 0, -+ .size = SZ_2M, -+ }, { -+ .name = "root-fs", -+ .offset = SZ_2M, -+ .size = (SZ_8M + SZ_4M + SZ_1M), -+ }, { -+ .name = "u-boot", -+ .offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M), -+ .size = SZ_1M, -+ }, -+}; -+ -+static struct physmap_flash_data lb88rc8480_boot_flash_data = { -+ .parts = lb88rc8480_boot_flash_parts, -+ .nr_parts = ARRAY_SIZE(lb88rc8480_boot_flash_parts), -+ .width = 1, /* 8 bit bus width */ -+}; -+ -+static struct resource lb88rc8480_boot_flash_resource = { -+ .flags = IORESOURCE_MEM, -+ .start = LB88RC8480_NOR_BOOT_BASE, -+ .end = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1, -+}; -+ -+static struct platform_device lb88rc8480_boot_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev = { -+ .platform_data = &lb88rc8480_boot_flash_data, -+ }, -+ .num_resources = 1, -+ .resource = &lb88rc8480_boot_flash_resource, -+}; -+ -+static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = { -+ .phy_addr = 1, -+ .mac_addr = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 }, -+}; -+ -+static void __init lb88rc8480_init(void) -+{ -+ /* -+ * Basic setup. Needs to be called early. -+ */ -+ loki_init(); -+ -+ loki_ge0_init(&lb88rc8480_ge0_data); -+ loki_sas_init(); -+ loki_uart0_init(); -+ loki_uart1_init(); -+ -+ loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE, -+ LB88RC8480_FLASH_BOOT_CS_SIZE); -+ platform_device_register(&lb88rc8480_boot_flash); -+} -+ -+MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board") -+ /* Maintainer: Ke Wei */ -+ .phys_io = LOKI_REGS_PHYS_BASE, -+ .io_pg_offst = ((LOKI_REGS_VIRT_BASE) >> 18) & 0xfffc, -+ .boot_params = 0x00000100, -+ .init_machine = lb88rc8480_init, -+ .map_io = loki_map_io, -+ .init_irq = loki_init_irq, -+ .timer = &loki_timer, -+MACHINE_END ---- /dev/null -+++ b/arch/arm/mach-mv78xx0/Kconfig -@@ -0,0 +1,13 @@ -+if ARCH_MV78XX0 -+ -+menu "Marvell MV78xx0 Implementations" -+ -+config MACH_DB78X00_BP -+ bool "Marvell DB-78x00-BP Development Board" -+ help -+ Say 'Y' here if you want your kernel to support the -+ Marvell DB-78x00-BP Development Board. -+ -+endmenu -+ -+endif ---- /dev/null -+++ b/arch/arm/mach-mv78xx0/Makefile -@@ -0,0 +1,2 @@ -+obj-y += common.o addr-map.o irq.o pcie.o -+obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o ---- /dev/null -+++ b/arch/arm/mach-mv78xx0/Makefile.boot -@@ -0,0 +1,3 @@ -+ zreladdr-y := 0x00008000 -+params_phys-y := 0x00000100 -+initrd_phys-y := 0x00800000 ---- /dev/null -+++ b/arch/arm/mach-mv78xx0/addr-map.c -@@ -0,0 +1,156 @@ -+/* -+ * arch/arm/mach-mv78xx0/addr-map.c -+ * -+ * Address map functions for Marvell MV78xx0 SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+/* -+ * Generic Address Decode Windows bit settings -+ */ -+#define TARGET_DDR 0 -+#define TARGET_DEV_BUS 1 -+#define TARGET_PCIE0 4 -+#define TARGET_PCIE1 8 -+#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0) -+#define ATTR_DEV_SPI_ROM 0x1f -+#define ATTR_DEV_BOOT 0x2f -+#define ATTR_DEV_CS3 0x37 -+#define ATTR_DEV_CS2 0x3b -+#define ATTR_DEV_CS1 0x3d -+#define ATTR_DEV_CS0 0x3e -+#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l))) -+#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) -+ -+/* -+ * Helpers to get DDR bank info -+ */ -+#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -+#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) -+ -+/* -+ * CPU Address Decode Windows registers -+ */ -+#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) -+#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) -+#define WIN_CTRL_OFF 0x0000 -+#define WIN_BASE_OFF 0x0004 -+#define WIN_REMAP_LO_OFF 0x0008 -+#define WIN_REMAP_HI_OFF 0x000c -+ -+ -+struct mbus_dram_target_info mv78xx0_mbus_dram_info; -+ -+static void __init __iomem *win_cfg_base(int win) -+{ -+ /* -+ * Find the control register base address for this window. -+ * -+ * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's) -+ * MBUS bridge depending on which CPU core we're running on, -+ * so we don't need to take that into account here. -+ */ -+ -+ return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); -+} -+ -+static int __init cpu_win_can_remap(int win) -+{ -+ if (win < 8) -+ return 1; -+ -+ return 0; -+} -+ -+static void __init setup_cpu_win(int win, u32 base, u32 size, -+ u8 target, u8 attr, int remap) -+{ -+ void __iomem *addr = win_cfg_base(win); -+ u32 ctrl; -+ -+ base &= 0xffff0000; -+ ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; -+ -+ writel(base, addr + WIN_BASE_OFF); -+ writel(ctrl, addr + WIN_CTRL_OFF); -+ if (cpu_win_can_remap(win)) { -+ if (remap < 0) -+ remap = base; -+ -+ writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); -+ writel(0, addr + WIN_REMAP_HI_OFF); -+ } -+} -+ -+void __init mv78xx0_setup_cpu_mbus(void) -+{ -+ void __iomem *addr; -+ int i; -+ int cs; -+ -+ /* -+ * First, disable and clear windows. -+ */ -+ for (i = 0; i < 14; i++) { -+ addr = win_cfg_base(i); -+ -+ writel(0, addr + WIN_BASE_OFF); -+ writel(0, addr + WIN_CTRL_OFF); -+ if (cpu_win_can_remap(i)) { -+ writel(0, addr + WIN_REMAP_LO_OFF); -+ writel(0, addr + WIN_REMAP_HI_OFF); -+ } -+ } -+ -+ /* -+ * Setup MBUS dram target info. -+ */ -+ mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; -+ -+ if (mv78xx0_core_index() == 0) -+ addr = (void __iomem *)DDR_WINDOW_CPU0_BASE; -+ else -+ addr = (void __iomem *)DDR_WINDOW_CPU1_BASE; -+ -+ for (i = 0, cs = 0; i < 4; i++) { -+ u32 base = readl(addr + DDR_BASE_CS_OFF(i)); -+ u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); -+ -+ /* -+ * Chip select enabled? -+ */ -+ if (size & 1) { -+ struct mbus_dram_window *w; -+ -+ w = &mv78xx0_mbus_dram_info.cs[cs++]; -+ w->cs_index = i; -+ w->mbus_attr = 0xf & ~(1 << i); -+ w->base = base & 0xffff0000; -+ w->size = (size | 0x0000ffff) + 1; -+ } -+ } -+ mv78xx0_mbus_dram_info.num_cs = cs; -+} -+ -+void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, -+ int maj, int min) -+{ -+ setup_cpu_win(window, base, size, TARGET_PCIE(maj), -+ ATTR_PCIE_IO(min), -1); -+} -+ -+void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, -+ int maj, int min) -+{ -+ setup_cpu_win(window, base, size, TARGET_PCIE(maj), -+ ATTR_PCIE_MEM(min), -1); -+} ---- /dev/null -+++ b/arch/arm/mach-mv78xx0/common.c -@@ -0,0 +1,754 @@ -+/* -+ * arch/arm/mach-mv78xx0/common.c -+ * -+ * Core functions for Marvell MV78xx0 SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+ -+/***************************************************************************** -+ * Common bits -+ ****************************************************************************/ -+int mv78xx0_core_index(void) -+{ -+ u32 extra; -+ -+ /* -+ * Read Extra Features register. -+ */ -+ __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); -+ -+ return !!(extra & 0x00004000); -+} -+ -+static int get_hclk(void) -+{ -+ int hclk; -+ -+ /* -+ * HCLK tick rate is configured by DEV_D[7:5] pins. -+ */ -+ switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { -+ case 0: -+ hclk = 166666667; -+ break; -+ case 1: -+ hclk = 200000000; -+ break; -+ case 2: -+ hclk = 266666667; -+ break; -+ case 3: -+ hclk = 333333333; -+ break; -+ case 4: -+ hclk = 400000000; -+ break; -+ default: -+ panic("unknown HCLK PLL setting: %.8x\n", -+ readl(SAMPLE_AT_RESET_LOW)); -+ } -+ -+ return hclk; -+} -+ -+static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) -+{ -+ u32 cfg; -+ -+ /* -+ * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 -+ * PCLK/L2CLK by bits [19:14]. -+ */ -+ if (core_index == 0) { -+ cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; -+ } else { -+ cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; -+ } -+ -+ /* -+ * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK -+ * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6). -+ */ -+ *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; -+ -+ /* -+ * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK -+ * ratio (1, 2, 3). -+ */ -+ *l2clk = *pclk / (((cfg >> 4) & 3) + 1); -+} -+ -+static int get_tclk(void) -+{ -+ int tclk; -+ -+ /* -+ * TCLK tick rate is configured by DEV_A[2:0] strap pins. -+ */ -+ switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { -+ case 1: -+ tclk = 166666667; -+ break; -+ case 3: -+ tclk = 200000000; -+ break; -+ default: -+ panic("unknown TCLK PLL setting: %.8x\n", -+ readl(SAMPLE_AT_RESET_HIGH)); -+ } -+ -+ return tclk; -+} -+ -+ -+/***************************************************************************** -+ * I/O Address Mapping -+ ****************************************************************************/ -+static struct map_desc mv78xx0_io_desc[] __initdata = { -+ { -+ .virtual = MV78XX0_CORE_REGS_VIRT_BASE, -+ .pfn = 0, -+ .length = MV78XX0_CORE_REGS_SIZE, -+ .type = MT_DEVICE, -+ }, { -+ .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), -+ .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), -+ .length = MV78XX0_PCIE_IO_SIZE * 8, -+ .type = MT_DEVICE, -+ }, { -+ .virtual = MV78XX0_REGS_VIRT_BASE, -+ .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), -+ .length = MV78XX0_REGS_SIZE, -+ .type = MT_DEVICE, -+ }, -+}; -+ -+void __init mv78xx0_map_io(void) -+{ -+ unsigned long phys; -+ -+ /* -+ * Map the right set of per-core registers depending on -+ * which core we are running on. -+ */ -+ if (mv78xx0_core_index() == 0) { -+ phys = MV78XX0_CORE0_REGS_PHYS_BASE; -+ } else { -+ phys = MV78XX0_CORE1_REGS_PHYS_BASE; -+ } -+ mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys); -+ -+ iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc)); -+} -+ -+ -+/***************************************************************************** -+ * EHCI -+ ****************************************************************************/ -+static struct orion_ehci_data mv78xx0_ehci_data = { -+ .dram = &mv78xx0_mbus_dram_info, -+}; -+ -+static u64 ehci_dmamask = 0xffffffffUL; -+ -+ -+/***************************************************************************** -+ * EHCI0 -+ ****************************************************************************/ -+static struct resource mv78xx0_ehci0_resources[] = { -+ { -+ .start = USB0_PHYS_BASE, -+ .end = USB0_PHYS_BASE + 0x0fff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_MV78XX0_USB_0, -+ .end = IRQ_MV78XX0_USB_0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ehci0 = { -+ .name = "orion-ehci", -+ .id = 0, -+ .dev = { -+ .dma_mask = &ehci_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &mv78xx0_ehci_data, -+ }, -+ .resource = mv78xx0_ehci0_resources, -+ .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources), -+}; -+ -+void __init mv78xx0_ehci0_init(void) -+{ -+ platform_device_register(&mv78xx0_ehci0); -+} -+ -+ -+/***************************************************************************** -+ * EHCI1 -+ ****************************************************************************/ -+static struct resource mv78xx0_ehci1_resources[] = { -+ { -+ .start = USB1_PHYS_BASE, -+ .end = USB1_PHYS_BASE + 0x0fff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_MV78XX0_USB_1, -+ .end = IRQ_MV78XX0_USB_1, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ehci1 = { -+ .name = "orion-ehci", -+ .id = 1, -+ .dev = { -+ .dma_mask = &ehci_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &mv78xx0_ehci_data, -+ }, -+ .resource = mv78xx0_ehci1_resources, -+ .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources), -+}; -+ -+void __init mv78xx0_ehci1_init(void) -+{ -+ platform_device_register(&mv78xx0_ehci1); -+} -+ -+ -+/***************************************************************************** -+ * EHCI2 -+ ****************************************************************************/ -+static struct resource mv78xx0_ehci2_resources[] = { -+ { -+ .start = USB2_PHYS_BASE, -+ .end = USB2_PHYS_BASE + 0x0fff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_MV78XX0_USB_2, -+ .end = IRQ_MV78XX0_USB_2, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ehci2 = { -+ .name = "orion-ehci", -+ .id = 2, -+ .dev = { -+ .dma_mask = &ehci_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = &mv78xx0_ehci_data, -+ }, -+ .resource = mv78xx0_ehci2_resources, -+ .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources), -+}; -+ -+void __init mv78xx0_ehci2_init(void) -+{ -+ platform_device_register(&mv78xx0_ehci2); -+} -+ -+ -+/***************************************************************************** -+ * GE00 -+ ****************************************************************************/ -+struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = { -+ .t_clk = 0, -+ .dram = &mv78xx0_mbus_dram_info, -+}; -+ -+static struct resource mv78xx0_ge00_shared_resources[] = { -+ { -+ .name = "ge00 base", -+ .start = GE00_PHYS_BASE + 0x2000, -+ .end = GE00_PHYS_BASE + 0x3fff, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ge00_shared = { -+ .name = MV643XX_ETH_SHARED_NAME, -+ .id = 0, -+ .dev = { -+ .platform_data = &mv78xx0_ge00_shared_data, -+ }, -+ .num_resources = 1, -+ .resource = mv78xx0_ge00_shared_resources, -+}; -+ -+static struct resource mv78xx0_ge00_resources[] = { -+ { -+ .name = "ge00 irq", -+ .start = IRQ_MV78XX0_GE00_SUM, -+ .end = IRQ_MV78XX0_GE00_SUM, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ge00 = { -+ .name = MV643XX_ETH_NAME, -+ .id = 0, -+ .num_resources = 1, -+ .resource = mv78xx0_ge00_resources, -+}; -+ -+void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) -+{ -+ eth_data->shared = &mv78xx0_ge00_shared; -+ mv78xx0_ge00.dev.platform_data = eth_data; -+ -+ platform_device_register(&mv78xx0_ge00_shared); -+ platform_device_register(&mv78xx0_ge00); -+} -+ -+ -+/***************************************************************************** -+ * GE01 -+ ****************************************************************************/ -+struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = { -+ .t_clk = 0, -+ .dram = &mv78xx0_mbus_dram_info, -+}; -+ -+static struct resource mv78xx0_ge01_shared_resources[] = { -+ { -+ .name = "ge01 base", -+ .start = GE01_PHYS_BASE + 0x2000, -+ .end = GE01_PHYS_BASE + 0x3fff, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ge01_shared = { -+ .name = MV643XX_ETH_SHARED_NAME, -+ .id = 1, -+ .dev = { -+ .platform_data = &mv78xx0_ge01_shared_data, -+ }, -+ .num_resources = 1, -+ .resource = mv78xx0_ge01_shared_resources, -+}; -+ -+static struct resource mv78xx0_ge01_resources[] = { -+ { -+ .name = "ge01 irq", -+ .start = IRQ_MV78XX0_GE01_SUM, -+ .end = IRQ_MV78XX0_GE01_SUM, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ge01 = { -+ .name = MV643XX_ETH_NAME, -+ .id = 1, -+ .num_resources = 1, -+ .resource = mv78xx0_ge01_resources, -+}; -+ -+void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) -+{ -+ eth_data->shared = &mv78xx0_ge01_shared; -+ eth_data->shared_smi = &mv78xx0_ge00_shared; -+ mv78xx0_ge01.dev.platform_data = eth_data; -+ -+ platform_device_register(&mv78xx0_ge01_shared); -+ platform_device_register(&mv78xx0_ge01); -+} -+ -+ -+/***************************************************************************** -+ * GE10 -+ ****************************************************************************/ -+struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = { -+ .t_clk = 0, -+ .dram = &mv78xx0_mbus_dram_info, -+}; -+ -+static struct resource mv78xx0_ge10_shared_resources[] = { -+ { -+ .name = "ge10 base", -+ .start = GE10_PHYS_BASE + 0x2000, -+ .end = GE10_PHYS_BASE + 0x3fff, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ge10_shared = { -+ .name = MV643XX_ETH_SHARED_NAME, -+ .id = 2, -+ .dev = { -+ .platform_data = &mv78xx0_ge10_shared_data, -+ }, -+ .num_resources = 1, -+ .resource = mv78xx0_ge10_shared_resources, -+}; -+ -+static struct resource mv78xx0_ge10_resources[] = { -+ { -+ .name = "ge10 irq", -+ .start = IRQ_MV78XX0_GE10_SUM, -+ .end = IRQ_MV78XX0_GE10_SUM, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ge10 = { -+ .name = MV643XX_ETH_NAME, -+ .id = 2, -+ .num_resources = 1, -+ .resource = mv78xx0_ge10_resources, -+}; -+ -+void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) -+{ -+ eth_data->shared = &mv78xx0_ge10_shared; -+ eth_data->shared_smi = &mv78xx0_ge00_shared; -+ mv78xx0_ge10.dev.platform_data = eth_data; -+ -+ platform_device_register(&mv78xx0_ge10_shared); -+ platform_device_register(&mv78xx0_ge10); -+} -+ -+ -+/***************************************************************************** -+ * GE11 -+ ****************************************************************************/ -+struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = { -+ .t_clk = 0, -+ .dram = &mv78xx0_mbus_dram_info, -+}; -+ -+static struct resource mv78xx0_ge11_shared_resources[] = { -+ { -+ .name = "ge11 base", -+ .start = GE11_PHYS_BASE + 0x2000, -+ .end = GE11_PHYS_BASE + 0x3fff, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ge11_shared = { -+ .name = MV643XX_ETH_SHARED_NAME, -+ .id = 3, -+ .dev = { -+ .platform_data = &mv78xx0_ge11_shared_data, -+ }, -+ .num_resources = 1, -+ .resource = mv78xx0_ge11_shared_resources, -+}; -+ -+static struct resource mv78xx0_ge11_resources[] = { -+ { -+ .name = "ge11 irq", -+ .start = IRQ_MV78XX0_GE11_SUM, -+ .end = IRQ_MV78XX0_GE11_SUM, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_ge11 = { -+ .name = MV643XX_ETH_NAME, -+ .id = 3, -+ .num_resources = 1, -+ .resource = mv78xx0_ge11_resources, -+}; -+ -+void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) -+{ -+ eth_data->shared = &mv78xx0_ge11_shared; -+ eth_data->shared_smi = &mv78xx0_ge00_shared; -+ mv78xx0_ge11.dev.platform_data = eth_data; -+ -+ platform_device_register(&mv78xx0_ge11_shared); -+ platform_device_register(&mv78xx0_ge11); -+} -+ -+ -+/***************************************************************************** -+ * SATA -+ ****************************************************************************/ -+static struct resource mv78xx0_sata_resources[] = { -+ { -+ .name = "sata base", -+ .start = SATA_PHYS_BASE, -+ .end = SATA_PHYS_BASE + 0x5000 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .name = "sata irq", -+ .start = IRQ_MV78XX0_SATA, -+ .end = IRQ_MV78XX0_SATA, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_sata = { -+ .name = "sata_mv", -+ .id = 0, -+ .dev = { -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .num_resources = ARRAY_SIZE(mv78xx0_sata_resources), -+ .resource = mv78xx0_sata_resources, -+}; -+ -+void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) -+{ -+ sata_data->dram = &mv78xx0_mbus_dram_info; -+ mv78xx0_sata.dev.platform_data = sata_data; -+ platform_device_register(&mv78xx0_sata); -+} -+ -+ -+/***************************************************************************** -+ * UART0 -+ ****************************************************************************/ -+static struct plat_serial8250_port mv78xx0_uart0_data[] = { -+ { -+ .mapbase = UART0_PHYS_BASE, -+ .membase = (char *)UART0_VIRT_BASE, -+ .irq = IRQ_MV78XX0_UART_0, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = 0, -+ }, { -+ }, -+}; -+ -+static struct resource mv78xx0_uart0_resources[] = { -+ { -+ .start = UART0_PHYS_BASE, -+ .end = UART0_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_MV78XX0_UART_0, -+ .end = IRQ_MV78XX0_UART_0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_uart0 = { -+ .name = "serial8250", -+ .id = 0, -+ .dev = { -+ .platform_data = mv78xx0_uart0_data, -+ }, -+ .resource = mv78xx0_uart0_resources, -+ .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources), -+}; -+ -+void __init mv78xx0_uart0_init(void) -+{ -+ platform_device_register(&mv78xx0_uart0); -+} -+ -+ -+/***************************************************************************** -+ * UART1 -+ ****************************************************************************/ -+static struct plat_serial8250_port mv78xx0_uart1_data[] = { -+ { -+ .mapbase = UART1_PHYS_BASE, -+ .membase = (char *)UART1_VIRT_BASE, -+ .irq = IRQ_MV78XX0_UART_1, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = 0, -+ }, { -+ }, -+}; -+ -+static struct resource mv78xx0_uart1_resources[] = { -+ { -+ .start = UART1_PHYS_BASE, -+ .end = UART1_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_MV78XX0_UART_1, -+ .end = IRQ_MV78XX0_UART_1, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_uart1 = { -+ .name = "serial8250", -+ .id = 1, -+ .dev = { -+ .platform_data = mv78xx0_uart1_data, -+ }, -+ .resource = mv78xx0_uart1_resources, -+ .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources), -+}; -+ -+void __init mv78xx0_uart1_init(void) -+{ -+ platform_device_register(&mv78xx0_uart1); -+} -+ -+ -+/***************************************************************************** -+ * UART2 -+ ****************************************************************************/ -+static struct plat_serial8250_port mv78xx0_uart2_data[] = { -+ { -+ .mapbase = UART2_PHYS_BASE, -+ .membase = (char *)UART2_VIRT_BASE, -+ .irq = IRQ_MV78XX0_UART_2, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = 0, -+ }, { -+ }, -+}; -+ -+static struct resource mv78xx0_uart2_resources[] = { -+ { -+ .start = UART2_PHYS_BASE, -+ .end = UART2_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_MV78XX0_UART_2, -+ .end = IRQ_MV78XX0_UART_2, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_uart2 = { -+ .name = "serial8250", -+ .id = 2, -+ .dev = { -+ .platform_data = mv78xx0_uart2_data, -+ }, -+ .resource = mv78xx0_uart2_resources, -+ .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources), -+}; -+ -+void __init mv78xx0_uart2_init(void) -+{ -+ platform_device_register(&mv78xx0_uart2); -+} -+ -+ -+/***************************************************************************** -+ * UART3 -+ ****************************************************************************/ -+static struct plat_serial8250_port mv78xx0_uart3_data[] = { -+ { -+ .mapbase = UART3_PHYS_BASE, -+ .membase = (char *)UART3_VIRT_BASE, -+ .irq = IRQ_MV78XX0_UART_3, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = 0, -+ }, { -+ }, -+}; -+ -+static struct resource mv78xx0_uart3_resources[] = { -+ { -+ .start = UART3_PHYS_BASE, -+ .end = UART3_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_MV78XX0_UART_3, -+ .end = IRQ_MV78XX0_UART_3, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device mv78xx0_uart3 = { -+ .name = "serial8250", -+ .id = 3, -+ .dev = { -+ .platform_data = mv78xx0_uart3_data, -+ }, -+ .resource = mv78xx0_uart3_resources, -+ .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources), -+}; -+ -+void __init mv78xx0_uart3_init(void) -+{ -+ platform_device_register(&mv78xx0_uart3); -+} -+ -+ -+/***************************************************************************** -+ * Time handling -+ ****************************************************************************/ -+static void mv78xx0_timer_init(void) -+{ -+ orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk()); -+} -+ -+struct sys_timer mv78xx0_timer = { -+ .init = mv78xx0_timer_init, -+}; -+ -+ -+/***************************************************************************** -+ * General -+ ****************************************************************************/ -+static int __init is_l2_writethrough(void) -+{ -+ return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); -+} -+ -+void __init mv78xx0_init(void) -+{ -+ int core_index; -+ int hclk; -+ int pclk; -+ int l2clk; -+ int tclk; -+ -+ core_index = mv78xx0_core_index(); -+ hclk = get_hclk(); -+ get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); -+ tclk = get_tclk(); -+ -+ printk(KERN_INFO "MV78xx0 core #%d, ", core_index); -+ printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); -+ printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); -+ printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); -+ printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); -+ -+ mv78xx0_setup_cpu_mbus(); -+ -+#ifdef CONFIG_CACHE_FEROCEON_L2 -+ feroceon_l2_init(is_l2_writethrough()); -+#endif -+ -+ mv78xx0_ge00_shared_data.t_clk = tclk; -+ mv78xx0_ge01_shared_data.t_clk = tclk; -+ mv78xx0_ge10_shared_data.t_clk = tclk; -+ mv78xx0_ge11_shared_data.t_clk = tclk; -+ mv78xx0_uart0_data[0].uartclk = tclk; -+ mv78xx0_uart1_data[0].uartclk = tclk; -+ mv78xx0_uart2_data[0].uartclk = tclk; -+ mv78xx0_uart3_data[0].uartclk = tclk; -+} ---- /dev/null -+++ b/arch/arm/mach-mv78xx0/common.h -@@ -0,0 +1,49 @@ -+/* -+ * arch/arm/mach-mv78xx0/common.h -+ * -+ * Core functions for Marvell MV78xx0 SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ARCH_MV78XX0_COMMON_H -+#define __ARCH_MV78XX0_COMMON_H -+ -+struct mv643xx_eth_platform_data; -+struct mv_sata_platform_data; -+ -+/* -+ * Basic MV78xx0 init functions used early by machine-setup. -+ */ -+int mv78xx0_core_index(void); -+void mv78xx0_map_io(void); -+void mv78xx0_init(void); -+void mv78xx0_init_irq(void); -+ -+extern struct mbus_dram_target_info mv78xx0_mbus_dram_info; -+void mv78xx0_setup_cpu_mbus(void); -+void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, -+ int maj, int min); -+void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, -+ int maj, int min); -+ -+void mv78xx0_ehci0_init(void); -+void mv78xx0_ehci1_init(void); -+void mv78xx0_ehci2_init(void); -+void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data); -+void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data); -+void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data); -+void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data); -+void mv78xx0_pcie_init(int init_port0, int init_port1); -+void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data); -+void mv78xx0_uart0_init(void); -+void mv78xx0_uart1_init(void); -+void mv78xx0_uart2_init(void); -+void mv78xx0_uart3_init(void); -+ -+extern struct sys_timer mv78xx0_timer; -+ -+ -+#endif ---- /dev/null -+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c -@@ -0,0 +1,94 @@ -+/* -+ * arch/arm/mach-mv78xx0/db78x00-bp-setup.c -+ * -+ * Marvell DB-78x00-BP Development Board Setup -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+static struct mv643xx_eth_platform_data db78x00_ge00_data = { -+ .phy_addr = 8, -+}; -+ -+static struct mv643xx_eth_platform_data db78x00_ge01_data = { -+ .phy_addr = 9, -+}; -+ -+static struct mv643xx_eth_platform_data db78x00_ge10_data = { -+ .phy_addr = -1, -+}; -+ -+static struct mv643xx_eth_platform_data db78x00_ge11_data = { -+ .phy_addr = -1, -+}; -+ -+static struct mv_sata_platform_data db78x00_sata_data = { -+ .n_ports = 2, -+}; -+ -+static void __init db78x00_init(void) -+{ -+ /* -+ * Basic MV78xx0 setup. Needs to be called early. -+ */ -+ mv78xx0_init(); -+ -+ /* -+ * Partition on-chip peripherals between the two CPU cores. -+ */ -+ if (mv78xx0_core_index() == 0) { -+ mv78xx0_ehci0_init(); -+ mv78xx0_ehci1_init(); -+ mv78xx0_ehci2_init(); -+ mv78xx0_ge00_init(&db78x00_ge00_data); -+ mv78xx0_ge01_init(&db78x00_ge01_data); -+ mv78xx0_ge10_init(&db78x00_ge10_data); -+ mv78xx0_ge11_init(&db78x00_ge11_data); -+ mv78xx0_sata_init(&db78x00_sata_data); -+ mv78xx0_uart0_init(); -+ mv78xx0_uart2_init(); -+ } else { -+ mv78xx0_uart1_init(); -+ mv78xx0_uart3_init(); -+ } -+} -+ -+static int __init db78x00_pci_init(void) -+{ -+ if (machine_is_db78x00_bp()) { -+ /* -+ * Assign the x16 PCIe slot on the board to CPU core -+ * #0, and let CPU core #1 have the four x1 slots. -+ */ -+ if (mv78xx0_core_index() == 0) -+ mv78xx0_pcie_init(0, 1); -+ else -+ mv78xx0_pcie_init(1, 0); -+ } -+ -+ return 0; -+} -+subsys_initcall(db78x00_pci_init); -+ -+MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") -+ /* Maintainer: Lennert Buytenhek */ -+ .phys_io = MV78XX0_REGS_PHYS_BASE, -+ .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc, -+ .boot_params = 0x00000100, -+ .init_machine = db78x00_init, -+ .map_io = mv78xx0_map_io, -+ .init_irq = mv78xx0_init_irq, -+ .timer = &mv78xx0_timer, -+MACHINE_END ---- /dev/null -+++ b/arch/arm/mach-mv78xx0/irq.c -@@ -0,0 +1,22 @@ -+/* -+ * arch/arm/mach-mv78xx0/irq.c -+ * -+ * MV78xx0 IRQ handling. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+void __init mv78xx0_init_irq(void) -+{ -+ orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); -+ orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); -+} ---- /dev/null -+++ b/arch/arm/mach-mv78xx0/pcie.c -@@ -0,0 +1,312 @@ -+/* -+ * arch/arm/mach-mv78xx0/pcie.c -+ * -+ * PCIe functions for Marvell MV78xx0 SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+ -+struct pcie_port { -+ u8 maj; -+ u8 min; -+ u8 root_bus_nr; -+ void __iomem *base; -+ spinlock_t conf_lock; -+ char io_space_name[16]; -+ char mem_space_name[16]; -+ struct resource res[2]; -+}; -+ -+static struct pcie_port pcie_port[8]; -+static int num_pcie_ports; -+static struct resource pcie_io_space; -+static struct resource pcie_mem_space; -+ -+ -+static void __init mv78xx0_pcie_preinit(void) -+{ -+ int i; -+ u32 size_each; -+ u32 start; -+ int win; -+ -+ pcie_io_space.name = "PCIe I/O Space"; -+ pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); -+ pcie_io_space.end = -+ MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; -+ pcie_io_space.flags = IORESOURCE_IO; -+ if (request_resource(&iomem_resource, &pcie_io_space)) -+ panic("can't allocate PCIe I/O space"); -+ -+ pcie_mem_space.name = "PCIe MEM Space"; -+ pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; -+ pcie_mem_space.end = -+ MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; -+ pcie_mem_space.flags = IORESOURCE_MEM; -+ if (request_resource(&iomem_resource, &pcie_mem_space)) -+ panic("can't allocate PCIe MEM space"); -+ -+ for (i = 0; i < num_pcie_ports; i++) { -+ struct pcie_port *pp = pcie_port + i; -+ -+ snprintf(pp->io_space_name, sizeof(pp->io_space_name), -+ "PCIe %d.%d I/O", pp->maj, pp->min); -+ pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; -+ pp->res[0].name = pp->io_space_name; -+ pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); -+ pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; -+ pp->res[0].flags = IORESOURCE_IO; -+ -+ snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), -+ "PCIe %d.%d MEM", pp->maj, pp->min); -+ pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; -+ pp->res[1].name = pp->mem_space_name; -+ pp->res[1].flags = IORESOURCE_MEM; -+ } -+ -+ switch (num_pcie_ports) { -+ case 0: -+ size_each = 0; -+ break; -+ -+ case 1: -+ size_each = 0x30000000; -+ break; -+ -+ case 2 ... 3: -+ size_each = 0x10000000; -+ break; -+ -+ case 4 ... 6: -+ size_each = 0x08000000; -+ break; -+ -+ case 7: -+ size_each = 0x04000000; -+ break; -+ -+ default: -+ panic("invalid number of PCIe ports"); -+ } -+ -+ start = MV78XX0_PCIE_MEM_PHYS_BASE; -+ for (i = 0; i < num_pcie_ports; i++) { -+ struct pcie_port *pp = pcie_port + i; -+ -+ pp->res[1].start = start; -+ pp->res[1].end = start + size_each - 1; -+ start += size_each; -+ } -+ -+ for (i = 0; i < num_pcie_ports; i++) { -+ struct pcie_port *pp = pcie_port + i; -+ -+ if (request_resource(&pcie_io_space, &pp->res[0])) -+ panic("can't allocate PCIe I/O sub-space"); -+ -+ if (request_resource(&pcie_mem_space, &pp->res[1])) -+ panic("can't allocate PCIe MEM sub-space"); -+ } -+ -+ win = 0; -+ for (i = 0; i < num_pcie_ports; i++) { -+ struct pcie_port *pp = pcie_port + i; -+ -+ mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, -+ pp->res[0].end - pp->res[0].start + 1, -+ pp->maj, pp->min); -+ -+ mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start, -+ pp->res[1].end - pp->res[1].start + 1, -+ pp->maj, pp->min); -+ } -+} -+ -+static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) -+{ -+ struct pcie_port *pp; -+ -+ if (nr >= num_pcie_ports) -+ return 0; -+ -+ pp = &pcie_port[nr]; -+ pp->root_bus_nr = sys->busnr; -+ -+ /* -+ * Generic PCIe unit setup. -+ */ -+ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); -+ orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); -+ -+ sys->resource[0] = &pp->res[0]; -+ sys->resource[1] = &pp->res[1]; -+ sys->resource[2] = NULL; -+ -+ return 1; -+} -+ -+static struct pcie_port *bus_to_port(int bus) -+{ -+ int i; -+ -+ for (i = num_pcie_ports - 1; i >= 0; i--) { -+ int rbus = pcie_port[i].root_bus_nr; -+ if (rbus != -1 && rbus <= bus) -+ break; -+ } -+ -+ return i >= 0 ? pcie_port + i : NULL; -+} -+ -+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) -+{ -+ /* -+ * Don't go out when trying to access nonexisting devices -+ * on the local bus. -+ */ -+ if (bus == pp->root_bus_nr && dev > 1) -+ return 0; -+ -+ return 1; -+} -+ -+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, -+ int size, u32 *val) -+{ -+ struct pcie_port *pp = bus_to_port(bus->number); -+ unsigned long flags; -+ int ret; -+ -+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { -+ *val = 0xffffffff; -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ } -+ -+ spin_lock_irqsave(&pp->conf_lock, flags); -+ ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); -+ spin_unlock_irqrestore(&pp->conf_lock, flags); -+ -+ return ret; -+} -+ -+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, -+ int where, int size, u32 val) -+{ -+ struct pcie_port *pp = bus_to_port(bus->number); -+ unsigned long flags; -+ int ret; -+ -+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ spin_lock_irqsave(&pp->conf_lock, flags); -+ ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); -+ spin_unlock_irqrestore(&pp->conf_lock, flags); -+ -+ return ret; -+} -+ -+static struct pci_ops pcie_ops = { -+ .read = pcie_rd_conf, -+ .write = pcie_wr_conf, -+}; -+ -+static void __devinit rc_pci_fixup(struct pci_dev *dev) -+{ -+ /* -+ * Prevent enumeration of root complex. -+ */ -+ if (dev->bus->parent == NULL && dev->devfn == 0) { -+ int i; -+ -+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { -+ dev->resource[i].start = 0; -+ dev->resource[i].end = 0; -+ dev->resource[i].flags = 0; -+ } -+ } -+} -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); -+ -+static struct pci_bus __init * -+mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) -+{ -+ struct pci_bus *bus; -+ -+ if (nr < num_pcie_ports) { -+ bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); -+ } else { -+ bus = NULL; -+ BUG(); -+ } -+ -+ return bus; -+} -+ -+static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ struct pcie_port *pp = bus_to_port(dev->bus->number); -+ -+ return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min; -+} -+ -+static struct hw_pci mv78xx0_pci __initdata = { -+ .nr_controllers = 8, -+ .preinit = mv78xx0_pcie_preinit, -+ .swizzle = pci_std_swizzle, -+ .setup = mv78xx0_pcie_setup, -+ .scan = mv78xx0_pcie_scan_bus, -+ .map_irq = mv78xx0_pcie_map_irq, -+}; -+ -+static void __init add_pcie_port(int maj, int min, unsigned long base) -+{ -+ printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); -+ -+ if (orion_pcie_link_up((void __iomem *)base)) { -+ struct pcie_port *pp = &pcie_port[num_pcie_ports++]; -+ -+ printk("link up\n"); -+ -+ pp->maj = maj; -+ pp->min = min; -+ pp->root_bus_nr = -1; -+ pp->base = (void __iomem *)base; -+ spin_lock_init(&pp->conf_lock); -+ memset(pp->res, 0, sizeof(pp->res)); -+ } else { -+ printk("link down, ignoring\n"); -+ } -+} -+ -+void __init mv78xx0_pcie_init(int init_port0, int init_port1) -+{ -+ if (init_port0) { -+ add_pcie_port(0, 0, PCIE00_VIRT_BASE); -+ if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { -+ add_pcie_port(0, 1, PCIE01_VIRT_BASE); -+ add_pcie_port(0, 2, PCIE02_VIRT_BASE); -+ add_pcie_port(0, 3, PCIE03_VIRT_BASE); -+ } -+ } -+ -+ if (init_port1) { -+ add_pcie_port(1, 0, PCIE10_VIRT_BASE); -+ if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) { -+ add_pcie_port(1, 1, PCIE11_VIRT_BASE); -+ add_pcie_port(1, 2, PCIE12_VIRT_BASE); -+ add_pcie_port(1, 3, PCIE13_VIRT_BASE); -+ } -+ } -+ -+ pci_common_init(&mv78xx0_pci); -+} ---- a/arch/arm/mach-orion5x/Kconfig -+++ b/arch/arm/mach-orion5x/Kconfig -@@ -44,6 +44,36 @@ - Buffalo Linkstation Pro/Live platform. Both v1 and - v2 devices are supported. - -+config MACH_TS409 -+ bool "QNAP TS-409" -+ help -+ Say 'Y' here if you want your kernel to support the -+ QNAP TS-409 platform. -+ -+config MACH_WRT350N_V2 -+ bool "Linksys WRT350N v2" -+ help -+ Say 'Y' here if you want your kernel to support the -+ Linksys WRT350N v2 platform. -+ -+config MACH_TS78XX -+ bool "Technologic Systems TS-78xx" -+ help -+ Say 'Y' here if you want your kernel to support the -+ Technologic Systems TS-78xx platform. -+ -+config MACH_MV2120 -+ bool "HP Media Vault mv2120" -+ help -+ Say 'Y' here if you want your kernel to support the -+ HP Media Vault mv2120 or mv5100. -+ -+config MACH_MSS2 -+ bool "Maxtor Shared Storage II" -+ help -+ Say 'Y' here if you want your kernel to support the -+ Maxtor Shared Storage II platform. -+ - endmenu - - endif ---- a/arch/arm/mach-orion5x/Makefile -+++ b/arch/arm/mach-orion5x/Makefile -@@ -1,7 +1,12 @@ --obj-y += common.o addr-map.o pci.o gpio.o irq.o -+obj-y += common.o addr-map.o pci.o gpio.o irq.o mpp.o - obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o - obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o - obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o - obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o - obj-$(CONFIG_MACH_DNS323) += dns323-setup.o --obj-$(CONFIG_MACH_TS209) += ts209-setup.o -+obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o -+obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o -+obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o -+obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o -+obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o -+obj-$(CONFIG_MACH_MSS2) += mss2-setup.o ---- a/arch/arm/mach-orion5x/addr-map.c -+++ b/arch/arm/mach-orion5x/addr-map.c -@@ -70,6 +70,7 @@ - - - struct mbus_dram_target_info orion5x_mbus_dram_info; -+static int __initdata win_alloc_count; - - static int __init orion5x_cpu_win_can_remap(int win) - { -@@ -87,16 +88,22 @@ - static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) - { -- orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); -- orion5x_write(CPU_WIN_CTRL(win), -- ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); -+ if (win >= 8) { -+ printk(KERN_ERR "setup_cpu_win: trying to allocate " -+ "window %d\n", win); -+ return; -+ } -+ -+ writel(base & 0xffff0000, CPU_WIN_BASE(win)); -+ writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1, -+ CPU_WIN_CTRL(win)); - - if (orion5x_cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - -- orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); -- orion5x_write(CPU_WIN_REMAP_HI(win), 0); -+ writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); -+ writel(0, CPU_WIN_REMAP_HI(win)); - } - } - -@@ -109,11 +116,11 @@ - * First, disable and clear windows. - */ - for (i = 0; i < 8; i++) { -- orion5x_write(CPU_WIN_BASE(i), 0); -- orion5x_write(CPU_WIN_CTRL(i), 0); -+ writel(0, CPU_WIN_BASE(i)); -+ writel(0, CPU_WIN_CTRL(i)); - if (orion5x_cpu_win_can_remap(i)) { -- orion5x_write(CPU_WIN_REMAP_LO(i), 0); -- orion5x_write(CPU_WIN_REMAP_HI(i), 0); -+ writel(0, CPU_WIN_REMAP_LO(i)); -+ writel(0, CPU_WIN_REMAP_HI(i)); - } - } - -@@ -128,6 +135,7 @@ - TARGET_PCIE, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, - TARGET_PCI, ATTR_PCI_MEM, -1); -+ win_alloc_count = 4; - - /* - * Setup MBUS dram target info. -@@ -147,8 +155,8 @@ - w = &orion5x_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); -- w->base = base & 0xff000000; -- w->size = (size | 0x00ffffff) + 1; -+ w->base = base & 0xffff0000; -+ w->size = (size | 0x0000ffff) + 1; - } - } - orion5x_mbus_dram_info.num_cs = cs; -@@ -156,25 +164,30 @@ - - void __init orion5x_setup_dev_boot_win(u32 base, u32 size) - { -- setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); -+ setup_cpu_win(win_alloc_count++, base, size, -+ TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); - } - - void __init orion5x_setup_dev0_win(u32 base, u32 size) - { -- setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); -+ setup_cpu_win(win_alloc_count++, base, size, -+ TARGET_DEV_BUS, ATTR_DEV_CS0, -1); - } - - void __init orion5x_setup_dev1_win(u32 base, u32 size) - { -- setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); -+ setup_cpu_win(win_alloc_count++, base, size, -+ TARGET_DEV_BUS, ATTR_DEV_CS1, -1); - } - - void __init orion5x_setup_dev2_win(u32 base, u32 size) - { -- setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); -+ setup_cpu_win(win_alloc_count++, base, size, -+ TARGET_DEV_BUS, ATTR_DEV_CS2, -1); - } - - void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) - { -- setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); -+ setup_cpu_win(win_alloc_count++, base, size, -+ TARGET_PCIE, ATTR_PCIE_WA, -1); - } ---- a/arch/arm/mach-orion5x/common.c -+++ b/arch/arm/mach-orion5x/common.c -@@ -39,25 +39,22 @@ - .virtual = ORION5X_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), - .length = ORION5X_REGS_SIZE, -- .type = MT_DEVICE -- }, -- { -+ .type = MT_DEVICE, -+ }, { - .virtual = ORION5X_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), - .length = ORION5X_PCIE_IO_SIZE, -- .type = MT_DEVICE -- }, -- { -+ .type = MT_DEVICE, -+ }, { - .virtual = ORION5X_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), - .length = ORION5X_PCI_IO_SIZE, -- .type = MT_DEVICE -- }, -- { -+ .type = MT_DEVICE, -+ }, { - .virtual = ORION5X_PCIE_WA_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), - .length = ORION5X_PCIE_WA_SIZE, -- .type = MT_DEVICE -+ .type = MT_DEVICE, - }, - }; - -@@ -66,101 +63,32 @@ - iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); - } - -+ - /***************************************************************************** -- * UART -+ * EHCI - ****************************************************************************/ -- --static struct resource orion5x_uart_resources[] = { -- { -- .start = UART0_PHYS_BASE, -- .end = UART0_PHYS_BASE + 0xff, -- .flags = IORESOURCE_MEM, -- }, -- { -- .start = IRQ_ORION5X_UART0, -- .end = IRQ_ORION5X_UART0, -- .flags = IORESOURCE_IRQ, -- }, -- { -- .start = UART1_PHYS_BASE, -- .end = UART1_PHYS_BASE + 0xff, -- .flags = IORESOURCE_MEM, -- }, -- { -- .start = IRQ_ORION5X_UART1, -- .end = IRQ_ORION5X_UART1, -- .flags = IORESOURCE_IRQ, -- }, --}; -- --static struct plat_serial8250_port orion5x_uart_data[] = { -- { -- .mapbase = UART0_PHYS_BASE, -- .membase = (char *)UART0_VIRT_BASE, -- .irq = IRQ_ORION5X_UART0, -- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -- .iotype = UPIO_MEM, -- .regshift = 2, -- .uartclk = ORION5X_TCLK, -- }, -- { -- .mapbase = UART1_PHYS_BASE, -- .membase = (char *)UART1_VIRT_BASE, -- .irq = IRQ_ORION5X_UART1, -- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -- .iotype = UPIO_MEM, -- .regshift = 2, -- .uartclk = ORION5X_TCLK, -- }, -- { }, -+static struct orion_ehci_data orion5x_ehci_data = { -+ .dram = &orion5x_mbus_dram_info, - }; - --static struct platform_device orion5x_uart = { -- .name = "serial8250", -- .id = PLAT8250_DEV_PLATFORM, -- .dev = { -- .platform_data = orion5x_uart_data, -- }, -- .resource = orion5x_uart_resources, -- .num_resources = ARRAY_SIZE(orion5x_uart_resources), --}; -+static u64 ehci_dmamask = 0xffffffffUL; - --/******************************************************************************* -- * USB Controller - 2 interfaces -- ******************************************************************************/ - -+/***************************************************************************** -+ * EHCI0 -+ ****************************************************************************/ - static struct resource orion5x_ehci0_resources[] = { - { - .start = ORION5X_USB0_PHYS_BASE, - .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, -- }, -- { -+ }, { - .start = IRQ_ORION5X_USB0_CTRL, - .end = IRQ_ORION5X_USB0_CTRL, - .flags = IORESOURCE_IRQ, - }, - }; - --static struct resource orion5x_ehci1_resources[] = { -- { -- .start = ORION5X_USB1_PHYS_BASE, -- .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, -- .flags = IORESOURCE_MEM, -- }, -- { -- .start = IRQ_ORION5X_USB1_CTRL, -- .end = IRQ_ORION5X_USB1_CTRL, -- .flags = IORESOURCE_IRQ, -- }, --}; -- --static struct orion_ehci_data orion5x_ehci_data = { -- .dram = &orion5x_mbus_dram_info, --}; -- --static u64 ehci_dmamask = 0xffffffffUL; -- - static struct platform_device orion5x_ehci0 = { - .name = "orion-ehci", - .id = 0, -@@ -173,6 +101,27 @@ - .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), - }; - -+void __init orion5x_ehci0_init(void) -+{ -+ platform_device_register(&orion5x_ehci0); -+} -+ -+ -+/***************************************************************************** -+ * EHCI1 -+ ****************************************************************************/ -+static struct resource orion5x_ehci1_resources[] = { -+ { -+ .start = ORION5X_USB1_PHYS_BASE, -+ .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_ORION5X_USB1_CTRL, -+ .end = IRQ_ORION5X_USB1_CTRL, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ - static struct platform_device orion5x_ehci1 = { - .name = "orion-ehci", - .id = 1, -@@ -185,11 +134,15 @@ - .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), - }; - -+void __init orion5x_ehci1_init(void) -+{ -+ platform_device_register(&orion5x_ehci1); -+} -+ -+ - /***************************************************************************** -- * Gigabit Ethernet port -- * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) -+ * GigE - ****************************************************************************/ -- - struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = { - .dram = &orion5x_mbus_dram_info, - .t_clk = ORION5X_TCLK, -@@ -219,7 +172,7 @@ - .start = IRQ_ORION5X_ETH_SUM, - .end = IRQ_ORION5X_ETH_SUM, - .flags = IORESOURCE_IRQ, -- } -+ }, - }; - - static struct platform_device orion5x_eth = { -@@ -238,11 +191,10 @@ - platform_device_register(&orion5x_eth); - } - -+ - /***************************************************************************** -- * I2C controller -- * (The Orion and Discovery (MV643xx) families share the same I2C controller) -+ * I2C - ****************************************************************************/ -- - static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, -@@ -251,16 +203,15 @@ - - static struct resource orion5x_i2c_resources[] = { - { -- .name = "i2c base", -- .start = I2C_PHYS_BASE, -- .end = I2C_PHYS_BASE + 0x20 -1, -- .flags = IORESOURCE_MEM, -- }, -- { -- .name = "i2c irq", -- .start = IRQ_ORION5X_I2C, -- .end = IRQ_ORION5X_I2C, -- .flags = IORESOURCE_IRQ, -+ .name = "i2c base", -+ .start = I2C_PHYS_BASE, -+ .end = I2C_PHYS_BASE + 0x1f, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .name = "i2c irq", -+ .start = IRQ_ORION5X_I2C, -+ .end = IRQ_ORION5X_I2C, -+ .flags = IORESOURCE_IRQ, - }, - }; - -@@ -270,36 +221,41 @@ - .num_resources = ARRAY_SIZE(orion5x_i2c_resources), - .resource = orion5x_i2c_resources, - .dev = { -- .platform_data = &orion5x_i2c_pdata, -+ .platform_data = &orion5x_i2c_pdata, - }, - }; - -+void __init orion5x_i2c_init(void) -+{ -+ platform_device_register(&orion5x_i2c); -+} -+ -+ - /***************************************************************************** -- * Sata port -+ * SATA - ****************************************************************************/ - static struct resource orion5x_sata_resources[] = { -- { -- .name = "sata base", -- .start = ORION5X_SATA_PHYS_BASE, -- .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, -- .flags = IORESOURCE_MEM, -- }, - { -- .name = "sata irq", -- .start = IRQ_ORION5X_SATA, -- .end = IRQ_ORION5X_SATA, -- .flags = IORESOURCE_IRQ, -- }, -+ .name = "sata base", -+ .start = ORION5X_SATA_PHYS_BASE, -+ .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .name = "sata irq", -+ .start = IRQ_ORION5X_SATA, -+ .end = IRQ_ORION5X_SATA, -+ .flags = IORESOURCE_IRQ, -+ }, - }; - - static struct platform_device orion5x_sata = { -- .name = "sata_mv", -- .id = 0, -+ .name = "sata_mv", -+ .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -- .num_resources = ARRAY_SIZE(orion5x_sata_resources), -- .resource = orion5x_sata_resources, -+ .num_resources = ARRAY_SIZE(orion5x_sata_resources), -+ .resource = orion5x_sata_resources, - }; - - void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) -@@ -309,23 +265,111 @@ - platform_device_register(&orion5x_sata); - } - -+ - /***************************************************************************** -- * Time handling -+ * UART0 -+ ****************************************************************************/ -+static struct plat_serial8250_port orion5x_uart0_data[] = { -+ { -+ .mapbase = UART0_PHYS_BASE, -+ .membase = (char *)UART0_VIRT_BASE, -+ .irq = IRQ_ORION5X_UART0, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = ORION5X_TCLK, -+ }, { -+ }, -+}; -+ -+static struct resource orion5x_uart0_resources[] = { -+ { -+ .start = UART0_PHYS_BASE, -+ .end = UART0_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_ORION5X_UART0, -+ .end = IRQ_ORION5X_UART0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device orion5x_uart0 = { -+ .name = "serial8250", -+ .id = PLAT8250_DEV_PLATFORM, -+ .dev = { -+ .platform_data = orion5x_uart0_data, -+ }, -+ .resource = orion5x_uart0_resources, -+ .num_resources = ARRAY_SIZE(orion5x_uart0_resources), -+}; -+ -+void __init orion5x_uart0_init(void) -+{ -+ platform_device_register(&orion5x_uart0); -+} -+ -+ -+/***************************************************************************** -+ * UART1 - ****************************************************************************/ -+static struct plat_serial8250_port orion5x_uart1_data[] = { -+ { -+ .mapbase = UART1_PHYS_BASE, -+ .membase = (char *)UART1_VIRT_BASE, -+ .irq = IRQ_ORION5X_UART1, -+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, -+ .iotype = UPIO_MEM, -+ .regshift = 2, -+ .uartclk = ORION5X_TCLK, -+ }, { -+ }, -+}; -+ -+static struct resource orion5x_uart1_resources[] = { -+ { -+ .start = UART1_PHYS_BASE, -+ .end = UART1_PHYS_BASE + 0xff, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_ORION5X_UART1, -+ .end = IRQ_ORION5X_UART1, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device orion5x_uart1 = { -+ .name = "serial8250", -+ .id = PLAT8250_DEV_PLATFORM1, -+ .dev = { -+ .platform_data = orion5x_uart1_data, -+ }, -+ .resource = orion5x_uart1_resources, -+ .num_resources = ARRAY_SIZE(orion5x_uart1_resources), -+}; -+ -+void __init orion5x_uart1_init(void) -+{ -+ platform_device_register(&orion5x_uart1); -+} -+ - -+/***************************************************************************** -+ * Time handling -+ ****************************************************************************/ - static void orion5x_timer_init(void) - { - orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); - } - - struct sys_timer orion5x_timer = { -- .init = orion5x_timer_init, -+ .init = orion5x_timer_init, - }; - -+ - /***************************************************************************** - * General - ****************************************************************************/ -- - /* - * Identify device ID and rev from PCIe configuration header space '0'. - */ -@@ -350,8 +394,10 @@ - } else if (*dev == MV88F5181_DEV_ID) { - if (*rev == MV88F5181_REV_B1) { - *dev_name = "MV88F5181-Rev-B1"; -+ } else if (*rev == MV88F5181L_REV_A1) { -+ *dev_name = "MV88F5181L-Rev-A1"; - } else { -- *dev_name = "MV88F5181-Rev-Unsupported"; -+ *dev_name = "MV88F5181(L)-Rev-Unsupported"; - } - } else { - *dev_name = "Device-Unknown"; -@@ -370,15 +416,6 @@ - * Setup Orion address map - */ - orion5x_setup_cpu_mbus_bridge(); -- -- /* -- * Register devices. -- */ -- platform_device_register(&orion5x_uart); -- platform_device_register(&orion5x_ehci0); -- if (dev == MV88F5182_DEV_ID) -- platform_device_register(&orion5x_ehci1); -- platform_device_register(&orion5x_i2c); - } - - /* ---- a/arch/arm/mach-orion5x/common.h -+++ b/arch/arm/mach-orion5x/common.h -@@ -1,10 +1,12 @@ - #ifndef __ARCH_ORION5X_COMMON_H - #define __ARCH_ORION5X_COMMON_H - -+struct mv643xx_eth_platform_data; -+struct mv_sata_platform_data; -+ - /* - * Basic Orion init functions used early by machine-setup. - */ -- - void orion5x_map_io(void); - void orion5x_init_irq(void); - void orion5x_init(void); -@@ -23,13 +25,19 @@ - void orion5x_setup_dev2_win(u32 base, u32 size); - void orion5x_setup_pcie_wa_win(u32 base, u32 size); - -+void orion5x_ehci0_init(void); -+void orion5x_ehci1_init(void); -+void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); -+void orion5x_i2c_init(void); -+void orion5x_sata_init(struct mv_sata_platform_data *sata_data); -+void orion5x_uart0_init(void); -+void orion5x_uart1_init(void); -+ - /* -- * Shared code used internally by other Orion core functions. -- * (/mach-orion/pci.c) -+ * PCIe/PCI functions. - */ -- --struct pci_sys_data; - struct pci_bus; -+struct pci_sys_data; - - void orion5x_pcie_id(u32 *dev, u32 *rev); - int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); -@@ -40,26 +48,9 @@ - * Valid GPIO pins according to MPP setup, used by machine-setup. - * (/mach-orion/gpio.c). - */ -- --void orion5x_gpio_set_valid_pins(u32 pins); -+void orion5x_gpio_set_valid(unsigned pin, int valid); - void gpio_display(void); /* debug */ - --/* -- * Pull in Orion Ethernet platform_data, used by machine-setup -- */ -- --struct mv643xx_eth_platform_data; -- --void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); -- --/* -- * Orion Sata platform_data, used by machine-setup -- */ -- --struct mv_sata_platform_data; -- --void orion5x_sata_init(struct mv_sata_platform_data *sata_data); -- - struct machine_desc; - struct meminfo; - struct tag; ---- a/arch/arm/mach-orion5x/db88f5281-setup.c -+++ b/arch/arm/mach-orion5x/db88f5281-setup.c -@@ -27,6 +27,7 @@ - #include - #include - #include "common.h" -+#include "mpp.h" - - /***************************************************************************** - * DB-88F5281 on board devices -@@ -86,7 +87,7 @@ - .name = "physmap-flash", - .id = 0, - .dev = { -- .platform_data = &db88f5281_boot_flash_data, -+ .platform_data = &db88f5281_boot_flash_data, - }, - .num_resources = 1, - .resource = &db88f5281_boot_flash_resource, -@@ -110,7 +111,7 @@ - .name = "physmap-flash", - .id = 1, - .dev = { -- .platform_data = &db88f5281_nor_flash_data, -+ .platform_data = &db88f5281_nor_flash_data, - }, - .num_resources = 1, - .resource = &db88f5281_nor_flash_resource, -@@ -125,18 +126,15 @@ - .name = "kernel", - .offset = 0, - .size = SZ_2M, -- }, -- { -+ }, { - .name = "root", - .offset = SZ_2M, - .size = (SZ_16M - SZ_2M), -- }, -- { -+ }, { - .name = "user", - .offset = SZ_16M, - .size = SZ_8M, -- }, -- { -+ }, { - .name = "recovery", - .offset = (SZ_16M + SZ_8M), - .size = SZ_8M, -@@ -288,7 +286,6 @@ - ****************************************************************************/ - static struct mv643xx_eth_platform_data db88f5281_eth_data = { - .phy_addr = 8, -- .force_phy_addr = 1, - }; - - /***************************************************************************** -@@ -301,11 +298,28 @@ - /***************************************************************************** - * General Setup - ****************************************************************************/ -- --static struct platform_device *db88f5281_devs[] __initdata = { -- &db88f5281_boot_flash, -- &db88f5281_nor_flash, -- &db88f5281_nand_flash, -+static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = { -+ { 0, MPP_GPIO }, /* USB Over Current */ -+ { 1, MPP_GPIO }, /* USB Vbat input */ -+ { 2, MPP_PCI_ARB }, /* PCI_REQn[2] */ -+ { 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */ -+ { 4, MPP_PCI_ARB }, /* PCI_REQn[3] */ -+ { 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */ -+ { 6, MPP_GPIO }, /* JP0, CON17.2 */ -+ { 7, MPP_GPIO }, /* JP1, CON17.1 */ -+ { 8, MPP_GPIO }, /* JP2, CON11.2 */ -+ { 9, MPP_GPIO }, /* JP3, CON11.3 */ -+ { 10, MPP_GPIO }, /* RTC int */ -+ { 11, MPP_GPIO }, /* Baud Rate Generator */ -+ { 12, MPP_GPIO }, /* PCI int 1 */ -+ { 13, MPP_GPIO }, /* PCI int 2 */ -+ { 14, MPP_NAND }, /* NAND_REn[2] */ -+ { 15, MPP_NAND }, /* NAND_WEn[2] */ -+ { 16, MPP_UART }, /* UART1_RX */ -+ { 17, MPP_UART }, /* UART1_TX */ -+ { 18, MPP_UART }, /* UART1_CTSn */ -+ { 19, MPP_UART }, /* UART1_RTSn */ -+ { -1 }, - }; - - static void __init db88f5281_init(void) -@@ -315,39 +329,31 @@ - */ - orion5x_init(); - -+ orion5x_mpp_conf(db88f5281_mpp_modes); -+ writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ -+ - /* -- * Setup the CPU address decode windows for our on-board devices -+ * Configure peripherals. - */ -+ orion5x_ehci0_init(); -+ orion5x_eth_init(&db88f5281_eth_data); -+ orion5x_i2c_init(); -+ orion5x_uart0_init(); -+ orion5x_uart1_init(); -+ - orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE); -+ platform_device_register(&db88f5281_boot_flash); -+ - orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); -- orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); -- orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); - -- /* -- * Setup Multiplexing Pins: -- * MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input) -- * MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2] -- * MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3] -- * MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1) -- * MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3) -- * MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator) -- * MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2) -- * MPP14: NAND_REn[2] MPP15: NAND_WEn[2] -- * MPP16: UART1_RX MPP17: UART1_TX -- * MPP18: UART1_CTS MPP19: UART1_RTS -- * MPP-DEV: DEV_D[16:31] -- */ -- orion5x_write(MPP_0_7_CTRL, 0x00222203); -- orion5x_write(MPP_8_15_CTRL, 0x44000000); -- orion5x_write(MPP_16_19_CTRL, 0); -- orion5x_write(MPP_DEV_CTRL, 0); -+ orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); -+ platform_device_register(&db88f5281_nor_flash); - -- orion5x_gpio_set_valid_pins(0x00003fc3); -+ orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); -+ platform_device_register(&db88f5281_nand_flash); - -- platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); - i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); -- orion5x_eth_init(&db88f5281_eth_data); - } - - MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") ---- a/arch/arm/mach-orion5x/dns323-setup.c -+++ b/arch/arm/mach-orion5x/dns323-setup.c -@@ -27,6 +27,7 @@ - #include - #include - #include "common.h" -+#include "mpp.h" - - #define DNS323_GPIO_LED_RIGHT_AMBER 1 - #define DNS323_GPIO_LED_LEFT_AMBER 2 -@@ -52,8 +53,6 @@ - if (irq != -1) - return irq; - -- pr_err("%s: requested mapping for unknown device\n", __func__); -- - return -1; - } - -@@ -81,7 +80,6 @@ - - static struct mv643xx_eth_platform_data dns323_eth_data = { - .phy_addr = 8, -- .force_phy_addr = 1, - }; - - /**************************************************************************** -@@ -119,7 +117,7 @@ - .name = "u-boot", - .size = 0x00030000, - .offset = 0x007d0000, -- } -+ }, - }; - - static struct physmap_flash_data dns323_nor_flash_data = { -@@ -137,7 +135,9 @@ - static struct platform_device dns323_nor_flash = { - .name = "physmap-flash", - .id = 0, -- .dev = { .platform_data = &dns323_nor_flash_data, }, -+ .dev = { -+ .platform_data = &dns323_nor_flash_data, -+ }, - .resource = &dns323_nor_flash_resource, - .num_resources = 1, - }; -@@ -170,7 +170,9 @@ - static struct platform_device dns323_gpio_leds = { - .name = "leds-gpio", - .id = -1, -- .dev = { .platform_data = &dns323_led_data, }, -+ .dev = { -+ .platform_data = &dns323_led_data, -+ }, - }; - - /**************************************************************************** -@@ -183,35 +185,53 @@ - .gpio = DNS323_GPIO_KEY_RESET, - .desc = "Reset Button", - .active_low = 1, -- }, -- { -+ }, { - .code = KEY_POWER, - .gpio = DNS323_GPIO_KEY_POWER, - .desc = "Power Button", - .active_low = 1, -- } -+ }, - }; - - static struct gpio_keys_platform_data dns323_button_data = { - .buttons = dns323_buttons, -- .nbuttons = ARRAY_SIZE(dns323_buttons), -+ .nbuttons = ARRAY_SIZE(dns323_buttons), - }; - - static struct platform_device dns323_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, -- .dev = { .platform_data = &dns323_button_data, }, -+ .dev = { -+ .platform_data = &dns323_button_data, -+ }, - }; - - /**************************************************************************** - * General Setup - */ -- --static struct platform_device *dns323_plat_devices[] __initdata = { -- &dns323_nor_flash, -- &dns323_gpio_leds, -- &dns323_button_device, -+static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = { -+ { 0, MPP_PCIE_RST_OUTn }, -+ { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ -+ { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ -+ { 3, MPP_UNUSED }, -+ { 4, MPP_GPIO }, /* power button LED */ -+ { 5, MPP_GPIO }, /* power button LED */ -+ { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ -+ { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ -+ { 8, MPP_GPIO }, /* triggers power off */ -+ { 9, MPP_GPIO }, /* power button switch */ -+ { 10, MPP_GPIO }, /* reset button switch */ -+ { 11, MPP_UNUSED }, -+ { 12, MPP_UNUSED }, -+ { 13, MPP_UNUSED }, -+ { 14, MPP_UNUSED }, -+ { 15, MPP_UNUSED }, -+ { 16, MPP_UNUSED }, -+ { 17, MPP_UNUSED }, -+ { 18, MPP_UNUSED }, -+ { 19, MPP_UNUSED }, -+ { -1 }, - }; - - /* -@@ -225,17 +245,15 @@ - static struct i2c_board_info __initdata dns323_i2c_devices[] = { - { - I2C_BOARD_INFO("g760a", 0x3e), -- }, - #if 0 - /* this entry requires the new-style driver model lm75 driver, - * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */ -- { -+ }, { - I2C_BOARD_INFO("g751", 0x48), -- }, - #endif -- { -+ }, { - I2C_BOARD_INFO("m41t80", 0x68), -- } -+ }, - }; - - /* DNS-323 specific power off method */ -@@ -250,62 +268,35 @@ - /* Setup basic Orion functions. Need to be called early. */ - orion5x_init(); - -+ orion5x_mpp_conf(dns323_mpp_modes); -+ writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ -+ -+ /* -+ * Configure peripherals. -+ */ -+ orion5x_ehci0_init(); -+ orion5x_eth_init(&dns323_eth_data); -+ orion5x_i2c_init(); -+ orion5x_uart0_init(); -+ - /* setup flash mapping - * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 - */ - orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); -+ platform_device_register(&dns323_nor_flash); - -- /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIe -- * -- * Open a special address decode windows for the PCIe WA. -- */ -- orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, -- ORION5X_PCIE_WA_SIZE); -- -- /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ -- orion5x_write(MPP_0_7_CTRL, 0); -- orion5x_write(MPP_8_15_CTRL, 0); -- orion5x_write(MPP_16_19_CTRL, 0); -- orion5x_write(MPP_DEV_CTRL, 0); -- -- /* Define used GPIO pins -- -- GPIO Map: -- -- | 0 | | PEX_RST_OUT (not controlled by GPIO) -- | 1 | Out | right amber LED (= sata ch0 LED) (low-active) -- | 2 | Out | left amber LED (= sata ch1 LED) (low-active) -- | 3 | Out | //unknown// -- | 4 | Out | power button LED (low-active, together with pin #5) -- | 5 | Out | power button LED (low-active, together with pin #4) -- | 6 | In | GMT G751-2f overtemp. shutdown signal (low-active) -- | 7 | In | M41T80 nIRQ/OUT/SQW signal -- | 8 | Out | triggers power off (high-active) -- | 9 | In | power button switch (low-active) -- | 10 | In | reset button switch (low-active) -- | 11 | Out | //unknown// -- | 12 | Out | //unknown// -- | 13 | Out | //unknown// -- | 14 | Out | //unknown// -- | 15 | Out | //unknown// -- */ -- orion5x_gpio_set_valid_pins(0x07f6); -- -- /* register dns323 specific power-off method */ -- if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) -- || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)) -- pr_err("DNS323: failed to setup power-off GPIO\n"); -- -- pm_power_off = dns323_power_off; -+ platform_device_register(&dns323_gpio_leds); - -- /* register flash and other platform devices */ -- platform_add_devices(dns323_plat_devices, -- ARRAY_SIZE(dns323_plat_devices)); -+ platform_device_register(&dns323_button_device); - - i2c_register_board_info(0, dns323_i2c_devices, - ARRAY_SIZE(dns323_i2c_devices)); - -- orion5x_eth_init(&dns323_eth_data); -+ /* register dns323 specific power-off method */ -+ if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || -+ gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) -+ pr_err("DNS323: failed to setup power-off GPIO\n"); -+ pm_power_off = dns323_power_off; - } - - /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ ---- a/arch/arm/mach-orion5x/gpio.c -+++ b/arch/arm/mach-orion5x/gpio.c -@@ -24,9 +24,12 @@ - static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; - static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ - --void __init orion5x_gpio_set_valid_pins(u32 pins) -+void __init orion5x_gpio_set_valid(unsigned pin, int valid) - { -- gpio_valid[0] = pins; -+ if (valid) -+ __set_bit(pin, gpio_valid); -+ else -+ __clear_bit(pin, gpio_valid); - } - - /* -@@ -93,10 +96,10 @@ - { - int val, mask = 1 << pin; - -- if (orion5x_read(GPIO_IO_CONF) & mask) -- val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); -+ if (readl(GPIO_IO_CONF) & mask) -+ val = readl(GPIO_DATA_IN) ^ readl(GPIO_IN_POL); - else -- val = orion5x_read(GPIO_OUT); -+ val = readl(GPIO_OUT); - - return val & mask; - } -@@ -188,39 +191,39 @@ - printk("GPIO, free\n"); - } else { - printk("GPIO, used by %s, ", gpio_label[i]); -- if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { -+ if (readl(GPIO_IO_CONF) & (1 << i)) { - printk("input, active %s, level %s, edge %s\n", -- ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", -- ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", -- ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); -+ ((readl(GPIO_IN_POL) >> i) & 1) ? "low" : "high", -+ ((readl(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", -+ ((readl(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); - } else { -- printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); -+ printk("output, val=%d\n", (readl(GPIO_OUT) >> i) & 1); - } - } - } - - printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", -- MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); -+ MPP_0_7_CTRL, readl(MPP_0_7_CTRL)); - printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", -- MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); -+ MPP_8_15_CTRL, readl(MPP_8_15_CTRL)); - printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", -- MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); -+ MPP_16_19_CTRL, readl(MPP_16_19_CTRL)); - printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", -- MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); -+ MPP_DEV_CTRL, readl(MPP_DEV_CTRL)); - printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", -- GPIO_OUT, orion5x_read(GPIO_OUT)); -+ GPIO_OUT, readl(GPIO_OUT)); - printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", -- GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); -+ GPIO_IO_CONF, readl(GPIO_IO_CONF)); - printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", -- GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); -+ GPIO_BLINK_EN, readl(GPIO_BLINK_EN)); - printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", -- GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); -+ GPIO_IN_POL, readl(GPIO_IN_POL)); - printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", -- GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); -+ GPIO_DATA_IN, readl(GPIO_DATA_IN)); - printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", -- GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); -+ GPIO_LEVEL_MASK, readl(GPIO_LEVEL_MASK)); - printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", -- GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); -+ GPIO_EDGE_CAUSE, readl(GPIO_EDGE_CAUSE)); - printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", -- GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); -+ GPIO_EDGE_MASK, readl(GPIO_EDGE_MASK)); - } ---- a/arch/arm/mach-orion5x/irq.c -+++ b/arch/arm/mach-orion5x/irq.c -@@ -82,7 +82,7 @@ - int pin = irq_to_gpio(irq); - struct irq_desc *desc; - -- if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { -+ if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) { - printk(KERN_ERR "orion5x_gpio_set_irq_type failed " - "(irq %d, pin %d).\n", irq, pin); - return -EINVAL; -@@ -117,7 +117,7 @@ - /* - * set initial polarity based on current input level - */ -- if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) -+ if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN)) - & (1 << pin)) - orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ - else -@@ -149,8 +149,8 @@ - - BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); - offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; -- cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | -- (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); -+ cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) | -+ (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK)); - - for (pin = offs; pin < offs + 8; pin++) { - if (cause & (1 << pin)) { -@@ -158,9 +158,9 @@ - desc = irq_desc + irq; - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { - /* Swap polarity (race with GPIO line) */ -- u32 polarity = orion5x_read(GPIO_IN_POL); -+ u32 polarity = readl(GPIO_IN_POL); - polarity ^= 1 << pin; -- orion5x_write(GPIO_IN_POL, polarity); -+ writel(polarity, GPIO_IN_POL); - } - desc_handle_irq(irq, desc); - } -@@ -175,9 +175,9 @@ - /* - * Mask and clear GPIO IRQ interrupts - */ -- orion5x_write(GPIO_LEVEL_MASK, 0x0); -- orion5x_write(GPIO_EDGE_MASK, 0x0); -- orion5x_write(GPIO_EDGE_CAUSE, 0x0); -+ writel(0x0, GPIO_LEVEL_MASK); -+ writel(0x0, GPIO_EDGE_MASK); -+ writel(0x0, GPIO_EDGE_CAUSE); - - /* - * Register chained level handlers for GPIO IRQs by default. ---- a/arch/arm/mach-orion5x/kurobox_pro-setup.c -+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c -@@ -13,10 +13,12 @@ - #include - #include - #include -+#include - #include - #include - #include - #include -+#include - #include - #include - #include -@@ -25,6 +27,7 @@ - #include - #include - #include "common.h" -+#include "mpp.h" - - /***************************************************************************** - * KUROBOX-PRO Info -@@ -53,13 +56,11 @@ - .name = "uImage", - .offset = 0, - .size = SZ_4M, -- }, -- { -+ }, { - .name = "rootfs", - .offset = SZ_4M, - .size = SZ_64M, -- }, -- { -+ }, { - .name = "extra", - .offset = SZ_4M + SZ_64M, - .size = SZ_256M - (SZ_4M + SZ_64M), -@@ -132,8 +133,6 @@ - /* - * PCI isn't used on the Kuro - */ -- printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); -- - return -1; - } - -@@ -161,7 +160,6 @@ - - static struct mv643xx_eth_platform_data kurobox_pro_eth_data = { - .phy_addr = 8, -- .force_phy_addr = 1, - }; - - /***************************************************************************** -@@ -175,12 +173,169 @@ - * SATA - ****************************************************************************/ - static struct mv_sata_platform_data kurobox_pro_sata_data = { -- .n_ports = 2, -+ .n_ports = 2, - }; - - /***************************************************************************** -+ * Kurobox Pro specific power off method via UART1-attached microcontroller -+ ****************************************************************************/ -+ -+#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) -+ -+static int kurobox_pro_miconread(unsigned char *buf, int count) -+{ -+ int i; -+ int timeout; -+ -+ for (i = 0; i < count; i++) { -+ timeout = 10; -+ -+ while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) { -+ if (--timeout == 0) -+ break; -+ udelay(1000); -+ } -+ -+ if (timeout == 0) -+ break; -+ buf[i] = readl(UART1_REG(RX)); -+ } -+ -+ /* return read bytes */ -+ return i; -+} -+ -+static int kurobox_pro_miconwrite(const unsigned char *buf, int count) -+{ -+ int i = 0; -+ -+ while (count--) { -+ while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE)) -+ barrier(); -+ writel(buf[i++], UART1_REG(TX)); -+ } -+ -+ return 0; -+} -+ -+static int kurobox_pro_miconsend(const unsigned char *data, int count) -+{ -+ int i; -+ unsigned char checksum = 0; -+ unsigned char recv_buf[40]; -+ unsigned char send_buf[40]; -+ unsigned char correct_ack[3]; -+ int retry = 2; -+ -+ /* Generate checksum */ -+ for (i = 0; i < count; i++) -+ checksum -= data[i]; -+ -+ do { -+ /* Send data */ -+ kurobox_pro_miconwrite(data, count); -+ -+ /* send checksum */ -+ kurobox_pro_miconwrite(&checksum, 1); -+ -+ if (kurobox_pro_miconread(recv_buf, sizeof(recv_buf)) <= 3) { -+ printk(KERN_ERR ">%s: receive failed.\n", __func__); -+ -+ /* send preamble to clear the receive buffer */ -+ memset(&send_buf, 0xff, sizeof(send_buf)); -+ kurobox_pro_miconwrite(send_buf, sizeof(send_buf)); -+ -+ /* make dummy reads */ -+ mdelay(100); -+ kurobox_pro_miconread(recv_buf, sizeof(recv_buf)); -+ } else { -+ /* Generate expected ack */ -+ correct_ack[0] = 0x01; -+ correct_ack[1] = data[1]; -+ correct_ack[2] = 0x00; -+ -+ /* checksum Check */ -+ if ((recv_buf[0] + recv_buf[1] + recv_buf[2] + -+ recv_buf[3]) & 0xFF) { -+ printk(KERN_ERR ">%s: Checksum Error : " -+ "Received data[%02x, %02x, %02x, %02x]" -+ "\n", __func__, recv_buf[0], -+ recv_buf[1], recv_buf[2], recv_buf[3]); -+ } else { -+ /* Check Received Data */ -+ if (correct_ack[0] == recv_buf[0] && -+ correct_ack[1] == recv_buf[1] && -+ correct_ack[2] == recv_buf[2]) { -+ /* Interval for next command */ -+ mdelay(10); -+ -+ /* Receive ACK */ -+ return 0; -+ } -+ } -+ /* Received NAK or illegal Data */ -+ printk(KERN_ERR ">%s: Error : NAK or Illegal Data " -+ "Received\n", __func__); -+ } -+ } while (retry--); -+ -+ /* Interval for next command */ -+ mdelay(10); -+ -+ return -1; -+} -+ -+static void kurobox_pro_power_off(void) -+{ -+ const unsigned char watchdogkill[] = {0x01, 0x35, 0x00}; -+ const unsigned char shutdownwait[] = {0x00, 0x0c}; -+ const unsigned char poweroff[] = {0x00, 0x06}; -+ /* 38400 baud divisor */ -+ const unsigned divisor = ((ORION5X_TCLK + (8 * 38400)) / (16 * 38400)); -+ -+ pr_info("%s: triggering power-off...\n", __func__); -+ -+ /* hijack uart1 and reset into sane state (38400,8n1,even parity) */ -+ writel(0x83, UART1_REG(LCR)); -+ writel(divisor & 0xff, UART1_REG(DLL)); -+ writel((divisor >> 8) & 0xff, UART1_REG(DLM)); -+ writel(0x1b, UART1_REG(LCR)); -+ writel(0x00, UART1_REG(IER)); -+ writel(0x07, UART1_REG(FCR)); -+ writel(0x00, UART1_REG(MCR)); -+ -+ /* Send the commands to shutdown the Kurobox Pro */ -+ kurobox_pro_miconsend(watchdogkill, sizeof(watchdogkill)) ; -+ kurobox_pro_miconsend(shutdownwait, sizeof(shutdownwait)) ; -+ kurobox_pro_miconsend(poweroff, sizeof(poweroff)); -+} -+ -+/***************************************************************************** - * General Setup - ****************************************************************************/ -+static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = { -+ { 0, MPP_UNUSED }, -+ { 1, MPP_UNUSED }, -+ { 2, MPP_GPIO }, /* GPIO Micon */ -+ { 3, MPP_GPIO }, /* GPIO Rtc */ -+ { 4, MPP_UNUSED }, -+ { 5, MPP_UNUSED }, -+ { 6, MPP_NAND }, /* NAND Flash REn */ -+ { 7, MPP_NAND }, /* NAND Flash WEn */ -+ { 8, MPP_UNUSED }, -+ { 9, MPP_UNUSED }, -+ { 10, MPP_UNUSED }, -+ { 11, MPP_UNUSED }, -+ { 12, MPP_SATA_LED }, /* SATA 0 presence */ -+ { 13, MPP_SATA_LED }, /* SATA 1 presence */ -+ { 14, MPP_SATA_LED }, /* SATA 0 active */ -+ { 15, MPP_SATA_LED }, /* SATA 1 active */ -+ { 16, MPP_UART }, /* UART1 RXD */ -+ { 17, MPP_UART }, /* UART1 TXD */ -+ { 18, MPP_UART }, /* UART1 CTSn */ -+ { 19, MPP_UART }, /* UART1 RTSn */ -+ { -1 }, -+}; - - static void __init kurobox_pro_init(void) - { -@@ -189,46 +344,32 @@ - */ - orion5x_init(); - -- /* -- * Setup the CPU address decode windows for our devices -- */ -- orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, -- KUROBOX_PRO_NOR_BOOT_SIZE); -- orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); -+ orion5x_mpp_conf(kurobox_pro_mpp_modes); - - /* -- * Open a special address decode windows for the PCIe WA. -+ * Configure peripherals. - */ -- orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, -- ORION5X_PCIE_WA_SIZE); -- -- /* -- * Setup Multiplexing Pins -- -- * MPP[0-1] Not used -- * MPP[2] GPIO Micon -- * MPP[3] GPIO RTC -- * MPP[4-5] Not used -- * MPP[6] Nand Flash REn -- * MPP[7] Nand Flash WEn -- * MPP[8-11] Not used -- * MPP[12] SATA 0 presence Indication -- * MPP[13] SATA 1 presence Indication -- * MPP[14] SATA 0 active Indication -- * MPP[15] SATA 1 active indication -- * MPP[16-19] Not used -- */ -- orion5x_write(MPP_0_7_CTRL, 0x44220003); -- orion5x_write(MPP_8_15_CTRL, 0x55550000); -- orion5x_write(MPP_16_19_CTRL, 0x0); -- -- orion5x_gpio_set_valid_pins(0x0000000c); -+ orion5x_ehci0_init(); -+ orion5x_ehci1_init(); -+ orion5x_eth_init(&kurobox_pro_eth_data); -+ orion5x_i2c_init(); -+ orion5x_sata_init(&kurobox_pro_sata_data); -+ orion5x_uart0_init(); - -+ orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, -+ KUROBOX_PRO_NOR_BOOT_SIZE); - platform_device_register(&kurobox_pro_nor_flash); -- if (machine_is_kurobox_pro()) -+ -+ if (machine_is_kurobox_pro()) { -+ orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, -+ KUROBOX_PRO_NAND_SIZE); - platform_device_register(&kurobox_pro_nand_flash); -+ } -+ - i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); -- orion5x_eth_init(&kurobox_pro_eth_data); -- orion5x_sata_init(&kurobox_pro_sata_data); -+ -+ /* register Kurobox Pro specific power-off method */ -+ pm_power_off = kurobox_pro_power_off; - } - - #ifdef CONFIG_MACH_KUROBOX_PRO ---- /dev/null -+++ b/arch/arm/mach-orion5x/mpp.c -@@ -0,0 +1,163 @@ -+/* -+ * arch/arm/mach-orion5x/mpp.c -+ * -+ * MPP functions for Marvell Orion 5x SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+#include "mpp.h" -+ -+static int is_5181l(void) -+{ -+ u32 dev; -+ u32 rev; -+ -+ orion5x_pcie_id(&dev, &rev); -+ -+ return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0); -+} -+ -+static int is_5182(void) -+{ -+ u32 dev; -+ u32 rev; -+ -+ orion5x_pcie_id(&dev, &rev); -+ -+ return !!(dev == MV88F5182_DEV_ID); -+} -+ -+static int is_5281(void) -+{ -+ u32 dev; -+ u32 rev; -+ -+ orion5x_pcie_id(&dev, &rev); -+ -+ return !!(dev == MV88F5281_DEV_ID); -+} -+ -+static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type) -+{ -+ switch (type) { -+ case MPP_UNUSED: -+ case MPP_GPIO: -+ if (mpp == 0) -+ return 3; -+ if (mpp >= 1 && mpp <= 15) -+ return 0; -+ if (mpp >= 16 && mpp <= 19) { -+ if (is_5182()) -+ return 5; -+ if (type == MPP_UNUSED) -+ return 0; -+ } -+ return -1; -+ -+ case MPP_PCIE_RST_OUTn: -+ if (mpp == 0) -+ return 0; -+ return -1; -+ -+ case MPP_PCI_ARB: -+ if (mpp >= 0 && mpp <= 7) -+ return 2; -+ return -1; -+ -+ case MPP_PCI_PMEn: -+ if (mpp == 2) -+ return 3; -+ return -1; -+ -+ case MPP_GIGE: -+ if (mpp >= 8 && mpp <= 19) -+ return 1; -+ return -1; -+ -+ case MPP_NAND: -+ if (is_5182() || is_5281()) { -+ if (mpp >= 4 && mpp <= 7) -+ return 4; -+ if (mpp >= 12 && mpp <= 17) -+ return 4; -+ } -+ return -1; -+ -+ case MPP_PCI_CLK: -+ if (is_5181l() && mpp >= 6 && mpp <= 7) -+ return 5; -+ return -1; -+ -+ case MPP_SATA_LED: -+ if (is_5182()) { -+ if (mpp >= 4 && mpp <= 7) -+ return 5; -+ if (mpp >= 12 && mpp <= 15) -+ return 5; -+ } -+ return -1; -+ -+ case MPP_UART: -+ if (mpp >= 16 && mpp <= 19) -+ return 0; -+ return -1; -+ } -+ -+ printk(KERN_INFO "unknown MPP type %d\n", type); -+ -+ return -1; -+} -+ -+void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode) -+{ -+ u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL); -+ u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL); -+ u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL); -+ -+ while (mode->mpp >= 0) { -+ u32 *reg; -+ int num_type; -+ int shift; -+ -+ if (mode->mpp >= 0 && mode->mpp <= 7) -+ reg = &mpp_0_7_ctrl; -+ else if (mode->mpp >= 8 && mode->mpp <= 15) -+ reg = &mpp_8_15_ctrl; -+ else if (mode->mpp >= 16 && mode->mpp <= 19) -+ reg = &mpp_16_19_ctrl; -+ else { -+ printk(KERN_ERR "orion5x_mpp_conf: invalid MPP " -+ "(%d)\n", mode->mpp); -+ continue; -+ } -+ -+ num_type = determine_type_encoding(mode->mpp, mode->type); -+ if (num_type < 0) { -+ printk(KERN_ERR "orion5x_mpp_conf: invalid MPP " -+ "combination (%d, %d)\n", mode->mpp, -+ mode->type); -+ continue; -+ } -+ -+ shift = (mode->mpp & 7) << 2; -+ *reg &= ~(0xf << shift); -+ *reg |= (num_type & 0xf) << shift; -+ -+ orion5x_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO)); -+ -+ mode++; -+ } -+ -+ writel(mpp_0_7_ctrl, MPP_0_7_CTRL); -+ writel(mpp_8_15_ctrl, MPP_8_15_CTRL); -+ writel(mpp_16_19_ctrl, MPP_16_19_CTRL); -+} ---- /dev/null -+++ b/arch/arm/mach-orion5x/mpp.h -@@ -0,0 +1,74 @@ -+#ifndef __ARCH_ORION5X_MPP_H -+#define __ARCH_ORION5X_MPP_H -+ -+enum orion5x_mpp_type { -+ /* -+ * This MPP is unused. -+ */ -+ MPP_UNUSED, -+ -+ /* -+ * This MPP pin is used as a generic GPIO pin. Valid for -+ * MPPs 0-15 and device bus data pins 16-31. On 5182, also -+ * valid for MPPs 16-19. -+ */ -+ MPP_GPIO, -+ -+ /* -+ * This MPP is used as PCIe_RST_OUTn pin. Valid for -+ * MPP 0 only. -+ */ -+ MPP_PCIE_RST_OUTn, -+ -+ /* -+ * This MPP is used as PCI arbiter pin (REQn/GNTn). -+ * Valid for MPPs 0-7 only. -+ */ -+ MPP_PCI_ARB, -+ -+ /* -+ * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only. -+ */ -+ MPP_PCI_PMEn, -+ -+ /* -+ * This MPP is used as GigE half-duplex (COL, CRS) or GMII -+ * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for -+ * MPPs 8-19 only. -+ */ -+ MPP_GIGE, -+ -+ /* -+ * This MPP is used as NAND REn/WEn pin. Valid for MPPs -+ * 4-7 and 12-17 only, and only on the 5181l/5182/5281. -+ */ -+ MPP_NAND, -+ -+ /* -+ * This MPP is used as a PCI clock output pin. Valid for -+ * MPPs 6-7 only, and only on the 5181l. -+ */ -+ MPP_PCI_CLK, -+ -+ /* -+ * This MPP is used as a SATA presence/activity LED. -+ * Valid for MPPs 4-7 and 12-15 only, and only on the 5182. -+ */ -+ MPP_SATA_LED, -+ -+ /* -+ * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin. -+ * Valid for MPPs 16-19 only. -+ */ -+ MPP_UART, -+}; -+ -+struct orion5x_mpp_mode { -+ int mpp; -+ enum orion5x_mpp_type type; -+}; -+ -+void orion5x_mpp_conf(struct orion5x_mpp_mode *mode); -+ -+ -+#endif ---- /dev/null -+++ b/arch/arm/mach-orion5x/mss2-setup.c -@@ -0,0 +1,270 @@ -+/* -+ * Maxtor Shared Storage II Board Setup -+ * -+ * Maintainer: Sylver Bruneau -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+#include "mpp.h" -+ -+#define MSS2_NOR_BOOT_BASE 0xff800000 -+#define MSS2_NOR_BOOT_SIZE SZ_256K -+ -+/***************************************************************************** -+ * Maxtor Shared Storage II Info -+ ****************************************************************************/ -+ -+/* -+ * Maxtor Shared Storage II hardware : -+ * - Marvell 88F5182-A2 C500 -+ * - Marvell 88E1111 Gigabit Ethernet PHY -+ * - RTC M41T81 (@0x68) on I2C bus -+ * - 256KB NOR flash -+ * - 64MB of RAM -+ */ -+ -+/***************************************************************************** -+ * 256KB NOR Flash on BOOT Device -+ ****************************************************************************/ -+ -+static struct physmap_flash_data mss2_nor_flash_data = { -+ .width = 1, -+}; -+ -+static struct resource mss2_nor_flash_resource = { -+ .flags = IORESOURCE_MEM, -+ .start = MSS2_NOR_BOOT_BASE, -+ .end = MSS2_NOR_BOOT_BASE + MSS2_NOR_BOOT_SIZE - 1, -+}; -+ -+static struct platform_device mss2_nor_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev = { -+ .platform_data = &mss2_nor_flash_data, -+ }, -+ .resource = &mss2_nor_flash_resource, -+ .num_resources = 1, -+}; -+ -+/**************************************************************************** -+ * PCI setup -+ ****************************************************************************/ -+static int __init mss2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ int irq; -+ -+ /* -+ * Check for devices with hard-wired IRQs. -+ */ -+ irq = orion5x_pci_map_irq(dev, slot, pin); -+ if (irq != -1) -+ return irq; -+ -+ return -1; -+} -+ -+static struct hw_pci mss2_pci __initdata = { -+ .nr_controllers = 2, -+ .swizzle = pci_std_swizzle, -+ .setup = orion5x_pci_sys_setup, -+ .scan = orion5x_pci_sys_scan_bus, -+ .map_irq = mss2_pci_map_irq, -+}; -+ -+static int __init mss2_pci_init(void) -+{ -+ if (machine_is_mss2()) -+ pci_common_init(&mss2_pci); -+ -+ return 0; -+} -+subsys_initcall(mss2_pci_init); -+ -+ -+/***************************************************************************** -+ * Ethernet -+ ****************************************************************************/ -+ -+static struct mv643xx_eth_platform_data mss2_eth_data = { -+ .phy_addr = 8, -+}; -+ -+/***************************************************************************** -+ * SATA -+ ****************************************************************************/ -+ -+static struct mv_sata_platform_data mss2_sata_data = { -+ .n_ports = 2, -+}; -+ -+/***************************************************************************** -+ * GPIO buttons -+ ****************************************************************************/ -+ -+#define MSS2_GPIO_KEY_RESET 12 -+#define MSS2_GPIO_KEY_POWER 11 -+ -+static struct gpio_keys_button mss2_buttons[] = { -+ { -+ .code = KEY_POWER, -+ .gpio = MSS2_GPIO_KEY_POWER, -+ .desc = "Power", -+ .active_low = 1, -+ }, { -+ .code = KEY_RESTART, -+ .gpio = MSS2_GPIO_KEY_RESET, -+ .desc = "Reset", -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_keys_platform_data mss2_button_data = { -+ .buttons = mss2_buttons, -+ .nbuttons = ARRAY_SIZE(mss2_buttons), -+}; -+ -+static struct platform_device mss2_button_device = { -+ .name = "gpio-keys", -+ .id = -1, -+ .dev = { -+ .platform_data = &mss2_button_data, -+ }, -+}; -+ -+/***************************************************************************** -+ * RTC m41t81 on I2C bus -+ ****************************************************************************/ -+ -+#define MSS2_GPIO_RTC_IRQ 3 -+ -+static struct i2c_board_info __initdata mss2_i2c_rtc = { -+ I2C_BOARD_INFO("m41t81", 0x68), -+}; -+ -+/***************************************************************************** -+ * MSS2 power off method -+ ****************************************************************************/ -+/* -+ * On the Maxtor Shared Storage II, the shutdown process is the following : -+ * - Userland modifies U-boot env to tell U-boot to go idle at next boot -+ * - The board reboots -+ * - U-boot starts and go into an idle mode until the user press "power" -+ */ -+static void mss2_power_off(void) -+{ -+ u32 reg; -+ -+ /* -+ * Enable and issue soft reset -+ */ -+ reg = readl(CPU_RESET_MASK); -+ reg |= 1 << 2; -+ writel(reg, CPU_RESET_MASK); -+ -+ reg = readl(CPU_SOFT_RESET); -+ reg |= 1; -+ writel(reg, CPU_SOFT_RESET); -+} -+ -+/**************************************************************************** -+ * General Setup -+ ****************************************************************************/ -+static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = { -+ { 0, MPP_GPIO }, /* Power LED */ -+ { 1, MPP_GPIO }, /* Error LED */ -+ { 2, MPP_UNUSED }, -+ { 3, MPP_GPIO }, /* RTC interrupt */ -+ { 4, MPP_GPIO }, /* HDD ind. (Single/Dual)*/ -+ { 5, MPP_GPIO }, /* HD0 5V control */ -+ { 6, MPP_GPIO }, /* HD0 12V control */ -+ { 7, MPP_GPIO }, /* HD1 5V control */ -+ { 8, MPP_GPIO }, /* HD1 12V control */ -+ { 9, MPP_UNUSED }, -+ { 10, MPP_GPIO }, /* Fan control */ -+ { 11, MPP_GPIO }, /* Power button */ -+ { 12, MPP_GPIO }, /* Reset button */ -+ { 13, MPP_UNUSED }, -+ { 14, MPP_SATA_LED }, /* SATA 0 active */ -+ { 15, MPP_SATA_LED }, /* SATA 1 active */ -+ { 16, MPP_UNUSED }, -+ { 17, MPP_UNUSED }, -+ { 18, MPP_UNUSED }, -+ { 19, MPP_UNUSED }, -+ { -1 }, -+}; -+ -+static void __init mss2_init(void) -+{ -+ /* Setup basic Orion functions. Need to be called early. */ -+ orion5x_init(); -+ -+ orion5x_mpp_conf(mss2_mpp_modes); -+ -+ /* -+ * MPP[20] Unused -+ * MPP[21] PCI clock -+ * MPP[22] USB 0 over current -+ * MPP[23] USB 1 over current -+ */ -+ -+ /* -+ * Configure peripherals. -+ */ -+ orion5x_ehci0_init(); -+ orion5x_ehci1_init(); -+ orion5x_eth_init(&mss2_eth_data); -+ orion5x_i2c_init(); -+ orion5x_sata_init(&mss2_sata_data); -+ orion5x_uart0_init(); -+ -+ orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE); -+ platform_device_register(&mss2_nor_flash); -+ -+ platform_device_register(&mss2_button_device); -+ -+ if (gpio_request(MSS2_GPIO_RTC_IRQ, "rtc") == 0) { -+ if (gpio_direction_input(MSS2_GPIO_RTC_IRQ) == 0) -+ mss2_i2c_rtc.irq = gpio_to_irq(MSS2_GPIO_RTC_IRQ); -+ else -+ gpio_free(MSS2_GPIO_RTC_IRQ); -+ } -+ i2c_register_board_info(0, &mss2_i2c_rtc, 1); -+ -+ /* register mss2 specific power-off method */ -+ pm_power_off = mss2_power_off; -+} -+ -+MACHINE_START(MSS2, "Maxtor Shared Storage II") -+ /* Maintainer: Sylver Bruneau */ -+ .phys_io = ORION5X_REGS_PHYS_BASE, -+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, -+ .boot_params = 0x00000100, -+ .init_machine = mss2_init, -+ .map_io = orion5x_map_io, -+ .init_irq = orion5x_init_irq, -+ .timer = &orion5x_timer, -+ .fixup = tag_fixup_mem32 -+MACHINE_END ---- /dev/null -+++ b/arch/arm/mach-orion5x/mv2120-setup.c -@@ -0,0 +1,194 @@ -+/* -+ * Copyright (C) 2007 Herbert Valerio Riedel -+ * Copyright (C) 2008 Martin Michlmayr -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+#include "mpp.h" -+ -+#define MV2120_NOR_BOOT_BASE 0xf4000000 -+#define MV2120_NOR_BOOT_SIZE SZ_512K -+ -+#define MV2120_GPIO_RTC_IRQ 3 -+#define MV2120_GPIO_KEY_RESET 17 -+#define MV2120_GPIO_KEY_POWER 18 -+#define MV2120_GPIO_POWER_OFF 19 -+ -+ -+/***************************************************************************** -+ * Ethernet -+ ****************************************************************************/ -+static struct mv643xx_eth_platform_data mv2120_eth_data = { -+ .phy_addr = 8, -+}; -+ -+static struct mv_sata_platform_data mv2120_sata_data = { -+ .n_ports = 2, -+}; -+ -+static struct mtd_partition mv2120_partitions[] = { -+ { -+ .name = "firmware", -+ .size = 0x00080000, -+ .offset = 0, -+ }, -+}; -+ -+static struct physmap_flash_data mv2120_nor_flash_data = { -+ .width = 1, -+ .parts = mv2120_partitions, -+ .nr_parts = ARRAY_SIZE(mv2120_partitions) -+}; -+ -+static struct resource mv2120_nor_flash_resource = { -+ .flags = IORESOURCE_MEM, -+ .start = MV2120_NOR_BOOT_BASE, -+ .end = MV2120_NOR_BOOT_BASE + MV2120_NOR_BOOT_SIZE - 1, -+}; -+ -+static struct platform_device mv2120_nor_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev = { -+ .platform_data = &mv2120_nor_flash_data, -+ }, -+ .resource = &mv2120_nor_flash_resource, -+ .num_resources = 1, -+}; -+ -+static struct gpio_keys_button mv2120_buttons[] = { -+ { -+ .code = KEY_RESTART, -+ .gpio = MV2120_GPIO_KEY_RESET, -+ .desc = "reset", -+ .active_low = 1, -+ }, { -+ .code = KEY_POWER, -+ .gpio = MV2120_GPIO_KEY_POWER, -+ .desc = "power", -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_keys_platform_data mv2120_button_data = { -+ .buttons = mv2120_buttons, -+ .nbuttons = ARRAY_SIZE(mv2120_buttons), -+}; -+ -+static struct platform_device mv2120_button_device = { -+ .name = "gpio-keys", -+ .id = -1, -+ .num_resources = 0, -+ .dev = { -+ .platform_data = &mv2120_button_data, -+ }, -+}; -+ -+ -+/**************************************************************************** -+ * General Setup -+ ****************************************************************************/ -+static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = { -+ { 0, MPP_GPIO }, /* Sys status LED */ -+ { 1, MPP_GPIO }, /* Sys error LED */ -+ { 2, MPP_GPIO }, /* OverTemp interrupt */ -+ { 3, MPP_GPIO }, /* RTC interrupt */ -+ { 4, MPP_GPIO }, /* V_LED 5V */ -+ { 5, MPP_GPIO }, /* V_LED 3.3V */ -+ { 6, MPP_UNUSED }, -+ { 7, MPP_UNUSED }, -+ { 8, MPP_GPIO }, /* SATA 0 fail LED */ -+ { 9, MPP_GPIO }, /* SATA 1 fail LED */ -+ { 10, MPP_UNUSED }, -+ { 11, MPP_UNUSED }, -+ { 12, MPP_SATA_LED }, /* SATA 0 presence */ -+ { 13, MPP_SATA_LED }, /* SATA 1 presence */ -+ { 14, MPP_SATA_LED }, /* SATA 0 active */ -+ { 15, MPP_SATA_LED }, /* SATA 1 active */ -+ { 16, MPP_UNUSED }, -+ { 17, MPP_GPIO }, /* Reset button */ -+ { 18, MPP_GPIO }, /* Power button */ -+ { 19, MPP_GPIO }, /* Power off */ -+ { -1 }, -+}; -+ -+static struct i2c_board_info __initdata mv2120_i2c_rtc = { -+ I2C_BOARD_INFO("rtc-pcf8563", 0x51), -+ .irq = 0, -+}; -+ -+static void mv2120_power_off(void) -+{ -+ pr_info("%s: triggering power-off...\n", __func__); -+ gpio_set_value(MV2120_GPIO_POWER_OFF, 0); -+} -+ -+static void __init mv2120_init(void) -+{ -+ /* Setup basic Orion functions. Need to be called early. */ -+ orion5x_init(); -+ -+ orion5x_mpp_conf(mv2120_mpp_modes); -+ -+ /* -+ * Configure peripherals. -+ */ -+ orion5x_ehci0_init(); -+ orion5x_ehci1_init(); -+ orion5x_eth_init(&mv2120_eth_data); -+ orion5x_i2c_init(); -+ orion5x_sata_init(&mv2120_sata_data); -+ orion5x_uart0_init(); -+ -+ orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE); -+ platform_device_register(&mv2120_nor_flash); -+ -+ platform_device_register(&mv2120_button_device); -+ -+ if (gpio_request(MV2120_GPIO_RTC_IRQ, "rtc") == 0) { -+ if (gpio_direction_input(MV2120_GPIO_RTC_IRQ) == 0) -+ mv2120_i2c_rtc.irq = gpio_to_irq(MV2120_GPIO_RTC_IRQ); -+ else -+ gpio_free(MV2120_GPIO_RTC_IRQ); -+ } -+ i2c_register_board_info(0, &mv2120_i2c_rtc, 1); -+ -+ /* register mv2120 specific power-off method */ -+ if (gpio_request(MV2120_GPIO_POWER_OFF, "POWEROFF") != 0 || -+ gpio_direction_output(MV2120_GPIO_POWER_OFF, 1) != 0) -+ pr_err("mv2120: failed to setup power-off GPIO\n"); -+ pm_power_off = mv2120_power_off; -+} -+ -+/* Warning: HP uses a wrong mach-type (=526) in their bootloader */ -+MACHINE_START(MV2120, "HP Media Vault mv2120") -+ /* Maintainer: Martin Michlmayr */ -+ .phys_io = ORION5X_REGS_PHYS_BASE, -+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, -+ .boot_params = 0x00000100, -+ .init_machine = mv2120_init, -+ .map_io = orion5x_map_io, -+ .init_irq = orion5x_init_irq, -+ .timer = &orion5x_timer, -+ .fixup = tag_fixup_mem32 -+MACHINE_END ---- a/arch/arm/mach-orion5x/pci.c -+++ b/arch/arm/mach-orion5x/pci.c -@@ -152,6 +152,8 @@ - if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { - printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " - "read transaction workaround\n"); -+ orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, -+ ORION5X_PCIE_WA_SIZE); - pcie_ops.read = pcie_rd_conf_wa; - } - -@@ -240,13 +242,13 @@ - * PCI Address Decode Windows registers - */ - #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ -- ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ -- ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ -- ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) --#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ -- ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ -- ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ -- ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) -+ ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ -+ ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ -+ ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) -+#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ -+ ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ -+ ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ -+ ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) - #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) - #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) - -@@ -266,7 +268,7 @@ - - static int orion5x_pci_local_bus_nr(void) - { -- u32 conf = orion5x_read(PCI_P2P_CONF); -+ u32 conf = readl(PCI_P2P_CONF); - return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); - } - -@@ -276,11 +278,11 @@ - unsigned long flags; - spin_lock_irqsave(&orion5x_pci_lock, flags); - -- orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | -- PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | -- PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); -+ writel(PCI_CONF_BUS(bus) | -+ PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | -+ PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); - -- *val = orion5x_read(PCI_CONF_DATA); -+ *val = readl(PCI_CONF_DATA); - - if (size == 1) - *val = (*val >> (8*(where & 0x3))) & 0xff; -@@ -300,9 +302,9 @@ - - spin_lock_irqsave(&orion5x_pci_lock, flags); - -- orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | -- PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | -- PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); -+ writel(PCI_CONF_BUS(bus) | -+ PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | -+ PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); - - if (size == 4) { - __raw_writel(val, PCI_CONF_DATA); -@@ -353,9 +355,9 @@ - - static void __init orion5x_pci_set_bus_nr(int nr) - { -- u32 p2p = orion5x_read(PCI_P2P_CONF); -+ u32 p2p = readl(PCI_P2P_CONF); - -- if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { -+ if (readl(PCI_MODE) & PCI_MODE_PCIX) { - /* - * PCI-X mode - */ -@@ -372,7 +374,7 @@ - */ - p2p &= ~PCI_P2P_BUS_MASK; - p2p |= (nr << PCI_P2P_BUS_OFFS); -- orion5x_write(PCI_P2P_CONF, p2p); -+ writel(p2p, PCI_P2P_CONF); - } - } - -@@ -399,7 +401,7 @@ - * First, disable windows. - */ - win_enable = 0xffffffff; -- orion5x_write(PCI_BAR_ENABLE, win_enable); -+ writel(win_enable, PCI_BAR_ENABLE); - - /* - * Setup windows for DDR banks. -@@ -425,10 +427,10 @@ - */ - reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); - orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); -- orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), -- (cs->size - 1) & 0xfffff000); -- orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), -- cs->base & 0xfffff000); -+ writel((cs->size - 1) & 0xfffff000, -+ PCI_BAR_SIZE_DDR_CS(cs->cs_index)); -+ writel(cs->base & 0xfffff000, -+ PCI_BAR_REMAP_DDR_CS(cs->cs_index)); - - /* - * Enable decode window for this chip select. -@@ -439,7 +441,7 @@ - /* - * Re-enable decode windows. - */ -- orion5x_write(PCI_BAR_ENABLE, win_enable); -+ writel(win_enable, PCI_BAR_ENABLE); - - /* - * Disable automatic update of address remaping when writing to BARs. ---- a/arch/arm/mach-orion5x/rd88f5182-setup.c -+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c -@@ -26,6 +26,7 @@ - #include - #include - #include "common.h" -+#include "mpp.h" - - /***************************************************************************** - * RD-88F5182 Info -@@ -125,6 +126,7 @@ - - leds_event = rd88f5182_dbgled_event; - } -+ - return 0; - } - -@@ -220,7 +222,6 @@ - - static struct mv643xx_eth_platform_data rd88f5182_eth_data = { - .phy_addr = 8, -- .force_phy_addr = 1, - }; - - /***************************************************************************** -@@ -234,15 +235,34 @@ - * Sata - ****************************************************************************/ - static struct mv_sata_platform_data rd88f5182_sata_data = { -- .n_ports = 2, -+ .n_ports = 2, - }; - - /***************************************************************************** - * General Setup - ****************************************************************************/ -- --static struct platform_device *rd88f5182_devices[] __initdata = { -- &rd88f5182_nor_flash, -+static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = { -+ { 0, MPP_GPIO }, /* Debug Led */ -+ { 1, MPP_GPIO }, /* Reset Switch */ -+ { 2, MPP_UNUSED }, -+ { 3, MPP_GPIO }, /* RTC Int */ -+ { 4, MPP_GPIO }, -+ { 5, MPP_GPIO }, -+ { 6, MPP_GPIO }, /* PCI_intA */ -+ { 7, MPP_GPIO }, /* PCI_intB */ -+ { 8, MPP_UNUSED }, -+ { 9, MPP_UNUSED }, -+ { 10, MPP_UNUSED }, -+ { 11, MPP_UNUSED }, -+ { 12, MPP_SATA_LED }, /* SATA 0 presence */ -+ { 13, MPP_SATA_LED }, /* SATA 1 presence */ -+ { 14, MPP_SATA_LED }, /* SATA 0 active */ -+ { 15, MPP_SATA_LED }, /* SATA 1 active */ -+ { 16, MPP_UNUSED }, -+ { 17, MPP_UNUSED }, -+ { 18, MPP_UNUSED }, -+ { 19, MPP_UNUSED }, -+ { -1 }, - }; - - static void __init rd88f5182_init(void) -@@ -252,35 +272,9 @@ - */ - orion5x_init(); - -- /* -- * Setup the CPU address decode windows for our devices -- */ -- orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, -- RD88F5182_NOR_BOOT_SIZE); -- orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); -- -- /* -- * Open a special address decode windows for the PCIe WA. -- */ -- orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, -- ORION5X_PCIE_WA_SIZE); -+ orion5x_mpp_conf(rd88f5182_mpp_modes); - - /* -- * Setup Multiplexing Pins -- -- * MPP[0] Debug Led (GPIO - Out) -- * MPP[1] Debug Led (GPIO - Out) -- * MPP[2] N/A -- * MPP[3] RTC_Int (GPIO - In) -- * MPP[4] GPIO -- * MPP[5] GPIO -- * MPP[6] PCI_intA (GPIO - In) -- * MPP[7] PCI_intB (GPIO - In) -- * MPP[8-11] N/A -- * MPP[12] SATA 0 presence Indication -- * MPP[13] SATA 1 presence Indication -- * MPP[14] SATA 0 active Indication -- * MPP[15] SATA 1 active indication -- * MPP[16-19] Not used - * MPP[20] PCI Clock to MV88F5182 - * MPP[21] PCI Clock to mini PCI CON11 - * MPP[22] USB 0 over current indication -@@ -289,16 +283,23 @@ - * MPP[25] USB 0 over current enable - */ - -- orion5x_write(MPP_0_7_CTRL, 0x00000003); -- orion5x_write(MPP_8_15_CTRL, 0x55550000); -- orion5x_write(MPP_16_19_CTRL, 0x5555); -+ /* -+ * Configure peripherals. -+ */ -+ orion5x_ehci0_init(); -+ orion5x_ehci1_init(); -+ orion5x_eth_init(&rd88f5182_eth_data); -+ orion5x_i2c_init(); -+ orion5x_sata_init(&rd88f5182_sata_data); -+ orion5x_uart0_init(); - -- orion5x_gpio_set_valid_pins(0x000000fb); -+ orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, -+ RD88F5182_NOR_BOOT_SIZE); -+ -+ orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); -+ platform_device_register(&rd88f5182_nor_flash); - -- platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); - i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); -- orion5x_eth_init(&rd88f5182_eth_data); -- orion5x_sata_init(&rd88f5182_sata_data); - } - - MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") ---- a/arch/arm/mach-orion5x/ts209-setup.c -+++ b/arch/arm/mach-orion5x/ts209-setup.c -@@ -28,6 +28,8 @@ - #include - #include - #include "common.h" -+#include "mpp.h" -+#include "tsx09-common.h" - - #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 - #define QNAP_TS209_NOR_BOOT_SIZE SZ_8M -@@ -47,52 +49,54 @@ - ***************************************************************************/ - static struct mtd_partition qnap_ts209_partitions[] = { - { -- .name = "U-Boot", -- .size = 0x00080000, -- .offset = 0x00780000, -- .mask_flags = MTD_WRITEABLE, -+ .name = "U-Boot", -+ .size = 0x00080000, -+ .offset = 0x00780000, -+ .mask_flags = MTD_WRITEABLE, - }, { -- .name = "Kernel", -- .size = 0x00200000, -- .offset = 0, -+ .name = "Kernel", -+ .size = 0x00200000, -+ .offset = 0, - }, { -- .name = "RootFS1", -- .size = 0x00400000, -- .offset = 0x00200000, -+ .name = "RootFS1", -+ .size = 0x00400000, -+ .offset = 0x00200000, - }, { -- .name = "RootFS2", -- .size = 0x00100000, -- .offset = 0x00600000, -+ .name = "RootFS2", -+ .size = 0x00100000, -+ .offset = 0x00600000, - }, { -- .name = "U-Boot Config", -- .size = 0x00020000, -- .offset = 0x00760000, -+ .name = "U-Boot Config", -+ .size = 0x00020000, -+ .offset = 0x00760000, - }, { -- .name = "NAS Config", -- .size = 0x00060000, -- .offset = 0x00700000, -- .mask_flags = MTD_WRITEABLE, -- } -+ .name = "NAS Config", -+ .size = 0x00060000, -+ .offset = 0x00700000, -+ .mask_flags = MTD_WRITEABLE, -+ }, - }; - - static struct physmap_flash_data qnap_ts209_nor_flash_data = { -- .width = 1, -- .parts = qnap_ts209_partitions, -- .nr_parts = ARRAY_SIZE(qnap_ts209_partitions) -+ .width = 1, -+ .parts = qnap_ts209_partitions, -+ .nr_parts = ARRAY_SIZE(qnap_ts209_partitions) - }; - - static struct resource qnap_ts209_nor_flash_resource = { -- .flags = IORESOURCE_MEM, -- .start = QNAP_TS209_NOR_BOOT_BASE, -- .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ .start = QNAP_TS209_NOR_BOOT_BASE, -+ .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1, - }; - - static struct platform_device qnap_ts209_nor_flash = { -- .name = "physmap-flash", -- .id = 0, -- .dev = { .platform_data = &qnap_ts209_nor_flash_data, }, -- .resource = &qnap_ts209_nor_flash_resource, -- .num_resources = 1, -+ .name = "physmap-flash", -+ .id = 0, -+ .dev = { -+ .platform_data = &qnap_ts209_nor_flash_data, -+ }, -+ .resource = &qnap_ts209_nor_flash_resource, -+ .num_resources = 1, - }; - - /***************************************************************************** -@@ -164,12 +168,12 @@ - } - - static struct hw_pci qnap_ts209_pci __initdata = { -- .nr_controllers = 2, -- .preinit = qnap_ts209_pci_preinit, -- .swizzle = pci_std_swizzle, -- .setup = orion5x_pci_sys_setup, -- .scan = orion5x_pci_sys_scan_bus, -- .map_irq = qnap_ts209_pci_map_irq, -+ .nr_controllers = 2, -+ .preinit = qnap_ts209_pci_preinit, -+ .swizzle = pci_std_swizzle, -+ .setup = orion5x_pci_sys_setup, -+ .scan = orion5x_pci_sys_scan_bus, -+ .map_irq = qnap_ts209_pci_map_irq, - }; - - static int __init qnap_ts209_pci_init(void) -@@ -183,96 +187,6 @@ - subsys_initcall(qnap_ts209_pci_init); - - /***************************************************************************** -- * Ethernet -- ****************************************************************************/ -- --static struct mv643xx_eth_platform_data qnap_ts209_eth_data = { -- .phy_addr = 8, -- .force_phy_addr = 1, --}; -- --static int __init parse_hex_nibble(char n) --{ -- if (n >= '0' && n <= '9') -- return n - '0'; -- -- if (n >= 'A' && n <= 'F') -- return n - 'A' + 10; -- -- if (n >= 'a' && n <= 'f') -- return n - 'a' + 10; -- -- return -1; --} -- --static int __init parse_hex_byte(const char *b) --{ -- int hi; -- int lo; -- -- hi = parse_hex_nibble(b[0]); -- lo = parse_hex_nibble(b[1]); -- -- if (hi < 0 || lo < 0) -- return -1; -- -- return (hi << 4) | lo; --} -- --static int __init check_mac_addr(const char *addr_str) --{ -- u_int8_t addr[6]; -- int i; -- -- for (i = 0; i < 6; i++) { -- int byte; -- -- /* -- * Enforce "xx:xx:xx:xx:xx:xx\n" format. -- */ -- if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n')) -- return -1; -- -- byte = parse_hex_byte(addr_str + (i * 3)); -- if (byte < 0) -- return -1; -- addr[i] = byte; -- } -- -- printk(KERN_INFO "ts209: found ethernet mac address "); -- for (i = 0; i < 6; i++) -- printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); -- -- memcpy(qnap_ts209_eth_data.mac_addr, addr, 6); -- -- return 0; --} -- --/* -- * The 'NAS Config' flash partition has an ext2 filesystem which -- * contains a file that has the ethernet MAC address in plain text -- * (format "xx:xx:xx:xx:xx:xx\n".) -- */ --static void __init ts209_find_mac_addr(void) --{ -- unsigned long addr; -- -- for (addr = 0x00700000; addr < 0x00760000; addr += 1024) { -- char *nor_page; -- int ret = 0; -- -- nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024); -- if (nor_page != NULL) { -- ret = check_mac_addr(nor_page); -- iounmap(nor_page); -- } -- -- if (ret == 0) -- break; -- } --} -- --/***************************************************************************** - * RTC S35390A on I2C bus - ****************************************************************************/ - -@@ -280,7 +194,7 @@ - - static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = { - I2C_BOARD_INFO("s35390a", 0x30), -- .irq = 0, -+ .irq = 0, - }; - - /**************************************************************************** -@@ -297,70 +211,63 @@ - .gpio = QNAP_TS209_GPIO_KEY_MEDIA, - .desc = "USB Copy Button", - .active_low = 1, -- }, -- { -+ }, { - .code = KEY_POWER, - .gpio = QNAP_TS209_GPIO_KEY_RESET, - .desc = "Reset Button", - .active_low = 1, -- } -+ }, - }; - - static struct gpio_keys_platform_data qnap_ts209_button_data = { - .buttons = qnap_ts209_buttons, -- .nbuttons = ARRAY_SIZE(qnap_ts209_buttons), -+ .nbuttons = ARRAY_SIZE(qnap_ts209_buttons), - }; - - static struct platform_device qnap_ts209_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, -- .dev = { .platform_data = &qnap_ts209_button_data, }, -+ .dev = { -+ .platform_data = &qnap_ts209_button_data, -+ }, - }; - - /***************************************************************************** - * SATA - ****************************************************************************/ - static struct mv_sata_platform_data qnap_ts209_sata_data = { -- .n_ports = 2, -+ .n_ports = 2, - }; - - /***************************************************************************** - - * General Setup - ****************************************************************************/ -- --static struct platform_device *qnap_ts209_devices[] __initdata = { -- &qnap_ts209_nor_flash, -- &qnap_ts209_button_device, -+static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = { -+ { 0, MPP_UNUSED }, -+ { 1, MPP_GPIO }, /* USB copy button */ -+ { 2, MPP_GPIO }, /* Load defaults button */ -+ { 3, MPP_GPIO }, /* GPIO RTC */ -+ { 4, MPP_UNUSED }, -+ { 5, MPP_UNUSED }, -+ { 6, MPP_GPIO }, /* PCI Int A */ -+ { 7, MPP_GPIO }, /* PCI Int B */ -+ { 8, MPP_UNUSED }, -+ { 9, MPP_UNUSED }, -+ { 10, MPP_UNUSED }, -+ { 11, MPP_UNUSED }, -+ { 12, MPP_SATA_LED }, /* SATA 0 presence */ -+ { 13, MPP_SATA_LED }, /* SATA 1 presence */ -+ { 14, MPP_SATA_LED }, /* SATA 0 active */ -+ { 15, MPP_SATA_LED }, /* SATA 1 active */ -+ { 16, MPP_UART }, /* UART1 RXD */ -+ { 17, MPP_UART }, /* UART1 TXD */ -+ { 18, MPP_GPIO }, /* SW_RST */ -+ { 19, MPP_UNUSED }, -+ { -1 }, - }; - --/* -- * QNAP TS-[12]09 specific power off method via UART1-attached PIC -- */ -- --#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) -- --static void qnap_ts209_power_off(void) --{ -- /* 19200 baud divisor */ -- const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); -- -- pr_info("%s: triggering power-off...\n", __func__); -- -- /* hijack uart1 and reset into sane state (19200,8n1) */ -- orion5x_write(UART1_REG(LCR), 0x83); -- orion5x_write(UART1_REG(DLL), divisor & 0xff); -- orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff); -- orion5x_write(UART1_REG(LCR), 0x03); -- orion5x_write(UART1_REG(IER), 0x00); -- orion5x_write(UART1_REG(FCR), 0x00); -- orion5x_write(UART1_REG(MCR), 0x00); -- -- /* send the power-off command 'A' to PIC */ -- orion5x_write(UART1_REG(TX), 'A'); --} -- - static void __init qnap_ts209_init(void) - { - /* -@@ -368,51 +275,33 @@ - */ - orion5x_init(); - -- /* -- * Setup flash mapping -- */ -- orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, -- QNAP_TS209_NOR_BOOT_SIZE); -- -- /* -- * Open a special address decode windows for the PCIe WA. -- */ -- orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, -- ORION5X_PCIE_WA_SIZE); -+ orion5x_mpp_conf(ts209_mpp_modes); - - /* -- * Setup Multiplexing Pins -- -- * MPP[0] Reserved -- * MPP[1] USB copy button (0 active) -- * MPP[2] Load defaults button (0 active) -- * MPP[3] GPIO RTC -- * MPP[4-5] Reserved -- * MPP[6] PCI Int A -- * MPP[7] PCI Int B -- * MPP[8-11] Reserved -- * MPP[12] SATA 0 presence -- * MPP[13] SATA 1 presence -- * MPP[14] SATA 0 active -- * MPP[15] SATA 1 active -- * MPP[16] UART1 RXD -- * MPP[17] UART1 TXD -- * MPP[18] SW_RST (0 active) -- * MPP[19] Reserved - * MPP[20] PCI clock 0 - * MPP[21] PCI clock 1 - * MPP[22] USB 0 over current - * MPP[23-25] Reserved - */ -- orion5x_write(MPP_0_7_CTRL, 0x3); -- orion5x_write(MPP_8_15_CTRL, 0x55550000); -- orion5x_write(MPP_16_19_CTRL, 0x5500); -- orion5x_gpio_set_valid_pins(0x3cc0fff); - -- /* register ts209 specific power-off method */ -- pm_power_off = qnap_ts209_power_off; -+ /* -+ * Configure peripherals. -+ */ -+ orion5x_ehci0_init(); -+ orion5x_ehci1_init(); -+ qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE + -+ qnap_ts209_partitions[5].offset, -+ qnap_ts209_partitions[5].size); -+ orion5x_eth_init(&qnap_tsx09_eth_data); -+ orion5x_i2c_init(); -+ orion5x_sata_init(&qnap_ts209_sata_data); -+ orion5x_uart0_init(); -+ -+ orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, -+ QNAP_TS209_NOR_BOOT_SIZE); -+ platform_device_register(&qnap_ts209_nor_flash); - -- platform_add_devices(qnap_ts209_devices, -- ARRAY_SIZE(qnap_ts209_devices)); -+ platform_device_register(&qnap_ts209_button_device); - - /* Get RTC IRQ and register the chip */ - if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) { -@@ -425,14 +314,12 @@ - pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); - i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); - -- ts209_find_mac_addr(); -- orion5x_eth_init(&qnap_ts209_eth_data); -- -- orion5x_sata_init(&qnap_ts209_sata_data); -+ /* register tsx09 specific power-off method */ -+ pm_power_off = qnap_tsx09_power_off; - } - - MACHINE_START(TS209, "QNAP TS-109/TS-209") -- /* Maintainer: Byron Bradley */ -+ /* Maintainer: Byron Bradley */ - .phys_io = ORION5X_REGS_PHYS_BASE, - .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, - .boot_params = 0x00000100, ---- /dev/null -+++ b/arch/arm/mach-orion5x/ts409-setup.c -@@ -0,0 +1,273 @@ -+/* -+ * QNAP TS-409 Board Setup -+ * -+ * Maintainer: Sylver Bruneau -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+#include "mpp.h" -+#include "tsx09-common.h" -+ -+/***************************************************************************** -+ * QNAP TS-409 Info -+ ****************************************************************************/ -+ -+/* -+ * QNAP TS-409 hardware : -+ * - Marvell 88F5281-D0 -+ * - Marvell 88SX7042 SATA controller (PCIe) -+ * - Marvell 88E1118 Gigabit Ethernet PHY -+ * - RTC S35390A (@0x30) on I2C bus -+ * - 8MB NOR flash -+ * - 256MB of DDR-2 RAM -+ */ -+ -+/* -+ * 8MB NOR flash Device bus boot chip select -+ */ -+ -+#define QNAP_TS409_NOR_BOOT_BASE 0xff800000 -+#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M -+ -+/**************************************************************************** -+ * 8MiB NOR flash. The struct mtd_partition is not in the same order as the -+ * partitions on the device because we want to keep compatability with -+ * existing QNAP firmware. -+ * -+ * Layout as used by QNAP: -+ * [2] 0x00000000-0x00200000 : "Kernel" -+ * [3] 0x00200000-0x00600000 : "RootFS1" -+ * [4] 0x00600000-0x00700000 : "RootFS2" -+ * [6] 0x00700000-0x00760000 : "NAS Config" (read-only) -+ * [5] 0x00760000-0x00780000 : "U-Boot Config" -+ * [1] 0x00780000-0x00800000 : "U-Boot" (read-only) -+ ***************************************************************************/ -+static struct mtd_partition qnap_ts409_partitions[] = { -+ { -+ .name = "U-Boot", -+ .size = 0x00080000, -+ .offset = 0x00780000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "Kernel", -+ .size = 0x00200000, -+ .offset = 0, -+ }, { -+ .name = "RootFS1", -+ .size = 0x00400000, -+ .offset = 0x00200000, -+ }, { -+ .name = "RootFS2", -+ .size = 0x00100000, -+ .offset = 0x00600000, -+ }, { -+ .name = "U-Boot Config", -+ .size = 0x00020000, -+ .offset = 0x00760000, -+ }, { -+ .name = "NAS Config", -+ .size = 0x00060000, -+ .offset = 0x00700000, -+ .mask_flags = MTD_WRITEABLE, -+ }, -+}; -+ -+static struct physmap_flash_data qnap_ts409_nor_flash_data = { -+ .width = 1, -+ .parts = qnap_ts409_partitions, -+ .nr_parts = ARRAY_SIZE(qnap_ts409_partitions) -+}; -+ -+static struct resource qnap_ts409_nor_flash_resource = { -+ .flags = IORESOURCE_MEM, -+ .start = QNAP_TS409_NOR_BOOT_BASE, -+ .end = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1, -+}; -+ -+static struct platform_device qnap_ts409_nor_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev = { .platform_data = &qnap_ts409_nor_flash_data, }, -+ .num_resources = 1, -+ .resource = &qnap_ts409_nor_flash_resource, -+}; -+ -+/***************************************************************************** -+ * PCI -+ ****************************************************************************/ -+ -+static int __init qnap_ts409_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ int irq; -+ -+ /* -+ * Check for devices with hard-wired IRQs. -+ */ -+ irq = orion5x_pci_map_irq(dev, slot, pin); -+ if (irq != -1) -+ return irq; -+ -+ /* -+ * PCI isn't used on the TS-409 -+ */ -+ return -1; -+} -+ -+static struct hw_pci qnap_ts409_pci __initdata = { -+ .nr_controllers = 2, -+ .swizzle = pci_std_swizzle, -+ .setup = orion5x_pci_sys_setup, -+ .scan = orion5x_pci_sys_scan_bus, -+ .map_irq = qnap_ts409_pci_map_irq, -+}; -+ -+static int __init qnap_ts409_pci_init(void) -+{ -+ if (machine_is_ts409()) -+ pci_common_init(&qnap_ts409_pci); -+ -+ return 0; -+} -+ -+subsys_initcall(qnap_ts409_pci_init); -+ -+/***************************************************************************** -+ * RTC S35390A on I2C bus -+ ****************************************************************************/ -+ -+#define TS409_RTC_GPIO 10 -+ -+static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = { -+ I2C_BOARD_INFO("s35390a", 0x30), -+}; -+ -+/**************************************************************************** -+ * GPIO Attached Keys -+ * Power button is attached to the PIC microcontroller -+ ****************************************************************************/ -+ -+#define QNAP_TS409_GPIO_KEY_MEDIA 15 -+ -+static struct gpio_keys_button qnap_ts409_buttons[] = { -+ { -+ .code = KEY_RESTART, -+ .gpio = QNAP_TS409_GPIO_KEY_MEDIA, -+ .desc = "USB Copy Button", -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_keys_platform_data qnap_ts409_button_data = { -+ .buttons = qnap_ts409_buttons, -+ .nbuttons = ARRAY_SIZE(qnap_ts409_buttons), -+}; -+ -+static struct platform_device qnap_ts409_button_device = { -+ .name = "gpio-keys", -+ .id = -1, -+ .num_resources = 0, -+ .dev = { -+ .platform_data = &qnap_ts409_button_data, -+ }, -+}; -+ -+/***************************************************************************** -+ * General Setup -+ ****************************************************************************/ -+static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = { -+ { 0, MPP_UNUSED }, -+ { 1, MPP_UNUSED }, -+ { 2, MPP_UNUSED }, -+ { 3, MPP_UNUSED }, -+ { 4, MPP_GPIO }, /* HDD 1 status */ -+ { 5, MPP_GPIO }, /* HDD 2 status */ -+ { 6, MPP_GPIO }, /* HDD 3 status */ -+ { 7, MPP_GPIO }, /* HDD 4 status */ -+ { 8, MPP_UNUSED }, -+ { 9, MPP_UNUSED }, -+ { 10, MPP_GPIO }, /* RTC int */ -+ { 11, MPP_UNUSED }, -+ { 12, MPP_UNUSED }, -+ { 13, MPP_UNUSED }, -+ { 14, MPP_GPIO }, /* SW_RST */ -+ { 15, MPP_GPIO }, /* USB copy button */ -+ { 16, MPP_UART }, /* UART1 RXD */ -+ { 17, MPP_UART }, /* UART1 TXD */ -+ { 18, MPP_UNUSED }, -+ { 19, MPP_UNUSED }, -+ { -1 }, -+}; -+ -+static void __init qnap_ts409_init(void) -+{ -+ /* -+ * Setup basic Orion functions. Need to be called early. -+ */ -+ orion5x_init(); -+ -+ orion5x_mpp_conf(ts409_mpp_modes); -+ -+ /* -+ * Configure peripherals. -+ */ -+ orion5x_ehci0_init(); -+ qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE + -+ qnap_ts409_partitions[5].offset, -+ qnap_ts409_partitions[5].size); -+ orion5x_eth_init(&qnap_tsx09_eth_data); -+ orion5x_i2c_init(); -+ orion5x_uart0_init(); -+ -+ orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE, -+ QNAP_TS409_NOR_BOOT_SIZE); -+ platform_device_register(&qnap_ts409_nor_flash); -+ -+ platform_device_register(&qnap_ts409_button_device); -+ -+ /* Get RTC IRQ and register the chip */ -+ if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) { -+ if (gpio_direction_input(TS409_RTC_GPIO) == 0) -+ qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO); -+ else -+ gpio_free(TS409_RTC_GPIO); -+ } -+ if (qnap_ts409_i2c_rtc.irq == 0) -+ pr_warning("qnap_ts409_init: failed to get RTC IRQ\n"); -+ i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1); -+ -+ /* register tsx09 specific power-off method */ -+ pm_power_off = qnap_tsx09_power_off; -+} -+ -+MACHINE_START(TS409, "QNAP TS-409") -+ /* Maintainer: Sylver Bruneau */ -+ .phys_io = ORION5X_REGS_PHYS_BASE, -+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, -+ .boot_params = 0x00000100, -+ .init_machine = qnap_ts409_init, -+ .map_io = orion5x_map_io, -+ .init_irq = orion5x_init_irq, -+ .timer = &orion5x_timer, -+ .fixup = tag_fixup_mem32, -+MACHINE_END ---- /dev/null -+++ b/arch/arm/mach-orion5x/ts78xx-setup.c -@@ -0,0 +1,277 @@ -+/* -+ * arch/arm/mach-orion5x/ts78xx-setup.c -+ * -+ * Maintainer: Alexander Clouter -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+#include "mpp.h" -+ -+/***************************************************************************** -+ * TS-78xx Info -+ ****************************************************************************/ -+ -+/* -+ * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE -+ */ -+#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000 -+#define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000 -+#define TS78XX_FPGA_REGS_SIZE SZ_1M -+ -+#define TS78XX_FPGA_REGS_SYSCON_ID (TS78XX_FPGA_REGS_VIRT_BASE | 0x000) -+#define TS78XX_FPGA_REGS_SYSCON_LCDI (TS78XX_FPGA_REGS_VIRT_BASE | 0x004) -+#define TS78XX_FPGA_REGS_SYSCON_LCDO (TS78XX_FPGA_REGS_VIRT_BASE | 0x008) -+ -+#define TS78XX_FPGA_REGS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808) -+#define TS78XX_FPGA_REGS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c) -+ -+/* -+ * 512kB NOR flash Device -+ */ -+#define TS78XX_NOR_BOOT_BASE 0xff800000 -+#define TS78XX_NOR_BOOT_SIZE SZ_512K -+ -+/***************************************************************************** -+ * I/O Address Mapping -+ ****************************************************************************/ -+static struct map_desc ts78xx_io_desc[] __initdata = { -+ { -+ .virtual = TS78XX_FPGA_REGS_VIRT_BASE, -+ .pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE), -+ .length = TS78XX_FPGA_REGS_SIZE, -+ .type = MT_DEVICE, -+ }, -+}; -+ -+void __init ts78xx_map_io(void) -+{ -+ orion5x_map_io(); -+ iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc)); -+} -+ -+/***************************************************************************** -+ * 512kB NOR Boot Flash - the chip is a M25P40 -+ ****************************************************************************/ -+static struct mtd_partition ts78xx_nor_boot_flash_resources[] = { -+ { -+ .name = "ts-bootrom", -+ .offset = 0, -+ /* only the first 256kB is used */ -+ .size = SZ_256K, -+ .mask_flags = MTD_WRITEABLE, -+ }, -+}; -+ -+static struct physmap_flash_data ts78xx_nor_boot_flash_data = { -+ .width = 1, -+ .parts = ts78xx_nor_boot_flash_resources, -+ .nr_parts = ARRAY_SIZE(ts78xx_nor_boot_flash_resources), -+}; -+ -+static struct resource ts78xx_nor_boot_flash_resource = { -+ .flags = IORESOURCE_MEM, -+ .start = TS78XX_NOR_BOOT_BASE, -+ .end = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1, -+}; -+ -+static struct platform_device ts78xx_nor_boot_flash = { -+ .name = "physmap-flash", -+ .id = -1, -+ .dev = { -+ .platform_data = &ts78xx_nor_boot_flash_data, -+ }, -+ .num_resources = 1, -+ .resource = &ts78xx_nor_boot_flash_resource, -+}; -+ -+/***************************************************************************** -+ * Ethernet -+ ****************************************************************************/ -+static struct mv643xx_eth_platform_data ts78xx_eth_data = { -+ .phy_addr = 0, -+ .force_phy_addr = 1, -+}; -+ -+/***************************************************************************** -+ * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c -+ ****************************************************************************/ -+#ifdef CONFIG_RTC_DRV_M48T86 -+static unsigned char ts78xx_rtc_readbyte(unsigned long addr) -+{ -+ writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL); -+ return readb(TS78XX_FPGA_REGS_RTC_DATA); -+} -+ -+static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr) -+{ -+ writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL); -+ writeb(value, TS78XX_FPGA_REGS_RTC_DATA); -+} -+ -+static struct m48t86_ops ts78xx_rtc_ops = { -+ .readbyte = ts78xx_rtc_readbyte, -+ .writebyte = ts78xx_rtc_writebyte, -+}; -+ -+static struct platform_device ts78xx_rtc_device = { -+ .name = "rtc-m48t86", -+ .id = -1, -+ .dev = { -+ .platform_data = &ts78xx_rtc_ops, -+ }, -+ .num_resources = 0, -+}; -+ -+/* -+ * TS uses some of the user storage space on the RTC chip so see if it is -+ * present; as it's an optional feature at purchase time and not all boards -+ * will have it present -+ * -+ * I've used the method TS use in their rtc7800.c example for the detection -+ * -+ * TODO: track down a guinea pig without an RTC to see if we can work out a -+ * better RTC detection routine -+ */ -+static int __init ts78xx_rtc_init(void) -+{ -+ unsigned char tmp_rtc0, tmp_rtc1; -+ -+ tmp_rtc0 = ts78xx_rtc_readbyte(126); -+ tmp_rtc1 = ts78xx_rtc_readbyte(127); -+ -+ ts78xx_rtc_writebyte(0x00, 126); -+ ts78xx_rtc_writebyte(0x55, 127); -+ if (ts78xx_rtc_readbyte(127) == 0x55) { -+ ts78xx_rtc_writebyte(0xaa, 127); -+ if (ts78xx_rtc_readbyte(127) == 0xaa -+ && ts78xx_rtc_readbyte(126) == 0x00) { -+ ts78xx_rtc_writebyte(tmp_rtc0, 126); -+ ts78xx_rtc_writebyte(tmp_rtc1, 127); -+ platform_device_register(&ts78xx_rtc_device); -+ return 1; -+ } -+ } -+ -+ return 0; -+}; -+#else -+static int __init ts78xx_rtc_init(void) -+{ -+ return 0; -+} -+#endif -+ -+/***************************************************************************** -+ * SATA -+ ****************************************************************************/ -+static struct mv_sata_platform_data ts78xx_sata_data = { -+ .n_ports = 2, -+}; -+ -+/***************************************************************************** -+ * print some information regarding the board -+ ****************************************************************************/ -+static void __init ts78xx_print_board_id(void) -+{ -+ unsigned int board_info; -+ -+ board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID); -+ printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ", -+ board_info & 0xff, -+ (board_info >> 8) & 0xffffff); -+ board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI); -+ printk("JP1=%d, JP2=%d\n", -+ (board_info >> 30) & 0x1, -+ (board_info >> 31) & 0x1); -+}; -+ -+/***************************************************************************** -+ * General Setup -+ ****************************************************************************/ -+static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { -+ { 0, MPP_UNUSED }, -+ { 1, MPP_GPIO }, /* JTAG Clock */ -+ { 2, MPP_GPIO }, /* JTAG Data In */ -+ { 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */ -+ { 4, MPP_GPIO }, /* JTAG Data Out */ -+ { 5, MPP_GPIO }, /* JTAG TMS */ -+ { 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */ -+ { 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */ -+ { 8, MPP_UNUSED }, -+ { 9, MPP_UNUSED }, -+ { 10, MPP_UNUSED }, -+ { 11, MPP_UNUSED }, -+ { 12, MPP_UNUSED }, -+ { 13, MPP_UNUSED }, -+ { 14, MPP_UNUSED }, -+ { 15, MPP_UNUSED }, -+ { 16, MPP_UART }, -+ { 17, MPP_UART }, -+ { 18, MPP_UART }, -+ { 19, MPP_UART }, -+ { -1 }, -+}; -+ -+static void __init ts78xx_init(void) -+{ -+ /* -+ * Setup basic Orion functions. Need to be called early. -+ */ -+ orion5x_init(); -+ -+ ts78xx_print_board_id(); -+ -+ orion5x_mpp_conf(ts78xx_mpp_modes); -+ -+ /* -+ * MPP[20] PCI Clock Out 1 -+ * MPP[21] PCI Clock Out 0 -+ * MPP[22] Unused -+ * MPP[23] Unused -+ * MPP[24] Unused -+ * MPP[25] Unused -+ */ -+ -+ /* -+ * Configure peripherals. -+ */ -+ orion5x_ehci0_init(); -+ orion5x_ehci1_init(); -+ orion5x_eth_init(&ts78xx_eth_data); -+ orion5x_sata_init(&ts78xx_sata_data); -+ orion5x_uart0_init(); -+ orion5x_uart1_init(); -+ -+ orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE, -+ TS78XX_NOR_BOOT_SIZE); -+ platform_device_register(&ts78xx_nor_boot_flash); -+ -+ if (!ts78xx_rtc_init()) -+ printk(KERN_INFO "TS-78xx RTC not detected or enabled\n"); -+} -+ -+MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") -+ /* Maintainer: Alexander Clouter */ -+ .phys_io = ORION5X_REGS_PHYS_BASE, -+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, -+ .boot_params = 0x00000100, -+ .init_machine = ts78xx_init, -+ .map_io = ts78xx_map_io, -+ .init_irq = orion5x_init_irq, -+ .timer = &orion5x_timer, -+MACHINE_END ---- /dev/null -+++ b/arch/arm/mach-orion5x/tsx09-common.c -@@ -0,0 +1,132 @@ -+/* -+ * QNAP TS-x09 Boards common functions -+ * -+ * Maintainers: Lennert Buytenhek -+ * Byron Bradley -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include "tsx09-common.h" -+ -+/***************************************************************************** -+ * QNAP TS-x09 specific power off method via UART1-attached PIC -+ ****************************************************************************/ -+ -+#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) -+ -+void qnap_tsx09_power_off(void) -+{ -+ /* 19200 baud divisor */ -+ const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); -+ -+ pr_info("%s: triggering power-off...\n", __func__); -+ -+ /* hijack uart1 and reset into sane state (19200,8n1) */ -+ writel(0x83, UART1_REG(LCR)); -+ writel(divisor & 0xff, UART1_REG(DLL)); -+ writel((divisor >> 8) & 0xff, UART1_REG(DLM)); -+ writel(0x03, UART1_REG(LCR)); -+ writel(0x00, UART1_REG(IER)); -+ writel(0x00, UART1_REG(FCR)); -+ writel(0x00, UART1_REG(MCR)); -+ -+ /* send the power-off command 'A' to PIC */ -+ writel('A', UART1_REG(TX)); -+} -+ -+/***************************************************************************** -+ * Ethernet -+ ****************************************************************************/ -+ -+struct mv643xx_eth_platform_data qnap_tsx09_eth_data = { -+ .phy_addr = 8, -+}; -+ -+static int __init qnap_tsx09_parse_hex_nibble(char n) -+{ -+ if (n >= '0' && n <= '9') -+ return n - '0'; -+ -+ if (n >= 'A' && n <= 'F') -+ return n - 'A' + 10; -+ -+ if (n >= 'a' && n <= 'f') -+ return n - 'a' + 10; -+ -+ return -1; -+} -+ -+static int __init qnap_tsx09_parse_hex_byte(const char *b) -+{ -+ int hi; -+ int lo; -+ -+ hi = qnap_tsx09_parse_hex_nibble(b[0]); -+ lo = qnap_tsx09_parse_hex_nibble(b[1]); -+ -+ if (hi < 0 || lo < 0) -+ return -1; -+ -+ return (hi << 4) | lo; -+} -+ -+static int __init qnap_tsx09_check_mac_addr(const char *addr_str) -+{ -+ u_int8_t addr[6]; -+ int i; -+ -+ for (i = 0; i < 6; i++) { -+ int byte; -+ -+ /* -+ * Enforce "xx:xx:xx:xx:xx:xx\n" format. -+ */ -+ if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n')) -+ return -1; -+ -+ byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3)); -+ if (byte < 0) -+ return -1; -+ addr[i] = byte; -+ } -+ -+ printk(KERN_INFO "tsx09: found ethernet mac address "); -+ for (i = 0; i < 6; i++) -+ printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); -+ -+ memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6); -+ -+ return 0; -+} -+ -+/* -+ * The 'NAS Config' flash partition has an ext2 filesystem which -+ * contains a file that has the ethernet MAC address in plain text -+ * (format "xx:xx:xx:xx:xx:xx\n"). -+ */ -+void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size) -+{ -+ unsigned long addr; -+ -+ for (addr = mem_base; addr < (mem_base + size); addr += 1024) { -+ char *nor_page; -+ int ret = 0; -+ -+ nor_page = ioremap(addr, 1024); -+ if (nor_page != NULL) { -+ ret = qnap_tsx09_check_mac_addr(nor_page); -+ iounmap(nor_page); -+ } -+ -+ if (ret == 0) -+ break; -+ } -+} ---- /dev/null -+++ b/arch/arm/mach-orion5x/tsx09-common.h -@@ -0,0 +1,20 @@ -+#ifndef __ARCH_ORION5X_TSX09_COMMON_H -+#define __ARCH_ORION5X_TSX09_COMMON_H -+ -+/* -+ * QNAP TS-x09 Boards power-off function -+ */ -+extern void qnap_tsx09_power_off(void); -+ -+/* -+ * QNAP TS-x09 Boards function to find Ethernet MAC address in flash memory -+ */ -+extern void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size); -+ -+/* -+ * QNAP TS-x09 Boards ethernet declaration -+ */ -+extern struct mv643xx_eth_platform_data qnap_tsx09_eth_data; -+ -+ -+#endif ---- /dev/null -+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c -@@ -0,0 +1,173 @@ -+/* -+ * arch/arm/mach-orion5x/wrt350n-v2-setup.c -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+#include "mpp.h" -+ -+static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = { -+ { 0, MPP_GPIO }, /* Power LED green (0=on) */ -+ { 1, MPP_GPIO }, /* Security LED (0=on) */ -+ { 2, MPP_GPIO }, /* Internal Button (0=on) */ -+ { 3, MPP_GPIO }, /* Reset Button (0=on) */ -+ { 4, MPP_GPIO }, /* PCI int */ -+ { 5, MPP_GPIO }, /* Power LED orange (0=on) */ -+ { 6, MPP_GPIO }, /* USB LED (0=on) */ -+ { 7, MPP_GPIO }, /* Wireless LED (0=on) */ -+ { 8, MPP_UNUSED }, /* ??? */ -+ { 9, MPP_GIGE }, /* GE_RXERR */ -+ { 10, MPP_UNUSED }, /* ??? */ -+ { 11, MPP_UNUSED }, /* ??? */ -+ { 12, MPP_GIGE }, /* GE_TXD[4] */ -+ { 13, MPP_GIGE }, /* GE_TXD[5] */ -+ { 14, MPP_GIGE }, /* GE_TXD[6] */ -+ { 15, MPP_GIGE }, /* GE_TXD[7] */ -+ { 16, MPP_GIGE }, /* GE_RXD[4] */ -+ { 17, MPP_GIGE }, /* GE_RXD[5] */ -+ { 18, MPP_GIGE }, /* GE_RXD[6] */ -+ { 19, MPP_GIGE }, /* GE_RXD[7] */ -+ { -1 }, -+}; -+ -+/* -+ * 8M NOR flash Device bus boot chip select -+ */ -+#define WRT350N_V2_NOR_BOOT_BASE 0xf4000000 -+#define WRT350N_V2_NOR_BOOT_SIZE SZ_8M -+ -+static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = { -+ { -+ .name = "kernel", -+ .offset = 0x00000000, -+ .size = 0x00760000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x001a0000, -+ .size = 0x005c0000, -+ }, { -+ .name = "lang", -+ .offset = 0x00760000, -+ .size = 0x00040000, -+ }, { -+ .name = "nvram", -+ .offset = 0x007a0000, -+ .size = 0x00020000, -+ }, { -+ .name = "u-boot", -+ .offset = 0x007c0000, -+ .size = 0x00040000, -+ }, -+}; -+ -+static struct physmap_flash_data wrt350n_v2_nor_flash_data = { -+ .width = 1, -+ .parts = wrt350n_v2_nor_flash_partitions, -+ .nr_parts = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions), -+}; -+ -+static struct resource wrt350n_v2_nor_flash_resource = { -+ .flags = IORESOURCE_MEM, -+ .start = WRT350N_V2_NOR_BOOT_BASE, -+ .end = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1, -+}; -+ -+static struct platform_device wrt350n_v2_nor_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev = { -+ .platform_data = &wrt350n_v2_nor_flash_data, -+ }, -+ .num_resources = 1, -+ .resource = &wrt350n_v2_nor_flash_resource, -+}; -+ -+static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = { -+ .phy_addr = -1, -+}; -+ -+static void __init wrt350n_v2_init(void) -+{ -+ /* -+ * Setup basic Orion functions. Need to be called early. -+ */ -+ orion5x_init(); -+ -+ orion5x_mpp_conf(wrt350n_v2_mpp_modes); -+ -+ /* -+ * Configure peripherals. -+ */ -+ orion5x_ehci0_init(); -+ orion5x_eth_init(&wrt350n_v2_eth_data); -+ orion5x_uart0_init(); -+ -+ orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE, -+ WRT350N_V2_NOR_BOOT_SIZE); -+ platform_device_register(&wrt350n_v2_nor_flash); -+} -+ -+static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ int irq; -+ -+ /* -+ * Check for devices with hard-wired IRQs. -+ */ -+ irq = orion5x_pci_map_irq(dev, slot, pin); -+ if (irq != -1) -+ return irq; -+ -+ /* -+ * Mini-PCI slot. -+ */ -+ if (slot == 7) -+ return gpio_to_irq(4); -+ -+ return -1; -+} -+ -+static struct hw_pci wrt350n_v2_pci __initdata = { -+ .nr_controllers = 2, -+ .swizzle = pci_std_swizzle, -+ .setup = orion5x_pci_sys_setup, -+ .scan = orion5x_pci_sys_scan_bus, -+ .map_irq = wrt350n_v2_pci_map_irq, -+}; -+ -+static int __init wrt350n_v2_pci_init(void) -+{ -+ if (machine_is_wrt350n_v2()) -+ pci_common_init(&wrt350n_v2_pci); -+ -+ return 0; -+} -+subsys_initcall(wrt350n_v2_pci_init); -+ -+MACHINE_START(WRT350N_V2, "Linksys WRT350N v2") -+ /* Maintainer: Lennert Buytenhek */ -+ .phys_io = ORION5X_REGS_PHYS_BASE, -+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, -+ .boot_params = 0x00000100, -+ .init_machine = wrt350n_v2_init, -+ .map_io = orion5x_map_io, -+ .init_irq = orion5x_init_irq, -+ .timer = &orion5x_timer, -+ .fixup = tag_fixup_mem32, -+MACHINE_END ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -365,7 +365,7 @@ - # Feroceon - config CPU_FEROCEON - bool -- depends on ARCH_ORION5X -+ depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0 - default y - select CPU_32v5 - select CPU_ABRT_EV5T -@@ -373,7 +373,7 @@ - select CPU_CACHE_VIVT - select CPU_CP15_MMU - select CPU_COPY_FEROCEON if MMU -- select CPU_TLB_V4WBI if MMU -+ select CPU_TLB_FEROCEON if MMU - - config CPU_FEROCEON_OLD_ID - bool "Accept early Feroceon cores with an ARM926 ID" -@@ -551,6 +551,11 @@ - ARM Architecture Version 4 TLB with writeback cache and invalidate - instruction cache entry. - -+config CPU_TLB_FEROCEON -+ bool -+ help -+ Feroceon TLB (v4wbi with non-outer-cachable page table walks). -+ - config CPU_TLB_V6 - bool - -@@ -709,6 +714,14 @@ - bool - default n - -+config CACHE_FEROCEON_L2 -+ bool "Enable the Feroceon L2 cache controller" -+ depends on ARCH_KIRKWOOD || ARCH_MV78XX0 -+ default y -+ select OUTER_CACHE -+ help -+ This option enables the Feroceon L2 cache controller. -+ - config CACHE_L2X0 - bool "Enable the L2x0 outer cache controller" - depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 ---- a/arch/arm/mm/Makefile -+++ b/arch/arm/mm/Makefile -@@ -46,6 +46,7 @@ - obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o - obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o - obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o -+obj-$(CONFIG_CPU_TLB_FEROCEON) += tlb-v4wbi.o # reuse v4wbi TLB functions - obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o - obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o - -@@ -73,4 +74,5 @@ - obj-$(CONFIG_CPU_V6) += proc-v6.o - obj-$(CONFIG_CPU_V7) += proc-v7.o - -+obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o - obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o ---- /dev/null -+++ b/arch/arm/mm/cache-feroceon-l2.c -@@ -0,0 +1,318 @@ -+/* -+ * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support -+ * -+ * Copyright (C) 2008 Marvell Semiconductor -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ * -+ * References: -+ * - Unified Layer 2 Cache for Feroceon CPU Cores, -+ * Document ID MV-S104858-00, Rev. A, October 23 2007. -+ */ -+ -+#include -+#include -+#include -+ -+ -+/* -+ * Low-level cache maintenance operations. -+ * -+ * As well as the regular 'clean/invalidate/flush L2 cache line by -+ * MVA' instructions, the Feroceon L2 cache controller also features -+ * 'clean/invalidate L2 range by MVA' operations. -+ * -+ * Cache range operations are initiated by writing the start and -+ * end addresses to successive cp15 registers, and process every -+ * cache line whose first byte address lies in the inclusive range -+ * [start:end]. -+ * -+ * The cache range operations stall the CPU pipeline until completion. -+ * -+ * The range operations require two successive cp15 writes, in -+ * between which we don't want to be preempted. -+ */ -+static inline void l2_clean_pa(unsigned long addr) -+{ -+ __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr)); -+} -+ -+static inline void l2_clean_mva_range(unsigned long start, unsigned long end) -+{ -+ unsigned long flags; -+ -+ /* -+ * Make sure 'start' and 'end' reference the same page, as -+ * L2 is PIPT and range operations only do a TLB lookup on -+ * the start address. -+ */ -+ BUG_ON((start ^ end) & ~(PAGE_SIZE - 1)); -+ -+ raw_local_irq_save(flags); -+ __asm__("mcr p15, 1, %0, c15, c9, 4" : : "r" (start)); -+ __asm__("mcr p15, 1, %0, c15, c9, 5" : : "r" (end)); -+ raw_local_irq_restore(flags); -+} -+ -+static inline void l2_clean_pa_range(unsigned long start, unsigned long end) -+{ -+ l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end)); -+} -+ -+static inline void l2_clean_inv_pa(unsigned long addr) -+{ -+ __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr)); -+} -+ -+static inline void l2_inv_pa(unsigned long addr) -+{ -+ __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr)); -+} -+ -+static inline void l2_inv_mva_range(unsigned long start, unsigned long end) -+{ -+ unsigned long flags; -+ -+ /* -+ * Make sure 'start' and 'end' reference the same page, as -+ * L2 is PIPT and range operations only do a TLB lookup on -+ * the start address. -+ */ -+ BUG_ON((start ^ end) & ~(PAGE_SIZE - 1)); -+ -+ raw_local_irq_save(flags); -+ __asm__("mcr p15, 1, %0, c15, c11, 4" : : "r" (start)); -+ __asm__("mcr p15, 1, %0, c15, c11, 5" : : "r" (end)); -+ raw_local_irq_restore(flags); -+} -+ -+static inline void l2_inv_pa_range(unsigned long start, unsigned long end) -+{ -+ l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end)); -+} -+ -+ -+/* -+ * Linux primitives. -+ * -+ * Note that the end addresses passed to Linux primitives are -+ * noninclusive, while the hardware cache range operations use -+ * inclusive start and end addresses. -+ */ -+#define CACHE_LINE_SIZE 32 -+#define MAX_RANGE_SIZE 1024 -+ -+static int l2_wt_override; -+ -+static unsigned long calc_range_end(unsigned long start, unsigned long end) -+{ -+ unsigned long range_end; -+ -+ BUG_ON(start & (CACHE_LINE_SIZE - 1)); -+ BUG_ON(end & (CACHE_LINE_SIZE - 1)); -+ -+ /* -+ * Try to process all cache lines between 'start' and 'end'. -+ */ -+ range_end = end; -+ -+ /* -+ * Limit the number of cache lines processed at once, -+ * since cache range operations stall the CPU pipeline -+ * until completion. -+ */ -+ if (range_end > start + MAX_RANGE_SIZE) -+ range_end = start + MAX_RANGE_SIZE; -+ -+ /* -+ * Cache range operations can't straddle a page boundary. -+ */ -+ if (range_end > (start | (PAGE_SIZE - 1)) + 1) -+ range_end = (start | (PAGE_SIZE - 1)) + 1; -+ -+ return range_end; -+} -+ -+static void feroceon_l2_inv_range(unsigned long start, unsigned long end) -+{ -+ /* -+ * Clean and invalidate partial first cache line. -+ */ -+ if (start & (CACHE_LINE_SIZE - 1)) { -+ l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); -+ start = (start | (CACHE_LINE_SIZE - 1)) + 1; -+ } -+ -+ /* -+ * Clean and invalidate partial last cache line. -+ */ -+ if (end & (CACHE_LINE_SIZE - 1)) { -+ l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); -+ end &= ~(CACHE_LINE_SIZE - 1); -+ } -+ -+ /* -+ * Invalidate all full cache lines between 'start' and 'end'. -+ */ -+ while (start != end) { -+ unsigned long range_end = calc_range_end(start, end); -+ l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); -+ start = range_end; -+ } -+ -+ dsb(); -+} -+ -+static void feroceon_l2_clean_range(unsigned long start, unsigned long end) -+{ -+ /* -+ * If L2 is forced to WT, the L2 will always be clean and we -+ * don't need to do anything here. -+ */ -+ if (!l2_wt_override) { -+ start &= ~(CACHE_LINE_SIZE - 1); -+ end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); -+ while (start != end) { -+ unsigned long range_end = calc_range_end(start, end); -+ l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE); -+ start = range_end; -+ } -+ } -+ -+ dsb(); -+} -+ -+static void feroceon_l2_flush_range(unsigned long start, unsigned long end) -+{ -+ start &= ~(CACHE_LINE_SIZE - 1); -+ end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); -+ while (start != end) { -+ unsigned long range_end = calc_range_end(start, end); -+ if (!l2_wt_override) -+ l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE); -+ l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); -+ start = range_end; -+ } -+ -+ dsb(); -+} -+ -+ -+/* -+ * Routines to disable and re-enable the D-cache and I-cache at run -+ * time. These are necessary because the L2 cache can only be enabled -+ * or disabled while the L1 Dcache and Icache are both disabled. -+ */ -+static void __init invalidate_and_disable_dcache(void) -+{ -+ u32 cr; -+ -+ cr = get_cr(); -+ if (cr & CR_C) { -+ unsigned long flags; -+ -+ raw_local_irq_save(flags); -+ flush_cache_all(); -+ set_cr(cr & ~CR_C); -+ raw_local_irq_restore(flags); -+ } -+} -+ -+static void __init enable_dcache(void) -+{ -+ u32 cr; -+ -+ cr = get_cr(); -+ if (!(cr & CR_C)) -+ set_cr(cr | CR_C); -+} -+ -+static void __init __invalidate_icache(void) -+{ -+ int dummy; -+ -+ __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0\n" : "=r" (dummy)); -+} -+ -+static void __init invalidate_and_disable_icache(void) -+{ -+ u32 cr; -+ -+ cr = get_cr(); -+ if (cr & CR_I) { -+ set_cr(cr & ~CR_I); -+ __invalidate_icache(); -+ } -+} -+ -+static void __init enable_icache(void) -+{ -+ u32 cr; -+ -+ cr = get_cr(); -+ if (!(cr & CR_I)) -+ set_cr(cr | CR_I); -+} -+ -+static inline u32 read_extra_features(void) -+{ -+ u32 u; -+ -+ __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u)); -+ -+ return u; -+} -+ -+static inline void write_extra_features(u32 u) -+{ -+ __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); -+} -+ -+static void __init disable_l2_prefetch(void) -+{ -+ u32 u; -+ -+ /* -+ * Read the CPU Extra Features register and verify that the -+ * Disable L2 Prefetch bit is set. -+ */ -+ u = read_extra_features(); -+ if (!(u & 0x01000000)) { -+ printk(KERN_INFO "Feroceon L2: Disabling L2 prefetch.\n"); -+ write_extra_features(u | 0x01000000); -+ } -+} -+ -+static void __init enable_l2(void) -+{ -+ u32 u; -+ -+ u = read_extra_features(); -+ if (!(u & 0x00400000)) { -+ printk(KERN_INFO "Feroceon L2: Enabling L2\n"); -+ -+ invalidate_and_disable_dcache(); -+ invalidate_and_disable_icache(); -+ write_extra_features(u | 0x00400000); -+ enable_icache(); -+ enable_dcache(); -+ } -+} -+ -+void __init feroceon_l2_init(int __l2_wt_override) -+{ -+ l2_wt_override = __l2_wt_override; -+ -+ disable_l2_prefetch(); -+ -+ outer_cache.inv_range = feroceon_l2_inv_range; -+ outer_cache.clean_range = feroceon_l2_clean_range; -+ outer_cache.flush_range = feroceon_l2_flush_range; -+ -+ enable_l2(); -+ -+ printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n", -+ l2_wt_override ? ", in WT override mode" : ""); -+} ---- a/arch/arm/mm/proc-feroceon.S -+++ b/arch/arm/mm/proc-feroceon.S -@@ -44,11 +44,31 @@ - */ - #define CACHE_DLINESIZE 32 - -+ .bss -+ .align 3 -+__cache_params_loc: -+ .space 8 -+ - .text -+__cache_params: -+ .word __cache_params_loc -+ - /* - * cpu_feroceon_proc_init() - */ - ENTRY(cpu_feroceon_proc_init) -+ mrc p15, 0, r0, c0, c0, 1 @ read cache type register -+ ldr r1, __cache_params -+ mov r2, #(16 << 5) -+ tst r0, #(1 << 16) @ get way -+ mov r0, r0, lsr #18 @ get cache size order -+ movne r3, #((4 - 1) << 30) @ 4-way -+ and r0, r0, #0xf -+ moveq r3, #0 @ 1-way -+ mov r2, r2, lsl r0 @ actual cache size -+ movne r2, r2, lsr #2 @ turned into # of sets -+ sub r2, r2, #(1 << 5) -+ stmia r1, {r2, r3} - mov pc, lr - - /* -@@ -59,6 +79,13 @@ - mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, ip - bl feroceon_flush_kern_cache_all -+ -+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) -+ mov r0, #0 -+ mcr p15, 1, r0, c15, c9, 0 @ clean L2 -+ mcr p15, 0, r0, c7, c10, 4 @ drain WB -+#endif -+ - mrc p15, 0, r0, c1, c0, 0 @ ctrl register - bic r0, r0, #0x1000 @ ...i............ - bic r0, r0, #0x000e @ ............wca. -@@ -117,11 +144,19 @@ - */ - ENTRY(feroceon_flush_kern_cache_all) - mov r2, #VM_EXEC -- mov ip, #0 -+ - __flush_whole_cache: --1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate -- bne 1b -+ ldr r1, __cache_params -+ ldmia r1, {r1, r3} -+1: orr ip, r1, r3 -+2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way -+ subs ip, ip, #(1 << 30) @ next way -+ bcs 2b -+ subs r1, r1, #(1 << 5) @ next set -+ bcs 1b -+ - tst r2, #VM_EXEC -+ mov ip, #0 - mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache - mcrne p15, 0, ip, c7, c10, 4 @ drain WB - mov pc, lr -@@ -138,7 +173,6 @@ - */ - .align 5 - ENTRY(feroceon_flush_user_cache_range) -- mov ip, #0 - sub r3, r1, r0 @ calculate total size - cmp r3, #CACHE_DLIMIT - bgt __flush_whole_cache -@@ -152,6 +186,7 @@ - cmp r0, r1 - blo 1b - tst r2, #VM_EXEC -+ mov ip, #0 - mcrne p15, 0, ip, c7, c10, 4 @ drain WB - mov pc, lr - -@@ -209,6 +244,20 @@ - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mov pc, lr - -+ .align 5 -+ENTRY(feroceon_range_flush_kern_dcache_page) -+ mrs r2, cpsr -+ add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive -+ orr r3, r2, #PSR_I_BIT -+ msr cpsr_c, r3 @ disable interrupts -+ mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start -+ mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top -+ msr cpsr_c, r2 @ restore interrupts -+ mov r0, #0 -+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache -+ mcr p15, 0, r0, c7, c10, 4 @ drain WB -+ mov pc, lr -+ - /* - * dma_inv_range(start, end) - * -@@ -225,10 +274,10 @@ - .align 5 - ENTRY(feroceon_dma_inv_range) - tst r0, #CACHE_DLINESIZE - 1 -+ bic r0, r0, #CACHE_DLINESIZE - 1 - mcrne p15, 0, r0, c7, c10, 1 @ clean D entry - tst r1, #CACHE_DLINESIZE - 1 - mcrne p15, 0, r1, c7, c10, 1 @ clean D entry -- bic r0, r0, #CACHE_DLINESIZE - 1 - 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry - add r0, r0, #CACHE_DLINESIZE - cmp r0, r1 -@@ -236,6 +285,22 @@ - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mov pc, lr - -+ .align 5 -+ENTRY(feroceon_range_dma_inv_range) -+ mrs r2, cpsr -+ tst r0, #CACHE_DLINESIZE - 1 -+ mcrne p15, 0, r0, c7, c10, 1 @ clean D entry -+ tst r1, #CACHE_DLINESIZE - 1 -+ mcrne p15, 0, r1, c7, c10, 1 @ clean D entry -+ cmp r1, r0 -+ subne r1, r1, #1 @ top address is inclusive -+ orr r3, r2, #PSR_I_BIT -+ msr cpsr_c, r3 @ disable interrupts -+ mcr p15, 5, r0, c15, c14, 0 @ D inv range start -+ mcr p15, 5, r1, c15, c14, 1 @ D inv range top -+ msr cpsr_c, r2 @ restore interrupts -+ mov pc, lr -+ - /* - * dma_clean_range(start, end) - * -@@ -256,6 +321,19 @@ - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mov pc, lr - -+ .align 5 -+ENTRY(feroceon_range_dma_clean_range) -+ mrs r2, cpsr -+ cmp r1, r0 -+ subne r1, r1, #1 @ top address is inclusive -+ orr r3, r2, #PSR_I_BIT -+ msr cpsr_c, r3 @ disable interrupts -+ mcr p15, 5, r0, c15, c13, 0 @ D clean range start -+ mcr p15, 5, r1, c15, c13, 1 @ D clean range top -+ msr cpsr_c, r2 @ restore interrupts -+ mcr p15, 0, r0, c7, c10, 4 @ drain WB -+ mov pc, lr -+ - /* - * dma_flush_range(start, end) - * -@@ -274,6 +352,19 @@ - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mov pc, lr - -+ .align 5 -+ENTRY(feroceon_range_dma_flush_range) -+ mrs r2, cpsr -+ cmp r1, r0 -+ subne r1, r1, #1 @ top address is inclusive -+ orr r3, r2, #PSR_I_BIT -+ msr cpsr_c, r3 @ disable interrupts -+ mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start -+ mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top -+ msr cpsr_c, r2 @ restore interrupts -+ mcr p15, 0, r0, c7, c10, 4 @ drain WB -+ mov pc, lr -+ - ENTRY(feroceon_cache_fns) - .long feroceon_flush_kern_cache_all - .long feroceon_flush_user_cache_all -@@ -285,12 +376,33 @@ - .long feroceon_dma_clean_range - .long feroceon_dma_flush_range - -+ENTRY(feroceon_range_cache_fns) -+ .long feroceon_flush_kern_cache_all -+ .long feroceon_flush_user_cache_all -+ .long feroceon_flush_user_cache_range -+ .long feroceon_coherent_kern_range -+ .long feroceon_coherent_user_range -+ .long feroceon_range_flush_kern_dcache_page -+ .long feroceon_range_dma_inv_range -+ .long feroceon_range_dma_clean_range -+ .long feroceon_range_dma_flush_range -+ - .align 5 - ENTRY(cpu_feroceon_dcache_clean_area) -+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) -+ mov r2, r0 -+ mov r3, r1 -+#endif - 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #CACHE_DLINESIZE - subs r1, r1, #CACHE_DLINESIZE - bhi 1b -+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) -+1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry -+ add r2, r2, #CACHE_DLINESIZE -+ subs r3, r3, #CACHE_DLINESIZE -+ bhi 1b -+#endif - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mov pc, lr - -@@ -306,16 +418,25 @@ - .align 5 - ENTRY(cpu_feroceon_switch_mm) - #ifdef CONFIG_MMU -- mov ip, #0 --@ && 'Clean & Invalidate whole DCache' --1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate -- bne 1b -- mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache -- mcr p15, 0, ip, c7, c10, 4 @ drain WB -+ /* -+ * Note: we wish to call __flush_whole_cache but we need to preserve -+ * lr to do so. The only way without touching main memory is to -+ * use r2 which is normally used to test the VM_EXEC flag, and -+ * compensate locally for the skipped ops if it is not set. -+ */ -+ mov r2, lr @ abuse r2 to preserve lr -+ bl __flush_whole_cache -+ @ if r2 contains the VM_EXEC bit then the next 2 ops are done already -+ tst r2, #VM_EXEC -+ mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache -+ mcreq p15, 0, ip, c7, c10, 4 @ drain WB -+ - mcr p15, 0, r0, c2, c0, 0 @ load page table pointer - mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs --#endif -+ mov pc, r2 -+#else - mov pc, lr -+#endif - - /* - * cpu_feroceon_set_pte_ext(ptep, pte, ext) -@@ -345,6 +466,9 @@ - str r2, [r0] @ hardware version - mov r0, r0 - mcr p15, 0, r0, c7, c10, 1 @ clean D entry -+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) -+ mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry -+#endif - mcr p15, 0, r0, c7, c10, 4 @ drain WB - #endif - mov pc, lr -@@ -414,6 +538,21 @@ - .asciz "Feroceon" - .size cpu_feroceon_name, . - cpu_feroceon_name - -+ .type cpu_88fr531_name, #object -+cpu_88fr531_name: -+ .asciz "Feroceon 88FR531-vd" -+ .size cpu_88fr531_name, . - cpu_88fr531_name -+ -+ .type cpu_88fr571_name, #object -+cpu_88fr571_name: -+ .asciz "Feroceon 88FR571-vd" -+ .size cpu_88fr571_name, . - cpu_88fr571_name -+ -+ .type cpu_88fr131_name, #object -+cpu_88fr131_name: -+ .asciz "Feroceon 88FR131" -+ .size cpu_88fr131_name, . - cpu_88fr131_name -+ - .align - - .section ".proc.info.init", #alloc, #execinstr -@@ -421,15 +560,15 @@ - #ifdef CONFIG_CPU_FEROCEON_OLD_ID - .type __feroceon_old_id_proc_info,#object - __feroceon_old_id_proc_info: -- .long 0x41069260 -- .long 0xfffffff0 -- .long PMD_TYPE_SECT | \ -+ .long 0x41009260 -+ .long 0xff00fff0 -+ .long PMD_TYPE_SECT | \ - PMD_SECT_BUFFERABLE | \ - PMD_SECT_CACHEABLE | \ - PMD_BIT4 | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ -- .long PMD_TYPE_SECT | \ -+ .long PMD_TYPE_SECT | \ - PMD_BIT4 | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ -@@ -445,17 +584,17 @@ - .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info - #endif - -- .type __feroceon_proc_info,#object --__feroceon_proc_info: -+ .type __88fr531_proc_info,#object -+__88fr531_proc_info: - .long 0x56055310 - .long 0xfffffff0 -- .long PMD_TYPE_SECT | \ -+ .long PMD_TYPE_SECT | \ - PMD_SECT_BUFFERABLE | \ - PMD_SECT_CACHEABLE | \ - PMD_BIT4 | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ -- .long PMD_TYPE_SECT | \ -+ .long PMD_TYPE_SECT | \ - PMD_BIT4 | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ -@@ -463,9 +602,59 @@ - .long cpu_arch_name - .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP -- .long cpu_feroceon_name -+ .long cpu_88fr531_name - .long feroceon_processor_functions - .long v4wbi_tlb_fns - .long feroceon_user_fns - .long feroceon_cache_fns -- .size __feroceon_proc_info, . - __feroceon_proc_info -+ .size __88fr531_proc_info, . - __88fr531_proc_info -+ -+ .type __88fr571_proc_info,#object -+__88fr571_proc_info: -+ .long 0x56155710 -+ .long 0xfffffff0 -+ .long PMD_TYPE_SECT | \ -+ PMD_SECT_BUFFERABLE | \ -+ PMD_SECT_CACHEABLE | \ -+ PMD_BIT4 | \ -+ PMD_SECT_AP_WRITE | \ -+ PMD_SECT_AP_READ -+ .long PMD_TYPE_SECT | \ -+ PMD_BIT4 | \ -+ PMD_SECT_AP_WRITE | \ -+ PMD_SECT_AP_READ -+ b __feroceon_setup -+ .long cpu_arch_name -+ .long cpu_elf_name -+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP -+ .long cpu_88fr571_name -+ .long feroceon_processor_functions -+ .long v4wbi_tlb_fns -+ .long feroceon_user_fns -+ .long feroceon_range_cache_fns -+ .size __88fr571_proc_info, . - __88fr571_proc_info -+ -+ .type __88fr131_proc_info,#object -+__88fr131_proc_info: -+ .long 0x56251310 -+ .long 0xfffffff0 -+ .long PMD_TYPE_SECT | \ -+ PMD_SECT_BUFFERABLE | \ -+ PMD_SECT_CACHEABLE | \ -+ PMD_BIT4 | \ -+ PMD_SECT_AP_WRITE | \ -+ PMD_SECT_AP_READ -+ .long PMD_TYPE_SECT | \ -+ PMD_BIT4 | \ -+ PMD_SECT_AP_WRITE | \ -+ PMD_SECT_AP_READ -+ b __feroceon_setup -+ .long cpu_arch_name -+ .long cpu_elf_name -+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP -+ .long cpu_88fr131_name -+ .long feroceon_processor_functions -+ .long v4wbi_tlb_fns -+ .long feroceon_user_fns -+ .long feroceon_range_cache_fns -+ .size __88fr131_proc_info, . - __88fr131_proc_info ---- a/arch/arm/plat-orion/irq.c -+++ b/arch/arm/plat-orion/irq.c -@@ -36,8 +36,8 @@ - - static struct irq_chip orion_irq_chip = { - .name = "orion_irq", -- .ack = orion_irq_mask, - .mask = orion_irq_mask, -+ .mask_ack = orion_irq_mask, - .unmask = orion_irq_unmask, - }; - -@@ -59,6 +59,7 @@ - set_irq_chip(irq, &orion_irq_chip); - set_irq_chip_data(irq, maskaddr); - set_irq_handler(irq, handle_level_irq); -+ irq_desc[irq].status |= IRQ_LEVEL; - set_irq_flags(irq, IRQF_VALID); - } - } ---- a/arch/arm/plat-orion/pcie.c -+++ b/arch/arm/plat-orion/pcie.c -@@ -39,6 +39,7 @@ - #define PCIE_CONF_DATA_OFF 0x18fc - #define PCIE_MASK_OFF 0x1910 - #define PCIE_CTRL_OFF 0x1a00 -+#define PCIE_CTRL_X1_MODE 0x0001 - #define PCIE_STAT_OFF 0x1a04 - #define PCIE_STAT_DEV_OFFS 20 - #define PCIE_STAT_DEV_MASK 0x1f -@@ -62,6 +63,11 @@ - return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); - } - -+int __init orion_pcie_x4_mode(void __iomem *base) -+{ -+ return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); -+} -+ - int orion_pcie_get_local_bus_nr(void __iomem *base) - { - u32 stat = readl(base + PCIE_STAT_OFF); ---- a/arch/arm/plat-orion/time.c -+++ b/arch/arm/plat-orion/time.c -@@ -74,7 +74,7 @@ - /* - * Clear and enable clockevent timer interrupt. - */ -- writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); -+ writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); - - u = readl(BRIDGE_MASK); - u |= BRIDGE_INT_TIMER1; -@@ -138,7 +138,7 @@ - /* - * ACK pending timer interrupt. - */ -- writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); -+ writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); - - } - local_irq_restore(flags); -@@ -159,7 +159,7 @@ - /* - * ACK timer interrupt and call event handler. - */ -- writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); -+ writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); - orion_clkevt.event_handler(&orion_clkevt); - - return IRQ_HANDLED; ---- a/drivers/net/mv643xx_eth.c -+++ b/drivers/net/mv643xx_eth.c -@@ -34,406 +34,145 @@ - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -+ - #include - #include - #include --#include - #include - #include - #include -- --#include - #include - #include - #include -- - #include - #include - #include - #include - #include -- - #include -- - #include - #include --#include - #include --#include --#include - --#define MV643XX_CHECKSUM_OFFLOAD_TX --#define MV643XX_NAPI --#define MV643XX_TX_FAST_REFILL --#undef MV643XX_COAL -- --#define MV643XX_TX_COAL 100 --#ifdef MV643XX_COAL --#define MV643XX_RX_COAL 100 --#endif -+static char mv643xx_eth_driver_name[] = "mv643xx_eth"; -+static char mv643xx_eth_driver_version[] = "1.1"; - --#ifdef MV643XX_CHECKSUM_OFFLOAD_TX -+#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX -+#define MV643XX_ETH_NAPI -+#define MV643XX_ETH_TX_FAST_REFILL -+ -+#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX - #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) - #else - #define MAX_DESCS_PER_SKB 1 - #endif - --#define ETH_VLAN_HLEN 4 --#define ETH_FCS_LEN 4 --#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ --#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ -- ETH_VLAN_HLEN + ETH_FCS_LEN) --#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \ -- dma_get_cache_alignment()) -- - /* - * Registers shared between all ports. - */ --#define PHY_ADDR_REG 0x0000 --#define SMI_REG 0x0004 --#define WINDOW_BASE(i) (0x0200 + ((i) << 3)) --#define WINDOW_SIZE(i) (0x0204 + ((i) << 3)) --#define WINDOW_REMAP_HIGH(i) (0x0280 + ((i) << 2)) --#define WINDOW_BAR_ENABLE 0x0290 --#define WINDOW_PROTECT(i) (0x0294 + ((i) << 4)) -+#define PHY_ADDR 0x0000 -+#define SMI_REG 0x0004 -+#define WINDOW_BASE(w) (0x0200 + ((w) << 3)) -+#define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) -+#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) -+#define WINDOW_BAR_ENABLE 0x0290 -+#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) - - /* - * Per-port registers. - */ --#define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10)) --#define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10)) --#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) --#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) --#define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10)) --#define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10)) --#define PORT_STATUS_REG(p) (0x0444 + ((p) << 10)) --#define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10)) --#define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10)) --#define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10)) --#define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10)) --#define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10)) --#define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10)) --#define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10)) --#define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10)) --#define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10)) --#define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10)) --#define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7)) --#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10)) --#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10)) --#define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10)) -- --/* These macros describe Ethernet Port configuration reg (Px_cR) bits */ --#define UNICAST_NORMAL_MODE (0 << 0) --#define UNICAST_PROMISCUOUS_MODE (1 << 0) --#define DEFAULT_RX_QUEUE(queue) ((queue) << 1) --#define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4) --#define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7) --#define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) --#define RECEIVE_BC_IF_IP (0 << 8) --#define REJECT_BC_IF_IP (1 << 8) --#define RECEIVE_BC_IF_ARP (0 << 9) --#define REJECT_BC_IF_ARP (1 << 9) --#define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12) --#define CAPTURE_TCP_FRAMES_DIS (0 << 14) --#define CAPTURE_TCP_FRAMES_EN (1 << 14) --#define CAPTURE_UDP_FRAMES_DIS (0 << 15) --#define CAPTURE_UDP_FRAMES_EN (1 << 15) --#define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16) --#define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19) --#define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22) -- --#define PORT_CONFIG_DEFAULT_VALUE \ -- UNICAST_NORMAL_MODE | \ -- DEFAULT_RX_QUEUE(0) | \ -- DEFAULT_RX_ARP_QUEUE(0) | \ -- RECEIVE_BC_IF_NOT_IP_OR_ARP | \ -- RECEIVE_BC_IF_IP | \ -- RECEIVE_BC_IF_ARP | \ -- CAPTURE_TCP_FRAMES_DIS | \ -- CAPTURE_UDP_FRAMES_DIS | \ -- DEFAULT_RX_TCP_QUEUE(0) | \ -- DEFAULT_RX_UDP_QUEUE(0) | \ -- DEFAULT_RX_BPDU_QUEUE(0) -- --/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/ --#define CLASSIFY_EN (1 << 0) --#define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1) --#define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1) --#define PARTITION_DISABLE (0 << 2) --#define PARTITION_ENABLE (1 << 2) -- --#define PORT_CONFIG_EXTEND_DEFAULT_VALUE \ -- SPAN_BPDU_PACKETS_AS_NORMAL | \ -- PARTITION_DISABLE -- --/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */ --#define RIFB (1 << 0) --#define RX_BURST_SIZE_1_64BIT (0 << 1) --#define RX_BURST_SIZE_2_64BIT (1 << 1) -+#define PORT_CONFIG(p) (0x0400 + ((p) << 10)) -+#define UNICAST_PROMISCUOUS_MODE 0x00000001 -+#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10)) -+#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) -+#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) -+#define SDMA_CONFIG(p) (0x041c + ((p) << 10)) -+#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) -+#define PORT_STATUS(p) (0x0444 + ((p) << 10)) -+#define TX_FIFO_EMPTY 0x00000400 -+#define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) -+#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10)) -+#define TX_BW_RATE(p) (0x0450 + ((p) << 10)) -+#define TX_BW_MTU(p) (0x0458 + ((p) << 10)) -+#define TX_BW_BURST(p) (0x045c + ((p) << 10)) -+#define INT_CAUSE(p) (0x0460 + ((p) << 10)) -+#define INT_TX_END 0x07f80000 -+#define INT_RX 0x0007fbfc -+#define INT_EXT 0x00000002 -+#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) -+#define INT_EXT_LINK 0x00100000 -+#define INT_EXT_PHY 0x00010000 -+#define INT_EXT_TX_ERROR_0 0x00000100 -+#define INT_EXT_TX_0 0x00000001 -+#define INT_EXT_TX 0x0000ffff -+#define INT_MASK(p) (0x0468 + ((p) << 10)) -+#define INT_MASK_EXT(p) (0x046c + ((p) << 10)) -+#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) -+#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10)) -+#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10)) -+#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10)) -+#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10)) -+#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4)) -+#define RXQ_COMMAND(p) (0x0680 + ((p) << 10)) -+#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2)) -+#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4)) -+#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4)) -+#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4)) -+#define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) -+#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) -+#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) -+#define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) -+ -+ -+/* -+ * SDMA configuration register. -+ */ - #define RX_BURST_SIZE_4_64BIT (2 << 1) --#define RX_BURST_SIZE_8_64BIT (3 << 1) --#define RX_BURST_SIZE_16_64BIT (4 << 1) - #define BLM_RX_NO_SWAP (1 << 4) --#define BLM_RX_BYTE_SWAP (0 << 4) - #define BLM_TX_NO_SWAP (1 << 5) --#define BLM_TX_BYTE_SWAP (0 << 5) --#define DESCRIPTORS_BYTE_SWAP (1 << 6) --#define DESCRIPTORS_NO_SWAP (0 << 6) --#define IPG_INT_RX(value) (((value) & 0x3fff) << 8) --#define TX_BURST_SIZE_1_64BIT (0 << 22) --#define TX_BURST_SIZE_2_64BIT (1 << 22) - #define TX_BURST_SIZE_4_64BIT (2 << 22) --#define TX_BURST_SIZE_8_64BIT (3 << 22) --#define TX_BURST_SIZE_16_64BIT (4 << 22) - - #if defined(__BIG_ENDIAN) - #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ - RX_BURST_SIZE_4_64BIT | \ -- IPG_INT_RX(0) | \ - TX_BURST_SIZE_4_64BIT - #elif defined(__LITTLE_ENDIAN) - #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ - RX_BURST_SIZE_4_64BIT | \ - BLM_RX_NO_SWAP | \ - BLM_TX_NO_SWAP | \ -- IPG_INT_RX(0) | \ - TX_BURST_SIZE_4_64BIT - #else - #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined - #endif - --/* These macros describe Ethernet Port serial control reg (PSCR) bits */ --#define SERIAL_PORT_DISABLE (0 << 0) --#define SERIAL_PORT_ENABLE (1 << 0) --#define DO_NOT_FORCE_LINK_PASS (0 << 1) --#define FORCE_LINK_PASS (1 << 1) --#define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2) --#define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2) --#define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3) --#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) --#define ADV_NO_FLOW_CTRL (0 << 4) --#define ADV_SYMMETRIC_FLOW_CTRL (1 << 4) --#define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5) --#define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) --#define FORCE_BP_MODE_NO_JAM (0 << 7) --#define FORCE_BP_MODE_JAM_TX (1 << 7) --#define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7) --#define SERIAL_PORT_CONTROL_RESERVED (1 << 9) --#define FORCE_LINK_FAIL (0 << 10) --#define DO_NOT_FORCE_LINK_FAIL (1 << 10) --#define RETRANSMIT_16_ATTEMPTS (0 << 11) --#define RETRANSMIT_FOREVER (1 << 11) --#define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13) --#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) --#define DTE_ADV_0 (0 << 14) --#define DTE_ADV_1 (1 << 14) --#define DISABLE_AUTO_NEG_BYPASS (0 << 15) --#define ENABLE_AUTO_NEG_BYPASS (1 << 15) --#define AUTO_NEG_NO_CHANGE (0 << 16) --#define RESTART_AUTO_NEG (1 << 16) --#define MAX_RX_PACKET_1518BYTE (0 << 17) -+ -+/* -+ * Port serial control register. -+ */ -+#define SET_MII_SPEED_TO_100 (1 << 24) -+#define SET_GMII_SPEED_TO_1000 (1 << 23) -+#define SET_FULL_DUPLEX_MODE (1 << 21) - #define MAX_RX_PACKET_1522BYTE (1 << 17) --#define MAX_RX_PACKET_1552BYTE (2 << 17) --#define MAX_RX_PACKET_9022BYTE (3 << 17) --#define MAX_RX_PACKET_9192BYTE (4 << 17) - #define MAX_RX_PACKET_9700BYTE (5 << 17) - #define MAX_RX_PACKET_MASK (7 << 17) --#define CLR_EXT_LOOPBACK (0 << 20) --#define SET_EXT_LOOPBACK (1 << 20) --#define SET_HALF_DUPLEX_MODE (0 << 21) --#define SET_FULL_DUPLEX_MODE (1 << 21) --#define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22) --#define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) --#define SET_GMII_SPEED_TO_10_100 (0 << 23) --#define SET_GMII_SPEED_TO_1000 (1 << 23) --#define SET_MII_SPEED_TO_10 (0 << 24) --#define SET_MII_SPEED_TO_100 (1 << 24) -+#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) -+#define DO_NOT_FORCE_LINK_FAIL (1 << 10) -+#define SERIAL_PORT_CONTROL_RESERVED (1 << 9) -+#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) -+#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) -+#define FORCE_LINK_PASS (1 << 1) -+#define SERIAL_PORT_ENABLE (1 << 0) -+ -+#define DEFAULT_RX_QUEUE_SIZE 400 -+#define DEFAULT_TX_QUEUE_SIZE 800 - --#define PORT_SERIAL_CONTROL_DEFAULT_VALUE \ -- DO_NOT_FORCE_LINK_PASS | \ -- ENABLE_AUTO_NEG_FOR_DUPLX | \ -- DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ -- ADV_SYMMETRIC_FLOW_CTRL | \ -- FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ -- FORCE_BP_MODE_NO_JAM | \ -- (1 << 9) /* reserved */ | \ -- DO_NOT_FORCE_LINK_FAIL | \ -- RETRANSMIT_16_ATTEMPTS | \ -- ENABLE_AUTO_NEG_SPEED_GMII | \ -- DTE_ADV_0 | \ -- DISABLE_AUTO_NEG_BYPASS | \ -- AUTO_NEG_NO_CHANGE | \ -- MAX_RX_PACKET_9700BYTE | \ -- CLR_EXT_LOOPBACK | \ -- SET_FULL_DUPLEX_MODE | \ -- ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX -- --/* These macros describe Ethernet Serial Status reg (PSR) bits */ --#define PORT_STATUS_MODE_10_BIT (1 << 0) --#define PORT_STATUS_LINK_UP (1 << 1) --#define PORT_STATUS_FULL_DUPLEX (1 << 2) --#define PORT_STATUS_FLOW_CONTROL (1 << 3) --#define PORT_STATUS_GMII_1000 (1 << 4) --#define PORT_STATUS_MII_100 (1 << 5) --/* PSR bit 6 is undocumented */ --#define PORT_STATUS_TX_IN_PROGRESS (1 << 7) --#define PORT_STATUS_AUTONEG_BYPASSED (1 << 8) --#define PORT_STATUS_PARTITION (1 << 9) --#define PORT_STATUS_TX_FIFO_EMPTY (1 << 10) --/* PSR bits 11-31 are reserved */ -- --#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 --#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 -- --#define DESC_SIZE 64 -- --#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ --#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ -- --#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2) --#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9) --#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR) --#define ETH_INT_CAUSE_EXT 0x00000002 --#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT) -- --#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0) --#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8) --#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR) --#define ETH_INT_CAUSE_PHY 0x00010000 --#define ETH_INT_CAUSE_STATE 0x00100000 --#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \ -- ETH_INT_CAUSE_STATE) -- --#define ETH_INT_MASK_ALL 0x00000000 --#define ETH_INT_MASK_ALL_EXT 0x00000000 -- --#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ --#define PHY_WAIT_MICRO_SECONDS 10 -- --/* Buffer offset from buffer pointer */ --#define RX_BUF_OFFSET 0x2 -- --/* Gigabit Ethernet Unit Global Registers */ -- --/* MIB Counters register definitions */ --#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 --#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 --#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 --#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc --#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 --#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 --#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 --#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c --#define ETH_MIB_FRAMES_64_OCTETS 0x20 --#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 --#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 --#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c --#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 --#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 --#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 --#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c --#define ETH_MIB_GOOD_FRAMES_SENT 0x40 --#define ETH_MIB_EXCESSIVE_COLLISION 0x44 --#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 --#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c --#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 --#define ETH_MIB_FC_SENT 0x54 --#define ETH_MIB_GOOD_FC_RECEIVED 0x58 --#define ETH_MIB_BAD_FC_RECEIVED 0x5c --#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 --#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 --#define ETH_MIB_OVERSIZE_RECEIVED 0x68 --#define ETH_MIB_JABBER_RECEIVED 0x6c --#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 --#define ETH_MIB_BAD_CRC_EVENT 0x74 --#define ETH_MIB_COLLISION 0x78 --#define ETH_MIB_LATE_COLLISION 0x7c -- --/* Port serial status reg (PSR) */ --#define ETH_INTERFACE_PCM 0x00000001 --#define ETH_LINK_IS_UP 0x00000002 --#define ETH_PORT_AT_FULL_DUPLEX 0x00000004 --#define ETH_RX_FLOW_CTRL_ENABLED 0x00000008 --#define ETH_GMII_SPEED_1000 0x00000010 --#define ETH_MII_SPEED_100 0x00000020 --#define ETH_TX_IN_PROGRESS 0x00000080 --#define ETH_BYPASS_ACTIVE 0x00000100 --#define ETH_PORT_AT_PARTITION_STATE 0x00000200 --#define ETH_PORT_TX_FIFO_EMPTY 0x00000400 -- --/* SMI reg */ --#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ --#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ --#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ --#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ -- --/* Interrupt Cause Register Bit Definitions */ -- --/* SDMA command status fields macros */ -- --/* Tx & Rx descriptors status */ --#define ETH_ERROR_SUMMARY 0x00000001 -- --/* Tx & Rx descriptors command */ --#define ETH_BUFFER_OWNED_BY_DMA 0x80000000 -- --/* Tx descriptors status */ --#define ETH_LC_ERROR 0 --#define ETH_UR_ERROR 0x00000002 --#define ETH_RL_ERROR 0x00000004 --#define ETH_LLC_SNAP_FORMAT 0x00000200 -- --/* Rx descriptors status */ --#define ETH_OVERRUN_ERROR 0x00000002 --#define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004 --#define ETH_RESOURCE_ERROR 0x00000006 --#define ETH_VLAN_TAGGED 0x00080000 --#define ETH_BPDU_FRAME 0x00100000 --#define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000 --#define ETH_OTHER_FRAME_TYPE 0x00400000 --#define ETH_LAYER_2_IS_ETH_V_2 0x00800000 --#define ETH_FRAME_TYPE_IP_V_4 0x01000000 --#define ETH_FRAME_HEADER_OK 0x02000000 --#define ETH_RX_LAST_DESC 0x04000000 --#define ETH_RX_FIRST_DESC 0x08000000 --#define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000 --#define ETH_RX_ENABLE_INTERRUPT 0x20000000 --#define ETH_LAYER_4_CHECKSUM_OK 0x40000000 -- --/* Rx descriptors byte count */ --#define ETH_FRAME_FRAGMENTED 0x00000004 -- --/* Tx descriptors command */ --#define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400 --#define ETH_FRAME_SET_TO_VLAN 0x00008000 --#define ETH_UDP_FRAME 0x00010000 --#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000 --#define ETH_GEN_IP_V_4_CHECKSUM 0x00040000 --#define ETH_ZERO_PADDING 0x00080000 --#define ETH_TX_LAST_DESC 0x00100000 --#define ETH_TX_FIRST_DESC 0x00200000 --#define ETH_GEN_CRC 0x00400000 --#define ETH_TX_ENABLE_INTERRUPT 0x00800000 --#define ETH_AUTO_MODE 0x40000000 -- --#define ETH_TX_IHL_SHIFT 11 -- --/* typedefs */ -- --typedef enum _eth_func_ret_status { -- ETH_OK, /* Returned as expected. */ -- ETH_ERROR, /* Fundamental error. */ -- ETH_RETRY, /* Could not process request. Try later.*/ -- ETH_END_OF_JOB, /* Ring has nothing to process. */ -- ETH_QUEUE_FULL, /* Ring resource error. */ -- ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ --} ETH_FUNC_RET_STATUS; - --/* These are for big-endian machines. Little endian needs different -- * definitions. -+/* -+ * RX/TX descriptors. - */ - #if defined(__BIG_ENDIAN) --struct eth_rx_desc { -+struct rx_desc { - u16 byte_cnt; /* Descriptor buffer byte count */ - u16 buf_size; /* Buffer size */ - u32 cmd_sts; /* Descriptor command status */ -@@ -441,7 +180,7 @@ - u32 buf_ptr; /* Descriptor buffer pointer */ - }; - --struct eth_tx_desc { -+struct tx_desc { - u16 byte_cnt; /* buffer byte count */ - u16 l4i_chk; /* CPU provided TCP checksum */ - u32 cmd_sts; /* Command/status field */ -@@ -449,7 +188,7 @@ - u32 buf_ptr; /* pointer to buffer for this descriptor*/ - }; - #elif defined(__LITTLE_ENDIAN) --struct eth_rx_desc { -+struct rx_desc { - u32 cmd_sts; /* Descriptor command status */ - u16 buf_size; /* Buffer size */ - u16 byte_cnt; /* Descriptor buffer byte count */ -@@ -457,7 +196,7 @@ - u32 next_desc_ptr; /* Next descriptor pointer */ - }; - --struct eth_tx_desc { -+struct tx_desc { - u32 cmd_sts; /* Command/status field */ - u16 l4i_chk; /* CPU provided TCP checksum */ - u16 byte_cnt; /* buffer byte count */ -@@ -468,18 +207,59 @@ - #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined - #endif - --/* Unified struct for Rx and Tx operations. The user is not required to */ --/* be familier with neither Tx nor Rx descriptors. */ --struct pkt_info { -- unsigned short byte_cnt; /* Descriptor buffer byte count */ -- unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ -- unsigned int cmd_sts; /* Descriptor command status */ -- dma_addr_t buf_ptr; /* Descriptor buffer pointer */ -- struct sk_buff *return_info; /* User resource return information */ -+/* RX & TX descriptor command */ -+#define BUFFER_OWNED_BY_DMA 0x80000000 -+ -+/* RX & TX descriptor status */ -+#define ERROR_SUMMARY 0x00000001 -+ -+/* RX descriptor status */ -+#define LAYER_4_CHECKSUM_OK 0x40000000 -+#define RX_ENABLE_INTERRUPT 0x20000000 -+#define RX_FIRST_DESC 0x08000000 -+#define RX_LAST_DESC 0x04000000 -+ -+/* TX descriptor command */ -+#define TX_ENABLE_INTERRUPT 0x00800000 -+#define GEN_CRC 0x00400000 -+#define TX_FIRST_DESC 0x00200000 -+#define TX_LAST_DESC 0x00100000 -+#define ZERO_PADDING 0x00080000 -+#define GEN_IP_V4_CHECKSUM 0x00040000 -+#define GEN_TCP_UDP_CHECKSUM 0x00020000 -+#define UDP_FRAME 0x00010000 -+ -+#define TX_IHL_SHIFT 11 -+ -+ -+/* global *******************************************************************/ -+struct mv643xx_eth_shared_private { -+ /* -+ * Ethernet controller base address. -+ */ -+ void __iomem *base; -+ -+ /* -+ * Protects access to SMI_REG, which is shared between ports. -+ */ -+ spinlock_t phy_lock; -+ -+ /* -+ * Per-port MBUS window access register value. -+ */ -+ u32 win_protect; -+ -+ /* -+ * Hardware-specific parameters. -+ */ -+ unsigned int t_clk; -+ int extended_rx_coal_limit; -+ int tx_bw_control_moved; - }; - --/* Ethernet port specific information */ --struct mv643xx_mib_counters { -+ -+/* per-port *****************************************************************/ -+struct mib_counters { - u64 good_octets_received; - u32 bad_octets_received; - u32 internal_mac_transmit_err; -@@ -512,461 +292,282 @@ - u32 late_collision; - }; - --struct mv643xx_shared_private { -- void __iomem *eth_base; -- -- /* used to protect SMI_REG, which is shared across ports */ -- spinlock_t phy_lock; -- -- u32 win_protect; -- -- unsigned int t_clk; --}; -- --struct mv643xx_private { -- struct mv643xx_shared_private *shared; -- int port_num; /* User Ethernet port number */ -- -- struct mv643xx_shared_private *shared_smi; -+struct rx_queue { -+ int index; - -- u32 rx_sram_addr; /* Base address of rx sram area */ -- u32 rx_sram_size; /* Size of rx sram area */ -- u32 tx_sram_addr; /* Base address of tx sram area */ -- u32 tx_sram_size; /* Size of tx sram area */ -+ int rx_ring_size; - -- int rx_resource_err; /* Rx ring resource error flag */ -+ int rx_desc_count; -+ int rx_curr_desc; -+ int rx_used_desc; - -- /* Tx/Rx rings managment indexes fields. For driver use */ -+ struct rx_desc *rx_desc_area; -+ dma_addr_t rx_desc_dma; -+ int rx_desc_area_size; -+ struct sk_buff **rx_skb; - -- /* Next available and first returning Rx resource */ -- int rx_curr_desc_q, rx_used_desc_q; -+ struct timer_list rx_oom; -+}; - -- /* Next available and first returning Tx resource */ -- int tx_curr_desc_q, tx_used_desc_q; -+struct tx_queue { -+ int index; - --#ifdef MV643XX_TX_FAST_REFILL -- u32 tx_clean_threshold; --#endif -+ int tx_ring_size; - -- struct eth_rx_desc *p_rx_desc_area; -- dma_addr_t rx_desc_dma; -- int rx_desc_area_size; -- struct sk_buff **rx_skb; -+ int tx_desc_count; -+ int tx_curr_desc; -+ int tx_used_desc; - -- struct eth_tx_desc *p_tx_desc_area; -+ struct tx_desc *tx_desc_area; - dma_addr_t tx_desc_dma; - int tx_desc_area_size; - struct sk_buff **tx_skb; -+}; - -- struct work_struct tx_timeout_task; -+struct mv643xx_eth_private { -+ struct mv643xx_eth_shared_private *shared; -+ int port_num; - - struct net_device *dev; -- struct napi_struct napi; -- struct net_device_stats stats; -- struct mv643xx_mib_counters mib_counters; -+ -+ struct mv643xx_eth_shared_private *shared_smi; -+ int phy_addr; -+ - spinlock_t lock; -- /* Size of Tx Ring per queue */ -- int tx_ring_size; -- /* Number of tx descriptors in use */ -- int tx_desc_count; -- /* Size of Rx Ring per queue */ -- int rx_ring_size; -- /* Number of rx descriptors in use */ -- int rx_desc_count; -+ -+ struct mib_counters mib_counters; -+ struct work_struct tx_timeout_task; -+ struct mii_if_info mii; - - /* -- * Used in case RX Ring is empty, which can be caused when -- * system does not have resources (skb's) -+ * RX state. - */ -- struct timer_list timeout; -- -- u32 rx_int_coal; -- u32 tx_int_coal; -- struct mii_if_info mii; --}; -+ int default_rx_ring_size; -+ unsigned long rx_desc_sram_addr; -+ int rx_desc_sram_size; -+ u8 rxq_mask; -+ int rxq_primary; -+ struct napi_struct napi; -+ struct rx_queue rxq[8]; - --/* Static function declarations */ --static void eth_port_init(struct mv643xx_private *mp); --static void eth_port_reset(struct mv643xx_private *mp); --static void eth_port_start(struct net_device *dev); -- --static void ethernet_phy_reset(struct mv643xx_private *mp); -- --static void eth_port_write_smi_reg(struct mv643xx_private *mp, -- unsigned int phy_reg, unsigned int value); -- --static void eth_port_read_smi_reg(struct mv643xx_private *mp, -- unsigned int phy_reg, unsigned int *value); -- --static void eth_clear_mib_counters(struct mv643xx_private *mp); -- --static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, -- struct pkt_info *p_pkt_info); --static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, -- struct pkt_info *p_pkt_info); -- --static void eth_port_uc_addr_get(struct mv643xx_private *mp, -- unsigned char *p_addr); --static void eth_port_uc_addr_set(struct mv643xx_private *mp, -- unsigned char *p_addr); --static void eth_port_set_multicast_list(struct net_device *); --static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, -- unsigned int queues); --static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp, -- unsigned int queues); --static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp); --static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp); --static int mv643xx_eth_open(struct net_device *); --static int mv643xx_eth_stop(struct net_device *); --static void eth_port_init_mac_tables(struct mv643xx_private *mp); --#ifdef MV643XX_NAPI --static int mv643xx_poll(struct napi_struct *napi, int budget); -+ /* -+ * TX state. -+ */ -+ int default_tx_ring_size; -+ unsigned long tx_desc_sram_addr; -+ int tx_desc_sram_size; -+ u8 txq_mask; -+ int txq_primary; -+ struct tx_queue txq[8]; -+#ifdef MV643XX_ETH_TX_FAST_REFILL -+ int tx_clean_threshold; - #endif --static int ethernet_phy_get(struct mv643xx_private *mp); --static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr); --static int ethernet_phy_detect(struct mv643xx_private *mp); --static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location); --static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val); --static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); --static const struct ethtool_ops mv643xx_ethtool_ops; -+}; - --static char mv643xx_driver_name[] = "mv643xx_eth"; --static char mv643xx_driver_version[] = "1.0"; - --static inline u32 rdl(struct mv643xx_private *mp, int offset) -+/* port register accessors **************************************************/ -+static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) - { -- return readl(mp->shared->eth_base + offset); -+ return readl(mp->shared->base + offset); - } - --static inline void wrl(struct mv643xx_private *mp, int offset, u32 data) -+static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) - { -- writel(data, mp->shared->eth_base + offset); -+ writel(data, mp->shared->base + offset); - } - --/* -- * Changes MTU (maximum transfer unit) of the gigabit ethenret port -- * -- * Input : pointer to ethernet interface network device structure -- * new mtu size -- * Output : 0 upon success, -EINVAL upon failure -- */ --static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) --{ -- if ((new_mtu > 9500) || (new_mtu < 64)) -- return -EINVAL; -- -- dev->mtu = new_mtu; -- if (!netif_running(dev)) -- return 0; -- -- /* -- * Stop and then re-open the interface. This will allocate RX -- * skbs of the new MTU. -- * There is a possible danger that the open will not succeed, -- * due to memory being full, which might fail the open function. -- */ -- mv643xx_eth_stop(dev); -- if (mv643xx_eth_open(dev)) { -- printk(KERN_ERR "%s: Fatal error on opening device\n", -- dev->name); -- } -- -- return 0; --} - --/* -- * mv643xx_eth_rx_refill_descs -- * -- * Fills / refills RX queue on a certain gigabit ethernet port -- * -- * Input : pointer to ethernet interface network device structure -- * Output : N/A -- */ --static void mv643xx_eth_rx_refill_descs(struct net_device *dev) -+/* rxq/txq helper functions *************************************************/ -+static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- struct pkt_info pkt_info; -- struct sk_buff *skb; -- int unaligned; -- -- while (mp->rx_desc_count < mp->rx_ring_size) { -- skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment()); -- if (!skb) -- break; -- mp->rx_desc_count++; -- unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); -- if (unaligned) -- skb_reserve(skb, dma_get_cache_alignment() - unaligned); -- pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; -- pkt_info.byte_cnt = ETH_RX_SKB_SIZE; -- pkt_info.buf_ptr = dma_map_single(NULL, skb->data, -- ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); -- pkt_info.return_info = skb; -- if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { -- printk(KERN_ERR -- "%s: Error allocating RX Ring\n", dev->name); -- break; -- } -- skb_reserve(skb, ETH_HW_IP_ALIGN); -- } -- /* -- * If RX ring is empty of SKB, set a timer to try allocating -- * again at a later time. -- */ -- if (mp->rx_desc_count == 0) { -- printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); -- mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */ -- add_timer(&mp->timeout); -- } -+ return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); - } - --/* -- * mv643xx_eth_rx_refill_descs_timer_wrapper -- * -- * Timer routine to wake up RX queue filling task. This function is -- * used only in case the RX queue is empty, and all alloc_skb has -- * failed (due to out of memory event). -- * -- * Input : pointer to ethernet interface network device structure -- * Output : N/A -- */ --static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data) -+static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) - { -- mv643xx_eth_rx_refill_descs((struct net_device *)data); -+ return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); - } - --/* -- * mv643xx_eth_update_mac_address -- * -- * Update the MAC address of the port in the address table -- * -- * Input : pointer to ethernet interface network device structure -- * Output : N/A -- */ --static void mv643xx_eth_update_mac_address(struct net_device *dev) -+static void rxq_enable(struct rx_queue *rxq) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- -- eth_port_init_mac_tables(mp); -- eth_port_uc_addr_set(mp, dev->dev_addr); -+ struct mv643xx_eth_private *mp = rxq_to_mp(rxq); -+ wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index); - } - --/* -- * mv643xx_eth_set_rx_mode -- * -- * Change from promiscuos to regular rx mode -- * -- * Input : pointer to ethernet interface network device structure -- * Output : N/A -- */ --static void mv643xx_eth_set_rx_mode(struct net_device *dev) -+static void rxq_disable(struct rx_queue *rxq) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- u32 config_reg; -- -- config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num)); -- if (dev->flags & IFF_PROMISC) -- config_reg |= (u32) UNICAST_PROMISCUOUS_MODE; -- else -- config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE; -- wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg); -+ struct mv643xx_eth_private *mp = rxq_to_mp(rxq); -+ u8 mask = 1 << rxq->index; - -- eth_port_set_multicast_list(dev); -+ wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8); -+ while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask) -+ udelay(10); - } - --/* -- * mv643xx_eth_set_mac_address -- * -- * Change the interface's mac address. -- * No special hardware thing should be done because interface is always -- * put in promiscuous mode. -- * -- * Input : pointer to ethernet interface network device structure and -- * a pointer to the designated entry to be added to the cache. -- * Output : zero upon success, negative upon failure -- */ --static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) -+static void txq_enable(struct tx_queue *txq) - { -- int i; -- -- for (i = 0; i < 6; i++) -- /* +2 is for the offset of the HW addr type */ -- dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; -- mv643xx_eth_update_mac_address(dev); -- return 0; -+ struct mv643xx_eth_private *mp = txq_to_mp(txq); -+ wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index); - } - --/* -- * mv643xx_eth_tx_timeout -- * -- * Called upon a timeout on transmitting a packet -- * -- * Input : pointer to ethernet interface network device structure. -- * Output : N/A -- */ --static void mv643xx_eth_tx_timeout(struct net_device *dev) -+static void txq_disable(struct tx_queue *txq) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- -- printk(KERN_INFO "%s: TX timeout ", dev->name); -+ struct mv643xx_eth_private *mp = txq_to_mp(txq); -+ u8 mask = 1 << txq->index; - -- /* Do the reset outside of interrupt context */ -- schedule_work(&mp->tx_timeout_task); -+ wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8); -+ while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask) -+ udelay(10); - } - --/* -- * mv643xx_eth_tx_timeout_task -- * -- * Actual routine to reset the adapter when a timeout on Tx has occurred -- */ --static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) -+static void __txq_maybe_wake(struct tx_queue *txq) - { -- struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, -- tx_timeout_task); -- struct net_device *dev = mp->dev; -+ struct mv643xx_eth_private *mp = txq_to_mp(txq); - -- if (!netif_running(dev)) -- return; -+ /* -+ * netif_{stop,wake}_queue() flow control only applies to -+ * the primary queue. -+ */ -+ BUG_ON(txq->index != mp->txq_primary); - -- netif_stop_queue(dev); -+ if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB) -+ netif_wake_queue(mp->dev); -+} - -- eth_port_reset(mp); -- eth_port_start(dev); - -- if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) -- netif_wake_queue(dev); --} -+/* rx ***********************************************************************/ -+static void txq_reclaim(struct tx_queue *txq, int force); - --/** -- * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors -- * -- * If force is non-zero, frees uncompleted descriptors as well -- */ --static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) -+static void rxq_refill(struct rx_queue *rxq) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- struct eth_tx_desc *desc; -- u32 cmd_sts; -- struct sk_buff *skb; -+ struct mv643xx_eth_private *mp = rxq_to_mp(rxq); - unsigned long flags; -- int tx_index; -- dma_addr_t addr; -- int count; -- int released = 0; -- -- while (mp->tx_desc_count > 0) { -- spin_lock_irqsave(&mp->lock, flags); -- -- /* tx_desc_count might have changed before acquiring the lock */ -- if (mp->tx_desc_count <= 0) { -- spin_unlock_irqrestore(&mp->lock, flags); -- return released; -- } -- -- tx_index = mp->tx_used_desc_q; -- desc = &mp->p_tx_desc_area[tx_index]; -- cmd_sts = desc->cmd_sts; - -- if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { -- spin_unlock_irqrestore(&mp->lock, flags); -- return released; -- } -+ spin_lock_irqsave(&mp->lock, flags); - -- mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; -- mp->tx_desc_count--; -+ while (rxq->rx_desc_count < rxq->rx_ring_size) { -+ int skb_size; -+ struct sk_buff *skb; -+ int unaligned; -+ int rx; - -- addr = desc->buf_ptr; -- count = desc->byte_cnt; -- skb = mp->tx_skb[tx_index]; -- if (skb) -- mp->tx_skb[tx_index] = NULL; -+ /* -+ * Reserve 2+14 bytes for an ethernet header (the -+ * hardware automatically prepends 2 bytes of dummy -+ * data to each received packet), 4 bytes for a VLAN -+ * header, and 4 bytes for the trailing FCS -- 24 -+ * bytes total. -+ */ -+ skb_size = mp->dev->mtu + 24; - -- if (cmd_sts & ETH_ERROR_SUMMARY) { -- printk("%s: Error in TX\n", dev->name); -- dev->stats.tx_errors++; -- } -+ skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1); -+ if (skb == NULL) -+ break; - -- spin_unlock_irqrestore(&mp->lock, flags); -+ unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); -+ if (unaligned) -+ skb_reserve(skb, dma_get_cache_alignment() - unaligned); - -- if (cmd_sts & ETH_TX_FIRST_DESC) -- dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); -- else -- dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); -+ rxq->rx_desc_count++; -+ rx = rxq->rx_used_desc; -+ rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size; -+ -+ rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data, -+ skb_size, DMA_FROM_DEVICE); -+ rxq->rx_desc_area[rx].buf_size = skb_size; -+ rxq->rx_skb[rx] = skb; -+ wmb(); -+ rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA | -+ RX_ENABLE_INTERRUPT; -+ wmb(); - -- if (skb) -- dev_kfree_skb_irq(skb); -+ /* -+ * The hardware automatically prepends 2 bytes of -+ * dummy data to each received packet, so that the -+ * IP header ends up 16-byte aligned. -+ */ -+ skb_reserve(skb, 2); -+ } - -- released = 1; -+ if (rxq->rx_desc_count != rxq->rx_ring_size) { -+ rxq->rx_oom.expires = jiffies + (HZ / 10); -+ add_timer(&rxq->rx_oom); - } - -- return released; -+ spin_unlock_irqrestore(&mp->lock, flags); - } - --static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) -+static inline void rxq_refill_timer_wrapper(unsigned long data) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- -- if (mv643xx_eth_free_tx_descs(dev, 0) && -- mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) -- netif_wake_queue(dev); -+ rxq_refill((struct rx_queue *)data); - } - --static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) -+static int rxq_process(struct rx_queue *rxq, int budget) - { -- mv643xx_eth_free_tx_descs(dev, 1); --} -+ struct mv643xx_eth_private *mp = rxq_to_mp(rxq); -+ struct net_device_stats *stats = &mp->dev->stats; -+ int rx; - --/* -- * mv643xx_eth_receive -- * -- * This function is forward packets that are received from the port's -- * queues toward kernel core or FastRoute them to another interface. -- * -- * Input : dev - a pointer to the required interface -- * max - maximum number to receive (0 means unlimted) -- * -- * Output : number of served packets -- */ --static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -- struct net_device_stats *stats = &dev->stats; -- unsigned int received_packets = 0; -- struct sk_buff *skb; -- struct pkt_info pkt_info; -- -- while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { -- dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, -- DMA_FROM_DEVICE); -- mp->rx_desc_count--; -- received_packets++; -+ rx = 0; -+ while (rx < budget) { -+ struct rx_desc *rx_desc; -+ unsigned int cmd_sts; -+ struct sk_buff *skb; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&mp->lock, flags); -+ -+ rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; -+ -+ cmd_sts = rx_desc->cmd_sts; -+ if (cmd_sts & BUFFER_OWNED_BY_DMA) { -+ spin_unlock_irqrestore(&mp->lock, flags); -+ break; -+ } -+ rmb(); -+ -+ skb = rxq->rx_skb[rxq->rx_curr_desc]; -+ rxq->rx_skb[rxq->rx_curr_desc] = NULL; -+ -+ rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size; -+ -+ spin_unlock_irqrestore(&mp->lock, flags); -+ -+ dma_unmap_single(NULL, rx_desc->buf_ptr + 2, -+ mp->dev->mtu + 24, DMA_FROM_DEVICE); -+ rxq->rx_desc_count--; -+ rx++; - - /* - * Update statistics. -- * Note byte count includes 4 byte CRC count -+ * -+ * Note that the descriptor byte count includes 2 dummy -+ * bytes automatically inserted by the hardware at the -+ * start of the packet (which we don't count), and a 4 -+ * byte CRC at the end of the packet (which we do count). - */ - stats->rx_packets++; -- stats->rx_bytes += pkt_info.byte_cnt; -- skb = pkt_info.return_info; -+ stats->rx_bytes += rx_desc->byte_cnt - 2; -+ - /* -- * In case received a packet without first / last bits on OR -- * the error summary bit is on, the packets needs to be dropeed. -+ * In case we received a packet without first / last bits -+ * on, or the error summary bit is set, the packet needs -+ * to be dropped. - */ -- if (((pkt_info.cmd_sts -- & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != -- (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) -- || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { -+ if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != -+ (RX_FIRST_DESC | RX_LAST_DESC)) -+ || (cmd_sts & ERROR_SUMMARY)) { - stats->rx_dropped++; -- if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | -- ETH_RX_LAST_DESC)) != -- (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { -+ -+ if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != -+ (RX_FIRST_DESC | RX_LAST_DESC)) { - if (net_ratelimit()) -- printk(KERN_ERR -- "%s: Received packet spread " -- "on multiple descriptors\n", -- dev->name); -+ dev_printk(KERN_ERR, &mp->dev->dev, -+ "received packet spanning " -+ "multiple descriptors\n"); - } -- if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) -+ -+ if (cmd_sts & ERROR_SUMMARY) - stats->rx_errors++; - - dev_kfree_skb_irq(skb); -@@ -975,668 +576,120 @@ - * The -4 is for the CRC in the trailer of the - * received packet - */ -- skb_put(skb, pkt_info.byte_cnt - 4); -+ skb_put(skb, rx_desc->byte_cnt - 2 - 4); - -- if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { -+ if (cmd_sts & LAYER_4_CHECKSUM_OK) { - skb->ip_summed = CHECKSUM_UNNECESSARY; - skb->csum = htons( -- (pkt_info.cmd_sts & 0x0007fff8) >> 3); -+ (cmd_sts & 0x0007fff8) >> 3); - } -- skb->protocol = eth_type_trans(skb, dev); --#ifdef MV643XX_NAPI -+ skb->protocol = eth_type_trans(skb, mp->dev); -+#ifdef MV643XX_ETH_NAPI - netif_receive_skb(skb); - #else - netif_rx(skb); - #endif - } -- dev->last_rx = jiffies; -+ -+ mp->dev->last_rx = jiffies; - } -- mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ - -- return received_packets; -+ rxq_refill(rxq); -+ -+ return rx; - } - --/* Set the mv643xx port configuration register for the speed/duplex mode. */ --static void mv643xx_eth_update_pscr(struct net_device *dev, -- struct ethtool_cmd *ecmd) -+#ifdef MV643XX_ETH_NAPI -+static int mv643xx_eth_poll(struct napi_struct *napi, int budget) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- int port_num = mp->port_num; -- u32 o_pscr, n_pscr; -- unsigned int queues; -+ struct mv643xx_eth_private *mp; -+ int rx; -+ int i; - -- o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); -- n_pscr = o_pscr; -+ mp = container_of(napi, struct mv643xx_eth_private, napi); - -- /* clear speed, duplex and rx buffer size fields */ -- n_pscr &= ~(SET_MII_SPEED_TO_100 | -- SET_GMII_SPEED_TO_1000 | -- SET_FULL_DUPLEX_MODE | -- MAX_RX_PACKET_MASK); -- -- if (ecmd->duplex == DUPLEX_FULL) -- n_pscr |= SET_FULL_DUPLEX_MODE; -- -- if (ecmd->speed == SPEED_1000) -- n_pscr |= SET_GMII_SPEED_TO_1000 | -- MAX_RX_PACKET_9700BYTE; -- else { -- if (ecmd->speed == SPEED_100) -- n_pscr |= SET_MII_SPEED_TO_100; -- n_pscr |= MAX_RX_PACKET_1522BYTE; -- } -- -- if (n_pscr != o_pscr) { -- if ((o_pscr & SERIAL_PORT_ENABLE) == 0) -- wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); -- else { -- queues = mv643xx_eth_port_disable_tx(mp); -+#ifdef MV643XX_ETH_TX_FAST_REFILL -+ if (++mp->tx_clean_threshold > 5) { -+ mp->tx_clean_threshold = 0; -+ for (i = 0; i < 8; i++) -+ if (mp->txq_mask & (1 << i)) -+ txq_reclaim(mp->txq + i, 0); -+ } -+#endif - -- o_pscr &= ~SERIAL_PORT_ENABLE; -- wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr); -- wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); -- wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); -- if (queues) -- mv643xx_eth_port_enable_tx(mp, queues); -- } -+ rx = 0; -+ for (i = 7; rx < budget && i >= 0; i--) -+ if (mp->rxq_mask & (1 << i)) -+ rx += rxq_process(mp->rxq + i, budget - rx); -+ -+ if (rx < budget) { -+ netif_rx_complete(mp->dev, napi); -+ wrl(mp, INT_CAUSE(mp->port_num), 0); -+ wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); -+ wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); - } -+ -+ return rx; - } -+#endif - --/* -- * mv643xx_eth_int_handler -- * -- * Main interrupt handler for the gigbit ethernet ports -- * -- * Input : irq - irq number (not used) -- * dev_id - a pointer to the required interface's data structure -- * regs - not used -- * Output : N/A -- */ - --static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) -+/* tx ***********************************************************************/ -+static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) - { -- struct net_device *dev = (struct net_device *)dev_id; -- struct mv643xx_private *mp = netdev_priv(dev); -- u32 eth_int_cause, eth_int_cause_ext = 0; -- unsigned int port_num = mp->port_num; -- -- /* Read interrupt cause registers */ -- eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) & -- ETH_INT_UNMASK_ALL; -- if (eth_int_cause & ETH_INT_CAUSE_EXT) { -- eth_int_cause_ext = rdl(mp, -- INTERRUPT_CAUSE_EXTEND_REG(port_num)) & -- ETH_INT_UNMASK_ALL_EXT; -- wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), -- ~eth_int_cause_ext); -- } -- -- /* PHY status changed */ -- if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) { -- struct ethtool_cmd cmd; -+ int frag; - -- if (mii_link_ok(&mp->mii)) { -- mii_ethtool_gset(&mp->mii, &cmd); -- mv643xx_eth_update_pscr(dev, &cmd); -- mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); -- if (!netif_carrier_ok(dev)) { -- netif_carrier_on(dev); -- if (mp->tx_ring_size - mp->tx_desc_count >= -- MAX_DESCS_PER_SKB) -- netif_wake_queue(dev); -- } -- } else if (netif_carrier_ok(dev)) { -- netif_stop_queue(dev); -- netif_carrier_off(dev); -- } -+ for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { -+ skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; -+ if (fragp->size <= 8 && fragp->page_offset & 7) -+ return 1; - } - --#ifdef MV643XX_NAPI -- if (eth_int_cause & ETH_INT_CAUSE_RX) { -- /* schedule the NAPI poll routine to maintain port */ -- wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); -+ return 0; -+} - -- /* wait for previous write to complete */ -- rdl(mp, INTERRUPT_MASK_REG(port_num)); -+static int txq_alloc_desc_index(struct tx_queue *txq) -+{ -+ int tx_desc_curr; - -- netif_rx_schedule(dev, &mp->napi); -- } --#else -- if (eth_int_cause & ETH_INT_CAUSE_RX) -- mv643xx_eth_receive_queue(dev, INT_MAX); --#endif -- if (eth_int_cause_ext & ETH_INT_CAUSE_TX) -- mv643xx_eth_free_completed_tx_descs(dev); -+ BUG_ON(txq->tx_desc_count >= txq->tx_ring_size); - -- /* -- * If no real interrupt occured, exit. -- * This can happen when using gigE interrupt coalescing mechanism. -- */ -- if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) -- return IRQ_NONE; -+ tx_desc_curr = txq->tx_curr_desc; -+ txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size; - -- return IRQ_HANDLED; --} -- --#ifdef MV643XX_COAL -- --/* -- * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path -- * -- * DESCRIPTION: -- * This routine sets the RX coalescing interrupt mechanism parameter. -- * This parameter is a timeout counter, that counts in 64 t_clk -- * chunks ; that when timeout event occurs a maskable interrupt -- * occurs. -- * The parameter is calculated using the tClk of the MV-643xx chip -- * , and the required delay of the interrupt in usec. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet port -- * unsigned int delay Delay in usec -- * -- * OUTPUT: -- * Interrupt coalescing mechanism value is set in MV-643xx chip. -- * -- * RETURN: -- * The interrupt coalescing value set in the gigE port. -- * -- */ --static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp, -- unsigned int delay) --{ -- unsigned int port_num = mp->port_num; -- unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; -- -- /* Set RX Coalescing mechanism */ -- wrl(mp, SDMA_CONFIG_REG(port_num), -- ((coal & 0x3fff) << 8) | -- (rdl(mp, SDMA_CONFIG_REG(port_num)) -- & 0xffc000ff)); -- -- return coal; --} --#endif -- --/* -- * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path -- * -- * DESCRIPTION: -- * This routine sets the TX coalescing interrupt mechanism parameter. -- * This parameter is a timeout counter, that counts in 64 t_clk -- * chunks ; that when timeout event occurs a maskable interrupt -- * occurs. -- * The parameter is calculated using the t_cLK frequency of the -- * MV-643xx chip and the required delay in the interrupt in uSec -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet port -- * unsigned int delay Delay in uSeconds -- * -- * OUTPUT: -- * Interrupt coalescing mechanism value is set in MV-643xx chip. -- * -- * RETURN: -- * The interrupt coalescing value set in the gigE port. -- * -- */ --static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp, -- unsigned int delay) --{ -- unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; -- -- /* Set TX Coalescing mechanism */ -- wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4); -- -- return coal; --} -- --/* -- * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. -- * -- * DESCRIPTION: -- * This function prepares a Rx chained list of descriptors and packet -- * buffers in a form of a ring. The routine must be called after port -- * initialization routine and before port start routine. -- * The Ethernet SDMA engine uses CPU bus addresses to access the various -- * devices in the system (i.e. DRAM). This function uses the ethernet -- * struct 'virtual to physical' routine (set by the user) to set the ring -- * with physical addresses. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port Control srtuct. -- * -- * OUTPUT: -- * The routine updates the Ethernet port control struct with information -- * regarding the Rx descriptors and buffers. -- * -- * RETURN: -- * None. -- */ --static void ether_init_rx_desc_ring(struct mv643xx_private *mp) --{ -- volatile struct eth_rx_desc *p_rx_desc; -- int rx_desc_num = mp->rx_ring_size; -- int i; -- -- /* initialize the next_desc_ptr links in the Rx descriptors ring */ -- p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; -- for (i = 0; i < rx_desc_num; i++) { -- p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + -- ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); -- } -- -- /* Save Rx desc pointer to driver struct. */ -- mp->rx_curr_desc_q = 0; -- mp->rx_used_desc_q = 0; -- -- mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); --} -- --/* -- * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. -- * -- * DESCRIPTION: -- * This function prepares a Tx chained list of descriptors and packet -- * buffers in a form of a ring. The routine must be called after port -- * initialization routine and before port start routine. -- * The Ethernet SDMA engine uses CPU bus addresses to access the various -- * devices in the system (i.e. DRAM). This function uses the ethernet -- * struct 'virtual to physical' routine (set by the user) to set the ring -- * with physical addresses. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port Control srtuct. -- * -- * OUTPUT: -- * The routine updates the Ethernet port control struct with information -- * regarding the Tx descriptors and buffers. -- * -- * RETURN: -- * None. -- */ --static void ether_init_tx_desc_ring(struct mv643xx_private *mp) --{ -- int tx_desc_num = mp->tx_ring_size; -- struct eth_tx_desc *p_tx_desc; -- int i; -- -- /* Initialize the next_desc_ptr links in the Tx descriptors ring */ -- p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; -- for (i = 0; i < tx_desc_num; i++) { -- p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + -- ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); -- } -- -- mp->tx_curr_desc_q = 0; -- mp->tx_used_desc_q = 0; -- -- mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); --} -- --static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -- int err; -- -- spin_lock_irq(&mp->lock); -- err = mii_ethtool_sset(&mp->mii, cmd); -- spin_unlock_irq(&mp->lock); -- -- return err; --} -- --static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -- int err; -- -- spin_lock_irq(&mp->lock); -- err = mii_ethtool_gset(&mp->mii, cmd); -- spin_unlock_irq(&mp->lock); -- -- /* The PHY may support 1000baseT_Half, but the mv643xx does not */ -- cmd->supported &= ~SUPPORTED_1000baseT_Half; -- cmd->advertising &= ~ADVERTISED_1000baseT_Half; -- -- return err; --} -- --/* -- * mv643xx_eth_open -- * -- * This function is called when openning the network device. The function -- * should initialize all the hardware, initialize cyclic Rx/Tx -- * descriptors chain and buffers and allocate an IRQ to the network -- * device. -- * -- * Input : a pointer to the network device structure -- * -- * Output : zero of success , nonzero if fails. -- */ -- --static int mv643xx_eth_open(struct net_device *dev) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -- unsigned int port_num = mp->port_num; -- unsigned int size; -- int err; -- -- /* Clear any pending ethernet port interrupts */ -- wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0); -- wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); -- /* wait for previous write to complete */ -- rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num)); -- -- err = request_irq(dev->irq, mv643xx_eth_int_handler, -- IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); -- if (err) { -- printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name); -- return -EAGAIN; -- } -- -- eth_port_init(mp); -- -- memset(&mp->timeout, 0, sizeof(struct timer_list)); -- mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; -- mp->timeout.data = (unsigned long)dev; -- -- /* Allocate RX and TX skb rings */ -- mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, -- GFP_KERNEL); -- if (!mp->rx_skb) { -- printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); -- err = -ENOMEM; -- goto out_free_irq; -- } -- mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, -- GFP_KERNEL); -- if (!mp->tx_skb) { -- printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); -- err = -ENOMEM; -- goto out_free_rx_skb; -- } -- -- /* Allocate TX ring */ -- mp->tx_desc_count = 0; -- size = mp->tx_ring_size * sizeof(struct eth_tx_desc); -- mp->tx_desc_area_size = size; -- -- if (mp->tx_sram_size) { -- mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, -- mp->tx_sram_size); -- mp->tx_desc_dma = mp->tx_sram_addr; -- } else -- mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, -- &mp->tx_desc_dma, -- GFP_KERNEL); -- -- if (!mp->p_tx_desc_area) { -- printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", -- dev->name, size); -- err = -ENOMEM; -- goto out_free_tx_skb; -- } -- BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ -- memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); -- -- ether_init_tx_desc_ring(mp); -- -- /* Allocate RX ring */ -- mp->rx_desc_count = 0; -- size = mp->rx_ring_size * sizeof(struct eth_rx_desc); -- mp->rx_desc_area_size = size; -- -- if (mp->rx_sram_size) { -- mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, -- mp->rx_sram_size); -- mp->rx_desc_dma = mp->rx_sram_addr; -- } else -- mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, -- &mp->rx_desc_dma, -- GFP_KERNEL); -- -- if (!mp->p_rx_desc_area) { -- printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", -- dev->name, size); -- printk(KERN_ERR "%s: Freeing previously allocated TX queues...", -- dev->name); -- if (mp->rx_sram_size) -- iounmap(mp->p_tx_desc_area); -- else -- dma_free_coherent(NULL, mp->tx_desc_area_size, -- mp->p_tx_desc_area, mp->tx_desc_dma); -- err = -ENOMEM; -- goto out_free_tx_skb; -- } -- memset((void *)mp->p_rx_desc_area, 0, size); -- -- ether_init_rx_desc_ring(mp); -- -- mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ -- --#ifdef MV643XX_NAPI -- napi_enable(&mp->napi); --#endif -- -- eth_port_start(dev); -- -- /* Interrupt Coalescing */ -- --#ifdef MV643XX_COAL -- mp->rx_int_coal = -- eth_port_set_rx_coal(mp, MV643XX_RX_COAL); --#endif -- -- mp->tx_int_coal = -- eth_port_set_tx_coal(mp, MV643XX_TX_COAL); -- -- /* Unmask phy and link status changes interrupts */ -- wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT); -- -- /* Unmask RX buffer and TX end interrupt */ -- wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); -- -- return 0; -- --out_free_tx_skb: -- kfree(mp->tx_skb); --out_free_rx_skb: -- kfree(mp->rx_skb); --out_free_irq: -- free_irq(dev->irq, dev); -- -- return err; --} -- --static void mv643xx_eth_free_tx_rings(struct net_device *dev) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -- -- /* Stop Tx Queues */ -- mv643xx_eth_port_disable_tx(mp); -- -- /* Free outstanding skb's on TX ring */ -- mv643xx_eth_free_all_tx_descs(dev); -- -- BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); -- -- /* Free TX ring */ -- if (mp->tx_sram_size) -- iounmap(mp->p_tx_desc_area); -- else -- dma_free_coherent(NULL, mp->tx_desc_area_size, -- mp->p_tx_desc_area, mp->tx_desc_dma); --} -- --static void mv643xx_eth_free_rx_rings(struct net_device *dev) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -- int curr; -- -- /* Stop RX Queues */ -- mv643xx_eth_port_disable_rx(mp); -- -- /* Free preallocated skb's on RX rings */ -- for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { -- if (mp->rx_skb[curr]) { -- dev_kfree_skb(mp->rx_skb[curr]); -- mp->rx_desc_count--; -- } -- } -- -- if (mp->rx_desc_count) -- printk(KERN_ERR -- "%s: Error in freeing Rx Ring. %d skb's still" -- " stuck in RX Ring - ignoring them\n", dev->name, -- mp->rx_desc_count); -- /* Free RX ring */ -- if (mp->rx_sram_size) -- iounmap(mp->p_rx_desc_area); -- else -- dma_free_coherent(NULL, mp->rx_desc_area_size, -- mp->p_rx_desc_area, mp->rx_desc_dma); --} -- --/* -- * mv643xx_eth_stop -- * -- * This function is used when closing the network device. -- * It updates the hardware, -- * release all memory that holds buffers and descriptors and release the IRQ. -- * Input : a pointer to the device structure -- * Output : zero if success , nonzero if fails -- */ -- --static int mv643xx_eth_stop(struct net_device *dev) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -- unsigned int port_num = mp->port_num; -- -- /* Mask all interrupts on ethernet port */ -- wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); -- /* wait for previous write to complete */ -- rdl(mp, INTERRUPT_MASK_REG(port_num)); -- --#ifdef MV643XX_NAPI -- napi_disable(&mp->napi); --#endif -- netif_carrier_off(dev); -- netif_stop_queue(dev); -- -- eth_port_reset(mp); -- -- mv643xx_eth_free_tx_rings(dev); -- mv643xx_eth_free_rx_rings(dev); -- -- free_irq(dev->irq, dev); -- -- return 0; --} -- --#ifdef MV643XX_NAPI --/* -- * mv643xx_poll -- * -- * This function is used in case of NAPI -- */ --static int mv643xx_poll(struct napi_struct *napi, int budget) --{ -- struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); -- struct net_device *dev = mp->dev; -- unsigned int port_num = mp->port_num; -- int work_done; -- --#ifdef MV643XX_TX_FAST_REFILL -- if (++mp->tx_clean_threshold > 5) { -- mv643xx_eth_free_completed_tx_descs(dev); -- mp->tx_clean_threshold = 0; -- } --#endif -- -- work_done = 0; -- if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) -- != (u32) mp->rx_used_desc_q) -- work_done = mv643xx_eth_receive_queue(dev, budget); -- -- if (work_done < budget) { -- netif_rx_complete(dev, napi); -- wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0); -- wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); -- wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); -- } -- -- return work_done; --} --#endif -- --/** -- * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments -- * -- * Hardware can't handle unaligned fragments smaller than 9 bytes. -- * This helper function detects that case. -- */ -- --static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) --{ -- unsigned int frag; -- skb_frag_t *fragp; -- -- for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { -- fragp = &skb_shinfo(skb)->frags[frag]; -- if (fragp->size <= 8 && fragp->page_offset & 0x7) -- return 1; -- } -- return 0; --} -- --/** -- * eth_alloc_tx_desc_index - return the index of the next available tx desc -- */ --static int eth_alloc_tx_desc_index(struct mv643xx_private *mp) --{ -- int tx_desc_curr; -- -- BUG_ON(mp->tx_desc_count >= mp->tx_ring_size); -- -- tx_desc_curr = mp->tx_curr_desc_q; -- mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; -- -- BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); -+ BUG_ON(txq->tx_curr_desc == txq->tx_used_desc); - - return tx_desc_curr; - } - --/** -- * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. -- * -- * Ensure the data for each fragment to be transmitted is mapped properly, -- * then fill in descriptors in the tx hw queue. -- */ --static void eth_tx_fill_frag_descs(struct mv643xx_private *mp, -- struct sk_buff *skb) -+static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) - { -+ int nr_frags = skb_shinfo(skb)->nr_frags; - int frag; -- int tx_index; -- struct eth_tx_desc *desc; -- -- for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { -- skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; - -- tx_index = eth_alloc_tx_desc_index(mp); -- desc = &mp->p_tx_desc_area[tx_index]; -+ for (frag = 0; frag < nr_frags; frag++) { -+ skb_frag_t *this_frag; -+ int tx_index; -+ struct tx_desc *desc; -+ -+ this_frag = &skb_shinfo(skb)->frags[frag]; -+ tx_index = txq_alloc_desc_index(txq); -+ desc = &txq->tx_desc_area[tx_index]; - -- desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA; -- /* Last Frag enables interrupt and frees the skb */ -- if (frag == (skb_shinfo(skb)->nr_frags - 1)) { -- desc->cmd_sts |= ETH_ZERO_PADDING | -- ETH_TX_LAST_DESC | -- ETH_TX_ENABLE_INTERRUPT; -- mp->tx_skb[tx_index] = skb; -- } else -- mp->tx_skb[tx_index] = NULL; -+ /* -+ * The last fragment will generate an interrupt -+ * which will free the skb on TX completion. -+ */ -+ if (frag == nr_frags - 1) { -+ desc->cmd_sts = BUFFER_OWNED_BY_DMA | -+ ZERO_PADDING | TX_LAST_DESC | -+ TX_ENABLE_INTERRUPT; -+ txq->tx_skb[tx_index] = skb; -+ } else { -+ desc->cmd_sts = BUFFER_OWNED_BY_DMA; -+ txq->tx_skb[tx_index] = NULL; -+ } - -- desc = &mp->p_tx_desc_area[tx_index]; - desc->l4i_chk = 0; - desc->byte_cnt = this_frag->size; - desc->buf_ptr = dma_map_page(NULL, this_frag->page, -@@ -1651,37 +704,28 @@ - return (__force __be16)sum; - } - --/** -- * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw -- * -- * Ensure the data for an skb to be transmitted is mapped properly, -- * then fill in descriptors in the tx hw queue and start the hardware. -- */ --static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, -- struct sk_buff *skb) -+static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) - { -+ int nr_frags = skb_shinfo(skb)->nr_frags; - int tx_index; -- struct eth_tx_desc *desc; -+ struct tx_desc *desc; - u32 cmd_sts; - int length; -- int nr_frags = skb_shinfo(skb)->nr_frags; - -- cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; -+ cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; - -- tx_index = eth_alloc_tx_desc_index(mp); -- desc = &mp->p_tx_desc_area[tx_index]; -+ tx_index = txq_alloc_desc_index(txq); -+ desc = &txq->tx_desc_area[tx_index]; - - if (nr_frags) { -- eth_tx_fill_frag_descs(mp, skb); -+ txq_submit_frag_skb(txq, skb); - - length = skb_headlen(skb); -- mp->tx_skb[tx_index] = NULL; -+ txq->tx_skb[tx_index] = NULL; - } else { -- cmd_sts |= ETH_ZERO_PADDING | -- ETH_TX_LAST_DESC | -- ETH_TX_ENABLE_INTERRUPT; -+ cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; - length = skb->len; -- mp->tx_skb[tx_index] = skb; -+ txq->tx_skb[tx_index] = skb; - } - - desc->byte_cnt = length; -@@ -1690,13 +734,13 @@ - if (skb->ip_summed == CHECKSUM_PARTIAL) { - BUG_ON(skb->protocol != htons(ETH_P_IP)); - -- cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | -- ETH_GEN_IP_V_4_CHECKSUM | -- ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; -+ cmd_sts |= GEN_TCP_UDP_CHECKSUM | -+ GEN_IP_V4_CHECKSUM | -+ ip_hdr(skb)->ihl << TX_IHL_SHIFT; - - switch (ip_hdr(skb)->protocol) { - case IPPROTO_UDP: -- cmd_sts |= ETH_UDP_FRAME; -+ cmd_sts |= UDP_FRAME; - desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); - break; - case IPPROTO_TCP: -@@ -1707,7 +751,7 @@ - } - } else { - /* Errata BTS #50, IHL must be 5 if no HW checksum */ -- cmd_sts |= 5 << ETH_TX_IHL_SHIFT; -+ cmd_sts |= 5 << TX_IHL_SHIFT; - desc->l4i_chk = 0; - } - -@@ -1717,1649 +761,1818 @@ - - /* ensure all descriptors are written before poking hardware */ - wmb(); -- mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); -+ txq_enable(txq); - -- mp->tx_desc_count += nr_frags + 1; -+ txq->tx_desc_count += nr_frags + 1; - } - --/** -- * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission -- * -- */ --static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) -+static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) - { -- struct mv643xx_private *mp = netdev_priv(dev); -+ struct mv643xx_eth_private *mp = netdev_priv(dev); - struct net_device_stats *stats = &dev->stats; -+ struct tx_queue *txq; - unsigned long flags; - -- BUG_ON(netif_queue_stopped(dev)); -- - if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { - stats->tx_dropped++; -- printk(KERN_DEBUG "%s: failed to linearize tiny " -- "unaligned fragment\n", dev->name); -+ dev_printk(KERN_DEBUG, &dev->dev, -+ "failed to linearize skb with tiny " -+ "unaligned fragment\n"); - return NETDEV_TX_BUSY; - } - - spin_lock_irqsave(&mp->lock, flags); - -- if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { -- printk(KERN_ERR "%s: transmit with queue full\n", dev->name); -- netif_stop_queue(dev); -+ txq = mp->txq + mp->txq_primary; -+ -+ if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) { - spin_unlock_irqrestore(&mp->lock, flags); -- return NETDEV_TX_BUSY; -+ if (txq->index == mp->txq_primary && net_ratelimit()) -+ dev_printk(KERN_ERR, &dev->dev, -+ "primary tx queue full?!\n"); -+ kfree_skb(skb); -+ return NETDEV_TX_OK; - } - -- eth_tx_submit_descs_for_skb(mp, skb); -+ txq_submit_skb(txq, skb); - stats->tx_bytes += skb->len; - stats->tx_packets++; - dev->trans_start = jiffies; - -- if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) -- netif_stop_queue(dev); -+ if (txq->index == mp->txq_primary) { -+ int entries_left; -+ -+ entries_left = txq->tx_ring_size - txq->tx_desc_count; -+ if (entries_left < MAX_DESCS_PER_SKB) -+ netif_stop_queue(dev); -+ } - - spin_unlock_irqrestore(&mp->lock, flags); - - return NETDEV_TX_OK; - } - --#ifdef CONFIG_NET_POLL_CONTROLLER --static void mv643xx_netpoll(struct net_device *netdev) -+ -+/* tx rate control **********************************************************/ -+/* -+ * Set total maximum TX rate (shared by all TX queues for this port) -+ * to 'rate' bits per second, with a maximum burst of 'burst' bytes. -+ */ -+static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) - { -- struct mv643xx_private *mp = netdev_priv(netdev); -- int port_num = mp->port_num; -+ int token_rate; -+ int mtu; -+ int bucket_size; -+ -+ token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); -+ if (token_rate > 1023) -+ token_rate = 1023; - -- wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); -- /* wait for previous write to complete */ -- rdl(mp, INTERRUPT_MASK_REG(port_num)); -+ mtu = (mp->dev->mtu + 255) >> 8; -+ if (mtu > 63) -+ mtu = 63; - -- mv643xx_eth_int_handler(netdev->irq, netdev); -+ bucket_size = (burst + 255) >> 8; -+ if (bucket_size > 65535) -+ bucket_size = 65535; - -- wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); -+ if (mp->shared->tx_bw_control_moved) { -+ wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate); -+ wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu); -+ wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size); -+ } else { -+ wrl(mp, TX_BW_RATE(mp->port_num), token_rate); -+ wrl(mp, TX_BW_MTU(mp->port_num), mtu); -+ wrl(mp, TX_BW_BURST(mp->port_num), bucket_size); -+ } - } --#endif - --static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, -- int speed, int duplex, -- struct ethtool_cmd *cmd) -+static void txq_set_rate(struct tx_queue *txq, int rate, int burst) - { -- struct mv643xx_private *mp = netdev_priv(dev); -+ struct mv643xx_eth_private *mp = txq_to_mp(txq); -+ int token_rate; -+ int bucket_size; - -- memset(cmd, 0, sizeof(*cmd)); -+ token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); -+ if (token_rate > 1023) -+ token_rate = 1023; - -- cmd->port = PORT_MII; -- cmd->transceiver = XCVR_INTERNAL; -- cmd->phy_address = phy_address; -+ bucket_size = (burst + 255) >> 8; -+ if (bucket_size > 65535) -+ bucket_size = 65535; - -- if (speed == 0) { -- cmd->autoneg = AUTONEG_ENABLE; -- /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ -- cmd->speed = SPEED_100; -- cmd->advertising = ADVERTISED_10baseT_Half | -- ADVERTISED_10baseT_Full | -- ADVERTISED_100baseT_Half | -- ADVERTISED_100baseT_Full; -- if (mp->mii.supports_gmii) -- cmd->advertising |= ADVERTISED_1000baseT_Full; -- } else { -- cmd->autoneg = AUTONEG_DISABLE; -- cmd->speed = speed; -- cmd->duplex = duplex; -- } -+ wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14); -+ wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index), -+ (bucket_size << 10) | token_rate); - } - --/*/ -- * mv643xx_eth_probe -- * -- * First function called after registering the network device. -- * It's purpose is to initialize the device as an ethernet device, -- * fill the ethernet device structure with pointers * to functions, -- * and set the MAC address of the interface -- * -- * Input : struct device * -- * Output : -ENOMEM if failed , 0 if success -- */ --static int mv643xx_eth_probe(struct platform_device *pdev) -+static void txq_set_fixed_prio_mode(struct tx_queue *txq) - { -- struct mv643xx_eth_platform_data *pd; -- int port_num; -- struct mv643xx_private *mp; -- struct net_device *dev; -- u8 *p; -- struct resource *res; -- int err; -- struct ethtool_cmd cmd; -- int duplex = DUPLEX_HALF; -- int speed = 0; /* default to auto-negotiation */ -- DECLARE_MAC_BUF(mac); -+ struct mv643xx_eth_private *mp = txq_to_mp(txq); -+ int off; -+ u32 val; - -- pd = pdev->dev.platform_data; -- if (pd == NULL) { -- printk(KERN_ERR "No mv643xx_eth_platform_data\n"); -- return -ENODEV; -- } -+ /* -+ * Turn on fixed priority mode. -+ */ -+ if (mp->shared->tx_bw_control_moved) -+ off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); -+ else -+ off = TXQ_FIX_PRIO_CONF(mp->port_num); - -- if (pd->shared == NULL) { -- printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); -- return -ENODEV; -- } -+ val = rdl(mp, off); -+ val |= 1 << txq->index; -+ wrl(mp, off, val); -+} - -- dev = alloc_etherdev(sizeof(struct mv643xx_private)); -- if (!dev) -- return -ENOMEM; -+static void txq_set_wrr(struct tx_queue *txq, int weight) -+{ -+ struct mv643xx_eth_private *mp = txq_to_mp(txq); -+ int off; -+ u32 val; - -- platform_set_drvdata(pdev, dev); -+ /* -+ * Turn off fixed priority mode. -+ */ -+ if (mp->shared->tx_bw_control_moved) -+ off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); -+ else -+ off = TXQ_FIX_PRIO_CONF(mp->port_num); - -- mp = netdev_priv(dev); -- mp->dev = dev; --#ifdef MV643XX_NAPI -- netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); --#endif -+ val = rdl(mp, off); -+ val &= ~(1 << txq->index); -+ wrl(mp, off, val); - -- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -- BUG_ON(!res); -- dev->irq = res->start; -+ /* -+ * Configure WRR weight for this queue. -+ */ -+ off = TXQ_BW_WRR_CONF(mp->port_num, txq->index); - -- dev->open = mv643xx_eth_open; -- dev->stop = mv643xx_eth_stop; -- dev->hard_start_xmit = mv643xx_eth_start_xmit; -- dev->set_mac_address = mv643xx_eth_set_mac_address; -- dev->set_multicast_list = mv643xx_eth_set_rx_mode; -+ val = rdl(mp, off); -+ val = (val & ~0xff) | (weight & 0xff); -+ wrl(mp, off, val); -+} - -- /* No need to Tx Timeout */ -- dev->tx_timeout = mv643xx_eth_tx_timeout; - --#ifdef CONFIG_NET_POLL_CONTROLLER -- dev->poll_controller = mv643xx_netpoll; --#endif -+/* mii management interface *************************************************/ -+#define SMI_BUSY 0x10000000 -+#define SMI_READ_VALID 0x08000000 -+#define SMI_OPCODE_READ 0x04000000 -+#define SMI_OPCODE_WRITE 0x00000000 - -- dev->watchdog_timeo = 2 * HZ; -- dev->base_addr = 0; -- dev->change_mtu = mv643xx_eth_change_mtu; -- dev->do_ioctl = mv643xx_eth_do_ioctl; -- SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); -+static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr, -+ unsigned int reg, unsigned int *value) -+{ -+ void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; -+ unsigned long flags; -+ int i; -+ -+ /* the SMI register is a shared resource */ -+ spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); -+ -+ /* wait for the SMI register to become available */ -+ for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { -+ if (i == 1000) { -+ printk("%s: PHY busy timeout\n", mp->dev->name); -+ goto out; -+ } -+ udelay(10); -+ } -+ -+ writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); -+ -+ /* now wait for the data to be valid */ -+ for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) { -+ if (i == 1000) { -+ printk("%s: PHY read timeout\n", mp->dev->name); -+ goto out; -+ } -+ udelay(10); -+ } -+ -+ *value = readl(smi_reg) & 0xffff; -+out: -+ spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); -+} -+ -+static void smi_reg_write(struct mv643xx_eth_private *mp, -+ unsigned int addr, -+ unsigned int reg, unsigned int value) -+{ -+ void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; -+ unsigned long flags; -+ int i; -+ -+ /* the SMI register is a shared resource */ -+ spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); -+ -+ /* wait for the SMI register to become available */ -+ for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { -+ if (i == 1000) { -+ printk("%s: PHY busy timeout\n", mp->dev->name); -+ goto out; -+ } -+ udelay(10); -+ } -+ -+ writel(SMI_OPCODE_WRITE | (reg << 21) | -+ (addr << 16) | (value & 0xffff), smi_reg); -+out: -+ spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); -+} -+ -+ -+/* mib counters *************************************************************/ -+static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) -+{ -+ return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); -+} -+ -+static void mib_counters_clear(struct mv643xx_eth_private *mp) -+{ -+ int i; -+ -+ for (i = 0; i < 0x80; i += 4) -+ mib_read(mp, i); -+} -+ -+static void mib_counters_update(struct mv643xx_eth_private *mp) -+{ -+ struct mib_counters *p = &mp->mib_counters; -+ -+ p->good_octets_received += mib_read(mp, 0x00); -+ p->good_octets_received += (u64)mib_read(mp, 0x04) << 32; -+ p->bad_octets_received += mib_read(mp, 0x08); -+ p->internal_mac_transmit_err += mib_read(mp, 0x0c); -+ p->good_frames_received += mib_read(mp, 0x10); -+ p->bad_frames_received += mib_read(mp, 0x14); -+ p->broadcast_frames_received += mib_read(mp, 0x18); -+ p->multicast_frames_received += mib_read(mp, 0x1c); -+ p->frames_64_octets += mib_read(mp, 0x20); -+ p->frames_65_to_127_octets += mib_read(mp, 0x24); -+ p->frames_128_to_255_octets += mib_read(mp, 0x28); -+ p->frames_256_to_511_octets += mib_read(mp, 0x2c); -+ p->frames_512_to_1023_octets += mib_read(mp, 0x30); -+ p->frames_1024_to_max_octets += mib_read(mp, 0x34); -+ p->good_octets_sent += mib_read(mp, 0x38); -+ p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32; -+ p->good_frames_sent += mib_read(mp, 0x40); -+ p->excessive_collision += mib_read(mp, 0x44); -+ p->multicast_frames_sent += mib_read(mp, 0x48); -+ p->broadcast_frames_sent += mib_read(mp, 0x4c); -+ p->unrec_mac_control_received += mib_read(mp, 0x50); -+ p->fc_sent += mib_read(mp, 0x54); -+ p->good_fc_received += mib_read(mp, 0x58); -+ p->bad_fc_received += mib_read(mp, 0x5c); -+ p->undersize_received += mib_read(mp, 0x60); -+ p->fragments_received += mib_read(mp, 0x64); -+ p->oversize_received += mib_read(mp, 0x68); -+ p->jabber_received += mib_read(mp, 0x6c); -+ p->mac_receive_error += mib_read(mp, 0x70); -+ p->bad_crc_event += mib_read(mp, 0x74); -+ p->collision += mib_read(mp, 0x78); -+ p->late_collision += mib_read(mp, 0x7c); -+} -+ -+ -+/* ethtool ******************************************************************/ -+struct mv643xx_eth_stats { -+ char stat_string[ETH_GSTRING_LEN]; -+ int sizeof_stat; -+ int netdev_off; -+ int mp_off; -+}; -+ -+#define SSTAT(m) \ -+ { #m, FIELD_SIZEOF(struct net_device_stats, m), \ -+ offsetof(struct net_device, stats.m), -1 } -+ -+#define MIBSTAT(m) \ -+ { #m, FIELD_SIZEOF(struct mib_counters, m), \ -+ -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } -+ -+static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { -+ SSTAT(rx_packets), -+ SSTAT(tx_packets), -+ SSTAT(rx_bytes), -+ SSTAT(tx_bytes), -+ SSTAT(rx_errors), -+ SSTAT(tx_errors), -+ SSTAT(rx_dropped), -+ SSTAT(tx_dropped), -+ MIBSTAT(good_octets_received), -+ MIBSTAT(bad_octets_received), -+ MIBSTAT(internal_mac_transmit_err), -+ MIBSTAT(good_frames_received), -+ MIBSTAT(bad_frames_received), -+ MIBSTAT(broadcast_frames_received), -+ MIBSTAT(multicast_frames_received), -+ MIBSTAT(frames_64_octets), -+ MIBSTAT(frames_65_to_127_octets), -+ MIBSTAT(frames_128_to_255_octets), -+ MIBSTAT(frames_256_to_511_octets), -+ MIBSTAT(frames_512_to_1023_octets), -+ MIBSTAT(frames_1024_to_max_octets), -+ MIBSTAT(good_octets_sent), -+ MIBSTAT(good_frames_sent), -+ MIBSTAT(excessive_collision), -+ MIBSTAT(multicast_frames_sent), -+ MIBSTAT(broadcast_frames_sent), -+ MIBSTAT(unrec_mac_control_received), -+ MIBSTAT(fc_sent), -+ MIBSTAT(good_fc_received), -+ MIBSTAT(bad_fc_received), -+ MIBSTAT(undersize_received), -+ MIBSTAT(fragments_received), -+ MIBSTAT(oversize_received), -+ MIBSTAT(jabber_received), -+ MIBSTAT(mac_receive_error), -+ MIBSTAT(bad_crc_event), -+ MIBSTAT(collision), -+ MIBSTAT(late_collision), -+}; -+ -+static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ int err; -+ -+ spin_lock_irq(&mp->lock); -+ err = mii_ethtool_gset(&mp->mii, cmd); -+ spin_unlock_irq(&mp->lock); - --#ifdef MV643XX_CHECKSUM_OFFLOAD_TX --#ifdef MAX_SKB_FRAGS - /* -- * Zero copy can only work if we use Discovery II memory. Else, we will -- * have to map the buffers to ISA memory which is only 16 MB -+ * The MAC does not support 1000baseT_Half. - */ -- dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; --#endif --#endif -+ cmd->supported &= ~SUPPORTED_1000baseT_Half; -+ cmd->advertising &= ~ADVERTISED_1000baseT_Half; - -- /* Configure the timeout task */ -- INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); -+ return err; -+} - -- spin_lock_init(&mp->lock); -+static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ cmd->supported = SUPPORTED_MII; -+ cmd->advertising = ADVERTISED_MII; -+ cmd->speed = SPEED_1000; -+ cmd->duplex = DUPLEX_FULL; -+ cmd->port = PORT_MII; -+ cmd->phy_address = 0; -+ cmd->transceiver = XCVR_INTERNAL; -+ cmd->autoneg = AUTONEG_DISABLE; -+ cmd->maxtxpkt = 1; -+ cmd->maxrxpkt = 1; - -- mp->shared = platform_get_drvdata(pd->shared); -- port_num = mp->port_num = pd->port_number; -+ return 0; -+} - -- if (mp->shared->win_protect) -- wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); -+static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ int err; - -- mp->shared_smi = mp->shared; -- if (pd->shared_smi != NULL) -- mp->shared_smi = platform_get_drvdata(pd->shared_smi); -- -- /* set default config values */ -- eth_port_uc_addr_get(mp, dev->dev_addr); -- mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; -- mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; -+ /* -+ * The MAC does not support 1000baseT_Half. -+ */ -+ cmd->advertising &= ~ADVERTISED_1000baseT_Half; - -- if (is_valid_ether_addr(pd->mac_addr)) -- memcpy(dev->dev_addr, pd->mac_addr, 6); -+ spin_lock_irq(&mp->lock); -+ err = mii_ethtool_sset(&mp->mii, cmd); -+ spin_unlock_irq(&mp->lock); - -- if (pd->phy_addr || pd->force_phy_addr) -- ethernet_phy_set(mp, pd->phy_addr); -+ return err; -+} - -- if (pd->rx_queue_size) -- mp->rx_ring_size = pd->rx_queue_size; -+static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ return -EINVAL; -+} - -- if (pd->tx_queue_size) -- mp->tx_ring_size = pd->tx_queue_size; -+static void mv643xx_eth_get_drvinfo(struct net_device *dev, -+ struct ethtool_drvinfo *drvinfo) -+{ -+ strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); -+ strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); -+ strncpy(drvinfo->fw_version, "N/A", 32); -+ strncpy(drvinfo->bus_info, "platform", 32); -+ drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); -+} -+ -+static int mv643xx_eth_nway_reset(struct net_device *dev) -+{ -+ struct mv643xx_eth_private *mp = netdev_priv(dev); - -- if (pd->tx_sram_size) { -- mp->tx_sram_size = pd->tx_sram_size; -- mp->tx_sram_addr = pd->tx_sram_addr; -+ return mii_nway_restart(&mp->mii); -+} -+ -+static int mv643xx_eth_nway_reset_phyless(struct net_device *dev) -+{ -+ return -EINVAL; -+} -+ -+static u32 mv643xx_eth_get_link(struct net_device *dev) -+{ -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ -+ return mii_link_ok(&mp->mii); -+} -+ -+static u32 mv643xx_eth_get_link_phyless(struct net_device *dev) -+{ -+ return 1; -+} -+ -+static void mv643xx_eth_get_strings(struct net_device *dev, -+ uint32_t stringset, uint8_t *data) -+{ -+ int i; -+ -+ if (stringset == ETH_SS_STATS) { -+ for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { -+ memcpy(data + i * ETH_GSTRING_LEN, -+ mv643xx_eth_stats[i].stat_string, -+ ETH_GSTRING_LEN); -+ } - } -+} -+ -+static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, -+ struct ethtool_stats *stats, -+ uint64_t *data) -+{ -+ struct mv643xx_eth_private *mp = dev->priv; -+ int i; -+ -+ mib_counters_update(mp); -+ -+ for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { -+ const struct mv643xx_eth_stats *stat; -+ void *p; -+ -+ stat = mv643xx_eth_stats + i; -+ -+ if (stat->netdev_off >= 0) -+ p = ((void *)mp->dev) + stat->netdev_off; -+ else -+ p = ((void *)mp) + stat->mp_off; - -- if (pd->rx_sram_size) { -- mp->rx_sram_size = pd->rx_sram_size; -- mp->rx_sram_addr = pd->rx_sram_addr; -+ data[i] = (stat->sizeof_stat == 8) ? -+ *(uint64_t *)p : *(uint32_t *)p; - } -+} - -- duplex = pd->duplex; -- speed = pd->speed; -+static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) -+{ -+ if (sset == ETH_SS_STATS) -+ return ARRAY_SIZE(mv643xx_eth_stats); - -- /* Hook up MII support for ethtool */ -- mp->mii.dev = dev; -- mp->mii.mdio_read = mv643xx_mdio_read; -- mp->mii.mdio_write = mv643xx_mdio_write; -- mp->mii.phy_id = ethernet_phy_get(mp); -- mp->mii.phy_id_mask = 0x3f; -- mp->mii.reg_num_mask = 0x1f; -+ return -EOPNOTSUPP; -+} - -- err = ethernet_phy_detect(mp); -- if (err) { -- pr_debug("%s: No PHY detected at addr %d\n", -- dev->name, ethernet_phy_get(mp)); -+static const struct ethtool_ops mv643xx_eth_ethtool_ops = { -+ .get_settings = mv643xx_eth_get_settings, -+ .set_settings = mv643xx_eth_set_settings, -+ .get_drvinfo = mv643xx_eth_get_drvinfo, -+ .nway_reset = mv643xx_eth_nway_reset, -+ .get_link = mv643xx_eth_get_link, -+ .set_sg = ethtool_op_set_sg, -+ .get_strings = mv643xx_eth_get_strings, -+ .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, -+ .get_sset_count = mv643xx_eth_get_sset_count, -+}; -+ -+static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = { -+ .get_settings = mv643xx_eth_get_settings_phyless, -+ .set_settings = mv643xx_eth_set_settings_phyless, -+ .get_drvinfo = mv643xx_eth_get_drvinfo, -+ .nway_reset = mv643xx_eth_nway_reset_phyless, -+ .get_link = mv643xx_eth_get_link_phyless, -+ .set_sg = ethtool_op_set_sg, -+ .get_strings = mv643xx_eth_get_strings, -+ .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, -+ .get_sset_count = mv643xx_eth_get_sset_count, -+}; -+ -+ -+/* address handling *********************************************************/ -+static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) -+{ -+ unsigned int mac_h; -+ unsigned int mac_l; -+ -+ mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num)); -+ mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num)); -+ -+ addr[0] = (mac_h >> 24) & 0xff; -+ addr[1] = (mac_h >> 16) & 0xff; -+ addr[2] = (mac_h >> 8) & 0xff; -+ addr[3] = mac_h & 0xff; -+ addr[4] = (mac_l >> 8) & 0xff; -+ addr[5] = mac_l & 0xff; -+} -+ -+static void init_mac_tables(struct mv643xx_eth_private *mp) -+{ -+ int i; -+ -+ for (i = 0; i < 0x100; i += 4) { -+ wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0); -+ wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0); -+ } -+ -+ for (i = 0; i < 0x10; i += 4) -+ wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0); -+} -+ -+static void set_filter_table_entry(struct mv643xx_eth_private *mp, -+ int table, unsigned char entry) -+{ -+ unsigned int table_reg; -+ -+ /* Set "accepts frame bit" at specified table entry */ -+ table_reg = rdl(mp, table + (entry & 0xfc)); -+ table_reg |= 0x01 << (8 * (entry & 3)); -+ wrl(mp, table + (entry & 0xfc), table_reg); -+} -+ -+static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) -+{ -+ unsigned int mac_h; -+ unsigned int mac_l; -+ int table; -+ -+ mac_l = (addr[4] << 8) | addr[5]; -+ mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; -+ -+ wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l); -+ wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h); -+ -+ table = UNICAST_TABLE(mp->port_num); -+ set_filter_table_entry(mp, table, addr[5] & 0x0f); -+} -+ -+static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) -+{ -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ -+ /* +2 is for the offset of the HW addr type */ -+ memcpy(dev->dev_addr, addr + 2, 6); -+ -+ init_mac_tables(mp); -+ uc_addr_set(mp, dev->dev_addr); -+ -+ return 0; -+} -+ -+static int addr_crc(unsigned char *addr) -+{ -+ int crc = 0; -+ int i; -+ -+ for (i = 0; i < 6; i++) { -+ int j; -+ -+ crc = (crc ^ addr[i]) << 8; -+ for (j = 7; j >= 0; j--) { -+ if (crc & (0x100 << j)) -+ crc ^= 0x107 << j; -+ } -+ } -+ -+ return crc; -+} -+ -+static void mv643xx_eth_set_rx_mode(struct net_device *dev) -+{ -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ u32 port_config; -+ struct dev_addr_list *addr; -+ int i; -+ -+ port_config = rdl(mp, PORT_CONFIG(mp->port_num)); -+ if (dev->flags & IFF_PROMISC) -+ port_config |= UNICAST_PROMISCUOUS_MODE; -+ else -+ port_config &= ~UNICAST_PROMISCUOUS_MODE; -+ wrl(mp, PORT_CONFIG(mp->port_num), port_config); -+ -+ if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { -+ int port_num = mp->port_num; -+ u32 accept = 0x01010101; -+ -+ for (i = 0; i < 0x100; i += 4) { -+ wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); -+ wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); -+ } -+ return; -+ } -+ -+ for (i = 0; i < 0x100; i += 4) { -+ wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0); -+ wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0); -+ } -+ -+ for (addr = dev->mc_list; addr != NULL; addr = addr->next) { -+ u8 *a = addr->da_addr; -+ int table; -+ -+ if (addr->da_addrlen != 6) -+ continue; -+ -+ if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { -+ table = SPECIAL_MCAST_TABLE(mp->port_num); -+ set_filter_table_entry(mp, table, a[5]); -+ } else { -+ int crc = addr_crc(a); -+ -+ table = OTHER_MCAST_TABLE(mp->port_num); -+ set_filter_table_entry(mp, table, crc); -+ } -+ } -+} -+ -+ -+/* rx/tx queue initialisation ***********************************************/ -+static int rxq_init(struct mv643xx_eth_private *mp, int index) -+{ -+ struct rx_queue *rxq = mp->rxq + index; -+ struct rx_desc *rx_desc; -+ int size; -+ int i; -+ -+ rxq->index = index; -+ -+ rxq->rx_ring_size = mp->default_rx_ring_size; -+ -+ rxq->rx_desc_count = 0; -+ rxq->rx_curr_desc = 0; -+ rxq->rx_used_desc = 0; -+ -+ size = rxq->rx_ring_size * sizeof(struct rx_desc); -+ -+ if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) { -+ rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, -+ mp->rx_desc_sram_size); -+ rxq->rx_desc_dma = mp->rx_desc_sram_addr; -+ } else { -+ rxq->rx_desc_area = dma_alloc_coherent(NULL, size, -+ &rxq->rx_desc_dma, -+ GFP_KERNEL); -+ } -+ -+ if (rxq->rx_desc_area == NULL) { -+ dev_printk(KERN_ERR, &mp->dev->dev, -+ "can't allocate rx ring (%d bytes)\n", size); - goto out; - } -+ memset(rxq->rx_desc_area, 0, size); - -- ethernet_phy_reset(mp); -- mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); -- mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); -- mv643xx_eth_update_pscr(dev, &cmd); -- mv643xx_set_settings(dev, &cmd); -+ rxq->rx_desc_area_size = size; -+ rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), -+ GFP_KERNEL); -+ if (rxq->rx_skb == NULL) { -+ dev_printk(KERN_ERR, &mp->dev->dev, -+ "can't allocate rx skb ring\n"); -+ goto out_free; -+ } - -- SET_NETDEV_DEV(dev, &pdev->dev); -- err = register_netdev(dev); -- if (err) -+ rx_desc = (struct rx_desc *)rxq->rx_desc_area; -+ for (i = 0; i < rxq->rx_ring_size; i++) { -+ int nexti = (i + 1) % rxq->rx_ring_size; -+ rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + -+ nexti * sizeof(struct rx_desc); -+ } -+ -+ init_timer(&rxq->rx_oom); -+ rxq->rx_oom.data = (unsigned long)rxq; -+ rxq->rx_oom.function = rxq_refill_timer_wrapper; -+ -+ return 0; -+ -+ -+out_free: -+ if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) -+ iounmap(rxq->rx_desc_area); -+ else -+ dma_free_coherent(NULL, size, -+ rxq->rx_desc_area, -+ rxq->rx_desc_dma); -+ -+out: -+ return -ENOMEM; -+} -+ -+static void rxq_deinit(struct rx_queue *rxq) -+{ -+ struct mv643xx_eth_private *mp = rxq_to_mp(rxq); -+ int i; -+ -+ rxq_disable(rxq); -+ -+ del_timer_sync(&rxq->rx_oom); -+ -+ for (i = 0; i < rxq->rx_ring_size; i++) { -+ if (rxq->rx_skb[i]) { -+ dev_kfree_skb(rxq->rx_skb[i]); -+ rxq->rx_desc_count--; -+ } -+ } -+ -+ if (rxq->rx_desc_count) { -+ dev_printk(KERN_ERR, &mp->dev->dev, -+ "error freeing rx ring -- %d skbs stuck\n", -+ rxq->rx_desc_count); -+ } -+ -+ if (rxq->index == mp->rxq_primary && -+ rxq->rx_desc_area_size <= mp->rx_desc_sram_size) -+ iounmap(rxq->rx_desc_area); -+ else -+ dma_free_coherent(NULL, rxq->rx_desc_area_size, -+ rxq->rx_desc_area, rxq->rx_desc_dma); -+ -+ kfree(rxq->rx_skb); -+} -+ -+static int txq_init(struct mv643xx_eth_private *mp, int index) -+{ -+ struct tx_queue *txq = mp->txq + index; -+ struct tx_desc *tx_desc; -+ int size; -+ int i; -+ -+ txq->index = index; -+ -+ txq->tx_ring_size = mp->default_tx_ring_size; -+ -+ txq->tx_desc_count = 0; -+ txq->tx_curr_desc = 0; -+ txq->tx_used_desc = 0; -+ -+ size = txq->tx_ring_size * sizeof(struct tx_desc); -+ -+ if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) { -+ txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, -+ mp->tx_desc_sram_size); -+ txq->tx_desc_dma = mp->tx_desc_sram_addr; -+ } else { -+ txq->tx_desc_area = dma_alloc_coherent(NULL, size, -+ &txq->tx_desc_dma, -+ GFP_KERNEL); -+ } -+ -+ if (txq->tx_desc_area == NULL) { -+ dev_printk(KERN_ERR, &mp->dev->dev, -+ "can't allocate tx ring (%d bytes)\n", size); - goto out; -+ } -+ memset(txq->tx_desc_area, 0, size); - -- p = dev->dev_addr; -- printk(KERN_NOTICE -- "%s: port %d with MAC address %s\n", -- dev->name, port_num, print_mac(mac, p)); -+ txq->tx_desc_area_size = size; -+ txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb), -+ GFP_KERNEL); -+ if (txq->tx_skb == NULL) { -+ dev_printk(KERN_ERR, &mp->dev->dev, -+ "can't allocate tx skb ring\n"); -+ goto out_free; -+ } - -- if (dev->features & NETIF_F_SG) -- printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); -+ tx_desc = (struct tx_desc *)txq->tx_desc_area; -+ for (i = 0; i < txq->tx_ring_size; i++) { -+ int nexti = (i + 1) % txq->tx_ring_size; -+ tx_desc[i].next_desc_ptr = txq->tx_desc_dma + -+ nexti * sizeof(struct tx_desc); -+ } - -- if (dev->features & NETIF_F_IP_CSUM) -- printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", -- dev->name); -+ return 0; -+ -+ -+out_free: -+ if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) -+ iounmap(txq->tx_desc_area); -+ else -+ dma_free_coherent(NULL, size, -+ txq->tx_desc_area, -+ txq->tx_desc_dma); -+ -+out: -+ return -ENOMEM; -+} -+ -+static void txq_reclaim(struct tx_queue *txq, int force) -+{ -+ struct mv643xx_eth_private *mp = txq_to_mp(txq); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&mp->lock, flags); -+ while (txq->tx_desc_count > 0) { -+ int tx_index; -+ struct tx_desc *desc; -+ u32 cmd_sts; -+ struct sk_buff *skb; -+ dma_addr_t addr; -+ int count; -+ -+ tx_index = txq->tx_used_desc; -+ desc = &txq->tx_desc_area[tx_index]; -+ cmd_sts = desc->cmd_sts; -+ -+ if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) -+ break; -+ -+ txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size; -+ txq->tx_desc_count--; -+ -+ addr = desc->buf_ptr; -+ count = desc->byte_cnt; -+ skb = txq->tx_skb[tx_index]; -+ txq->tx_skb[tx_index] = NULL; -+ -+ if (cmd_sts & ERROR_SUMMARY) { -+ dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); -+ mp->dev->stats.tx_errors++; -+ } -+ -+ /* -+ * Drop mp->lock while we free the skb. -+ */ -+ spin_unlock_irqrestore(&mp->lock, flags); - --#ifdef MV643XX_CHECKSUM_OFFLOAD_TX -- printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); -+ if (cmd_sts & TX_FIRST_DESC) -+ dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); -+ else -+ dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); -+ -+ if (skb) -+ dev_kfree_skb_irq(skb); -+ -+ spin_lock_irqsave(&mp->lock, flags); -+ } -+ spin_unlock_irqrestore(&mp->lock, flags); -+} -+ -+static void txq_deinit(struct tx_queue *txq) -+{ -+ struct mv643xx_eth_private *mp = txq_to_mp(txq); -+ -+ txq_disable(txq); -+ txq_reclaim(txq, 1); -+ -+ BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); -+ -+ if (txq->index == mp->txq_primary && -+ txq->tx_desc_area_size <= mp->tx_desc_sram_size) -+ iounmap(txq->tx_desc_area); -+ else -+ dma_free_coherent(NULL, txq->tx_desc_area_size, -+ txq->tx_desc_area, txq->tx_desc_dma); -+ -+ kfree(txq->tx_skb); -+} -+ -+ -+/* netdev ops and related ***************************************************/ -+static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) -+{ -+ u32 pscr_o; -+ u32 pscr_n; -+ -+ pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); -+ -+ /* clear speed, duplex and rx buffer size fields */ -+ pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 | -+ SET_GMII_SPEED_TO_1000 | -+ SET_FULL_DUPLEX_MODE | -+ MAX_RX_PACKET_MASK); -+ -+ if (speed == SPEED_1000) { -+ pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE; -+ } else { -+ if (speed == SPEED_100) -+ pscr_n |= SET_MII_SPEED_TO_100; -+ pscr_n |= MAX_RX_PACKET_1522BYTE; -+ } -+ -+ if (duplex == DUPLEX_FULL) -+ pscr_n |= SET_FULL_DUPLEX_MODE; -+ -+ if (pscr_n != pscr_o) { -+ if ((pscr_o & SERIAL_PORT_ENABLE) == 0) -+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); -+ else { -+ int i; -+ -+ for (i = 0; i < 8; i++) -+ if (mp->txq_mask & (1 << i)) -+ txq_disable(mp->txq + i); -+ -+ pscr_o &= ~SERIAL_PORT_ENABLE; -+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o); -+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); -+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); -+ -+ for (i = 0; i < 8; i++) -+ if (mp->txq_mask & (1 << i)) -+ txq_enable(mp->txq + i); -+ } -+ } -+} -+ -+static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) -+{ -+ struct net_device *dev = (struct net_device *)dev_id; -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ u32 int_cause; -+ u32 int_cause_ext; -+ u32 txq_active; -+ -+ int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & -+ (INT_TX_END | INT_RX | INT_EXT); -+ if (int_cause == 0) -+ return IRQ_NONE; -+ -+ int_cause_ext = 0; -+ if (int_cause & INT_EXT) { -+ int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num)) -+ & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); -+ wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext); -+ } -+ -+ if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) { -+ if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) { -+ int i; -+ -+ if (mp->phy_addr != -1) { -+ struct ethtool_cmd cmd; -+ -+ mii_ethtool_gset(&mp->mii, &cmd); -+ update_pscr(mp, cmd.speed, cmd.duplex); -+ } -+ -+ for (i = 0; i < 8; i++) -+ if (mp->txq_mask & (1 << i)) -+ txq_enable(mp->txq + i); -+ -+ if (!netif_carrier_ok(dev)) { -+ netif_carrier_on(dev); -+ __txq_maybe_wake(mp->txq + mp->txq_primary); -+ } -+ } else if (netif_carrier_ok(dev)) { -+ netif_stop_queue(dev); -+ netif_carrier_off(dev); -+ } -+ } -+ -+ /* -+ * RxBuffer or RxError set for any of the 8 queues? -+ */ -+#ifdef MV643XX_ETH_NAPI -+ if (int_cause & INT_RX) { -+ wrl(mp, INT_MASK(mp->port_num), 0x00000000); -+ rdl(mp, INT_MASK(mp->port_num)); -+ -+ netif_rx_schedule(dev, &mp->napi); -+ } -+#else -+ if (int_cause & INT_RX) { -+ int i; -+ -+ for (i = 7; i >= 0; i--) -+ if (mp->rxq_mask & (1 << i)) -+ rxq_process(mp->rxq + i, INT_MAX); -+ } - #endif - --#ifdef MV643XX_COAL -- printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", -- dev->name); --#endif -+ txq_active = rdl(mp, TXQ_COMMAND(mp->port_num)); -+ -+ /* -+ * TxBuffer or TxError set for any of the 8 queues? -+ */ -+ if (int_cause_ext & INT_EXT_TX) { -+ int i; -+ -+ for (i = 0; i < 8; i++) -+ if (mp->txq_mask & (1 << i)) -+ txq_reclaim(mp->txq + i, 0); -+ } -+ -+ /* -+ * Any TxEnd interrupts? -+ */ -+ if (int_cause & INT_TX_END) { -+ int i; -+ -+ wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END)); -+ for (i = 0; i < 8; i++) { -+ struct tx_queue *txq = mp->txq + i; -+ if (txq->tx_desc_count && !((txq_active >> i) & 1)) -+ txq_enable(txq); -+ } -+ } -+ -+ /* -+ * Enough space again in the primary TX queue for a full packet? -+ */ -+ if (int_cause_ext & INT_EXT_TX) { -+ struct tx_queue *txq = mp->txq + mp->txq_primary; -+ __txq_maybe_wake(txq); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static void phy_reset(struct mv643xx_eth_private *mp) -+{ -+ unsigned int data; -+ -+ smi_reg_read(mp, mp->phy_addr, 0, &data); -+ data |= 0x8000; -+ smi_reg_write(mp, mp->phy_addr, 0, data); -+ -+ do { -+ udelay(1); -+ smi_reg_read(mp, mp->phy_addr, 0, &data); -+ } while (data & 0x8000); -+} -+ -+static void port_start(struct mv643xx_eth_private *mp) -+{ -+ u32 pscr; -+ int i; -+ -+ /* -+ * Configure basic link parameters. -+ */ -+ pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); -+ pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); -+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); -+ pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | -+ DISABLE_AUTO_NEG_SPEED_GMII | -+ DISABLE_AUTO_NEG_FOR_DUPLEX | -+ DO_NOT_FORCE_LINK_FAIL | -+ SERIAL_PORT_CONTROL_RESERVED; -+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); -+ pscr |= SERIAL_PORT_ENABLE; -+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); -+ -+ wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); -+ -+ /* -+ * Perform PHY reset, if there is a PHY. -+ */ -+ if (mp->phy_addr != -1) { -+ struct ethtool_cmd cmd; -+ -+ mv643xx_eth_get_settings(mp->dev, &cmd); -+ phy_reset(mp); -+ mv643xx_eth_set_settings(mp->dev, &cmd); -+ } -+ -+ /* -+ * Configure TX path and queues. -+ */ -+ tx_set_rate(mp, 1000000000, 16777216); -+ for (i = 0; i < 8; i++) { -+ struct tx_queue *txq = mp->txq + i; -+ int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i); -+ u32 addr; -+ -+ if ((mp->txq_mask & (1 << i)) == 0) -+ continue; -+ -+ addr = (u32)txq->tx_desc_dma; -+ addr += txq->tx_curr_desc * sizeof(struct tx_desc); -+ wrl(mp, off, addr); -+ -+ txq_set_rate(txq, 1000000000, 16777216); -+ txq_set_fixed_prio_mode(txq); -+ } -+ -+ /* -+ * Add configured unicast address to address filter table. -+ */ -+ uc_addr_set(mp, mp->dev->dev_addr); -+ -+ /* -+ * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast -+ * frames to RX queue #0. -+ */ -+ wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000); - --#ifdef MV643XX_NAPI -- printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); --#endif -+ /* -+ * Treat BPDUs as normal multicasts, and disable partition mode. -+ */ -+ wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000); - -- if (mp->tx_sram_size > 0) -- printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); -+ /* -+ * Enable the receive queues. -+ */ -+ for (i = 0; i < 8; i++) { -+ struct rx_queue *rxq = mp->rxq + i; -+ int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i); -+ u32 addr; - -- return 0; -+ if ((mp->rxq_mask & (1 << i)) == 0) -+ continue; - --out: -- free_netdev(dev); -+ addr = (u32)rxq->rx_desc_dma; -+ addr += rxq->rx_curr_desc * sizeof(struct rx_desc); -+ wrl(mp, off, addr); - -- return err; -+ rxq_enable(rxq); -+ } - } - --static int mv643xx_eth_remove(struct platform_device *pdev) -+static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay) - { -- struct net_device *dev = platform_get_drvdata(pdev); -+ unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; -+ u32 val; - -- unregister_netdev(dev); -- flush_scheduled_work(); -+ val = rdl(mp, SDMA_CONFIG(mp->port_num)); -+ if (mp->shared->extended_rx_coal_limit) { -+ if (coal > 0xffff) -+ coal = 0xffff; -+ val &= ~0x023fff80; -+ val |= (coal & 0x8000) << 10; -+ val |= (coal & 0x7fff) << 7; -+ } else { -+ if (coal > 0x3fff) -+ coal = 0x3fff; -+ val &= ~0x003fff00; -+ val |= (coal & 0x3fff) << 8; -+ } -+ wrl(mp, SDMA_CONFIG(mp->port_num), val); -+} - -- free_netdev(dev); -- platform_set_drvdata(pdev, NULL); -- return 0; -+static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay) -+{ -+ unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; -+ -+ if (coal > 0x3fff) -+ coal = 0x3fff; -+ wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4); - } - --static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp, -- struct mbus_dram_target_info *dram) -+static int mv643xx_eth_open(struct net_device *dev) - { -- void __iomem *base = msp->eth_base; -- u32 win_enable; -- u32 win_protect; -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ int err; - int i; - -- for (i = 0; i < 6; i++) { -- writel(0, base + WINDOW_BASE(i)); -- writel(0, base + WINDOW_SIZE(i)); -- if (i < 4) -- writel(0, base + WINDOW_REMAP_HIGH(i)); -+ wrl(mp, INT_CAUSE(mp->port_num), 0); -+ wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); -+ rdl(mp, INT_CAUSE_EXT(mp->port_num)); -+ -+ err = request_irq(dev->irq, mv643xx_eth_irq, -+ IRQF_SHARED | IRQF_SAMPLE_RANDOM, -+ dev->name, dev); -+ if (err) { -+ dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); -+ return -EAGAIN; - } - -- win_enable = 0x3f; -- win_protect = 0; -- -- for (i = 0; i < dram->num_cs; i++) { -- struct mbus_dram_window *cs = dram->cs + i; -+ init_mac_tables(mp); - -- writel((cs->base & 0xffff0000) | -- (cs->mbus_attr << 8) | -- dram->mbus_dram_target_id, base + WINDOW_BASE(i)); -- writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); -+ for (i = 0; i < 8; i++) { -+ if ((mp->rxq_mask & (1 << i)) == 0) -+ continue; -+ -+ err = rxq_init(mp, i); -+ if (err) { -+ while (--i >= 0) -+ if (mp->rxq_mask & (1 << i)) -+ rxq_deinit(mp->rxq + i); -+ goto out; -+ } - -- win_enable &= ~(1 << i); -- win_protect |= 3 << (2 * i); -+ rxq_refill(mp->rxq + i); - } - -- writel(win_enable, base + WINDOW_BAR_ENABLE); -- msp->win_protect = win_protect; --} -- --static int mv643xx_eth_shared_probe(struct platform_device *pdev) --{ -- static int mv643xx_version_printed = 0; -- struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; -- struct mv643xx_shared_private *msp; -- struct resource *res; -- int ret; -- -- if (!mv643xx_version_printed++) -- printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); -- -- ret = -EINVAL; -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- if (res == NULL) -- goto out; -+ for (i = 0; i < 8; i++) { -+ if ((mp->txq_mask & (1 << i)) == 0) -+ continue; -+ -+ err = txq_init(mp, i); -+ if (err) { -+ while (--i >= 0) -+ if (mp->txq_mask & (1 << i)) -+ txq_deinit(mp->txq + i); -+ goto out_free; -+ } -+ } - -- ret = -ENOMEM; -- msp = kmalloc(sizeof(*msp), GFP_KERNEL); -- if (msp == NULL) -- goto out; -- memset(msp, 0, sizeof(*msp)); -+#ifdef MV643XX_ETH_NAPI -+ napi_enable(&mp->napi); -+#endif - -- msp->eth_base = ioremap(res->start, res->end - res->start + 1); -- if (msp->eth_base == NULL) -- goto out_free; -+ port_start(mp); - -- spin_lock_init(&msp->phy_lock); -- msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; -+ set_rx_coal(mp, 0); -+ set_tx_coal(mp, 0); - -- platform_set_drvdata(pdev, msp); -+ wrl(mp, INT_MASK_EXT(mp->port_num), -+ INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); - -- /* -- * (Re-)program MBUS remapping windows if we are asked to. -- */ -- if (pd != NULL && pd->dram != NULL) -- mv643xx_eth_conf_mbus_windows(msp, pd->dram); -+ wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); - - return 0; - -+ - out_free: -- kfree(msp); -+ for (i = 0; i < 8; i++) -+ if (mp->rxq_mask & (1 << i)) -+ rxq_deinit(mp->rxq + i); - out: -- return ret; -+ free_irq(dev->irq, dev); -+ -+ return err; - } - --static int mv643xx_eth_shared_remove(struct platform_device *pdev) -+static void port_reset(struct mv643xx_eth_private *mp) - { -- struct mv643xx_shared_private *msp = platform_get_drvdata(pdev); -+ unsigned int data; -+ int i; - -- iounmap(msp->eth_base); -- kfree(msp); -+ for (i = 0; i < 8; i++) { -+ if (mp->rxq_mask & (1 << i)) -+ rxq_disable(mp->rxq + i); -+ if (mp->txq_mask & (1 << i)) -+ txq_disable(mp->txq + i); -+ } -+ while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY)) -+ udelay(10); - -- return 0; -+ /* Reset the Enable bit in the Configuration Register */ -+ data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); -+ data &= ~(SERIAL_PORT_ENABLE | -+ DO_NOT_FORCE_LINK_FAIL | -+ FORCE_LINK_PASS); -+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data); - } - --static void mv643xx_eth_shutdown(struct platform_device *pdev) -+static int mv643xx_eth_stop(struct net_device *dev) - { -- struct net_device *dev = platform_get_drvdata(pdev); -- struct mv643xx_private *mp = netdev_priv(dev); -- unsigned int port_num = mp->port_num; -- -- /* Mask all interrupts on ethernet port */ -- wrl(mp, INTERRUPT_MASK_REG(port_num), 0); -- rdl(mp, INTERRUPT_MASK_REG(port_num)); -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ int i; - -- eth_port_reset(mp); --} -+ wrl(mp, INT_MASK(mp->port_num), 0x00000000); -+ rdl(mp, INT_MASK(mp->port_num)); - --static struct platform_driver mv643xx_eth_driver = { -- .probe = mv643xx_eth_probe, -- .remove = mv643xx_eth_remove, -- .shutdown = mv643xx_eth_shutdown, -- .driver = { -- .name = MV643XX_ETH_NAME, -- .owner = THIS_MODULE, -- }, --}; -+#ifdef MV643XX_ETH_NAPI -+ napi_disable(&mp->napi); -+#endif -+ netif_carrier_off(dev); -+ netif_stop_queue(dev); - --static struct platform_driver mv643xx_eth_shared_driver = { -- .probe = mv643xx_eth_shared_probe, -- .remove = mv643xx_eth_shared_remove, -- .driver = { -- .name = MV643XX_ETH_SHARED_NAME, -- .owner = THIS_MODULE, -- }, --}; -+ free_irq(dev->irq, dev); - --/* -- * mv643xx_init_module -- * -- * Registers the network drivers into the Linux kernel -- * -- * Input : N/A -- * -- * Output : N/A -- */ --static int __init mv643xx_init_module(void) --{ -- int rc; -+ port_reset(mp); -+ mib_counters_update(mp); - -- rc = platform_driver_register(&mv643xx_eth_shared_driver); -- if (!rc) { -- rc = platform_driver_register(&mv643xx_eth_driver); -- if (rc) -- platform_driver_unregister(&mv643xx_eth_shared_driver); -+ for (i = 0; i < 8; i++) { -+ if (mp->rxq_mask & (1 << i)) -+ rxq_deinit(mp->rxq + i); -+ if (mp->txq_mask & (1 << i)) -+ txq_deinit(mp->txq + i); - } -- return rc; --} - --/* -- * mv643xx_cleanup_module -- * -- * Registers the network drivers into the Linux kernel -- * -- * Input : N/A -- * -- * Output : N/A -- */ --static void __exit mv643xx_cleanup_module(void) --{ -- platform_driver_unregister(&mv643xx_eth_driver); -- platform_driver_unregister(&mv643xx_eth_shared_driver); -+ return 0; - } - --module_init(mv643xx_init_module); --module_exit(mv643xx_cleanup_module); -- --MODULE_LICENSE("GPL"); --MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" -- " and Dale Farnsworth"); --MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); --MODULE_ALIAS("platform:" MV643XX_ETH_NAME); --MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); -- --/* -- * The second part is the low level driver of the gigE ethernet ports. -- */ -- --/* -- * Marvell's Gigabit Ethernet controller low level driver -- * -- * DESCRIPTION: -- * This file introduce low level API to Marvell's Gigabit Ethernet -- * controller. This Gigabit Ethernet Controller driver API controls -- * 1) Operations (i.e. port init, start, reset etc'). -- * 2) Data flow (i.e. port send, receive etc'). -- * Each Gigabit Ethernet port is controlled via -- * struct mv643xx_private. -- * This struct includes user configuration information as well as -- * driver internal data needed for its operations. -- * -- * Supported Features: -- * - This low level driver is OS independent. Allocating memory for -- * the descriptor rings and buffers are not within the scope of -- * this driver. -- * - The user is free from Rx/Tx queue managing. -- * - This low level driver introduce functionality API that enable -- * the to operate Marvell's Gigabit Ethernet Controller in a -- * convenient way. -- * - Simple Gigabit Ethernet port operation API. -- * - Simple Gigabit Ethernet port data flow API. -- * - Data flow and operation API support per queue functionality. -- * - Support cached descriptors for better performance. -- * - Enable access to all four DRAM banks and internal SRAM memory -- * spaces. -- * - PHY access and control API. -- * - Port control register configuration API. -- * - Full control over Unicast and Multicast MAC configurations. -- * -- * Operation flow: -- * -- * Initialization phase -- * This phase complete the initialization of the the -- * mv643xx_private struct. -- * User information regarding port configuration has to be set -- * prior to calling the port initialization routine. -- * -- * In this phase any port Tx/Rx activity is halted, MIB counters -- * are cleared, PHY address is set according to user parameter and -- * access to DRAM and internal SRAM memory spaces. -- * -- * Driver ring initialization -- * Allocating memory for the descriptor rings and buffers is not -- * within the scope of this driver. Thus, the user is required to -- * allocate memory for the descriptors ring and buffers. Those -- * memory parameters are used by the Rx and Tx ring initialization -- * routines in order to curve the descriptor linked list in a form -- * of a ring. -- * Note: Pay special attention to alignment issues when using -- * cached descriptors/buffers. In this phase the driver store -- * information in the mv643xx_private struct regarding each queue -- * ring. -- * -- * Driver start -- * This phase prepares the Ethernet port for Rx and Tx activity. -- * It uses the information stored in the mv643xx_private struct to -- * initialize the various port registers. -- * -- * Data flow: -- * All packet references to/from the driver are done using -- * struct pkt_info. -- * This struct is a unified struct used with Rx and Tx operations. -- * This way the user is not required to be familiar with neither -- * Tx nor Rx descriptors structures. -- * The driver's descriptors rings are management by indexes. -- * Those indexes controls the ring resources and used to indicate -- * a SW resource error: -- * 'current' -- * This index points to the current available resource for use. For -- * example in Rx process this index will point to the descriptor -- * that will be passed to the user upon calling the receive -- * routine. In Tx process, this index will point to the descriptor -- * that will be assigned with the user packet info and transmitted. -- * 'used' -- * This index points to the descriptor that need to restore its -- * resources. For example in Rx process, using the Rx buffer return -- * API will attach the buffer returned in packet info to the -- * descriptor pointed by 'used'. In Tx process, using the Tx -- * descriptor return will merely return the user packet info with -- * the command status of the transmitted buffer pointed by the -- * 'used' index. Nevertheless, it is essential to use this routine -- * to update the 'used' index. -- * 'first' -- * This index supports Tx Scatter-Gather. It points to the first -- * descriptor of a packet assembled of multiple buffers. For -- * example when in middle of Such packet we have a Tx resource -- * error the 'curr' index get the value of 'first' to indicate -- * that the ring returned to its state before trying to transmit -- * this packet. -- * -- * Receive operation: -- * The eth_port_receive API set the packet information struct, -- * passed by the caller, with received information from the -- * 'current' SDMA descriptor. -- * It is the user responsibility to return this resource back -- * to the Rx descriptor ring to enable the reuse of this source. -- * Return Rx resource is done using the eth_rx_return_buff API. -- * -- * Prior to calling the initialization routine eth_port_init() the user -- * must set the following fields under mv643xx_private struct: -- * port_num User Ethernet port number. -- * port_config User port configuration value. -- * port_config_extend User port config extend value. -- * port_sdma_config User port SDMA config value. -- * port_serial_control User port serial control value. -- * -- * This driver data flow is done using the struct pkt_info which -- * is a unified struct for Rx and Tx operations: -- * -- * byte_cnt Tx/Rx descriptor buffer byte count. -- * l4i_chk CPU provided TCP Checksum. For Tx operation -- * only. -- * cmd_sts Tx/Rx descriptor command status. -- * buf_ptr Tx/Rx descriptor buffer pointer. -- * return_info Tx/Rx user resource return information. -- */ -- --/* Ethernet Port routines */ --static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, -- int table, unsigned char entry); -- --/* -- * eth_port_init - Initialize the Ethernet port driver -- * -- * DESCRIPTION: -- * This function prepares the ethernet port to start its activity: -- * 1) Completes the ethernet port driver struct initialization toward port -- * start routine. -- * 2) Resets the device to a quiescent state in case of warm reboot. -- * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -- * 4) Clean MAC tables. The reset status of those tables is unknown. -- * 5) Set PHY address. -- * Note: Call this routine prior to eth_port_start routine and after -- * setting user values in the user fields of Ethernet port control -- * struct. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet port control struct -- * -- * OUTPUT: -- * See description. -- * -- * RETURN: -- * None. -- */ --static void eth_port_init(struct mv643xx_private *mp) -+static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) - { -- mp->rx_resource_err = 0; -+ struct mv643xx_eth_private *mp = netdev_priv(dev); - -- eth_port_reset(mp); -+ if (mp->phy_addr != -1) -+ return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); - -- eth_port_init_mac_tables(mp); -+ return -EOPNOTSUPP; - } - --/* -- * eth_port_start - Start the Ethernet port activity. -- * -- * DESCRIPTION: -- * This routine prepares the Ethernet port for Rx and Tx activity: -- * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -- * has been initialized a descriptor's ring (using -- * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) -- * 2. Initialize and enable the Ethernet configuration port by writing to -- * the port's configuration and command registers. -- * 3. Initialize and enable the SDMA by writing to the SDMA's -- * configuration and command registers. After completing these steps, -- * the ethernet port SDMA can starts to perform Rx and Tx activities. -- * -- * Note: Each Rx and Tx queue descriptor's list must be initialized prior -- * to calling this function (use ether_init_tx_desc_ring for Tx queues -- * and ether_init_rx_desc_ring for Rx queues). -- * -- * INPUT: -- * dev - a pointer to the required interface -- * -- * OUTPUT: -- * Ethernet port is ready to receive and transmit. -- * -- * RETURN: -- * None. -- */ --static void eth_port_start(struct net_device *dev) -+static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- unsigned int port_num = mp->port_num; -- int tx_curr_desc, rx_curr_desc; -- u32 pscr; -- struct ethtool_cmd ethtool_cmd; -- -- /* Assignment of Tx CTRP of given queue */ -- tx_curr_desc = mp->tx_curr_desc_q; -- wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num), -- (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); -+ struct mv643xx_eth_private *mp = netdev_priv(dev); - -- /* Assignment of Rx CRDP of given queue */ -- rx_curr_desc = mp->rx_curr_desc_q; -- wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num), -- (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); -- -- /* Add the assigned Ethernet address to the port's address table */ -- eth_port_uc_addr_set(mp, dev->dev_addr); -+ if (new_mtu < 64 || new_mtu > 9500) -+ return -EINVAL; - -- /* Assign port configuration and command. */ -- wrl(mp, PORT_CONFIG_REG(port_num), -- PORT_CONFIG_DEFAULT_VALUE); -+ dev->mtu = new_mtu; -+ tx_set_rate(mp, 1000000000, 16777216); - -- wrl(mp, PORT_CONFIG_EXTEND_REG(port_num), -- PORT_CONFIG_EXTEND_DEFAULT_VALUE); -+ if (!netif_running(dev)) -+ return 0; - -- pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); -+ /* -+ * Stop and then re-open the interface. This will allocate RX -+ * skbs of the new MTU. -+ * There is a possible danger that the open will not succeed, -+ * due to memory being full. -+ */ -+ mv643xx_eth_stop(dev); -+ if (mv643xx_eth_open(dev)) { -+ dev_printk(KERN_ERR, &dev->dev, -+ "fatal error on re-opening device after " -+ "MTU change\n"); -+ } - -- pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); -- wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); -+ return 0; -+} - -- pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | -- DISABLE_AUTO_NEG_SPEED_GMII | -- DISABLE_AUTO_NEG_FOR_DUPLX | -- DO_NOT_FORCE_LINK_FAIL | -- SERIAL_PORT_CONTROL_RESERVED; -+static void tx_timeout_task(struct work_struct *ugly) -+{ -+ struct mv643xx_eth_private *mp; - -- wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); -+ mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); -+ if (netif_running(mp->dev)) { -+ netif_stop_queue(mp->dev); - -- pscr |= SERIAL_PORT_ENABLE; -- wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); -+ port_reset(mp); -+ port_start(mp); - -- /* Assign port SDMA configuration */ -- wrl(mp, SDMA_CONFIG_REG(port_num), -- PORT_SDMA_CONFIG_DEFAULT_VALUE); -- -- /* Enable port Rx. */ -- mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED); -- -- /* Disable port bandwidth limits by clearing MTU register */ -- wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0); -- -- /* save phy settings across reset */ -- mv643xx_get_settings(dev, ðtool_cmd); -- ethernet_phy_reset(mp); -- mv643xx_set_settings(dev, ðtool_cmd); -+ __txq_maybe_wake(mp->txq + mp->txq_primary); -+ } - } - --/* -- * eth_port_uc_addr_set - Write a MAC address into the port's hw registers -- */ --static void eth_port_uc_addr_set(struct mv643xx_private *mp, -- unsigned char *p_addr) -+static void mv643xx_eth_tx_timeout(struct net_device *dev) - { -- unsigned int port_num = mp->port_num; -- unsigned int mac_h; -- unsigned int mac_l; -- int table; -+ struct mv643xx_eth_private *mp = netdev_priv(dev); - -- mac_l = (p_addr[4] << 8) | (p_addr[5]); -- mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | -- (p_addr[3] << 0); -- -- wrl(mp, MAC_ADDR_LOW(port_num), mac_l); -- wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); -- -- /* Accept frames with this address */ -- table = DA_FILTER_UNICAST_TABLE_BASE(port_num); -- eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f); -+ dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); -+ -+ schedule_work(&mp->tx_timeout_task); - } - --/* -- * eth_port_uc_addr_get - Read the MAC address from the port's hw registers -- */ --static void eth_port_uc_addr_get(struct mv643xx_private *mp, -- unsigned char *p_addr) -+#ifdef CONFIG_NET_POLL_CONTROLLER -+static void mv643xx_eth_netpoll(struct net_device *dev) - { -- unsigned int port_num = mp->port_num; -- unsigned int mac_h; -- unsigned int mac_l; -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ -+ wrl(mp, INT_MASK(mp->port_num), 0x00000000); -+ rdl(mp, INT_MASK(mp->port_num)); - -- mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); -- mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); -+ mv643xx_eth_irq(dev->irq, dev); - -- p_addr[0] = (mac_h >> 24) & 0xff; -- p_addr[1] = (mac_h >> 16) & 0xff; -- p_addr[2] = (mac_h >> 8) & 0xff; -- p_addr[3] = mac_h & 0xff; -- p_addr[4] = (mac_l >> 8) & 0xff; -- p_addr[5] = mac_l & 0xff; -+ wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT); - } -+#endif - --/* -- * The entries in each table are indexed by a hash of a packet's MAC -- * address. One bit in each entry determines whether the packet is -- * accepted. There are 4 entries (each 8 bits wide) in each register -- * of the table. The bits in each entry are defined as follows: -- * 0 Accept=1, Drop=0 -- * 3-1 Queue (ETH_Q0=0) -- * 7-4 Reserved = 0; -- */ --static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, -- int table, unsigned char entry) -+static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg) - { -- unsigned int table_reg; -- unsigned int tbl_offset; -- unsigned int reg_offset; -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ int val; - -- tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ -- reg_offset = entry % 4; /* Entry offset within the register */ -+ smi_reg_read(mp, addr, reg, &val); - -- /* Set "accepts frame bit" at specified table entry */ -- table_reg = rdl(mp, table + tbl_offset); -- table_reg |= 0x01 << (8 * reg_offset); -- wrl(mp, table + tbl_offset, table_reg); -+ return val; - } - --/* -- * eth_port_mc_addr - Multicast address settings. -- * -- * The MV device supports multicast using two tables: -- * 1) Special Multicast Table for MAC addresses of the form -- * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). -- * The MAC DA[7:0] bits are used as a pointer to the Special Multicast -- * Table entries in the DA-Filter table. -- * 2) Other Multicast Table for multicast of another type. A CRC-8bit -- * is used as an index to the Other Multicast Table entries in the -- * DA-Filter table. This function calculates the CRC-8bit value. -- * In either case, eth_port_set_filter_table_entry() is then called -- * to set to set the actual table entry. -- */ --static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr) -+static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val) - { -- unsigned int port_num = mp->port_num; -- unsigned int mac_h; -- unsigned int mac_l; -- unsigned char crc_result = 0; -- int table; -- int mac_array[48]; -- int crc[8]; -- int i; -+ struct mv643xx_eth_private *mp = netdev_priv(dev); -+ smi_reg_write(mp, addr, reg, val); -+} - -- if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && -- (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { -- table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num); -- eth_port_set_filter_table_entry(mp, table, p_addr[5]); -- return; -- } - -- /* Calculate CRC-8 out of the given address */ -- mac_h = (p_addr[0] << 8) | (p_addr[1]); -- mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | -- (p_addr[4] << 8) | (p_addr[5] << 0); -- -- for (i = 0; i < 32; i++) -- mac_array[i] = (mac_l >> i) & 0x1; -- for (i = 32; i < 48; i++) -- mac_array[i] = (mac_h >> (i - 32)) & 0x1; -- -- crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ -- mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ -- mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ -- mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ -- mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; -- -- crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ -- mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ -- mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ -- mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ -- mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ -- mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ -- mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; -- -- crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ -- mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ -- mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ -- mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ -- mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ -- mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; -- -- crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ -- mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ -- mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ -- mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ -- mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ -- mac_array[3] ^ mac_array[2] ^ mac_array[1]; -- -- crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ -- mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ -- mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ -- mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ -- mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ -- mac_array[3] ^ mac_array[2]; -- -- crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ -- mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ -- mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ -- mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ -- mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ -- mac_array[4] ^ mac_array[3]; -- -- crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ -- mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ -- mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ -- mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ -- mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ -- mac_array[4]; -- -- crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ -- mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ -- mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ -- mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ -- mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; -+/* platform glue ************************************************************/ -+static void -+mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, -+ struct mbus_dram_target_info *dram) -+{ -+ void __iomem *base = msp->base; -+ u32 win_enable; -+ u32 win_protect; -+ int i; - -- for (i = 0; i < 8; i++) -- crc_result = crc_result | (crc[i] << i); -+ for (i = 0; i < 6; i++) { -+ writel(0, base + WINDOW_BASE(i)); -+ writel(0, base + WINDOW_SIZE(i)); -+ if (i < 4) -+ writel(0, base + WINDOW_REMAP_HIGH(i)); -+ } - -- table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num); -- eth_port_set_filter_table_entry(mp, table, crc_result); --} -+ win_enable = 0x3f; -+ win_protect = 0; - --/* -- * Set the entire multicast list based on dev->mc_list. -- */ --static void eth_port_set_multicast_list(struct net_device *dev) --{ -+ for (i = 0; i < dram->num_cs; i++) { -+ struct mbus_dram_window *cs = dram->cs + i; - -- struct dev_mc_list *mc_list; -- int i; -- int table_index; -- struct mv643xx_private *mp = netdev_priv(dev); -- unsigned int eth_port_num = mp->port_num; -- -- /* If the device is in promiscuous mode or in all multicast mode, -- * we will fully populate both multicast tables with accept. -- * This is guaranteed to yield a match on all multicast addresses... -- */ -- if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { -- for (table_index = 0; table_index <= 0xFC; table_index += 4) { -- /* Set all entries in DA filter special multicast -- * table (Ex_dFSMT) -- * Set for ETH_Q0 for now -- * Bits -- * 0 Accept=1, Drop=0 -- * 3-1 Queue ETH_Q0=0 -- * 7-4 Reserved = 0; -- */ -- wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); -+ writel((cs->base & 0xffff0000) | -+ (cs->mbus_attr << 8) | -+ dram->mbus_dram_target_id, base + WINDOW_BASE(i)); -+ writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); - -- /* Set all entries in DA filter other multicast -- * table (Ex_dFOMT) -- * Set for ETH_Q0 for now -- * Bits -- * 0 Accept=1, Drop=0 -- * 3-1 Queue ETH_Q0=0 -- * 7-4 Reserved = 0; -- */ -- wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); -- } -- return; -+ win_enable &= ~(1 << i); -+ win_protect |= 3 << (2 * i); - } - -- /* We will clear out multicast tables every time we get the list. -- * Then add the entire new list... -- */ -- for (table_index = 0; table_index <= 0xFC; table_index += 4) { -- /* Clear DA filter special multicast table (Ex_dFSMT) */ -- wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE -- (eth_port_num) + table_index, 0); -- -- /* Clear DA filter other multicast table (Ex_dFOMT) */ -- wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE -- (eth_port_num) + table_index, 0); -- } -- -- /* Get pointer to net_device multicast list and add each one... */ -- for (i = 0, mc_list = dev->mc_list; -- (i < 256) && (mc_list != NULL) && (i < dev->mc_count); -- i++, mc_list = mc_list->next) -- if (mc_list->dmi_addrlen == 6) -- eth_port_mc_addr(mp, mc_list->dmi_addr); -+ writel(win_enable, base + WINDOW_BAR_ENABLE); -+ msp->win_protect = win_protect; - } - --/* -- * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -- * -- * DESCRIPTION: -- * Go through all the DA filter tables (Unicast, Special Multicast & -- * Other Multicast) and set each entry to 0. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port. -- * -- * OUTPUT: -- * Multicast and Unicast packets are rejected. -- * -- * RETURN: -- * None. -- */ --static void eth_port_init_mac_tables(struct mv643xx_private *mp) -+static void infer_hw_params(struct mv643xx_eth_shared_private *msp) - { -- unsigned int port_num = mp->port_num; -- int table_index; -+ /* -+ * Check whether we have a 14-bit coal limit field in bits -+ * [21:8], or a 16-bit coal limit in bits [25,21:7] of the -+ * SDMA config register. -+ */ -+ writel(0x02000000, msp->base + SDMA_CONFIG(0)); -+ if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000) -+ msp->extended_rx_coal_limit = 1; -+ else -+ msp->extended_rx_coal_limit = 0; - -- /* Clear DA filter unicast table (Ex_dFUT) */ -- for (table_index = 0; table_index <= 0xC; table_index += 4) -- wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) + -- table_index, 0); -- -- for (table_index = 0; table_index <= 0xFC; table_index += 4) { -- /* Clear DA filter special multicast table (Ex_dFSMT) */ -- wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) + -- table_index, 0); -- /* Clear DA filter other multicast table (Ex_dFOMT) */ -- wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) + -- table_index, 0); -- } -+ /* -+ * Check whether the TX rate control registers are in the -+ * old or the new place. -+ */ -+ writel(1, msp->base + TX_BW_MTU_MOVED(0)); -+ if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) -+ msp->tx_bw_control_moved = 1; -+ else -+ msp->tx_bw_control_moved = 0; - } - --/* -- * eth_clear_mib_counters - Clear all MIB counters -- * -- * DESCRIPTION: -- * This function clears all MIB counters of a specific ethernet port. -- * A read from the MIB counter will reset the counter. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port. -- * -- * OUTPUT: -- * After reading all MIB counters, the counters resets. -- * -- * RETURN: -- * MIB counter value. -- * -- */ --static void eth_clear_mib_counters(struct mv643xx_private *mp) -+static int mv643xx_eth_shared_probe(struct platform_device *pdev) - { -- unsigned int port_num = mp->port_num; -- int i; -- -- /* Perform dummy reads from MIB counters */ -- for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; -- i += 4) -- rdl(mp, MIB_COUNTERS_BASE(port_num) + i); --} -+ static int mv643xx_eth_version_printed = 0; -+ struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; -+ struct mv643xx_eth_shared_private *msp; -+ struct resource *res; -+ int ret; - --static inline u32 read_mib(struct mv643xx_private *mp, int offset) --{ -- return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset); --} -+ if (!mv643xx_eth_version_printed++) -+ printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); - --static void eth_update_mib_counters(struct mv643xx_private *mp) --{ -- struct mv643xx_mib_counters *p = &mp->mib_counters; -- int offset; -+ ret = -EINVAL; -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (res == NULL) -+ goto out; - -- p->good_octets_received += -- read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); -- p->good_octets_received += -- (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; -+ ret = -ENOMEM; -+ msp = kmalloc(sizeof(*msp), GFP_KERNEL); -+ if (msp == NULL) -+ goto out; -+ memset(msp, 0, sizeof(*msp)); - -- for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; -- offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; -- offset += 4) -- *(u32 *)((char *)p + offset) += read_mib(mp, offset); -+ msp->base = ioremap(res->start, res->end - res->start + 1); -+ if (msp->base == NULL) -+ goto out_free; - -- p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); -- p->good_octets_sent += -- (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; -+ spin_lock_init(&msp->phy_lock); - -- for (offset = ETH_MIB_GOOD_FRAMES_SENT; -- offset <= ETH_MIB_LATE_COLLISION; -- offset += 4) -- *(u32 *)((char *)p + offset) += read_mib(mp, offset); --} -+ /* -+ * (Re-)program MBUS remapping windows if we are asked to. -+ */ -+ if (pd != NULL && pd->dram != NULL) -+ mv643xx_eth_conf_mbus_windows(msp, pd->dram); - --/* -- * ethernet_phy_detect - Detect whether a phy is present -- * -- * DESCRIPTION: -- * This function tests whether there is a PHY present on -- * the specified port. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port. -- * -- * OUTPUT: -- * None -- * -- * RETURN: -- * 0 on success -- * -ENODEV on failure -- * -- */ --static int ethernet_phy_detect(struct mv643xx_private *mp) --{ -- unsigned int phy_reg_data0; -- int auto_neg; -+ /* -+ * Detect hardware parameters. -+ */ -+ msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; -+ infer_hw_params(msp); - -- eth_port_read_smi_reg(mp, 0, &phy_reg_data0); -- auto_neg = phy_reg_data0 & 0x1000; -- phy_reg_data0 ^= 0x1000; /* invert auto_neg */ -- eth_port_write_smi_reg(mp, 0, phy_reg_data0); -- -- eth_port_read_smi_reg(mp, 0, &phy_reg_data0); -- if ((phy_reg_data0 & 0x1000) == auto_neg) -- return -ENODEV; /* change didn't take */ -+ platform_set_drvdata(pdev, msp); - -- phy_reg_data0 ^= 0x1000; -- eth_port_write_smi_reg(mp, 0, phy_reg_data0); - return 0; -+ -+out_free: -+ kfree(msp); -+out: -+ return ret; - } - --/* -- * ethernet_phy_get - Get the ethernet port PHY address. -- * -- * DESCRIPTION: -- * This routine returns the given ethernet port PHY address. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port. -- * -- * OUTPUT: -- * None. -- * -- * RETURN: -- * PHY address. -- * -- */ --static int ethernet_phy_get(struct mv643xx_private *mp) -+static int mv643xx_eth_shared_remove(struct platform_device *pdev) - { -- unsigned int reg_data; -+ struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); - -- reg_data = rdl(mp, PHY_ADDR_REG); -+ iounmap(msp->base); -+ kfree(msp); - -- return ((reg_data >> (5 * mp->port_num)) & 0x1f); -+ return 0; - } - --/* -- * ethernet_phy_set - Set the ethernet port PHY address. -- * -- * DESCRIPTION: -- * This routine sets the given ethernet port PHY address. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port. -- * int phy_addr PHY address. -- * -- * OUTPUT: -- * None. -- * -- * RETURN: -- * None. -- * -- */ --static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr) -+static struct platform_driver mv643xx_eth_shared_driver = { -+ .probe = mv643xx_eth_shared_probe, -+ .remove = mv643xx_eth_shared_remove, -+ .driver = { -+ .name = MV643XX_ETH_SHARED_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) - { -- u32 reg_data; - int addr_shift = 5 * mp->port_num; -+ u32 data; - -- reg_data = rdl(mp, PHY_ADDR_REG); -- reg_data &= ~(0x1f << addr_shift); -- reg_data |= (phy_addr & 0x1f) << addr_shift; -- wrl(mp, PHY_ADDR_REG, reg_data); -+ data = rdl(mp, PHY_ADDR); -+ data &= ~(0x1f << addr_shift); -+ data |= (phy_addr & 0x1f) << addr_shift; -+ wrl(mp, PHY_ADDR, data); - } - --/* -- * ethernet_phy_reset - Reset Ethernet port PHY. -- * -- * DESCRIPTION: -- * This routine utilizes the SMI interface to reset the ethernet port PHY. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port. -- * -- * OUTPUT: -- * The PHY is reset. -- * -- * RETURN: -- * None. -- * -- */ --static void ethernet_phy_reset(struct mv643xx_private *mp) -+static int phy_addr_get(struct mv643xx_eth_private *mp) - { -- unsigned int phy_reg_data; -+ unsigned int data; - -- /* Reset the PHY */ -- eth_port_read_smi_reg(mp, 0, &phy_reg_data); -- phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ -- eth_port_write_smi_reg(mp, 0, phy_reg_data); -+ data = rdl(mp, PHY_ADDR); - -- /* wait for PHY to come out of reset */ -- do { -- udelay(1); -- eth_port_read_smi_reg(mp, 0, &phy_reg_data); -- } while (phy_reg_data & 0x8000); -+ return (data >> (5 * mp->port_num)) & 0x1f; - } - --static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, -- unsigned int queues) -+static void set_params(struct mv643xx_eth_private *mp, -+ struct mv643xx_eth_platform_data *pd) - { -- wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues); --} -+ struct net_device *dev = mp->dev; - --static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp, -- unsigned int queues) --{ -- wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues); --} -+ if (is_valid_ether_addr(pd->mac_addr)) -+ memcpy(dev->dev_addr, pd->mac_addr, 6); -+ else -+ uc_addr_get(mp, dev->dev_addr); - --static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp) --{ -- unsigned int port_num = mp->port_num; -- u32 queues; -+ if (pd->phy_addr == -1) { -+ mp->shared_smi = NULL; -+ mp->phy_addr = -1; -+ } else { -+ mp->shared_smi = mp->shared; -+ if (pd->shared_smi != NULL) -+ mp->shared_smi = platform_get_drvdata(pd->shared_smi); -+ -+ if (pd->force_phy_addr || pd->phy_addr) { -+ mp->phy_addr = pd->phy_addr & 0x3f; -+ phy_addr_set(mp, mp->phy_addr); -+ } else { -+ mp->phy_addr = phy_addr_get(mp); -+ } -+ } - -- /* Stop Tx port activity. Check port Tx activity. */ -- queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF; -- if (queues) { -- /* Issue stop command for active queues only */ -- wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8)); -+ mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE; -+ if (pd->rx_queue_size) -+ mp->default_rx_ring_size = pd->rx_queue_size; -+ mp->rx_desc_sram_addr = pd->rx_sram_addr; -+ mp->rx_desc_sram_size = pd->rx_sram_size; - -- /* Wait for all Tx activity to terminate. */ -- /* Check port cause register that all Tx queues are stopped */ -- while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF) -- udelay(PHY_WAIT_MICRO_SECONDS); -+ if (pd->rx_queue_mask) -+ mp->rxq_mask = pd->rx_queue_mask; -+ else -+ mp->rxq_mask = 0x01; -+ mp->rxq_primary = fls(mp->rxq_mask) - 1; - -- /* Wait for Tx FIFO to empty */ -- while (rdl(mp, PORT_STATUS_REG(port_num)) & -- ETH_PORT_TX_FIFO_EMPTY) -- udelay(PHY_WAIT_MICRO_SECONDS); -- } -+ mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE; -+ if (pd->tx_queue_size) -+ mp->default_tx_ring_size = pd->tx_queue_size; -+ mp->tx_desc_sram_addr = pd->tx_sram_addr; -+ mp->tx_desc_sram_size = pd->tx_sram_size; - -- return queues; -+ if (pd->tx_queue_mask) -+ mp->txq_mask = pd->tx_queue_mask; -+ else -+ mp->txq_mask = 0x01; -+ mp->txq_primary = fls(mp->txq_mask) - 1; - } - --static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp) -+static int phy_detect(struct mv643xx_eth_private *mp) - { -- unsigned int port_num = mp->port_num; -- u32 queues; -+ unsigned int data; -+ unsigned int data2; - -- /* Stop Rx port activity. Check port Rx activity. */ -- queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF; -- if (queues) { -- /* Issue stop command for active queues only */ -- wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8)); -+ smi_reg_read(mp, mp->phy_addr, 0, &data); -+ smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000); - -- /* Wait for all Rx activity to terminate. */ -- /* Check port cause register that all Rx queues are stopped */ -- while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF) -- udelay(PHY_WAIT_MICRO_SECONDS); -- } -+ smi_reg_read(mp, mp->phy_addr, 0, &data2); -+ if (((data ^ data2) & 0x1000) == 0) -+ return -ENODEV; -+ -+ smi_reg_write(mp, mp->phy_addr, 0, data); - -- return queues; -+ return 0; - } - --/* -- * eth_port_reset - Reset Ethernet port -- * -- * DESCRIPTION: -- * This routine resets the chip by aborting any SDMA engine activity and -- * clearing the MIB counters. The Receiver and the Transmit unit are in -- * idle state after this command is performed and the port is disabled. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port. -- * -- * OUTPUT: -- * Channel activity is halted. -- * -- * RETURN: -- * None. -- * -- */ --static void eth_port_reset(struct mv643xx_private *mp) -+static int phy_init(struct mv643xx_eth_private *mp, -+ struct mv643xx_eth_platform_data *pd) - { -- unsigned int port_num = mp->port_num; -- unsigned int reg_data; -- -- mv643xx_eth_port_disable_tx(mp); -- mv643xx_eth_port_disable_rx(mp); -- -- /* Clear all MIB counters */ -- eth_clear_mib_counters(mp); -+ struct ethtool_cmd cmd; -+ int err; - -- /* Reset the Enable bit in the Configuration Register */ -- reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); -- reg_data &= ~(SERIAL_PORT_ENABLE | -- DO_NOT_FORCE_LINK_FAIL | -- FORCE_LINK_PASS); -- wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data); --} -+ err = phy_detect(mp); -+ if (err) { -+ dev_printk(KERN_INFO, &mp->dev->dev, -+ "no PHY detected at addr %d\n", mp->phy_addr); -+ return err; -+ } -+ phy_reset(mp); - -+ mp->mii.phy_id = mp->phy_addr; -+ mp->mii.phy_id_mask = 0x3f; -+ mp->mii.reg_num_mask = 0x1f; -+ mp->mii.dev = mp->dev; -+ mp->mii.mdio_read = mv643xx_eth_mdio_read; -+ mp->mii.mdio_write = mv643xx_eth_mdio_write; - --/* -- * eth_port_read_smi_reg - Read PHY registers -- * -- * DESCRIPTION: -- * This routine utilize the SMI interface to interact with the PHY in -- * order to perform PHY register read. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port. -- * unsigned int phy_reg PHY register address offset. -- * unsigned int *value Register value buffer. -- * -- * OUTPUT: -- * Write the value of a specified PHY register into given buffer. -- * -- * RETURN: -- * false if the PHY is busy or read data is not in valid state. -- * true otherwise. -- * -- */ --static void eth_port_read_smi_reg(struct mv643xx_private *mp, -- unsigned int phy_reg, unsigned int *value) --{ -- void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; -- int phy_addr = ethernet_phy_get(mp); -- unsigned long flags; -- int i; -+ mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); - -- /* the SMI register is a shared resource */ -- spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); -+ memset(&cmd, 0, sizeof(cmd)); - -- /* wait for the SMI register to become available */ -- for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { -- if (i == PHY_WAIT_ITERATIONS) { -- printk("%s: PHY busy timeout\n", mp->dev->name); -- goto out; -- } -- udelay(PHY_WAIT_MICRO_SECONDS); -+ cmd.port = PORT_MII; -+ cmd.transceiver = XCVR_INTERNAL; -+ cmd.phy_address = mp->phy_addr; -+ if (pd->speed == 0) { -+ cmd.autoneg = AUTONEG_ENABLE; -+ cmd.speed = SPEED_100; -+ cmd.advertising = ADVERTISED_10baseT_Half | -+ ADVERTISED_10baseT_Full | -+ ADVERTISED_100baseT_Half | -+ ADVERTISED_100baseT_Full; -+ if (mp->mii.supports_gmii) -+ cmd.advertising |= ADVERTISED_1000baseT_Full; -+ } else { -+ cmd.autoneg = AUTONEG_DISABLE; -+ cmd.speed = pd->speed; -+ cmd.duplex = pd->duplex; - } - -- writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ, -- smi_reg); -- -- /* now wait for the data to be valid */ -- for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) { -- if (i == PHY_WAIT_ITERATIONS) { -- printk("%s: PHY read timeout\n", mp->dev->name); -- goto out; -- } -- udelay(PHY_WAIT_MICRO_SECONDS); -- } -+ update_pscr(mp, cmd.speed, cmd.duplex); -+ mv643xx_eth_set_settings(mp->dev, &cmd); - -- *value = readl(smi_reg) & 0xffff; --out: -- spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); -+ return 0; - } - --/* -- * eth_port_write_smi_reg - Write to PHY registers -- * -- * DESCRIPTION: -- * This routine utilize the SMI interface to interact with the PHY in -- * order to perform writes to PHY registers. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port. -- * unsigned int phy_reg PHY register address offset. -- * unsigned int value Register value. -- * -- * OUTPUT: -- * Write the given value to the specified PHY register. -- * -- * RETURN: -- * false if the PHY is busy. -- * true otherwise. -- * -- */ --static void eth_port_write_smi_reg(struct mv643xx_private *mp, -- unsigned int phy_reg, unsigned int value) -+static int mv643xx_eth_probe(struct platform_device *pdev) - { -- void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; -- int phy_addr = ethernet_phy_get(mp); -- unsigned long flags; -- int i; -+ struct mv643xx_eth_platform_data *pd; -+ struct mv643xx_eth_private *mp; -+ struct net_device *dev; -+ struct resource *res; -+ DECLARE_MAC_BUF(mac); -+ int err; - -- /* the SMI register is a shared resource */ -- spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); -+ pd = pdev->dev.platform_data; -+ if (pd == NULL) { -+ dev_printk(KERN_ERR, &pdev->dev, -+ "no mv643xx_eth_platform_data\n"); -+ return -ENODEV; -+ } - -- /* wait for the SMI register to become available */ -- for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { -- if (i == PHY_WAIT_ITERATIONS) { -- printk("%s: PHY busy timeout\n", mp->dev->name); -- goto out; -- } -- udelay(PHY_WAIT_MICRO_SECONDS); -+ if (pd->shared == NULL) { -+ dev_printk(KERN_ERR, &pdev->dev, -+ "no mv643xx_eth_platform_data->shared\n"); -+ return -ENODEV; - } - -- writel((phy_addr << 16) | (phy_reg << 21) | -- ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg); --out: -- spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); --} -+ dev = alloc_etherdev(sizeof(struct mv643xx_eth_private)); -+ if (!dev) -+ return -ENOMEM; - --/* -- * Wrappers for MII support library. -- */ --static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -- int val; -+ mp = netdev_priv(dev); -+ platform_set_drvdata(pdev, mp); - -- eth_port_read_smi_reg(mp, location, &val); -- return val; --} -+ mp->shared = platform_get_drvdata(pd->shared); -+ mp->port_num = pd->port_number; - --static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -- eth_port_write_smi_reg(mp, location, val); --} -+ mp->dev = dev; -+#ifdef MV643XX_ETH_NAPI -+ netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64); -+#endif - --/* -- * eth_port_receive - Get received information from Rx ring. -- * -- * DESCRIPTION: -- * This routine returns the received data to the caller. There is no -- * data copying during routine operation. All information is returned -- * using pointer to packet information struct passed from the caller. -- * If the routine exhausts Rx ring resources then the resource error flag -- * is set. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port Control srtuct. -- * struct pkt_info *p_pkt_info User packet buffer. -- * -- * OUTPUT: -- * Rx ring current and used indexes are updated. -- * -- * RETURN: -- * ETH_ERROR in case the routine can not access Rx desc ring. -- * ETH_QUEUE_FULL if Rx ring resources are exhausted. -- * ETH_END_OF_JOB if there is no received data. -- * ETH_OK otherwise. -- */ --static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, -- struct pkt_info *p_pkt_info) --{ -- int rx_next_curr_desc, rx_curr_desc, rx_used_desc; -- volatile struct eth_rx_desc *p_rx_desc; -- unsigned int command_status; -- unsigned long flags; -+ set_params(mp, pd); - -- /* Do not process Rx ring in case of Rx ring resource error */ -- if (mp->rx_resource_err) -- return ETH_QUEUE_FULL; -+ spin_lock_init(&mp->lock); - -- spin_lock_irqsave(&mp->lock, flags); -+ mib_counters_clear(mp); -+ INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); - -- /* Get the Rx Desc ring 'curr and 'used' indexes */ -- rx_curr_desc = mp->rx_curr_desc_q; -- rx_used_desc = mp->rx_used_desc_q; -- -- p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; -- -- /* The following parameters are used to save readings from memory */ -- command_status = p_rx_desc->cmd_sts; -- rmb(); -+ if (mp->phy_addr != -1) { -+ err = phy_init(mp, pd); -+ if (err) -+ goto out; - -- /* Nothing to receive... */ -- if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -- spin_unlock_irqrestore(&mp->lock, flags); -- return ETH_END_OF_JOB; -+ SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); -+ } else { -+ SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless); - } - -- p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; -- p_pkt_info->cmd_sts = command_status; -- p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; -- p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; -- p_pkt_info->l4i_chk = p_rx_desc->buf_size; -- -- /* -- * Clean the return info field to indicate that the -- * packet has been moved to the upper layers -- */ -- mp->rx_skb[rx_curr_desc] = NULL; - -- /* Update current index in data structure */ -- rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; -- mp->rx_curr_desc_q = rx_next_curr_desc; -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ BUG_ON(!res); -+ dev->irq = res->start; - -- /* Rx descriptors exhausted. Set the Rx ring resource error flag */ -- if (rx_next_curr_desc == rx_used_desc) -- mp->rx_resource_err = 1; -+ dev->hard_start_xmit = mv643xx_eth_xmit; -+ dev->open = mv643xx_eth_open; -+ dev->stop = mv643xx_eth_stop; -+ dev->set_multicast_list = mv643xx_eth_set_rx_mode; -+ dev->set_mac_address = mv643xx_eth_set_mac_address; -+ dev->do_ioctl = mv643xx_eth_ioctl; -+ dev->change_mtu = mv643xx_eth_change_mtu; -+ dev->tx_timeout = mv643xx_eth_tx_timeout; -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ dev->poll_controller = mv643xx_eth_netpoll; -+#endif -+ dev->watchdog_timeo = 2 * HZ; -+ dev->base_addr = 0; - -- spin_unlock_irqrestore(&mp->lock, flags); -+#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX -+ /* -+ * Zero copy can only work if we use Discovery II memory. Else, we will -+ * have to map the buffers to ISA memory which is only 16 MB -+ */ -+ dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; -+#endif - -- return ETH_OK; --} -+ SET_NETDEV_DEV(dev, &pdev->dev); - --/* -- * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. -- * -- * DESCRIPTION: -- * This routine returns a Rx buffer back to the Rx ring. It retrieves the -- * next 'used' descriptor and attached the returned buffer to it. -- * In case the Rx ring was in "resource error" condition, where there are -- * no available Rx resources, the function resets the resource error flag. -- * -- * INPUT: -- * struct mv643xx_private *mp Ethernet Port Control srtuct. -- * struct pkt_info *p_pkt_info Information on returned buffer. -- * -- * OUTPUT: -- * New available Rx resource in Rx descriptor ring. -- * -- * RETURN: -- * ETH_ERROR in case the routine can not access Rx desc ring. -- * ETH_OK otherwise. -- */ --static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, -- struct pkt_info *p_pkt_info) --{ -- int used_rx_desc; /* Where to return Rx resource */ -- volatile struct eth_rx_desc *p_used_rx_desc; -- unsigned long flags; -+ if (mp->shared->win_protect) -+ wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); - -- spin_lock_irqsave(&mp->lock, flags); -+ err = register_netdev(dev); -+ if (err) -+ goto out; - -- /* Get 'used' Rx descriptor */ -- used_rx_desc = mp->rx_used_desc_q; -- p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; -+ dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n", -+ mp->port_num, print_mac(mac, dev->dev_addr)); - -- p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; -- p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; -- mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; -+ if (dev->features & NETIF_F_SG) -+ dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n"); - -- /* Flush the write pipe */ -+ if (dev->features & NETIF_F_IP_CSUM) -+ dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n"); - -- /* Return the descriptor to DMA ownership */ -- wmb(); -- p_used_rx_desc->cmd_sts = -- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; -- wmb(); -+#ifdef MV643XX_ETH_NAPI -+ dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n"); -+#endif - -- /* Move the used descriptor pointer to the next descriptor */ -- mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; -+ if (mp->tx_desc_sram_size > 0) -+ dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); - -- /* Any Rx return cancels the Rx resource error status */ -- mp->rx_resource_err = 0; -+ return 0; - -- spin_unlock_irqrestore(&mp->lock, flags); -+out: -+ free_netdev(dev); - -- return ETH_OK; -+ return err; - } - --/************* Begin ethtool support *************************/ -- --struct mv643xx_stats { -- char stat_string[ETH_GSTRING_LEN]; -- int sizeof_stat; -- int stat_offset; --}; -- --#define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \ -- offsetof(struct mv643xx_private, m) -- --static const struct mv643xx_stats mv643xx_gstrings_stats[] = { -- { "rx_packets", MV643XX_STAT(stats.rx_packets) }, -- { "tx_packets", MV643XX_STAT(stats.tx_packets) }, -- { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, -- { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, -- { "rx_errors", MV643XX_STAT(stats.rx_errors) }, -- { "tx_errors", MV643XX_STAT(stats.tx_errors) }, -- { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, -- { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, -- { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, -- { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, -- { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, -- { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, -- { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, -- { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, -- { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, -- { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, -- { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, -- { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, -- { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, -- { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, -- { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, -- { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, -- { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, -- { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, -- { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, -- { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, -- { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, -- { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, -- { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, -- { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, -- { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, -- { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, -- { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, -- { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, -- { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, -- { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, -- { "collision", MV643XX_STAT(mib_counters.collision) }, -- { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, --}; -+static int mv643xx_eth_remove(struct platform_device *pdev) -+{ -+ struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); - --#define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) -+ unregister_netdev(mp->dev); -+ flush_scheduled_work(); -+ free_netdev(mp->dev); - --static void mv643xx_get_drvinfo(struct net_device *netdev, -- struct ethtool_drvinfo *drvinfo) --{ -- strncpy(drvinfo->driver, mv643xx_driver_name, 32); -- strncpy(drvinfo->version, mv643xx_driver_version, 32); -- strncpy(drvinfo->fw_version, "N/A", 32); -- strncpy(drvinfo->bus_info, "mv643xx", 32); -- drvinfo->n_stats = MV643XX_STATS_LEN; --} -+ platform_set_drvdata(pdev, NULL); - --static int mv643xx_get_sset_count(struct net_device *netdev, int sset) --{ -- switch (sset) { -- case ETH_SS_STATS: -- return MV643XX_STATS_LEN; -- default: -- return -EOPNOTSUPP; -- } -+ return 0; - } - --static void mv643xx_get_ethtool_stats(struct net_device *netdev, -- struct ethtool_stats *stats, uint64_t *data) -+static void mv643xx_eth_shutdown(struct platform_device *pdev) - { -- struct mv643xx_private *mp = netdev->priv; -- int i; -+ struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); - -- eth_update_mib_counters(mp); -+ /* Mask all interrupts on ethernet port */ -+ wrl(mp, INT_MASK(mp->port_num), 0); -+ rdl(mp, INT_MASK(mp->port_num)); - -- for (i = 0; i < MV643XX_STATS_LEN; i++) { -- char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; -- data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == -- sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; -- } -+ if (netif_running(mp->dev)) -+ port_reset(mp); - } - --static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, -- uint8_t *data) --{ -- int i; -- -- switch(stringset) { -- case ETH_SS_STATS: -- for (i=0; i < MV643XX_STATS_LEN; i++) { -- memcpy(data + i * ETH_GSTRING_LEN, -- mv643xx_gstrings_stats[i].stat_string, -- ETH_GSTRING_LEN); -- } -- break; -- } --} -+static struct platform_driver mv643xx_eth_driver = { -+ .probe = mv643xx_eth_probe, -+ .remove = mv643xx_eth_remove, -+ .shutdown = mv643xx_eth_shutdown, -+ .driver = { -+ .name = MV643XX_ETH_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; - --static u32 mv643xx_eth_get_link(struct net_device *dev) -+static int __init mv643xx_eth_init_module(void) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- -- return mii_link_ok(&mp->mii); --} -+ int rc; - --static int mv643xx_eth_nway_restart(struct net_device *dev) --{ -- struct mv643xx_private *mp = netdev_priv(dev); -+ rc = platform_driver_register(&mv643xx_eth_shared_driver); -+ if (!rc) { -+ rc = platform_driver_register(&mv643xx_eth_driver); -+ if (rc) -+ platform_driver_unregister(&mv643xx_eth_shared_driver); -+ } - -- return mii_nway_restart(&mp->mii); -+ return rc; - } -+module_init(mv643xx_eth_init_module); - --static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+static void __exit mv643xx_eth_cleanup_module(void) - { -- struct mv643xx_private *mp = netdev_priv(dev); -- -- return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); -+ platform_driver_unregister(&mv643xx_eth_driver); -+ platform_driver_unregister(&mv643xx_eth_shared_driver); - } -+module_exit(mv643xx_eth_cleanup_module); - --static const struct ethtool_ops mv643xx_ethtool_ops = { -- .get_settings = mv643xx_get_settings, -- .set_settings = mv643xx_set_settings, -- .get_drvinfo = mv643xx_get_drvinfo, -- .get_link = mv643xx_eth_get_link, -- .set_sg = ethtool_op_set_sg, -- .get_sset_count = mv643xx_get_sset_count, -- .get_ethtool_stats = mv643xx_get_ethtool_stats, -- .get_strings = mv643xx_get_strings, -- .nway_reset = mv643xx_eth_nway_restart, --}; -- --/************* End ethtool support *************************/ -+MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " -+ "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); -+MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); -+MODULE_ALIAS("platform:" MV643XX_ETH_NAME); ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/debug-macro.S -@@ -0,0 +1,20 @@ -+/* -+ * include/asm-arm/arch-kirkwood/debug-macro.S -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#include -+ -+ .macro addruart,rx -+ mrc p15, 0, \rx, c1, c0 -+ tst \rx, #1 @ MMU enabled? -+ ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE -+ ldrne \rx, =KIRKWOOD_REGS_VIRT_BASE -+ orr \rx, \rx, #0x00012000 -+ .endm -+ -+#define UART_SHIFT 2 -+#include ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/dma.h -@@ -0,0 +1 @@ -+/* empty */ ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/entry-macro.S -@@ -0,0 +1,40 @@ -+/* -+ * include/asm-arm/arch-kirkwood/entry-macro.S -+ * -+ * Low-level IRQ helper macros for Marvell Kirkwood platforms -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+ -+ .macro disable_fiq -+ .endm -+ -+ .macro arch_ret_to_user, tmp1, tmp2 -+ .endm -+ -+ .macro get_irqnr_preamble, base, tmp -+ ldr \base, =IRQ_VIRT_BASE -+ .endm -+ -+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -+ @ check low interrupts -+ ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] -+ ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] -+ mov \irqnr, #31 -+ ands \irqstat, \irqstat, \tmp -+ bne 1001f -+ -+ @ if no low interrupts set, check high interrupts -+ ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] -+ ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF] -+ mov \irqnr, #63 -+ ands \irqstat, \irqstat, \tmp -+ -+ @ find first active interrupt source -+1001: clzne \irqstat, \irqstat -+ subne \irqnr, \irqnr, \irqstat -+ .endm ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/hardware.h -@@ -0,0 +1,21 @@ -+/* -+ * include/asm-arm/arch-kirkwood/hardware.h -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include "kirkwood.h" -+ -+#define pcibios_assign_all_busses() 1 -+ -+#define PCIBIOS_MIN_IO 0x00001000 -+#define PCIBIOS_MIN_MEM 0x01000000 -+#define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */ -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/io.h -@@ -0,0 +1,26 @@ -+/* -+ * include/asm-arm/arch-kirkwood/io.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_IO_H -+#define __ASM_ARCH_IO_H -+ -+#include "kirkwood.h" -+ -+#define IO_SPACE_LIMIT 0xffffffff -+ -+static inline void __iomem *__io(unsigned long addr) -+{ -+ return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE) -+ + KIRKWOOD_PCIE_IO_VIRT_BASE); -+} -+ -+#define __io(a) __io(a) -+#define __mem_pci(a) (a) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/irqs.h -@@ -0,0 +1,63 @@ -+/* -+ * include/asm-arm/arch-kirkwood/irqs.h -+ * -+ * IRQ definitions for Marvell Kirkwood SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_IRQS_H -+#define __ASM_ARCH_IRQS_H -+ -+#include "kirkwood.h" /* need GPIO_MAX */ -+ -+/* -+ * Low Interrupt Controller -+ */ -+#define IRQ_KIRKWOOD_HIGH_SUM 0 -+#define IRQ_KIRKWOOD_BRIDGE 1 -+#define IRQ_KIRKWOOD_HOST2CPU 2 -+#define IRQ_KIRKWOOD_CPU2HOST 3 -+#define IRQ_KIRKWOOD_XOR_00 5 -+#define IRQ_KIRKWOOD_XOR_01 6 -+#define IRQ_KIRKWOOD_XOR_10 7 -+#define IRQ_KIRKWOOD_XOR_11 8 -+#define IRQ_KIRKWOOD_PCIE 9 -+#define IRQ_KIRKWOOD_GE00_SUM 11 -+#define IRQ_KIRKWOOD_GE01_SUM 15 -+#define IRQ_KIRKWOOD_USB 19 -+#define IRQ_KIRKWOOD_SATA 21 -+#define IRQ_KIRKWOOD_CRYPTO 22 -+#define IRQ_KIRKWOOD_SPI 23 -+#define IRQ_KIRKWOOD_I2S 24 -+#define IRQ_KIRKWOOD_TS_0 26 -+#define IRQ_KIRKWOOD_SDIO 28 -+#define IRQ_KIRKWOOD_TWSI 29 -+#define IRQ_KIRKWOOD_AVB 30 -+#define IRQ_KIRKWOOD_TDMI 31 -+ -+/* -+ * High Interrupt Controller -+ */ -+#define IRQ_KIRKWOOD_UART_0 33 -+#define IRQ_KIRKWOOD_UART_1 34 -+#define IRQ_KIRKWOOD_GPIO_LOW_0_7 35 -+#define IRQ_KIRKWOOD_GPIO_LOW_8_15 36 -+#define IRQ_KIRKWOOD_GPIO_LOW_16_23 37 -+#define IRQ_KIRKWOOD_GPIO_LOW_24_31 38 -+#define IRQ_KIRKWOOD_GPIO_HIGH_0_7 39 -+#define IRQ_KIRKWOOD_GPIO_HIGH_8_15 40 -+#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41 -+ -+/* -+ * KIRKWOOD General Purpose Pins -+ */ -+#define IRQ_KIRKWOOD_GPIO_START 64 -+#define NR_GPIO_IRQS GPIO_MAX -+ -+#define NR_IRQS (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/kirkwood.h -@@ -0,0 +1,99 @@ -+/* -+ * include/asm-arm/arch-kirkwood/kirkwood.h -+ * -+ * Generic definitions for Marvell Kirkwood SoC flavors: -+ * 88F6180, 88F6192 and 88F6281. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_KIRKWOOD_H -+#define __ASM_ARCH_KIRKWOOD_H -+ -+/* -+ * Marvell Kirkwood address maps. -+ * -+ * phys -+ * e0000000 PCIe Memory space -+ * f1000000 on-chip peripheral registers -+ * f2000000 PCIe I/O space -+ * f3000000 NAND controller address window -+ * -+ * virt phys size -+ * fee00000 f1000000 1M on-chip peripheral registers -+ * fef00000 f2000000 1M PCIe I/O space -+ */ -+ -+#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 -+#define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K -+ * is the minimal window size -+ */ -+ -+#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 -+#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 -+#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 -+#define KIRKWOOD_PCIE_IO_SIZE SZ_1M -+ -+#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 -+#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 -+#define KIRKWOOD_REGS_SIZE SZ_1M -+ -+#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 -+#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M -+ -+/* -+ * MBUS bridge registers. -+ */ -+#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) -+#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) -+#define CPU_RESET 0x00000002 -+//#define L2_WRITETHROUGH 0x00020000 -+#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) -+#define SOFT_RESET_OUT_EN 0x00000004 -+#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) -+#define SOFT_RESET 0x00000001 -+#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) -+#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) -+#define BRIDGE_INT_TIMER0 0x0002 -+#define BRIDGE_INT_TIMER1 0x0004 -+#define BRIDGE_INT_TIMER1_CLR (~0x0004) -+#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) -+#define IRQ_CAUSE_LOW_OFF 0x0000 -+#define IRQ_MASK_LOW_OFF 0x0004 -+#define IRQ_CAUSE_HIGH_OFF 0x0010 -+#define IRQ_MASK_HIGH_OFF 0x0014 -+#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -+ -+/* -+ * Register Map -+ */ -+#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) -+#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) -+ -+#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) -+#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) -+#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) -+#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) -+#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) -+#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) -+#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -+#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -+#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -+#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) -+ -+#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) -+ -+#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) -+ -+#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) -+#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) -+ -+#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) -+ -+ -+#define GPIO_MAX 50 -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/memory.h -@@ -0,0 +1,14 @@ -+/* -+ * include/asm-arm/arch-kirkwood/memory.h -+ */ -+ -+#ifndef __ASM_ARCH_MEMORY_H -+#define __ASM_ARCH_MEMORY_H -+ -+#define PHYS_OFFSET UL(0x00000000) -+ -+#define __virt_to_bus(x) __virt_to_phys(x) -+#define __bus_to_virt(x) __phys_to_virt(x) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/system.h -@@ -0,0 +1,37 @@ -+/* -+ * include/asm-arm/arch-kirkwood/system.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_SYSTEM_H -+#define __ASM_ARCH_SYSTEM_H -+ -+#include -+#include -+ -+static inline void arch_idle(void) -+{ -+ cpu_do_idle(); -+} -+ -+static inline void arch_reset(char mode) -+{ -+ /* -+ * Enable soft reset to assert RSTOUTn. -+ */ -+ writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); -+ -+ /* -+ * Assert soft reset. -+ */ -+ writel(SOFT_RESET, SYSTEM_SOFT_RESET); -+ -+ while (1) -+ ; -+} -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/timex.h -@@ -0,0 +1,11 @@ -+/* -+ * include/asm-arm/arch-kirkwood/timex.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#define CLOCK_TICK_RATE (100 * HZ) -+ -+#define KIRKWOOD_TCLK 166666667 ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/uncompress.h -@@ -0,0 +1,47 @@ -+/* -+ * include/asm-arm/arch-kirkwood/uncompress.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+ -+#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) -+ -+static void putc(const char c) -+{ -+ unsigned char *base = SERIAL_BASE; -+ int i; -+ -+ for (i = 0; i < 0x1000; i++) { -+ if (base[UART_LSR << 2] & UART_LSR_THRE) -+ break; -+ barrier(); -+ } -+ -+ base[UART_TX << 2] = c; -+} -+ -+static void flush(void) -+{ -+ unsigned char *base = SERIAL_BASE; -+ unsigned char mask; -+ int i; -+ -+ mask = UART_LSR_TEMT | UART_LSR_THRE; -+ -+ for (i = 0; i < 0x1000; i++) { -+ if ((base[UART_LSR << 2] & mask) == mask) -+ break; -+ barrier(); -+ } -+} -+ -+/* -+ * nothing to do -+ */ -+#define arch_decomp_setup() -+#define arch_decomp_wdog() ---- /dev/null -+++ b/include/asm-arm/arch-kirkwood/vmalloc.h -@@ -0,0 +1,5 @@ -+/* -+ * include/asm-arm/arch-kirkwood/vmalloc.h -+ */ -+ -+#define VMALLOC_END 0xfe800000 ---- /dev/null -+++ b/include/asm-arm/arch-loki/debug-macro.S -@@ -0,0 +1,20 @@ -+/* -+ * include/asm-arm/arch-loki/debug-macro.S -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#include -+ -+ .macro addruart,rx -+ mrc p15, 0, \rx, c1, c0 -+ tst \rx, #1 @ MMU enabled? -+ ldreq \rx, =LOKI_REGS_PHYS_BASE -+ ldrne \rx, =LOKI_REGS_VIRT_BASE -+ orr \rx, \rx, #0x00012000 -+ .endm -+ -+#define UART_SHIFT 2 -+#include ---- /dev/null -+++ b/include/asm-arm/arch-loki/dma.h -@@ -0,0 +1 @@ -+/* empty */ ---- /dev/null -+++ b/include/asm-arm/arch-loki/entry-macro.S -@@ -0,0 +1,30 @@ -+/* -+ * include/asm-arm/arch-loki/entry-macro.S -+ * -+ * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+ -+ .macro disable_fiq -+ .endm -+ -+ .macro arch_ret_to_user, tmp1, tmp2 -+ .endm -+ -+ .macro get_irqnr_preamble, base, tmp -+ ldr \base, =IRQ_VIRT_BASE -+ .endm -+ -+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -+ ldr \irqstat, [\base, #IRQ_CAUSE_OFF] -+ ldr \tmp, [\base, #IRQ_MASK_OFF] -+ mov \irqnr, #0 -+ ands \irqstat, \irqstat, \tmp -+ clzne \irqnr, \irqstat -+ rsbne \irqnr, \irqnr, #31 -+ .endm ---- /dev/null -+++ b/include/asm-arm/arch-loki/hardware.h -@@ -0,0 +1,15 @@ -+/* -+ * include/asm-arm/arch-loki/hardware.h -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include "loki.h" -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-loki/io.h -@@ -0,0 +1,26 @@ -+/* -+ * include/asm-arm/arch-loki/io.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_IO_H -+#define __ASM_ARCH_IO_H -+ -+#include "loki.h" -+ -+#define IO_SPACE_LIMIT 0xffffffff -+ -+static inline void __iomem *__io(unsigned long addr) -+{ -+ return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE) -+ + LOKI_PCIE0_IO_VIRT_BASE); -+} -+ -+#define __io(a) __io(a) -+#define __mem_pci(a) (a) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-loki/irqs.h -@@ -0,0 +1,58 @@ -+/* -+ * include/asm-arm/arch-loki/irqs.h -+ * -+ * IRQ definitions for Marvell Loki (88RC8480) SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_IRQS_H -+#define __ASM_ARCH_IRQS_H -+ -+#include "loki.h" /* need GPIO_MAX */ -+ -+/* -+ * Interrupt Controller -+ */ -+#define IRQ_LOKI_PCIE_A_CPU_DRBL 0 -+#define IRQ_LOKI_CPU_PCIE_A_DRBL 1 -+#define IRQ_LOKI_PCIE_B_CPU_DRBL 2 -+#define IRQ_LOKI_CPU_PCIE_B_DRBL 3 -+#define IRQ_LOKI_COM_A_ERR 6 -+#define IRQ_LOKI_COM_A_IN 7 -+#define IRQ_LOKI_COM_A_OUT 8 -+#define IRQ_LOKI_COM_B_ERR 9 -+#define IRQ_LOKI_COM_B_IN 10 -+#define IRQ_LOKI_COM_B_OUT 11 -+#define IRQ_LOKI_DMA_A 12 -+#define IRQ_LOKI_DMA_B 13 -+#define IRQ_LOKI_SAS_A 14 -+#define IRQ_LOKI_SAS_B 15 -+#define IRQ_LOKI_DDR 16 -+#define IRQ_LOKI_XOR 17 -+#define IRQ_LOKI_BRIDGE 18 -+#define IRQ_LOKI_PCIE_A_ERR 20 -+#define IRQ_LOKI_PCIE_A_INT 21 -+#define IRQ_LOKI_PCIE_B_ERR 22 -+#define IRQ_LOKI_PCIE_B_INT 23 -+#define IRQ_LOKI_GBE_A_INT 24 -+#define IRQ_LOKI_GBE_B_INT 25 -+#define IRQ_LOKI_DEV_ERR 26 -+#define IRQ_LOKI_UART0 27 -+#define IRQ_LOKI_UART1 28 -+#define IRQ_LOKI_TWSI 29 -+#define IRQ_LOKI_GPIO_23_0 30 -+#define IRQ_LOKI_GPIO_25_24 31 -+ -+/* -+ * Loki General Purpose Pins -+ */ -+#define IRQ_LOKI_GPIO_START 32 -+#define NR_GPIO_IRQS GPIO_MAX -+ -+#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-loki/loki.h -@@ -0,0 +1,97 @@ -+/* -+ * include/asm-arm/arch-loki/loki.h -+ * -+ * Generic definitions for Marvell Loki (88RC8480) SoC flavors -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_LOKI_H -+#define __ASM_ARCH_LOKI_H -+ -+/* -+ * Marvell Loki (88RC8480) address maps. -+ * -+ * phys -+ * d0000000 on-chip peripheral registers -+ * e0000000 PCIe 0 Memory space -+ * e8000000 PCIe 1 Memory space -+ * f0000000 PCIe 0 I/O space -+ * f0100000 PCIe 1 I/O space -+ * -+ * virt phys size -+ * fed00000 d0000000 1M on-chip peripheral registers -+ * fee00000 f0000000 64K PCIe 0 I/O space -+ * fef00000 f0100000 64K PCIe 1 I/O space -+ */ -+ -+#define LOKI_REGS_PHYS_BASE 0xd0000000 -+#define LOKI_REGS_VIRT_BASE 0xfed00000 -+#define LOKI_REGS_SIZE SZ_1M -+ -+#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000 -+#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000 -+#define LOKI_PCIE0_IO_BUS_BASE 0x00000000 -+#define LOKI_PCIE0_IO_SIZE SZ_64K -+ -+#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000 -+#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000 -+#define LOKI_PCIE1_IO_BUS_BASE 0x00000000 -+#define LOKI_PCIE1_IO_SIZE SZ_64K -+ -+#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000 -+#define LOKI_PCIE0_MEM_SIZE SZ_128M -+ -+#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000 -+#define LOKI_PCIE1_MEM_SIZE SZ_128M -+ -+/* -+ * Register Map -+ */ -+#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000) -+#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000) -+#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -+#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -+#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -+#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) -+ -+#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000) -+#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x)) -+#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) -+#define SOFT_RESET_OUT_EN 0x00000004 -+#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) -+#define SOFT_RESET 0x00000001 -+#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) -+#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) -+#define BRIDGE_INT_TIMER0 0x0002 -+#define BRIDGE_INT_TIMER1 0x0004 -+#define BRIDGE_INT_TIMER1_CLR 0x0004 -+#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) -+#define IRQ_CAUSE_OFF 0x0000 -+#define IRQ_MASK_OFF 0x0004 -+#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -+ -+#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000) -+ -+#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000) -+ -+#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000) -+ -+#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000) -+ -+#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000) -+#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000) -+ -+#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000) -+#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000) -+ -+#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000) -+#define DDR_REG(x) (DDR_VIRT_BASE | (x)) -+ -+ -+#define GPIO_MAX 8 -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-loki/memory.h -@@ -0,0 +1,14 @@ -+/* -+ * include/asm-arm/arch-loki/memory.h -+ */ -+ -+#ifndef __ASM_ARCH_MEMORY_H -+#define __ASM_ARCH_MEMORY_H -+ -+#define PHYS_OFFSET UL(0x00000000) -+ -+#define __virt_to_bus(x) __virt_to_phys(x) -+#define __bus_to_virt(x) __phys_to_virt(x) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-loki/system.h -@@ -0,0 +1,37 @@ -+/* -+ * include/asm-arm/arch-loki/system.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_SYSTEM_H -+#define __ASM_ARCH_SYSTEM_H -+ -+#include -+#include -+ -+static inline void arch_idle(void) -+{ -+ cpu_do_idle(); -+} -+ -+static inline void arch_reset(char mode) -+{ -+ /* -+ * Enable soft reset to assert RSTOUTn. -+ */ -+ writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); -+ -+ /* -+ * Assert soft reset. -+ */ -+ writel(SOFT_RESET, SYSTEM_SOFT_RESET); -+ -+ while (1) -+ ; -+} -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-loki/timex.h -@@ -0,0 +1,11 @@ -+/* -+ * include/asm-arm/arch-loki/timex.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#define CLOCK_TICK_RATE (100 * HZ) -+ -+#define LOKI_TCLK 180000000 ---- /dev/null -+++ b/include/asm-arm/arch-loki/uncompress.h -@@ -0,0 +1,47 @@ -+/* -+ * include/asm-arm/arch-loki/uncompress.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+ -+#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) -+ -+static void putc(const char c) -+{ -+ unsigned char *base = SERIAL_BASE; -+ int i; -+ -+ for (i = 0; i < 0x1000; i++) { -+ if (base[UART_LSR << 2] & UART_LSR_THRE) -+ break; -+ barrier(); -+ } -+ -+ base[UART_TX << 2] = c; -+} -+ -+static void flush(void) -+{ -+ unsigned char *base = SERIAL_BASE; -+ unsigned char mask; -+ int i; -+ -+ mask = UART_LSR_TEMT | UART_LSR_THRE; -+ -+ for (i = 0; i < 0x1000; i++) { -+ if ((base[UART_LSR << 2] & mask) == mask) -+ break; -+ barrier(); -+ } -+} -+ -+/* -+ * nothing to do -+ */ -+#define arch_decomp_setup() -+#define arch_decomp_wdog() ---- /dev/null -+++ b/include/asm-arm/arch-loki/vmalloc.h -@@ -0,0 +1,5 @@ -+/* -+ * include/asm-arm/arch-loki/vmalloc.h -+ */ -+ -+#define VMALLOC_END 0xfe800000 ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/debug-macro.S -@@ -0,0 +1,20 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/debug-macro.S -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+*/ -+ -+#include -+ -+ .macro addruart,rx -+ mrc p15, 0, \rx, c1, c0 -+ tst \rx, #1 @ MMU enabled? -+ ldreq \rx, =MV78XX0_REGS_PHYS_BASE -+ ldrne \rx, =MV78XX0_REGS_VIRT_BASE -+ orr \rx, \rx, #0x00012000 -+ .endm -+ -+#define UART_SHIFT 2 -+#include ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/dma.h -@@ -0,0 +1 @@ -+/* empty */ ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/entry-macro.S -@@ -0,0 +1,39 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/entry-macro.S -+ * -+ * Low-level IRQ helper macros for Marvell MV78xx0 platforms -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+ -+ .macro disable_fiq -+ .endm -+ -+ .macro arch_ret_to_user, tmp1, tmp2 -+ .endm -+ -+ .macro get_irqnr_preamble, base, tmp -+ ldr \base, =IRQ_VIRT_BASE -+ .endm -+ -+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -+ @ check low interrupts -+ ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] -+ ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] -+ mov \irqnr, #31 -+ ands \irqstat, \irqstat, \tmp -+ -+ @ if no low interrupts set, check high interrupts -+ ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] -+ ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF] -+ moveq \irqnr, #63 -+ andeqs \irqstat, \irqstat, \tmp -+ -+ @ find first active interrupt source -+ clzne \irqstat, \irqstat -+ subne \irqnr, \irqnr, \irqstat -+ .endm ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/hardware.h -@@ -0,0 +1,21 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/hardware.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include "mv78xx0.h" -+ -+#define pcibios_assign_all_busses() 1 -+ -+#define PCIBIOS_MIN_IO 0x00001000 -+#define PCIBIOS_MIN_MEM 0x01000000 -+#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */ -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/io.h -@@ -0,0 +1,26 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/io.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_IO_H -+#define __ASM_ARCH_IO_H -+ -+#include "mv78xx0.h" -+ -+#define IO_SPACE_LIMIT 0xffffffff -+ -+static inline void __iomem *__io(unsigned long addr) -+{ -+ return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) -+ + MV78XX0_PCIE_IO_VIRT_BASE(0)); -+} -+ -+#define __io(a) __io(a) -+#define __mem_pci(a) (a) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/irqs.h -@@ -0,0 +1,91 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/irqs.h -+ * -+ * IRQ definitions for Marvell MV78xx0 SoCs -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_IRQS_H -+#define __ASM_ARCH_IRQS_H -+ -+#include "mv78xx0.h" /* need GPIO_MAX */ -+ -+/* -+ * MV78xx0 Low Interrupt Controller -+ */ -+#define IRQ_MV78XX0_ERR 0 -+#define IRQ_MV78XX0_SPI 1 -+#define IRQ_MV78XX0_I2C_0 2 -+#define IRQ_MV78XX0_I2C_1 3 -+#define IRQ_MV78XX0_IDMA_0 4 -+#define IRQ_MV78XX0_IDMA_1 5 -+#define IRQ_MV78XX0_IDMA_2 6 -+#define IRQ_MV78XX0_IDMA_3 7 -+#define IRQ_MV78XX0_TIMER_0 8 -+#define IRQ_MV78XX0_TIMER_1 9 -+#define IRQ_MV78XX0_TIMER_2 10 -+#define IRQ_MV78XX0_TIMER_3 11 -+#define IRQ_MV78XX0_UART_0 12 -+#define IRQ_MV78XX0_UART_1 13 -+#define IRQ_MV78XX0_UART_2 14 -+#define IRQ_MV78XX0_UART_3 15 -+#define IRQ_MV78XX0_USB_0 16 -+#define IRQ_MV78XX0_USB_1 17 -+#define IRQ_MV78XX0_USB_2 18 -+#define IRQ_MV78XX0_CRYPTO 19 -+#define IRQ_MV78XX0_SDIO_0 20 -+#define IRQ_MV78XX0_SDIO_1 21 -+#define IRQ_MV78XX0_XOR_0 22 -+#define IRQ_MV78XX0_XOR_1 23 -+#define IRQ_MV78XX0_I2S_0 24 -+#define IRQ_MV78XX0_I2S_1 25 -+#define IRQ_MV78XX0_SATA 26 -+#define IRQ_MV78XX0_TDMI 27 -+ -+/* -+ * MV78xx0 High Interrupt Controller -+ */ -+#define IRQ_MV78XX0_PCIE_00 32 -+#define IRQ_MV78XX0_PCIE_01 33 -+#define IRQ_MV78XX0_PCIE_02 34 -+#define IRQ_MV78XX0_PCIE_03 35 -+#define IRQ_MV78XX0_PCIE_10 36 -+#define IRQ_MV78XX0_PCIE_11 37 -+#define IRQ_MV78XX0_PCIE_12 38 -+#define IRQ_MV78XX0_PCIE_13 39 -+#define IRQ_MV78XX0_GE00_SUM 40 -+#define IRQ_MV78XX0_GE00_RX 41 -+#define IRQ_MV78XX0_GE00_TX 42 -+#define IRQ_MV78XX0_GE00_MISC 43 -+#define IRQ_MV78XX0_GE01_SUM 44 -+#define IRQ_MV78XX0_GE01_RX 45 -+#define IRQ_MV78XX0_GE01_TX 46 -+#define IRQ_MV78XX0_GE01_MISC 47 -+#define IRQ_MV78XX0_GE10_SUM 48 -+#define IRQ_MV78XX0_GE10_RX 49 -+#define IRQ_MV78XX0_GE10_TX 50 -+#define IRQ_MV78XX0_GE10_MISC 51 -+#define IRQ_MV78XX0_GE11_SUM 52 -+#define IRQ_MV78XX0_GE11_RX 53 -+#define IRQ_MV78XX0_GE11_TX 54 -+#define IRQ_MV78XX0_GE11_MISC 55 -+#define IRQ_MV78XX0_GPIO_0_7 56 -+#define IRQ_MV78XX0_GPIO_8_15 57 -+#define IRQ_MV78XX0_GPIO_16_23 58 -+#define IRQ_MV78XX0_GPIO_24_31 59 -+#define IRQ_MV78XX0_DB_IN 60 -+#define IRQ_MV78XX0_DB_OUT 61 -+ -+/* -+ * MV78XX0 General Purpose Pins -+ */ -+#define IRQ_MV78XX0_GPIO_START 64 -+#define NR_GPIO_IRQS GPIO_MAX -+ -+#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/memory.h -@@ -0,0 +1,14 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/memory.h -+ */ -+ -+#ifndef __ASM_ARCH_MEMORY_H -+#define __ASM_ARCH_MEMORY_H -+ -+#define PHYS_OFFSET UL(0x00000000) -+ -+#define __virt_to_bus(x) __virt_to_phys(x) -+#define __bus_to_virt(x) __phys_to_virt(x) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/mv78xx0.h -@@ -0,0 +1,126 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/mv78xx0.h -+ * -+ * Generic definitions for Marvell MV78xx0 SoC flavors: -+ * MV781x0 and MV782x0. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_MV78XX0_H -+#define __ASM_ARCH_MV78XX0_H -+ -+/* -+ * Marvell MV78xx0 address maps. -+ * -+ * phys -+ * c0000000 PCIe Memory space -+ * f0800000 PCIe #0 I/O space -+ * f0900000 PCIe #1 I/O space -+ * f0a00000 PCIe #2 I/O space -+ * f0b00000 PCIe #3 I/O space -+ * f0c00000 PCIe #4 I/O space -+ * f0d00000 PCIe #5 I/O space -+ * f0e00000 PCIe #6 I/O space -+ * f0f00000 PCIe #7 I/O space -+ * f1000000 on-chip peripheral registers -+ * -+ * virt phys size -+ * fe400000 f102x000 16K core-specific peripheral registers -+ * fe700000 f0800000 1M PCIe #0 I/O space -+ * fe800000 f0900000 1M PCIe #1 I/O space -+ * fe900000 f0a00000 1M PCIe #2 I/O space -+ * fea00000 f0b00000 1M PCIe #3 I/O space -+ * feb00000 f0c00000 1M PCIe #4 I/O space -+ * fec00000 f0d00000 1M PCIe #5 I/O space -+ * fed00000 f0e00000 1M PCIe #6 I/O space -+ * fee00000 f0f00000 1M PCIe #7 I/O space -+ * fef00000 f1000000 1M on-chip peripheral registers -+ */ -+#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 -+#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 -+#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 -+#define MV78XX0_CORE_REGS_SIZE SZ_16K -+ -+#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -+#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) -+#define MV78XX0_PCIE_IO_SIZE SZ_1M -+ -+#define MV78XX0_REGS_PHYS_BASE 0xf1000000 -+#define MV78XX0_REGS_VIRT_BASE 0xfef00000 -+#define MV78XX0_REGS_SIZE SZ_1M -+ -+#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 -+#define MV78XX0_PCIE_MEM_SIZE 0x30000000 -+ -+/* -+ * Core-specific peripheral registers. -+ */ -+#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) -+#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) -+#define L2_WRITETHROUGH 0x00020000 -+#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) -+#define SOFT_RESET_OUT_EN 0x00000004 -+#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) -+#define SOFT_RESET 0x00000001 -+#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) -+#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) -+#define BRIDGE_INT_TIMER0 0x0002 -+#define BRIDGE_INT_TIMER1 0x0004 -+#define BRIDGE_INT_TIMER1_CLR (~0x0004) -+#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) -+#define IRQ_CAUSE_LOW_OFF 0x0004 -+#define IRQ_CAUSE_HIGH_OFF 0x0008 -+#define IRQ_MASK_LOW_OFF 0x0010 -+#define IRQ_MASK_HIGH_OFF 0x0014 -+#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -+ -+/* -+ * Register Map -+ */ -+#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) -+#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) -+#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700) -+ -+#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) -+#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) -+#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) -+#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) -+#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -+#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -+#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -+#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) -+#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) -+#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) -+#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) -+#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) -+ -+#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) -+#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) -+ -+#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) -+#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) -+#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) -+#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) -+ -+#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) -+#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) -+#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) -+ -+#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) -+#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) -+ -+#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) -+#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) -+#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) -+#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) -+ -+#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) -+ -+ -+#define GPIO_MAX 32 -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/system.h -@@ -0,0 +1,37 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/system.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_SYSTEM_H -+#define __ASM_ARCH_SYSTEM_H -+ -+#include -+#include -+ -+static inline void arch_idle(void) -+{ -+ cpu_do_idle(); -+} -+ -+static inline void arch_reset(char mode) -+{ -+ /* -+ * Enable soft reset to assert RSTOUTn. -+ */ -+ writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); -+ -+ /* -+ * Assert soft reset. -+ */ -+ writel(SOFT_RESET, SYSTEM_SOFT_RESET); -+ -+ while (1) -+ ; -+} -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/timex.h -@@ -0,0 +1,9 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/timex.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#define CLOCK_TICK_RATE (100 * HZ) ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/uncompress.h -@@ -0,0 +1,47 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/uncompress.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+ -+#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) -+ -+static void putc(const char c) -+{ -+ unsigned char *base = SERIAL_BASE; -+ int i; -+ -+ for (i = 0; i < 0x1000; i++) { -+ if (base[UART_LSR << 2] & UART_LSR_THRE) -+ break; -+ barrier(); -+ } -+ -+ base[UART_TX << 2] = c; -+} -+ -+static void flush(void) -+{ -+ unsigned char *base = SERIAL_BASE; -+ unsigned char mask; -+ int i; -+ -+ mask = UART_LSR_TEMT | UART_LSR_THRE; -+ -+ for (i = 0; i < 0x1000; i++) { -+ if ((base[UART_LSR << 2] & mask) == mask) -+ break; -+ barrier(); -+ } -+} -+ -+/* -+ * nothing to do -+ */ -+#define arch_decomp_setup() -+#define arch_decomp_wdog() ---- /dev/null -+++ b/include/asm-arm/arch-mv78xx0/vmalloc.h -@@ -0,0 +1,5 @@ -+/* -+ * include/asm-arm/arch-mv78xx0/vmalloc.h -+ */ -+ -+#define VMALLOC_END 0xfe000000 ---- a/include/asm-arm/arch-orion5x/io.h -+++ b/include/asm-arm/arch-orion5x/io.h -@@ -14,7 +14,6 @@ - #include "orion5x.h" - - #define IO_SPACE_LIMIT 0xffffffff --#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE - - static inline void __iomem * - __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) -@@ -53,15 +52,12 @@ - /***************************************************************************** - * Helpers to access Orion registers - ****************************************************************************/ --#define orion5x_read(r) __raw_readl(r) --#define orion5x_write(r, val) __raw_writel(val, r) -- - /* - * These are not preempt-safe. Locks, if needed, must be taken - * care of by the caller. - */ --#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) --#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) -+#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r)) -+#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r)) - - - #endif ---- a/include/asm-arm/arch-orion5x/orion5x.h -+++ b/include/asm-arm/arch-orion5x/orion5x.h -@@ -2,7 +2,7 @@ - * include/asm-arm/arch-orion5x/orion5x.h - * - * Generic definitions of Orion SoC flavors: -- * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. -+ * Orion-1, Orion-VoIP, Orion-NAS, and Orion-2. - * - * Maintainer: Tzachi Perelstein - * -@@ -63,9 +63,11 @@ - /******************************************************************************* - * Supported Devices & Revisions - ******************************************************************************/ --/* Orion-1 (88F5181) */ -+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ - #define MV88F5181_DEV_ID 0x5181 - #define MV88F5181_REV_B1 3 -+#define MV88F5181L_REV_A0 8 -+#define MV88F5181L_REV_A1 9 - /* Orion-NAS (88F5182) */ - #define MV88F5182_DEV_ID 0x5182 - #define MV88F5182_REV_A2 2 -@@ -152,6 +154,7 @@ - #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) - #define BRIDGE_INT_TIMER0 0x0002 - #define BRIDGE_INT_TIMER1 0x0004 -+#define BRIDGE_INT_TIMER1_CLR (~0x0004) - #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) - #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) - ---- a/include/asm-arm/arch-orion5x/uncompress.h -+++ b/include/asm-arm/arch-orion5x/uncompress.h -@@ -8,23 +8,38 @@ - * warranty of any kind, whether express or implied. - */ - -+#include - #include - --#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) --#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) -- --#define LSR_THRE 0x20 -+#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) - - static void putc(const char c) - { -- int j = 0x1000; -- while (--j && !(*MV_UART_LSR & LSR_THRE)) -+ unsigned char *base = SERIAL_BASE; -+ int i; -+ -+ for (i = 0; i < 0x1000; i++) { -+ if (base[UART_LSR << 2] & UART_LSR_THRE) -+ break; - barrier(); -- *MV_UART_THR = c; -+ } -+ -+ base[UART_TX << 2] = c; - } - - static void flush(void) - { -+ unsigned char *base = SERIAL_BASE; -+ unsigned char mask; -+ int i; -+ -+ mask = UART_LSR_TEMT | UART_LSR_THRE; -+ -+ for (i = 0; i < 0x1000; i++) { -+ if ((base[UART_LSR << 2] & mask) == mask) -+ break; -+ barrier(); -+ } - } - - /* ---- a/include/asm-arm/assembler.h -+++ b/include/asm-arm/assembler.h -@@ -56,6 +56,21 @@ - #endif - - /* -+ * This can be used to enable code to cacheline align the destination -+ * pointer when bulk writing to memory. Experiments on StrongARM and -+ * XScale didn't show this a worthwhile thing to do when the cache is not -+ * set to write-allocate (this would need further testing on XScale when WA -+ * is used). -+ * -+ * On Feroceon there is much to gain however, regardless of cache mode. -+ */ -+#ifdef CONFIG_CPU_FEROCEON -+#define CALGN(code...) code -+#else -+#define CALGN(code...) -+#endif -+ -+/* - * Enable and disable interrupts - */ - #if __LINUX_ARM_ARCH__ >= 6 ---- a/include/asm-arm/cacheflush.h -+++ b/include/asm-arm/cacheflush.h -@@ -95,11 +95,7 @@ - #endif - - #if defined(CONFIG_CPU_FEROCEON) --# ifdef _CACHE --# define MULTI_CACHE 1 --# else --# define _CACHE feroceon --# endif -+# define MULTI_CACHE 1 - #endif - - #if defined(CONFIG_CPU_V6) ---- /dev/null -+++ b/include/asm-arm/plat-orion/cache-feroceon-l2.h -@@ -0,0 +1,11 @@ -+/* -+ * include/asm-arm/plat-orion/cache-feroceon-l2.h -+ * -+ * Copyright (C) 2008 Marvell Semiconductor -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+extern void __init feroceon_l2_init(int l2_wt_override); ---- a/include/asm-arm/plat-orion/pcie.h -+++ b/include/asm-arm/plat-orion/pcie.h -@@ -14,6 +14,7 @@ - u32 orion_pcie_dev_id(void __iomem *base); - u32 orion_pcie_rev(void __iomem *base); - int orion_pcie_link_up(void __iomem *base); -+int orion_pcie_x4_mode(void __iomem *base); - int orion_pcie_get_local_bus_nr(void __iomem *base); - void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); - void orion_pcie_setup(void __iomem *base, ---- a/include/asm-arm/tlbflush.h -+++ b/include/asm-arm/tlbflush.h -@@ -39,6 +39,7 @@ - #define TLB_V6_D_ASID (1 << 17) - #define TLB_V6_I_ASID (1 << 18) - -+#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ - #define TLB_DCLEAN (1 << 30) - #define TLB_WB (1 << 31) - -@@ -51,6 +52,7 @@ - * v4 - ARMv4 without write buffer - * v4wb - ARMv4 with write buffer without I TLB flush entry instruction - * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction -+ * fr - Feroceon (v4wbi with non-outer-cacheable page table walks) - * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction - */ - #undef _TLB -@@ -103,6 +105,23 @@ - # define v4wbi_always_flags (-1UL) - #endif - -+#define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \ -+ TLB_V4_I_FULL | TLB_V4_D_FULL | \ -+ TLB_V4_I_PAGE | TLB_V4_D_PAGE) -+ -+#ifdef CONFIG_CPU_TLB_FEROCEON -+# define fr_possible_flags fr_tlb_flags -+# define fr_always_flags fr_tlb_flags -+# ifdef _TLB -+# define MULTI_TLB 1 -+# else -+# define _TLB v4wbi -+# endif -+#else -+# define fr_possible_flags 0 -+# define fr_always_flags (-1UL) -+#endif -+ - #define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \ - TLB_V4_I_FULL | TLB_V4_D_FULL | \ - TLB_V4_D_PAGE) -@@ -245,12 +264,14 @@ - #define possible_tlb_flags (v3_possible_flags | \ - v4_possible_flags | \ - v4wbi_possible_flags | \ -+ fr_possible_flags | \ - v4wb_possible_flags | \ - v6wbi_possible_flags) - - #define always_tlb_flags (v3_always_flags & \ - v4_always_flags & \ - v4wbi_always_flags & \ -+ fr_always_flags & \ - v4wb_always_flags & \ - v6wbi_always_flags) - -@@ -417,6 +438,11 @@ - if (tlb_flag(TLB_DCLEAN)) - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" - : : "r" (pmd) : "cc"); -+ -+ if (tlb_flag(TLB_L2CLEAN_FR)) -+ asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" -+ : : "r" (pmd) : "cc"); -+ - if (tlb_flag(TLB_WB)) - dsb(); - } -@@ -428,6 +454,10 @@ - if (tlb_flag(TLB_DCLEAN)) - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" - : : "r" (pmd) : "cc"); -+ -+ if (tlb_flag(TLB_L2CLEAN_FR)) -+ asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" -+ : : "r" (pmd) : "cc"); - } - - #undef tlb_flag ---- a/include/linux/mv643xx_eth.h -+++ b/include/linux/mv643xx_eth.h -@@ -17,30 +17,59 @@ - - struct mv643xx_eth_shared_platform_data { - struct mbus_dram_target_info *dram; -- unsigned int t_clk; -+ unsigned int t_clk; - }; - - struct mv643xx_eth_platform_data { -+ /* -+ * Pointer back to our parent instance, and our port number. -+ */ - struct platform_device *shared; -- int port_number; -+ int port_number; - -+ /* -+ * Whether a PHY is present, and if yes, at which address. -+ */ - struct platform_device *shared_smi; -+ int force_phy_addr; -+ int phy_addr; - -- u16 force_phy_addr; /* force override if phy_addr == 0 */ -- u16 phy_addr; -- -- /* If speed is 0, then speed and duplex are autonegotiated. */ -- int speed; /* 0, SPEED_10, SPEED_100, SPEED_1000 */ -- int duplex; /* DUPLEX_HALF or DUPLEX_FULL */ -- -- /* non-zero values of the following fields override defaults */ -- u32 tx_queue_size; -- u32 rx_queue_size; -- u32 tx_sram_addr; -- u32 tx_sram_size; -- u32 rx_sram_addr; -- u32 rx_sram_size; -- u8 mac_addr[6]; /* mac address if non-zero*/ -+ /* -+ * Use this MAC address if it is valid, overriding the -+ * address that is already in the hardware. -+ */ -+ u8 mac_addr[6]; -+ -+ /* -+ * If speed is 0, autonegotiation is enabled. -+ * Valid values for speed: 0, SPEED_10, SPEED_100, SPEED_1000. -+ * Valid values for duplex: DUPLEX_HALF, DUPLEX_FULL. -+ */ -+ int speed; -+ int duplex; -+ -+ /* -+ * Which RX/TX queues to use. -+ */ -+ int rx_queue_mask; -+ int tx_queue_mask; -+ -+ /* -+ * Override default RX/TX queue sizes if nonzero. -+ */ -+ int rx_queue_size; -+ int tx_queue_size; -+ -+ /* -+ * Use on-chip SRAM for RX/TX descriptors if size is nonzero -+ * and sufficient to contain all descriptors for the requested -+ * ring sizes. -+ */ -+ unsigned long rx_sram_addr; -+ int rx_sram_size; -+ unsigned long tx_sram_addr; -+ int tx_sram_size; - }; - --#endif /* __LINUX_MV643XX_ETH_H */ -+ -+#endif diff --git a/target/linux/orion/patches/010-ignore_atag_cmdline.patch b/target/linux/orion/patches/010-ignore_atag_cmdline.patch deleted file mode 100644 index 45975fe38f..0000000000 --- a/target/linux/orion/patches/010-ignore_atag_cmdline.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/kernel/setup.c -+++ b/arch/arm/kernel/setup.c -@@ -719,7 +719,7 @@ - - static int __init parse_tag_cmdline(const struct tag *tag) - { -- strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); -+// strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); - return 0; - } - diff --git a/target/linux/orion/patches/050-wrt350nv2_cfi_workaround.patch b/target/linux/orion/patches/050-wrt350nv2_cfi_workaround.patch deleted file mode 100644 index 270d3e5f12..0000000000 --- a/target/linux/orion/patches/050-wrt350nv2_cfi_workaround.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -323,8 +323,9 @@ - return NULL; - } - -- if (extp->MajorVersion != '1' || -- (extp->MinorVersion < '0' || extp->MinorVersion > '4')) { -+ if ((extp->MajorVersion != '0' && extp->MinorVersion != '0') && -+ (extp->MajorVersion != '1' || -+ (extp->MinorVersion < '0' || extp->MinorVersion > '4'))) { - if (cfi->mfr == MANUFACTURER_SAMSUNG && - (extp->MajorVersion == '3' && extp->MinorVersion == '3')) { - printk(KERN_NOTICE " Newer Samsung flash detected, " diff --git a/target/linux/orion/patches/099-add_netgear_wnr854t_support.patch b/target/linux/orion/patches/099-add_netgear_wnr854t_support.patch deleted file mode 100644 index 206002a791..0000000000 --- a/target/linux/orion/patches/099-add_netgear_wnr854t_support.patch +++ /dev/null @@ -1,199 +0,0 @@ ---- a/arch/arm/mach-orion5x/Kconfig -+++ b/arch/arm/mach-orion5x/Kconfig -@@ -74,6 +74,12 @@ - Say 'Y' here if you want your kernel to support the - Maxtor Shared Storage II platform. - -+config MACH_WNR854T -+ bool "Netgear WNR854T" -+ help -+ Say 'Y' here if you want your kernel to support the -+ Netgear WNR854T platform. -+ - endmenu - - endif ---- a/arch/arm/mach-orion5x/Makefile -+++ b/arch/arm/mach-orion5x/Makefile -@@ -10,3 +10,4 @@ - obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o - obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o - obj-$(CONFIG_MACH_MSS2) += mss2-setup.o -+obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o ---- /dev/null -+++ b/arch/arm/mach-orion5x/wnr854t-setup.c -@@ -0,0 +1,164 @@ -+/* -+ * arch/arm/mach-orion5x/wnr854t-setup.c -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "common.h" -+#include "mpp.h" -+ -+static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = { -+ { 0, MPP_GPIO }, /* Power LED green (0=on) */ -+ { 1, MPP_GPIO }, /* Reset Button (0=off) */ -+ { 2, MPP_GPIO }, /* Power LED blink (0=off) */ -+ { 3, MPP_GPIO }, /* WAN Status LED amber (0=off) */ -+ { 4, MPP_GPIO }, /* PCI int */ -+ { 5, MPP_GPIO }, /* ??? */ -+ { 6, MPP_GPIO }, /* ??? */ -+ { 7, MPP_GPIO }, /* ??? */ -+ { 8, MPP_UNUSED }, /* ??? */ -+ { 9, MPP_GIGE }, /* GE_RXERR */ -+ { 10, MPP_UNUSED }, /* ??? */ -+ { 11, MPP_UNUSED }, /* ??? */ -+ { 12, MPP_GIGE }, /* GE_TXD[4] */ -+ { 13, MPP_GIGE }, /* GE_TXD[5] */ -+ { 14, MPP_GIGE }, /* GE_TXD[6] */ -+ { 15, MPP_GIGE }, /* GE_TXD[7] */ -+ { 16, MPP_GIGE }, /* GE_RXD[4] */ -+ { 17, MPP_GIGE }, /* GE_RXD[5] */ -+ { 18, MPP_GIGE }, /* GE_RXD[6] */ -+ { 19, MPP_GIGE }, /* GE_RXD[7] */ -+ { -1 }, -+}; -+ -+/* -+ * 8M NOR flash Device bus boot chip select -+ */ -+#define WNR854T_NOR_BOOT_BASE 0xf4000000 -+#define WNR854T_NOR_BOOT_SIZE SZ_8M -+ -+static struct mtd_partition wnr854t_nor_flash_partitions[] = { -+ { -+ .name = "kernel", -+ .offset = 0x00000000, -+ .size = 0x00100000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x00100000, -+ .size = 0x00660000, -+ }, { -+ .name = "uboot", -+ .offset = 0x00760000, -+ .size = 0x00040000, -+ }, -+}; -+ -+static struct physmap_flash_data wnr854t_nor_flash_data = { -+ .width = 2, -+ .parts = wnr854t_nor_flash_partitions, -+ .nr_parts = ARRAY_SIZE(wnr854t_nor_flash_partitions), -+}; -+ -+static struct resource wnr854t_nor_flash_resource = { -+ .flags = IORESOURCE_MEM, -+ .start = WNR854T_NOR_BOOT_BASE, -+ .end = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1, -+}; -+ -+static struct platform_device wnr854t_nor_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev = { -+ .platform_data = &wnr854t_nor_flash_data, -+ }, -+ .num_resources = 1, -+ .resource = &wnr854t_nor_flash_resource, -+}; -+ -+static struct mv643xx_eth_platform_data wnr854t_eth_data = { -+ .phy_addr = -1, -+}; -+ -+static void __init wnr854t_init(void) -+{ -+ /* -+ * Setup basic Orion functions. Need to be called early. -+ */ -+ orion5x_init(); -+ -+ orion5x_mpp_conf(wnr854t_mpp_modes); -+ -+ /* -+ * Configure peripherals. -+ */ -+ orion5x_eth_init(&wnr854t_eth_data); -+ orion5x_uart0_init(); -+ -+ orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE, -+ WNR854T_NOR_BOOT_SIZE); -+ platform_device_register(&wnr854t_nor_flash); -+} -+ -+static int __init wnr854t_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ int irq; -+ -+ /* -+ * Check for devices with hard-wired IRQs. -+ */ -+ irq = orion5x_pci_map_irq(dev, slot, pin); -+ if (irq != -1) -+ return irq; -+ -+ /* -+ * Mini-PCI slot. -+ */ -+ if (slot == 7) -+ return gpio_to_irq(4); -+ -+ return -1; -+} -+ -+static struct hw_pci wnr854t_pci __initdata = { -+ .nr_controllers = 2, -+ .swizzle = pci_std_swizzle, -+ .setup = orion5x_pci_sys_setup, -+ .scan = orion5x_pci_sys_scan_bus, -+ .map_irq = wnr854t_pci_map_irq, -+}; -+ -+static int __init wnr854t_pci_init(void) -+{ -+ if (machine_is_wnr854t()) -+ pci_common_init(&wnr854t_pci); -+ -+ return 0; -+} -+subsys_initcall(wnr854t_pci_init); -+ -+MACHINE_START(WNR854T, "Netgear WNR854T") -+ /* Maintainer: Imre Kaloz */ -+ .phys_io = ORION5X_REGS_PHYS_BASE, -+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, -+ .boot_params = 0x00000100, -+ .init_machine = wnr854t_init, -+ .map_io = orion5x_map_io, -+ .init_irq = orion5x_init_irq, -+ .timer = &orion5x_timer, -+ .fixup = tag_fixup_mem32, -+MACHINE_END ---- a/arch/arm/configs/orion5x_defconfig -+++ b/arch/arm/configs/orion5x_defconfig -@@ -166,6 +166,7 @@ - CONFIG_MACH_DNS323=y - CONFIG_MACH_TS209=y - CONFIG_MACH_LINKSTATION_PRO=y -+CONFIG_MACH_WNR854T=y - - # - # Boot options diff --git a/target/linux/orion/patches/100-openwrt_partition_map.patch b/target/linux/orion/patches/100-openwrt_partition_map.patch deleted file mode 100644 index 082c0c1b75..0000000000 --- a/target/linux/orion/patches/100-openwrt_partition_map.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c -+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c -@@ -56,19 +56,11 @@ - { - .name = "kernel", - .offset = 0x00000000, -- .size = 0x00760000, -+ .size = 0x00100000, - }, { - .name = "rootfs", -- .offset = 0x001a0000, -- .size = 0x005c0000, -- }, { -- .name = "lang", -- .offset = 0x00760000, -- .size = 0x00040000, -- }, { -- .name = "nvram", -- .offset = 0x007a0000, -- .size = 0x00020000, -+ .offset = 0x00100000, -+ .size = 0x006c0000, - }, { - .name = "u-boot", - .offset = 0x007c0000, diff --git a/target/linux/ps3/Makefile b/target/linux/ps3/Makefile deleted file mode 100644 index daa2c62d78..0000000000 --- a/target/linux/ps3/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright (C) 2007 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=powerpc -BOARD:=ps3 -BOARDNAME:=Sony PS3 Game Console - -LINUX_VERSION:=2.6.25.17 - -KERNEL_CC:= - -include $(INCLUDE_DIR)/target.mk - -define Target/Description - Build bootloader images for the Sony PS3 Game Console -endef - -# no generic patches required -define Kernel/Prepare - bzcat $(DL_DIR)/$(LINUX_SOURCE) | $(TAR) -C $(KERNEL_BUILD_DIR) $(TAR_OPTIONS) - $(call PatchDir,$(PATCH_DIR),) -endef - -KERNELNAME:="zImage" - -$(eval $(call BuildTarget)) diff --git a/target/linux/ps3/README b/target/linux/ps3/README deleted file mode 100644 index 2d08b8c259..0000000000 --- a/target/linux/ps3/README +++ /dev/null @@ -1,43 +0,0 @@ -OpenWRT on the Sony PS3 Game Console - -The OpenWRT build will create both a 1st stage PS3-Linux image -suitable for programming into the PS3 flash memory, and a 2nd -stage PS3-Linux image suitable for loading via bootloaders or -the kexec utility. - -The 2nd stage image is convenient for testing new builds. It can -be loaded from disk, USB device, or the network by an existing -Other OS bootloader. After the 2nd stage image is tested and -found to be good, the 1st stage image can then be programmed into -flash memory. It is recommended to use this method during -development to avoid corrupting the flash memory contents, which -requires a reboot to the Game OS to repair. - -Known good Other OS bootloader images and installation information -can be found here: - - http://www.kernel.org/pub/linux/kernel/people/geoff/cell/ - -The 2nd stage image file is bin/openwrt-ps3-vmlinux.elf. It can -be loaded with an entry in the bootloader config file. It has -no initrd file. - -The 1st stage image is named bin/otheros.bld. It can be programmed -into flash memory either from Linux or the Game OS. From Linux, -use the command: - - ps3-flash-util -w otheros.bld - -From the Game OS, use the menu item 'Install Other OS'. - -Tips on how to recover your PS3-Linux system when it hangs up or no -longer boots can be found here: - - http://www.kernel.org/pub/linux/kernel/people/geoff/cell/ps3-howto/ps3-boot-recovery-howto.txt - -To alter the kernel command line options, run 'make kernel_menuconfig' -and go to 'Kernel Options' -> 'Initial kernel command string'. - -The default video behavior is to autodetect the monitor capabilities, -which should work for most monitors. More info on video modes can be -found in the man page of the ps3-video-mode utility. diff --git a/target/linux/ps3/base-files/bin/login b/target/linux/ps3/base-files/bin/login deleted file mode 100755 index 2e649f04fe..0000000000 --- a/target/linux/ps3/base-files/bin/login +++ /dev/null @@ -1,45 +0,0 @@ -#!/bin/sh -# Copyright (C) 2008 OpenWrt.org - -bl_option=/sbin/bl-option - -if [ ! -f $bl_option ] || - [ ! `$bl_option --get-telnet-enabled` ] || - [ `$bl_option --get-telnet-enabled` = "0" ]; then - echo \ -" - === IMPORTANT ========================== - Telnet login is disabled for security - reasons. Enabling telnet login on the - host will allow any user connected to - the same network to login to the host. - - You can enable telnet login with the - following command in the host console: - - # $bl_option -T 1 - - You can disable telnet login with the - following command in the host console: - - # $bl_option -T 0 - ---------------------------------------- -" - exit 0 -fi - -grep '^root:[^!]' /etc/passwd >&- 2>&- -[ "$?" = "0" -a -z "$FAILSAFE" ] && -{ - echo "Login failed." - exit 0 -} || { -cat << EOF - === IMPORTANT ============================ - Use 'passwd' to set your login password - this will disable telnet and enable SSH - ------------------------------------------ -EOF -} - -exec /bin/ash --login diff --git a/target/linux/ps3/base-files/etc/banner b/target/linux/ps3/base-files/etc/banner deleted file mode 100644 index 4d671c7ba5..0000000000 --- a/target/linux/ps3/base-files/etc/banner +++ /dev/null @@ -1,6 +0,0 @@ - _____ _____ _____ - | _ || ___||___ | - | __||___ ||___ | - |__| |_____||_____| - L I N U X - diff --git a/target/linux/ps3/base-files/etc/config/system b/target/linux/ps3/base-files/etc/config/system deleted file mode 100644 index 1334f3eb22..0000000000 --- a/target/linux/ps3/base-files/etc/config/system +++ /dev/null @@ -1,2 +0,0 @@ -config system - option hostname ps3-linux diff --git a/target/linux/ps3/base-files/etc/inittab b/target/linux/ps3/base-files/etc/inittab deleted file mode 100644 index 96abea9842..0000000000 --- a/target/linux/ps3/base-files/etc/inittab +++ /dev/null @@ -1,7 +0,0 @@ -::sysinit:/etc/init.d/rcS S boot -::shutdown:/etc/init.d/rcS K stop -::ctrlaltdel:/sbin/reboot -::restart:/sbin/init -tty1::respawn:/sbin/initrun -tty2::askfirst:/bin/ash --login -tty3::askfirst:/bin/ash --login diff --git a/target/linux/ps3/base-files/sbin/bl-option b/target/linux/ps3/base-files/sbin/bl-option deleted file mode 100755 index 8eea93d979..0000000000 --- a/target/linux/ps3/base-files/sbin/bl-option +++ /dev/null @@ -1,113 +0,0 @@ -#!/bin/sh -# -# Copyright (C) 2008 Sony Computer Entertainment Inc. -# Copyright 2008 Sony Corp. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -# - -usage() { - echo "" >&2 - echo "SYNOPSIS" >&2 - echo " bl-option [OPTION]" >&2 - echo "" >&2 - echo "DESCRIPTION" >&2 - echo " Get and set PS3 bootloader options in flash." >&2 - echo "" >&2 - echo "OPTIONS" >&2 - echo " -m, --get-video-mode" >&2 - echo " Get the bootloader video mode." >&2 - echo "" >&2 - echo " -M, --set-video-mode value" >&2 - echo " Set the bootloader video mode." >&2 - echo "" >&2 - echo " -p, --get-petitboot-default" >&2 - echo " Get the default Petitboot menu item." >&2 - echo "" >&2 - echo " -P, --set-petitboot-default value" >&2 - echo " Set the default Petitboot menu item." >&2 - echo "" >&2 - echo " -t, --get-telnet-enabled" >&2 - echo " Get the telnet enabled flag." >&2 - echo "" >&2 - echo " -T, --set-telnet-enabled value" >&2 - echo " Set the telnet enabled flag." >&2 - echo "" >&2 - echo " -h, --help" >&2 - echo " Print a help message." >&2 - echo "" >&2 - echo "SEE ALSO" >&2 - echo " ps3-flash-util(8)" >&2 - echo "" >&2 - exit 1 -} - -if [ "$#" -eq 0 ] ; then - echo "ERROR: bad arg" >&2; - usage -fi - -get_flag() { - flags=`ps3-flash-util --db-print $1 $2` - echo $(( ${flags:-0} & $3 )) -} - -set_flag() { - flags=`ps3-flash-util --db-print $1 $2` - - if [ $4 -eq 0 ]; then - ps3-flash-util --db-write-half $1 $2 $(( ${flags:-0} & ~$3 )) - else - ps3-flash-util --db-write-half $1 $2 $(( ${flags:-0} | $3 )) - fi -} - -# owners -petitboot="3" - -# keys -menu="1" -video="2" -flags="3" - -# flags -telnet="1" - -case "$1" in - -m | --get-video-mode) - ps3-flash-util --db-print ${petitboot} ${video} - ;; - -M | --set-video-mode) - ps3-flash-util --db-write-half ${petitboot} ${video} $2 - ;; - -p | --get-petitboot-default) - ps3-flash-util --db-print ${petitboot} ${menu} - ;; - -P | --set-petitboot-default) - ps3-flash-util --db-write-word ${petitboot} ${menu} $2 - ;; - -t | --get-telnet-enabled) - get_flag ${petitboot} ${flags} ${telnet} - ;; - -T | --set-telnet-enabled) - set_flag ${petitboot} ${flags} ${telnet} $2 - ;; - -h | --help) - usage - ;; - *) - echo "ERROR: bad arg $1" >&2; - usage - ;; -esac diff --git a/target/linux/ps3/base-files/sbin/initrun b/target/linux/ps3/base-files/sbin/initrun deleted file mode 100755 index e253c24b3a..0000000000 --- a/target/linux/ps3/base-files/sbin/initrun +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -/bin/ash --login diff --git a/target/linux/ps3/config-2.6.25 b/target/linux/ps3/config-2.6.25 deleted file mode 100644 index 576272477a..0000000000 --- a/target/linux/ps3/config-2.6.25 +++ /dev/null @@ -1,976 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.25 -# Wed Apr 23 14:44:56 2008 -# -CONFIG_PPC64=y - -# -# Processor support -# -# CONFIG_POWER4_ONLY is not set -CONFIG_POWER3=y -CONFIG_POWER4=y -CONFIG_TUNE_CELL=y -CONFIG_PPC_FPU=y -CONFIG_ALTIVEC=y -CONFIG_PPC_STD_MMU=y -# CONFIG_PPC_MM_SLICES is not set -CONFIG_VIRT_CPU_ACCOUNTING=y -CONFIG_SMP=y -CONFIG_NR_CPUS=2 -CONFIG_64BIT=y -CONFIG_WORD_SIZE=64 -CONFIG_PPC_MERGE=y -CONFIG_MMU=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_HAVE_SETUP_PER_CPU_AREA=y -CONFIG_IRQ_PER_CPU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_ARCH_HAS_ILOG2_U32=y -CONFIG_ARCH_HAS_ILOG2_U64=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_ARCH_NO_VIRT_TO_BUS=y -CONFIG_PPC=y -CONFIG_EARLY_PRINTK=y -CONFIG_COMPAT=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_PPC_OF=y -CONFIG_OF=y -# CONFIG_PPC_UDBG_16550 is not set -# CONFIG_GENERIC_TBSYNC is not set -CONFIG_AUDIT_ARCH=y -CONFIG_GENERIC_BUG=y -# CONFIG_DEFAULT_UIMAGE is not set -# CONFIG_PPC_DCR_NATIVE is not set -# CONFIG_PPC_DCR_MMIO is not set -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -# CONFIG_SYSVIPC is not set -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_CGROUPS is not set -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -# CONFIG_KALLSYMS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_COMPAT_BRK=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_ANON_INODES=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -# CONFIG_SHMEM is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_TINY_SHMEM=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set -CONFIG_BLOCK=y -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_BLK_DEV_BSG is not set -CONFIG_BLOCK_COMPAT=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -CONFIG_CLASSIC_RCU=y - -# -# Platform support -# -CONFIG_PPC_MULTIPLATFORM=y -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set -# CONFIG_PPC_PSERIES is not set -# CONFIG_PPC_ISERIES is not set -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set -# CONFIG_PPC_PMAC is not set -# CONFIG_PPC_MAPLE is not set -# CONFIG_PPC_PASEMI is not set -# CONFIG_PPC_CELLEB is not set -CONFIG_PPC_PS3=y - -# -# PS3 Platform Options -# -# CONFIG_PS3_ADVANCED is not set -CONFIG_PS3_HTAB_SIZE=20 -# CONFIG_PS3_DYNAMIC_DMA is not set -CONFIG_PS3_VUART=y -CONFIG_PS3_PS3AV=y -CONFIG_PS3_SYS_MANAGER=y -CONFIG_PS3_STORAGE=y -CONFIG_PS3_DISK=y -CONFIG_PS3_ROM=y -CONFIG_PS3_FLASH=y -# CONFIG_PS3_LPM is not set -CONFIG_PPC_CELL=y -# CONFIG_PPC_CELL_NATIVE is not set -# CONFIG_PPC_IBM_CELL_BLADE is not set -# CONFIG_SND_PS3 is not set - -# -# Cell Broadband Engine options -# -# CONFIG_SPU_FS is not set -# CONFIG_SPU_BASE is not set -# CONFIG_PQ2ADS is not set -# CONFIG_IPIC is not set -# CONFIG_MPIC is not set -# CONFIG_MPIC_WEIRD is not set -# CONFIG_PPC_I8259 is not set -# CONFIG_U3_DART is not set -# CONFIG_PPC_RTAS is not set -# CONFIG_MMIO_NVRAM is not set -# CONFIG_PPC_MPC106 is not set -# CONFIG_PPC_970_NAP is not set -# CONFIG_PPC_INDIRECT_IO is not set -# CONFIG_GENERIC_IOMAP is not set -# CONFIG_CPU_FREQ is not set -# CONFIG_FSL_ULI1575 is not set - -# -# Kernel options -# -# CONFIG_TICK_ONESHOT is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_BINFMT_ELF=y -CONFIG_COMPAT_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_FORCE_MAX_ZONEORDER=13 -# CONFIG_IOMMU_VMERGE is not set -CONFIG_IOMMU_HELPER=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_HAS_WALK_MEMORY=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y -CONFIG_KEXEC=y -# CONFIG_CRASH_DUMP is not set -# CONFIG_IRQ_ALL_CPUS is not set -# CONFIG_NUMA is not set -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set -# CONFIG_DISCONTIGMEM_MANUAL is not set -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM=y -CONFIG_HAVE_MEMORY_PRESENT=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_SPARSE=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y -CONFIG_ARCH_MEMORY_PROBE=y -# CONFIG_PPC_HAS_HASH_64K is not set -# CONFIG_PPC_64K_PAGES is not set -# CONFIG_SCHED_SMT is not set -CONFIG_PROC_DEVICETREE=y -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="" -# CONFIG_PM is not set -# CONFIG_SECCOMP is not set -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -CONFIG_ZONE_DMA=y -CONFIG_GENERIC_ISA_DMA=y -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set -CONFIG_KERNEL_START=0xc000000000000000 - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -CONFIG_OF_DEVICE=y -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=65535 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -CONFIG_MISC_DEVICES=y -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_PROC_FS is not set - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -# CONFIG_MACINTOSH_DRIVERS is not set -CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_NET_ETHERNET is not set -CONFIG_NETDEV_1000=y -# CONFIG_E1000E_ENABLED is not set -CONFIG_GELIC_NET=y -# CONFIG_GELIC_WIRELESS is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -# CONFIG_JOYSTICK_ANALOG is not set -# CONFIG_JOYSTICK_A3D is not set -# CONFIG_JOYSTICK_ADI is not set -# CONFIG_JOYSTICK_COBRA is not set -# CONFIG_JOYSTICK_GF2K is not set -# CONFIG_JOYSTICK_GRIP is not set -# CONFIG_JOYSTICK_GRIP_MP is not set -# CONFIG_JOYSTICK_GUILLEMOT is not set -# CONFIG_JOYSTICK_INTERACT is not set -# CONFIG_JOYSTICK_SIDEWINDER is not set -# CONFIG_JOYSTICK_TMDC is not set -# CONFIG_JOYSTICK_IFORCE is not set -# CONFIG_JOYSTICK_WARRIOR is not set -# CONFIG_JOYSTICK_MAGELLAN is not set -# CONFIG_JOYSTICK_SPACEORB is not set -# CONFIG_JOYSTICK_SPACEBALL is not set -# CONFIG_JOYSTICK_STINGER is not set -# CONFIG_JOYSTICK_TWIDJOY is not set -# CONFIG_JOYSTICK_JOYDUMP is not set -# CONFIG_JOYSTICK_XPAD is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=16 -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_HANGCHECK_TIMER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set - -# -# Sonics Silicon Backplane -# -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_OF is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_IBM_GXT4500 is not set -CONFIG_FB_PS3=y -CONFIG_FB_PS3_DEFAULT_SIZE_M=9 -# CONFIG_FB_VIRTUAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -# CONFIG_LOGO is not set - -# -# Sound -# -# CONFIG_SOUND is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set -# CONFIG_USB_HIDDEV is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set - -# -# USB Host Controller Drivers -# -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y -CONFIG_USB_EHCI_HCD_PPC_OF=y -# CONFIG_USB_ISP116X_HCD is not set -CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_HCD_PPC_OF is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# may also be needed; see USB_STORAGE Help for more information -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_GADGET is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_EDAC is not set -# CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set - -# -# Userspace I/O -# -# CONFIG_UIO is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -# CONFIG_ZISOFS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLBFS is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_SAMPLES is not set -# CONFIG_IRQSTACKS is not set -# CONFIG_BOOTX_TEXT is not set -# CONFIG_PPC_EARLY_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=y -# CONFIG_CRYPTO_SEQIV is not set -CONFIG_CRYPTO_MANAGER=y -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_GF128MUL is not set -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_PCBC=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_LZO is not set -# CONFIG_PPC_CLOCK is not set diff --git a/target/linux/ps3/image/Makefile b/target/linux/ps3/image/Makefile deleted file mode 100644 index 1d04c40ae8..0000000000 --- a/target/linux/ps3/image/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (C) 2007 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Image/Prepare - cp $(LINUX_DIR)/arch/powerpc/boot/otheros.bld $(KDIR)/image -endef - -define Image/BuildKernel - cp $(KDIR)/image $(BIN_DIR)/otheros.bld - cp $(KDIR)/vmlinux.elf $(BIN_DIR)/openwrt-$(BOARD)-vmlinux.elf -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/ps3/patches-2.6.25/100-ps3-system-bus-quiet-match-output.patch b/target/linux/ps3/patches-2.6.25/100-ps3-system-bus-quiet-match-output.patch deleted file mode 100644 index c2ae9f2cc8..0000000000 --- a/target/linux/ps3/patches-2.6.25/100-ps3-system-bus-quiet-match-output.patch +++ /dev/null @@ -1,69 +0,0 @@ -Subject: PS3: Quiet system bus match output - -Reduce the verbosity of the output from ps3_system_bus_match(). - -Signed-off-by: Geoff Levand ---- - arch/powerpc/platforms/ps3/system-bus.c | 21 +++++++++++++-------- - 1 file changed, 13 insertions(+), 8 deletions(-) - ---- a/arch/powerpc/platforms/ps3/system-bus.c -+++ b/arch/powerpc/platforms/ps3/system-bus.c -@@ -349,9 +349,14 @@ - - result = dev->match_id == drv->match_id; - -- pr_info("%s:%d: dev=%u(%s), drv=%u(%s): %s\n", __func__, __LINE__, -- dev->match_id, dev->core.bus_id, drv->match_id, drv->core.name, -- (result ? "match" : "miss")); -+ if (result) -+ pr_info("%s:%d: dev=%u(%s), drv=%u(%s): match\n", __func__, -+ __LINE__, dev->match_id, dev->core.bus_id, -+ drv->match_id, drv->core.name); -+ else -+ pr_debug("%s:%d: dev=%u(%s), drv=%u(%s): miss\n", __func__, -+ __LINE__, dev->match_id, dev->core.bus_id, -+ drv->match_id, drv->core.name); - return result; - } - -@@ -362,7 +367,7 @@ - struct ps3_system_bus_driver *drv; - - BUG_ON(!dev); -- pr_info(" -> %s:%d: %s\n", __func__, __LINE__, _dev->bus_id); -+ pr_debug(" -> %s:%d: %s\n", __func__, __LINE__, _dev->bus_id); - - drv = ps3_system_bus_dev_to_system_bus_drv(dev); - BUG_ON(!drv); -@@ -370,10 +375,10 @@ - if (drv->probe) - result = drv->probe(dev); - else -- pr_info("%s:%d: %s no probe method\n", __func__, __LINE__, -+ pr_debug("%s:%d: %s no probe method\n", __func__, __LINE__, - dev->core.bus_id); - -- pr_info(" <- %s:%d: %s\n", __func__, __LINE__, dev->core.bus_id); -+ pr_debug(" <- %s:%d: %s\n", __func__, __LINE__, dev->core.bus_id); - return result; - } - -@@ -384,7 +389,7 @@ - struct ps3_system_bus_driver *drv; - - BUG_ON(!dev); -- pr_info(" -> %s:%d: %s\n", __func__, __LINE__, _dev->bus_id); -+ pr_debug(" -> %s:%d: %s\n", __func__, __LINE__, _dev->bus_id); - - drv = ps3_system_bus_dev_to_system_bus_drv(dev); - BUG_ON(!drv); -@@ -395,7 +400,7 @@ - dev_dbg(&dev->core, "%s:%d %s: no remove method\n", - __func__, __LINE__, drv->core.name); - -- pr_info(" <- %s:%d: %s\n", __func__, __LINE__, dev->core.bus_id); -+ pr_debug(" <- %s:%d: %s\n", __func__, __LINE__, dev->core.bus_id); - return result; - } - diff --git a/target/linux/pxa/Makefile b/target/linux/pxa/Makefile deleted file mode 100644 index 952110b05d..0000000000 --- a/target/linux/pxa/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (C) 2006-2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=pxa -BOARDNAME:=Marvell/Intel PXA2xx -FEATURES:=jffs2 broken - -LINUX_VERSION:=2.6.21.7 - -include $(INCLUDE_DIR)/target.mk - -define Target/Description - Build images for PAX2xx systems, eg. Gumstix. -endef - -define Kernel/Configure - $(call Kernel/Configure/Default) - $(SED) 's,.*CONFIG_AEABI.*,$(if $(CONFIG_EABI_SUPPORT),CONFIG_AEABI=y,# CONFIG_AEABI is not set),' $(LINUX_DIR)/.config - $(if $(CONFIG_EABI_SUPPORT),echo '# CONFIG_OABI_COMPAT is not set' >> $(LINUX_DIR)/.config) -endef - -KERNELNAME:="uImage" - -$(eval $(call BuildTarget)) diff --git a/target/linux/pxa/config-default b/target/linux/pxa/config-default deleted file mode 100644 index b880daf4c8..0000000000 --- a/target/linux/pxa/config-default +++ /dev/null @@ -1,357 +0,0 @@ -CONFIG_AC97_BUS=m -# CONFIG_AEABI is not set -# CONFIG_AIRO_CS is not set -CONFIG_ALIGNMENT_HANDLING=0x2 -CONFIG_ALIGNMENT_TRAP=y -CONFIG_APM_EMULATION=m -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -CONFIG_ARCH_GUMSTIX=y -# CONFIG_ARCH_GUMSTIX_F is not set -# CONFIG_ARCH_GUMSTIX_ORIG is not set -CONFIG_ARCH_GUMSTIX_VERDEX=y -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_LUBBOCK is not set -CONFIG_ARCH_MTD_XIP=y -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_PNX4008 is not set -CONFIG_ARCH_PXA=y -# CONFIG_ARCH_PXA_IDP is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_VERSATILE is not set -CONFIG_ARM=y -# CONFIG_ARM_THUMB is not set -# CONFIG_ARPD is not set -# CONFIG_ARTHUR is not set -CONFIG_ATA=m -# CONFIG_ATA_NONSTANDARD is not set -# CONFIG_ATM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BINFMT_AOUT is not set -CONFIG_BITREVERSE=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDE=m -CONFIG_BLK_DEV_IDECS=m -CONFIG_BLK_DEV_IDEDISK=m -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_BONDING is not set -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_BT_BNEP_MC_FILTER is not set -# CONFIG_BT_BNEP_PROTO_FILTER is not set -CONFIG_BT_GUMSTIX=m -# CONFIG_BT_HCIBCM203X is not set -# CONFIG_BT_HCIBFUSB is not set -# CONFIG_BT_HCIBPA10X is not set -# CONFIG_BT_HCIUART_BCSP is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_CIFS is not set -CONFIG_CMDLINE="console=ttyS0,115200n8" -# CONFIG_CONFIGFS_FS is not set -CONFIG_CPU_32=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_FREQ is not set -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_XSCALE=y -# CONFIG_CRC16 is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_USER is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_DM9000 is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_EPOLL is not set -# CONFIG_EXT2_FS is not set -CONFIG_FB=y -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_DDC is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_MBX is not set -# CONFIG_FB_MODE_HELPERS is not set -CONFIG_FB_PXA=y -# CONFIG_FB_PXA_ALPS_CDOLLAR is not set -# CONFIG_FB_PXA_NONEOFTHEABOVE is not set -CONFIG_FB_PXA_PARAMETERS=y -CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C=y -# CONFIG_FB_PXA_SHARP_LQ043_PSP is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_SVGALIB is not set -CONFIG_FB_TILEBLITTING=y -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FONTS=y -# CONFIG_FONT_10x18 is not set -CONFIG_FONT_6x11=y -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_8x16 is not set -# CONFIG_FONT_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FPE_FASTFPE is not set -# CONFIG_FPE_NWFPE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_POSIX_ACL=y -CONFIG_GENERIC_GPIO=y -# CONFIG_HAMRADIO is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -# CONFIG_HERMES is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_HFS_FS is not set -CONFIG_HID=m -CONFIG_HW_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=m -# CONFIG_I2C_ALGOBIT is not set -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_PXA=m -CONFIG_I2C_PXA_SLAVE=y -CONFIG_IDE=m -# CONFIG_IDE_ARM is not set -CONFIG_IDE_GENERIC=m -# CONFIG_IEEE80211_SOFTMAC is not set -# CONFIG_IFB is not set -# CONFIG_IKCONFIG is not set -# CONFIG_INET_DIAG is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_INPUT=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_TSDEV=m -CONFIG_INPUT_TSDEV_SCREEN_X=480 -CONFIG_INPUT_TSDEV_SCREEN_Y=272 -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -# CONFIG_ISDN is not set -# CONFIG_ISO9660_FS is not set -CONFIG_IWMMXT=y -CONFIG_KEYBOARD_ATKBD=m -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_LLC2 is not set -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_MACH_LOGICPD_PXA270 is not set -# CONFIG_MACH_MAINSTONE is not set -# CONFIG_MACH_TRIZEPS4 is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MII=m -# CONFIG_MINIX_FS is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_PXA=y -CONFIG_MOUSE_PS2=m -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_I1=y -# CONFIG_MTD_CFI_I2 is not set -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_GUMSTIX=y -# CONFIG_MTD_JEDECPROBE is not set -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set -# CONFIG_MTD_ONENAND is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SHARP_SL is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_XIP is not set -# CONFIG_NETFILTER_XT_TARGET_TARPIT is not set -CONFIG_NET_SCH_FIFO=y -CONFIG_NO_IDLE_HZ=y -# CONFIG_NO_IOPORT is not set -# CONFIG_NVRAM is not set -# CONFIG_OUTER_CACHE is not set -# CONFIG_PACKET is not set -CONFIG_PATA_PCMCIA=m -# CONFIG_PATA_PLATFORM is not set -CONFIG_PCCARD=m -CONFIG_PCMCIA=m -CONFIG_PCMCIA_LOAD_CIS=y -CONFIG_PCMCIA_PXA2XX=m -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set -# CONFIG_PNPACPI is not set -CONFIG_PROC_GPIO=m -# CONFIG_PROC_GPIO_DEBUG is not set -CONFIG_PXA27x=y -# CONFIG_PXA_SHARPSL is not set -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_SA1100_WATCHDOG=m -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_PROC_FS is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_SERIO=m -CONFIG_SERIO_LIBPS2=m -# CONFIG_SERIO_RAW is not set -CONFIG_SERIO_SERPORT=m -# CONFIG_SHMEM is not set -CONFIG_SMC911X=m -CONFIG_SMC911X_GUMSTIX=m -CONFIG_SMC91X=m -CONFIG_SMC91X_GUMSTIX=m -CONFIG_SND_AC97_CODEC=m -CONFIG_SND_PXA2XX_AC97=m -CONFIG_SND_PXA2XX_PCM=m -CONFIG_SND_PXA2XX_SOC=m -CONFIG_SND_PXA2XX_SOC_AC97=m -CONFIG_SND_PXA2XX_SOC_GUMSTIX=m -CONFIG_SND_SOC=m -CONFIG_SND_SOC_AC97_BUS=y -CONFIG_SND_SOC_AC97_CODEC=m -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_SWAP is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TINY_SHMEM=y -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -CONFIG_TOUCHSCREEN_UCB1400=m -# CONFIG_TUN is not set -# CONFIG_UDF_FS is not set -CONFIG_UID16=y -CONFIG_UNIX=m -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_USBPCWATCHDOG is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_GTCO is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_HCD=m -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_USBNET is not set -# CONFIG_USB_USBNET_MII is not set -# CONFIG_USB_YEALINK is not set -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VGA_CONSOLE is not set -# CONFIG_VIDEO_DEV is not set -# CONFIG_VLAN_8021Q is not set -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFS_FS is not set -# CONFIG_XIP_KERNEL is not set -CONFIG_XSCALE_PMU=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/pxa/image/Makefile b/target/linux/pxa/image/Makefile deleted file mode 100644 index 64330b0260..0000000000 --- a/target/linux/pxa/image/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Image/Prepare - cp $(LINUX_DIR)/arch/arm/boot/uImage $(KDIR)/uImage -endef - -define Image/BuildKernel - cp $(KDIR)/uImage $(BIN_DIR)/openwrt-$(BOARD)-uImage -endef - -define Image/Build - $(call Image/Build/$(1),$(1)) -endef - -define Image/Build/jffs2-64k - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=65536 conv=sync -endef - -define Image/Build/jffs2-128k - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync -endef - -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/pxa/patches-2.6.21/001-pxa-regs-additions.patch b/target/linux/pxa/patches-2.6.21/001-pxa-regs-additions.patch deleted file mode 100644 index f8361f41b8..0000000000 --- a/target/linux/pxa/patches-2.6.21/001-pxa-regs-additions.patch +++ /dev/null @@ -1,28 +0,0 @@ -Index: linux-2.6.21.7/include/asm-arm/arch-pxa/pxa-regs.h -=================================================================== ---- linux-2.6.21.7.orig/include/asm-arm/arch-pxa/pxa-regs.h -+++ linux-2.6.21.7/include/asm-arm/arch-pxa/pxa-regs.h -@@ -1316,6 +1316,7 @@ - #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ - #define GPIO78_nCS_2 78 /* chip select 2 */ - #define GPIO79_nCS_3 79 /* chip select 3 */ -+#define GPIO79_pSKTSEL 79 /* Socket Select for Card Space (PXA27x) */ - #define GPIO80_nCS_4 80 /* chip select 4 */ - #define GPIO81_NSCLK 81 /* NSSP clock */ - #define GPIO82_NSFRM 82 /* NSSP Frame */ -@@ -1324,6 +1325,7 @@ - #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ - #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ - #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ -+#define GPIO105_nPCE_2 105 /* Card Enable for Card Space (PXA27x) */ - #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ - #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ - #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ -@@ -1468,6 +1470,7 @@ - #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) - #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) - #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) -+#define GPIO105_nPCE_2_MD (105 | GPIO_ALT_FN_1_OUT) - #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) - #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) - #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) diff --git a/target/linux/pxa/patches-2.6.21/002-header.patch b/target/linux/pxa/patches-2.6.21/002-header.patch deleted file mode 100644 index 471692517f..0000000000 --- a/target/linux/pxa/patches-2.6.21/002-header.patch +++ /dev/null @@ -1,170 +0,0 @@ -Index: linux-2.6.21.7/include/asm-arm/arch-pxa/gumstix.h -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/include/asm-arm/arch-pxa/gumstix.h -@@ -0,0 +1,165 @@ -+/* -+ * linux/include/asm-arm/arch-pxa/gumstix.h -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+ -+/* BTRESET - Reset line to Bluetooth module, active low signal. */ -+#define GPIO_GUMSTIX_BTRESET 7 -+#define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT) -+ -+ -+/* GPIOn - Input from MAX823 (or equiv), normalizing USB +5V -+ into a clean interrupt signal for determining cable presence -+ On the original gumstix, this is GPIO81, and GPIO83 needs to be defined as well. -+ On the gumstix F, this moves to GPIO17 and GPIO37 */ -+/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn -+ has detected a cable insertion; driven low otherwise. */ -+ -+#ifdef CONFIG_ARCH_GUMSTIX_ORIG -+ -+#define GPIO_GUMSTIX_USB_GPIOn 81 -+#define GPIO_GUMSTIX_USB_GPIOx 83 -+ -+#else -+ -+#define GPIO_GUMSTIX_USB_GPIOn 35 -+#define GPIO_GUMSTIX_USB_GPIOx 41 -+ -+#endif -+ -+#define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn) /* usb state change */ -+#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN) -+#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT) -+#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN) -+ -+ -+/* -+ * SMC Ethernet definitions -+ * ETH_RST provides a hardware reset line to the ethernet chip -+ * ETH is the IRQ line in from the ethernet chip to the PXA -+ */ -+#ifndef CONFIG_ARCH_GUMSTIX_VERDEX -+#define GPIO_GUMSTIX_ETH0_RST 80 -+#define GPIO_GUMSTIX_ETH0 36 -+#else -+#define GPIO_GUMSTIX_ETH0_RST 32 -+#define GPIO_GUMSTIX_ETH0 99 -+#endif -+#define GPIO_GUMSTIX_ETH1_RST 52 -+#define GPIO_GUMSTIX_ETH1 27 -+ -+#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT) -+#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT) -+#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) -+#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) -+ -+#define GUMSTIX_ETH0_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH0) -+#define GUMSTIX_ETH1_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH1) -+ -+ -+/* CF reset line */ -+#define GPIO8_CF_RESET 8 -+#define GPIO97_CF_RESET 97 -+#define GPIO110_CF_RESET 110 -+#ifndef CONFIG_ARCH_GUMSTIX_VERDEX -+#define GPIO_GUMSTIX_CF_RESET GPIO8_CF_RESET -+#else -+#define GPIO_GUMSTIX_CF_RESET GPIO97_CF_RESET -+#endif -+#define GPIO_GUMSTIX_CF_OLD_RESET GPIO110_CF_RESET -+ -+ -+/* CF signals shared by both sockets */ -+#define GPIO_GUMSTIX_nPOE GPIO48_nPOE -+#define GPIO_GUMSTIX_nPWE GPIO49_nPWE -+#define GPIO_GUMSTIX_nPIOR GPIO50_nPIOR -+#define GPIO_GUMSTIX_nPIOW GPIO51_nPIOW -+#ifndef CONFIG_ARCH_GUMSTIX_VERDEX -+#define GPIO_GUMSTIX_nPCE_1 GPIO52_nPCE_1 -+#define GPIO_GUMSTIX_nPCE_2 GPIO53_nPCE_2 -+#define GPIO_GUMSTIX_pSKTSEL GPIO54_pSKTSEL -+#else -+#define GPIO_GUMSTIX_nPCE_1 GPIO102_nPCE_1 -+#define GPIO_GUMSTIX_nPCE_2 GPIO105_nPCE_2 -+#define GPIO_GUMSTIX_pSKTSEL GPIO79_pSKTSEL -+#endif -+#define GPIO_GUMSTIX_nPREG GPIO55_nPREG -+#define GPIO_GUMSTIX_nPWAIT GPIO56_nPWAIT -+#define GPIO_GUMSTIX_nIOIS16 GPIO57_nIOIS16 -+ -+#define GPIO_GUMSTIX_nPOE_MD GPIO48_nPOE_MD -+#define GPIO_GUMSTIX_nPWE_MD GPIO49_nPWE_MD -+#define GPIO_GUMSTIX_nPIOR_MD GPIO50_nPIOR_MD -+#define GPIO_GUMSTIX_nPIOW_MD GPIO51_nPIOW_MD -+#ifndef CONFIG_ARCH_GUMSTIX_VERDEX -+#define GPIO_GUMSTIX_nPCE_1_MD GPIO52_nPCE_1_MD -+#define GPIO_GUMSTIX_nPCE_2_MD GPIO53_nPCE_2_MD -+#define GPIO_GUMSTIX_pSKTSEL_MD GPIO54_pSKTSEL_MD -+#else -+#define GPIO_GUMSTIX_nPCE_1_MD GPIO102_nPCE_1_MD -+#define GPIO_GUMSTIX_nPCE_2_MD GPIO105_nPCE_2_MD -+#define GPIO_GUMSTIX_pSKTSEL_MD GPIO79_pSKTSEL_MD -+#endif -+#define GPIO_GUMSTIX_nPREG_MD GPIO55_nPREG_MD -+#define GPIO_GUMSTIX_nPWAIT_MD GPIO56_nPWAIT_MD -+#define GPIO_GUMSTIX_nIOIS16_MD GPIO57_nIOIS16_MD -+ -+/* CF slot 0 */ -+#define GPIO4_nBVD1_0 4 -+#define GPIO4_nSTSCHG_0 GPIO4_nBVD1_0 -+#define GPIO11_nCD_0 11 -+#define GPIO26_PRDY_nBSY_0 26 -+ -+#define GPIO111_nBVD1_0 111 -+#define GPIO111_nSTSCHG_0 GPIO111_nBVD1_0 -+#define GPIO104_nCD_0 104 -+#define GPIO96_PRDY_nBSY_0 96 -+#define GPIO109_PRDY_nBSY_0 109 -+ -+#ifndef CONFIG_ARCH_GUMSTIX_VERDEX -+#define GPIO_GUMSTIX_nBVD1_0 GPIO4_nBVD1_0 -+#define GPIO_GUMSTIX_nSTSCHG_0 GPIO4_nSTSCHG_0 -+#define GPIO_GUMSTIX_nCD_0 GPIO11_nCD_0 -+#define GPIO_GUMSTIX_PRDY_nBSY_0 GPIO26_PRDY_nBSY_0 -+#else -+#define GPIO_GUMSTIX_nBVD1_0 GPIO111_nBVD1_0 -+#define GPIO_GUMSTIX_nSTSCHG_0 GPIO111_nSTSCHG_0 -+#define GPIO_GUMSTIX_nCD_0 GPIO104_nCD_0 -+#define GPIO_GUMSTIX_PRDY_nBSY_0 GPIO96_PRDY_nBSY_0 -+#endif -+#define GPIO_GUMSTIX_PRDY_nBSY_0_OLD GPIO109_PRDY_nBSY_0 -+ -+#define GUMSTIX_S0_nSTSCHG_IRQ IRQ_GPIO(GPIO_GUMSTIX_nSTSCHG_0) -+#define GUMSTIX_S0_nCD_IRQ IRQ_GPIO(GPIO_GUMSTIX_nCD_0) -+#define GUMSTIX_S0_PRDY_nBSY_IRQ IRQ_GPIO(GPIO_GUMSTIX_PRDY_nBSY_0) -+#define GUMSTIX_S0_PRDY_nBSY_OLD_IRQ IRQ_GPIO(GPIO_GUMSTIX_PRDY_nBSY_0_OLD) -+ -+/* CF slot 1 */ -+#define GPIO18_nBVD1_1 18 -+#define GPIO18_nSTSCHG_1 GPIO18_nBVD1_1 -+#define GPIO36_nCD_1 36 -+#define GPIO27_PRDY_nBSY_1 27 -+ -+#define GPIO_GUMSTIX_nBVD1_1 GPIO18_nBVD1_1 -+#define GPIO_GUMSTIX_nSTSCHG_1 GPIO18_nSTSCHG_1 -+#define GPIO_GUMSTIX_nCD_1 GPIO36_nCD_1 -+#define GPIO_GUMSTIX_PRDY_nBSY_1 GPIO27_PRDY_nBSY_1 -+ -+#define GUMSTIX_S1_nSTSCHG_IRQ IRQ_GPIO(GPIO_GUMSTIX_nSTSCHG_1) -+#define GUMSTIX_S1_nCD_IRQ IRQ_GPIO(GPIO_GUMSTIX_nCD_1) -+#define GUMSTIX_S1_PRDY_nBSY_IRQ IRQ_GPIO(GPIO_GUMSTIX_PRDY_nBSY_1) -+ -+/* CF GPIO line modes */ -+#define GPIO_GUMSTIX_CF_RESET_MD ( GPIO_GUMSTIX_CF_RESET | GPIO_OUT ) -+#define GPIO_GUMSTIX_CF_OLD_RESET_MD ( GPIO_GUMSTIX_CF_OLD_RESET | GPIO_OUT ) -+#define GPIO_GUMSTIX_nSTSCHG_0_MD ( GPIO_GUMSTIX_nSTSCHG_0 | GPIO_IN ) -+#define GPIO_GUMSTIX_nCD_0_MD ( GPIO_GUMSTIX_nCD_0 | GPIO_IN ) -+#define GPIO_GUMSTIX_PRDY_nBSY_0_MD ( GPIO_GUMSTIX_PRDY_nBSY_0 | GPIO_IN ) -+#define GPIO_GUMSTIX_PRDY_nBSY_0_OLD_MD ( GPIO_GUMSTIX_PRDY_nBSY_0_OLD | GPIO_IN ) -+#define GPIO_GUMSTIX_nSTSCHG_1_MD ( GPIO_GUMSTIX_nSTSCHG_1 | GPIO_IN ) -+#define GPIO_GUMSTIX_nCD_1_MD ( GPIO_GUMSTIX_nCD_1 | GPIO_IN ) -+#define GPIO_GUMSTIX_PRDY_nBSY_1_MD ( GPIO_GUMSTIX_PRDY_nBSY_1 | GPIO_IN ) diff --git a/target/linux/pxa/patches-2.6.21/003-arch-config.patch b/target/linux/pxa/patches-2.6.21/003-arch-config.patch deleted file mode 100644 index 9b203d3a89..0000000000 --- a/target/linux/pxa/patches-2.6.21/003-arch-config.patch +++ /dev/null @@ -1,62 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/mach-pxa/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/Kconfig -+++ linux-2.6.21.7/arch/arm/mach-pxa/Kconfig -@@ -5,6 +5,10 @@ menu "Intel PXA2xx Implementations" - choice - prompt "Select target board" - -+config ARCH_GUMSTIX -+ bool "Gumstix Platform" -+ depends on ARCH_PXA -+ - config ARCH_LUBBOCK - bool "Intel DBPXA250 Development Platform" - select PXA25x -@@ -116,6 +120,34 @@ config MACH_TOSA - bool "Enable Sharp SL-6000x (Tosa) Support" - depends on PXA_SHARPSL_25x - -+choice -+ depends on ARCH_GUMSTIX -+ prompt "Gumstix Platform Version" -+ default ARCH_GUMSTIX_F -+ -+config ARCH_GUMSTIX_ORIG -+ bool "Original Gumstix" -+ select PXA25x -+ help -+ The original gumstix platform, including the gs-200x and gs-400x and the waysmall -+ systems using these boards. (Almost nobody has one of these) -+ -+config ARCH_GUMSTIX_F -+ bool "Gumstix-F" -+ select PXA25x -+ help -+ The updated Gumstix basix and connex boards with 60-pin connector, and -+ waysmall systems using these boards, including ws-200ax and ws-400ax. -+ -+config ARCH_GUMSTIX_VERDEX -+ bool "Gumstix Verdex" -+ select PXA27x -+ help -+ The Gumstix verdex boards with 24, 60, and 120-pin connectors, and -+ computer systems using these boards. -+ -+endchoice -+ - config PXA25x - bool - help -Index: linux-2.6.21.7/arch/arm/mach-pxa/Makefile -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/Makefile -+++ linux-2.6.21.7/arch/arm/mach-pxa/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_PXA25x) += pxa25x.o - obj-$(CONFIG_PXA27x) += pxa27x.o - - # Specific board support -+obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o - obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o - obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o - obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o diff --git a/target/linux/pxa/patches-2.6.21/004-board-init.patch b/target/linux/pxa/patches-2.6.21/004-board-init.patch deleted file mode 100644 index d96c9811a8..0000000000 --- a/target/linux/pxa/patches-2.6.21/004-board-init.patch +++ /dev/null @@ -1,81 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -@@ -0,0 +1,76 @@ -+/* -+ * linux/arch/arm/mach-pxa/gumstix.c -+ * -+ * Support for the Gumstix computer platform -+ * -+ * Author: Craig Hughes -+ * Created: December 8 2004 -+ * Copyright: (C) 2004, Craig Hughes -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "generic.h" -+ -+static int gumstix_mci_init(struct device *dev, irqreturn_t (*lubbock_detect_int)(int, void *, struct pt_regs *), void *data) -+{ -+ // Set up MMC controller -+ pxa_gpio_mode(GPIO6_MMCCLK_MD); -+ pxa_gpio_mode(GPIO53_MMCCLK_MD); -+ pxa_gpio_mode(GPIO8_MMCCS0_MD); -+ -+ return 0; -+} -+ -+static struct pxamci_platform_data gumstix_mci_platform_data = { -+ .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, -+ .init = &gumstix_mci_init, -+}; -+ -+static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = { -+ .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn, -+ .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx, -+}; -+ -+static struct platform_device gum_audio_device = { -+ .name = "pxa2xx-ac97", -+ .id = -1, -+}; -+ -+static struct platform_device *devices[] __initdata = { -+ &gum_audio_device, -+}; -+ -+static void __init gumstix_init(void) -+{ -+ pxa_set_mci_info(&gumstix_mci_platform_data); -+ pxa_set_udc_info(&gumstix_udc_info); -+ (void) platform_add_devices(devices, ARRAY_SIZE(devices)); -+} -+ -+MACHINE_START(GUMSTIX, "The Gumstix Platform") -+ .phys_io = 0x40000000, -+ .boot_params = 0xa0000100, -+ .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, -+ .timer = &pxa_timer, -+ .map_io = pxa_map_io, -+ .init_irq = pxa_init_irq, -+ .init_machine = gumstix_init, -+MACHINE_END diff --git a/target/linux/pxa/patches-2.6.21/005-compact-flash.patch b/target/linux/pxa/patches-2.6.21/005-compact-flash.patch deleted file mode 100644 index d866555f33..0000000000 --- a/target/linux/pxa/patches-2.6.21/005-compact-flash.patch +++ /dev/null @@ -1,287 +0,0 @@ -Index: linux-2.6.21.7/drivers/pcmcia/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/pcmcia/Makefile -+++ linux-2.6.21.7/drivers/pcmcia/Makefile -@@ -69,4 +69,4 @@ sa1100_cs-$(CONFIG_SA1100_SIMPAD) += sa - pxa2xx_cs-$(CONFIG_ARCH_LUBBOCK) += pxa2xx_lubbock.o sa1111_generic.o - pxa2xx_cs-$(CONFIG_MACH_MAINSTONE) += pxa2xx_mainstone.o - pxa2xx_cs-$(CONFIG_PXA_SHARPSL) += pxa2xx_sharpsl.o -- -+pxa2xx_cs-$(CONFIG_ARCH_GUMSTIX) += pxa2xx_gumstix.o -Index: linux-2.6.21.7/drivers/pcmcia/pxa2xx_gumstix.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/drivers/pcmcia/pxa2xx_gumstix.c -@@ -0,0 +1,272 @@ -+/* -+ * linux/drivers/pcmcia/pxa2xx_gumstix.c -+ * -+ * Gumstix PCMCIA specific routines. Based on Mainstone -+ * -+ * Copyright 2004, Craig Hughes -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "soc_common.h" -+ -+static struct pcmcia_irqs gumstix_pcmcia_irqs0[] = { -+ { 0, GUMSTIX_S0_nCD_IRQ, "CF0 nCD" }, -+ { 0, GUMSTIX_S0_nSTSCHG_IRQ, "CF0 nSTSCHG" }, -+}; -+ -+static struct pcmcia_irqs gumstix_pcmcia_irqs1[] = { -+ { 1, GUMSTIX_S1_nCD_IRQ, "CF1 nCD" }, -+ { 1, GUMSTIX_S1_nSTSCHG_IRQ, "CF1 nSTSCHG" }, -+}; -+ -+static int net_cf_vx_mode = 0; -+ -+static int gumstix_pcmcia_hw_init(struct soc_pcmcia_socket *skt) -+{ -+ if(skt->nr == 0) -+ { -+ pxa_gpio_mode(GPIO_GUMSTIX_nSTSCHG_0_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nCD_0_MD); -+ if(net_cf_vx_mode) -+ pxa_gpio_mode(GPIO_GUMSTIX_PRDY_nBSY_0_OLD_MD); -+ else -+ pxa_gpio_mode(GPIO_GUMSTIX_PRDY_nBSY_0_MD); -+ } else { -+ pxa_gpio_mode(GPIO_GUMSTIX_nSTSCHG_1_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nCD_1_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_PRDY_nBSY_1_MD); -+ } -+ -+ pxa_gpio_mode(GPIO_GUMSTIX_nPOE_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nPWE_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nPIOR_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nPIOW_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nPCE_1_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nPCE_2_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_pSKTSEL_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nPREG_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nPWAIT_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_nIOIS16_MD); -+ -+ skt->irq = (skt->nr == 0) ? ((net_cf_vx_mode == 0) ? GUMSTIX_S0_PRDY_nBSY_IRQ : GUMSTIX_S0_PRDY_nBSY_OLD_IRQ) : GUMSTIX_S1_PRDY_nBSY_IRQ; -+ -+ return (skt->nr == 0) ? soc_pcmcia_request_irqs(skt, gumstix_pcmcia_irqs0, ARRAY_SIZE(gumstix_pcmcia_irqs0)) : -+ soc_pcmcia_request_irqs(skt, gumstix_pcmcia_irqs1, ARRAY_SIZE(gumstix_pcmcia_irqs1)); -+} -+ -+static void gumstix_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) -+{ -+ if(skt->nr == 0) -+ { -+ soc_pcmcia_free_irqs(skt, gumstix_pcmcia_irqs0, ARRAY_SIZE(gumstix_pcmcia_irqs0)); -+ } else { -+ soc_pcmcia_free_irqs(skt, gumstix_pcmcia_irqs1, ARRAY_SIZE(gumstix_pcmcia_irqs1)); -+ } -+} -+ -+static void gumstix_pcmcia_socket_state(struct soc_pcmcia_socket *skt, -+ struct pcmcia_state *state) -+{ -+ unsigned int cd, prdy_nbsy, nbvd1; -+ if(skt->nr == 0) -+ { -+ cd = GPIO_GUMSTIX_nCD_0; -+ if(net_cf_vx_mode) -+ prdy_nbsy = GPIO_GUMSTIX_PRDY_nBSY_0_OLD; -+ else -+ prdy_nbsy = GPIO_GUMSTIX_PRDY_nBSY_0; -+ nbvd1 = GPIO_GUMSTIX_nBVD1_0; -+ } else { -+ cd = GPIO_GUMSTIX_nCD_1; -+ prdy_nbsy = GPIO_GUMSTIX_PRDY_nBSY_1; -+ nbvd1 = GPIO_GUMSTIX_nBVD1_1; -+ } -+ state->detect = !(GPLR(cd) & GPIO_bit(cd)); -+ state->ready = !!(GPLR(prdy_nbsy) & GPIO_bit(prdy_nbsy)); -+ state->bvd1 = !!(GPLR(nbvd1) & GPIO_bit(nbvd1)); -+ state->bvd2 = 1; -+ state->vs_3v = 0; -+ state->vs_Xv = 0; -+ state->wrprot = 0; -+} -+ -+static int gumstix_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, -+ const socket_state_t *state) -+{ -+ return 0; -+} -+ -+static void gumstix_pcmcia_socket_init(struct soc_pcmcia_socket *skt) -+{ -+ if(skt->nr) { -+ soc_pcmcia_enable_irqs(skt, gumstix_pcmcia_irqs0, ARRAY_SIZE(gumstix_pcmcia_irqs0)); -+ } else { -+ soc_pcmcia_enable_irqs(skt, gumstix_pcmcia_irqs1, ARRAY_SIZE(gumstix_pcmcia_irqs1)); -+ } -+} -+ -+static void gumstix_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) -+{ -+ if(skt->nr) { -+ soc_pcmcia_disable_irqs(skt, gumstix_pcmcia_irqs0, ARRAY_SIZE(gumstix_pcmcia_irqs0)); -+ } else { -+ soc_pcmcia_disable_irqs(skt, gumstix_pcmcia_irqs1, ARRAY_SIZE(gumstix_pcmcia_irqs1)); -+ } -+} -+ -+static struct pcmcia_low_level gumstix_pcmcia_ops = { -+ .owner = THIS_MODULE, -+ .hw_init = gumstix_pcmcia_hw_init, -+ .hw_shutdown = gumstix_pcmcia_hw_shutdown, -+ .socket_state = gumstix_pcmcia_socket_state, -+ .configure_socket = gumstix_pcmcia_configure_socket, -+ .socket_init = gumstix_pcmcia_socket_init, -+ .socket_suspend = gumstix_pcmcia_socket_suspend, -+ .nr = 2, -+}; -+ -+static struct platform_device *gumstix_pcmcia_device; -+ -+inline void __init gumstix_pcmcia_cpld_clk(void) -+{ -+ GPCR(GPIO_GUMSTIX_nPOE) = GPIO_bit(GPIO_GUMSTIX_nPOE); -+ GPSR(GPIO_GUMSTIX_nPOE) = GPIO_bit(GPIO_GUMSTIX_nPOE); -+} -+ -+inline unsigned char __init gumstix_pcmcia_cpld_read_bits(int bits) -+{ -+ unsigned char result = 0; -+ unsigned int shift = 0; -+ while(bits--) -+ { -+ result |= !!(GPLR(GPIO_GUMSTIX_nCD_0) & GPIO_bit(GPIO_GUMSTIX_nCD_0)) << shift; -+ shift ++; -+ gumstix_pcmcia_cpld_clk(); -+ } -+ printk("CPLD responded with: %02x\n",result); -+ return result; -+} -+ -+/* We use the CPLD on the CF-CF card to read a value from a shift register. If we can read that -+ * magic sequence, then we have 2 CF cards; otherwise we assume just one -+ * The CPLD will send the value of the shift register on GPIO11 (the CD line for slot 0) -+ * when RESET is held in reset. We use GPIO48 (nPOE) as a clock signal, -+ * GPIO52/53 (card enable for both cards) to control read/write to the shift register -+ */ -+static void __init gumstix_count_cards(void) -+{ -+ pxa_gpio_mode(GPIO_GUMSTIX_nPOE | GPIO_OUT); -+ pxa_gpio_mode(GPIO_GUMSTIX_nPCE_1 | GPIO_OUT); -+ pxa_gpio_mode(GPIO_GUMSTIX_nPCE_2 | GPIO_OUT); -+ pxa_gpio_mode(GPIO_GUMSTIX_nCD_0 | GPIO_IN); -+ if(net_cf_vx_mode) -+ pxa_gpio_mode(GPIO_GUMSTIX_CF_OLD_RESET | GPIO_OUT); -+ else -+ pxa_gpio_mode(GPIO_GUMSTIX_CF_RESET | GPIO_OUT); -+ -+ // Enter reset -+ if(net_cf_vx_mode) -+ GPSR(GPIO_GUMSTIX_CF_OLD_RESET) = GPIO_bit(GPIO_GUMSTIX_CF_OLD_RESET); -+ else -+ GPSR(GPIO_GUMSTIX_CF_RESET) = GPIO_bit(GPIO_GUMSTIX_CF_RESET); -+ -+ // Setup the shift register -+ GPSR(GPIO_GUMSTIX_nPCE_1) = GPIO_bit(GPIO_GUMSTIX_nPCE_1); -+ GPCR(GPIO_GUMSTIX_nPCE_2) = GPIO_bit(GPIO_GUMSTIX_nPCE_2); -+ -+ // Tick the clock to program the shift register -+ gumstix_pcmcia_cpld_clk(); -+ -+ // Now set shift register into read mode -+ GPCR(GPIO_GUMSTIX_nPCE_1) = GPIO_bit(GPIO_GUMSTIX_nPCE_1); -+ GPSR(GPIO_GUMSTIX_nPCE_2) = GPIO_bit(GPIO_GUMSTIX_nPCE_2); -+ -+ // We can read the bits now -- 0xC2 means "Dual compact flash" -+ if(gumstix_pcmcia_cpld_read_bits(8) != 0xC2) -+ { -+ // We do not have 2 CF slots -+ gumstix_pcmcia_ops.nr = 1; -+ } -+} -+ -+#ifdef CONFIG_ARCH_GUMSTIX_VERDEX -+static void __init gumstix_check_if_netCF_vx(void) -+{ -+ void *network_controller_memory = ioremap(0x04000300,16); -+ // Look for the special 91c111 value in the bank select register -+ if((0xff00 & readw(network_controller_memory+0x0e)) == 0x3300) { -+ printk("Detected netCF-vx board: using older GPIO configuration\n"); -+ net_cf_vx_mode = 1; -+ } else { -+ printk("Not netCF-vx board: using newer GPIO configuration\n"); -+ net_cf_vx_mode = 0; -+ } -+ iounmap(network_controller_memory); -+} -+#endif -+ -+static int __init gumstix_pcmcia_init(void) -+{ -+ int ret; -+ -+#ifdef CONFIG_ARCH_GUMSTIX_VERDEX -+ gumstix_check_if_netCF_vx(); -+#endif -+ -+ gumstix_count_cards(); -+ -+ udelay(50); -+ if(net_cf_vx_mode) -+ GPCR(GPIO_GUMSTIX_CF_OLD_RESET) = GPIO_bit(GPIO_GUMSTIX_CF_OLD_RESET); -+ else -+ GPCR(GPIO_GUMSTIX_CF_RESET) = GPIO_bit(GPIO_GUMSTIX_CF_RESET); -+ -+ gumstix_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); -+ if (!gumstix_pcmcia_device) -+ return -ENOMEM; -+ -+ gumstix_pcmcia_device->dev.platform_data = &gumstix_pcmcia_ops; -+ -+ ret = platform_device_add(gumstix_pcmcia_device); -+ if (ret) -+ platform_device_put(gumstix_pcmcia_device); -+ -+ return ret; -+} -+ -+static void __exit gumstix_pcmcia_exit(void) -+{ -+ /* -+ * This call is supposed to free our gumstix_pcmcia_device. -+ * Unfortunately platform_device don't have a free method, and -+ * we can't assume it's free of any reference at this point so we -+ * can't free it either. -+ */ -+ platform_device_unregister(gumstix_pcmcia_device); -+} -+ -+fs_initcall(gumstix_pcmcia_init); -+module_exit(gumstix_pcmcia_exit); -+ -+MODULE_LICENSE("GPL"); diff --git a/target/linux/pxa/patches-2.6.21/006-defconfig.patch b/target/linux/pxa/patches-2.6.21/006-defconfig.patch deleted file mode 100644 index 3d9dc5cfc3..0000000000 --- a/target/linux/pxa/patches-2.6.21/006-defconfig.patch +++ /dev/null @@ -1,766 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/configs/gumstix_defconfig -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/arch/arm/configs/gumstix_defconfig -@@ -0,0 +1,761 @@ -+# -+# Automatically generated make config: don't edit -+# -+CONFIG_ARM=y -+CONFIG_MMU=y -+CONFIG_UID16=y -+CONFIG_RWSEM_GENERIC_SPINLOCK=y -+ -+# -+# Code maturity level options -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_CLEAN_COMPILE=y -+CONFIG_BROKEN_ON_SMP=y -+ -+# -+# General setup -+# -+# CONFIG_SWAP is not set -+CONFIG_SYSVIPC=y -+# CONFIG_POSIX_MQUEUE is not set -+# CONFIG_BSD_PROCESS_ACCT is not set -+# CONFIG_SYSCTL is not set -+# CONFIG_AUDIT is not set -+CONFIG_LOG_BUF_SHIFT=14 -+CONFIG_HOTPLUG=y -+# CONFIG_IKCONFIG is not set -+CONFIG_EMBEDDED=y -+# CONFIG_KALLSYMS is not set -+# CONFIG_FUTEX is not set -+# CONFIG_EPOLL is not set -+CONFIG_IOSCHED_NOOP=y -+# CONFIG_IOSCHED_AS is not set -+# CONFIG_IOSCHED_DEADLINE is not set -+# CONFIG_IOSCHED_CFQ is not set -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+ -+# -+# Loadable module support -+# -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_MODULE_FORCE_UNLOAD is not set -+CONFIG_OBSOLETE_MODPARM=y -+# CONFIG_MODVERSIONS is not set -+CONFIG_KMOD=y -+ -+# -+# System Type -+# -+# CONFIG_ARCH_CLPS7500 is not set -+# CONFIG_ARCH_CLPS711X is not set -+# CONFIG_ARCH_CO285 is not set -+# CONFIG_ARCH_EBSA110 is not set -+# CONFIG_ARCH_CAMELOT is not set -+# CONFIG_ARCH_FOOTBRIDGE is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_IOP3XX is not set -+# CONFIG_ARCH_IXP4XX is not set -+# CONFIG_ARCH_L7200 is not set -+CONFIG_ARCH_PXA=y -+# CONFIG_ARCH_RPC is not set -+# CONFIG_ARCH_SA1100 is not set -+# CONFIG_ARCH_S3C2410 is not set -+# CONFIG_ARCH_SHARK is not set -+# CONFIG_ARCH_LH7A40X is not set -+# CONFIG_ARCH_OMAP is not set -+# CONFIG_ARCH_VERSATILE_PB is not set -+# CONFIG_ARCH_IMX is not set -+ -+# -+# Intel PXA2xx Implementations -+# -+CONFIG_ARCH_GUMSTIX=y -+# CONFIG_ARCH_LUBBOCK is not set -+# CONFIG_MACH_MAINSTONE is not set -+# CONFIG_ARCH_PXA_IDP is not set -+# CONFIG_ARCH_GUMSTIX_ORIG is not set -+CONFIG_ARCH_GUMSTIX_F=y -+CONFIG_PXA25x=y -+ -+# -+# Processor Type -+# -+CONFIG_CPU_32=y -+CONFIG_CPU_XSCALE=y -+CONFIG_CPU_32v5=y -+CONFIG_CPU_ABRT_EV5T=y -+CONFIG_CPU_TLB_V4WBI=y -+CONFIG_CPU_MINICACHE=y -+ -+# -+# Processor Features -+# -+# CONFIG_ARM_THUMB is not set -+CONFIG_XSCALE_PMU=y -+ -+# -+# General setup -+# -+# CONFIG_ZBOOT_ROM is not set -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_TABLE=y -+CONFIG_CPU_FREQ_PXA=y -+# CONFIG_CPU_FREQ_PROC_INTF is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=m -+CONFIG_CPU_FREQ_GOV_POWERSAVE=m -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_PROC_GPIO=m -+ -+# -+# PCMCIA/CardBus support -+# -+CONFIG_PCMCIA=m -+# CONFIG_PCMCIA_DEBUG is not set -+# CONFIG_TCIC is not set -+CONFIG_PCMCIA_PXA2XX=m -+ -+# -+# At least one math emulation must be selected -+# -+CONFIG_FPE_NWFPE=y -+# CONFIG_FPE_NWFPE_XP is not set -+# CONFIG_FPE_FASTFPE is not set -+# CONFIG_VFP is not set -+CONFIG_BINFMT_ELF=y -+# CONFIG_BINFMT_AOUT is not set -+# CONFIG_BINFMT_MISC is not set -+ -+# -+# Generic Driver Options -+# -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+# CONFIG_FW_LOADER is not set -+# CONFIG_PM is not set -+# CONFIG_PREEMPT is not set -+# CONFIG_ARTHUR is not set -+CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f02 rootfstype=jffs2 reboot=cold,hard" -+CONFIG_ALIGNMENT_TRAP=y -+ -+# -+# Parallel port support -+# -+# CONFIG_PARPORT is not set -+ -+# -+# Memory Technology Devices (MTD) -+# -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+CONFIG_MTD_PARTITIONS=y -+# CONFIG_MTD_CONCAT is not set -+# CONFIG_MTD_REDBOOT_PARTS is not set -+# CONFIG_MTD_CMDLINE_PARTS is not set -+# CONFIG_MTD_AFS_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLOCK=y -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+CONFIG_MTD_CFI=y -+# CONFIG_MTD_JEDECPROBE is not set -+CONFIG_MTD_GEN_PROBE=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_NOSWAP=y -+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -+CONFIG_MTD_CFI_GEOMETRY=y -+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+# CONFIG_MTD_CFI_I2 is not set -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+CONFIG_MTD_CFI_INTELEXT=y -+# CONFIG_MTD_CFI_AMDSTD is not set -+# CONFIG_MTD_CFI_STAA is not set -+CONFIG_MTD_CFI_UTIL=y -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+ -+# -+# Mapping drivers for chip access -+# -+CONFIG_MTD_COMPLEX_MAPPINGS=y -+CONFIG_MTD_PHYSMAP=y -+CONFIG_MTD_PHYSMAP_START=0x00000000 -+CONFIG_MTD_PHYSMAP_LEN=0x00400000 -+CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -+CONFIG_MTD_GUMSTIX=y -+# CONFIG_MTD_ARM_INTEGRATOR is not set -+# CONFIG_MTD_EDB7312 is not set -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLKMTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+ -+# -+# NAND Flash Device Drivers -+# -+# CONFIG_MTD_NAND is not set -+ -+# -+# Plug and Play support -+# -+ -+# -+# Block devices -+# -+# CONFIG_BLK_DEV_FD is not set -+CONFIG_BLK_DEV_LOOP=m -+# CONFIG_BLK_DEV_CRYPTOLOOP is not set -+# CONFIG_BLK_DEV_NBD is not set -+# CONFIG_BLK_DEV_RAM is not set -+ -+# -+# Multi-device support (RAID and LVM) -+# -+# CONFIG_MD is not set -+ -+# -+# Networking support -+# -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=m -+CONFIG_PACKET_MMAP=y -+# CONFIG_NETLINK_DEV is not set -+CONFIG_UNIX=m -+# CONFIG_NET_KEY is not set -+CONFIG_INET=y -+# CONFIG_IP_MULTICAST is not set -+# CONFIG_IP_ADVANCED_ROUTER is not set -+# CONFIG_IP_PNP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_ARPD is not set -+# CONFIG_SYN_COOKIES is not set -+# CONFIG_INET_AH is not set -+# CONFIG_INET_ESP is not set -+# CONFIG_INET_IPCOMP is not set -+# CONFIG_INET_TUNNEL is not set -+# CONFIG_IPV6 is not set -+# CONFIG_NETFILTER is not set -+ -+# -+# SCTP Configuration (EXPERIMENTAL) -+# -+# CONFIG_IP_SCTP is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_NET_DIVERT is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+# CONFIG_NET_HW_FLOWCONTROL is not set -+ -+# -+# QoS and/or fair queueing -+# -+# CONFIG_NET_SCHED is not set -+# CONFIG_NET_CLS_ROUTE is not set -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_NETPOLL is not set -+# CONFIG_NET_POLL_CONTROLLER is not set -+# CONFIG_HAMRADIO is not set -+# CONFIG_IRDA is not set -+CONFIG_BT=m -+CONFIG_BT_GUMSTIX=m -+CONFIG_BT_L2CAP=m -+CONFIG_BT_SCO=m -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+ -+# -+# Bluetooth device drivers -+# -+CONFIG_BT_HCIUART=m -+CONFIG_BT_HCIUART_H4=y -+# CONFIG_BT_HCIUART_BCSP is not set -+# CONFIG_BT_HCIDTL1 is not set -+# CONFIG_BT_HCIBT3C is not set -+# CONFIG_BT_HCIBLUECARD is not set -+# CONFIG_BT_HCIBTUART is not set -+CONFIG_BT_HCIVHCI=m -+CONFIG_NETDEVICES=y -+# CONFIG_DUMMY is not set -+# CONFIG_BONDING is not set -+# CONFIG_EQUALIZER is not set -+# CONFIG_TUN is not set -+ -+# -+# Ethernet (10 or 100Mbit) -+# -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=m -+CONFIG_SMC91X=m -+CONFIG_SMC91X_GUMSTIX=m -+ -+# -+# Ethernet (1000 Mbit) -+# -+ -+# -+# Ethernet (10000 Mbit) -+# -+ -+# -+# Token Ring devices -+# -+ -+# -+# Wireless LAN (non-hamradio) -+# -+# CONFIG_NET_RADIO is not set -+ -+# -+# PCMCIA network device support -+# -+# CONFIG_NET_PCMCIA is not set -+ -+# -+# Wan interfaces -+# -+# CONFIG_WAN is not set -+# CONFIG_PPP is not set -+# CONFIG_SLIP is not set -+# CONFIG_SHAPER is not set -+# CONFIG_NETCONSOLE is not set -+ -+# -+# ATA/ATAPI/MFM/RLL support -+# -+CONFIG_IDE=m -+CONFIG_BLK_DEV_IDE=m -+ -+# -+# Please see Documentation/ide.txt for help/info on IDE drives -+# -+# CONFIG_BLK_DEV_IDE_SATA is not set -+# CONFIG_BLK_DEV_IDEDISK is not set -+CONFIG_BLK_DEV_IDECS=m -+# CONFIG_BLK_DEV_IDECD is not set -+# CONFIG_BLK_DEV_IDETAPE is not set -+# CONFIG_BLK_DEV_IDEFLOPPY is not set -+# CONFIG_IDE_TASK_IOCTL is not set -+# CONFIG_IDE_TASKFILE_IO is not set -+ -+# -+# IDE chipset support/bugfixes -+# -+CONFIG_IDE_GENERIC=m -+# CONFIG_IDE_ARM is not set -+# CONFIG_BLK_DEV_IDEDMA is not set -+# CONFIG_IDEDMA_AUTO is not set -+# CONFIG_BLK_DEV_HD is not set -+ -+# -+# SCSI device support -+# -+# CONFIG_SCSI is not set -+ -+# -+# Fusion MPT device support -+# -+ -+# -+# IEEE 1394 (FireWire) support -+# -+ -+# -+# I2O device support -+# -+ -+# -+# ISDN subsystem -+# -+# CONFIG_ISDN is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=m -+ -+# -+# Userland interfaces -+# -+# CONFIG_INPUT_MOUSEDEV is not set -+# CONFIG_INPUT_JOYDEV is not set -+# CONFIG_INPUT_TSDEV is not set -+# CONFIG_INPUT_EVDEV is not set -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input I/O drivers -+# -+# CONFIG_GAMEPORT is not set -+CONFIG_SOUND_GAMEPORT=y -+CONFIG_SERIO=y -+# CONFIG_SERIO_I8042 is not set -+# CONFIG_SERIO_SERPORT is not set -+# CONFIG_SERIO_CT82C710 is not set -+ -+# -+# Input Device Drivers -+# -+# CONFIG_INPUT_KEYBOARD is not set -+# CONFIG_INPUT_MOUSE is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+# CONFIG_INPUT_MISC is not set -+ -+# -+# Character devices -+# -+# CONFIG_VT is not set -+# CONFIG_SERIAL_NONSTANDARD is not set -+ -+# -+# Serial drivers -+# -+# CONFIG_SERIAL_8250 is not set -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_PXA=y -+CONFIG_SERIAL_PXA_CONSOLE=y -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+CONFIG_UNIX98_PTYS=y -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_QIC02_TAPE is not set -+ -+# -+# IPMI -+# -+# CONFIG_IPMI_HANDLER is not set -+ -+# -+# Watchdog Cards -+# -+CONFIG_WATCHDOG=y -+# CONFIG_WATCHDOG_NOWAYOUT is not set -+ -+# -+# Watchdog Device Drivers -+# -+# CONFIG_SOFT_WATCHDOG is not set -+CONFIG_SA1100_WATCHDOG=y -+# CONFIG_NVRAM is not set -+# CONFIG_RTC is not set -+# CONFIG_GEN_RTC is not set -+CONFIG_SA1100_RTC=m -+# CONFIG_DTLK is not set -+# CONFIG_R3964 is not set -+ -+# -+# Ftape, the floppy tape device driver -+# -+# CONFIG_AGP is not set -+# CONFIG_DRM is not set -+ -+# -+# PCMCIA character devices -+# -+# CONFIG_SYNCLINK_CS is not set -+# CONFIG_RAW_DRIVER is not set -+ -+# -+# I2C support -+# -+# CONFIG_I2C is not set -+ -+# -+# Multimedia devices -+# -+# CONFIG_VIDEO_DEV is not set -+ -+# -+# Digital Video Broadcasting Devices -+# -+# CONFIG_DVB is not set -+ -+# -+# File systems -+# -+# CONFIG_EXT2_FS is not set -+# CONFIG_EXT3_FS is not set -+# CONFIG_JBD is not set -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+# CONFIG_XFS_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_ROMFS_FS is not set -+# CONFIG_QUOTA is not set -+# CONFIG_AUTOFS_FS is not set -+# CONFIG_AUTOFS4_FS is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+# CONFIG_ISO9660_FS is not set -+# CONFIG_UDF_FS is not set -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=m -+CONFIG_MSDOS_FS=m -+CONFIG_VFAT_FS=m -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+# CONFIG_NTFS_FS is not set -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_SYSFS=y -+# CONFIG_DEVFS_FS is not set -+# CONFIG_DEVPTS_FS_XATTR is not set -+CONFIG_TMPFS=y -+# CONFIG_HUGETLB_PAGE is not set -+CONFIG_RAMFS=y -+ -+# -+# Miscellaneous filesystems -+# -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+# CONFIG_JFFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+# CONFIG_JFFS2_FS_NAND is not set -+CONFIG_JFFS2_COMPRESSION_OPTIONS=y -+CONFIG_JFFS2_ZLIB=y -+CONFIG_JFFS2_RTIME=y -+CONFIG_JFFS2_RUBIN=y -+# CONFIG_JFFS2_CMODE_NONE is not set -+# CONFIG_JFFS2_CMODE_PRIORITY is not set -+CONFIG_JFFS2_CMODE_SIZE=y -+# CONFIG_CRAMFS is not set -+# CONFIG_VXFS_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+ -+# -+# Network File Systems -+# -+CONFIG_NFS_FS=m -+CONFIG_NFS_V3=y -+# CONFIG_NFS_V4 is not set -+# CONFIG_NFS_DIRECTIO is not set -+# CONFIG_NFSD is not set -+CONFIG_LOCKD=m -+CONFIG_LOCKD_V4=y -+# CONFIG_EXPORTFS is not set -+CONFIG_SUNRPC=m -+# CONFIG_RPCSEC_GSS_KRB5 is not set -+# CONFIG_RPCSEC_GSS_SPKM3 is not set -+# CONFIG_SMB_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_NCP_FS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+# CONFIG_MAC_PARTITION is not set -+CONFIG_MSDOS_PARTITION=y -+# CONFIG_BSD_DISKLABEL is not set -+# CONFIG_MINIX_SUBPARTITION is not set -+# CONFIG_SOLARIS_X86_PARTITION is not set -+# CONFIG_UNIXWARE_DISKLABEL is not set -+# CONFIG_LDM_PARTITION is not set -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_SUN_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+ -+# -+# Native Language Support -+# -+CONFIG_NLS=m -+CONFIG_NLS_DEFAULT="iso8859-1" -+CONFIG_NLS_CODEPAGE_437=m -+# CONFIG_NLS_CODEPAGE_737 is not set -+# CONFIG_NLS_CODEPAGE_775 is not set -+# CONFIG_NLS_CODEPAGE_850 is not set -+# CONFIG_NLS_CODEPAGE_852 is not set -+# CONFIG_NLS_CODEPAGE_855 is not set -+# CONFIG_NLS_CODEPAGE_857 is not set -+# CONFIG_NLS_CODEPAGE_860 is not set -+# CONFIG_NLS_CODEPAGE_861 is not set -+# CONFIG_NLS_CODEPAGE_862 is not set -+# CONFIG_NLS_CODEPAGE_863 is not set -+# CONFIG_NLS_CODEPAGE_864 is not set -+# CONFIG_NLS_CODEPAGE_865 is not set -+# CONFIG_NLS_CODEPAGE_866 is not set -+# CONFIG_NLS_CODEPAGE_869 is not set -+# CONFIG_NLS_CODEPAGE_936 is not set -+# CONFIG_NLS_CODEPAGE_950 is not set -+# CONFIG_NLS_CODEPAGE_932 is not set -+# CONFIG_NLS_CODEPAGE_949 is not set -+# CONFIG_NLS_CODEPAGE_874 is not set -+# CONFIG_NLS_ISO8859_8 is not set -+# CONFIG_NLS_CODEPAGE_1250 is not set -+# CONFIG_NLS_CODEPAGE_1251 is not set -+# CONFIG_NLS_ASCII is not set -+CONFIG_NLS_ISO8859_1=m -+# CONFIG_NLS_ISO8859_2 is not set -+# CONFIG_NLS_ISO8859_3 is not set -+# CONFIG_NLS_ISO8859_4 is not set -+# CONFIG_NLS_ISO8859_5 is not set -+# CONFIG_NLS_ISO8859_6 is not set -+# CONFIG_NLS_ISO8859_7 is not set -+# CONFIG_NLS_ISO8859_9 is not set -+# CONFIG_NLS_ISO8859_13 is not set -+# CONFIG_NLS_ISO8859_14 is not set -+# CONFIG_NLS_ISO8859_15 is not set -+# CONFIG_NLS_KOI8_R is not set -+# CONFIG_NLS_KOI8_U is not set -+# CONFIG_NLS_UTF8 is not set -+ -+# -+# Profiling support -+# -+# CONFIG_PROFILING is not set -+ -+# -+# Graphics support -+# -+# CONFIG_FB is not set -+ -+# -+# Sound -+# -+# CONFIG_SOUND is not set -+ -+# -+# Misc devices -+# -+ -+# -+# USB support -+# -+ -+# -+# USB Gadget Support -+# -+CONFIG_USB_GADGET=m -+CONFIG_USB_GADGET_GUMSTIX=m -+# CONFIG_USB_GADGET_NET2280 is not set -+CONFIG_USB_GADGET_PXA2XX=y -+CONFIG_USB_PXA2XX=m -+# CONFIG_USB_PXA2XX_SMALL is not set -+# CONFIG_USB_GADGET_GOKU is not set -+# CONFIG_USB_GADGET_SA1100 is not set -+# CONFIG_USB_GADGET_DUMMY_HCD is not set -+# CONFIG_USB_GADGET_DUALSPEED is not set -+# CONFIG_USB_ZERO is not set -+CONFIG_USB_ETH=m -+CONFIG_USB_ETH_RNDIS=y -+# CONFIG_USB_GADGETFS is not set -+# CONFIG_USB_FILE_STORAGE is not set -+# CONFIG_USB_G_SERIAL is not set -+ -+# -+# MMC/SD Card support -+# -+CONFIG_MMC=m -+# CONFIG_MMC_DEBUG is not set -+CONFIG_MMC_BLOCK=m -+CONFIG_MMC_PXA=m -+ -+# -+# Kernel hacking -+# -+# CONFIG_DEBUG_KERNEL is not set -+# CONFIG_DEBUG_INFO is not set -+CONFIG_FRAME_POINTER=y -+# CONFIG_DEBUG_USER is not set -+ -+# -+# Security options -+# -+# CONFIG_SECURITY is not set -+ -+# -+# Cryptographic options -+# -+# CONFIG_CRYPTO is not set -+ -+# -+# Library routines -+# -+# CONFIG_CRC_CCITT is not set -+CONFIG_CRC32=y -+# CONFIG_LIBCRC32C is not set -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y diff --git a/target/linux/pxa/patches-2.6.21/007-flash.patch b/target/linux/pxa/patches-2.6.21/007-flash.patch deleted file mode 100644 index 3d4df09521..0000000000 --- a/target/linux/pxa/patches-2.6.21/007-flash.patch +++ /dev/null @@ -1,171 +0,0 @@ -Index: linux-2.6.21.7/drivers/mtd/maps/gumstix-flash.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/drivers/mtd/maps/gumstix-flash.c -@@ -0,0 +1,136 @@ -+/* -+ * Map driver for the Gumstix platform -+ * -+ * Author: Craig Hughes -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+ -+#define ROM_ADDR 0x00000000 -+#define FLASH_ADDR 0x00000000 -+ -+#define WINDOW_SIZE 64*1024*1024 -+ -+static struct map_info gumstix_flash_maps[1] = { { -+ .name = "Gumstix Flash ROM", -+ .size = WINDOW_SIZE, -+ .phys = FLASH_ADDR, -+ .bankwidth = 2, -+} }; -+ -+static struct mtd_partition gumstix_flash_partitions[] = { -+ { -+ .name = "Bootloader", -+ .size = 0x00040000, -+ .offset = FLASH_ADDR -+ },{ -+ .name = "RootFS", -+ .size = MTDPART_SIZ_FULL, -+ .offset = MTDPART_OFS_APPEND -+ } -+}; -+ -+static struct mtd_info *mymtds[1]; -+static struct mtd_partition *parsed_parts[1]; -+static int nr_parsed_parts[1]; -+ -+static const char *probes[] = { NULL }; -+ -+static int __init gumstix_flashmap_init(void) -+{ -+ int ret = 0, i; -+ -+ for (i = 0; i < 1; i++) { -+ gumstix_flash_maps[i].virt = ioremap(gumstix_flash_maps[i].phys, WINDOW_SIZE); -+ if (!gumstix_flash_maps[i].virt) { -+ printk(KERN_WARNING "Failed to ioremap %s\n", gumstix_flash_maps[i].name); -+ if (!ret) -+ ret = -ENOMEM; -+ continue; -+ } -+ simple_map_init(&gumstix_flash_maps[i]); -+ -+ printk(KERN_NOTICE "Probing %s at physical address 0x%08lx (%d-bit bankwidth)\n", -+ gumstix_flash_maps[i].name, gumstix_flash_maps[i].phys, -+ gumstix_flash_maps[i].bankwidth * 8); -+ -+ mymtds[i] = do_map_probe("cfi_probe", &gumstix_flash_maps[i]); -+ -+ if (!mymtds[i]) { -+ iounmap((void *)gumstix_flash_maps[i].virt); -+ if (gumstix_flash_maps[i].cached) -+ iounmap(gumstix_flash_maps[i].cached); -+ if (!ret) -+ ret = -EIO; -+ continue; -+ } -+ mymtds[i]->owner = THIS_MODULE; -+ -+ ret = parse_mtd_partitions(mymtds[i], probes, -+ &parsed_parts[i], 0); -+ -+ if (ret > 0) -+ nr_parsed_parts[i] = ret; -+ } -+ -+ if (!mymtds[0]) -+ return ret; -+ -+ for (i = 0; i < 1; i++) { -+ if (!mymtds[i]) { -+ printk(KERN_WARNING "%s is absent. Skipping\n", gumstix_flash_maps[i].name); -+ } else if (nr_parsed_parts[i]) { -+ add_mtd_partitions(mymtds[i], parsed_parts[i], nr_parsed_parts[i]); -+ } else if (!i) { -+ printk("Using static partitions on %s\n", gumstix_flash_maps[i].name); -+ add_mtd_partitions(mymtds[i], gumstix_flash_partitions, ARRAY_SIZE(gumstix_flash_partitions)); -+ } else { -+ printk("Registering %s as whole device\n", gumstix_flash_maps[i].name); -+ add_mtd_device(mymtds[i]); -+ } -+ } -+ return 0; -+} -+ -+static void __exit gumstix_flashmap_cleanup(void) -+{ -+ int i; -+ for (i = 0; i < 1; i++) { -+ if (!mymtds[i]) -+ continue; -+ -+ if (nr_parsed_parts[i] || !i) -+ del_mtd_partitions(mymtds[i]); -+ else -+ del_mtd_device(mymtds[i]); -+ -+ map_destroy(mymtds[i]); -+ iounmap((void *)gumstix_flash_maps[i].virt); -+ if (gumstix_flash_maps[i].cached) -+ iounmap(gumstix_flash_maps[i].cached); -+ -+ if (parsed_parts[i]) -+ kfree(parsed_parts[i]); -+ } -+} -+ -+module_init(gumstix_flashmap_init); -+module_exit(gumstix_flashmap_cleanup); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Gumstix, Inc. "); -+MODULE_DESCRIPTION("MTD map driver for the Gumstix Platform"); -Index: linux-2.6.21.7/drivers/mtd/maps/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/drivers/mtd/maps/Kconfig -+++ linux-2.6.21.7/drivers/mtd/maps/Kconfig -@@ -131,6 +131,13 @@ config MTD_SBC_GXX - More info at - . - -+config MTD_GUMSTIX -+ tristate "CFI Flash device mapped on Gumstix" -+ depends on ARCH_GUMSTIX && MTD_CFI_INTELEXT && MTD_PARTITIONS -+ help -+ This provides a driver for the on-board flash of the Gumstix -+ single board computers. -+ - config MTD_LUBBOCK - tristate "CFI Flash device mapped on Intel Lubbock XScale eval board" - depends on ARCH_LUBBOCK && MTD_CFI_INTELEXT && MTD_PARTITIONS -Index: linux-2.6.21.7/drivers/mtd/maps/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/mtd/maps/Makefile -+++ linux-2.6.21.7/drivers/mtd/maps/Makefile -@@ -21,6 +21,7 @@ obj-$(CONFIG_MTD_ICHXROM) += ichxrom.o - obj-$(CONFIG_MTD_CK804XROM) += ck804xrom.o - obj-$(CONFIG_MTD_TSUNAMI) += tsunami_flash.o - obj-$(CONFIG_MTD_LUBBOCK) += lubbock-flash.o -+obj-$(CONFIG_MTD_GUMSTIX) += gumstix-flash.o - obj-$(CONFIG_MTD_MAINSTONE) += mainstone-flash.o - obj-$(CONFIG_MTD_MBX860) += mbx860.o - obj-$(CONFIG_MTD_CEIVA) += ceiva.o diff --git a/target/linux/pxa/patches-2.6.21/008-pxa2xx_udc.patch b/target/linux/pxa/patches-2.6.21/008-pxa2xx_udc.patch deleted file mode 100644 index bfb7997556..0000000000 --- a/target/linux/pxa/patches-2.6.21/008-pxa2xx_udc.patch +++ /dev/null @@ -1,65 +0,0 @@ -Index: linux-2.6.21.7/drivers/usb/gadget/pxa2xx_udc.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/pxa2xx_udc.c -+++ linux-2.6.21.7/drivers/usb/gadget/pxa2xx_udc.c -@@ -51,6 +51,7 @@ - #include - #include - #include -+#include - #ifdef CONFIG_ARCH_PXA - #include - #endif -@@ -101,6 +102,10 @@ static const char ep0name [] = "ep0"; - - #endif - -+#ifdef CONFIG_ARCH_GUMSTIX -+#undef CONFIG_USB_PXA2XX_SMALL -+#endif -+ - #include "pxa2xx_udc.h" - - -@@ -2541,6 +2546,41 @@ static int __init pxa2xx_udc_probe(struc - } - #endif - -+ /* Reset UDCCS register to be able to recover from whatever -+ * state UDC was previously in. */ -+ *dev->ep[ 2].reg_udccs = UDCCS_BO_RPC | UDCCS_BO_SST; -+#ifndef CONFIG_USB_PXA2XX_SMALL -+ *dev->ep[ 7].reg_udccs = UDCCS_BO_RPC | UDCCS_BO_SST; -+ *dev->ep[12].reg_udccs = UDCCS_BO_RPC | UDCCS_BO_SST; -+#endif -+ -+ *dev->ep[ 1].reg_udccs = UDCCS_BI_TPC | UDCCS_BI_FTF | -+ UDCCS_BI_TUR | UDCCS_BI_SST | UDCCS_BI_TSP; -+#ifndef CONFIG_USB_PXA2XX_SMALL -+ *dev->ep[ 6].reg_udccs = UDCCS_BI_TPC | UDCCS_BI_FTF | -+ UDCCS_BI_TUR | UDCCS_BI_SST | UDCCS_BI_TSP; -+ *dev->ep[11].reg_udccs = UDCCS_BI_TPC | UDCCS_BI_FTF | -+ UDCCS_BI_TUR | UDCCS_BI_SST | UDCCS_BI_TSP; -+ -+ *dev->ep[ 3].reg_udccs = UDCCS_II_TPC | UDCCS_II_FTF | -+ UDCCS_II_TUR | UDCCS_II_TSP; -+ *dev->ep[ 8].reg_udccs = UDCCS_II_TPC | UDCCS_II_FTF | -+ UDCCS_II_TUR | UDCCS_II_TSP; -+ *dev->ep[13].reg_udccs = UDCCS_II_TPC | UDCCS_II_FTF | -+ UDCCS_II_TUR | UDCCS_II_TSP; -+ -+ *dev->ep[ 4].reg_udccs = UDCCS_IO_RPC | UDCCS_IO_ROF; -+ *dev->ep[ 9].reg_udccs = UDCCS_IO_RPC | UDCCS_IO_ROF; -+ *dev->ep[11].reg_udccs = UDCCS_IO_RPC | UDCCS_IO_ROF; -+ -+ *dev->ep[ 5].reg_udccs = UDCCS_INT_TPC | UDCCS_INT_FTF | -+ UDCCS_INT_TUR | UDCCS_INT_SST; -+ *dev->ep[10].reg_udccs = UDCCS_INT_TPC | UDCCS_INT_FTF | -+ UDCCS_INT_TUR | UDCCS_INT_SST; -+ *dev->ep[15].reg_udccs = UDCCS_INT_TPC | UDCCS_INT_FTF | -+ UDCCS_INT_TUR | UDCCS_INT_SST; -+#endif -+ - /* other non-static parts of init */ - dev->dev = &pdev->dev; - dev->mach = pdev->dev.platform_data; diff --git a/target/linux/pxa/patches-2.6.21/009-bkpxa-pxa-cpu.patch b/target/linux/pxa/patches-2.6.21/009-bkpxa-pxa-cpu.patch deleted file mode 100644 index ce9e6a1ad5..0000000000 --- a/target/linux/pxa/patches-2.6.21/009-bkpxa-pxa-cpu.patch +++ /dev/null @@ -1,117 +0,0 @@ -Status: WORKS -PXA CPU enhancements - -from patch 1667: -- 64K PTEs -from hh.org-cvs: -- support in pxa_gpio_mode for active low - -# -# Patch managed by http://www.mn-logistik.de/unsupported/pxa250/patcher -# - -Index: linux-2.6.21.7/arch/arm/mm/proc-xscale.S -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mm/proc-xscale.S -+++ linux-2.6.21.7/arch/arm/mm/proc-xscale.S -@@ -474,11 +474,62 @@ ENTRY(cpu_xscale_set_pte_ext) - movne r2, #0 @ no -> fault - - str r2, [r0] @ hardware version -+ -+ @ We try to map 64K page entries when possible. -+ @ We do that for kernel space only since the usage pattern from -+ @ the setting of VM area is quite simple. User space is not worth -+ @ the implied complexity because of ever randomly changing PTEs -+ @ (page aging, swapout, etc) requiring constant coherency checks. -+ @ Since PTEs are usually set in increasing order, we test the -+ @ possibility for a large page only when given the last PTE of a -+ @ 64K boundary. -+ tsteq r1, #L_PTE_USER -+ andeq r1, r0, #(15 << 2) -+ teqeq r1, #(15 << 2) -+ beq 1f -+ - mov ip, #0 - mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line - mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer - mov pc, lr - -+ @ See if we have 16 identical PTEs but with consecutive base addresses -+1: bic r3, r2, #0x0000f000 -+ mov r1, #0x0000f000 -+2: eor r2, r2, r3 -+ teq r2, r1 -+ bne 4f -+ subs r1, r1, #0x00001000 -+ ldr r2, [r0, #-4]! -+ bne 2b -+ eors r2, r2, r3 -+ bne 4f -+ -+ @ Now create our LARGE PTE from the current EXT one. -+ bic r3, r3, #PTE_TYPE_MASK -+ orr r3, r3, #PTE_TYPE_LARGE -+ and r2, r3, #0x30 @ EXT_AP --> LARGE_AP0 -+ orr r2, r2, r2, lsl #2 @ add LARGE_AP1 -+ orr r2, r2, r2, lsl #4 @ add LARGE_AP3 + LARGE_AP2 -+ and r1, r3, #0x3c0 @ EXT_TEX -+ bic r3, r3, #0x3c0 -+ orr r2, r2, r1, lsl #(12 - 6) @ --> LARGE_TEX -+ orr r2, r2, r3 @ add remaining bits -+ -+ @ then put it in the pagetable -+ mov r3, r2 -+3: strd r2, [r0], #8 -+ tst r0, #(15 << 2) -+ bne 3b -+ -+ @ Then sync the 2 corresponding cache lines -+ sub r0, r0, #(16 << 2) -+ mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line -+4: orr r0, r0, #(15 << 2) -+ mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line -+ mov ip, #0 -+ mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer -+ mov pc, lr - - .ltorg - -Index: linux-2.6.21.7/include/asm-arm/arch-pxa/pxa-regs.h -=================================================================== ---- linux-2.6.21.7.orig/include/asm-arm/arch-pxa/pxa-regs.h -+++ linux-2.6.21.7/include/asm-arm/arch-pxa/pxa-regs.h -@@ -1345,6 +1345,7 @@ - #define GPIO_ALT_FN_2_OUT 0x280 - #define GPIO_ALT_FN_3_IN 0x300 - #define GPIO_ALT_FN_3_OUT 0x380 -+#define GPIO_ACTIVE_LOW 0x1000 - #define GPIO_MD_MASK_NR 0x07f - #define GPIO_MD_MASK_DIR 0x080 - #define GPIO_MD_MASK_FN 0x300 -@@ -1597,6 +1598,25 @@ - #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ - #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ - -+#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ -+#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ -+#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ -+#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ -+#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ -+#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ -+#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ -+#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ -+#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ -+#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ -+#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ -+#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ -+#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ -+#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ -+#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ -+#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ -+#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ -+#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ -+ - - /* - * SSP Serial Port Registers diff --git a/target/linux/pxa/patches-2.6.21/010-bkpxa-pxa-cpufreq.patch b/target/linux/pxa/patches-2.6.21/010-bkpxa-pxa-cpufreq.patch deleted file mode 100644 index 0ee3533dec..0000000000 --- a/target/linux/pxa/patches-2.6.21/010-bkpxa-pxa-cpufreq.patch +++ /dev/null @@ -1,403 +0,0 @@ -Status: WORKS -PXA CPU frequency change support -added mods from Stefan Eletzhofer and Lothar Weissmann - -# -# Patch managed by http://www.mn-logistik.de/unsupported/pxa250/patcher -# - -Index: linux-2.6.21.7/arch/arm/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/Kconfig -+++ linux-2.6.21.7/arch/arm/Kconfig -@@ -800,7 +800,7 @@ config KEXEC - - endmenu - --if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX ) -+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA ) - - menu "CPU Frequency scaling" - -@@ -838,6 +838,12 @@ config CPU_FREQ_IMX - - endmenu - -+config CPU_FREQ_PXA -+ bool -+ depends on CPU_FREQ && ARCH_PXA -+ default y -+ select CPU_FREQ_DEFAULT_GOV_USERSPACE -+ - endif - - menu "Floating point emulation" -Index: linux-2.6.21.7/arch/arm/mach-pxa/Makefile -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/Makefile -+++ linux-2.6.21.7/arch/arm/mach-pxa/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_LEDS) += $(led-y) - # Misc features - obj-$(CONFIG_PM) += pm.o sleep.o - obj-$(CONFIG_PXA_SSP) += ssp.o -+obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o - - ifeq ($(CONFIG_PXA27x),y) - obj-$(CONFIG_PM) += standby.o -Index: linux-2.6.21.7/arch/arm/mach-pxa/cpu-pxa.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/arch/arm/mach-pxa/cpu-pxa.c -@@ -0,0 +1,321 @@ -+/* -+ * linux/arch/arm/mach-pxa/cpu-pxa.c -+ * -+ * Copyright (C) 2002,2003 Intrinsyc Software -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * History: -+ * 31-Jul-2002 : Initial version [FB] -+ * 29-Jan-2003 : added PXA255 support [FB] -+ * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) -+ * -+ * Note: -+ * This driver may change the memory bus clock rate, but will not do any -+ * platform specific access timing changes... for example if you have flash -+ * memory connected to CS0, you will need to register a platform specific -+ * notifier which will adjust the memory access strobes to maintain a -+ * minimum strobe width. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DEBUG 0 -+ -+#ifdef DEBUG -+ static unsigned int freq_debug = DEBUG; -+ MODULE_PARM(freq_debug, "i"); -+ MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); -+#else -+ #define freq_debug 0 -+#endif -+ -+typedef struct -+{ -+ unsigned int khz; -+ unsigned int membus; -+ unsigned int cccr; -+ unsigned int div2; -+} pxa_freqs_t; -+ -+/* Define the refresh period in mSec for the SDRAM and the number of rows */ -+#define SDRAM_TREF 64 /* standard 64ms SDRAM */ -+#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ -+#define MDREFR_DRI(x) ((x*SDRAM_TREF)/(SDRAM_ROWS*32)) -+ -+#define CCLKCFG_TURBO 0x1 -+#define CCLKCFG_FCS 0x2 -+#define PXA25x_MIN_FREQ 99500 -+#define PXA25x_MAX_FREQ 398100 -+#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) -+#define MDREFR_DRI_MASK 0xFFF -+ -+ -+/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ -+static pxa_freqs_t pxa255_run_freqs[] = -+{ -+ /* CPU MEMBUS CCCR DIV2*/ -+ { 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */ -+ {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */ -+ {199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */ -+ {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */ -+ {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */ -+ {398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */ -+ {0,} -+}; -+#define NUM_RUN_FREQS (sizeof(pxa255_run_freqs)/sizeof(pxa_freqs_t)) -+ -+static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1]; -+ -+/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ -+static pxa_freqs_t pxa255_turbo_freqs[] = -+{ -+ /* CPU MEMBUS CCCR DIV2*/ -+ { 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */ -+ {199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */ -+ {298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */ -+ {298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */ -+ {398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */ -+ {0,} -+}; -+#define NUM_TURBO_FREQS (sizeof(pxa255_turbo_freqs)/sizeof(pxa_freqs_t)) -+ -+static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1]; -+ -+extern unsigned get_clk_frequency_khz(int info); -+ -+/* find a valid frequency point */ -+static int pxa_verify_policy(struct cpufreq_policy *policy) -+{ -+ int ret; -+ struct cpufreq_frequency_table *pxa_freqs_table; -+ -+ if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) { -+ pxa_freqs_table = pxa255_run_freq_table; -+ } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { -+ pxa_freqs_table = pxa255_turbo_freq_table; -+ } else { -+ printk("CPU PXA: Unknown policy found. " -+ "Using CPUFREQ_POLICY_PERFORMANCE\n"); -+ pxa_freqs_table = pxa255_run_freq_table; -+ } -+ ret=cpufreq_frequency_table_verify(policy, pxa_freqs_table); -+ -+ if(freq_debug) { -+ printk("Verified CPU policy: %dKhz min to %dKhz max\n", -+ policy->min, policy->max); -+ } -+ -+ return ret; -+} -+ -+static int pxa_set_target(struct cpufreq_policy *policy, -+ unsigned int target_freq, -+ unsigned int relation) -+{ -+ int idx; -+ unsigned long cpus_allowed; -+ int cpu = policy->cpu; -+ struct cpufreq_freqs freqs; -+ pxa_freqs_t *pxa_freq_settings; -+ struct cpufreq_frequency_table *pxa_freqs_table; -+ unsigned long flags; -+ unsigned int unused; -+ unsigned int preset_mdrefr, postset_mdrefr; -+ -+ /* -+ * Save this threads cpus_allowed mask. -+ */ -+ cpus_allowed = current->cpus_allowed; -+ -+ /* -+ * Bind to the specified CPU. When this call returns, -+ * we should be running on the right CPU. -+ */ -+ set_cpus_allowed(current, 1 << cpu); -+ BUG_ON(cpu != smp_processor_id()); -+ -+ /* Get the current policy */ -+ if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) { -+ pxa_freq_settings = pxa255_run_freqs; -+ pxa_freqs_table = pxa255_run_freq_table; -+ }else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { -+ pxa_freq_settings = pxa255_turbo_freqs; -+ pxa_freqs_table = pxa255_turbo_freq_table; -+ }else { -+ printk("CPU PXA: Unknown policy found. " -+ "Using CPUFREQ_POLICY_PERFORMANCE\n"); -+ pxa_freq_settings = pxa255_run_freqs; -+ pxa_freqs_table = pxa255_run_freq_table; -+ } -+ -+ /* Lookup the next frequency */ -+ if (cpufreq_frequency_table_target(policy, pxa_freqs_table, -+ target_freq, relation, &idx)) { -+ return -EINVAL; -+ } -+ -+ freqs.old = policy->cur; -+ freqs.new = pxa_freq_settings[idx].khz; -+ freqs.cpu = policy->cpu; -+ if(freq_debug) { -+ printk(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n", -+ freqs.new/1000, (pxa_freq_settings[idx].div2) ? -+ (pxa_freq_settings[idx].membus/2000) : -+ (pxa_freq_settings[idx].membus/1000)); -+ } -+ -+ void *ramstart = phys_to_virt(0xa0000000); -+ -+ /* -+ * Tell everyone what we're about to do... -+ * you should add a notify client with any platform specific -+ * Vcc changing capability -+ */ -+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); -+ -+ /* Calculate the next MDREFR. If we're slowing down the SDRAM clock -+ * we need to preset the smaller DRI before the change. If we're speeding -+ * up we need to set the larger DRI value after the change. -+ */ -+ preset_mdrefr = postset_mdrefr = MDREFR; -+ if((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) { -+ preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) | -+ MDREFR_DRI(pxa_freq_settings[idx].membus); -+ } -+ postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) | -+ MDREFR_DRI(pxa_freq_settings[idx].membus); -+ -+ /* If we're dividing the memory clock by two for the SDRAM clock, this -+ * must be set prior to the change. Clearing the divide must be done -+ * after the change. -+ */ -+ if(pxa_freq_settings[idx].div2) { -+ preset_mdrefr |= MDREFR_DB2_MASK; -+ postset_mdrefr |= MDREFR_DB2_MASK; -+ } else { -+ postset_mdrefr &= ~MDREFR_DB2_MASK; -+ } -+ -+ local_irq_save(flags); -+ -+ /* Set new the CCCR */ -+ CCCR = pxa_freq_settings[idx].cccr; -+ -+ __asm__ __volatile__(" \ -+ ldr r4, [%1] ; /* load MDREFR */ \ -+ b 2f ; \ -+ .align 5 ; \ -+1: \ -+ str %4, [%1] ; /* preset the MDREFR */ \ -+ mcr p14, 0, %2, c6, c0, 0 ; /* set CCLKCFG[FCS] */ \ -+ str %5, [%1] ; /* postset the MDREFR */ \ -+ \ -+ b 3f ; \ -+2: b 1b ; \ -+3: nop ; \ -+ " -+ : "=&r" (unused) -+ : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart), \ -+ "r" (preset_mdrefr), "r" (postset_mdrefr) -+ : "r4", "r5"); -+ local_irq_restore(flags); -+ -+ /* -+ * Restore the CPUs allowed mask. -+ */ -+ set_cpus_allowed(current, cpus_allowed); -+ -+ /* -+ * Tell everyone what we've just done... -+ * you should add a notify client with any platform specific -+ * SDRAM refresh timer adjustments -+ */ -+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); -+ -+ return 0; -+} -+ -+static int pxa_cpufreq_init(struct cpufreq_policy *policy) -+{ -+ unsigned long cpus_allowed; -+ unsigned int cpu = policy->cpu; -+ int i; -+ -+ cpus_allowed = current->cpus_allowed; -+ -+ set_cpus_allowed(current, 1 << cpu); -+ BUG_ON(cpu != smp_processor_id()); -+ -+ /* set default policy and cpuinfo */ -+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR; -+ policy->policy = CPUFREQ_POLICY_PERFORMANCE; -+ policy->cpuinfo.max_freq = PXA25x_MAX_FREQ; -+ policy->cpuinfo.min_freq = PXA25x_MIN_FREQ; -+ policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ -+ policy->cur = get_clk_frequency_khz(0); /* current freq */ -+ policy->min = policy->max = policy->cur; -+ -+ /* Generate the run cpufreq_frequency_table struct */ -+ for(i=0;i -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+static struct proc_dir_entry *proc_gpio_parent; -+static struct proc_dir_entry *proc_gpios[PXA_LAST_GPIO + 1]; -+ -+typedef struct -+{ -+ int gpio; -+ char name[32]; -+} gpio_summary_type; -+ -+static gpio_summary_type gpio_summaries[PXA_LAST_GPIO + 1]; -+ -+static int proc_gpio_write(struct file *file, const char __user *buf, -+ unsigned long count, void *data) -+{ -+ char *cur, lbuf[count + 1]; -+ gpio_summary_type *summary = data; -+ u32 altfn, direction, setclear, gafr; -+ -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EACCES; -+ -+ memset(lbuf, 0, count + 1); -+ -+ if (copy_from_user(lbuf, buf, count)) -+ return -EFAULT; -+ -+ cur = lbuf; -+ -+ // Initialize to current state -+ altfn = ((GAFR(summary->gpio) >> ((summary->gpio & 0x0f) << 0x01)) & 0x03); -+ direction = GPDR(summary->gpio) & GPIO_bit(summary->gpio); -+ setclear = GPLR(summary->gpio) & GPIO_bit(summary->gpio); -+ while(1) -+ { -+ // We accept options: {GPIO|AF1|AF2|AF3}, {set|clear}, {in|out} -+ // Anything else is an error -+ while(cur[0] && (isspace(cur[0]) || ispunct(cur[0]))) cur = &(cur[1]); -+ -+ if('\0' == cur[0]) break; -+ -+ // Ok, so now we're pointing at the start of something -+ switch(cur[0]) -+ { -+ case 'G': -+ // Check that next is "PIO" -- '\0' will cause safe short-circuit if end of buf -+ if(!(cur[1] == 'P' && cur[2] == 'I' && cur[3] == 'O')) goto parse_error; -+ // Ok, so set this GPIO to GPIO (non-ALT) function -+ altfn = 0; -+ cur = &(cur[4]); -+ break; -+ case 'A': -+ if(!(cur[1] == 'F' && cur[2] >= '1' && cur[2] <= '3')) goto parse_error; -+ altfn = cur[2] - '0'; -+ cur = &(cur[3]); -+ break; -+ case 's': -+ if(!(cur[1] == 'e' && cur[2] == 't')) goto parse_error; -+ setclear = 1; -+ cur = &(cur[3]); -+ break; -+ case 'c': -+ if(!(cur[1] == 'l' && cur[2] == 'e' && cur[3] == 'a' && cur[4] == 'r')) goto parse_error; -+ setclear = 0; -+ cur = &(cur[5]); -+ break; -+ case 'i': -+ if(!(cur[1] == 'n')) goto parse_error; -+ direction = 0; -+ cur = &(cur[2]); -+ break; -+ case 'o': -+ if(!(cur[1] == 'u' && cur[2] == 't')) goto parse_error; -+ direction = 1; -+ cur = &(cur[3]); -+ break; -+ default: goto parse_error; -+ } -+ } -+ // Ok, now set gpio mode and value -+ if(direction) -+ GPDR(summary->gpio) |= GPIO_bit(summary->gpio); -+ else -+ GPDR(summary->gpio) &= ~GPIO_bit(summary->gpio); -+ -+ gafr = GAFR(summary->gpio) & ~(0x3 << (((summary->gpio) & 0xf)*2)); -+ GAFR(summary->gpio) = gafr | (altfn << (((summary->gpio) & 0xf)*2)); -+ -+ if(direction && !altfn) -+ { -+ if(setclear) GPSR(summary->gpio) = GPIO_bit(summary->gpio); -+ else GPCR(summary->gpio) = GPIO_bit(summary->gpio); -+ } -+ -+#ifdef CONFIG_PROC_GPIO_DEBUG -+ printk(KERN_INFO "Set (%s,%s,%s) via /proc/gpio/%s\n",altfn ? (altfn == 1 ? "AF1" : (altfn == 2 ? "AF2" : "AF3")) : "GPIO", -+ direction ? "out" : "in", -+ setclear ? "set" : "clear", -+ summary->name); -+#endif -+ -+ return count; -+ -+parse_error: -+ printk(KERN_CRIT "Parse error: Expect \"[GPIO|AF1|AF2|AF3]|[set|clear]|[in|out] ...\"\n"); -+ return -EINVAL; -+} -+ -+static int proc_gpio_read(char *page, char **start, off_t off, -+ int count, int *eof, void *data) -+{ -+ char *p = page; -+ gpio_summary_type *summary = data; -+ int len, i, af; -+ i = summary->gpio; -+ -+ p += sprintf(p, "%d\t%s\t%s\t%s\n", i, -+ (af = ((GAFR(i) >> ((i & 0x0f) << 0x01)) & 0x03)) ? (af == 1 ? "AF1" : (af == 2 ? "AF2" : "AF3")) : "GPIO", -+ (GPDR(i) & GPIO_bit(i)) ? "out" : "in", -+ (GPLR(i) & GPIO_bit(i)) ? "set" : "clear"); -+ -+ len = (p - page) - off; -+ -+ if(len < 0) -+ { -+ len = 0; -+ } -+ -+ *eof = (len <= count) ? 1 : 0; -+ *start = page + off; -+ -+ return len; -+} -+ -+ -+#ifdef CONFIG_PXA25x -+static const char const *GAFR_DESC[] = { "GAFR0_L", "GAFR0_U", "GAFR1_L", "GAFR1_U", "GAFR2_L", "GAFR2_U" }; -+#elif defined(CONFIG_PXA27x) -+static const char const *GAFR_DESC[] = { "GAFR0_L", "GAFR0_U", "GAFR1_L", "GAFR1_U", "GAFR2_L", "GAFR2_U", "GAFR3_L", "GAFR3_U" }; -+#endif -+ -+static int proc_gafr_read(char *page, char **start, off_t off, -+ int count, int *eof, void *data) -+{ -+ char *p = page; -+ int i, len; -+ -+ for(i=0; idata = &gpio_summaries[i]; -+ proc_gpios[i]->read_proc = proc_gpio_read; -+ proc_gpios[i]->write_proc = proc_gpio_write; -+ } -+ } -+ -+ create_proc_read_entry("GAFR", 0444, proc_gpio_parent, proc_gafr_read, NULL); -+ create_proc_read_entry("GPDR", 0444, proc_gpio_parent, proc_gpdr_read, NULL); -+ create_proc_read_entry("GPLR", 0444, proc_gpio_parent, proc_gplr_read, NULL); -+ -+ return 0; -+} -+ -+static void gpio_exit(void) -+{ -+ int i; -+ -+ remove_proc_entry("GAFR", proc_gpio_parent); -+ remove_proc_entry("GPDR", proc_gpio_parent); -+ remove_proc_entry("GPLR", proc_gpio_parent); -+ -+ for(i=0; i < (PXA_LAST_GPIO+1); i++) -+ { -+ if(proc_gpios[i]) remove_proc_entry(gpio_summaries[i].name, proc_gpio_parent); -+ } -+ if(proc_gpio_parent) remove_proc_entry("gpio", NULL); -+} -+ -+module_init(gpio_init); -+module_exit(gpio_exit); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/pxa/patches-2.6.21/012-serial-ether-addr.patch b/target/linux/pxa/patches-2.6.21/012-serial-ether-addr.patch deleted file mode 100644 index 93535fa47b..0000000000 --- a/target/linux/pxa/patches-2.6.21/012-serial-ether-addr.patch +++ /dev/null @@ -1,62 +0,0 @@ -Index: linux-2.6.21.7/drivers/usb/gadget/ether.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/ether.c -+++ linux-2.6.21.7/drivers/usb/gadget/ether.c -@@ -2249,6 +2249,38 @@ static u8 __devinit nibble (unsigned cha - return 0; - } - -+static inline unsigned int is_gumstix_oui(u8 *addr) -+{ -+ return (addr[0] == 0x00 && addr[1] == 0x15 && addr[2] == 0xC9); -+} -+ -+/** -+ * gen_serial_ether_addr - Generate software assigned Ethernet address -+ * based on the system_serial number -+ * @addr: Pointer to a six-byte array containing the Ethernet address -+ * -+ * Generate an Ethernet address (MAC) that is not multicast -+ * and has the local assigned bit set, keyed on the system_serial -+ */ -+static inline void gen_serial_ether_addr(u8 *addr) -+{ -+ static u8 ether_serial_digit = 0; -+ addr [0] = system_serial_high >> 8; -+ addr [1] = system_serial_high; -+ addr [2] = system_serial_low >> 24; -+ addr [3] = system_serial_low >> 16; -+ addr [4] = system_serial_low >> 8; -+ addr [5] = (system_serial_low & 0xc0) | /* top bits are from system serial */ -+ (2 << 4) | /* 2 bits identify interface type 1=ether, 2=usb, 3&4 undef */ -+ ((ether_serial_digit++) & 0x0f); /* 15 possible interfaces of each type */ -+ -+ if(!is_gumstix_oui(addr)) -+ { -+ addr [0] &= 0xfe; /* clear multicast bit */ -+ addr [0] |= 0x02; /* set local assignment bit (IEEE802) */ -+ } -+} -+ - static int __devinit get_ether_addr(const char *str, u8 *dev_addr) - { - if (str) { -@@ -2266,8 +2298,16 @@ static int __devinit get_ether_addr(cons - if (is_valid_ether_addr (dev_addr)) - return 0; - } -- random_ether_addr(dev_addr); -- return 1; -+ if(system_serial_high | system_serial_low) -+ { -+ gen_serial_ether_addr(dev_addr); -+ return 0; -+ } -+ else -+ { -+ random_ether_addr(dev_addr); -+ return 1; -+ } - } - - static int __devinit diff --git a/target/linux/pxa/patches-2.6.21/013-cpufreq-better-freqs.patch b/target/linux/pxa/patches-2.6.21/013-cpufreq-better-freqs.patch deleted file mode 100644 index 829f75cdce..0000000000 --- a/target/linux/pxa/patches-2.6.21/013-cpufreq-better-freqs.patch +++ /dev/null @@ -1,53 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/mach-pxa/cpu-pxa.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/cpu-pxa.c -+++ linux-2.6.21.7/arch/arm/mach-pxa/cpu-pxa.c -@@ -65,8 +65,8 @@ typedef struct - - #define CCLKCFG_TURBO 0x1 - #define CCLKCFG_FCS 0x2 --#define PXA25x_MIN_FREQ 99500 --#define PXA25x_MAX_FREQ 398100 -+#define PXA25x_MIN_FREQ 99533 -+#define PXA25x_MAX_FREQ 530842 - #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) - #define MDREFR_DRI_MASK 0xFFF - -@@ -75,12 +75,14 @@ typedef struct - static pxa_freqs_t pxa255_run_freqs[] = - { - /* CPU MEMBUS CCCR DIV2*/ -- { 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */ -- {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */ -- {199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */ -- {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */ -- {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */ -- {398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */ -+ { 99533, 99533, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */ -+ {132710, 132710, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */ -+ {199066, 99533, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */ -+ {265421, 132710, 0x143, 0}, /* run=265, turbo=265, PXbus=133, SDRAM=133 */ -+ {331776, 165888, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */ -+ {398131, 99533, 0x161, 0}, /* run=398, turbo=398, PXbus=99, SDRAM=99 */ -+ {398131, 132710, 0x1c3, 0}, /* run=265, turbo=398, PXbus=133, SDRAM=133 */ -+ {530842, 132710, 0x163, 0}, /* run=531, turbo=531, PXbus=133, SDRAM=133 */ - {0,} - }; - #define NUM_RUN_FREQS (sizeof(pxa255_run_freqs)/sizeof(pxa_freqs_t)) -@@ -91,11 +93,11 @@ static struct cpufreq_frequency_table px - static pxa_freqs_t pxa255_turbo_freqs[] = - { - /* CPU MEMBUS CCCR DIV2*/ -- { 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */ -- {199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */ -- {298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */ -- {298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */ -- {398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */ -+ { 99533, 99533, 0x121, 1}, /* run=99, turbo= 99, PXbus=99, SDRAM=50 */ -+ {149299, 99533, 0x1a1, 0}, /* run=99, turbo=149, PXbus=99, SDRAM=99 */ -+ {199066, 99533, 0x221, 0}, /* run=99, turbo=199, PXbus=99, SDRAM=99 */ -+ {298598, 99533, 0x321, 0}, /* run=99, turbo=299, PXbus=99, SDRAM=99 */ -+ {398131, 99533, 0x241, 1}, /* run=199, turbo=398, PXbus=99, SDRAM=50 */ - {0,} - }; - #define NUM_TURBO_FREQS (sizeof(pxa255_turbo_freqs)/sizeof(pxa_freqs_t)) diff --git a/target/linux/pxa/patches-2.6.21/014-ethernet-config.patch b/target/linux/pxa/patches-2.6.21/014-ethernet-config.patch deleted file mode 100644 index de0d031d5f..0000000000 --- a/target/linux/pxa/patches-2.6.21/014-ethernet-config.patch +++ /dev/null @@ -1,26 +0,0 @@ -Index: linux-2.6.21.7/drivers/net/smc91x.h -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/smc91x.h -+++ linux-2.6.21.7/drivers/net/smc91x.h -@@ -55,6 +55,21 @@ - #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) - #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) - -+#elif defined(CONFIG_ARCH_GUMSTIX) -+#define SMC_CAN_USE_8BIT 0 -+#define SMC_CAN_USE_16BIT 1 -+#define SMC_CAN_USE_32BIT 0 -+#define SMC_NOWAIT 1 -+#define SMC_USE_PXA_DMA 1 -+#define SMC_IO_SHIFT 0 -+#define SMC_inw(a, r) readw((a) + (r)) -+#define SMC_outw(v, a, r) writew(v, (a) + (r)) -+#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) -+#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) -+#define RPC_LSA_DEFAULT RPC_LED_100_10 -+#define RPC_LSB_DEFAULT RPC_LED_TX_RX -+ -+ - #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) - - /* We can only do 16-bit reads and writes in the static memory space. */ diff --git a/target/linux/pxa/patches-2.6.21/015-smc-ether-addr.patch b/target/linux/pxa/patches-2.6.21/015-smc-ether-addr.patch deleted file mode 100644 index e45c4668c1..0000000000 --- a/target/linux/pxa/patches-2.6.21/015-smc-ether-addr.patch +++ /dev/null @@ -1,62 +0,0 @@ -Index: linux-2.6.21.7/drivers/net/smc91x.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/smc91x.c -+++ linux-2.6.21.7/drivers/net/smc91x.c -@@ -1815,6 +1815,39 @@ static int __init smc_findirq(void __iom - return probe_irq_off(cookie); - } - -+static inline unsigned int is_gumstix_oui(u8 *addr) -+{ -+ return (addr[0] == 0x00 && addr[1] == 0x15 && addr[2] == 0xC9); -+} -+ -+/** -+ * gen_serial_ether_addr - Generate software assigned Ethernet address -+ * based on the system_serial number -+ * @addr: Pointer to a six-byte array containing the Ethernet address -+ * -+ * Generate an Ethernet address (MAC) that is not multicast -+ * and has the local assigned bit set, keyed on the system_serial -+ */ -+static inline void gen_serial_ether_addr(u8 *addr) -+{ -+ static u8 ether_serial_digit = 0; -+ addr [0] = system_serial_high >> 8; -+ addr [1] = system_serial_high; -+ addr [2] = system_serial_low >> 24; -+ addr [3] = system_serial_low >> 16; -+ addr [4] = system_serial_low >> 8; -+ addr [5] = (system_serial_low & 0xc0) | /* top bits are from system serial */ -+ (1 << 4) | /* 2 bits identify interface type 1=ether, 2=usb, 3&4 undef */ -+ ((ether_serial_digit++) & 0x0f); /* 15 possible interfaces of each type */ -+ -+ if(!is_gumstix_oui(addr)) -+ { -+ addr [0] &= 0xfe; /* clear multicast bit */ -+ addr [0] |= 0x02; /* set local assignment bit (IEEE802) */ -+ } -+} -+ -+ - /* - * Function: smc_probe(unsigned long ioaddr) - * -@@ -2032,15 +2065,13 @@ static int __init smc_probe(struct net_d - THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); - - if (!is_valid_ether_addr(dev->dev_addr)) { -- printk("%s: Invalid ethernet MAC address. Please " -- "set using ifconfig\n", dev->name); -- } else { -+ gen_serial_ether_addr(dev->dev_addr); -+ } - /* Print the Ethernet address */ - printk("%s: Ethernet addr: ", dev->name); - for (i = 0; i < 5; i++) - printk("%2.2x:", dev->dev_addr[i]); - printk("%2.2x\n", dev->dev_addr[5]); -- } - - if (lp->phy_type == 0) { - PRINTK("%s: No PHY found\n", dev->name); diff --git a/target/linux/pxa/patches-2.6.21/016-cpufreq-ondemand-by-default.patch b/target/linux/pxa/patches-2.6.21/016-cpufreq-ondemand-by-default.patch deleted file mode 100644 index dba8d9f032..0000000000 --- a/target/linux/pxa/patches-2.6.21/016-cpufreq-ondemand-by-default.patch +++ /dev/null @@ -1,42 +0,0 @@ -Index: linux-2.6.21.7/drivers/cpufreq/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/drivers/cpufreq/Kconfig -+++ linux-2.6.21.7/drivers/cpufreq/Kconfig -@@ -52,7 +52,7 @@ config CPU_FREQ_STAT_DETAILS - - choice - prompt "Default CPUFreq governor" -- default CPU_FREQ_DEFAULT_GOV_USERSPACE if CPU_FREQ_SA1100 || CPU_FREQ_SA1110 -+ default CPU_FREQ_DEFAULT_GOV_USERSPACE if CPU_FREQ_SA1100 || CPU_FREQ_SA1110 || CPU_FREQ_PXA - default CPU_FREQ_DEFAULT_GOV_PERFORMANCE - help - This option sets which CPUFreq governor shall be loaded at -@@ -75,6 +75,14 @@ config CPU_FREQ_DEFAULT_GOV_USERSPACE - program shall be able to set the CPU dynamically without having - to enable the userspace governor manually. - -+config CPU_FREQ_DEFAULT_GOV_ONDEMAND -+ bool "ondemand" -+ select CPU_FREQ_GOV_ONDEMAND -+ help -+ Use the CPUFreq governor 'ondemand' as default. This sets -+ the frequency dynamically based on CPU load, throttling up -+ and down as necessary. -+ - endchoice - - config CPU_FREQ_GOV_PERFORMANCE -Index: linux-2.6.21.7/include/linux/cpufreq.h -=================================================================== ---- linux-2.6.21.7.orig/include/linux/cpufreq.h -+++ linux-2.6.21.7/include/linux/cpufreq.h -@@ -286,6 +286,9 @@ extern struct cpufreq_governor cpufreq_g - #elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE) - extern struct cpufreq_governor cpufreq_gov_userspace; - #define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_userspace -+#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND) -+extern struct cpufreq_governor cpufreq_gov_dbs; -+#define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_dbs; - #endif - - diff --git a/target/linux/pxa/patches-2.6.21/017-modular-init-bluetooth.patch b/target/linux/pxa/patches-2.6.21/017-modular-init-bluetooth.patch deleted file mode 100644 index 108a4ca8ed..0000000000 --- a/target/linux/pxa/patches-2.6.21/017-modular-init-bluetooth.patch +++ /dev/null @@ -1,108 +0,0 @@ -Index: linux-2.6.21.7/net/bluetooth/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/net/bluetooth/Kconfig -+++ linux-2.6.21.7/net/bluetooth/Kconfig -@@ -30,6 +30,12 @@ menuconfig BT - Bluetooth kernel modules are provided in the BlueZ packages. - For more information, see . - -+config BT_GUMSTIX -+ tristate -+ default m if BT=m -+ default y if BT=y -+ depends on BT && ARCH_GUMSTIX -+ - config BT_L2CAP - tristate "L2CAP protocol support" - depends on BT -Index: linux-2.6.21.7/net/bluetooth/Makefile -=================================================================== ---- linux-2.6.21.7.orig/net/bluetooth/Makefile -+++ linux-2.6.21.7/net/bluetooth/Makefile -@@ -9,5 +9,6 @@ obj-$(CONFIG_BT_RFCOMM) += rfcomm/ - obj-$(CONFIG_BT_BNEP) += bnep/ - obj-$(CONFIG_BT_CMTP) += cmtp/ - obj-$(CONFIG_BT_HIDP) += hidp/ -+obj-$(CONFIG_BT_GUMSTIX)+= gumstix_bluetooth.o - - bluetooth-objs := af_bluetooth.o hci_core.o hci_conn.o hci_event.o hci_sock.o hci_sysfs.o lib.o -Index: linux-2.6.21.7/net/bluetooth/af_bluetooth.c -=================================================================== ---- linux-2.6.21.7.orig/net/bluetooth/af_bluetooth.c -+++ linux-2.6.21.7/net/bluetooth/af_bluetooth.c -@@ -327,12 +327,20 @@ static struct net_proto_family bt_sock_f - .create = bt_sock_create, - }; - -+#ifdef CONFIG_ARCH_GUMSTIX -+extern void gumstix_bluetooth_load(void); -+#endif -+ - static int __init bt_init(void) - { - int err; - - BT_INFO("Core ver %s", VERSION); - -+#ifdef CONFIG_ARCH_GUMSTIX -+ gumstix_bluetooth_load(); -+#endif -+ - err = bt_sysfs_init(); - if (err < 0) - return err; -Index: linux-2.6.21.7/net/bluetooth/gumstix_bluetooth.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/net/bluetooth/gumstix_bluetooth.c -@@ -0,0 +1,50 @@ -+/* -+ * Gumstix bluetooth module intialization driver -+ * -+ * Author: Craig Hughes -+ * Created: December 9, 2004 -+ * Copyright: (C) 2004 Craig Hughes -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ */ -+ -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+static void gumstix_bluetooth_load(void) -+{ -+} -+ -+EXPORT_SYMBOL(gumstix_bluetooth_load); -+ -+int __init gumstix_bluetooth_init(void) -+{ -+ /* Set up GPIOs to use the BTUART */ -+ pxa_gpio_mode(GPIO42_HWRXD_MD); -+ pxa_gpio_mode(GPIO43_HWTXD_MD); -+ pxa_gpio_mode(GPIO44_HWCTS_MD); -+ pxa_gpio_mode(GPIO45_HWRTS_MD); -+ -+ return 0; -+} -+ -+void __exit gumstix_bluetooth_exit(void) -+{ -+} -+ -+module_init(gumstix_bluetooth_init); -+module_exit(gumstix_bluetooth_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Craig Hughes "); -+MODULE_DESCRIPTION("Gumstix board bluetooth module initialization driver"); -+MODULE_VERSION("1:0.1"); diff --git a/target/linux/pxa/patches-2.6.21/018-modular-init-smc91x.patch b/target/linux/pxa/patches-2.6.21/018-modular-init-smc91x.patch deleted file mode 100644 index 9e04f13db1..0000000000 --- a/target/linux/pxa/patches-2.6.21/018-modular-init-smc91x.patch +++ /dev/null @@ -1,203 +0,0 @@ -Index: linux-2.6.21.7/drivers/net/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/Kconfig -+++ linux-2.6.21.7/drivers/net/Kconfig -@@ -959,6 +959,12 @@ config SMC91X - module, say M here and read as well - as . - -+config SMC91X_GUMSTIX -+ tristate -+ default m if SMC91X=m -+ default y if SMC91X=y -+ depends on SMC91X && ARCH_GUMSTIX -+ - config SMC9194 - tristate "SMC 9194 support" - depends on NET_VENDOR_SMC && (ISA || MAC && BROKEN) -Index: linux-2.6.21.7/drivers/net/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/Makefile -+++ linux-2.6.21.7/drivers/net/Makefile -@@ -201,6 +201,7 @@ obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o - - obj-$(CONFIG_MACB) += macb.o - -+obj-$(CONFIG_SMC91X_GUMSTIX) += gumstix-smc91x.o - obj-$(CONFIG_ARM) += arm/ - obj-$(CONFIG_DEV_APPLETALK) += appletalk/ - obj-$(CONFIG_TR) += tokenring/ -Index: linux-2.6.21.7/drivers/net/smc91x.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/smc91x.c -+++ linux-2.6.21.7/drivers/net/smc91x.c -@@ -2373,6 +2373,10 @@ static struct platform_driver smc_driver - }, - }; - -+#ifdef CONFIG_ARCH_GUMSTIX -+extern void gumstix_smc91x_load(void); -+#endif -+ - static int __init smc_init(void) - { - #ifdef MODULE -@@ -2384,6 +2388,10 @@ static int __init smc_init(void) - #endif - #endif - -+#ifdef CONFIG_ARCH_GUMSTIX -+ gumstix_smc91x_load(); -+#endif -+ - return platform_driver_register(&smc_driver); - } - -Index: linux-2.6.21.7/drivers/net/gumstix-smc91x.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/drivers/net/gumstix-smc91x.c -@@ -0,0 +1,143 @@ -+/* -+ * Gumstix SMC91C111 chip intialization driver -+ * -+ * Author: Craig Hughes -+ * Created: December 9, 2004 -+ * Copyright: (C) 2004 Craig Hughes -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#define SMC_DEBUG 0 -+#include -+#include "smc91x.h" -+ -+static struct resource gumstix_smc91x0_resources[] = { -+ [0] = { -+ .name = "smc91x-regs", -+ .start = PXA_CS1_PHYS + 0x00000300, -+ .end = PXA_CS1_PHYS + 0x000fffff, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = GUMSTIX_ETH0_IRQ, -+ .end = GUMSTIX_ETH0_IRQ, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct resource gumstix_smc91x1_resources[] = { -+ [0] = { -+ .name = "smc91x-regs", -+ .start = PXA_CS2_PHYS + 0x00000300, -+ .end = PXA_CS2_PHYS + 0x000fffff, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = GUMSTIX_ETH1_IRQ, -+ .end = GUMSTIX_ETH1_IRQ, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device gumstix_smc91x0_device = { -+ .name = "smc91x", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(gumstix_smc91x0_resources), -+ .resource = gumstix_smc91x0_resources, -+}; -+ -+static struct platform_device gumstix_smc91x1_device = { -+ .name = "smc91x", -+ .id = 1, -+ .num_resources = ARRAY_SIZE(gumstix_smc91x1_resources), -+ .resource = gumstix_smc91x1_resources, -+}; -+ -+static struct platform_device *smc91x_devices[] = { -+ &gumstix_smc91x0_device, -+ &gumstix_smc91x1_device, -+}; -+ -+/* First we're going to test if there's a 2nd SMC91C111, and if not, then we'll free up those resources and the GPIO lines -+ * that it would otherwise use. We have no choice but to probe by doing: -+ * Set nCS2 to CS2 mode -+ * Set the reset line to GPIO out mode, and pull it high, then drop it low (to trigger reset) -+ * Read from the memory space to check for the sentinel sequence identifying a likely SMC91C111 device -+ */ -+int __init gumstix_smc91x_init(void) -+{ -+ unsigned int val, num_devices=ARRAY_SIZE(smc91x_devices); -+ void *ioaddr; -+ -+ /* Set up nPWE */ -+ pxa_gpio_mode(GPIO49_nPWE_MD); -+ -+ pxa_gpio_mode(GPIO78_nCS_2_MD); -+ // If either if statement fails, then we'll drop out and turn_off_eth1, -+ // if both succeed, then we'll skip that and just proceed with 2 cards -+ if(request_mem_region(gumstix_smc91x1_resources[0].start, SMC_IO_EXTENT, "smc91x probe")) -+ { -+ ioaddr = ioremap(gumstix_smc91x1_resources[0].start, SMC_IO_EXTENT); -+ val = ioread16(ioaddr + BANK_SELECT); -+ iounmap(ioaddr); -+ release_mem_region(gumstix_smc91x1_resources[0].start, SMC_IO_EXTENT); -+ if ((val & 0xFF00) == 0x3300) { -+ goto proceed; -+ } -+ } -+ -+turn_off_eth1: -+ // This is apparently not an SMC91C111 -+ // So, let's decrement the number of devices to request, and reset the GPIO lines to GPIO IN mode -+ num_devices--; -+ smc91x_devices[1] = NULL; -+ pxa_gpio_mode(78 | GPIO_IN); -+ -+proceed: -+ pxa_gpio_mode(GPIO15_nCS_1_MD); -+ -+ if(smc91x_devices[1]) pxa_gpio_mode(GPIO_GUMSTIX_ETH1_RST_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_ETH0_RST_MD); -+ if(smc91x_devices[1]) GPSR(GPIO_GUMSTIX_ETH1_RST) = GPIO_bit(GPIO_GUMSTIX_ETH1_RST); -+ GPSR(GPIO_GUMSTIX_ETH0_RST) = GPIO_bit(GPIO_GUMSTIX_ETH0_RST); -+ udelay(1); // Hold RESET for at least 100ns -+ if(smc91x_devices[1]) GPCR(GPIO_GUMSTIX_ETH1_RST) = GPIO_bit(GPIO_GUMSTIX_ETH1_RST); -+ GPCR(GPIO_GUMSTIX_ETH0_RST) = GPIO_bit(GPIO_GUMSTIX_ETH0_RST); -+ msleep(50); -+ -+ return platform_add_devices(smc91x_devices, num_devices); -+} -+ -+void __exit gumstix_smc91x_exit(void) -+{ -+ if(smc91x_devices[1] != NULL) platform_device_unregister(&gumstix_smc91x1_device); -+ platform_device_unregister(&gumstix_smc91x0_device); -+} -+ -+void gumstix_smc91x_load(void) {} -+EXPORT_SYMBOL(gumstix_smc91x_load); -+ -+module_init(gumstix_smc91x_init); -+module_exit(gumstix_smc91x_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Craig Hughes "); -+MODULE_DESCRIPTION("Gumstix board SMC91C111 chip initialization driver"); -+MODULE_VERSION("1:0.1"); diff --git a/target/linux/pxa/patches-2.6.21/019-modular-init-usb-gadget.patch b/target/linux/pxa/patches-2.6.21/019-modular-init-usb-gadget.patch deleted file mode 100644 index e24e93aa15..0000000000 --- a/target/linux/pxa/patches-2.6.21/019-modular-init-usb-gadget.patch +++ /dev/null @@ -1,106 +0,0 @@ -Index: linux-2.6.21.7/drivers/usb/gadget/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/Kconfig -+++ linux-2.6.21.7/drivers/usb/gadget/Kconfig -@@ -56,6 +56,14 @@ config USB_GADGET_DEBUG_FILES - config USB_GADGET_SELECTED - boolean - -+config USB_GADGET_GUMSTIX -+ tristate -+ default m if USB_GADGET=m -+ default y if USB_GADGET=y -+ depends on USB_GADGET && ARCH_GUMSTIX -+ help -+ USB Gadget support for the Gumstix platform -+ - # - # USB Peripheral Controller Support - # -Index: linux-2.6.21.7/drivers/usb/gadget/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/Makefile -+++ linux-2.6.21.7/drivers/usb/gadget/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_USB_GOKU) += goku_udc.o - obj-$(CONFIG_USB_OMAP) += omap_udc.o - obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o - obj-$(CONFIG_USB_AT91) += at91_udc.o -+obj-$(CONFIG_USB_GADGET_GUMSTIX) += gumstix_gadget.o - - # - # USB gadget drivers -Index: linux-2.6.21.7/drivers/usb/gadget/pxa2xx_udc.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/pxa2xx_udc.c -+++ linux-2.6.21.7/drivers/usb/gadget/pxa2xx_udc.c -@@ -2752,8 +2752,16 @@ static struct platform_driver udc_driver - }, - }; - -+#ifdef CONFIG_ARCH_GUMSTIX -+extern void gumstix_usb_gadget_load(void); -+#endif -+ - static int __init udc_init(void) - { -+#ifdef CONFIG_ARCH_GUMSTIX -+ gumstix_usb_gadget_load(); -+#endif -+ - printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION); - return platform_driver_register(&udc_driver); - } -Index: linux-2.6.21.7/drivers/usb/gadget/gumstix_gadget.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/drivers/usb/gadget/gumstix_gadget.c -@@ -0,0 +1,49 @@ -+/* -+ * Gumstix USB gadget intialization driver -+ * -+ * Author: Craig Hughes -+ * Created: December 9, 2004 -+ * Copyright: (C) 2004 Craig Hughes -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ */ -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+int __init gumstix_usb_gadget_init(void) -+{ -+ pxa_gpio_mode(GPIO_GUMSTIX_USB_GPIOx_DIS_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_USB_GPIOn_MD); -+ -+ set_irq_type(GUMSTIX_USB_INTR_IRQ, IRQT_BOTHEDGE); -+ -+ return 0; -+} -+ -+void __exit gumstix_usb_gadget_exit(void) -+{ -+} -+ -+void gumstix_usb_gadget_load(void) {} -+EXPORT_SYMBOL(gumstix_usb_gadget_load); -+ -+module_init(gumstix_usb_gadget_init); -+module_exit(gumstix_usb_gadget_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Craig Hughes "); -+MODULE_DESCRIPTION("Gumstix board USB gadget initialization driver"); -+MODULE_VERSION("1:0.1"); diff --git a/target/linux/pxa/patches-2.6.21/020-bugfix-i2c-include.patch b/target/linux/pxa/patches-2.6.21/020-bugfix-i2c-include.patch deleted file mode 100644 index fea6a938ee..0000000000 --- a/target/linux/pxa/patches-2.6.21/020-bugfix-i2c-include.patch +++ /dev/null @@ -1,12 +0,0 @@ -Index: linux-2.6.21.7/drivers/i2c/busses/i2c-pxa.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/i2c/busses/i2c-pxa.c -+++ linux-2.6.21.7/drivers/i2c/busses/i2c-pxa.c -@@ -32,6 +32,7 @@ - #include - #include - -+#include - #include - #include - #include diff --git a/target/linux/pxa/patches-2.6.21/021-bugfix-mmc-clock.patch b/target/linux/pxa/patches-2.6.21/021-bugfix-mmc-clock.patch deleted file mode 100644 index 9fc6d19842..0000000000 --- a/target/linux/pxa/patches-2.6.21/021-bugfix-mmc-clock.patch +++ /dev/null @@ -1,14 +0,0 @@ -Index: linux-2.6.21.7/drivers/mmc/pxamci.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/mmc/pxamci.c -+++ linux-2.6.21.7/drivers/mmc/pxamci.c -@@ -366,8 +366,7 @@ static void pxamci_set_ios(struct mmc_ho - - if (ios->clock) { - unsigned int clk = CLOCKRATE / ios->clock; -- if (CLOCKRATE / clk > ios->clock) -- clk <<= 1; -+ if(clk > (1<<6)) clk = (1<<6); - host->clkrt = fls(clk) - 1; - pxa_set_cken(CKEN12_MMC, 1); - diff --git a/target/linux/pxa/patches-2.6.21/022-bugfix-pxa-cpufreq.patch b/target/linux/pxa/patches-2.6.21/022-bugfix-pxa-cpufreq.patch deleted file mode 100644 index 2776e85bba..0000000000 --- a/target/linux/pxa/patches-2.6.21/022-bugfix-pxa-cpufreq.patch +++ /dev/null @@ -1,64 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/mach-pxa/cpu-pxa.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/cpu-pxa.c -+++ linux-2.6.21.7/arch/arm/mach-pxa/cpu-pxa.c -@@ -60,7 +60,7 @@ typedef struct - - /* Define the refresh period in mSec for the SDRAM and the number of rows */ - #define SDRAM_TREF 64 /* standard 64ms SDRAM */ --#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ -+#define SDRAM_ROWS 8192 /* 64MB=8192 32MB=4096 */ - #define MDREFR_DRI(x) ((x*SDRAM_TREF)/(SDRAM_ROWS*32)) - - #define CCLKCFG_TURBO 0x1 -@@ -136,7 +136,7 @@ static int pxa_set_target(struct cpufreq - unsigned int relation) - { - int idx; -- unsigned long cpus_allowed; -+ cpumask_t cpus_allowed; - int cpu = policy->cpu; - struct cpufreq_freqs freqs; - pxa_freqs_t *pxa_freq_settings; -@@ -144,6 +144,7 @@ static int pxa_set_target(struct cpufreq - unsigned long flags; - unsigned int unused; - unsigned int preset_mdrefr, postset_mdrefr; -+ void *ramstart; - - /* - * Save this threads cpus_allowed mask. -@@ -154,7 +155,7 @@ static int pxa_set_target(struct cpufreq - * Bind to the specified CPU. When this call returns, - * we should be running on the right CPU. - */ -- set_cpus_allowed(current, 1 << cpu); -+ set_cpus_allowed(current, cpumask_of_cpu(cpu)); - BUG_ON(cpu != smp_processor_id()); - - /* Get the current policy */ -@@ -187,7 +188,7 @@ static int pxa_set_target(struct cpufreq - (pxa_freq_settings[idx].membus/1000)); - } - -- void *ramstart = phys_to_virt(0xa0000000); -+ ramstart = phys_to_virt(0xa0000000); - - /* - * Tell everyone what we're about to do... -@@ -260,13 +261,13 @@ static int pxa_set_target(struct cpufreq - - static int pxa_cpufreq_init(struct cpufreq_policy *policy) - { -- unsigned long cpus_allowed; -+ cpumask_t cpus_allowed; - unsigned int cpu = policy->cpu; - int i; - - cpus_allowed = current->cpus_allowed; - -- set_cpus_allowed(current, 1 << cpu); -+ set_cpus_allowed(current, cpumask_of_cpu(cpu)); - BUG_ON(cpu != smp_processor_id()); - - /* set default policy and cpuinfo */ diff --git a/target/linux/pxa/patches-2.6.21/023-bugfix-serial-interrupt.patch b/target/linux/pxa/patches-2.6.21/023-bugfix-serial-interrupt.patch deleted file mode 100644 index 042aa02414..0000000000 --- a/target/linux/pxa/patches-2.6.21/023-bugfix-serial-interrupt.patch +++ /dev/null @@ -1,25 +0,0 @@ -Index: linux-2.6.21.7/drivers/serial/pxa.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/serial/pxa.c -+++ linux-2.6.21.7/drivers/serial/pxa.c -@@ -235,15 +235,19 @@ static inline irqreturn_t serial_pxa_irq - struct uart_pxa_port *up = dev_id; - unsigned int iir, lsr; - -+ serial_out(up, UART_MCR, serial_in(up, UART_MCR) & ~UART_MCR_RTS); // Clear RTS - iir = serial_in(up, UART_IIR); - if (iir & UART_IIR_NO_INT) -- return IRQ_NONE; -+ { -+ //printk(KERN_WARNING "serial_pxa_irq: odd -- interrupt triggered, but no interrupt in IIR: %08x\n",iir); -+ } - lsr = serial_in(up, UART_LSR); - if (lsr & UART_LSR_DR) - receive_chars(up, &lsr); - check_modem_status(up); - if (lsr & UART_LSR_THRE) - transmit_chars(up); -+ serial_out(up, UART_MCR, serial_in(up, UART_MCR) | UART_MCR_RTS); // Assert RTS - return IRQ_HANDLED; - } - diff --git a/target/linux/pxa/patches-2.6.21/024-bugfix-serial-register-status.patch b/target/linux/pxa/patches-2.6.21/024-bugfix-serial-register-status.patch deleted file mode 100644 index 46111d55d7..0000000000 --- a/target/linux/pxa/patches-2.6.21/024-bugfix-serial-register-status.patch +++ /dev/null @@ -1,69 +0,0 @@ -Index: linux-2.6.21.7/drivers/serial/pxa.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/serial/pxa.c -+++ linux-2.6.21.7/drivers/serial/pxa.c -@@ -57,6 +57,8 @@ struct uart_pxa_port { - unsigned int lsr_break_flag; - unsigned int cken; - char *name; -+ unsigned int msr; -+ unsigned int lsr; - }; - - static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) -@@ -159,6 +161,7 @@ static inline void receive_chars(struct - - ignore_char: - *status = serial_in(up, UART_LSR); -+ up->lsr = *status; - } while ((*status & UART_LSR_DR) && (max_count-- > 0)); - tty_flip_buffer_push(tty); - } -@@ -211,7 +214,7 @@ static inline void check_modem_status(st - int status; - - status = serial_in(up, UART_MSR); -- -+ up->msr = status; - if ((status & UART_MSR_ANY_DELTA) == 0) - return; - -@@ -242,6 +245,7 @@ static inline irqreturn_t serial_pxa_irq - //printk(KERN_WARNING "serial_pxa_irq: odd -- interrupt triggered, but no interrupt in IIR: %08x\n",iir); - } - lsr = serial_in(up, UART_LSR); -+ up->lsr = lsr; - if (lsr & UART_LSR_DR) - receive_chars(up, &lsr); - check_modem_status(up); -@@ -258,7 +262,7 @@ static unsigned int serial_pxa_tx_empty( - unsigned int ret; - - spin_lock_irqsave(&up->port.lock, flags); -- ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; -+ ret = up->lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0; - spin_unlock_irqrestore(&up->port.lock, flags); - - return ret; -@@ -270,7 +274,7 @@ static unsigned int serial_pxa_get_mctrl - unsigned char status; - unsigned int ret; - -- status = serial_in(up, UART_MSR); -+ status = up->msr; - - ret = 0; - if (status & UART_MSR_DCD) -@@ -400,10 +404,10 @@ static int serial_pxa_startup(struct uar - /* - * And clear the interrupt registers again for luck. - */ -- (void) serial_in(up, UART_LSR); -+ up->lsr = serial_in(up, UART_LSR); - (void) serial_in(up, UART_RX); - (void) serial_in(up, UART_IIR); -- (void) serial_in(up, UART_MSR); -+ up->msr = serial_in(up, UART_MSR); - - return 0; - } diff --git a/target/linux/pxa/patches-2.6.21/025-mach-types-fix.patch b/target/linux/pxa/patches-2.6.21/025-mach-types-fix.patch deleted file mode 100644 index faf04a4c42..0000000000 --- a/target/linux/pxa/patches-2.6.21/025-mach-types-fix.patch +++ /dev/null @@ -1,13 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/tools/mach-types -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/tools/mach-types -+++ linux-2.6.21.7/arch/arm/tools/mach-types -@@ -387,7 +387,7 @@ s5c7375 ARCH_S5C7375 S5C7375 369 - spearhead ARCH_SPEARHEAD SPEARHEAD 370 - pantera ARCH_PANTERA PANTERA 371 - prayoglite ARCH_PRAYOGLITE PRAYOGLITE 372 --gumstix ARCH_GUMSTIK GUMSTIK 373 -+gumstix ARCH_GUMSTIX GUMSTIX 373 - rcube ARCH_RCUBE RCUBE 374 - rea_olv ARCH_REA_OLV REA_OLV 375 - pxa_iphone ARCH_PXA_IPHONE PXA_IPHONE 376 diff --git a/target/linux/pxa/patches-2.6.21/026-pcm-gcc-411-bugfix.patch b/target/linux/pxa/patches-2.6.21/026-pcm-gcc-411-bugfix.patch deleted file mode 100644 index 2bfdffe1b1..0000000000 --- a/target/linux/pxa/patches-2.6.21/026-pcm-gcc-411-bugfix.patch +++ /dev/null @@ -1,60 +0,0 @@ -Index: linux-2.6.21.7/include/sound/pcm_params.h -=================================================================== ---- linux-2.6.21.7.orig/include/sound/pcm_params.h -+++ linux-2.6.21.7/include/sound/pcm_params.h -@@ -179,16 +179,8 @@ static inline int snd_mask_single(const - return 1; - } - --static inline int snd_mask_refine(struct snd_mask *mask, -- const struct snd_mask *v) --{ -- struct snd_mask old; -- snd_mask_copy(&old, mask); -- snd_mask_intersect(mask, v); -- if (snd_mask_empty(mask)) -- return -EINVAL; -- return !snd_mask_eq(mask, &old); --} -+void snd_mask_print( const struct snd_mask *m1, const struct snd_mask *m2 ); -+int snd_mask_refine(struct snd_mask *mask, const struct snd_mask *v); - - static inline int snd_mask_refine_first(struct snd_mask *mask) - { -Index: linux-2.6.21.7/sound/core/pcm_lib.c -=================================================================== ---- linux-2.6.21.7.orig/sound/core/pcm_lib.c -+++ linux-2.6.21.7/sound/core/pcm_lib.c -@@ -2128,3 +2128,18 @@ snd_pcm_sframes_t snd_pcm_lib_readv(stru - } - - EXPORT_SYMBOL(snd_pcm_lib_readv); -+ -+int snd_mask_refine(struct snd_mask *mask, -+ const struct snd_mask *v) -+{ -+ struct snd_mask old; -+ snd_mask_copy(&old, mask); -+ snd_mask_print(mask, v); -+ snd_mask_intersect(mask, v); -+ snd_mask_print(mask, v); -+ if (snd_mask_empty(mask)) -+ return -EINVAL; -+ return !snd_mask_eq(mask, &old); -+} -+ -+EXPORT_SYMBOL(snd_mask_refine); -Index: linux-2.6.21.7/sound/core/pcm_native.c -=================================================================== ---- linux-2.6.21.7.orig/sound/core/pcm_native.c -+++ linux-2.6.21.7/sound/core/pcm_native.c -@@ -3450,3 +3450,9 @@ const struct file_operations snd_pcm_f_o - .fasync = snd_pcm_fasync, - } - }; -+ -+void snd_mask_print( const struct snd_mask *m1, const struct snd_mask *m2 ) -+{ -+// printk( "0x%08x %08x v: 0x%08x %08x\n", m1->bits[1], m1->bits[0], m2->bits[1], m2->bits[0] ); -+} -+ diff --git a/target/linux/pxa/patches-2.6.21/027-ucb1400-ac97-audio.patch b/target/linux/pxa/patches-2.6.21/027-ucb1400-ac97-audio.patch deleted file mode 100644 index b6b965ab1b..0000000000 --- a/target/linux/pxa/patches-2.6.21/027-ucb1400-ac97-audio.patch +++ /dev/null @@ -1,298 +0,0 @@ -Index: linux-2.6.21.7/sound/pci/ac97/ac97_codec.c -=================================================================== ---- linux-2.6.21.7.orig/sound/pci/ac97/ac97_codec.c -+++ linux-2.6.21.7/sound/pci/ac97/ac97_codec.c -@@ -158,7 +158,7 @@ static const struct ac97_codec_id snd_ac - { 0x4e534300, 0xffffffff, "LM4540,43,45,46,48", NULL, NULL }, // only guess --jk - { 0x4e534331, 0xffffffff, "LM4549", NULL, NULL }, - { 0x4e534350, 0xffffffff, "LM4550", patch_lm4550, NULL }, // volume wrap fix --{ 0x50534304, 0xffffffff, "UCB1400", patch_ucb1400, NULL }, -+{ 0x50534304, 0xffffffff, "UCB1400", patch_ucb1400, NULL, AC97_HAS_NO_STD_PCM }, - { 0x53494c20, 0xffffffe0, "Si3036,8", mpatch_si3036, mpatch_si3036, AC97_MODEM_PATCH }, - { 0x54524102, 0xffffffff, "TR28022", NULL, NULL }, - { 0x54524106, 0xffffffff, "TR28026", NULL, NULL }, -Index: linux-2.6.21.7/sound/pci/ac97/ac97_patch.c -=================================================================== ---- linux-2.6.21.7.orig/sound/pci/ac97/ac97_patch.c -+++ linux-2.6.21.7/sound/pci/ac97/ac97_patch.c -@@ -29,6 +29,10 @@ - #include - #include - -+#include -+#include -+#include -+ - #include - #include - #include -@@ -406,6 +410,227 @@ int patch_yamaha_ymf753(struct snd_ac97 - } - - /* -+ * UCB1400 codec -+ */ -+ -+#define AC97_UCB1400_FCSR1 0x6a -+#define AC97_UCB1400_FCSR2 0x6c -+ -+static const struct snd_kcontrol_new ucb1400_snd_ac97_controls[] = { -+ AC97_SINGLE("Tone Control - Bass", AC97_UCB1400_FCSR1, 11, 4, 0), -+ AC97_SINGLE("Tone Control - Treble", AC97_UCB1400_FCSR1, 9, 2, 0), -+ AC97_SINGLE("Headphone Playback Switch", AC97_UCB1400_FCSR1, 6, 1, 0), -+ AC97_SINGLE("De-emphasis", AC97_UCB1400_FCSR1, 5, 1, 0), -+ AC97_SINGLE("DC Filter", AC97_UCB1400_FCSR1, 4, 1, 0), -+ AC97_SINGLE("Hi-pass Filter", AC97_UCB1400_FCSR1, 3, 1, 0), -+ AC97_SINGLE("ADC Filter", AC97_UCB1400_FCSR2, 12, 1, 0), -+}; -+ -+#define NUM_GPIO_LINES 10 -+ -+static struct proc_dir_entry *proc_gpio_parent; -+static struct proc_dir_entry *proc_gpios[NUM_GPIO_LINES]; -+ -+typedef struct -+{ -+ int gpio; -+ char name[32]; -+ struct snd_ac97 *ac97; -+} gpio_summary_type; -+ -+static gpio_summary_type gpio_summaries[NUM_GPIO_LINES] = -+{ -+ { 0, "UCB1400-0-0" }, -+ { 1, "UCB1400-0-1" }, -+ { 2, "UCB1400-0-2" }, -+ { 3, "UCB1400-0-3" }, -+ { 4, "UCB1400-0-4" }, -+ { 5, "UCB1400-0-5" }, -+ { 6, "UCB1400-0-6" }, -+ { 7, "UCB1400-0-7" }, -+ { 8, "UCB1400-0-8" }, -+ { 9, "UCB1400-0-9" } -+}; -+ -+ -+static int proc_ucb1400_ac97_gpio_write(struct file *file, const char __user *buf, -+ unsigned long count, void *data) -+{ -+ char *cur, lbuf[count + 1]; -+ gpio_summary_type *summary = data; -+ u32 direction_is_out, operation_is_set; -+ int i = summary->gpio; -+ u16 dir, value; -+ -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EACCES; -+ -+ memset(lbuf, 0, count + 1); -+ -+ if (copy_from_user(lbuf, buf, count)) -+ return -EFAULT; -+ -+ cur = lbuf; -+ -+ // Get current values -+ direction_is_out = !!(snd_ac97_read(summary->ac97, 0x5c) & (0x0001 << i)); -+ operation_is_set = !!(snd_ac97_read(summary->ac97, 0x5a) & (0x0001 << i)); -+ while(1) -+ { -+ // We accept options: {GPIO|AF1|AF2|AF3}, {set|clear}, {in|out} -+ // Anything else is an error -+ while(cur[0] && (isspace(cur[0]) || ispunct(cur[0]))) cur = &(cur[1]); -+ -+ if('\0' == cur[0]) break; -+ -+ // Ok, so now we're pointing at the start of something -+ switch(cur[0]) -+ { -+ case 'G': -+ // Check that next is "PIO" -- '\0' will cause safe short-circuit if end of buf -+ if(!(cur[1] == 'P' && cur[2] == 'I' && cur[3] == 'O')) goto parse_error; -+ cur = &(cur[4]); -+ break; -+ case 's': -+ if(!(cur[1] == 'e' && cur[2] == 't')) goto parse_error; -+ operation_is_set = 1; -+ cur = &(cur[3]); -+ break; -+ case 'c': -+ if(!(cur[1] == 'l' && cur[2] == 'e' && cur[3] == 'a' && cur[4] == 'r')) goto -+parse_error; -+ operation_is_set = 0; -+ cur = &(cur[5]); -+ break; -+ case 'i': -+ if(!(cur[1] == 'n')) goto parse_error; -+ direction_is_out = 0; -+ cur = &(cur[2]); -+ break; -+ case 'o': -+ if(!(cur[1] == 'u' && cur[2] == 't')) goto parse_error; -+ direction_is_out = 1; -+ cur = &(cur[3]); -+ break; -+ default: goto parse_error; -+ } -+ } -+ -+ // set/get value -+ dir = snd_ac97_read(summary->ac97, 0x5c); -+ value = snd_ac97_read(summary->ac97, 0x5a); -+ if (direction_is_out) -+ { -+ dir |= 0x0001 << i; -+ if (operation_is_set) -+ { -+ value |= 0x0001 << i; -+ } -+ else -+ { -+ value &= ~(0x0001 << i); -+ } -+ -+ snd_ac97_write(summary->ac97, 0x5c, dir); -+ snd_ac97_write(summary->ac97, 0x5a, value); -+ } -+ else // direction in -+ { -+ dir &= ~(0x0001 << i); -+ snd_ac97_write(summary->ac97, 0x5c, dir); -+ operation_is_set = snd_ac97_read(summary->ac97, 0x5a) & ~(0x0001 << i); -+ } -+ -+#ifdef CONFIG_PROC_GPIO_DEBUG -+ printk(KERN_INFO "Set (%s,%s,%s) via /proc/gpio/%s\n", -+ "GPIO", -+ direction_is_out ? "out" : "in", -+ operation_is_set ? "set" : "clear", -+ summary->name); -+#endif -+ -+ return count; -+ -+parse_error: -+ printk(KERN_CRIT "Parse error: Expect \"GPIO|[set|clear]|[in|out] ...\"\n"); -+ return -EINVAL; -+} -+ -+static int proc_ucb1400_ac97_gpio_read(char *page, char **start, off_t off, -+ int count, int *eof, void *data) -+{ -+ char *p = page; -+ gpio_summary_type *summary = data; -+ int len, i; /*, af;*/ -+ i = summary->gpio; -+ -+ p += sprintf(p, "%d\t%s\t%s\t%s\n", i, -+ "GPIO", -+ (snd_ac97_read(summary->ac97, 0x5c) & (0x0001 << i)) ? "out" : "in", -+ (snd_ac97_read(summary->ac97, 0x5a) & (0x0001 << i)) ? "set" : "clear"); -+ -+ len = (p - page) - off; -+ -+ if(len < 0) -+ { -+ len = 0; -+ } -+ -+ *eof = (len <= count) ? 1 : 0; -+ *start = page + off; -+ -+ return len; -+} -+ -+int patch_ucb1400(struct snd_ac97 * ac97) -+{ -+ int err, i; -+ -+ proc_gpio_parent = proc_mkdir("gpio", NULL); -+ if(!proc_gpio_parent) return 0; -+ -+ for(i=0; i < NUM_GPIO_LINES; i++) -+ { -+ proc_gpios[i] = create_proc_entry(gpio_summaries[i].name, 0644, proc_gpio_parent); -+ if(proc_gpios[i]) -+ { -+ gpio_summaries[i].ac97 = ac97; -+ proc_gpios[i]->data = &gpio_summaries[i]; -+ proc_gpios[i]->read_proc = proc_ucb1400_ac97_gpio_read; -+ proc_gpios[i]->write_proc = proc_ucb1400_ac97_gpio_write; -+ } -+ } -+ -+ for(i = 0; i < ARRAY_SIZE(ucb1400_snd_ac97_controls); i++) { -+ if((err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&ucb1400_snd_ac97_controls[i], ac97))) < 0) -+ return err; -+ } -+ -+ snd_ac97_write_cache(ac97, AC97_UCB1400_FCSR1, -+ (0 << 11) | // 0 base boost -+ (0 << 9) | // 0 treble boost -+ (0 << 7) | // Mode = flat -+ (1 << 6) | // Headphones enable -+ (0 << 5) | // De-emphasis disabled -+ (1 << 4) | // DC filter enabled -+ (1 << 3) | // Hi-pass filter enabled -+ (0 << 2) | // disable interrupt signalling via GPIO_INT -+ (1 << 0) // clear ADC overflow status if set -+ ); -+ -+ snd_ac97_write_cache(ac97, AC97_UCB1400_FCSR2, -+ (0 << 15) | // must be 0 -+ (0 << 13) | // must be 0 -+ (1 << 12) | // ADC filter enabled -+ (0 << 10) | // must be 0 -+ (0 << 4) | // Smart low power mode on neither Codec nor PLL -+ (0 << 0) // must be 0 -+ ); -+ -+ return 0; -+} -+ -+/* - * May 2, 2003 Liam Girdwood - * removed broken wolfson00 patch. - * added support for WM9705,WM9708,WM9709,WM9710,WM9711,WM9712 and WM9717. -@@ -3408,41 +3633,3 @@ int patch_lm4550(struct snd_ac97 *ac97) - ac97->res_table = lm4550_restbl; - return 0; - } -- --/* -- * UCB1400 codec (http://www.semiconductors.philips.com/acrobat_download/datasheets/UCB1400-02.pdf) -- */ --static const struct snd_kcontrol_new snd_ac97_controls_ucb1400[] = { --/* enable/disable headphone driver which allows direct connection to -- stereo headphone without the use of external DC blocking -- capacitors */ --AC97_SINGLE("Headphone Driver", 0x6a, 6, 1, 0), --/* Filter used to compensate the DC offset is added in the ADC to remove idle -- tones from the audio band. */ --AC97_SINGLE("DC Filter", 0x6a, 4, 1, 0), --/* Control smart-low-power mode feature. Allows automatic power down -- of unused blocks in the ADC analog front end and the PLL. */ --AC97_SINGLE("Smart Low Power Mode", 0x6c, 4, 3, 0), --}; -- --static int patch_ucb1400_specific(struct snd_ac97 * ac97) --{ -- int idx, err; -- for (idx = 0; idx < ARRAY_SIZE(snd_ac97_controls_ucb1400); idx++) -- if ((err = snd_ctl_add(ac97->bus->card, snd_ctl_new1(&snd_ac97_controls_ucb1400[idx], ac97))) < 0) -- return err; -- return 0; --} -- --static struct snd_ac97_build_ops patch_ucb1400_ops = { -- .build_specific = patch_ucb1400_specific, --}; -- --int patch_ucb1400(struct snd_ac97 * ac97) --{ -- ac97->build_ops = &patch_ucb1400_ops; -- /* enable headphone driver and smart low power mode by default */ -- snd_ac97_write(ac97, 0x6a, 0x0050); -- snd_ac97_write(ac97, 0x6c, 0x0030); -- return 0; --} diff --git a/target/linux/pxa/patches-2.6.21/028-gumstix-asoc.patch b/target/linux/pxa/patches-2.6.21/028-gumstix-asoc.patch deleted file mode 100644 index 5e6d11fb12..0000000000 --- a/target/linux/pxa/patches-2.6.21/028-gumstix-asoc.patch +++ /dev/null @@ -1,224 +0,0 @@ -Index: linux-2.6.21.7/sound/soc/pxa/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/sound/soc/pxa/Kconfig -+++ linux-2.6.21.7/sound/soc/pxa/Kconfig -@@ -16,6 +16,7 @@ config SND_PXA2XX_SOC_AC97 - tristate - select AC97_BUS - select SND_SOC_AC97_BUS -+ select SND_PXA2XX_AC97 - - config SND_PXA2XX_SOC_I2S - tristate -@@ -56,4 +57,12 @@ config SND_PXA2XX_SOC_TOSA - Say Y if you want to add support for SoC audio on Sharp - Zaurus SL-C6000x models (Tosa). - -+config SND_PXA2XX_SOC_GUMSTIX -+ tristate "SoC AC97 Audio support for Gumstix" -+ depends on SND_PXA2XX_SOC && ARCH_GUMSTIX -+ select SND_PXA2XX_SOC_AC97 -+ select SND_SOC_AC97_CODEC -+ help -+ Say Y if you want to add support for SoC audio on Gumstix -+ - endmenu -Index: linux-2.6.21.7/sound/soc/pxa/Makefile -=================================================================== ---- linux-2.6.21.7.orig/sound/soc/pxa/Makefile -+++ linux-2.6.21.7/sound/soc/pxa/Makefile -@@ -12,9 +12,11 @@ snd-soc-corgi-objs := corgi.o - snd-soc-poodle-objs := poodle.o - snd-soc-tosa-objs := tosa.o - snd-soc-spitz-objs := spitz.o -+snd-soc-gumstix-objs := gumstix.o - - obj-$(CONFIG_SND_PXA2XX_SOC_CORGI) += snd-soc-corgi.o - obj-$(CONFIG_SND_PXA2XX_SOC_POODLE) += snd-soc-poodle.o - obj-$(CONFIG_SND_PXA2XX_SOC_TOSA) += snd-soc-tosa.o - obj-$(CONFIG_SND_PXA2XX_SOC_SPITZ) += snd-soc-spitz.o -+obj-$(CONFIG_SND_PXA2XX_SOC_GUMSTIX) += snd-soc-gumstix.o - -Index: linux-2.6.21.7/sound/soc/pxa/gumstix.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/sound/soc/pxa/gumstix.c -@@ -0,0 +1,109 @@ -+/* -+ * gumstix.c -- SoC audio for Gumstix -+ * -+ * Copyright 2005 Wolfson Microelectronics PLC. -+ * Copyright 2005 Openedhand Ltd. -+ * Copyright 2007 Gumstix Inc. -+ * -+ * Authors: Liam Girdwood -+ * Richard Purdie -+ * Craig Hughes -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * Revision history -+ * 26 April 2007 - Initial revision forked from tosa.c -+ * -+ * -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "pxa2xx-pcm.h" -+#include "pxa2xx-ac97.h" -+#include "../codecs/ac97.h" -+ -+static struct snd_soc_machine gumstix; -+ -+static int gumstix_ac97_init(struct snd_soc_codec *codec) -+{ -+ // For now, do nothing -- should move the ucb1400 patch stuff here -+ return 0; -+} -+ -+/* For right now, just add UCB1400 -- once that's working, we can also add -+ * PCM channels via SPI to bluetooth module, GSM module, or whatnot */ -+static struct snd_soc_dai_link gumstix_dai[] = { -+{ -+ .name = "ucb1400", -+ .stream_name = "UCB1400", -+ .cpu_dai = &pxa_ac97_dai[PXA2XX_DAI_AC97_HIFI], -+ .codec_dai = &ac97_dai, -+ .init = gumstix_ac97_init, -+}, -+}; -+ -+static struct snd_soc_machine snd_soc_machine_gumstix = { -+ .name = "Gumstix", -+ .dai_link = gumstix_dai, -+ .num_links = ARRAY_SIZE(gumstix_dai), -+}; -+ -+static struct snd_soc_device gumstix_snd_devdata = { -+ .machine = &snd_soc_machine_gumstix, -+ .platform = &pxa2xx_soc_platform, -+ .codec_dev = &soc_codec_dev_ac97, -+}; -+ -+static struct platform_device *gumstix_snd_device; -+ -+static int __init gumstix_init(void) -+{ -+ int ret; -+ -+ if (!machine_is_gumstix()) -+ return -ENODEV; -+ -+ gumstix_snd_device = platform_device_alloc("soc-audio", -1); -+ if (!gumstix_snd_device) -+ return -ENOMEM; -+ -+ platform_set_drvdata(gumstix_snd_device, &gumstix_snd_devdata); -+ gumstix_snd_devdata.dev = &gumstix_snd_device->dev; -+ ret = platform_device_add(gumstix_snd_device); -+ -+ if (ret) -+ platform_device_put(gumstix_snd_device); -+ -+ return ret; -+} -+ -+static void __exit gumstix_exit(void) -+{ -+ platform_device_unregister(gumstix_snd_device); -+} -+ -+module_init(gumstix_init); -+module_exit(gumstix_exit); -+ -+/* Module information */ -+MODULE_AUTHOR("Craig Hughes "); -+MODULE_DESCRIPTION("ALSA SoC Gumstix"); -+MODULE_LICENSE("GPL"); -Index: linux-2.6.21.7/sound/soc/codecs/ac97.c -=================================================================== ---- linux-2.6.21.7.orig/sound/soc/codecs/ac97.c -+++ linux-2.6.21.7/sound/soc/codecs/ac97.c -@@ -43,7 +43,7 @@ static int ac97_prepare(struct snd_pcm_s - #define STD_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ - SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) - --static struct snd_soc_codec_dai ac97_dai = { -+struct snd_soc_codec_dai ac97_dai = { - .name = "AC97 HiFi", - .playback = { - .stream_name = "AC97 Playback", -@@ -61,6 +61,8 @@ static struct snd_soc_codec_dai ac97_dai - .prepare = ac97_prepare,}, - }; - -+EXPORT_SYMBOL_GPL(ac97_dai); -+ - static unsigned int ac97_read(struct snd_soc_codec *codec, - unsigned int reg) - { -Index: linux-2.6.21.7/sound/soc/codecs/ac97.h -=================================================================== ---- linux-2.6.21.7.orig/sound/soc/codecs/ac97.h -+++ linux-2.6.21.7/sound/soc/codecs/ac97.h -@@ -14,5 +14,6 @@ - #define __LINUX_SND_SOC_AC97_H - - extern struct snd_soc_codec_device soc_codec_dev_ac97; -+extern struct snd_soc_codec_dai ac97_dai; - - #endif -Index: linux-2.6.21.7/sound/soc/pxa/pxa2xx-ac97.c -=================================================================== ---- linux-2.6.21.7.orig/sound/soc/pxa/pxa2xx-ac97.c -+++ linux-2.6.21.7/sound/soc/pxa/pxa2xx-ac97.c -@@ -154,18 +154,26 @@ static void pxa2xx_ac97_warm_reset(struc - - static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97) - { -- GCR &= GCR_COLD_RST; /* clear everything but nCRST */ -- GCR &= ~GCR_COLD_RST; /* then assert nCRST */ -- -- gsr_bits = 0; - #ifdef CONFIG_PXA27x - /* PXA27x Developers Manual section 13.5.2.2.1 */ -+ GCR |= GCR_ACLINK_OFF; -+ udelay(5); -+ GCR &= GCR_COLD_RST; /* Mask all interrupts */ -+ GCR &= ~GCR_COLD_RST; /* cold reset */ -+ udelay(5); - pxa_set_cken(1 << 31, 1); - udelay(5); -- pxa_set_cken(1 << 31, 0); -+ GCR |= GCR_PRIRDY_IEN|GCR_SECRDY_IEN; /* unmask the interrupts */ -+ pxa_set_cken(1 << 31, 0); /* clear CKEN31 */ -+ udelay(5); - GCR = GCR_COLD_RST; - udelay(50); -+ wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); - #else -+ GCR &= GCR_COLD_RST; /* clear everything but nCRST */ -+ GCR &= ~GCR_COLD_RST; /* then assert nCRST */ -+ -+ gsr_bits = 0; - GCR = GCR_COLD_RST; - GCR |= GCR_CDONE_IE|GCR_SDONE_IE; - wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); diff --git a/target/linux/pxa/patches-2.6.21/029-disable-uncompress-message.patch b/target/linux/pxa/patches-2.6.21/029-disable-uncompress-message.patch deleted file mode 100644 index 0fd97fd527..0000000000 --- a/target/linux/pxa/patches-2.6.21/029-disable-uncompress-message.patch +++ /dev/null @@ -1,32 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/boot/compressed/misc.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/boot/compressed/misc.c -+++ linux-2.6.21.7/arch/arm/boot/compressed/misc.c -@@ -322,7 +322,6 @@ void flush_window(void) - bytes_out += (ulg)outcnt; - output_ptr += (ulg)outcnt; - outcnt = 0; -- putstr("."); - } - - #ifndef arch_error -@@ -354,9 +353,7 @@ decompress_kernel(ulg output_start, ulg - arch_decomp_setup(); - - makecrc(); -- putstr("Uncompressing Linux..."); - gunzip(); -- putstr(" done, booting the kernel.\n"); - return output_ptr; - } - #else -@@ -368,9 +365,7 @@ int main() - output_data = output_buffer; - - makecrc(); -- putstr("Uncompressing Linux..."); - gunzip(); -- putstr("done.\n"); - return 0; - } - #endif diff --git a/target/linux/pxa/patches-2.6.21/030-serial-divisor.patch b/target/linux/pxa/patches-2.6.21/030-serial-divisor.patch deleted file mode 100644 index 036fb634cd..0000000000 --- a/target/linux/pxa/patches-2.6.21/030-serial-divisor.patch +++ /dev/null @@ -1,31 +0,0 @@ -Index: linux-2.6.21.7/drivers/serial/pxa.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/serial/pxa.c -+++ linux-2.6.21.7/drivers/serial/pxa.c -@@ -41,6 +41,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -577,8 +578,16 @@ static void serial_pxa_config_port(struc - static int - serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) - { -- /* we don't want the core code to modify any port params */ -- return -EINVAL; -+ struct uart_pxa_port *up = (struct uart_pxa_port *)port; -+ int ret = 0; -+ -+ if (up->port.uartclk / 16 != ser->baud_base) -+ ret = -EINVAL; -+ else if (((up->port.line & 1) == 0) && ser->baud_base > 230400) /* Max baud rate for STUART and FFUART */ -+ ret = -EINVAL; -+ else if (((up->port.line & 1) != 0) && ser->baud_base > 921600) /* Max baud rate for HWUART and BTUART */ -+ ret = -EINVAL; -+ return ret; - } - - static const char * diff --git a/target/linux/pxa/patches-2.6.21/031-mmc-card-detect.patch b/target/linux/pxa/patches-2.6.21/031-mmc-card-detect.patch deleted file mode 100644 index 9954ed8438..0000000000 --- a/target/linux/pxa/patches-2.6.21/031-mmc-card-detect.patch +++ /dev/null @@ -1,80 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/gumstix.c -+++ linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -@@ -29,19 +29,55 @@ - - #include "generic.h" - --static int gumstix_mci_init(struct device *dev, irqreturn_t (*lubbock_detect_int)(int, void *, struct pt_regs *), void *data) -+static struct pxamci_platform_data gumstix_mci_platform_data; -+ -+static int gumstix_mci_init(struct device *dev, irqreturn_t (*gumstix_detect_int)(int, void *, struct pt_regs *), void *data) - { -- // Set up MMC controller -+ int err; -+ - pxa_gpio_mode(GPIO6_MMCCLK_MD); - pxa_gpio_mode(GPIO53_MMCCLK_MD); - pxa_gpio_mode(GPIO8_MMCCS0_MD); - -+ pxa_gpio_mode(GUMSTIX_GPIO_nSD_DETECT | GPIO_IN); -+ set_irq_type(GUMSTIX_IRQ_GPIO_nSD_DETECT, IRQT_BOTHEDGE); -+ pxa_gpio_mode(GUMSTIX_GPIO_nSD_WP | GPIO_IN); -+ -+ gumstix_mci_platform_data.detect_delay = msecs_to_jiffies(250); -+ -+ err = request_irq(GUMSTIX_IRQ_GPIO_nSD_DETECT, gumstix_detect_int, SA_INTERRUPT, -+ "MMC card detect", data); -+ if (err) { -+ printk(KERN_ERR "gumstix_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); -+ return -1; -+ } -+ -+ err = set_irq_type(GUMSTIX_IRQ_GPIO_nSD_DETECT, IRQT_BOTHEDGE); -+ - return 0; - } - -+static int gumstix_mci_get_ro(struct device *dev) -+{ -+#ifdef CONFIG_ARCH_GUMSTIX_VERDEX -+ return 0; // microSD is always writable on verdex -+#else -+ int ro; -+ ro = GPLR(GUMSTIX_GPIO_nSD_WP) & GPIO_bit(GUMSTIX_GPIO_nSD_WP); -+ return ro; -+#endif -+} -+ -+static void gumstix_mci_exit(struct device *dev, void *data) -+{ -+ free_irq(GUMSTIX_IRQ_GPIO_nSD_DETECT, data); -+} -+ - static struct pxamci_platform_data gumstix_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, -- .init = &gumstix_mci_init, -+ .init = gumstix_mci_init, -+ .get_ro = gumstix_mci_get_ro, -+ .exit = gumstix_mci_exit, - }; - - static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = { -Index: linux-2.6.21.7/include/asm-arm/arch-pxa/gumstix.h -=================================================================== ---- linux-2.6.21.7.orig/include/asm-arm/arch-pxa/gumstix.h -+++ linux-2.6.21.7/include/asm-arm/arch-pxa/gumstix.h -@@ -36,6 +36,12 @@ - #define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT) - #define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN) - -+/* -+ * SD/MMC definitions -+ */ -+#define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */ -+#define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */ -+#define GUMSTIX_IRQ_GPIO_nSD_DETECT IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT) - - /* - * SMC Ethernet definitions diff --git a/target/linux/pxa/patches-2.6.21/032-misalignment-handling.patch b/target/linux/pxa/patches-2.6.21/032-misalignment-handling.patch deleted file mode 100644 index dca1cbed0d..0000000000 --- a/target/linux/pxa/patches-2.6.21/032-misalignment-handling.patch +++ /dev/null @@ -1,38 +0,0 @@ -Change the default alingment handling to not be silent failure -Index: linux-2.6.21.7/arch/arm/mm/alignment.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mm/alignment.c -+++ linux-2.6.21.7/arch/arm/mm/alignment.c -@@ -797,6 +797,8 @@ static int __init alignment_init(void) - res->write_proc = proc_alignment_write; - #endif - -+ ai_usermode = CONFIG_ALIGNMENT_HANDLING; -+ - hook_fault_code(1, do_alignment, SIGILL, "alignment exception"); - hook_fault_code(3, do_alignment, SIGILL, "alignment exception"); - -Index: linux-2.6.21.7/arch/arm/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/Kconfig -+++ linux-2.6.21.7/arch/arm/Kconfig -@@ -709,6 +709,19 @@ config ALIGNMENT_TRAP - correct operation of some network protocols. With an IP-only - configuration it is safe to say N, otherwise say Y. - -+config ALIGNMENT_HANDLING -+ hex "Userspace alignment trap handling" -+ default "0x3" -+ depends on ALIGNMENT_TRAP -+ help -+ How should we handle alignment errors in userspace by default? This is a bitfield where: -+ 0 - silently ignore alignment errors (will lead to unexpected results) -+ 1 - report alignment errors through printk (will lead to unexpected results, but you'll know about them) -+ 2 - fix the alignment and make things work properly (performance degradation for un-aligned code) -+ 4 - raise SIGBUS on alignment traps -+ A good number to choose is probably either 3 (work slowly but log message) or 5 (log message and SIGBUS). -+ You can change the behavior at runtime through /proc/cpu/alignment if you have PROC_FS enabled. -+ - endmenu - - menu "Boot options" diff --git a/target/linux/pxa/patches-2.6.21/033-compile-fix-pxa_cpufreq.patch b/target/linux/pxa/patches-2.6.21/033-compile-fix-pxa_cpufreq.patch deleted file mode 100644 index 4ef55a3332..0000000000 --- a/target/linux/pxa/patches-2.6.21/033-compile-fix-pxa_cpufreq.patch +++ /dev/null @@ -1,13 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/mach-pxa/cpu-pxa.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/cpu-pxa.c -+++ linux-2.6.21.7/arch/arm/mach-pxa/cpu-pxa.c -@@ -42,7 +42,7 @@ - - #define DEBUG 0 - --#ifdef DEBUG -+#if defined (DEBUG) && DEBUG > 0 - static unsigned int freq_debug = DEBUG; - MODULE_PARM(freq_debug, "i"); - MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); diff --git a/target/linux/pxa/patches-2.6.21/034-ramfs-mode-support.patch b/target/linux/pxa/patches-2.6.21/034-ramfs-mode-support.patch deleted file mode 100644 index d8fa62edcf..0000000000 --- a/target/linux/pxa/patches-2.6.21/034-ramfs-mode-support.patch +++ /dev/null @@ -1,88 +0,0 @@ -Index: linux-2.6.21.7/fs/ramfs/inode.c -=================================================================== ---- linux-2.6.21.7.orig/fs/ramfs/inode.c -+++ linux-2.6.21.7/fs/ramfs/inode.c -@@ -33,6 +33,7 @@ - #include - #include - #include -+#include - - #include - #include "internal.h" -@@ -160,10 +161,66 @@ static const struct super_operations ram - .drop_inode = generic_delete_inode, - }; - -+static int ramfs_parse_options(char *options, int *mode) -+{ -+ char *this_char, *value, *rest; -+ -+ while (options != NULL) { -+ this_char = options; -+ for (;;) { -+ /* -+ * NUL-terminate this option: unfortunately, -+ * mount options form a comma-separated list, -+ * but mpol's nodelist may also contain commas. -+ */ -+ options = strchr(options, ','); -+ if (options == NULL) -+ break; -+ options++; -+ if (!isdigit(*options)) { -+ options[-1] = '\0'; -+ break; -+ } -+ } -+ if (!*this_char) -+ continue; -+ if ((value = strchr(this_char,'=')) != NULL) { -+ *value++ = 0; -+ } else { -+ printk(KERN_ERR -+ "ramfs: No value for mount option '%s'\n", -+ this_char); -+ return 1; -+ } -+ -+ if (!strcmp(this_char,"mode")) { -+ if (!mode) -+ continue; -+ *mode = simple_strtoul(value,&rest,8); -+ if (*rest) -+ goto bad_val; -+ } else { -+ printk(KERN_ERR "ramfs: Bad mount option %s\n", -+ this_char); -+ return 1; -+ } -+ } -+ return 0; -+ -+bad_val: -+ printk(KERN_ERR "ramfs: Bad value '%s' for mount option '%s'\n", -+ value, this_char); -+ return 1; -+} -+ - static int ramfs_fill_super(struct super_block * sb, void * data, int silent) - { - struct inode * inode; - struct dentry * root; -+ int mode = 0755; -+ -+ if (ramfs_parse_options(data, &mode)) -+ return -EINVAL; - - sb->s_maxbytes = MAX_LFS_FILESIZE; - sb->s_blocksize = PAGE_CACHE_SIZE; -@@ -171,7 +228,7 @@ static int ramfs_fill_super(struct super - sb->s_magic = RAMFS_MAGIC; - sb->s_op = &ramfs_ops; - sb->s_time_gran = 1; -- inode = ramfs_get_inode(sb, S_IFDIR | 0755, 0); -+ inode = ramfs_get_inode(sb, S_IFDIR | mode, 0); - if (!inode) - return -ENOMEM; - diff --git a/target/linux/pxa/patches-2.6.21/035-pxafb-definition.patch b/target/linux/pxa/patches-2.6.21/035-pxafb-definition.patch deleted file mode 100644 index e45dad3aed..0000000000 --- a/target/linux/pxa/patches-2.6.21/035-pxafb-definition.patch +++ /dev/null @@ -1,180 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/gumstix.c -+++ linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -@@ -25,6 +25,7 @@ - #include - #include - #include -+#include - #include - - #include "generic.h" -@@ -90,6 +91,89 @@ static struct platform_device gum_audio_ - .id = -1, - }; - -+ -+#if defined(CONFIG_FB_PXA_SHARP_LQ043_PSP) || defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C) -+static void gumstix_lcd_backlight(int on_or_off) -+{ -+ if(on_or_off) -+ { -+ pxa_gpio_mode(17 | GPIO_IN); -+ } else { -+ GPCR(17) = GPIO_bit(17); -+ pxa_gpio_mode(17 | GPIO_OUT); -+ GPCR(17) = GPIO_bit(17); -+ } -+} -+#endif -+ -+ -+#ifdef CONFIG_FB_PXA_ALPS_CDOLLAR -+static struct pxafb_mode_info gumstix_fb_mode = { -+ .pixclock = 300000, -+ .xres = 240, -+ .yres = 320, -+ .bpp = 16, -+ .hsync_len = 2, -+ .left_margin = 1, -+ .right_margin = 1, -+ .vsync_len = 3, -+ .upper_margin = 0, -+ .lower_margin = 0, -+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+}; -+ -+static struct pxafb_mach_info gumstix_fb_info = { -+ .modes = &gumstix_fb_mode, -+ .num_modes = 1, -+ .lccr0 = LCCR0_Pas | LCCR0_Sngl | LCCR0_Color, -+ .lccr3 = 0, -+}; -+#elif defined(CONFIG_FB_PXA_SHARP_LQ043_PSP) -+static struct pxafb_mode_info gumstix_fb_mode = { -+ .pixclock = 110000, -+ .xres = 480, -+ .yres = 272, -+ .bpp = 16, -+ .hsync_len = 41, -+ .left_margin = 2, -+ .right_margin = 2, -+ .vsync_len = 10, -+ .upper_margin = 2, -+ .lower_margin = 2, -+ .sync = 0, // Hsync and Vsync both active low -+}; -+ -+static struct pxafb_mach_info gumstix_fb_info = { -+ .modes = &gumstix_fb_mode, -+ .num_modes = 1, -+ .lccr0 = LCCR0_Act | LCCR0_Sngl | LCCR0_Color, -+ .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | (3 << 30), -+ .pxafb_backlight_power = &gumstix_lcd_backlight, -+}; -+#elif defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C) -+static struct pxafb_mode_info gumstix_fb_mode = { -+ .pixclock = 108696, // 9.2MHz typical DOTCLK from datasheet -+ .xres = 480, -+ .hsync_len = 41, // HLW from datasheet: 41 typ -+ .left_margin = 4, // HBP - HLW from datasheet: 45 - 41 = 4 -+ .right_margin = 8, // HFP from datasheet: 8 typ -+ .yres = 272, -+ .vsync_len = 10, // VLW from datasheet: 10 typ -+ .upper_margin = 2, // VBP - VLW from datasheet: 12 - 10 = 2 -+ .lower_margin = 4, // VFP from datasheet: 4 typ -+ .bpp = 16, -+ .sync = 0, // Hsync and Vsync both active low -+}; -+ -+static struct pxafb_mach_info gumstix_fb_info = { -+ .modes = &gumstix_fb_mode, -+ .num_modes = 1, -+ .lccr0 = LCCR0_Act | LCCR0_Sngl | LCCR0_Color, -+ .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | (3 << 30), -+ .pxafb_backlight_power = &gumstix_lcd_backlight, -+}; -+#endif -+ - static struct platform_device *devices[] __initdata = { - &gum_audio_device, - }; -@@ -98,6 +182,9 @@ static void __init gumstix_init(void) - { - pxa_set_mci_info(&gumstix_mci_platform_data); - pxa_set_udc_info(&gumstix_udc_info); -+#if defined(CONFIG_FB_PXA_ALPS_CDOLLAR) | defined(CONFIG_FB_PXA_SHARP_LQ043_PSP) | defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C) -+ set_pxa_fb_info(&gumstix_fb_info); -+#endif - (void) platform_add_devices(devices, ARRAY_SIZE(devices)); - } - -Index: linux-2.6.21.7/drivers/video/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/drivers/video/Kconfig -+++ linux-2.6.21.7/drivers/video/Kconfig -@@ -1495,6 +1495,37 @@ config FB_PXA - - If unsure, say N. - -+choice -+ depends on FB_PXA -+ prompt "LCD Panel" -+ default FB_PXA_SAMSUNG_LTE430WQ_F0C -+ -+config FB_PXA_ALPS_CDOLLAR -+ boolean "Chris Dollar's ALPS screen" -+ ---help--- -+ Enable definitions (over-ridable on the kernel command line if -+ "PXA LCD command line parameters" is also selected) for an ALPS -+ screen which Chris Dollar uses -+ -+config FB_PXA_SHARP_LQ043_PSP -+ boolean "SHARP LQ043... series" -+ ---help--- -+ Enable definitions (over-ridable on the kernel command line if -+ "PXA LCD command line parameters" is also selected) for a SHARP -+ LQ043... screen, such as the one used by the PSP. These screens are -+ the ones normally sold by gumstix with its boards. -+ -+config FB_PXA_SAMSUNG_LTE430WQ_F0C -+ boolean "Samsung LTE430WQ-F0C (standard gumstix LCD)" -+ ---help--- -+ Enable definitions for a Samsung LTE430WQ-F0C LCD panel, such as the ones resold -+ by gumstix for use with their "LCD-Ready" boards. -+ -+config FB_PXA_NONEOFTHEABOVE -+ boolean "None of the above" -+ -+endchoice -+ - config FB_PXA_PARAMETERS - bool "PXA LCD command line parameters" - default n -Index: linux-2.6.21.7/drivers/video/pxafb.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/video/pxafb.c -+++ linux-2.6.21.7/drivers/video/pxafb.c -@@ -22,6 +22,7 @@ - * - */ - -+#include - #include - #include - #include -@@ -789,7 +790,13 @@ static void pxafb_setup_gpio(struct pxaf - pxa_gpio_mode(GPIO74_LCD_FCLK_MD); - pxa_gpio_mode(GPIO75_LCD_LCLK_MD); - pxa_gpio_mode(GPIO76_LCD_PCLK_MD); -+#ifdef CONFIG_FB_PXA_SHARP_LQ043_PSP -+ /* DISP must be always high while screen is on */ -+ pxa_gpio_mode(GPIO77_LCD_ACBIAS | GPIO_OUT); -+ GPSR(GPIO77_LCD_ACBIAS) = GPIO_bit(GPIO77_LCD_ACBIAS); -+#else - pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD); -+#endif - } - - static void pxafb_enable_controller(struct pxafb_info *fbi) diff --git a/target/linux/pxa/patches-2.6.21/036-270-usb-gadget-udc.patch b/target/linux/pxa/patches-2.6.21/036-270-usb-gadget-udc.patch deleted file mode 100644 index 7dcac4b7d0..0000000000 --- a/target/linux/pxa/patches-2.6.21/036-270-usb-gadget-udc.patch +++ /dev/null @@ -1,2739 +0,0 @@ -Index: linux-2.6.21.7/drivers/usb/gadget/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/Kconfig -+++ linux-2.6.21.7/drivers/usb/gadget/Kconfig -@@ -129,6 +129,28 @@ config USB_PXA2XX_SMALL - default y if USB_ETH - default y if USB_G_SERIAL - -+config USB_GADGET_PXA27X -+ boolean "PXA 27x" -+ depends on ARCH_PXA && PXA27x -+ help -+ Intel's PXA 27x series XScale ARM-5TE processors include -+ an integrated full speed USB 1.1 device controller. -+ -+ Say "y" to link the driver statically, or "m" to build a -+ dynamically linked module called "pxa27x_udc" and force all -+ gadget drivers to also be dynamically linked. -+ -+config USB_PXA27X -+ tristate -+ depends on USB_GADGET_PXA27X -+ default USB_GADGET -+ select USB_GADGET_SELECTED -+ -+config USB_PXA27X_DMA -+ bool # "Use DMA support" -+ depends on USB_GADGET_PXA27X -+ default n -+ - config USB_GADGET_GOKU - boolean "Toshiba TC86C001 'Goku-S'" - depends on PCI -Index: linux-2.6.21.7/drivers/usb/gadget/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/Makefile -+++ linux-2.6.21.7/drivers/usb/gadget/Makefile -@@ -7,6 +7,7 @@ obj-$(CONFIG_USB_PXA2XX) += pxa2xx_udc.o - obj-$(CONFIG_USB_GOKU) += goku_udc.o - obj-$(CONFIG_USB_OMAP) += omap_udc.o - obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o -+obj-$(CONFIG_USB_PXA27X) += pxa27x_udc.o - obj-$(CONFIG_USB_AT91) += at91_udc.o - obj-$(CONFIG_USB_GADGET_GUMSTIX) += gumstix_gadget.o - -Index: linux-2.6.21.7/drivers/usb/gadget/pxa27x_udc.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/drivers/usb/gadget/pxa27x_udc.c -@@ -0,0 +1,2352 @@ -+/* -+ * linux/drivers/usb/gadget/pxa27x_udc.c -+ * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers -+ * -+ * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) -+ * Copyright (C) 2003 Robert Schwebel, Pengutronix -+ * Copyright (C) 2003 Benedikt Spranger, Pengutronix -+ * Copyright (C) 2003 David Brownell -+ * Copyright (C) 2003 Joshua Wise -+ * Copyright (C) 2004 Intel Corporation -+ * Copyright (C) 2005 SDG Systems, LLC (Aric Blumer) -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ */ -+ -+#undef DEBUG -+ // #define DEBUG 1 -+ //#define VERBOSE DBG_VERBOSE -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+ -+/* -+ * This driver handles the USB Device Controller (UDC) in Intel's PXA 27777777x -+ * series processors. -+ * Such controller drivers work with a gadget driver. The gadget driver -+ * returns descriptors, implements configuration and data protocols used -+ * by the host to interact with this device, and allocates endpoints to -+ * the different protocol interfaces. The controller driver virtualizes -+ * usb hardware so that the gadget drivers will be more portable. -+ * -+ * This UDC hardware wants to implement a bit too much USB protocol, so -+ * it constrains the sorts of USB configuration change events that work. -+ * The errata for these chips are misleading; some "fixed" bugs from -+ * pxa250 a0/a1 b0/b1/b2 sure act like they're still there. -+ */ -+ -+#define DRIVER_VERSION "21-Jul-2005" -+#define DRIVER_DESC "PXA 27x USB Device Controller driver" -+ -+ -+static const char driver_name [] = "pxa27x_udc"; -+ -+static const char ep0name [] = "ep0"; -+ -+ -+#define USE_DMA -+//#define DISABLE_TEST_MODE -+ -+#ifdef CONFIG_PROC_FS -+#define UDC_PROC_FILE -+#endif -+ -+#include "pxa27x_udc.h" -+ -+#if 0 -+#ifdef CONFIG_EMBEDDED -+/* few strings, and little code to use them */ -+#undef DEBUG -+#undef UDC_PROC_FILE -+#endif -+#endif -+ -+#ifdef USE_DMA -+static int use_dma = 1; -+module_param(use_dma, bool, 0); -+MODULE_PARM_DESC (use_dma, "true to use dma"); -+ -+static void dma_nodesc_handler (int dmach, void *_ep); -+static void kick_dma(struct pxa27x_ep *ep, struct pxa27x_request *req); -+ -+#define DMASTR " (dma support)" -+ -+#else /* !USE_DMA */ -+#define DMASTR " (pio only)" -+#endif -+ -+#ifdef CONFIG_USB_PXA27X_SMALL -+#define SIZE_STR " (small)" -+#else -+#define SIZE_STR "" -+#endif -+ -+#ifdef DISABLE_TEST_MODE -+/* (mode == 0) == no undocumented chip tweaks -+ * (mode & 1) == double buffer bulk IN -+ * (mode & 2) == double buffer bulk OUT -+ * ... so mode = 3 (or 7, 15, etc) does it for both -+ */ -+static ushort fifo_mode = 0; -+module_param(fifo_mode, ushort, 0); -+MODULE_PARM_DESC (fifo_mode, "pxa27x udc fifo mode"); -+#endif -+ -+#define UDCISR0_IR0 0x3 -+#define UDCISR_INT_MASK (UDC_INT_FIFOERROR | UDC_INT_PACKETCMP) -+#define UDCICR_INT_MASK UDCISR_INT_MASK -+ -+#define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME) -+/* --------------------------------------------------------------------------- -+ * endpoint related parts of the api to the usb controller hardware, -+ * used by gadget driver; and the inner talker-to-hardware core. -+ * --------------------------------------------------------------------------- -+ */ -+ -+static void pxa27x_ep_fifo_flush (struct usb_ep *ep); -+static void nuke (struct pxa27x_ep *, int status); -+ -+static void pio_irq_enable(int ep_num) -+{ -+ if (ep_num < 16) -+ UDCICR0 |= 3 << (ep_num * 2); -+ else { -+ ep_num -= 16; -+ UDCICR1 |= 3 << (ep_num * 2); -+ } -+} -+ -+static void pio_irq_disable(int ep_num) -+{ -+ ep_num &= 0xf; -+ if (ep_num < 16) -+ UDCICR0 &= ~(3 << (ep_num * 2)); -+ else { -+ ep_num -= 16; -+ UDCICR1 &= ~(3 << (ep_num * 2)); -+ } -+} -+ -+/* The UDCCR reg contains mask and interrupt status bits, -+ * so using '|=' isn't safe as it may ack an interrupt. -+ */ -+#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE) -+ -+static inline void udc_set_mask_UDCCR(int mask) -+{ -+ UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS); -+} -+ -+static inline void udc_clear_mask_UDCCR(int mask) -+{ -+ UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS); -+} -+ -+static inline void udc_ack_int_UDCCR(int mask) -+{ -+ /* udccr contains the bits we dont want to change */ -+ __u32 udccr = UDCCR & UDCCR_MASK_BITS; -+ -+ UDCCR = udccr | (mask & ~UDCCR_MASK_BITS); -+} -+ -+/* -+ * endpoint enable/disable -+ * -+ * we need to verify the descriptors used to enable endpoints. since pxa27x -+ * endpoint configurations are fixed, and are pretty much always enabled, -+ * there's not a lot to manage here. -+ * -+ * because pxa27x can't selectively initialize bulk (or interrupt) endpoints, -+ * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except -+ * for a single interface (with only the default altsetting) and for gadget -+ * drivers that don't halt endpoints (not reset by set_interface). that also -+ * means that if you use ISO, you must violate the USB spec rule that all -+ * iso endpoints must be in non-default altsettings. -+ */ -+static int pxa27x_ep_enable (struct usb_ep *_ep, -+ const struct usb_endpoint_descriptor *desc) -+{ -+ struct pxa27x_ep *ep; -+ struct pxa27x_udc *dev; -+ -+ ep = container_of (_ep, struct pxa27x_ep, ep); -+ if (!_ep || !desc || _ep->name == ep0name -+ || desc->bDescriptorType != USB_DT_ENDPOINT -+ || ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) { -+ DMSG("%s, bad ep or descriptor\n", __FUNCTION__); -+ return -EINVAL; -+ } -+ -+ /* xfer types must match, except that interrupt ~= bulk */ -+ if( ep->ep_type != USB_ENDPOINT_XFER_BULK -+ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { -+ DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name); -+ return -EINVAL; -+ } -+ -+ /* hardware _could_ do smaller, but driver doesn't */ -+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK -+ && le16_to_cpu (desc->wMaxPacketSize) -+ != BULK_FIFO_SIZE) -+ || !desc->wMaxPacketSize) { -+ DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name); -+ return -ERANGE; -+ } -+ -+ dev = ep->dev; -+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { -+ DMSG("%s, bogus device state\n", __FUNCTION__); -+ return -ESHUTDOWN; -+ } -+ -+ ep->desc = desc; -+ ep->dma = -1; -+ ep->stopped = 0; -+ ep->pio_irqs = ep->dma_irqs = 0; -+ ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize); -+ -+ /* flush fifo (mostly for OUT buffers) */ -+ pxa27x_ep_fifo_flush (_ep); -+ -+ /* ... reset halt state too, if we could ... */ -+ -+#ifdef USE_DMA -+ /* for (some) bulk and ISO endpoints, try to get a DMA channel and -+ * bind it to the endpoint. otherwise use PIO. -+ */ -+ DMSG("%s: called attributes=%d\n", __FUNCTION__, ep->ep_type); -+ switch (ep->ep_type) { -+ case USB_ENDPOINT_XFER_ISOC: -+ if (le16_to_cpu(desc->wMaxPacketSize) % 32) -+ break; -+ // fall through -+ case USB_ENDPOINT_XFER_BULK: -+ if (!use_dma || !ep->reg_drcmr) -+ break; -+ ep->dma = pxa_request_dma ((char *)_ep->name, -+ (le16_to_cpu (desc->wMaxPacketSize) > 64) -+ ? DMA_PRIO_MEDIUM /* some iso */ -+ : DMA_PRIO_LOW, -+ dma_nodesc_handler, ep); -+ if (ep->dma >= 0) { -+ *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma; -+ DMSG("%s using dma%d\n", _ep->name, ep->dma); -+ } -+ default: -+ break; -+ } -+#endif -+ DBG(DBG_VERBOSE, "enabled %s\n", _ep->name); -+ return 0; -+} -+ -+static int pxa27x_ep_disable (struct usb_ep *_ep) -+{ -+ struct pxa27x_ep *ep; -+ -+ ep = container_of (_ep, struct pxa27x_ep, ep); -+ if (!_ep || !ep->desc) { -+ DMSG("%s, %s not enabled\n", __FUNCTION__, -+ _ep ? ep->ep.name : NULL); -+ return -EINVAL; -+ } -+ nuke (ep, -ESHUTDOWN); -+ -+#ifdef USE_DMA -+ if (ep->dma >= 0) { -+ *ep->reg_drcmr = 0; -+ pxa_free_dma (ep->dma); -+ ep->dma = -1; -+ } -+#endif -+ -+ /* flush fifo (mostly for IN buffers) */ -+ pxa27x_ep_fifo_flush (_ep); -+ -+ ep->desc = 0; -+ ep->stopped = 1; -+ -+ DBG(DBG_VERBOSE, "%s disabled\n", _ep->name); -+ return 0; -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* for the pxa27x, these can just wrap kmalloc/kfree. gadget drivers -+ * must still pass correctly initialized endpoints, since other controller -+ * drivers may care about how it's currently set up (dma issues etc). -+ */ -+ -+/* -+ * pxa27x_ep_alloc_request - allocate a request data structure -+ */ -+static struct usb_request * -+pxa27x_ep_alloc_request (struct usb_ep *_ep, unsigned gfp_flags) -+{ -+ struct pxa27x_request *req; -+ -+ req = kmalloc (sizeof *req, gfp_flags); -+ if (!req) -+ return 0; -+ -+ memset (req, 0, sizeof *req); -+ INIT_LIST_HEAD (&req->queue); -+ return &req->req; -+} -+ -+ -+/* -+ * pxa27x_ep_free_request - deallocate a request data structure -+ */ -+static void -+pxa27x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req) -+{ -+ struct pxa27x_request *req; -+ -+ req = container_of(_req, struct pxa27x_request, req); -+ WARN_ON (!list_empty (&req->queue)); -+ kfree(req); -+} -+ -+ -+/* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's -+ * no device-affinity and the heap works perfectly well for i/o buffers. -+ * It wastes much less memory than dma_alloc_coherent() would, and even -+ * prevents cacheline (32 bytes wide) sharing problems. -+ */ -+static void * -+pxa27x_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes, -+ dma_addr_t *dma, unsigned gfp_flags) -+{ -+ char *retval; -+ -+ retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM)); -+ if (retval) -+ *dma = virt_to_bus (retval); -+ return retval; -+} -+ -+static void -+pxa27x_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma, -+ unsigned bytes) -+{ -+ kfree (buf); -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* -+ * done - retire a request; caller blocked irqs -+ */ -+static void done(struct pxa27x_ep *ep, struct pxa27x_request *req, int status) -+{ -+ list_del_init(&req->queue); -+ if (likely (req->req.status == -EINPROGRESS)) -+ req->req.status = status; -+ else -+ status = req->req.status; -+ -+ if (status && status != -ESHUTDOWN) -+ DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n", -+ ep->ep.name, &req->req, status, -+ req->req.actual, req->req.length); -+ -+ /* don't modify queue heads during completion callback */ -+ req->req.complete(&ep->ep, &req->req); -+} -+ -+ -+static inline void ep0_idle (struct pxa27x_udc *dev) -+{ -+ dev->ep0state = EP0_IDLE; -+ LED_EP0_OFF; -+} -+ -+static int -+write_packet(volatile u32 *uddr, struct pxa27x_request *req, unsigned max) -+{ -+ u32 *buf; -+ int length, count, remain; -+ -+ buf = (u32*)(req->req.buf + req->req.actual); -+ prefetch(buf); -+ -+ /* how big will this packet be? */ -+ length = min(req->req.length - req->req.actual, max); -+ req->req.actual += length; -+ -+ remain = length & 0x3; -+ count = length & ~(0x3); -+ -+ while (likely(count)) { -+ *uddr = *buf++; -+ count -= 4; -+ } -+ -+ if (remain) { -+ volatile u8* reg=(u8*)uddr; -+ char *rd =(u8*)buf; -+ -+ while (remain--) { -+ *reg=*rd++; -+ } -+ } -+ -+ return length; -+} -+ -+/* -+ * write to an IN endpoint fifo, as many packets as possible. -+ * irqs will use this to write the rest later. -+ * caller guarantees at least one packet buffer is ready (or a zlp). -+ */ -+static int -+write_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req) -+{ -+ unsigned max; -+ -+ max = le16_to_cpu(ep->desc->wMaxPacketSize); -+ do { -+ int count; -+ int is_last, is_short; -+ -+ count = write_packet(ep->reg_udcdr, req, max); -+ -+ /* last packet is usually short (or a zlp) */ -+ if (unlikely (count != max)) -+ is_last = is_short = 1; -+ else { -+ if (likely(req->req.length != req->req.actual) -+ || req->req.zero) -+ is_last = 0; -+ else -+ is_last = 1; -+ /* interrupt/iso maxpacket may not fill the fifo */ -+ is_short = unlikely (max < ep->fifo_size); -+ } -+ -+ DMSG("wrote %s count:%d bytes%s%s %d left %p\n", -+ ep->ep.name, count, -+ is_last ? "/L" : "", is_short ? "/S" : "", -+ req->req.length - req->req.actual, &req->req); -+ -+ /* let loose that packet. maybe try writing another one, -+ * double buffering might work. TSP, TPC, and TFS -+ * bit values are the same for all normal IN endpoints. -+ */ -+ *ep->reg_udccsr = UDCCSR_PC; -+ if (is_short) -+ *ep->reg_udccsr = UDCCSR_SP; -+ -+ /* requests complete when all IN data is in the FIFO */ -+ if (is_last) { -+ done (ep, req, 0); -+ if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) { -+ pio_irq_disable (ep->ep_num); -+#ifdef USE_DMA -+ /* unaligned data and zlps couldn't use dma */ -+ if (unlikely(!list_empty(&ep->queue))) { -+ req = list_entry(ep->queue.next, -+ struct pxa27x_request, queue); -+ kick_dma(ep,req); -+ return 0; -+ } -+#endif -+ } -+ return 1; -+ } -+ -+ // TODO experiment: how robust can fifo mode tweaking be? -+ // double buffering is off in the default fifo mode, which -+ // prevents TFS from being set here. -+ -+ } while (*ep->reg_udccsr & UDCCSR_FS); -+ return 0; -+} -+ -+/* caller asserts req->pending (ep0 irq status nyet cleared); starts -+ * ep0 data stage. these chips want very simple state transitions. -+ */ -+static inline -+void ep0start(struct pxa27x_udc *dev, u32 flags, const char *tag) -+{ -+ UDCCSR0 = flags|UDCCSR0_SA|UDCCSR0_OPC; -+ UDCISR0 = UDCICR_INT(0, UDC_INT_FIFOERROR | UDC_INT_PACKETCMP); -+ dev->req_pending = 0; -+ DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n", -+ __FUNCTION__, tag, UDCCSR0, flags); -+} -+ -+static int -+write_ep0_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req) -+{ -+ unsigned count; -+ int is_short; -+ -+ count = write_packet(&UDCDR0, req, EP0_FIFO_SIZE); -+ ep->dev->stats.write.bytes += count; -+ -+ /* last packet "must be" short (or a zlp) */ -+ is_short = (count != EP0_FIFO_SIZE); -+ -+ DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count, -+ req->req.length - req->req.actual, &req->req); -+ -+ if (unlikely (is_short)) { -+ if (ep->dev->req_pending) -+ ep0start(ep->dev, UDCCSR0_IPR, "short IN"); -+ else -+ UDCCSR0 = UDCCSR0_IPR; -+ -+ count = req->req.length; -+ done (ep, req, 0); -+ ep0_idle(ep->dev); -+#if 0 -+ /* This seems to get rid of lost status irqs in some cases: -+ * host responds quickly, or next request involves config -+ * change automagic, or should have been hidden, or ... -+ * -+ * FIXME get rid of all udelays possible... -+ */ -+ if (count >= EP0_FIFO_SIZE) { -+ count = 100; -+ do { -+ if ((UDCCSR0 & UDCCSR0_OPC) != 0) { -+ /* clear OPC, generate ack */ -+ UDCCSR0 = UDCCSR0_OPC; -+ break; -+ } -+ count--; -+ udelay(1); -+ } while (count); -+ } -+#endif -+ } else if (ep->dev->req_pending) -+ ep0start(ep->dev, 0, "IN"); -+ return is_short; -+} -+ -+ -+/* -+ * read_fifo - unload packet(s) from the fifo we use for usb OUT -+ * transfers and put them into the request. caller should have made -+ * sure there's at least one packet ready. -+ * -+ * returns true if the request completed because of short packet or the -+ * request buffer having filled (and maybe overran till end-of-packet). -+ */ -+static int -+read_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req) -+{ -+ for (;;) { -+ u32 *buf; -+ int bufferspace, count, is_short; -+ -+ /* make sure there's a packet in the FIFO.*/ -+ if (unlikely ((*ep->reg_udccsr & UDCCSR_PC) == 0)) -+ break; -+ buf =(u32*) (req->req.buf + req->req.actual); -+ prefetchw(buf); -+ bufferspace = req->req.length - req->req.actual; -+ -+ /* read all bytes from this packet */ -+ if (likely (*ep->reg_udccsr & UDCCSR_BNE)) { -+ count = 0x3ff & *ep->reg_udcbcr; -+ req->req.actual += min (count, bufferspace); -+ } else /* zlp */ -+ count = 0; -+ -+ is_short = (count < ep->ep.maxpacket); -+ DMSG("read %s udccsr:%02x, count:%d bytes%s req %p %d/%d\n", -+ ep->ep.name, *ep->reg_udccsr, count, -+ is_short ? "/S" : "", -+ &req->req, req->req.actual, req->req.length); -+ -+// dump_regs(ep->ep_num ); -+ count = min(count, bufferspace); -+ while (likely (count > 0)) { -+ *buf++ = *ep->reg_udcdr; -+ count -= 4; -+ } -+ DMSG("Buf:0x%p\n", req->req.buf); -+ -+ *ep->reg_udccsr = UDCCSR_PC; -+ /* RPC/RSP/RNE could now reflect the other packet buffer */ -+ -+ /* completion */ -+ if (is_short || req->req.actual == req->req.length) { -+ done (ep, req, 0); -+ if (list_empty(&ep->queue)) -+ pio_irq_disable (ep->ep_num); -+ return 1; -+ } -+ -+ /* finished that packet. the next one may be waiting... */ -+ } -+ return 0; -+} -+ -+/* -+ * special ep0 version of the above. no UBCR0 or double buffering; status -+ * handshaking is magic. most device protocols don't need control-OUT. -+ * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other -+ * protocols do use them. -+ */ -+static int -+read_ep0_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req) -+{ -+ u32 *buf, word; -+ unsigned bufferspace; -+ -+ buf = (u32*) (req->req.buf + req->req.actual); -+ bufferspace = req->req.length - req->req.actual; -+ -+ while (UDCCSR0 & UDCCSR0_RNE) { -+ word = UDCDR0; -+ -+ if (unlikely (bufferspace == 0)) { -+ /* this happens when the driver's buffer -+ * is smaller than what the host sent. -+ * discard the extra data. -+ */ -+ if (req->req.status != -EOVERFLOW) -+ DMSG("%s overflow\n", ep->ep.name); -+ req->req.status = -EOVERFLOW; -+ } else { -+ *buf++ = word; -+ req->req.actual += 4; -+ bufferspace -= 4; -+ } -+ } -+ -+ UDCCSR0 = UDCCSR0_OPC ; -+ -+ /* completion */ -+ if (req->req.actual >= req->req.length) -+ return 1; -+ -+ /* finished that packet. the next one may be waiting... */ -+ return 0; -+} -+ -+#ifdef USE_DMA -+ -+#define MAX_IN_DMA ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE) -+static void kick_dma(struct pxa27x_ep *ep, struct pxa27x_request *req) -+{ -+ u32 dcmd = 0; -+ u32 len = req->req.length; -+ u32 buf = req->req.dma; -+ u32 fifo = io_v2p ((u32)ep->reg_udcdr); -+ -+ buf += req->req.actual; -+ len -= req->req.actual; -+ ep->dma_con = 0; -+ -+ DMSG("%s: req:0x%p length:%d, actual:%d dma:%d\n", -+ __FUNCTION__, &req->req, req->req.length, -+ req->req.actual,ep->dma); -+ -+ /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */ -+ DCSR(ep->dma) = DCSR_NODESC; -+ if (buf & 0x3) -+ DALGN |= 1 << ep->dma; -+ else -+ DALGN &= ~(1 << ep->dma); -+ -+ if (ep->dir_in) { -+ DSADR(ep->dma) = buf; -+ DTADR(ep->dma) = fifo; -+ if (len > MAX_IN_DMA) { -+ len= MAX_IN_DMA; -+ ep->dma_con =1 ; -+ } else if (len >= ep->ep.maxpacket) { -+ if ((ep->dma_con = (len % ep->ep.maxpacket) != 0)) -+ len = ep->ep.maxpacket; -+ } -+ dcmd = len | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN -+ | DCMD_FLOWTRG | DCMD_INCSRCADDR; -+ } else { -+ DSADR(ep->dma) = fifo; -+ DTADR(ep->dma) = buf; -+ dcmd = len | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN -+ | DCMD_FLOWSRC | DCMD_INCTRGADDR; -+ } -+ *ep->reg_udccsr = UDCCSR_DME; -+ DCMD(ep->dma) = dcmd; -+ DCSR(ep->dma) = DCSR_NODESC | DCSR_EORIRQEN \ -+ | ((ep->dir_in) ? DCSR_STOPIRQEN : 0); -+ *ep->reg_drcmr = ep->dma | DRCMR_MAPVLD; -+ DCSR(ep->dma) |= DCSR_RUN; -+} -+ -+static void cancel_dma(struct pxa27x_ep *ep) -+{ -+ struct pxa27x_request *req; -+ u32 tmp; -+ -+ if (DCSR(ep->dma) == 0 || list_empty(&ep->queue)) -+ return; -+ -+ DMSG("hehe dma:%d,dcsr:0x%x\n", ep->dma, DCSR(ep->dma)); -+ DCSR(ep->dma) = 0; -+ while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0) -+ cpu_relax(); -+ -+ req = list_entry(ep->queue.next, struct pxa27x_request, queue); -+ tmp = DCMD(ep->dma) & DCMD_LENGTH; -+ req->req.actual = req->req.length - tmp; -+ -+ /* the last tx packet may be incomplete, so flush the fifo. -+ * FIXME correct req.actual if we can -+ */ -+ *ep->reg_udccsr = UDCCSR_FEF; -+} -+ -+static void dma_nodesc_handler(int dmach, void *_ep) -+{ -+ struct pxa27x_ep *ep = _ep; -+ struct pxa27x_request *req, *req_next; -+ u32 dcsr, tmp, completed; -+ -+ local_irq_disable(); -+ -+ req = list_entry(ep->queue.next, struct pxa27x_request, queue); -+ -+ DMSG("%s, buf:0x%p\n",__FUNCTION__, req->req.buf); -+ -+ ep->dma_irqs++; -+ ep->dev->stats.irqs++; -+ HEX_DISPLAY(ep->dev->stats.irqs); -+ -+ completed = 0; -+ -+ dcsr = DCSR(dmach); -+ DCSR(ep->dma) &= ~DCSR_RUN; -+ -+ if (dcsr & DCSR_BUSERR) { -+ DCSR(dmach) = DCSR_BUSERR; -+ printk(KERN_ERR " Buss Error\n"); -+ req->req.status = -EIO; -+ completed = 1; -+ } else if (dcsr & DCSR_ENDINTR) { -+ DCSR(dmach) = DCSR_ENDINTR; -+ if (ep->dir_in) { -+ tmp = req->req.length - req->req.actual; -+ /* Last packet is a short one*/ -+ if ( tmp < ep->ep.maxpacket) { -+ int count = 0; -+ -+ *ep->reg_udccsr = UDCCSR_SP | \ -+ (*ep->reg_udccsr & UDCCSR_MASK); -+ /*Wait for packet out */ -+ while( (count++ < 10000) && \ -+ !(*ep->reg_udccsr & UDCCSR_FS)); -+ if (count >= 10000) -+ DMSG("Failed to send packet\n"); -+ else -+ DMSG("%s: short packet sent len:%d," -+ "length:%d,actual:%d\n", __FUNCTION__, -+ tmp, req->req.length, req->req.actual); -+ req->req.actual = req->req.length; -+ completed = 1; -+ /* There are still packets to transfer */ -+ } else if ( ep->dma_con) { -+ DMSG("%s: more packets,length:%d,actual:%d\n", -+ __FUNCTION__,req->req.length, -+ req->req.actual); -+ req->req.actual += ep->ep.maxpacket; -+ completed = 0; -+ } else { -+ DMSG("%s: no more packets,length:%d," -+ "actual:%d\n", __FUNCTION__, -+ req->req.length, req->req.actual); -+ req->req.actual = req->req.length; -+ completed = 1; -+ } -+ } else { -+ req->req.actual = req->req.length; -+ completed = 1; -+ } -+ } else if (dcsr & DCSR_EORINTR) { //Only happened in OUT DMA -+ int remain,udccsr ; -+ -+ DCSR(dmach) = DCSR_EORINTR; -+ remain = DCMD(dmach) & DCMD_LENGTH; -+ req->req.actual = req->req.length - remain; -+ -+ udccsr = *ep->reg_udccsr; -+ if (udccsr & UDCCSR_SP) { -+ *ep->reg_udccsr = UDCCSR_PC | (udccsr & UDCCSR_MASK); -+ completed = 1; -+ } -+ DMSG("%s: length:%d actual:%d\n", -+ __FUNCTION__, req->req.length, req->req.actual); -+ } else -+ DMSG("%s: Others dma:%d DCSR:0x%x DCMD:0x%x\n", -+ __FUNCTION__, dmach, DCSR(dmach), DCMD(dmach)); -+ -+ if (likely(completed)) { -+ if (req->queue.next != &ep->queue) { -+ req_next = list_entry(req->queue.next, -+ struct pxa27x_request, queue); -+ kick_dma(ep, req_next); -+ } -+ done(ep, req, 0); -+ } else { -+ kick_dma(ep, req); -+ } -+ -+ local_irq_enable(); -+} -+ -+#endif -+/*-------------------------------------------------------------------------*/ -+ -+static int -+pxa27x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, unsigned gfp_flags) -+{ -+ struct pxa27x_ep *ep; -+ struct pxa27x_request *req; -+ struct pxa27x_udc *dev; -+ unsigned long flags; -+ -+ req = container_of(_req, struct pxa27x_request, req); -+ if (unlikely (!_req || !_req->complete || !_req->buf|| -+ !list_empty(&req->queue))) { -+ DMSG("%s, bad params\n", __FUNCTION__); -+ return -EINVAL; -+ } -+ -+ ep = container_of(_ep, struct pxa27x_ep, ep); -+ if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) { -+ DMSG("%s, bad ep\n", __FUNCTION__); -+ return -EINVAL; -+ } -+ -+ DMSG("%s, ep point %d is queue\n", __FUNCTION__, ep->ep_num); -+ -+ dev = ep->dev; -+ if (unlikely (!dev->driver -+ || dev->gadget.speed == USB_SPEED_UNKNOWN)) { -+ DMSG("%s, bogus device state\n", __FUNCTION__); -+ return -ESHUTDOWN; -+ } -+ -+ /* iso is always one packet per request, that's the only way -+ * we can report per-packet status. that also helps with dma. -+ */ -+ if (unlikely (ep->ep_type == USB_ENDPOINT_XFER_ISOC -+ && req->req.length > le16_to_cpu -+ (ep->desc->wMaxPacketSize))) -+ return -EMSGSIZE; -+ -+#ifdef USE_DMA -+ // FIXME caller may already have done the dma mapping -+ if (ep->dma >= 0) { -+ _req->dma = dma_map_single(dev->dev, _req->buf, _req->length, -+ (ep->dir_in) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); -+ } -+#endif -+ -+ DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n", -+ _ep->name, _req, _req->length, _req->buf); -+ -+ local_irq_save(flags); -+ -+ _req->status = -EINPROGRESS; -+ _req->actual = 0; -+ -+ /* kickstart this i/o queue? */ -+ if (list_empty(&ep->queue) && !ep->stopped) { -+ if (ep->desc == 0 /* ep0 */) { -+ unsigned length = _req->length; -+ -+ switch (dev->ep0state) { -+ case EP0_IN_DATA_PHASE: -+ dev->stats.write.ops++; -+ if (write_ep0_fifo(ep, req)) -+ req = 0; -+ break; -+ -+ case EP0_OUT_DATA_PHASE: -+ dev->stats.read.ops++; -+ if (dev->req_pending) -+ ep0start(dev, UDCCSR0_IPR, "OUT"); -+ if (length == 0 || ((UDCCSR0 & UDCCSR0_RNE) != 0 -+ && read_ep0_fifo(ep, req))) { -+ ep0_idle(dev); -+ done(ep, req, 0); -+ req = 0; -+ } -+ break; -+ case EP0_NO_ACTION: -+ ep0_idle(dev); -+ req=0; -+ break; -+ default: -+ DMSG("ep0 i/o, odd state %d\n", dev->ep0state); -+ local_irq_restore (flags); -+ return -EL2HLT; -+ } -+#ifdef USE_DMA -+ /* either start dma or prime pio pump */ -+ } else if (ep->dma >= 0) { -+ kick_dma(ep, req); -+#endif -+ /* can the FIFO can satisfy the request immediately? */ -+ } else if (ep->dir_in -+ && (*ep->reg_udccsr & UDCCSR_FS) != 0 -+ && write_fifo(ep, req)) { -+ req = 0; -+ } else if ((*ep->reg_udccsr & UDCCSR_FS) != 0 -+ && read_fifo(ep, req)) { -+ req = 0; -+ } -+ DMSG("req:%p,ep->desc:%p,ep->dma:%d\n", req, ep->desc, ep->dma); -+ if (likely (req && ep->desc) && ep->dma < 0) -+ pio_irq_enable(ep->ep_num); -+ } -+ -+ /* pio or dma irq handler advances the queue. */ -+ if (likely (req != 0)) -+ list_add_tail(&req->queue, &ep->queue); -+ local_irq_restore(flags); -+ -+ return 0; -+} -+ -+ -+/* -+ * nuke - dequeue ALL requests -+ */ -+static void nuke(struct pxa27x_ep *ep, int status) -+{ -+ struct pxa27x_request *req; -+ -+ /* called with irqs blocked */ -+#ifdef USE_DMA -+ if (ep->dma >= 0 && !ep->stopped) -+ cancel_dma(ep); -+#endif -+ while (!list_empty(&ep->queue)) { -+ req = list_entry(ep->queue.next, struct pxa27x_request, queue); -+ done(ep, req, status); -+ } -+ if (ep->desc) -+ pio_irq_disable (ep->ep_num); -+} -+ -+ -+/* dequeue JUST ONE request */ -+static int pxa27x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) -+{ -+ struct pxa27x_ep *ep; -+ struct pxa27x_request *req; -+ unsigned long flags; -+ -+ ep = container_of(_ep, struct pxa27x_ep, ep); -+ if (!_ep || ep->ep.name == ep0name) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ /* make sure it's actually queued on this endpoint */ -+ list_for_each_entry (req, &ep->queue, queue) { -+ if (&req->req == _req) -+ break; -+ } -+ if (&req->req != _req) { -+ local_irq_restore(flags); -+ return -EINVAL; -+ } -+ -+#ifdef USE_DMA -+ if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) { -+ cancel_dma(ep); -+ done(ep, req, -ECONNRESET); -+ /* restart i/o */ -+ if (!list_empty(&ep->queue)) { -+ req = list_entry(ep->queue.next, -+ struct pxa27x_request, queue); -+ kick_dma(ep, req); -+ } -+ } else -+#endif -+ done(ep, req, -ECONNRESET); -+ -+ local_irq_restore(flags); -+ return 0; -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int pxa27x_ep_set_halt(struct usb_ep *_ep, int value) -+{ -+ struct pxa27x_ep *ep; -+ unsigned long flags; -+ -+ DMSG("%s is called\n", __FUNCTION__); -+ ep = container_of(_ep, struct pxa27x_ep, ep); -+ if (unlikely (!_ep -+ || (!ep->desc && ep->ep.name != ep0name)) -+ || ep->ep_type == USB_ENDPOINT_XFER_ISOC) { -+ DMSG("%s, bad ep\n", __FUNCTION__); -+ return -EINVAL; -+ } -+ if (value == 0) { -+ /* this path (reset toggle+halt) is needed to implement -+ * SET_INTERFACE on normal hardware. but it can't be -+ * done from software on the PXA UDC, and the hardware -+ * forgets to do it as part of SET_INTERFACE automagic. -+ */ -+ DMSG("only host can clear %s halt\n", _ep->name); -+ return -EROFS; -+ } -+ -+ local_irq_save(flags); -+ -+ if (ep->dir_in && ((*ep->reg_udccsr & UDCCSR_FS) == 0 -+ || !list_empty(&ep->queue))) { -+ local_irq_restore(flags); -+ return -EAGAIN; -+ } -+ -+ /* FST bit is the same for control, bulk in, bulk out, interrupt in */ -+ *ep->reg_udccsr = UDCCSR_FST|UDCCSR_FEF; -+ -+ /* ep0 needs special care */ -+ if (!ep->desc) { -+ start_watchdog(ep->dev); -+ ep->dev->req_pending = 0; -+ ep->dev->ep0state = EP0_STALL; -+ LED_EP0_OFF; -+ -+ /* and bulk/intr endpoints like dropping stalls too */ -+ } else { -+ unsigned i; -+ for (i = 0; i < 1000; i += 20) { -+ if (*ep->reg_udccsr & UDCCSR_SST) -+ break; -+ udelay(20); -+ } -+ } -+ local_irq_restore(flags); -+ -+ DBG(DBG_VERBOSE, "%s halt\n", _ep->name); -+ return 0; -+} -+ -+static int pxa27x_ep_fifo_status(struct usb_ep *_ep) -+{ -+ struct pxa27x_ep *ep; -+ -+ ep = container_of(_ep, struct pxa27x_ep, ep); -+ if (!_ep) { -+ DMSG("%s, bad ep\n", __FUNCTION__); -+ return -ENODEV; -+ } -+ /* pxa can't report unclaimed bytes from IN fifos */ -+ if (ep->dir_in) -+ return -EOPNOTSUPP; -+ if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN -+ || (*ep->reg_udccsr & UDCCSR_FS) == 0) -+ return 0; -+ else -+ return (*ep->reg_udcbcr & 0xfff) + 1; -+} -+ -+static void pxa27x_ep_fifo_flush(struct usb_ep *_ep) -+{ -+ struct pxa27x_ep *ep; -+ -+ ep = container_of(_ep, struct pxa27x_ep, ep); -+ if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { -+ DMSG("%s, bad ep\n", __FUNCTION__); -+ return; -+ } -+ -+ /* toggle and halt bits stay unchanged */ -+ -+ /* for OUT, just read and discard the FIFO contents. */ -+ if (!ep->dir_in) { -+ while (((*ep->reg_udccsr) & UDCCSR_BNE) != 0) -+ (void) *ep->reg_udcdr; -+ return; -+ } -+ -+ /* most IN status is the same, but ISO can't stall */ -+ *ep->reg_udccsr = UDCCSR_PC|UDCCSR_FST|UDCCSR_TRN -+ | (ep->ep_type == USB_ENDPOINT_XFER_ISOC) -+ ? 0 : UDCCSR_SST; -+} -+ -+ -+static struct usb_ep_ops pxa27x_ep_ops = { -+ .enable = pxa27x_ep_enable, -+ .disable = pxa27x_ep_disable, -+ -+ .alloc_request = pxa27x_ep_alloc_request, -+ .free_request = pxa27x_ep_free_request, -+ -+ .alloc_buffer = pxa27x_ep_alloc_buffer, -+ .free_buffer = pxa27x_ep_free_buffer, -+ -+ .queue = pxa27x_ep_queue, -+ .dequeue = pxa27x_ep_dequeue, -+ -+ .set_halt = pxa27x_ep_set_halt, -+ .fifo_status = pxa27x_ep_fifo_status, -+ .fifo_flush = pxa27x_ep_fifo_flush, -+}; -+ -+ -+/* --------------------------------------------------------------------------- -+ * device-scoped parts of the api to the usb controller hardware -+ * --------------------------------------------------------------------------- -+ */ -+ -+static int pxa27x_udc_get_frame(struct usb_gadget *_gadget) -+{ -+ return (UDCFNR & 0x3FF); -+} -+ -+static int pxa27x_udc_wakeup(struct usb_gadget *_gadget) -+{ -+ /* host may not have enabled remote wakeup */ -+ if ((UDCCR & UDCCR_DWRE) == 0) -+ return -EHOSTUNREACH; -+ udc_set_mask_UDCCR(UDCCR_UDR); -+ return 0; -+} -+ -+static const struct usb_gadget_ops pxa27x_udc_ops = { -+ .get_frame = pxa27x_udc_get_frame, -+ .wakeup = pxa27x_udc_wakeup, -+ // current versions must always be self-powered -+}; -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+#ifdef UDC_PROC_FILE -+ -+static const char proc_node_name [] = "driver/udc"; -+ -+static int -+udc_proc_read(char *page, char **start, off_t off, int count, -+ int *eof, void *_dev) -+{ -+ char *buf = page; -+ struct pxa27x_udc *dev = _dev; -+ char *next = buf; -+ unsigned size = count; -+ unsigned long flags; -+ int i, t; -+ u32 tmp; -+ -+ if (off != 0) -+ return 0; -+ -+ local_irq_save(flags); -+ -+ /* basic device status */ -+ t = scnprintf(next, size, DRIVER_DESC "\n" -+ "%s version: %s\nGadget driver: %s\n", -+ driver_name, DRIVER_VERSION SIZE_STR DMASTR, -+ dev->driver ? dev->driver->driver.name : "(none)"); -+ size -= t; -+ next += t; -+ -+ /* registers for device and ep0 */ -+ t = scnprintf(next, size, -+ "uicr %02X.%02X, usir %02X.%02x, ufnr %02X\n", -+ UDCICR1, UDCICR0, UDCISR1, UDCISR0, UDCFNR); -+ size -= t; -+ next += t; -+ -+ tmp = UDCCR; -+ t = scnprintf(next, size,"udccr %02X =%s%s%s%s%s%s%s%s%s%s, con=%d,inter=%d,altinter=%d\n", tmp, -+ (tmp & UDCCR_OEN) ? " oen":"", -+ (tmp & UDCCR_AALTHNP) ? " aalthnp":"", -+ (tmp & UDCCR_AHNP) ? " rem" : "", -+ (tmp & UDCCR_BHNP) ? " rstir" : "", -+ (tmp & UDCCR_DWRE) ? " dwre" : "", -+ (tmp & UDCCR_SMAC) ? " smac" : "", -+ (tmp & UDCCR_EMCE) ? " emce" : "", -+ (tmp & UDCCR_UDR) ? " udr" : "", -+ (tmp & UDCCR_UDA) ? " uda" : "", -+ (tmp & UDCCR_UDE) ? " ude" : "", -+ (tmp & UDCCR_ACN) >> UDCCR_ACN_S, -+ (tmp & UDCCR_AIN) >> UDCCR_AIN_S, -+ (tmp & UDCCR_AAISN)>> UDCCR_AAISN_S ); -+ -+ size -= t; -+ next += t; -+ -+ tmp = UDCCSR0; -+ t = scnprintf(next, size, -+ "udccsr0 %02X =%s%s%s%s%s%s%s\n", tmp, -+ (tmp & UDCCSR0_SA) ? " sa" : "", -+ (tmp & UDCCSR0_RNE) ? " rne" : "", -+ (tmp & UDCCSR0_FST) ? " fst" : "", -+ (tmp & UDCCSR0_SST) ? " sst" : "", -+ (tmp & UDCCSR0_DME) ? " dme" : "", -+ (tmp & UDCCSR0_IPR) ? " ipr" : "", -+ (tmp & UDCCSR0_OPC) ? " opc" : ""); -+ size -= t; -+ next += t; -+ -+ if (!dev->driver) -+ goto done; -+ -+ t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n", -+ dev->stats.write.bytes, dev->stats.write.ops, -+ dev->stats.read.bytes, dev->stats.read.ops, -+ dev->stats.irqs); -+ size -= t; -+ next += t; -+ -+ /* dump endpoint queues */ -+ for (i = 0; i < UDC_EP_NUM; i++) { -+ struct pxa27x_ep *ep = &dev->ep [i]; -+ struct pxa27x_request *req; -+ int t; -+ -+ if (i != 0) { -+ const struct usb_endpoint_descriptor *d; -+ -+ d = ep->desc; -+ if (!d) -+ continue; -+ tmp = *dev->ep [i].reg_udccsr; -+ t = scnprintf(next, size, -+ "%s max %d %s udccs %02x udccr:0x%x\n", -+ ep->ep.name, le16_to_cpu (d->wMaxPacketSize), -+ (ep->dma >= 0) ? "dma" : "pio", tmp, -+ *dev->ep[i].reg_udccr); -+ /* TODO translate all five groups of udccs bits! */ -+ -+ } else /* ep0 should only have one transfer queued */ -+ t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n", -+ ep->pio_irqs); -+ if (t <= 0 || t > size) -+ goto done; -+ size -= t; -+ next += t; -+ -+ if (list_empty(&ep->queue)) { -+ t = scnprintf(next, size, "\t(nothing queued)\n"); -+ if (t <= 0 || t > size) -+ goto done; -+ size -= t; -+ next += t; -+ continue; -+ } -+ list_for_each_entry(req, &ep->queue, queue) { -+#ifdef USE_DMA -+ if (ep->dma >= 0 && req->queue.prev == &ep->queue) -+ t = scnprintf(next, size, -+ "\treq %p len %d/%d " -+ "buf %p (dma%d dcmd %08x)\n", -+ &req->req, req->req.actual, -+ req->req.length, req->req.buf, -+ ep->dma, DCMD(ep->dma) -+ // low 13 bits == bytes-to-go -+ ); -+ else -+#endif -+ t = scnprintf(next, size, -+ "\treq %p len %d/%d buf %p\n", -+ &req->req, req->req.actual, -+ req->req.length, req->req.buf); -+ if (t <= 0 || t > size) -+ goto done; -+ size -= t; -+ next += t; -+ } -+ } -+ -+done: -+ local_irq_restore(flags); -+ *eof = 1; -+ return count - size; -+} -+ -+#define create_proc_files() \ -+ create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev) -+#define remove_proc_files() \ -+ remove_proc_entry(proc_node_name, NULL) -+ -+#else /* !UDC_PROC_FILE */ -+#define create_proc_files() do {} while (0) -+#define remove_proc_files() do {} while (0) -+ -+#endif /* UDC_PROC_FILE */ -+ -+/* "function" sysfs attribute */ -+static ssize_t -+show_function (struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+ struct pxa27x_udc *dev = dev_get_drvdata (_dev); -+ -+ if (!dev->driver -+ || !dev->driver->function -+ || strlen (dev->driver->function) > PAGE_SIZE) -+ return 0; -+ return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function); -+} -+static DEVICE_ATTR (function, S_IRUGO, show_function, NULL); -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* -+ * udc_disable - disable USB device controller -+ */ -+static void udc_disable(struct pxa27x_udc *dev) -+{ -+ UDCICR0 = UDCICR1 = 0x00000000; -+ -+ udc_clear_mask_UDCCR(UDCCR_UDE); -+ -+ /* Disable clock for USB device */ -+ pxa_set_cken(CKEN11_USB, 0); -+ -+ ep0_idle (dev); -+ dev->gadget.speed = USB_SPEED_UNKNOWN; -+ LED_CONNECTED_OFF; -+ if (dev->mach->udc_command) -+ dev->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); -+} -+ -+ -+/* -+ * udc_reinit - initialize software state -+ */ -+static void udc_reinit(struct pxa27x_udc *dev) -+{ -+ u32 i; -+ -+ dev->ep0state = EP0_IDLE; -+ -+ /* basic endpoint records init */ -+ for (i = 0; i < UDC_EP_NUM; i++) { -+ struct pxa27x_ep *ep = &dev->ep[i]; -+ -+ ep->stopped = 0; -+ ep->pio_irqs = ep->dma_irqs = 0; -+ } -+ dev->configuration = 0; -+ dev->interface = 0; -+ dev->alternate = 0; -+ /* the rest was statically initialized, and is read-only */ -+} -+ -+/* until it's enabled, this UDC should be completely invisible -+ * to any USB host. -+ */ -+static void udc_enable (struct pxa27x_udc *dev) -+{ -+ udc_clear_mask_UDCCR(UDCCR_UDE); -+ -+ // MST_MSCWR2 &= ~(MST_MSCWR2_nUSBC_SC); -+ -+ /* Enable clock for USB device */ -+ pxa_set_cken(CKEN11_USB, 1); -+ -+ UDCICR0 = UDCICR1 = 0; -+ -+ ep0_idle(dev); -+ dev->gadget.speed = USB_SPEED_FULL; -+ dev->stats.irqs = 0; -+ -+ udc_set_mask_UDCCR(UDCCR_UDE); -+ udelay (2); -+ if (UDCCR & UDCCR_EMCE) -+ { -+ printk(KERN_ERR ": There are error in configuration, udc disabled\n"); -+ } -+ -+ /* caller must be able to sleep in order to cope -+ * with startup transients. -+ */ -+ msleep(100); -+ -+ /* enable suspend/resume and reset irqs */ -+ UDCICR1 = UDCICR1_IECC | UDCICR1_IERU | UDCICR1_IESU | UDCICR1_IERS; -+ -+ /* enable ep0 irqs */ -+ UDCICR0 = UDCICR_INT(0,UDCICR_INT_MASK); -+#if 0 -+ for(i=1; i < UDC_EP_NUM; i++) { -+ if (dev->ep[i].assigned) -+ pio_irq_enable(i); -+ } -+#endif -+ if (dev->mach->udc_command) -+ dev->mach->udc_command(PXA2XX_UDC_CMD_CONNECT); -+} -+ -+ -+/* when a driver is successfully registered, it will receive -+ * control requests including set_configuration(), which enables -+ * non-control requests. then usb traffic follows until a -+ * disconnect is reported. then a host may connect again, or -+ * the driver might get unbound. -+ */ -+int usb_gadget_register_driver(struct usb_gadget_driver *driver) -+{ -+ struct pxa27x_udc *dev = the_controller; -+ int retval; -+#if 0 -+ DMSG("dev=0x%x, driver=0x%x, speed=%d," -+ "bind=0x%x, unbind=0x%x, disconnect=0x%x, setup=0x%x\n", -+ (unsigned)dev, (unsigned)driver, driver->speed, -+ (unsigned)driver->bind, (unsigned)driver->unbind, -+ (unsigned)driver->disconnect, (unsigned)driver->setup); -+#endif -+ if (!driver || driver->speed != USB_SPEED_FULL -+ || !driver->bind -+ || !driver->unbind -+ || !driver->disconnect -+ || !driver->setup) -+ return -EINVAL; -+ if (!dev) -+ return -ENODEV; -+ if (dev->driver) -+ return -EBUSY; -+ -+ /* first hook up the driver ... */ -+ dev->driver = driver; -+ dev->gadget.dev.driver = &driver->driver; -+ -+ device_add (&dev->gadget.dev); -+ retval = driver->bind(&dev->gadget); -+ if (retval) { -+ DMSG("bind to driver %s --> error %d\n", -+ driver->driver.name, retval); -+ device_del (&dev->gadget.dev); -+ -+ dev->driver = 0; -+ dev->gadget.dev.driver = 0; -+ return retval; -+ } -+ device_create_file(dev->dev, &dev_attr_function); -+ -+ /* ... then enable host detection and ep0; and we're ready -+ * for set_configuration as well as eventual disconnect. -+ * NOTE: this shouldn't power up until later. -+ */ -+ DMSG("registered gadget driver '%s'\n", driver->driver.name); -+ udc_enable(dev); -+ dump_state(dev); -+ return 0; -+} -+EXPORT_SYMBOL(usb_gadget_register_driver); -+ -+static void -+stop_activity(struct pxa27x_udc *dev, struct usb_gadget_driver *driver) -+{ -+ int i; -+ -+ DMSG("Trace path 1\n"); -+ /* don't disconnect drivers more than once */ -+ if (dev->gadget.speed == USB_SPEED_UNKNOWN) -+ driver = 0; -+ dev->gadget.speed = USB_SPEED_UNKNOWN; -+ -+ /* prevent new request submissions, kill any outstanding requests */ -+ for (i = 0; i < UDC_EP_NUM; i++) { -+ struct pxa27x_ep *ep = &dev->ep[i]; -+ -+ ep->stopped = 1; -+ nuke(ep, -ESHUTDOWN); -+ } -+ del_timer_sync(&dev->timer); -+ -+ /* report disconnect; the driver is already quiesced */ -+ if (driver) -+ driver->disconnect(&dev->gadget); -+ -+ /* re-init driver-visible data structures */ -+ udc_reinit(dev); -+} -+ -+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) -+{ -+ struct pxa27x_udc *dev = the_controller; -+ -+ if (!dev) -+ return -ENODEV; -+ if (!driver || driver != dev->driver) -+ return -EINVAL; -+ -+ local_irq_disable(); -+ udc_disable(dev); -+ stop_activity(dev, driver); -+ local_irq_enable(); -+ -+ driver->unbind(&dev->gadget); -+ dev->driver = 0; -+ -+ device_del (&dev->gadget.dev); -+ device_remove_file(dev->dev, &dev_attr_function); -+ -+ DMSG("unregistered gadget driver '%s'\n", driver->driver.name); -+ dump_state(dev); -+ return 0; -+} -+EXPORT_SYMBOL(usb_gadget_unregister_driver); -+ -+#ifndef enable_disconnect_irq -+#define enable_disconnect_irq() do {} while (0) -+#define disable_disconnect_irq() do {} while (0) -+#endif -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static inline void clear_ep_state (struct pxa27x_udc *dev) -+{ -+ unsigned i; -+ -+ /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint -+ * fifos, and pending transactions mustn't be continued in any case. -+ */ -+ for (i = 1; i < UDC_EP_NUM; i++) -+ nuke(&dev->ep[i], -ECONNABORTED); -+} -+ -+static void udc_watchdog(unsigned long _dev) -+{ -+ struct pxa27x_udc *dev = (void *)_dev; -+ -+ local_irq_disable(); -+ if (dev->ep0state == EP0_STALL -+ && (UDCCSR0 & UDCCSR0_FST) == 0 -+ && (UDCCSR0 & UDCCSR0_SST) == 0) { -+ UDCCSR0 = UDCCSR0_FST|UDCCSR0_FTF; -+ DBG(DBG_VERBOSE, "ep0 re-stall\n"); -+ start_watchdog(dev); -+ } -+ local_irq_enable(); -+} -+ -+static void handle_ep0 (struct pxa27x_udc *dev) -+{ -+ u32 udccsr0 = UDCCSR0; -+ struct pxa27x_ep *ep = &dev->ep [0]; -+ struct pxa27x_request *req; -+ union { -+ struct usb_ctrlrequest r; -+ u8 raw [8]; -+ u32 word [2]; -+ } u; -+ -+ if (list_empty(&ep->queue)) -+ req = 0; -+ else -+ req = list_entry(ep->queue.next, struct pxa27x_request, queue); -+ -+ /* clear stall status */ -+ if (udccsr0 & UDCCSR0_SST) { -+ nuke(ep, -EPIPE); -+ UDCCSR0 = UDCCSR0_SST; -+ del_timer(&dev->timer); -+ ep0_idle(dev); -+ } -+ -+ /* previous request unfinished? non-error iff back-to-back ... */ -+ if ((udccsr0 & UDCCSR0_SA) != 0 && dev->ep0state != EP0_IDLE) { -+ nuke(ep, 0); -+ del_timer(&dev->timer); -+ ep0_idle(dev); -+ } -+ -+ switch (dev->ep0state) { -+ case EP0_NO_ACTION: -+ printk(KERN_INFO"%s: Busy\n", __FUNCTION__); -+ /*Fall through */ -+ case EP0_IDLE: -+ /* late-breaking status? */ -+ udccsr0 = UDCCSR0; -+ -+ /* start control request? */ -+ if (likely((udccsr0 & (UDCCSR0_OPC|UDCCSR0_SA|UDCCSR0_RNE)) -+ == (UDCCSR0_OPC|UDCCSR0_SA|UDCCSR0_RNE))) { -+ int i; -+ -+ nuke (ep, -EPROTO); -+ /* read SETUP packet */ -+ for (i = 0; i < 2; i++) { -+ if (unlikely(!(UDCCSR0 & UDCCSR0_RNE))) { -+bad_setup: -+ DMSG("SETUP %d!\n", i); -+ goto stall; -+ } -+ u.word [i] = UDCDR0; -+ } -+ if (unlikely((UDCCSR0 & UDCCSR0_RNE) != 0)) -+ goto bad_setup; -+ -+ le16_to_cpus (&u.r.wValue); -+ le16_to_cpus (&u.r.wIndex); -+ le16_to_cpus (&u.r.wLength); -+ -+ LED_EP0_ON; -+ -+ DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n", -+ u.r.bRequestType, u.r.bRequest, -+ u.r.wValue, u.r.wIndex, u.r.wLength); -+ /* cope with automagic for some standard requests. */ -+ dev->req_std = (u.r.bRequestType & USB_TYPE_MASK) -+ == USB_TYPE_STANDARD; -+ dev->req_config = 0; -+ dev->req_pending = 1; -+#if 0 -+ switch (u.r.bRequest) { -+ /* hardware was supposed to hide this */ -+ case USB_REQ_SET_CONFIGURATION: -+ case USB_REQ_SET_INTERFACE: -+ case USB_REQ_SET_ADDRESS: -+ printk(KERN_ERR "Should not come here\n"); -+ break; -+ } -+ -+#endif -+ if (u.r.bRequestType & USB_DIR_IN) -+ dev->ep0state = EP0_IN_DATA_PHASE; -+ else -+ dev->ep0state = EP0_OUT_DATA_PHASE; -+ i = dev->driver->setup(&dev->gadget, &u.r); -+ -+ if (i < 0) { -+ /* hardware automagic preventing STALL... */ -+ if (dev->req_config) { -+ /* hardware sometimes neglects to tell -+ * tell us about config change events, -+ * so later ones may fail... -+ */ -+ WARN("config change %02x fail %d?\n", -+ u.r.bRequest, i); -+ return; -+ /* TODO experiment: if has_cfr, -+ * hardware didn't ACK; maybe we -+ * could actually STALL! -+ */ -+ } -+ DBG(DBG_VERBOSE, "protocol STALL, " -+ "%02x err %d\n", UDCCSR0, i); -+stall: -+ /* the watchdog timer helps deal with cases -+ * where udc seems to clear FST wrongly, and -+ * then NAKs instead of STALLing. -+ */ -+ ep0start(dev, UDCCSR0_FST|UDCCSR0_FTF, "stall"); -+ start_watchdog(dev); -+ dev->ep0state = EP0_STALL; -+ LED_EP0_OFF; -+ -+ /* deferred i/o == no response yet */ -+ } else if (dev->req_pending) { -+ if (likely(dev->ep0state == EP0_IN_DATA_PHASE -+ || dev->req_std || u.r.wLength)) -+ ep0start(dev, 0, "defer"); -+ else -+ ep0start(dev, UDCCSR0_IPR, "defer/IPR"); -+ } -+ -+ /* expect at least one data or status stage irq */ -+ return; -+ -+ } else { -+ /* some random early IRQ: -+ * - we acked FST -+ * - IPR cleared -+ * - OPC got set, without SA (likely status stage) -+ */ -+ UDCCSR0 = udccsr0 & (UDCCSR0_SA|UDCCSR0_OPC); -+ } -+ break; -+ case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ -+ if (udccsr0 & UDCCSR0_OPC) { -+ UDCCSR0 = UDCCSR0_OPC|UDCCSR0_FTF; -+ DBG(DBG_VERBOSE, "ep0in premature status\n"); -+ if (req) -+ done(ep, req, 0); -+ ep0_idle(dev); -+ } else /* irq was IPR clearing */ { -+ if (req) { -+ /* this IN packet might finish the request */ -+ (void) write_ep0_fifo(ep, req); -+ } /* else IN token before response was written */ -+ } -+ break; -+ case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ -+ if (udccsr0 & UDCCSR0_OPC) { -+ if (req) { -+ /* this OUT packet might finish the request */ -+ if (read_ep0_fifo(ep, req)) -+ done(ep, req, 0); -+ /* else more OUT packets expected */ -+ } /* else OUT token before read was issued */ -+ } else /* irq was IPR clearing */ { -+ DBG(DBG_VERBOSE, "ep0out premature status\n"); -+ if (req) -+ done(ep, req, 0); -+ ep0_idle(dev); -+ } -+ break; -+ case EP0_STALL: -+ UDCCSR0 = UDCCSR0_FST; -+ break; -+ } -+ UDCISR0 = UDCISR_INT(0, UDCISR_INT_MASK); -+} -+ -+ -+static void handle_ep(struct pxa27x_ep *ep) -+{ -+ struct pxa27x_request *req; -+ int completed; -+ u32 udccsr=0; -+ -+ DMSG("%s is called\n", __FUNCTION__); -+ do { -+ completed = 0; -+ if (likely (!list_empty(&ep->queue))) { -+ req = list_entry(ep->queue.next, -+ struct pxa27x_request, queue); -+ } else -+ req = 0; -+ -+// udccsr = *ep->reg_udccsr; -+ DMSG("%s: req:%p, udcisr0:0x%x udccsr %p:0x%x\n", __FUNCTION__, -+ req, UDCISR0, ep->reg_udccsr, *ep->reg_udccsr); -+ if (unlikely(ep->dir_in)) { -+ udccsr = (UDCCSR_SST | UDCCSR_TRN) & *ep->reg_udccsr; -+ if (unlikely (udccsr)) -+ *ep->reg_udccsr = udccsr; -+ -+ if (req && likely ((*ep->reg_udccsr & UDCCSR_FS) != 0)) -+ completed = write_fifo(ep, req); -+ -+ } else { -+ udccsr = (UDCCSR_SST | UDCCSR_TRN) & *ep->reg_udccsr; -+ if (unlikely(udccsr)) -+ *ep->reg_udccsr = udccsr; -+ -+ /* fifos can hold packets, ready for reading... */ -+ if (likely(req)) { -+ completed = read_fifo(ep, req); -+ } else { -+ pio_irq_disable (ep->ep_num); -+ *ep->reg_udccsr = UDCCSR_FEF; -+ DMSG("%s: no req for out data\n", -+ __FUNCTION__); -+ } -+ } -+ ep->pio_irqs++; -+ } while (completed); -+} -+ -+static void pxa27x_change_configuration (struct pxa27x_udc *dev) -+{ -+ struct usb_ctrlrequest req ; -+ -+ req.bRequestType = 0; -+ req.bRequest = USB_REQ_SET_CONFIGURATION; -+ req.wValue = dev->configuration; -+ req.wIndex = 0; -+ req.wLength = 0; -+ -+ dev->ep0state = EP0_NO_ACTION; -+ dev->driver->setup(&dev->gadget, &req); -+ -+} -+ -+static void pxa27x_change_interface (struct pxa27x_udc *dev) -+{ -+ struct usb_ctrlrequest req; -+ -+ req.bRequestType = USB_RECIP_INTERFACE; -+ req.bRequest = USB_REQ_SET_INTERFACE; -+ req.wValue = dev->alternate; -+ req.wIndex = dev->interface; -+ req.wLength = 0; -+ -+ dev->ep0state = EP0_NO_ACTION; -+ dev->driver->setup(&dev->gadget, &req); -+} -+ -+/* -+ * pxa27x_udc_irq - interrupt handler -+ * -+ * avoid delays in ep0 processing. the control handshaking isn't always -+ * under software control (pxa250c0 and the pxa255 are better), and delays -+ * could cause usb protocol errors. -+ */ -+static irqreturn_t -+pxa27x_udc_irq(int irq, void *_dev) -+{ -+ struct pxa27x_udc *dev = _dev; -+ int handled; -+ -+ dev->stats.irqs++; -+ HEX_DISPLAY(dev->stats.irqs); -+ -+// printk("\n"); -+ DBG(DBG_VERBOSE, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, " -+ "UDCCR:0x%08x\n", UDCISR0, UDCISR1, UDCCR); -+ do { -+ u32 udcir = UDCISR1 & 0xF8000000; -+ -+ handled = 0; -+ -+ /* SUSpend Interrupt Request */ -+ if (unlikely(udcir & UDCISR1_IRSU)) { -+ UDCISR1 = UDCISR1_IRSU; -+ handled = 1; -+ DBG(DBG_VERBOSE, "USB suspend\n"); -+ if (dev->gadget.speed != USB_SPEED_UNKNOWN -+ && dev->driver -+ && dev->driver->suspend) -+ dev->driver->suspend(&dev->gadget); -+ ep0_idle (dev); -+ } -+ -+ /* RESume Interrupt Request */ -+ if (unlikely(udcir & UDCISR1_IRRU)) { -+ UDCISR1 = UDCISR1_IRRU; -+ handled = 1; -+ DBG(DBG_VERBOSE, "USB resume\n"); -+ -+ if (dev->gadget.speed != USB_SPEED_UNKNOWN -+ && dev->driver -+ && dev->driver->resume) -+ dev->driver->resume(&dev->gadget); -+ } -+ -+ if (unlikely(udcir & UDCISR1_IRCC)) { -+ unsigned config, interface, alternate; -+ -+ handled = 1; -+ DBG(DBG_VERBOSE, "USB SET_CONFIGURATION or " -+ "SET_INTERFACE command received\n"); -+ -+ UDCCR |= UDCCR_SMAC; -+ -+ config = (UDCCR & UDCCR_ACN) >> UDCCR_ACN_S; -+ -+ if (dev->configuration != config) { -+ dev->configuration = config; -+ pxa27x_change_configuration(dev) ; -+ } -+ -+ interface = (UDCCR & UDCCR_AIN) >> UDCCR_AIN_S; -+ alternate = (UDCCR & UDCCR_AAISN) >> UDCCR_AAISN_S; -+ -+ if ( (dev->configuration != interface) || \ -+ (dev->alternate != alternate)){ -+ dev->interface = config; -+ dev->alternate = alternate; -+ pxa27x_change_interface(dev); -+ } -+ -+ UDCISR1 = UDCISR1_IRCC; -+ DMSG("%s: con:%d,inter:%d,alt:%d\n", -+ __FUNCTION__, config,interface, alternate); -+ } -+ -+ /* ReSeT Interrupt Request - USB reset */ -+ if (unlikely(udcir & UDCISR1_IRRS)) { -+ UDCISR1 = UDCISR1_IRRS; -+ handled = 1; -+ -+ if ((UDCCR & UDCCR_UDA) == 0) { -+ DBG(DBG_VERBOSE, "USB reset start\n"); -+ -+ /* reset driver and endpoints, -+ * in case that's not yet done -+ */ -+ stop_activity (dev, dev->driver); -+ -+ } -+ INFO("USB reset\n"); -+ dev->gadget.speed = USB_SPEED_FULL; -+ memset(&dev->stats, 0, sizeof dev->stats); -+ -+ } else { -+ u32 udcisr0 = UDCISR0 ; -+ u32 udcisr1 = UDCISR1 & 0xFFFF; -+ int i; -+ -+ if (unlikely (!udcisr0 && !udcisr1)) -+ continue; -+ -+ DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", udcisr1,udcisr0); -+ -+ /* control traffic */ -+ if (udcisr0 & UDCISR0_IR0) { -+ dev->ep[0].pio_irqs++; -+ handle_ep0(dev); -+ handled = 1; -+ } -+ -+ udcisr0 >>= 2; -+ /* endpoint data transfers */ -+ for (i = 1; udcisr0!=0 && i < 16; udcisr0>>=2,i++) { -+ UDCISR0 = UDCISR_INT(i, UDCISR_INT_MASK); -+ -+ if (udcisr0 & UDC_INT_FIFOERROR) -+ printk(KERN_ERR" Endpoint %d Fifo error\n", i); -+ if (udcisr0 & UDC_INT_PACKETCMP) { -+ handle_ep(&dev->ep[i]); -+ handled = 1; -+ } -+ -+ } -+ -+ for (i = 0; udcisr1!=0 && i < 8; udcisr1 >>= 2, i++) { -+ UDCISR1 = UDCISR_INT(i, UDCISR_INT_MASK); -+ -+ if (udcisr1 & UDC_INT_FIFOERROR) { -+ printk(KERN_ERR" Endpoint %d fifo error\n", (i+16)); -+ } -+ -+ if (udcisr1 & UDC_INT_PACKETCMP) { -+ handle_ep(&dev->ep[i+16]); -+ handled = 1; -+ } -+ } -+ } -+ -+ /* we could also ask for 1 msec SOF (SIR) interrupts */ -+ -+ } while (handled); -+ return IRQ_HANDLED; -+} -+ -+static inline void validate_fifo_size(struct pxa27x_ep *pxa_ep, u8 bmAttributes) -+{ -+ switch (bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { -+ case USB_ENDPOINT_XFER_CONTROL: -+ pxa_ep->fifo_size = EP0_FIFO_SIZE; -+ break; -+ case USB_ENDPOINT_XFER_ISOC: -+ pxa_ep->fifo_size = ISO_FIFO_SIZE; -+ break; -+ case USB_ENDPOINT_XFER_BULK: -+ pxa_ep->fifo_size = BULK_FIFO_SIZE; -+ break; -+ case USB_ENDPOINT_XFER_INT: -+ pxa_ep->fifo_size = INT_FIFO_SIZE; -+ break; -+ default: -+ break; -+ } -+} -+ -+static void udc_init_ep(struct pxa27x_udc *dev) -+{ -+ int i; -+ -+ INIT_LIST_HEAD (&dev->gadget.ep_list); -+ INIT_LIST_HEAD (&dev->gadget.ep0->ep_list); -+ -+ for (i = 0; i < UDC_EP_NUM; i++) { -+ struct pxa27x_ep *ep = &dev->ep[i]; -+ -+ ep->dma = -1; -+ if (i != 0) { -+ memset(ep, 0, sizeof(*ep)); -+ } -+ INIT_LIST_HEAD (&ep->queue); -+ } -+} -+#define NAME_SIZE 18 -+ -+struct usb_ep* pxa27x_ep_config( -+ struct usb_gadget *gadget, -+ struct usb_endpoint_descriptor *desc, -+ int config, int interface, int alt -+) -+{ -+ u32 tmp ; -+ unsigned i; -+ char* name; -+ struct usb_ep * ep = NULL; -+ struct pxa27x_ep *pxa_ep = NULL; -+ struct pxa27x_udc *dev = the_controller; -+ -+ DMSG("pxa27x_config_ep is called\n"); -+ DMSG(" usb endpoint descriptor is:\n" -+ " bLength:%d\n" -+ " bDescriptorType:%x\n" -+ " bEndpointAddress:%x\n" -+ " bmAttributes:%x\n" -+ " wMaxPacketSize:%d\n", -+ desc->bLength, -+ desc->bDescriptorType,desc->bEndpointAddress, -+ desc->bmAttributes,desc->wMaxPacketSize); -+ -+ for (i = 1; i < UDC_EP_NUM; i++) { -+ if(!dev->ep[i].assigned) { -+ pxa_ep = &dev->ep[i]; -+ pxa_ep->assigned = 1; -+ pxa_ep->ep_num = i; -+ break; -+ } -+ } -+ if (unlikely(i == UDC_EP_NUM)) { -+ printk(KERN_ERR __FILE__ ": Failed to find a spare endpoint\n"); -+ return ep; -+ } -+ -+ -+ ep = &pxa_ep->ep; -+ -+ pxa_ep->dev = dev; -+ pxa_ep->desc = desc; -+ pxa_ep->pio_irqs = pxa_ep->dma_irqs = 0; -+ pxa_ep->dma = -1; -+ -+ if (!(desc->bEndpointAddress & 0xF)) -+ desc->bEndpointAddress |= i; -+ -+ if (!(desc->wMaxPacketSize)) { -+ validate_fifo_size(pxa_ep, desc->bmAttributes); -+ desc->wMaxPacketSize = pxa_ep->fifo_size; -+ } else -+ pxa_ep->fifo_size = desc->wMaxPacketSize; -+ -+ pxa_ep->dir_in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0; -+ pxa_ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; -+ pxa_ep->stopped = 1; -+ pxa_ep->dma_con = 0; -+ pxa_ep->config = config; -+ pxa_ep->interface = interface; -+ pxa_ep->aisn = alt; -+ -+ pxa_ep->reg_udccsr = &UDCCSR0 + i; -+ pxa_ep->reg_udcbcr = &UDCBCR0 + i; -+ pxa_ep->reg_udcdr = &UDCDR0 + i ; -+ pxa_ep->reg_udccr = &UDCCRA - 1 + i; -+#ifdef USE_DMA -+ pxa_ep->reg_drcmr = &DRCMR24 + i; -+#endif -+ -+#if 0 -+ DMSG("udccsr=0x%8x, udcbcr=0x%8x, udcdr=0x%8x," -+ "udccr0=0x%8x\n", -+ (unsigned)pxa_ep->reg_udccsr, -+ (unsigned)pxa_ep->reg_udcbcr, -+ (unsigned)pxa_ep->reg_udcdr, -+ (unsigned)pxa_ep->reg_udccr); -+#endif -+ /* Configure UDCCR */ -+ tmp = 0; -+ tmp |= (pxa_ep->config << UDCCONR_CN_S) & UDCCONR_CN; -+ tmp |= (pxa_ep->interface << UDCCONR_IN_S) & UDCCONR_IN; -+ tmp |= (pxa_ep->aisn << UDCCONR_AISN_S) & UDCCONR_AISN; -+ tmp |= (desc->bEndpointAddress << UDCCONR_EN_S) & UDCCONR_EN; -+ tmp |= (pxa_ep->ep_type << UDCCONR_ET_S) & UDCCONR_ET; -+ tmp |= (pxa_ep->dir_in) ? UDCCONR_ED : 0; -+ tmp |= (min(pxa_ep->fifo_size, (unsigned)desc->wMaxPacketSize) \ -+ << UDCCONR_MPS_S ) & UDCCONR_MPS; -+ tmp |= UDCCONR_DE | UDCCONR_EE; -+// tmp |= UDCCONR_EE; -+ -+ *pxa_ep->reg_udccr = tmp; -+ -+#ifdef USE_DMA -+ /* Only BULK use DMA */ -+ if ((pxa_ep->ep_type & USB_ENDPOINT_XFERTYPE_MASK)\ -+ == USB_ENDPOINT_XFER_BULK) -+ *pxa_ep->reg_udccsr = UDCCSR_DME; -+#endif -+ -+ DMSG("UDCCR: 0x%p is 0x%x\n", pxa_ep->reg_udccr,*pxa_ep->reg_udccr); -+ -+ /* Fill ep name*/ -+ name = kmalloc(NAME_SIZE, GFP_KERNEL); -+ if (!name) { -+ printk(KERN_ERR "%s: Error\n", __FUNCTION__); -+ return NULL; -+ } -+ -+ switch (pxa_ep->ep_type) { -+ case USB_ENDPOINT_XFER_BULK: -+ sprintf(name, "Bulk-%s-%d", (pxa_ep->dir_in ? "in":"out"), i); -+ break; -+ case USB_ENDPOINT_XFER_INT: -+ sprintf(name, "Interrupt-%s-%d", (pxa_ep->dir_in ? \ -+ "in":"out"), i); -+ break; -+ default: -+ sprintf(name, "endpoint-%s-%d", (pxa_ep->dir_in ? \ -+ "in":"out"), i); -+ break; -+ } -+ ep->name = name; -+ -+ ep->ops = &pxa27x_ep_ops; -+ ep->maxpacket = min((ushort)pxa_ep->fifo_size, desc->wMaxPacketSize); -+ -+ list_add_tail (&ep->ep_list, &gadget->ep_list); -+ return ep; -+} -+ -+EXPORT_SYMBOL(pxa27x_ep_config); -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void nop_release (struct device *dev) -+{ -+ DMSG("%s %s\n", __FUNCTION__, dev->bus_id); -+} -+ -+/* this uses load-time allocation and initialization (instead of -+ * doing it at run-time) to save code, eliminate fault paths, and -+ * be more obviously correct. -+ */ -+static struct pxa27x_udc memory = { -+ .gadget = { -+ .ops = &pxa27x_udc_ops, -+ .ep0 = &memory.ep[0].ep, -+ .name = driver_name, -+ .dev = { -+ .bus_id = "gadget", -+ .release = nop_release, -+ }, -+ }, -+ -+ /* control endpoint */ -+ .ep[0] = { -+ .ep = { -+ .name = ep0name, -+ .ops = &pxa27x_ep_ops, -+ .maxpacket = EP0_FIFO_SIZE, -+ }, -+ .dev = &memory, -+ .reg_udccsr = &UDCCSR0, -+ .reg_udcdr = &UDCDR0, -+ } -+}; -+ -+#define CP15R0_VENDOR_MASK 0xffffe000 -+ -+#define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/xscale */ -+ -+/* -+ * probe - binds to the platform device -+ */ -+static int __init pxa27x_udc_probe(struct platform_device *_dev) -+{ -+ struct pxa27x_udc *dev = &memory; -+ int retval; -+ u32 chiprev; -+ -+ /* insist on Intel/ARM/XScale */ -+ asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev)); -+ if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) { -+ printk(KERN_ERR "%s: not XScale!\n", driver_name); -+ return -ENODEV; -+ } -+ /* other non-static parts of init */ -+ dev->dev = &_dev->dev; -+ dev->mach = _dev->dev.platform_data; -+ -+ init_timer(&dev->timer); -+ dev->timer.function = udc_watchdog; -+ dev->timer.data = (unsigned long) dev; -+ -+ device_initialize(&dev->gadget.dev); -+ dev->gadget.dev.parent = &_dev->dev; -+ dev->gadget.dev.dma_mask = _dev->dev.dma_mask; -+ -+ the_controller = dev; -+ platform_set_drvdata(_dev, dev); -+ -+ udc_disable(dev); -+ udc_init_ep(dev); -+ udc_reinit(dev); -+ -+ /* irq setup after old hardware state is cleaned up */ -+ retval = request_irq(IRQ_USB, pxa27x_udc_irq, -+ SA_INTERRUPT, driver_name, dev); -+ if (retval != 0) { -+ printk(KERN_ERR "%s: can't get irq %i, err %d\n", -+ driver_name, IRQ_USB, retval); -+ return -EBUSY; -+ } -+ dev->got_irq = 1; -+ -+ create_proc_files(); -+ -+ return 0; -+} -+ -+static int __exit pxa27x_udc_remove(struct platform_device *_dev) -+{ -+ struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev); -+ -+ udc_disable(dev); -+ remove_proc_files(); -+ usb_gadget_unregister_driver(dev->driver); -+ -+ if (dev->got_irq) { -+ free_irq(IRQ_USB, dev); -+ dev->got_irq = 0; -+ } -+ if (machine_is_lubbock() && dev->got_disc) { -+ free_irq(LUBBOCK_USB_DISC_IRQ, dev); -+ dev->got_disc = 0; -+ } -+ platform_set_drvdata(_dev, 0); -+ the_controller = 0; -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static void pxa27x_udc_shutdown(struct platform_device *_dev) -+{ -+ struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev); -+ -+ udc_disable(dev); -+} -+ -+static int pxa27x_udc_suspend(struct platform_device *_dev, pm_message_t state) -+{ -+ int i; -+ struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev); -+ -+ DMSG("%s is called\n", __FUNCTION__); -+ dev->udccsr0 = UDCCSR0; -+ for(i=1; (iep[i].assigned) { -+ struct pxa27x_ep *ep = &dev->ep[i]; -+ -+ ep->udccsr_value = *ep->reg_udccsr; -+ ep->udccr_value = *ep->reg_udccr; -+ DMSG("EP%d, udccsr:0x%x, udccr:0x%x\n", -+ i, *ep->reg_udccsr, *ep->reg_udccr); -+ } -+ } -+ -+ udc_clear_mask_UDCCR(UDCCR_UDE); -+ pxa_set_cken(CKEN11_USB, 0); -+ // MST_MSCWR2 |= MST_MSCWR2_nUSBC_SC; -+ -+ return 0; -+} -+ -+static int pxa27x_udc_resume(struct platform_device *_dev) -+{ -+ int i; -+ struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev); -+ -+ DMSG("%s is called\n", __FUNCTION__); -+ -+ UDCCSR0 = dev->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME); -+ for (i=1; i < UDC_EP_NUM; i++) { -+ if (dev->ep[i].assigned) { -+ struct pxa27x_ep *ep = &dev->ep[i]; -+ -+ *ep->reg_udccsr = ep->udccsr_value; -+ *ep->reg_udccr = ep->udccr_value; -+ DMSG("EP%d, udccsr:0x%x, udccr:0x%x\n", -+ i, *ep->reg_udccsr, *ep->reg_udccr); -+ } -+ } -+ udc_enable(dev); -+ /* OTGPH bit is set when sleep mode is entered. -+ * it indicates that OTG pad is retaining its state. -+ * Upon exit from sleep mode and before clearing OTGPH, -+ * Software must configure the USB OTG pad, UDC, and UHC -+ * to the state they were in before entering sleep mode.*/ -+ PSSR |= PSSR_OTGPH; -+ return 0; -+} -+#endif -+ -+/*-------------------------------------------------------------------------*/ -+ -+static struct platform_driver udc_driver = { -+ .driver = { -+ .name = "pxa2xx-udc", -+ }, -+ .probe = pxa27x_udc_probe, -+ .remove = __exit_p(pxa27x_udc_remove), -+ -+#ifdef CONFIG_PM -+ // FIXME power management support -+ .shutdown = pxa27x_udc_shutdown, -+ .suspend = pxa27x_udc_suspend, -+ .resume = pxa27x_udc_resume -+#endif -+}; -+ -+static int __init udc_init(void) -+{ -+ printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION); -+ return platform_driver_register(&udc_driver); -+} -+module_init(udc_init); -+ -+static void __exit udc_exit(void) -+{ -+ platform_driver_unregister(&udc_driver); -+} -+module_exit(udc_exit); -+ -+MODULE_DESCRIPTION(DRIVER_DESC); -+MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); -+MODULE_LICENSE("GPL"); -+ -Index: linux-2.6.21.7/drivers/usb/gadget/pxa27x_udc.h -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/drivers/usb/gadget/pxa27x_udc.h -@@ -0,0 +1,332 @@ -+/* -+ * linux/drivers/usb/gadget/pxa27x_udc.h -+ * Intel PXA27x on-chip full speed USB device controller -+ * -+ * Copyright (C) 2003 Robert Schwebel , Pengutronix -+ * Copyright (C) 2003 David Brownell -+ * Copyright (C) 2004 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __LINUX_USB_GADGET_PXA27X_H -+#define __LINUX_USB_GADGET_PXA27X_H -+ -+#include -+ -+struct pxa27x_udc; -+ -+struct pxa27x_ep { -+ struct usb_ep ep; -+ struct pxa27x_udc *dev; -+ -+ const struct usb_endpoint_descriptor *desc; -+ struct list_head queue; -+ unsigned long pio_irqs; -+ unsigned long dma_irqs; -+ -+ int dma; -+ unsigned fifo_size; -+ unsigned ep_num; -+ unsigned ep_type; -+ -+ unsigned stopped : 1; -+ unsigned dma_con : 1; -+ unsigned dir_in : 1; -+ unsigned assigned : 1; -+ -+ unsigned config; -+ unsigned interface; -+ unsigned aisn; -+ /* UDCCSR = UDC Control/Status Register for this EP -+ * UBCR = UDC Byte Count Remaining (contents of OUT fifo) -+ * UDCDR = UDC Endpoint Data Register (the fifo) -+ * UDCCR = UDC Endpoint Configuration Registers -+ * DRCM = DMA Request Channel Map -+ */ -+ volatile u32 *reg_udccsr; -+ volatile u32 *reg_udcbcr; -+ volatile u32 *reg_udcdr; -+ volatile u32 *reg_udccr; -+#ifdef USE_DMA -+ volatile u32 *reg_drcmr; -+#define drcmr(n) .reg_drcmr = & DRCMR ## n , -+#else -+#define drcmr(n) -+#endif -+ -+#ifdef CONFIG_PM -+ unsigned udccsr_value; -+ unsigned udccr_value; -+#endif -+}; -+ -+struct pxa27x_request { -+ struct usb_request req; -+ struct list_head queue; -+}; -+ -+enum ep0_state { -+ EP0_IDLE, -+ EP0_IN_DATA_PHASE, -+ EP0_OUT_DATA_PHASE, -+// EP0_END_XFER, -+ EP0_STALL, -+ EP0_NO_ACTION -+}; -+ -+#define EP0_FIFO_SIZE ((unsigned)16) -+#define BULK_FIFO_SIZE ((unsigned)64) -+#define ISO_FIFO_SIZE ((unsigned)256) -+#define INT_FIFO_SIZE ((unsigned)8) -+ -+struct udc_stats { -+ struct ep0stats { -+ unsigned long ops; -+ unsigned long bytes; -+ } read, write; -+ unsigned long irqs; -+}; -+ -+#ifdef CONFIG_USB_PXA27X_SMALL -+/* when memory's tight, SMALL config saves code+data. */ -+//#undef USE_DMA -+//#define UDC_EP_NUM 3 -+#endif -+ -+#ifndef UDC_EP_NUM -+#define UDC_EP_NUM 24 -+#endif -+ -+struct pxa27x_udc { -+ struct usb_gadget gadget; -+ struct usb_gadget_driver *driver; -+ -+ enum ep0_state ep0state; -+ struct udc_stats stats; -+ unsigned got_irq : 1, -+ got_disc : 1, -+ has_cfr : 1, -+ req_pending : 1, -+ req_std : 1, -+ req_config : 1; -+ -+#define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200)) -+ struct timer_list timer; -+ -+ struct device *dev; -+ struct pxa2xx_udc_mach_info *mach; -+ u64 dma_mask; -+ struct pxa27x_ep ep [UDC_EP_NUM]; -+ -+ unsigned configuration, -+ interface, -+ alternate; -+#ifdef CONFIG_PM -+ unsigned udccsr0; -+#endif -+}; -+ -+/*-------------------------------------------------------------------------*/ -+#if 0 -+#ifdef DEBUG -+#define HEX_DISPLAY(n) do { \ -+ if (machine_is_mainstone())\ -+ { MST_LEDDAT1 = (n); } \ -+ } while(0) -+ -+#define HEX_DISPLAY1(n) HEX_DISPLAY(n) -+ -+#define HEX_DISPLAY2(n) do { \ -+ if (machine_is_mainstone()) \ -+ { MST_LEDDAT2 = (n); } \ -+ } while(0) -+ -+#endif /* DEBUG */ -+#endif -+/*-------------------------------------------------------------------------*/ -+ -+/* LEDs are only for debug */ -+#ifndef HEX_DISPLAY -+#define HEX_DISPLAY(n) do {} while(0) -+#endif -+ -+#ifndef LED_CONNECTED_ON -+#define LED_CONNECTED_ON do {} while(0) -+#define LED_CONNECTED_OFF do {} while(0) -+#endif -+#ifndef LED_EP0_ON -+#define LED_EP0_ON do {} while (0) -+#define LED_EP0_OFF do {} while (0) -+#endif -+ -+static struct pxa27x_udc *the_controller; -+ -+#if 0 -+/*-------------------------------------------------------------------------*/ -+ -+ -+/* one GPIO should be used to detect host disconnect */ -+static inline int is_usb_connected(void) -+{ -+ if (!the_controller->mach->udc_is_connected) -+ return 1; -+ return the_controller->mach->udc_is_connected(); -+} -+ -+/* one GPIO should force the host to see this device (or not) */ -+static inline void make_usb_disappear(void) -+{ -+ if (!the_controller->mach->udc_command) -+ return; -+ the_controller->mach->udc_command(PXA27X_UDC_CMD_DISCONNECT); -+} -+ -+static inline void let_usb_appear(void) -+{ -+ if (!the_controller->mach->udc_command) -+ return; -+ the_controller->mach->udc_command(PXA2XX_UDC_CMD_CONNECT); -+} -+#endif -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* -+ * Debugging support vanishes in non-debug builds. DBG_NORMAL should be -+ * mostly silent during normal use/testing, with no timing side-effects. -+ */ -+#define DBG_NORMAL 1 /* error paths, device state transitions */ -+#define DBG_VERBOSE 2 /* add some success path trace info */ -+#define DBG_NOISY 3 /* ... even more: request level */ -+#define DBG_VERY_NOISY 4 /* ... even more: packet level */ -+ -+#ifdef DEBUG -+ -+static const char *state_name[] = { -+ "EP0_IDLE", -+ "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE", -+ "EP0_END_XFER", "EP0_STALL" -+}; -+ -+#define DMSG(stuff...) printk(KERN_ERR "udc: " stuff) -+ -+#ifdef VERBOSE -+# define UDC_DEBUG DBG_VERBOSE -+#else -+# define UDC_DEBUG DBG_NORMAL -+#endif -+ -+static void __attribute__ ((__unused__)) -+dump_udccr(const char *label) -+{ -+ u32 udccr = UDCCR; -+ DMSG("%s 0x%08x =%s%s%s%s%s%s%s%s%s%s, con=%d,inter=%d,altinter=%d\n", -+ label, udccr, -+ (udccr & UDCCR_OEN) ? " oen":"", -+ (udccr & UDCCR_AALTHNP) ? " aalthnp":"", -+ (udccr & UDCCR_AHNP) ? " rem" : "", -+ (udccr & UDCCR_BHNP) ? " rstir" : "", -+ (udccr & UDCCR_DWRE) ? " dwre" : "", -+ (udccr & UDCCR_SMAC) ? " smac" : "", -+ (udccr & UDCCR_EMCE) ? " emce" : "", -+ (udccr & UDCCR_UDR) ? " udr" : "", -+ (udccr & UDCCR_UDA) ? " uda" : "", -+ (udccr & UDCCR_UDE) ? " ude" : "", -+ (udccr & UDCCR_ACN) >> UDCCR_ACN_S, -+ (udccr & UDCCR_AIN) >> UDCCR_AIN_S, -+ (udccr & UDCCR_AAISN)>> UDCCR_AAISN_S ); -+} -+ -+static void __attribute__ ((__unused__)) -+dump_udccsr0(const char *label) -+{ -+ u32 udccsr0 = UDCCSR0; -+ -+ DMSG("%s %s 0x%08x =%s%s%s%s%s%s%s\n", -+ label, state_name[the_controller->ep0state], udccsr0, -+ (udccsr0 & UDCCSR0_SA) ? " sa" : "", -+ (udccsr0 & UDCCSR0_RNE) ? " rne" : "", -+ (udccsr0 & UDCCSR0_FST) ? " fst" : "", -+ (udccsr0 & UDCCSR0_SST) ? " sst" : "", -+ (udccsr0 & UDCCSR0_DME) ? " dme" : "", -+ (udccsr0 & UDCCSR0_IPR) ? " ipr" : "", -+ (udccsr0 & UDCCSR0_OPC) ? " opr" : ""); -+} -+ -+static void __attribute__ ((__unused__)) -+dump_state(struct pxa27x_udc *dev) -+{ -+ unsigned i; -+ -+ DMSG("%s, udcicr %02X.%02X, udcsir %02X.%02x, udcfnr %02X\n", -+ state_name[dev->ep0state], -+ UDCICR1, UDCICR0, UDCISR1, UDCISR0, UDCFNR); -+ dump_udccr("udccr"); -+ -+ if (!dev->driver) { -+ DMSG("no gadget driver bound\n"); -+ return; -+ } else -+ DMSG("ep0 driver '%s'\n", dev->driver->driver.name); -+ -+ -+ dump_udccsr0 ("udccsr0"); -+ DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n", -+ dev->stats.write.bytes, dev->stats.write.ops, -+ dev->stats.read.bytes, dev->stats.read.ops); -+ -+ for (i = 1; i < UDC_EP_NUM; i++) { -+ if (dev->ep [i].desc == 0) -+ continue; -+ DMSG ("udccs%d = %02x\n", i, *dev->ep->reg_udccsr); -+ } -+} -+ -+#if 0 -+static void dump_regs(u8 ep) -+{ -+ DMSG("EP:%d UDCCSR:0x%08x UDCBCR:0x%08x\n UDCCR:0x%08x\n", -+ ep,UDCCSN(ep), UDCBCN(ep), UDCCN(ep)); -+} -+static void dump_req (struct pxa27x_request *req) -+{ -+ struct usb_request *r = &req->req; -+ -+ DMSG("%s: buf:0x%08x length:%d dma:0x%08x actual:%d\n", -+ __FUNCTION__, (unsigned)r->buf, r->length, -+ r->dma, r->actual); -+} -+#endif -+ -+#else -+ -+#define DMSG(stuff...) do{}while(0) -+ -+#define dump_udccr(x) do{}while(0) -+#define dump_udccsr0(x) do{}while(0) -+#define dump_state(x) do{}while(0) -+ -+#define UDC_DEBUG ((unsigned)0) -+ -+#endif -+ -+#define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0) -+ -+#define WARN(stuff...) printk(KERN_WARNING "udc: " stuff) -+#define INFO(stuff...) printk(KERN_INFO "udc: " stuff) -+ -+ -+#endif /* __LINUX_USB_GADGET_PXA27X_H */ diff --git a/target/linux/pxa/patches-2.6.21/037-gumstix-pxa270-usb-host.patch b/target/linux/pxa/patches-2.6.21/037-gumstix-pxa270-usb-host.patch deleted file mode 100644 index 3462770912..0000000000 --- a/target/linux/pxa/patches-2.6.21/037-gumstix-pxa270-usb-host.patch +++ /dev/null @@ -1,366 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/gumstix.c -+++ linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -178,9 +179,34 @@ static struct platform_device *devices[] - &gum_audio_device, - }; - -+#ifdef CONFIG_ARCH_GUMSTIX_VERDEX -+static int gumstix_ohci_init(struct device *dev) -+{ -+ /* setup Port1 GPIO pin. */ -+ //pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */ -+ //pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */ -+ -+ // Turn on port 2 in host mode -+ UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE; -+ -+ UHCHR = (UHCHR) & -+ ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE); -+ -+ return 0; -+} -+ -+static struct pxaohci_platform_data gumstix_ohci_platform_data = { -+ .port_mode = PMM_PERPORT_MODE, -+ .init = gumstix_ohci_init, -+}; -+#endif -+ - static void __init gumstix_init(void) - { - pxa_set_mci_info(&gumstix_mci_platform_data); -+#ifdef CONFIG_ARCH_GUMSTIX_VERDEX -+ pxa_set_ohci_info(&gumstix_ohci_platform_data); -+#endif - pxa_set_udc_info(&gumstix_udc_info); - #if defined(CONFIG_FB_PXA_ALPS_CDOLLAR) | defined(CONFIG_FB_PXA_SHARP_LQ043_PSP) | defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C) - set_pxa_fb_info(&gumstix_fb_info); -Index: linux-2.6.21.7/drivers/usb/gadget/ether.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/ether.c -+++ linux-2.6.21.7/drivers/usb/gadget/ether.c -@@ -260,6 +260,8 @@ MODULE_PARM_DESC(host_addr, "Host Ethern - - #ifdef CONFIG_USB_GADGET_PXA27X - #define DEV_CONFIG_CDC -+extern struct usb_ep* pxa27x_ep_config(struct usb_gadget *gadget, -+ struct usb_endpoint_descriptor *desc,int config,int interface,int alt); - #endif - - #ifdef CONFIG_USB_GADGET_S3C2410 -@@ -482,15 +484,15 @@ eth_config = { - #ifdef CONFIG_USB_ETH_RNDIS - static struct usb_config_descriptor - rndis_config = { -- .bLength = sizeof rndis_config, -+ .bLength = sizeof rndis_config, - .bDescriptorType = USB_DT_CONFIG, - - /* compute wTotalLength on the fly */ -- .bNumInterfaces = 2, -+ .bNumInterfaces = 2, - .bConfigurationValue = DEV_RNDIS_CONFIG_VALUE, -- .iConfiguration = STRING_RNDIS, -+ .iConfiguration = STRING_RNDIS, - .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, -- .bMaxPower = 50, -+ .bMaxPower = 50, - }; - #endif - -@@ -532,15 +534,15 @@ control_intf = { - #ifdef CONFIG_USB_ETH_RNDIS - static const struct usb_interface_descriptor - rndis_control_intf = { -- .bLength = sizeof rndis_control_intf, -+ .bLength = sizeof rndis_control_intf, - .bDescriptorType = USB_DT_INTERFACE, - - .bInterfaceNumber = 0, -- .bNumEndpoints = 1, -+ .bNumEndpoints = 1, - .bInterfaceClass = USB_CLASS_COMM, - .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, - .bInterfaceProtocol = USB_CDC_ACM_PROTO_VENDOR, -- .iInterface = STRING_RNDIS_CONTROL, -+ .iInterface = STRING_RNDIS_CONTROL, - }; - #endif - -@@ -1342,7 +1344,7 @@ static void rndis_response_complete (str - - static void rndis_command_complete (struct usb_ep *ep, struct usb_request *req) - { -- struct eth_dev *dev = ep->driver_data; -+ struct eth_dev *dev = ep->driver_data; - int status; - - /* received RNDIS command from USB_CDC_SEND_ENCAPSULATED_COMMAND */ -@@ -1578,7 +1580,7 @@ done_set_intf: - - /* return the result */ - buf = rndis_get_next_response (dev->rndis_config, -- &value); -+ &value); - if (buf) { - memcpy (req->buf, buf, value); - req->complete = rndis_response_complete; -@@ -2064,7 +2066,7 @@ static void eth_req_free (struct usb_ep - static void - rndis_control_ack_complete (struct usb_ep *ep, struct usb_request *req) - { -- struct eth_dev *dev = ep->driver_data; -+ struct eth_dev *dev = ep->driver_data; - - if (req->status || req->actual != req->length) - DEBUG (dev, -@@ -2415,7 +2417,27 @@ eth_bind (struct usb_gadget *gadget) - - /* all we really need is bulk IN/OUT */ - usb_ep_autoconfig_reset (gadget); -+#ifdef CONFIG_USB_GADGET_PXA27X -+#ifdef CONFIG_USB_ETH_RNDIS -+ in_ep = pxa27x_ep_config (gadget, &fs_source_desc, -+ DEV_RNDIS_CONFIG_VALUE, -+ (int)rndis_data_intf.bInterfaceNumber, -+ (int)rndis_data_intf.bAlternateSetting); -+#elif defined(DEV_CONFIG_CDC) -+ in_ep = pxa27x_ep_config (gadget, &fs_source_desc, -+ DEV_CONFIG_VALUE, -+ (int)data_intf.bInterfaceNumber, -+ (int)data_intf.bAlternateSetting); -+#elif defined(DEV_CONFIG_SUBSET) -+ in_ep = pxa27x_ep_config (gadget, &fs_source_desc, -+ DEV_CONFIG_VALUE, -+ (int)subset_data_intf.bInterfaceNumber, -+ (int)subset_data_intf.bAlternateSetting); -+ -+#endif //CONFIG_USB_ETH_RNDIS -+#else - in_ep = usb_ep_autoconfig (gadget, &fs_source_desc); -+#endif //CONFIG_USB_GADGET_PXA27X - if (!in_ep) { - autoconf_fail: - dev_err (&gadget->dev, -@@ -2425,7 +2447,26 @@ autoconf_fail: - } - in_ep->driver_data = in_ep; /* claim */ - -+#ifdef CONFIG_USB_GADGET_PXA27X -+#ifdef CONFIG_USB_ETH_RNDIS -+ out_ep = pxa27x_ep_config (gadget, &fs_sink_desc, -+ DEV_RNDIS_CONFIG_VALUE, -+ (int)rndis_data_intf.bInterfaceNumber, -+ (int)rndis_data_intf.bAlternateSetting); -+#elif defined(DEV_CONFIG_CDC) -+ out_ep = pxa27x_ep_config (gadget, &fs_sink_desc, -+ DEV_CONFIG_VALUE, -+ (int)data_intf.bInterfaceNumber, -+ (int)data_intf.bAlternateSetting); -+#elif defined(DEV_CONFIG_SUBSET) -+ out_ep = pxa27x_ep_config (gadget, &fs_sink_desc, -+ DEV_CONFIG_VALUE, -+ (int)subset_data_intf.bInterfaceNumber, -+ (int)subset_data_intf.bAlternateSetting); -+#endif //CONFIG_USB_ETH_RNDIS -+#else - out_ep = usb_ep_autoconfig (gadget, &fs_sink_desc); -+#endif //CONFIG_USB_GADGET_PXA27X - if (!out_ep) - goto autoconf_fail; - out_ep->driver_data = out_ep; /* claim */ -@@ -2435,7 +2476,22 @@ autoconf_fail: - * Since some hosts expect one, try to allocate one anyway. - */ - if (cdc || rndis) { -+#ifdef CONFIG_USB_GADGET_PXA27X -+#ifdef CONFIG_USB_ETH_RNDIS -+ status_ep = pxa27x_ep_config (gadget, &fs_status_desc, -+ DEV_RNDIS_CONFIG_VALUE, -+ (int)rndis_control_intf.bInterfaceNumber, -+ (int)rndis_control_intf.bAlternateSetting); -+#elif defined(DEV_CONFIG_CDC) -+ status_ep = pxa27x_ep_config (gadget, &fs_status_desc, -+ DEV_CONFIG_VALUE, -+ (int)control_intf.bInterfaceNumber, -+ (int)control_intf.bAlternateSetting); -+ -+#endif //CONFIG_USB_ETH_RNDIS -+#else - status_ep = usb_ep_autoconfig (gadget, &fs_status_desc); -+#endif //CONFIG_USB_GADGET_PXA27X - if (status_ep) { - status_ep->driver_data = status_ep; /* claim */ - } else if (rndis) { -@@ -2444,11 +2500,13 @@ autoconf_fail: - gadget->name); - return -ENODEV; - #ifdef DEV_CONFIG_CDC -+#ifndef CONFIG_USB_GADGET_PXA27X - /* pxa25x only does CDC subset; often used with RNDIS */ - } else if (cdc) { - control_intf.bNumEndpoints = 0; - /* FIXME remove endpoint from descriptor list */ - #endif -+#endif - } - } - #endif -Index: linux-2.6.21.7/drivers/usb/gadget/file_storage.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/file_storage.c -+++ linux-2.6.21.7/drivers/usb/gadget/file_storage.c -@@ -280,6 +280,12 @@ MODULE_LICENSE("Dual BSD/GPL"); - #define DRIVER_PRODUCT_ID 0xa4a5 // Linux-USB File-backed Storage Gadget - - -+ -+#ifdef CONFIG_USB_GADGET_PXA27X -+extern struct usb_ep* pxa27x_ep_config(struct usb_gadget *gadget, -+ struct usb_endpoint_descriptor *desc,int config,int interface,int alt); -+#endif -+ - /* - * This driver assumes self-powered hardware and has no way for users to - * trigger remote wakeup. It uses autoconfiguration to select endpoints -@@ -3920,20 +3926,32 @@ static int __init fsg_bind(struct usb_ga - - /* Find all the endpoints we will use */ - usb_ep_autoconfig_reset(gadget); -+#ifdef CONFIG_USB_GADGET_PXA27X -+ ep = pxa27x_ep_config(gadget, &fs_bulk_in_desc, CONFIG_VALUE, 0, 0); -+#else - ep = usb_ep_autoconfig(gadget, &fs_bulk_in_desc); -+#endif - if (!ep) - goto autoconf_fail; - ep->driver_data = fsg; // claim the endpoint - fsg->bulk_in = ep; - -+#ifdef CONFIG_USB_GADGET_PXA27X -+ ep = pxa27x_ep_config(gadget, &fs_bulk_out_desc, CONFIG_VALUE, 0, 0); -+#else - ep = usb_ep_autoconfig(gadget, &fs_bulk_out_desc); -+#endif - if (!ep) - goto autoconf_fail; - ep->driver_data = fsg; // claim the endpoint - fsg->bulk_out = ep; - - if (transport_is_cbi()) { -+#ifdef CONFIG_USB_GADGET_PXA27X -+ ep = pxa27x_ep_config(gadget, &fs_intr_in_desc, CONFIG_VALUE, 0, 0); -+#else - ep = usb_ep_autoconfig(gadget, &fs_intr_in_desc); -+#endif - if (!ep) - goto autoconf_fail; - ep->driver_data = fsg; // claim the endpoint -@@ -4063,6 +4081,7 @@ autoconf_fail: - rc = -ENOTSUPP; - - out: -+ ERROR(fsg, "cleaning up on the way out\n"); - fsg->state = FSG_STATE_TERMINATED; // The thread is dead - fsg_unbind(gadget); - close_all_backing_files(fsg); -Index: linux-2.6.21.7/drivers/usb/gadget/serial.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/serial.c -+++ linux-2.6.21.7/drivers/usb/gadget/serial.c -@@ -126,6 +126,10 @@ static int debug = 1; - #define GS_LOG2_NOTIFY_INTERVAL 5 /* 1 << 5 == 32 msec */ - #define GS_NOTIFY_MAXPACKET 8 - -+#ifdef CONFIG_USB_GADGET_PXA27X -+extern struct usb_ep* pxa27x_ep_config(struct usb_gadget *gadget, -+ struct usb_endpoint_descriptor *desc,int config,int interface,int alt); -+#endif - - /* Structures */ - -@@ -1378,20 +1382,32 @@ static int __init gs_bind(struct usb_gad - - usb_ep_autoconfig_reset(gadget); - -+#ifdef CONFIG_USB_GADGET_PXA27X -+ ep = pxa27x_ep_config(gadget, &gs_fullspeed_in_desc, use_acm ? GS_ACM_CONFIG_ID : GS_BULK_CONFIG_ID, gs_bulk_interface_desc.bInterfaceNumber, gs_bulk_interface_desc.bAlternateSetting); -+#else - ep = usb_ep_autoconfig(gadget, &gs_fullspeed_in_desc); -+#endif - if (!ep) - goto autoconf_fail; - EP_IN_NAME = ep->name; - ep->driver_data = ep; /* claim the endpoint */ - -+#ifdef CONFIG_USB_GADGET_PXA27X -+ ep = pxa27x_ep_config(gadget, &gs_fullspeed_out_desc, use_acm ? GS_ACM_CONFIG_ID : GS_BULK_CONFIG_ID, gs_bulk_interface_desc.bInterfaceNumber, gs_bulk_interface_desc.bAlternateSetting); -+#else - ep = usb_ep_autoconfig(gadget, &gs_fullspeed_out_desc); -+#endif - if (!ep) - goto autoconf_fail; - EP_OUT_NAME = ep->name; - ep->driver_data = ep; /* claim the endpoint */ - - if (use_acm) { -+#ifdef CONFIG_USB_GADGET_PXA27X -+ ep = pxa27x_ep_config(gadget, &gs_fullspeed_notify_desc, GS_BULK_CONFIG_ID, gs_control_interface_desc.bInterfaceNumber, gs_control_interface_desc.bAlternateSetting); -+#else - ep = usb_ep_autoconfig(gadget, &gs_fullspeed_notify_desc); -+#endif - if (!ep) { - printk(KERN_ERR "gs_bind: cannot run ACM on %s\n", gadget->name); - goto autoconf_fail; -Index: linux-2.6.21.7/drivers/usb/gadget/zero.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/usb/gadget/zero.c -+++ linux-2.6.21.7/drivers/usb/gadget/zero.c -@@ -212,6 +212,11 @@ module_param (loopdefault, bool, S_IRUGO - #define STRING_SOURCE_SINK 250 - #define STRING_LOOPBACK 251 - -+#ifdef CONFIG_USB_GADGET_PXA27X -+extern struct usb_ep* pxa27x_ep_config(struct usb_gadget *gadget, -+ struct usb_endpoint_descriptor *desc,int config,int interface,int alt); -+#endif -+ - /* - * This device advertises two configurations; these numbers work - * on a pxa250 as well as more flexible hardware. -@@ -1155,7 +1160,11 @@ zero_bind (struct usb_gadget *gadget) - * but there may also be important quirks to address. - */ - usb_ep_autoconfig_reset (gadget); -+#ifdef CONFIG_USB_GADGET_PXA27X -+ ep = pxa27x_ep_config(gadget, &fs_source_desc, CONFIG_SOURCE_SINK, source_sink_intf.bInterfaceNumber, source_sink_intf.bAlternateSetting); -+#else - ep = usb_ep_autoconfig (gadget, &fs_source_desc); -+#endif - if (!ep) { - autoconf_fail: - printk (KERN_ERR "%s: can't autoconfigure on %s\n", -@@ -1164,8 +1173,12 @@ autoconf_fail: - } - EP_IN_NAME = ep->name; - ep->driver_data = ep; /* claim */ -- -+ -+#ifdef CONFIG_USB_GADGET_PXA27X -+ ep = pxa27x_ep_config(gadget, &fs_sink_desc, CONFIG_SOURCE_SINK, source_sink_intf.bInterfaceNumber, source_sink_intf.bAlternateSetting); -+#else - ep = usb_ep_autoconfig (gadget, &fs_sink_desc); -+#endif - if (!ep) - goto autoconf_fail; - EP_OUT_NAME = ep->name; diff --git a/target/linux/pxa/patches-2.6.21/038-cpufreq-fixup.patch b/target/linux/pxa/patches-2.6.21/038-cpufreq-fixup.patch deleted file mode 100644 index ddd2919d8b..0000000000 --- a/target/linux/pxa/patches-2.6.21/038-cpufreq-fixup.patch +++ /dev/null @@ -1,26 +0,0 @@ -Index: linux-2.6.21.7/drivers/cpufreq/cpufreq_ondemand.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/cpufreq/cpufreq_ondemand.c -+++ linux-2.6.21.7/drivers/cpufreq/cpufreq_ondemand.c -@@ -573,7 +573,7 @@ static int cpufreq_governor_dbs(struct c - return 0; - } - --static struct cpufreq_governor cpufreq_gov_dbs = { -+struct cpufreq_governor cpufreq_gov_dbs = { - .name = "ondemand", - .governor = cpufreq_governor_dbs, - .owner = THIS_MODULE, -Index: linux-2.6.21.7/drivers/cpufreq/cpufreq_conservative.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/cpufreq/cpufreq_conservative.c -+++ linux-2.6.21.7/drivers/cpufreq/cpufreq_conservative.c -@@ -551,7 +551,7 @@ static int cpufreq_governor_dbs(struct c - return 0; - } - --static struct cpufreq_governor cpufreq_gov_dbs = { -+struct cpufreq_governor cpufreq_gov_dbs = { - .name = "conservative", - .governor = cpufreq_governor_dbs, - .owner = THIS_MODULE, diff --git a/target/linux/pxa/patches-2.6.21/040-pxa-regs-fixup.patch b/target/linux/pxa/patches-2.6.21/040-pxa-regs-fixup.patch deleted file mode 100644 index 2f8923b890..0000000000 --- a/target/linux/pxa/patches-2.6.21/040-pxa-regs-fixup.patch +++ /dev/null @@ -1,12 +0,0 @@ -Index: linux-2.6.21.7/include/asm-arm/arch-pxa/udc.h -=================================================================== ---- linux-2.6.21.7.orig/include/asm-arm/arch-pxa/udc.h -+++ linux-2.6.21.7/include/asm-arm/arch-pxa/udc.h -@@ -5,6 +5,7 @@ - * USB Device Controller (UDC) is wired. - * - */ -+#include - #include - - extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); diff --git a/target/linux/pxa/patches-2.6.21/041-gumstix-fb-logo.patch b/target/linux/pxa/patches-2.6.21/041-gumstix-fb-logo.patch deleted file mode 100644 index ad222b33b2..0000000000 --- a/target/linux/pxa/patches-2.6.21/041-gumstix-fb-logo.patch +++ /dev/null @@ -1,10455 +0,0 @@ -Index: linux-2.6.21.7/drivers/video/logo/logo_linux_clut224.ppm -=================================================================== ---- linux-2.6.21.7.orig/drivers/video/logo/logo_linux_clut224.ppm -+++ linux-2.6.21.7/drivers/video/logo/logo_linux_clut224.ppm -@@ -1,1604 +1,8848 @@ - P3 --# Standard 224-color Linux logo --80 80 -+480 145 - 255 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 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3 3 3 3 3 0 0 0 0 0 0 -+3 3 3 0 0 0 0 0 0 0 0 0 3 3 3 4 4 4 3 3 3 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 3 3 3 4 4 4 3 3 3 0 0 0 0 0 0 0 0 0 3 3 3 -+0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 -+4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 -+4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 -+4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 -+4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 -+3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 -+4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 -+4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 -+3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 -+ diff --git a/target/linux/pxa/patches-2.6.21/042-gumstix-pxa270-mmc.patch b/target/linux/pxa/patches-2.6.21/042-gumstix-pxa270-mmc.patch deleted file mode 100644 index c6b6323f3b..0000000000 --- a/target/linux/pxa/patches-2.6.21/042-gumstix-pxa270-mmc.patch +++ /dev/null @@ -1,33 +0,0 @@ -Index: linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/gumstix.c -+++ linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -@@ -33,8 +33,9 @@ - - static struct pxamci_platform_data gumstix_mci_platform_data; - --static int gumstix_mci_init(struct device *dev, irqreturn_t (*gumstix_detect_int)(int, void *, struct pt_regs *), void *data) -+static int gumstix_mci_init(struct device *dev, irq_handler_t gumstix_detect_int, void *data) - { -+#ifndef CONFIG_ARCH_GUMSTIX_VERDEX - int err; - - pxa_gpio_mode(GPIO6_MMCCLK_MD); -@@ -55,6 +56,17 @@ static int gumstix_mci_init(struct devic - } - - err = set_irq_type(GUMSTIX_IRQ_GPIO_nSD_DETECT, IRQT_BOTHEDGE); -+#else -+ // Setup GPIOs for MMC on the 120-pin connector -+ // There is no card detect on a uSD connector so no interrupt to register -+ // There is no WP detect GPIO line either -+ pxa_gpio_mode(GPIO92_MMCDAT0_MD); -+ pxa_gpio_mode(GPIO112_MMCCMD_MD); -+ pxa_gpio_mode(GPIO110_MMCDAT2_MD); -+ pxa_gpio_mode(GPIO111_MMCDAT3_MD); -+ pxa_gpio_mode(GPIO109_MMCDAT1_MD); -+ pxa_gpio_mode(GPIO32_MMCCLK_MD); -+#endif - - return 0; - } diff --git a/target/linux/pxa/patches-2.6.21/043-pxafb-18bpp-mode.patch b/target/linux/pxa/patches-2.6.21/043-pxafb-18bpp-mode.patch deleted file mode 100644 index f8a6c1ad69..0000000000 --- a/target/linux/pxa/patches-2.6.21/043-pxafb-18bpp-mode.patch +++ /dev/null @@ -1,433 +0,0 @@ -Index: linux-2.6.21.7/drivers/video/pxafb.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/video/pxafb.c -+++ linux-2.6.21.7/drivers/video/pxafb.c -@@ -191,6 +191,10 @@ static int pxafb_bpp_to_lccr3(struct fb_ - case 4: ret = LCCR3_4BPP; break; - case 8: ret = LCCR3_8BPP; break; - case 16: ret = LCCR3_16BPP; break; -+ case 18: ret = (var->nonstd == 24 ? LCCR3_18BPP_PACKED : LCCR3_18BPP); break; -+ case 19: ret = (var->nonstd == 24 ? LCCR3_19BPP_PACKED : LCCR3_19BPP); break; -+ case 24: ret = LCCR3_24BPP; break; -+ case 25: ret = LCCR3_25BPP; break; - } - return ret; - } -@@ -204,11 +208,12 @@ static int pxafb_bpp_to_lccr3(struct fb_ - */ - static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) - { -- /* -- * Period = pixclock * bits_per_byte * bytes_per_transfer -- * / memory_bits_per_pixel; -- */ -- return var->pixclock * 8 * 16 / var->bits_per_pixel; -+ /* -+ * Period = pixclock * bits_per_byte * bytes_per_transfer -+ * / memory_bits_per_pixel; -+ */ -+ struct pxafb_mach_info *inf = fbi->dev->platform_data; -+ return var->pixclock * 8 * 16 / (var->nonstd ? var->nonstd : var->bits_per_pixel); - } - - extern unsigned int get_clk_frequency_khz(int info); -@@ -307,6 +312,26 @@ static int pxafb_check_var(struct fb_var - var->green.offset = 5; var->green.length = 6; - var->blue.offset = 0; var->blue.length = 5; - var->transp.offset = var->transp.length = 0; -+ } else if (var->bits_per_pixel == 18) { -+ var->transp.offset = var->transp.length = 0; -+ var->red.offset = 12; var->red.length=6; -+ var->green.offset = 6; var->green.length=6; -+ var->blue.offset = 0; var->blue.length=6; -+ } else if (var->bits_per_pixel == 19) { -+ var->transp.offset = 18; var->transp.length = 1; -+ var->red.offset = 12; var->red.length=6; -+ var->green.offset = 6; var->green.length=6; -+ var->blue.offset = 0; var->blue.length=6; -+ } else if (var->bits_per_pixel == 24) { -+ var->transp.offset = var->transp.length = 0; -+ var->red.offset = 16; var->red.length=8; -+ var->green.offset = 8; var->green.length=8; -+ var->blue.offset = 0; var->blue.length=8; -+ } else if (var->bits_per_pixel == 25) { -+ var->transp.offset = 18; var->transp.length = 1; -+ var->red.offset = 16; var->red.length=8; -+ var->green.offset = 8; var->green.length=8; -+ var->blue.offset = 0; var->blue.length=8; - } else { - var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0; - var->red.length = 8; -@@ -342,7 +367,7 @@ static int pxafb_set_par(struct fb_info - - pr_debug("pxafb: set_par\n"); - -- if (var->bits_per_pixel == 16) -+ if (var->bits_per_pixel >= 16) - fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; - else if (!fbi->cmap_static) - fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; -@@ -355,9 +380,10 @@ static int pxafb_set_par(struct fb_info - fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; - } - -- fbi->fb.fix.line_length = var->xres_virtual * -- var->bits_per_pixel / 8; -- if (var->bits_per_pixel == 16) -+ fbi->fb.fix.line_length = var->xres_virtual * -+ (var->nonstd ? var->nonstd : var->bits_per_pixel) / 8; -+ -+ if (var->bits_per_pixel >= 16) - fbi->palette_size = 0; - else - fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel; -@@ -374,7 +400,7 @@ static int pxafb_set_par(struct fb_info - */ - pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR); - -- if (fbi->fb.var.bits_per_pixel == 16) -+ if (fbi->fb.var.bits_per_pixel >= 16) - fb_dealloc_cmap(&fbi->fb.cmap); - else - fb_alloc_cmap(&fbi->fb.cmap, 1<fb.var.bits_per_pixel, 0); -@@ -584,6 +610,14 @@ static int pxafb_activate_var(struct fb_ - case 8: - case 16: - break; -+ case 18: -+ case 19: -+ case 24: -+ case 25: -+ if(var->nonstd) break; -+ printk(KERN_ERR "%s: must specify nonstd when bit depth==%d\n", -+ fbi->fb.fix.id, var->bits_per_pixel); -+ break; - default: - printk(KERN_ERR "%s: invalid bit depth %d\n", - fbi->fb.fix.id, var->bits_per_pixel); -@@ -679,7 +713,7 @@ static int pxafb_activate_var(struct fb_ - fbi->dmadesc_palette_cpu->fidr = 0; - fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; - -- if (var->bits_per_pixel == 16) { -+ if (var->bits_per_pixel >= 16) { - /* palette shouldn't be loaded in true-color mode */ - fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma; - fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */ -@@ -785,8 +819,19 @@ static void pxafb_setup_gpio(struct pxaf - return; - } - -- for (gpio = 58; ldd_bits; gpio++, ldd_bits--) -+ for (gpio = 58; min(ldd_bits,16); gpio++, ldd_bits--) - pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT); -+ -+ switch(fbi->fb.var.bits_per_pixel) -+ { -+ case 25: -+ case 24: -+ case 19: -+ case 18: -+ pxa_gpio_mode(GPIO86_LDD_16_MD); -+ pxa_gpio_mode(GPIO87_LDD_17_MD); -+ default: break; -+ } - pxa_gpio_mode(GPIO74_LCD_FCLK_MD); - pxa_gpio_mode(GPIO75_LCD_LCLK_MD); - pxa_gpio_mode(GPIO76_LCD_PCLK_MD); -@@ -1135,7 +1180,7 @@ static struct pxafb_info * __init pxafb_ - fbi->fb.fix.ywrapstep = 0; - fbi->fb.fix.accel = FB_ACCEL_NONE; - -- fbi->fb.var.nonstd = 0; -+ fbi->fb.var.nonstd = mode->nonstd; - fbi->fb.var.activate = FB_ACTIVATE_NOW; - fbi->fb.var.height = -1; - fbi->fb.var.width = -1; -@@ -1161,7 +1206,7 @@ static struct pxafb_info * __init pxafb_ - fbi->task_state = (u_char)-1; - - for (i = 0; i < inf->num_modes; i++) { -- smemlen = mode[i].xres * mode[i].yres * mode[i].bpp / 8; -+ smemlen = mode[i].xres * mode[i].yres * (mode[i].nonstd ? mode[i].nonstd : mode[i].bpp) / 8; - if (smemlen > fbi->fb.fix.smem_len) - fbi->fb.fix.smem_len = smemlen; - } -@@ -1189,12 +1234,19 @@ static int __init pxafb_parse_options(st - if (!strncmp(this_opt, "mode:", 5)) { - const char *name = this_opt+5; - unsigned int namelen = strlen(name); -- int res_specified = 0, bpp_specified = 0; -- unsigned int xres = 0, yres = 0, bpp = 0; -+ int res_specified = 0, bpp_specified = 0, nonstd_specified = 0; -+ unsigned int xres = 0, yres = 0, bpp = 0, nonstd = 0; - int yres_specified = 0; - int i; - for (i = namelen-1; i >= 0; i--) { - switch (name[i]) { -+ case '/': -+ if (!nonstd_specified) { -+ nonstd = simple_strtoul(&name[i+1], NULL, 0); -+ nonstd_specified = 1; -+ } else -+ goto done; -+ break; - case '-': - namelen = i; - if (!bpp_specified && !yres_specified) { -@@ -1227,12 +1279,29 @@ static int __init pxafb_parse_options(st - } - if (bpp_specified) - switch (bpp) { -+ case 18: -+ case 19: -+ case 24: -+ case 25: -+ if(nonstd_specified && (((bpp == 18 || bpp == 19) && nonstd == 24) || nonstd == 32)) -+ { -+ inf->modes[0].nonstd = nonstd; -+ dev_info(dev, "overriding nonstd pixel packing: %d\n",nonstd); -+ } else { -+ dev_err(dev, "Depth %d requires nonstd to be specified\n",bpp); -+ break; -+ } - case 1: - case 2: - case 4: - case 8: - case 16: - inf->modes[0].bpp = bpp; -+ if(nonstd_specified) { -+ dev_err(dev, "Depth %d requires nonstd to *not* be specified\n",bpp); -+ } else { -+ inf->modes[0].nonstd = 0; -+ } - dev_info(dev, "overriding bit depth: %d\n", bpp); - break; - default: -Index: linux-2.6.21.7/include/asm-arm/arch-pxa/pxa-regs.h -=================================================================== ---- linux-2.6.21.7.orig/include/asm-arm/arch-pxa/pxa-regs.h -+++ linux-2.6.21.7/include/asm-arm/arch-pxa/pxa-regs.h -@@ -1323,6 +1323,8 @@ - #define GPIO83_NSTXD 83 /* NSSP transmit */ - #define GPIO84_NSRXD 84 /* NSSP receive */ - #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ -+#define GPIO86_LDD_16 86 /* LCD data pin 16 */ -+#define GPIO87_LDD_17 87 /* LCD data pin 17 */ - #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ - #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ - #define GPIO105_nPCE_2 105 /* Card Enable for Card Space (PXA27x) */ -@@ -1468,6 +1470,8 @@ - #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) - #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) - #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) -+#define GPIO86_LDD_16_MD (86 | GPIO_ALT_FN_2_OUT) -+#define GPIO87_LDD_17_MD (87 | GPIO_ALT_FN_2_OUT) - #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) - #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) - #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) -@@ -1878,6 +1882,12 @@ - #define LCCR3_4BPP (2 << 24) - #define LCCR3_8BPP (3 << 24) - #define LCCR3_16BPP (4 << 24) -+#define LCCR3_18BPP (5 << 24) -+#define LCCR3_18BPP_PACKED (6 << 24) -+#define LCCR3_19BPP (7 << 24) -+#define LCCR3_19BPP_PACKED (1 << 29) -+#define LCCR3_24BPP ((1 << 29) | (1 << 24)) -+#define LCCR3_25BPP ((1 << 29) | (2 << 24)) - - #define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ - #define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ -Index: linux-2.6.21.7/include/asm-arm/arch-pxa/pxafb.h -=================================================================== ---- linux-2.6.21.7.orig/include/asm-arm/arch-pxa/pxafb.h -+++ linux-2.6.21.7/include/asm-arm/arch-pxa/pxafb.h -@@ -25,6 +25,7 @@ struct pxafb_mode_info { - u_short xres; - u_short yres; - -+ /* bpp is the path-to-screen bits per pixel, not the in-memory storage required */ - u_char bpp; - u_char hsync_len; - u_char left_margin; -@@ -36,7 +37,9 @@ struct pxafb_mode_info { - u_char sync; - - u_int cmap_greyscale:1, -- unused:31; -+ nonstd:8, /* nonstd represents the in-memory bits per pixel -+ ie 24 or 32 for 18/19bpp mode, or 32 for 24/25bpp mode */ -+ unused:23; - }; - - struct pxafb_mach_info { -Index: linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -=================================================================== ---- linux-2.6.21.7.orig/arch/arm/mach-pxa/gumstix.c -+++ linux-2.6.21.7/arch/arm/mach-pxa/gumstix.c -@@ -146,7 +146,8 @@ static struct pxafb_mode_info gumstix_fb - .pixclock = 110000, - .xres = 480, - .yres = 272, -- .bpp = 16, -+ .bpp = 18, -+ .nonstd = 24, - .hsync_len = 41, - .left_margin = 2, - .right_margin = 2, -@@ -174,7 +175,8 @@ static struct pxafb_mode_info gumstix_fb - .vsync_len = 10, // VLW from datasheet: 10 typ - .upper_margin = 2, // VBP - VLW from datasheet: 12 - 10 = 2 - .lower_margin = 4, // VFP from datasheet: 4 typ -- .bpp = 16, -+ .bpp = 18, -+ .nonstd = 24, - .sync = 0, // Hsync and Vsync both active low - }; - -Index: linux-2.6.21.7/drivers/video/cfbfillrect.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/video/cfbfillrect.c -+++ linux-2.6.21.7/drivers/video/cfbfillrect.c -@@ -62,7 +62,10 @@ pixel_to_pat( u32 bpp, u32 pixel) - return 0x0001001001001001ul*pixel; - case 16: - return 0x0001000100010001ul*pixel; -+ case 18: -+ case 19: - case 24: -+ case 25: - return 0x0000000001000001ul*pixel; - case 32: - return 0x0000000100000001ul*pixel; -@@ -87,7 +90,10 @@ pixel_to_pat( u32 bpp, u32 pixel) - return 0x00001001ul*pixel; - case 16: - return 0x00010001ul*pixel; -+ case 18: -+ case 19: - case 24: -+ case 25: - return 0x00000001ul*pixel; - case 32: - return 0x00000001ul*pixel; -@@ -346,7 +352,7 @@ void cfb_fillrect(struct fb_info *p, con - unsigned long pat, fg; - unsigned long width = rect->width, height = rect->height; - int bits = BITS_PER_LONG, bytes = bits >> 3; -- u32 bpp = p->var.bits_per_pixel; -+ u32 bpp = (p->var.nonstd ? p->var.nonstd : p->var.bits_per_pixel); - unsigned long __iomem *dst; - int dst_idx, left; - -Index: linux-2.6.21.7/drivers/video/cfbimgblt.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/video/cfbimgblt.c -+++ linux-2.6.21.7/drivers/video/cfbimgblt.c -@@ -83,7 +83,7 @@ static inline void color_imageblit(const - /* Draw the penguin */ - u32 __iomem *dst, *dst2; - u32 color = 0, val, shift; -- int i, n, bpp = p->var.bits_per_pixel; -+ int i, n, bpp = (p->var.nonstd ? p->var.nonstd : p->var.bits_per_pixel); - u32 null_bits = 32 - bpp; - u32 *palette = (u32 *) p->pseudo_palette; - const u8 *src = image->data; -@@ -140,7 +140,7 @@ static inline void slow_imageblit(const - u32 start_index, - u32 pitch_index) - { -- u32 shift, color = 0, bpp = p->var.bits_per_pixel; -+ u32 shift, color = 0, bpp = (p->var.nonstd ? p->var.nonstd : p->var.bits_per_pixel); - u32 __iomem *dst, *dst2; - u32 val, pitch = p->fix.line_length; - u32 null_bits = 32 - bpp; -@@ -213,7 +213,7 @@ static inline void fast_imageblit(const - u8 __iomem *dst1, u32 fgcolor, - u32 bgcolor) - { -- u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel; -+ u32 fgx = fgcolor, bgx = bgcolor, bpp = (p->var.nonstd ? p->var.nonstd : p->var.bits_per_pixel); - u32 ppw = 32/bpp, spitch = (image->width + 7)/8; - u32 bit_mask, end_mask, eorx, shift; - const char *s = image->data, *src; -@@ -262,7 +262,7 @@ static inline void fast_imageblit(const - void cfb_imageblit(struct fb_info *p, const struct fb_image *image) - { - u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0; -- u32 bpl = sizeof(u32), bpp = p->var.bits_per_pixel; -+ u32 bpl = sizeof(u32), bpp = (p->var.nonstd ? p->var.nonstd : p->var.bits_per_pixel); - u32 width = image->width; - u32 dx = image->dx, dy = image->dy; - u8 __iomem *dst1; -Index: linux-2.6.21.7/drivers/video/cfbcopyarea.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/video/cfbcopyarea.c -+++ linux-2.6.21.7/drivers/video/cfbcopyarea.c -@@ -365,8 +365,8 @@ void cfb_copyarea(struct fb_info *p, con - dst = src = (unsigned long __iomem *)((unsigned long)p->screen_base & ~(bytes-1)); - dst_idx = src_idx = 8*((unsigned long)p->screen_base & (bytes-1)); - // add offset of source and target area -- dst_idx += dy*bits_per_line + dx*p->var.bits_per_pixel; -- src_idx += sy*bits_per_line + sx*p->var.bits_per_pixel; -+ dst_idx += dy*bits_per_line + dx*(p->var.nonstd ? p->var.nonstd : p->var.bits_per_pixel); -+ src_idx += sy*bits_per_line + sx*(p->var.nonstd ? p->var.nonstd : p->var.bits_per_pixel); - - if (p->fbops->fb_sync) - p->fbops->fb_sync(p); -@@ -380,7 +380,7 @@ void cfb_copyarea(struct fb_info *p, con - src += src_idx >> (ffs(bits) - 1); - src_idx &= (bytes - 1); - bitcpy_rev(dst, dst_idx, src, src_idx, bits, -- width*p->var.bits_per_pixel); -+ width*(p->var.nonstd ? p->var.nonstd : p->var.bits_per_pixel)); - } - } else { - while (height--) { -@@ -389,7 +389,7 @@ void cfb_copyarea(struct fb_info *p, con - src += src_idx >> (ffs(bits) - 1); - src_idx &= (bytes - 1); - bitcpy(dst, dst_idx, src, src_idx, bits, -- width*p->var.bits_per_pixel); -+ width*(p->var.nonstd ? p->var.nonstd : p->var.bits_per_pixel)); - dst_idx += bits_per_line; - src_idx += bits_per_line; - } -Index: linux-2.6.21.7/drivers/video/console/fbcon.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/video/console/fbcon.c -+++ linux-2.6.21.7/drivers/video/console/fbcon.c -@@ -983,9 +983,10 @@ static const char *fbcon_startup(void) - - DPRINTK("mode: %s\n", info->fix.id); - DPRINTK("visual: %d\n", info->fix.visual); -- DPRINTK("res: %dx%d-%d\n", info->var.xres, -+ DPRINTK("res: %dx%d-%d(%d)\n", info->var.xres, - info->var.yres, -- info->var.bits_per_pixel); -+ info->var.bits_per_pixel, -+ info->var.nonstd ? info->var.nonstd : info->var.bits_per_pixel); - - #ifdef CONFIG_ATARI - if (MACH_IS_ATARI) { -Index: linux-2.6.21.7/Documentation/fb/pxafb.txt -=================================================================== ---- linux-2.6.21.7.orig/Documentation/fb/pxafb.txt -+++ linux-2.6.21.7/Documentation/fb/pxafb.txt -@@ -9,11 +9,13 @@ For example: - or on the kernel command line - video=pxafb:mode:640x480-8,passive - --mode:XRESxYRES[-BPP] -+mode:XRESxYRES[-BPP[/PACKING]] - XRES == LCCR1_PPL + 1 - YRES == LLCR2_LPP + 1 - The resolution of the display in pixels - BPP == The bit depth. Valid values are 1, 2, 4, 8 and 16. -+ PACKING == The in-memory bits per pixel. Valid values are 24, 32 when -+ BPP == 18,19,24,25 - - pixclock:PIXCLOCK - Pixel clock in picoseconds diff --git a/target/linux/pxa/patches-2.6.21/044-smc911x-fixup.patch b/target/linux/pxa/patches-2.6.21/044-smc911x-fixup.patch deleted file mode 100644 index 0985258c31..0000000000 --- a/target/linux/pxa/patches-2.6.21/044-smc911x-fixup.patch +++ /dev/null @@ -1,383 +0,0 @@ -Index: linux-2.6.21.7/drivers/net/smc911x.c -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/smc911x.c -+++ linux-2.6.21.7/drivers/net/smc911x.c -@@ -76,6 +76,7 @@ static const char version[] = - #include - #include - -+#include - #include - #include - -@@ -303,14 +304,14 @@ static void smc911x_reset(struct net_dev - SMC_SET_AFC_CFG(lp->afc_cfg); - - -- /* Set to LED outputs */ -- SMC_SET_GPIO_CFG(0x70070000); -+ /* Set to LED outputs and configure EEPROM pins as GP outputs */ -+ SMC_SET_GPIO_CFG(GPIO_CFG_LED1_EN_ | GPIO_CFG_LED2_EN_ | 1 << 20); - - /* -- * Deassert IRQ for 1*10us for edge type interrupts -+ * Deassert IRQ for 22*10us for edge type interrupts - * and drive IRQ pin push-pull - */ -- SMC_SET_IRQ_CFG( (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_ ); -+ SMC_SET_IRQ_CFG( (22 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_ ); - - /* clear anything saved */ - if (lp->pending_tx_skb != NULL) { -@@ -413,7 +414,7 @@ static inline void smc911x_drop_pkt(stru - if (fifo_count <= 4) { - /* Manually dump the packet data */ - while (fifo_count--) -- SMC_GET_RX_FIFO(); -+ (void)SMC_GET_RX_FIFO(); - } else { - /* Fast forward through the bad packet */ - SMC_SET_RX_DP_CTRL(RX_DP_CTRL_FFWD_BUSY_); -@@ -900,6 +901,7 @@ static void smc911x_phy_powerdown(struct - unsigned long ioaddr = dev->base_addr; - unsigned int bmcr; - -+ DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); - /* Enter Link Disable state */ - SMC_GET_PHY_BMCR(phy, bmcr); - bmcr |= BMCR_PDOWN; -@@ -925,6 +927,7 @@ static void smc911x_phy_check_media(stru - - if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { - /* duplex state has changed */ -+ DBG(SMC_DEBUG_MISC, "%s: duplex state has changed\n", dev->name); - SMC_GET_PHY_BMCR(phyaddr, bmcr); - SMC_GET_MAC_CR(cr); - if (lp->mii.full_duplex) { -@@ -960,6 +963,7 @@ static void smc911x_phy_configure(struct - int my_phy_caps; /* My PHY capabilities */ - int my_ad_caps; /* My Advertised capabilities */ - int status; -+ int bmcr; - unsigned long flags; - - DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __FUNCTION__); -@@ -1033,9 +1037,12 @@ static void smc911x_phy_configure(struct - - DBG(SMC_DEBUG_MISC, "%s: phy caps=0x%04x\n", dev->name, my_phy_caps); - DBG(SMC_DEBUG_MISC, "%s: phy advertised caps=0x%04x\n", dev->name, my_ad_caps); -+ DBG(SMC_DEBUG_MISC, "%s: phy advertised readback caps=0x%04x\n", dev->name, status); - - /* Restart auto-negotiation process in order to advertise my caps */ -- SMC_SET_PHY_BMCR(phyaddr, BMCR_ANENABLE | BMCR_ANRESTART); -+ SMC_GET_PHY_BMCR(phyaddr, bmcr); -+ bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; -+ SMC_SET_PHY_BMCR(phyaddr, bmcr); - - smc911x_phy_check_media(dev, 1); - -@@ -1888,6 +1895,39 @@ static int __init smc911x_findirq(unsign - return probe_irq_off(cookie); - } - -+static inline unsigned int is_gumstix_oui(u8 *addr) -+{ -+ return (addr[0] == 0x00 && addr[1] == 0x15 && addr[2] == 0xC9); -+} -+ -+/** -+ * gen_serial_ether_addr - Generate software assigned Ethernet address -+ * based on the system_serial number -+ * @addr: Pointer to a six-byte array containing the Ethernet address -+ * -+ * Generate an Ethernet address (MAC) that is not multicast -+ * and has the local assigned bit set, keyed on the system_serial -+ */ -+static inline void gen_serial_ether_addr(u8 *addr) -+{ -+ static u8 ether_serial_digit = 0; -+ addr [0] = system_serial_high >> 8; -+ addr [1] = system_serial_high; -+ addr [2] = system_serial_low >> 24; -+ addr [3] = system_serial_low >> 16; -+ addr [4] = system_serial_low >> 8; -+ addr [5] = (system_serial_low & 0xc0) | /* top bits are from system serial */ -+ (1 << 4) | /* 2 bits identify interface type 1=ether, 2=usb, 3&4 undef */ -+ ((ether_serial_digit++) & 0x0f); /* 15 possible interfaces of each type */ -+ -+ if(!is_gumstix_oui(addr)) -+ { -+ addr [0] &= 0xfe; /* clear multicast bit */ -+ addr [0] |= 0x02; /* set local assignment bit (IEEE802) */ -+ } -+} -+ -+ - /* - * Function: smc911x_probe(unsigned long ioaddr) - * -@@ -2116,15 +2156,13 @@ static int __init smc911x_probe(struct n - #endif - printk("\n"); - if (!is_valid_ether_addr(dev->dev_addr)) { -- printk("%s: Invalid ethernet MAC address. Please " -- "set using ifconfig\n", dev->name); -- } else { -- /* Print the Ethernet address */ -- printk("%s: Ethernet addr: ", dev->name); -- for (i = 0; i < 5; i++) -- printk("%2.2x:", dev->dev_addr[i]); -- printk("%2.2x\n", dev->dev_addr[5]); -+ gen_serial_ether_addr(dev->dev_addr); - } -+ /* Print the Ethernet address */ -+ printk("%s: Ethernet addr: ", dev->name); -+ for (i = 0; i < 5; i++) -+ printk("%2.2x:", dev->dev_addr[i]); -+ printk("%2.2x\n", dev->dev_addr[5]); - - if (lp->phy_type == 0) { - PRINTK("%s: No PHY found\n", dev->name); -@@ -2300,8 +2338,15 @@ static struct platform_driver smc911x_dr - }, - }; - -+#ifdef CONFIG_ARCH_GUMSTIX -+extern void gumstix_smc911x_load(void); -+#endif -+ - static int __init smc911x_init(void) - { -+#ifdef CONFIG_ARCH_GUMSTIX -+ gumstix_smc911x_load(); -+#endif - return platform_driver_register(&smc911x_driver); - } - -Index: linux-2.6.21.7/drivers/net/gumstix-smc911x.c -=================================================================== ---- /dev/null -+++ linux-2.6.21.7/drivers/net/gumstix-smc911x.c -@@ -0,0 +1,148 @@ -+/* -+ * Gumstix SMC911x chip intialization driver -+ * -+ * Author: Craig Hughes -+ * Created: December 9, 2004 -+ * Copyright: (C) 2004 Craig Hughes -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#define SMC_DEBUG 9 -+#include -+#include "smc911x.h" -+ -+static struct resource gumstix_smc911x0_resources[] = { -+ [0] = { -+ .name = "smc911x-regs", -+ .start = PXA_CS1_PHYS, -+ .end = PXA_CS1_PHYS + 0x000fffff, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = GUMSTIX_ETH0_IRQ, -+ .end = GUMSTIX_ETH0_IRQ, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct resource gumstix_smc911x1_resources[] = { -+ [0] = { -+ .name = "smc911x-regs", -+ .start = PXA_CS2_PHYS, -+ .end = PXA_CS2_PHYS + 0x000fffff, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = GUMSTIX_ETH1_IRQ, -+ .end = GUMSTIX_ETH1_IRQ, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device gumstix_smc911x0_device = { -+ .name = "smc911x", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(gumstix_smc911x0_resources), -+ .resource = gumstix_smc911x0_resources, -+}; -+ -+static struct platform_device gumstix_smc911x1_device = { -+ .name = "smc911x", -+ .id = 1, -+ .num_resources = ARRAY_SIZE(gumstix_smc911x1_resources), -+ .resource = gumstix_smc911x1_resources, -+}; -+ -+static struct platform_device *smc911x_devices[] = { -+ &gumstix_smc911x0_device, -+ &gumstix_smc911x1_device, -+}; -+ -+/* First we're going to test if there's a 2nd SMC911x, and if not, then we'll free up those resources and the GPIO lines -+ * that it would otherwise use. We have no choice but to probe by doing: -+ * Set nCS2 to CS2 mode -+ * Set the reset line to GPIO out mode, and pull it high, then drop it low (to trigger reset) -+ * Read from the memory space to check for the sentinel sequence identifying a likely SMC911x device -+ */ -+int __init gumstix_smc911x_init(void) -+{ -+ unsigned int val, num_devices=ARRAY_SIZE(smc911x_devices); -+ void *ioaddr; -+ -+ /* Set up nPWE */ -+ pxa_gpio_mode(GPIO49_nPWE_MD); -+ -+ pxa_gpio_mode(GPIO78_nCS_2_MD); -+ // If either if statement fails, then we'll drop out and turn_off_eth1, -+ // if both succeed, then we'll skip that and just proceed with 2 cards -+ if(request_mem_region(gumstix_smc911x1_resources[1].start, SMC911X_IO_EXTENT, "smc911x probe")) -+ { -+ ioaddr = ioremap(gumstix_smc911x1_resources[1].start, SMC911X_IO_EXTENT); -+ val = SMC_GET_PN(); -+ iounmap(ioaddr); -+ release_mem_region(gumstix_smc911x1_resources[1].start, SMC911X_IO_EXTENT); -+ if (CHIP_9115 == val || -+ CHIP_9116 == val || -+ CHIP_9117 == val || -+ CHIP_9118 == val ) { -+ goto proceed; -+ } -+ } -+ -+turn_off_eth1: -+ // This is apparently not an SMC911x -+ // So, let's decrement the number of devices to request, and reset the GPIO lines to GPIO IN mode -+ num_devices--; -+ smc911x_devices[1] = NULL; -+ pxa_gpio_mode(78 | GPIO_IN); -+ -+proceed: -+ pxa_gpio_mode(GPIO15_nCS_1_MD); -+ -+ if(smc911x_devices[1]) pxa_gpio_mode(GPIO_GUMSTIX_ETH1_RST_MD); -+ pxa_gpio_mode(GPIO_GUMSTIX_ETH0_RST_MD); -+ -+ if(smc911x_devices[1]) GPCR(GPIO_GUMSTIX_ETH1_RST) = GPIO_bit(GPIO_GUMSTIX_ETH1_RST); -+ GPCR(GPIO_GUMSTIX_ETH0_RST) = GPIO_bit(GPIO_GUMSTIX_ETH0_RST); -+ msleep(500); // Hold RESET for at least 200µ -+ -+ if(smc911x_devices[1]) GPSR(GPIO_GUMSTIX_ETH1_RST) = GPIO_bit(GPIO_GUMSTIX_ETH1_RST); -+ GPSR(GPIO_GUMSTIX_ETH0_RST) = GPIO_bit(GPIO_GUMSTIX_ETH0_RST); -+ msleep(50); -+ -+ return platform_add_devices(smc911x_devices, num_devices); -+} -+ -+void __exit gumstix_smc911x_exit(void) -+{ -+ if(smc911x_devices[1] != NULL) platform_device_unregister(&gumstix_smc911x1_device); -+ platform_device_unregister(&gumstix_smc911x0_device); -+} -+ -+void gumstix_smc911x_load(void) {} -+EXPORT_SYMBOL(gumstix_smc911x_load); -+ -+module_init(gumstix_smc911x_init); -+module_exit(gumstix_smc911x_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Craig Hughes "); -+MODULE_DESCRIPTION("Gumstix board SMC911x chip initialization driver"); -+MODULE_VERSION("1:0.1"); -Index: linux-2.6.21.7/drivers/net/Kconfig -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/Kconfig -+++ linux-2.6.21.7/drivers/net/Kconfig -@@ -1020,6 +1020,13 @@ config SMC911X - called smc911x. If you want to compile it as a module, say M - here and read - -+config SMC911X_GUMSTIX -+ tristate -+ default m if SMC911X=m -+ default y if SMC911X=y -+ depends on SMC911X && ARCH_GUMSTIX -+ -+ - config NET_VENDOR_RACAL - bool "Racal-Interlan (Micom) NI cards" - depends on NET_ETHERNET && ISA -Index: linux-2.6.21.7/drivers/net/Makefile -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/Makefile -+++ linux-2.6.21.7/drivers/net/Makefile -@@ -202,6 +202,7 @@ obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o - obj-$(CONFIG_MACB) += macb.o - - obj-$(CONFIG_SMC91X_GUMSTIX) += gumstix-smc91x.o -+obj-$(CONFIG_SMC911X_GUMSTIX) += gumstix-smc911x.o - obj-$(CONFIG_ARM) += arm/ - obj-$(CONFIG_DEV_APPLETALK) += appletalk/ - obj-$(CONFIG_TR) += tokenring/ -Index: linux-2.6.21.7/include/asm-arm/arch-pxa/gumstix.h -=================================================================== ---- linux-2.6.21.7.orig/include/asm-arm/arch-pxa/gumstix.h -+++ linux-2.6.21.7/include/asm-arm/arch-pxa/gumstix.h -@@ -52,7 +52,7 @@ - #define GPIO_GUMSTIX_ETH0_RST 80 - #define GPIO_GUMSTIX_ETH0 36 - #else --#define GPIO_GUMSTIX_ETH0_RST 32 -+#define GPIO_GUMSTIX_ETH0_RST 107 - #define GPIO_GUMSTIX_ETH0 99 - #endif - #define GPIO_GUMSTIX_ETH1_RST 52 -Index: linux-2.6.21.7/drivers/net/smc911x.h -=================================================================== ---- linux-2.6.21.7.orig/drivers/net/smc911x.h -+++ linux-2.6.21.7/drivers/net/smc911x.h -@@ -33,7 +33,9 @@ - * Use the DMA feature on PXA chips - */ - #ifdef CONFIG_ARCH_PXA -+#if !defined( CONFIG_SMC911X_GUMSTIX ) && !defined( CONFIG_SMC911X_GUMSTIX_MODULE ) - #define SMC_USE_PXA_DMA 1 -+#endif - #define SMC_USE_16BIT 0 - #define SMC_USE_32BIT 1 - #endif -@@ -46,13 +48,13 @@ - #if SMC_USE_16BIT - #define SMC_inb(a, r) readb((a) + (r)) - #define SMC_inw(a, r) readw((a) + (r)) --#define SMC_inl(a, r) ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16)) -+#define SMC_inl(a, r) ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw((a)+2, r)<<16)) - #define SMC_outb(v, a, r) writeb(v, (a) + (r)) - #define SMC_outw(v, a, r) writew(v, (a) + (r)) - #define SMC_outl(v, a, r) \ - do{ \ -- writel(v & 0xFFFF, (a) + (r)); \ -- writel(v >> 16, (a) + (r) + 2); \ -+ writel((v) & 0xFFFF, (a) + (r)); \ -+ writel((v) >> 16, (a) + (r) + 2); \ - } while (0) - #define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2) - #define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2) diff --git a/target/linux/pxa/patches/000-cpufreq.patch b/target/linux/pxa/patches/000-cpufreq.patch deleted file mode 100644 index 3cb6676b41..0000000000 --- a/target/linux/pxa/patches/000-cpufreq.patch +++ /dev/null @@ -1,533 +0,0 @@ -diff -Nurbw linux-2.6.17/arch/arm/Kconfig linux-2.6.17-patched/arch/arm/Kconfig ---- linux-2.6.17/arch/arm/Kconfig 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/arch/arm/Kconfig 2006-09-21 14:57:02.000000000 -0700 -@@ -656,7 +656,7 @@ - - endmenu - --if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1) -+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1 || ARCH_PXA) - - menu "CPU Frequency scaling" - -@@ -685,6 +685,13 @@ - - endmenu - -+config CPU_FREQ_PXA -+ bool -+ depends on CPU_FREQ && ARCH_PXA -+ default y -+ select CPU_FREQ_DEFAULT_GOV_USERSPACE -+ select CPU_FREQ_TABLE -+ - endif - - menu "Floating point emulation" -diff -Nurbw linux-2.6.17/arch/arm/mach-pxa/cpu-pxa.c linux-2.6.17-patched/arch/arm/mach-pxa/cpu-pxa.c ---- linux-2.6.17/arch/arm/mach-pxa/cpu-pxa.c 1969-12-31 16:00:00.000000000 -0800 -+++ linux-2.6.17-patched/arch/arm/mach-pxa/cpu-pxa.c 2006-09-21 14:57:02.000000000 -0700 -@@ -0,0 +1,324 @@ -+/* -+ * linux/arch/arm/mach-pxa/cpu-pxa.c -+ * -+ * Copyright (C) 2002,2003 Intrinsyc Software -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * History: -+ * 31-Jul-2002 : Initial version [FB] -+ * 29-Jan-2003 : added PXA255 support [FB] -+ * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) -+ * -+ * Note: -+ * This driver may change the memory bus clock rate, but will not do any -+ * platform specific access timing changes... for example if you have flash -+ * memory connected to CS0, you will need to register a platform specific -+ * notifier which will adjust the memory access strobes to maintain a -+ * minimum strobe width. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#undef DEBUG -+ -+#ifdef DEBUG -+ static unsigned int freq_debug = DEBUG; -+ module_param(freq_debug, int, 0); -+ MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); -+#else -+ #define freq_debug 0 -+#endif -+ -+typedef struct -+{ -+ unsigned int khz; -+ unsigned int membus; -+ unsigned int cccr; -+ unsigned int div2; -+} pxa_freqs_t; -+ -+/* Define the refresh period in mSec for the SDRAM and the number of rows */ -+#define SDRAM_TREF 64 /* standard 64ms SDRAM */ -+#define SDRAM_ROWS 2048 /* 64MB=8192 32MB=4096 */ -+#define MDREFR_DRI(x) ((x*SDRAM_TREF)/(SDRAM_ROWS*32)) -+ -+#define CCLKCFG_TURBO 0x1 -+#define CCLKCFG_FCS 0x2 -+#define PXA25x_MIN_FREQ 99533 -+#define PXA25x_MAX_FREQ 530842 -+#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) -+#define MDREFR_DRI_MASK 0xFFF -+ -+ -+/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ -+static pxa_freqs_t pxa255_run_freqs[] = -+{ -+ /* CPU MEMBUS CCCR DIV2*/ -+ { 99533, 99533, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */ -+ {132710, 132710, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */ -+ {199066, 99533, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */ -+ {265421, 132710, 0x143, 0}, /* run=265, turbo=265, PXbus=133, SDRAM=133 */ -+ {331776, 165888, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */ -+ {398131, 99533, 0x161, 0}, /* run=398, turbo=398, PXbus=99, SDRAM=99 */ -+ {398131, 132710, 0x1c3, 0}, /* run=265, turbo=398, PXbus=133, SDRAM=133 */ -+ {530842, 132710, 0x163, 0}, /* run=531, turbo=531, PXbus=133, SDRAM=133 */ -+ {0,} -+}; -+#define NUM_RUN_FREQS (sizeof(pxa255_run_freqs)/sizeof(pxa_freqs_t)) -+ -+static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1]; -+ -+/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ -+static pxa_freqs_t pxa255_turbo_freqs[] = -+{ -+ /* CPU MEMBUS CCCR DIV2*/ -+ { 99533, 99533, 0x121, 1}, /* run=99, turbo= 99, PXbus=99, SDRAM=50 */ -+ {149299, 99533, 0x1a1, 0}, /* run=99, turbo=149, PXbus=99, SDRAM=99 */ -+ {199066, 99533, 0x221, 0}, /* run=99, turbo=199, PXbus=99, SDRAM=99 */ -+ {298598, 99533, 0x321, 0}, /* run=99, turbo=299, PXbus=99, SDRAM=99 */ -+ {398131, 99533, 0x241, 1}, /* run=199, turbo=398, PXbus=99, SDRAM=50 */ -+ {0,} -+}; -+#define NUM_TURBO_FREQS (sizeof(pxa255_turbo_freqs)/sizeof(pxa_freqs_t)) -+ -+static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1]; -+ -+extern unsigned get_clk_frequency_khz(int info); -+ -+/* find a valid frequency point */ -+static int pxa_verify_policy(struct cpufreq_policy *policy) -+{ -+ int ret; -+ struct cpufreq_frequency_table *pxa_freqs_table; -+ -+ if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) { -+ pxa_freqs_table = pxa255_run_freq_table; -+ } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { -+ pxa_freqs_table = pxa255_turbo_freq_table; -+ } else { -+ printk("CPU PXA: Unknown policy found. " -+ "Using CPUFREQ_POLICY_PERFORMANCE\n"); -+ pxa_freqs_table = pxa255_run_freq_table; -+ } -+ ret=cpufreq_frequency_table_verify(policy, pxa_freqs_table); -+ -+ if(freq_debug) { -+ printk("Verified CPU policy: %dKhz min to %dKhz max\n", -+ policy->min, policy->max); -+ } -+ -+ return ret; -+} -+ -+static int pxa_set_target(struct cpufreq_policy *policy, -+ unsigned int target_freq, -+ unsigned int relation) -+{ -+ int idx; -+ cpumask_t cpus_allowed; -+ int cpu = policy->cpu; -+ struct cpufreq_freqs freqs; -+ pxa_freqs_t *pxa_freq_settings; -+ struct cpufreq_frequency_table *pxa_freqs_table; -+ unsigned long flags; -+ unsigned int unused; -+ unsigned int preset_mdrefr, postset_mdrefr; -+ void *ramstart; -+ -+ /* -+ * Save this threads cpus_allowed mask. -+ */ -+ cpus_allowed = current->cpus_allowed; -+ -+ /* -+ * Bind to the specified CPU. When this call returns, -+ * we should be running on the right CPU. -+ */ -+ set_cpus_allowed(current, cpumask_of_cpu(cpu)); -+ BUG_ON(cpu != smp_processor_id()); -+ -+ /* Get the current policy */ -+ if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) { -+ pxa_freq_settings = pxa255_run_freqs; -+ pxa_freqs_table = pxa255_run_freq_table; -+ }else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { -+ pxa_freq_settings = pxa255_turbo_freqs; -+ pxa_freqs_table = pxa255_turbo_freq_table; -+ }else { -+ printk("CPU PXA: Unknown policy found. " -+ "Using CPUFREQ_POLICY_PERFORMANCE\n"); -+ pxa_freq_settings = pxa255_run_freqs; -+ pxa_freqs_table = pxa255_run_freq_table; -+ } -+ -+ /* Lookup the next frequency */ -+ if (cpufreq_frequency_table_target(policy, pxa_freqs_table, -+ target_freq, relation, &idx)) { -+ return -EINVAL; -+ } -+ -+ freqs.old = policy->cur; -+ freqs.new = pxa_freq_settings[idx].khz; -+ freqs.cpu = policy->cpu; -+ if(freq_debug) { -+ printk(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n", -+ freqs.new/1000, (pxa_freq_settings[idx].div2) ? -+ (pxa_freq_settings[idx].membus/2000) : -+ (pxa_freq_settings[idx].membus/1000)); -+ } -+ -+ ramstart = phys_to_virt(0xa0000000); -+ -+ /* -+ * Tell everyone what we're about to do... -+ * you should add a notify client with any platform specific -+ * Vcc changing capability -+ */ -+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); -+ -+ /* Calculate the next MDREFR. If we're slowing down the SDRAM clock -+ * we need to preset the smaller DRI before the change. If we're speeding -+ * up we need to set the larger DRI value after the change. -+ */ -+ preset_mdrefr = postset_mdrefr = MDREFR; -+ if((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) { -+ preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) | -+ MDREFR_DRI(pxa_freq_settings[idx].membus); -+ } -+ postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) | -+ MDREFR_DRI(pxa_freq_settings[idx].membus); -+ -+ /* If we're dividing the memory clock by two for the SDRAM clock, this -+ * must be set prior to the change. Clearing the divide must be done -+ * after the change. -+ */ -+ if(pxa_freq_settings[idx].div2) { -+ preset_mdrefr |= MDREFR_DB2_MASK; -+ postset_mdrefr |= MDREFR_DB2_MASK; -+ } else { -+ postset_mdrefr &= ~MDREFR_DB2_MASK; -+ } -+ -+ local_irq_save(flags); -+ -+ /* Set new the CCCR */ -+ CCCR = pxa_freq_settings[idx].cccr; -+ -+ __asm__ __volatile__(" \ -+ ldr r4, [%1] ; /* load MDREFR */ \ -+ b 2f ; \ -+ .align 5 ; \ -+1: \ -+ str %4, [%1] ; /* preset the MDREFR */ \ -+ mcr p14, 0, %2, c6, c0, 0 ; /* set CCLKCFG[FCS] */ \ -+ str %5, [%1] ; /* postset the MDREFR */ \ -+ \ -+ b 3f ; \ -+2: b 1b ; \ -+3: nop ; \ -+ " -+ : "=&r" (unused) -+ : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart), \ -+ "r" (preset_mdrefr), "r" (postset_mdrefr) -+ : "r4", "r5"); -+ local_irq_restore(flags); -+ -+ /* -+ * Restore the CPUs allowed mask. -+ */ -+ set_cpus_allowed(current, cpus_allowed); -+ -+ /* -+ * Tell everyone what we've just done... -+ * you should add a notify client with any platform specific -+ * SDRAM refresh timer adjustments -+ */ -+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); -+ -+ return 0; -+} -+ -+static int pxa_cpufreq_init(struct cpufreq_policy *policy) -+{ -+ cpumask_t cpus_allowed; -+ unsigned int cpu = policy->cpu; -+ int i; -+ -+ cpus_allowed = current->cpus_allowed; -+ -+ set_cpus_allowed(current, cpumask_of_cpu(cpu)); -+ BUG_ON(cpu != smp_processor_id()); -+ -+ /* set default policy and cpuinfo */ -+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR; -+ policy->policy = CPUFREQ_POLICY_PERFORMANCE; -+ policy->cpuinfo.max_freq = PXA25x_MAX_FREQ; -+ policy->cpuinfo.min_freq = PXA25x_MIN_FREQ; -+ policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ -+ policy->cur = get_clk_frequency_khz(0); /* current freq */ -+ policy->min = policy->max = policy->cur; -+ -+ /* Generate the run cpufreq_frequency_table struct */ -+ for(i=0;i - #include --#include --#include -+#include -+#include -+#include -+#include -+#include - #include --#include - - #include - #include - #include --#include -+#include -+#include - #include - #include - #include - -+/**/ -+#include -+/**/ -+//kirti -+#include -+//kirti~ - - /* - * Debug macros - */ --#undef DEBUG -+#define DEBUG -+ -+extern void pxa_cpu_suspend(void); -+extern void pxa_cpu_resume(void); -+ -+int pm_pwronoff; -+/*Angelia Additions */ -+int pm_pedr=0; -+EXPORT_SYMBOL(pm_pwronoff); -+EXPORT_SYMBOL(pm_pedr); -+ - - #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x - #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] - --#define RESTORE_GPLEVEL(n) do { \ -- GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ -- GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ --} while (0) -- - /* - * List of global PXA peripheral registers to preserve. - * More ones like CP and general purpose register values are preserved -@@ -46,97 +61,405 @@ - */ - enum { SLEEP_SAVE_START = 0, - -- SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3, -- SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3, -- SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3, -- SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3, -- SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, -- -- SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, -- SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, -- SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, -- SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U, -+ SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER, -+ SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3, - -- SLEEP_SAVE_PSTR, -+ SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, -+ SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, -+ SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, -+ SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR2_L, -+ SLEEP_SAVE_GAFR0_U, SLEEP_SAVE_GAFR1_U, SLEEP_SAVE_GAFR2_U, -+ -+ SLEEP_SAVE_FFIER, SLEEP_SAVE_FFLCR, SLEEP_SAVE_FFMCR, -+ SLEEP_SAVE_FFSPR, SLEEP_SAVE_FFISR, -+ SLEEP_SAVE_FFDLL, SLEEP_SAVE_FFDLH,SLEEP_SAVE_FFFCR, -+ -+ SLEEP_SAVE_STIER, SLEEP_SAVE_STLCR, SLEEP_SAVE_STMCR, -+ SLEEP_SAVE_STSPR, SLEEP_SAVE_STISR, -+ SLEEP_SAVE_STDLL, SLEEP_SAVE_STDLH, -+ -+ SLEEP_SAVE_BTIER, SLEEP_SAVE_BTLCR, SLEEP_SAVE_BTMCR, -+ SLEEP_SAVE_BTSPR, SLEEP_SAVE_BTISR, -+ SLEEP_SAVE_BTDLL, SLEEP_SAVE_BTDLH, - - SLEEP_SAVE_ICMR, - SLEEP_SAVE_CKEN, - --#ifdef CONFIG_PXA27x -- SLEEP_SAVE_MDREFR, -- SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, -- SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, --#endif -+ SLEEP_SAVE_LCCR0, SLEEP_SAVE_LCCR1, SLEEP_SAVE_LCCR2,SLEEP_SAVE_LCCR3, -+ SLEEP_SAVE_TMEDCR, SLEEP_SAVE_FDADR0, SLEEP_SAVE_FSADR0,SLEEP_SAVE_FIDR0,SLEEP_SAVE_FDADR1, -+ SLEEP_SAVE_LDCMD0, -+ -+ SLEEP_SAVE_NSSCR0,SLEEP_SAVE_NSSCR1,SLEEP_SAVE_NSSSR,SLEEP_SAVE_NSSITR,SLEEP_SAVE_NSSDR, -+ SLEEP_SAVE_NSSTO,SLEEP_SAVE_NSSPSP, - -- SLEEP_SAVE_CKSUM, - -+ SLEEP_SAVE_CKSUM, - SLEEP_SAVE_SIZE - }; - -+/**/ -+#define UART_DTR 1 -+#define UART_RTS 2 -+ -+/**/ - --int pxa_pm_enter(suspend_state_t state) -+int pm_do_suspend(void) - { - unsigned long sleep_save[SLEEP_SAVE_SIZE]; - unsigned long checksum = 0; -- struct timespec delta, rtc; - int i; -+ int valbefore,valafter,valafter1; -+ int gpsr0,gpsr1,gpsr2; - extern void pxa_cpu_pm_enter(suspend_state_t state); - --#ifdef CONFIG_IWMMXT -- /* force any iWMMXt context to ram **/ -- iwmmxt_task_disable(NULL); --#endif -+ // YoKu 16Feb06 GPIO Changed -----> -+ -+ PGSR2 |= GPIO_bit(78); -+/* if(GPLR2 & GPIO_bit(78)) // LCD Reset Pin -+ PGSR2 |= GPIO_bit(78); -+ else -+ PGSR2 &= ~GPIO_bit(78); */ -+ GPDR0 &= ~GPIO_bit(0); -+ GPDR0 &= ~GPIO_bit(1); -+ GPDR0 &= ~GPIO_bit(3); //Tushar: 20 apr GPIO3 configured as input -+ GPDR0 &= ~GPIO_bit(2); -+// GPDR0 &= ~GPIO_bit(5); -+// GPDR0 &= ~GPIO_bit(6); -+// GPDR0 &= ~GPIO_bit(7); -+// GPDR0 &= ~GPIO_bit(8); -+ -+ -+// KeyCol pin Status in sleep mode -+ PGSR0 &= ~GPIO_bit(9); //19 -+ PGSR0 &= ~GPIO_bit(10); //20 -+ PGSR0 &= ~GPIO_bit(11); //21 -+ PGSR0 &= ~GPIO_bit(12); //22 -+ PGSR0 &= ~GPIO_bit(13); //23 -+ PGSR0 &= ~GPIO_bit(14); //24 -+ -+ printk("KER_PM: Setting up wakeup sources 26May06\n"); -+ -+ // KeyPad -+ //printk("KER_PM: Uncommented key pad wakeup sources\n"); -+ PWER |= GPIO_bit(5); //11 -+ PWER |= GPIO_bit(6); //12 -+ PWER |= GPIO_bit(7); //13 -+ PWER |= GPIO_bit(8); //14 -+ PFER |= GPIO_bit(5); //11 -+ PFER |= GPIO_bit(6); //12 -+ PFER |= GPIO_bit(7); //13 -+ PFER |= GPIO_bit(8); //14 -+ PRER |= GPIO_bit(5); //11 -+ PRER |= GPIO_bit(6); //12 -+ PRER |= GPIO_bit(7); //13 -+ PRER |= GPIO_bit(8); //14 -+ -+ // USB -+ PWER |= GPIO_bit(3); //6 -+ PFER |= GPIO_bit(3); //6 -+ PRER |= GPIO_bit(3); //6 -+ -+ // PMU -+ PWER |= GPIO_bit(2); //4 -+ PFER |= GPIO_bit(2); //4 -+ PRER |= GPIO_bit(2); //4 -+ -+ // Anup : GSM RI -+ PWER |= GPIO_bit(0); //0 -+ PFER |= GPIO_bit(0); //0 -+ PRER |= GPIO_bit(0); //0 -+ // anup prashant : for gsm reset problem 19 may 2006 -+ //GPDR0 |= GPIO_bit(18); YoKu Commented this line, GPIO18 should be i/p pin to avoid GSM Reset pulse -+ PGSR0 |= GPIO_bit(18); // GSM reset pin -+ PGSR0 |= GPIO_bit(0); // -+ PGSR1 |= GPIO_bit(38); // commneted .18 apr -+ // <----- YoKu -+ -+ // YoKu -----> -+ // When exiting from sleep mode, 10us Low pulse comes on GSM Reset and Pwr pin -+ // to avoid this configure GPIO 18,80 as input pins before going to sleep mode -+ GPDR0 &= ~GPIO_bit(18); -+ //GPDR2 &= ~GPIO_bit(80); -+ // <----- YoKu -+ -+ //kirti for RTC -+ PWER |= PWER_RTC; -+ //kirti cli(); -+ local_irq_disable(); -+ //kirti clf(); -+ local_fiq_disable(); -+ leds_event(led_stop); -+ -+ /* Put Current time into RCNR */ -+ RCNR = xtime.tv_sec; - -- /* preserve current time */ -- rtc.tv_sec = RCNR; -- rtc.tv_nsec = 0; -- save_time_delta(&delta, &rtc); -+ printk("11May2006 KERR: pgsr0=0x%08x pgsr1=0x%08x pgsr2= 0x%08x\n",PGSR0,PGSR1,PGSR2); -+ printk("KER_PM_DELAY: SSCR Going to Sleep at RCNR =%d\n\n\n\n\n\n",RCNR); -+ -+ /* -+ * Temporary solution. This won't be necessary once -+ * we move pxa support into the serial driver -+ * Save the FF UART -+ */ -+ -+ // Anup : commented for power saving mode problem -+ printk("\nPM: Why doesnt it prnt?? 26May06\n"); -+ printk("\nPM : GSM Sleep Mode enabled"); -+ -+ -+ FFMCR &= ~UART_RTS; -+ udelay(2000); -+ udelay(2000); -+ FFMCR &= ~UART_DTR ; -+ udelay(2000); -+ -+ udelay(2000); -+ // rupali -+ // Anup : Do not check here -+/* if(!pm_pwronoff) -+ { -+ printk("\nPM : Modem Control Register = %x " , FFMCR); -+ while( FFMSR & 0x00000020) -+ { -+ printk("\nPM : FFFSR = %x " , FFMSR); -+ } -+ } */ -+ udelay(2000); -+ -+//Tushar: 19 apr -+// NSSCR0 &= 0xFFFFFF7F; -+// printk("\nPM: NSSCR0 = %x" ,NSSCR0 ); -+ -+ SAVE(FFIER); -+ SAVE(FFLCR); -+ SAVE(FFMCR); -+ SAVE(FFSPR); -+ SAVE(FFISR); -+ FFLCR |= 0x80; -+ SAVE(FFDLL); -+ SAVE(FFDLH); -+ SAVE(FFFCR); -+ FFLCR &= 0xef; -+ -+ SAVE(STIER); -+ SAVE(STLCR); -+ SAVE(STMCR); -+ SAVE(STSPR); -+ SAVE(STISR); -+ STLCR |= 0x80; -+ SAVE(STDLL); -+ SAVE(STDLH); -+ STLCR &= 0xef; -+ -+ SAVE(BTIER); -+ SAVE(BTLCR); -+ SAVE(BTMCR); -+ SAVE(BTSPR); -+ SAVE(BTISR); -+ BTLCR |= 0x80; -+ SAVE(BTDLL); -+ SAVE(BTDLH); -+ BTLCR &= 0xef; -+ -+ /* save vital registers */ -+ SAVE(OSCR); -+ SAVE(OSMR0); -+ SAVE(OSMR1); -+ SAVE(OSMR2); -+ SAVE(OSMR3); -+ SAVE(OIER); - -- SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); - SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); - SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); - SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); -- SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); -- - SAVE(GAFR0_L); SAVE(GAFR0_U); - SAVE(GAFR1_L); SAVE(GAFR1_U); - SAVE(GAFR2_L); SAVE(GAFR2_U); - --#ifdef CONFIG_PXA27x -- SAVE(MDREFR); -- SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3); -- SAVE(GAFR3_L); SAVE(GAFR3_U); -- SAVE(PWER); SAVE(PCFR); SAVE(PRER); -- SAVE(PFER); SAVE(PKWR); --#endif -+ // YoKu 23Feb06 Added To save LCD Registers, updated by kirti 24Feb06 -----> -+ SAVE(LCCR0); SAVE(LCCR1); SAVE(LCCR2); SAVE(LCCR3); -+ SAVE(FDADR0); -+ SAVE(FDADR1); -+ LCSR = 0xffffffff; /* Clear LCD Status Register */ -+ -+// LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ -+// LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */ -+ -+ SAVE(LDCMD0); -+ // <----- YoKu -+ -+// LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ -+// LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */ -+ - - SAVE(ICMR); - ICMR = 0; - - SAVE(CKEN); -- SAVE(PSTR); -+ CKEN = 0; -+ -+ // Anup : For Wifi power saving mode 2 May 2006 -+ SAVE(NSSCR0);SAVE(NSSCR1);SAVE(NSSSR);SAVE(NSSITR);SAVE(NSSDR);SAVE(NSSTO); -+ SAVE(NSSPSP); -+ printk("\nMY favourite mode in life.......sleep.....\n"); -+ - - /* Note: wake up source are set up in each machine specific files */ - -+ /*Changes to keep the right sim selected */ -+ gpsr0 = GPLR0; -+ gpsr1 = GPLR1; -+ gpsr2 = GPLR2; -+ -+ /*Sim 1 selected */ -+ // YoKu GPIOs Changed -----> -+ if( (GPLR0 & GPIO_bit(21)) && !(GPLR0 & GPIO_bit(22)) ) // 62,63 -+ { -+ PGSR0 |= GPIO_bit(21) ; //62 -+ PGSR0 &= ~GPIO_bit(22) ; //63 -+ } -+ else if (!(GPLR0 & GPIO_bit(21)) && (GPLR0 & GPIO_bit(22)) ) // 62,63 -+ { -+ PGSR0 |= GPIO_bit(22) ; //63 -+ PGSR0 &= ~GPIO_bit(21) ; //62 -+ } /* sim 2*/ -+ // <----- YoKu -+ - /* clear GPIO transition detect bits */ - GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; --#ifdef CONFIG_PXA27x -- GEDR3 = GEDR3; --#endif - - /* Clear sleep reset status */ - RCSR = RCSR_SMR; - -+ /* set resume return address */ -+ PSPR = virt_to_phys(pxa_cpu_resume); -+ - /* before sleeping, calculate and save a checksum */ - for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) - checksum += sleep_save[i]; - sleep_save[SLEEP_SAVE_CKSUM] = checksum; - -- /* *** go zzz *** */ -- pxa_cpu_pm_enter(state); -+ PGSR0 |= GPIO_bit(15); //sidd for wake from Sleep 15, YoKu Comented ?? GPIO15 was ChipSelect -+ PGSR2 |= GPIO_bit(80); //sidd for GSM Engine 69, YoKu GPIO Changed Anup :commented -+ -+ PGSR1 &= ~GPIO_bit(33); //Tushar: BT Codec Power Down -+ -+ PGSR0 &= ~GPIO_bit(23); //Tushar: BGW200 Regulator OFF -+ -+// GPDR1 |= GPIO_bit(49); //Tushar: LCD Serial Data in changed to O/P -+ -+// PGSR1 &= ~GPIO_bit(48);//Tushar: LCD Serial Pins -+ -+// PGSR1 &= ~GPIO_bit(49); -+ -+// PGSR1 &= ~GPIO_bit(50); -+ -+// PGSR1 |= GPIO_bit(51); -+ -+// PGSR1 &= 0x03FFFFFF;//Tushar: 24apr LCD datalines -+// PGSR2 &= 0xFFFFFC00; -+ -+ PGSR0 &= ~GPIO_bit(24); //Tushar: Mux Control Signals -+ -+ PGSR0 &= ~GPIO_bit(25); -+ -+ PGSR0 &= ~GPIO_bit(26); -+ -+ PGSR0 &= ~GPIO_bit(27); -+ -+ // GPDR0 |= GPIO_bit(17); //Tushar: unused GPIOs 19apr -+ // GPCR0 |= GPIO_bit(17); -+ PGSR0 &= ~GPIO_bit(17); -+ -+// GPDR1 |= GPIO_bit(56); //Tushar: unused GPIOs 19apr -+ // GPCR1 |= GPIO_bit(56); -+ PGSR1 &= ~GPIO_bit(56); -+ -+// GPDR2 |= GPIO_bit(79);//Tushar: unused GPIOs 19apr -+// GPCR2 |= GPIO_bit(79); -+ PGSR2 &= ~GPIO_bit(79); -+ -+// GPDR1 |= 0x03F00000;//Tushar: unused GPIOs 19apr -+// GPCR1 |= 0x03F00000; -+ PGSR1 &= 0xFC0FFFFF; -+ -+ -+ GPDR0 |= GPIO_bit(19);//Tushar: SIM Present Inputs configured as outputs -+ GPDR0 |= GPIO_bit(20); -+ PGSR0 &= ~GPIO_bit(19); -+ PGSR0 &= ~GPIO_bit(20); -+ -+ -+//Tushar: 25apr FFRTS FFDTR & FFTXD -+ -+ PGSR1 |= GPIO_bit(39); -+ PGSR1 |= GPIO_bit(40); -+ PGSR1 |= GPIO_bit(41); -+/* -+ PGSR2 &= GPIO_bit(81); //Tushar: 24apr NSSP pins -+ PGSR2 &= GPIO_bit(82); -+ PGSR2 &= GPIO_bit(83); -+ -+ PGSR2 |= GPIO_bit(74); -+ PGSR2 |= GPIO_bit(75); -+ PGSR2 |= GPIO_bit(76); -+ PGSR2 |= GPIO_bit(77); -+*/ -+ if(pm_pwronoff) -+ { -+ /* We are here bcos of pressing of on off switch -+ We wake up now only on pwr switch */ -+ printk("Anup: Before sleeping \n"); -+ pm_pwronoff = 0; -+ PGSR0 &= ~GPIO_bit(23); //7 YoKu GPIO Changed -+ //PGSR2 &= ~GPIO_bit(64); //64 YoKu Commented in PWG500 64,7 was WifiReg, IN PWG600 it is 23 -+ -+ PGSR2 &= ~GPIO_bit(80); //69 YoKu GPIO Changed Anup : commnented -+ PWER = 0x0004; // YoKu Changed from 0x10 to 0x04 (i.e GPIO 4 -> 2) -+ PFER = 0x0004; -+ PRER = 0x0004; -+ -+// YoKu ----> -+// 11May2006 To reduce Power Off current from 7mA to 4mA -+ GPDR0 |= GPIO_bit(16); // BTReset o/p Low -+ PGSR0 &= ~GPIO_bit(16); -+ -+ GPDR1 |= GPIO_bit(33); // nMEC/nPDI o/p Low -+ PGSR1 &= ~GPIO_bit(33); -+ -+ GPDR1 |= GPIO_bit(45); // BTRTS o/p High -+ PGSR1 |= GPIO_bit(45); -+ -+ -+ GPDR1 |= GPIO_bit(43); // BTTXD o/p High -+ PGSR1 |= GPIO_bit(43); -+ -+ GPDR1 &= ~GPIO_bit(42); // BTRXD i/p -+ GPDR1 &= ~GPIO_bit(44); // BTCTS i/p -+// <---- YoKu -+ -+ PSPR = virt_to_phys(pxa_cpu_resume); // YoKu 29July05 to Resume from where u left, Original PSPR = 0 -+ } -+ -+ valbefore = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; // 62,63 YoKu GPIO Changed -+ -+ //printk("Anup: Before sleeping gpsr0=0x%08x gpsr1=0x%08x gpsr2= 0x%08x\n",gpsr0,gpsr1,gpsr2); -+ //kirti pxa_cpu_suspend(); -+ //printk("KER_PM: Going to sleep zzzzzzzzz\n"); -+ -+// OSCC |= OSCC_OON; //Tushar: 18 apr. enable 32.768KHz Oscillator -+ -+// PCFR |= PCFR_OPDE; //Tushar: 18 apr. disable 3.6864MHz oscillator -+ -+ pxa_cpu_pm_enter(PM_SUSPEND_MEM); - - cpu_init(); - -+ //kirti~ -+ /**/ -+ //FFMCR |= UART_DTR ; -+ /**/ -+ - /* after sleeping, validate the checksum */ - checksum = 0; - for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) -@@ -141,39 +464,63 @@ - checksum = 0; - for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) - checksum += sleep_save[i]; -- - /* if invalid, display message and wait for a hardware reset */ -- if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) { -+ if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) -+ { - #ifdef CONFIG_ARCH_LUBBOCK - LUB_HEXLED = 0xbadbadc5; - #endif - while (1) -- pxa_cpu_pm_enter(state); -+ { -+ printk("\n\n\nKERN_PM: CRC Error!!! after wakeup\n\n\n"); // YoKu 25May06 -+ - } - -+ } -+ valafter = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; //62,63 YoKu GPIO Changed -+ pm_pedr = PEDR ; -+ - /* ensure not to come back here if it wasn't intended */ - PSPR = 0; - -+ /*printk("YoKu: gafr0_L=0x%08x gafr0_U=0x%08x\n",GAFR0_L,GAFR0_U); -+ printk(" gafr1_L= 0x%08x gafr1_U= 0x%08x\n",GAFR1_L,GAFR1_U); -+ printk(" gafr2_L= 0x%08x gafr2_U= 0x%08x\n",GAFR2_L,GAFR2_U); */ - /* restore registers */ -- RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2); - RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); -+ RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); -+ RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); - RESTORE(GAFR0_L); RESTORE(GAFR0_U); - RESTORE(GAFR1_L); RESTORE(GAFR1_U); - RESTORE(GAFR2_L); RESTORE(GAFR2_U); -- RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); -- RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); -- RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); - --#ifdef CONFIG_PXA27x -- RESTORE(MDREFR); -- RESTORE_GPLEVEL(3); RESTORE(GPDR3); -- RESTORE(GAFR3_L); RESTORE(GAFR3_U); -- RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3); -- RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER); -- RESTORE(PFER); RESTORE(PKWR); --#endif - -- PSSR = PSSR_RDH | PSSR_PH; -+ // Anup : For Wifi power saving mode 2 May 2006 -+ RESTORE(NSSCR0);RESTORE(NSSCR1);RESTORE(NSSSR);RESTORE(NSSITR);RESTORE(NSSDR);RESTORE(NSSTO); -+ RESTORE(NSSPSP); -+ -+ // PSSR = PSSR_PH; -+ GPSR0 = gpsr0; -+ GPSR1 = gpsr1; -+ GPSR2 = gpsr2; -+ -+ // Anup : check values of these registers -+// printk("YoKu: gpsr0=0x%08x gpsr1=0x%08x gpsr2= 0x%08x\n",gpsr0,gpsr1,gpsr2); -+ //sidd -+ -+ GPCR0 |= ~gpsr0; -+ GPCR1 |= ~gpsr1; -+ GPCR2 |= ~gpsr2; -+ -+ -+ PSSR = ~PSSR_PH; -+ -+ RESTORE(OSMR0); -+ RESTORE(OSMR1); -+ RESTORE(OSMR2); -+ RESTORE(OSMR3); -+ RESTORE(OSCR); -+ RESTORE(OIER); - - RESTORE(CKEN); - -@@ -181,62 +528,181 @@ - ICCR = 1; - RESTORE(ICMR); - -- RESTORE(PSTR); -+ /* -+ * Temporary solution. This won't be necessary once -+ * we move pxa support into the serial driver. -+ * Restore the FF UART. -+ */ -+ RESTORE(BTMCR); -+ RESTORE(BTSPR); -+ RESTORE(BTLCR); -+ BTLCR |= 0x80; -+ RESTORE(BTDLH); -+ RESTORE(BTDLL); -+ RESTORE(BTLCR); -+ RESTORE(BTISR); -+ BTFCR = 0xc7; -+ RESTORE(BTIER); -+ -+ RESTORE(STMCR); -+ RESTORE(STSPR); -+ RESTORE(STLCR); -+ STLCR |= 0x80; -+ RESTORE(STDLH); -+ RESTORE(STDLL); -+ RESTORE(STLCR); -+ RESTORE(STISR); -+ STFCR = 0xc7; -+ RESTORE(STIER); -+ -+ RESTORE(FFMCR); -+ RESTORE(FFSPR); -+ RESTORE(FFLCR); -+ FFLCR |= 0x80; -+ RESTORE(FFDLH); -+ RESTORE(FFDLL); -+ RESTORE(FFLCR); -+ RESTORE(FFISR); -+ RESTORE(FFFCR); -+ FFFCR = 0xc7; -+ RESTORE(FFIER); -+ -+ // YoKu 23Feb06 Added To save LCD Registers, updated by kirti 24Feb06 -----> -+ RESTORE(LCCR3); RESTORE(LCCR2); RESTORE(LCCR1); -+ LCCR0=RESTORE(LCCR0) & ~LCCR0_ENB; -+ RESTORE(FDADR0); RESTORE(FDADR1); -+ LCCR0 |= LCCR0_ENB; -+ -+ // <----- YoKu - - /* restore current time */ -- rtc.tv_sec = RCNR; -- restore_time_delta(&delta, &rtc); -+ xtime.tv_sec = RCNR; -+ -+ valafter1 = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; //62,63 YoKu GPIO Changed -+ -+// SSCR0 &=0xFFFFFFFF; -+// printk("\nPM : val of SSCR0 = %x " , SSCR0); -+ -+ printk("KER_PM: Resumed at RCNR = %d RTSR= %x\n",RCNR,RTSR); -+ -+ printk("YoKu: pgsr0=0x%08x pgsr1=0x%08x pgsr2= 0x%08x\n",PGSR0,PGSR1,PGSR2); -+ -+ OSMR0 = 0; /* set initial match at 0 */ -+ OSSR = 0xf; /* clear status on all timers */ -+ OIER |= OIER_E0; /* enable match on timer 0 to cause interrupts */ -+ OSCR = 0; /* initialize free-running timer, force first match */ -+ -+ leds_event(led_start); -+ //kirti sti(); -+ // call i2c reset here----> -+ ICR = ICR_UR; -+ ISR = 0x7FF; //I2C_ISR_INIT; -+ ICR &= ~ICR_UR; -+ -+ ISAR = 0x32;//i2c->slave_addr; -+ -+ /* set control register values */ -+ ICR = (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE);//I2C_ICR_INIT; -+ -+ /* enable unit */ -+ ICR |= ICR_IUE; -+ udelay(100); -+ //<----- -+ -+ local_irq_enable(); - --#ifdef DEBUG -- printk(KERN_DEBUG "*** made it back from resume\n"); --#endif - - return 0; - } - --EXPORT_SYMBOL_GPL(pxa_pm_enter); -- - unsigned long sleep_phys_sp(void *sp) - { - return virt_to_phys(sp); - } - -+#ifdef CONFIG_SYSCTL - /* -- * Called after processes are frozen, but before we shut down devices. -+ * ARGH! ACPI people defined CTL_ACPI in linux/acpi.h rather than -+ * linux/sysctl.h. -+ * -+ * This means our interface here won't survive long - it needs a new -+ * interface. Quick hack to get this working - use sysctl id 9999. - */ --int pxa_pm_prepare(suspend_state_t state) --{ -- extern int pxa_cpu_pm_prepare(suspend_state_t state); -+#warning ACPI broke the kernel, this interface needs to be fixed up. -+#define CTL_ACPI 9999 -+#define ACPI_S1_SLP_TYP 19 - -- return pxa_cpu_pm_prepare(state); -+/* -+ * Send us to sleep. -+ */ -+static int sysctl_pm_do_suspend(ctl_table *ctl, int write, struct file *filp, -+ void *buffer, size_t *lenp) -+{ -+ int retval=0; -+ unsigned i , clock ; -+ if (write) -+ { -+ char buf[16], *p; -+ unsigned int sleepsec; -+ int len,left = *lenp; -+ -+ len = left; -+ if (left > sizeof(buf)) -+ left = sizeof(buf); -+ if (!copy_from_user(buf, buffer, left)) -+ { -+ buf[sizeof(buf) - 1] = '\0'; -+ sleepsec = simple_strtoul(buf, &p, 0); -+ printk("\nSleeping %d Pwronoff=%x RCNR=%d\n",sleepsec,pm_pwronoff,RCNR); -+ printk("\nPWER %x PFER=%x PRER=%x\n",PWER,PFER,PRER); -+ RTAR = xtime.tv_sec + sleepsec; -+ printk("\nRTAR=%d \n",RTAR); -+ } -+ } -+ retval = pm_do_suspend(); -+ clock = get_memclk_frequency_10khz(); -+ return retval; - } -- --EXPORT_SYMBOL_GPL(pxa_pm_prepare); - - /* -- * Called after devices are re-setup, but before processes are thawed. -+static struct ctl_table pm_table[] = -+{ -+ {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend}, -+ {0} -+}; - */ --int pxa_pm_finish(suspend_state_t state) -+static struct ctl_table pm_table[] = - { -- return 0; -+ { -+ ctl_name: ACPI_S1_SLP_TYP, -+ procname: "suspend", -+ mode: 0600, -+ proc_handler: (proc_handler *)&sysctl_pm_do_suspend, -+ }, -+ { -+ ctl_name: 0 - } -+}; - --EXPORT_SYMBOL_GPL(pxa_pm_finish); -+static struct ctl_table pm_dir_table[] = -+{ -+ {CTL_ACPI, "pm", NULL, 0, 0555, pm_table}, -+ {0} -+}; - - /* -- * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk. -+ * Initialize power interface - */ --static struct pm_ops pxa_pm_ops = { -- .pm_disk_mode = PM_DISK_FIRMWARE, -- .prepare = pxa_pm_prepare, -- .enter = pxa_pm_enter, -- .finish = pxa_pm_finish, --}; -- --static int __init pxa_pm_init(void) -+static int __init pm_init(void) - { -- pm_set_ops(&pxa_pm_ops); -+ register_sysctl_table(pm_dir_table, 1); -+ /*Adi: Adjust for clock value to RTC -+ RTTR = RTC clk - 1*/ -+ RTTR = 32913; -+ - return 0; - } - --device_initcall(pxa_pm_init); -+__initcall(pm_init); -+ -+#endif -diff -NurbwB linux-2.6.17/arch/arm/mach-pxa/sleep.S linux-2.6.17-patched/arch/arm/mach-pxa/sleep.S ---- linux-2.6.17/arch/arm/mach-pxa/sleep.S 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/arch/arm/mach-pxa/sleep.S 2006-09-11 13:07:05.000000000 -0700 -@@ -79,7 +79,7 @@ - ldr r5, [r4] - - @ enable SDRAM self-refresh mode -- orr r5, r5, #MDREFR_SLFRSH -+ orr r5, r5, #(MDREFR_SLFRSH | MDREFR_APD) - - #ifdef CONFIG_PXA27x - @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50) -diff -NurbwB linux-2.6.17/include/asm-arm/arch-pxa/pxa-regs.h linux-2.6.17-patched/include/asm-arm/arch-pxa/pxa-regs.h ---- linux-2.6.17/include/asm-arm/arch-pxa/pxa-regs.h 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/include/asm-arm/arch-pxa/pxa-regs.h 2006-09-11 11:04:36.000000000 -0700 -@@ -1748,6 +1748,15 @@ - #define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL)) - #define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL)) - -+#define NSSCR0 __REG(0x41400000) /* SSP Port 1 Control Register 0 */ -+#define NSSCR1 __REG(0x41400004) /* SSP Port 1 Control Register 1 */ -+#define NSSSR __REG(0x41400008) /* SSP Port 1 Status Register */ -+#define NSSITR __REG(0x4140000C) /* SSP Port 1 Interrupt Test Register */ -+#define NSSDR __REG(0x41400010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */ -+#define NSSTO __REG(0x41400028) /* SSP Port 1 Time Out Register */ -+#define NSSPSP __REG(0x4140002C) /* SSP Port 1 Programmable Serial Port Register */ -+ -+ - /* - * MultiMediaCard (MMC) controller - */ -diff -NurbwB linux-2.6.17/kernel/power/main.c linux-2.6.17-patched/kernel/power/main.c ---- linux-2.6.17/kernel/power/main.c 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/kernel/power/main.c 2006-09-11 12:59:20.000000000 -0700 -@@ -66,10 +66,12 @@ - goto Enable_cpu; - } - -+ /* - if (freeze_processes()) { - error = -EAGAIN; - goto Thaw; - } -+ */ - - if ((free_pages = nr_free_pages()) < FREE_PAGE_NUMBER) { - pr_debug("PM: free some memory\n"); -@@ -110,12 +112,15 @@ - - local_irq_save(flags); - -+ /* - if ((error = device_power_down(PMSG_SUSPEND))) { - printk(KERN_ERR "Some devices failed to power down\n"); - goto Done; - } -+ */ -+ - error = pm_ops->enter(state); -- device_power_up(); -+ //device_power_up(); - Done: - local_irq_restore(flags); - return error; diff --git a/target/linux/pxa/patches/002-usb_gadget.patch b/target/linux/pxa/patches/002-usb_gadget.patch deleted file mode 100644 index b6766d9b3b..0000000000 --- a/target/linux/pxa/patches/002-usb_gadget.patch +++ /dev/null @@ -1,58 +0,0 @@ -diff -NurbwB linux-2.6.17/drivers/usb/gadget/pxa2xx_udc.c linux-2.6.17-patched/drivers/usb/gadget/pxa2xx_udc.c ---- linux-2.6.17/drivers/usb/gadget/pxa2xx_udc.c 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/drivers/usb/gadget/pxa2xx_udc.c 2006-09-11 13:02:39.000000000 -0700 -@@ -87,8 +87,8 @@ - static const char ep0name [] = "ep0"; - - --// #define USE_DMA --// #define USE_OUT_DMA -+#define USE_DMA -+#define USE_OUT_DMA - // #define DISABLE_TEST_MODE - - #ifdef CONFIG_ARCH_IXP4XX -@@ -1513,7 +1513,7 @@ - #endif - - /* try to clear these bits before we enable the udc */ -- udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR); -+ udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RSTIR|UDCCR_RESIR); - - ep0_idle(dev); - dev->gadget.speed = USB_SPEED_UNKNOWN; -@@ -2043,6 +2043,9 @@ - struct pxa2xx_udc *dev = _dev; - int handled; - -+ -+ udc_set_mask_UDCCR( UDCCR_REM | UDCCR_SRM); -+ - dev->stats.irqs++; - HEX_DISPLAY(dev->stats.irqs); - do { -@@ -2137,6 +2139,8 @@ - /* we could also ask for 1 msec SOF (SIR) interrupts */ - - } while (handled); -+ -+ udc_clear_mask_UDCCR( UDCCR_SRM | UDCCR_REM); - return IRQ_HANDLED; - } - -@@ -2437,6 +2441,7 @@ - int retval, out_dma = 1; - u32 chiprev; - -+ local_irq_disable(); - /* insist on Intel/ARM/XScale */ - asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev)); - if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) { -@@ -2553,6 +2558,7 @@ - #endif - } - #endif -+ local_irq_enable(); - create_proc_files(); - - return 0; diff --git a/target/linux/pxa/patches/004-skbuf_hack.patch b/target/linux/pxa/patches/004-skbuf_hack.patch deleted file mode 100644 index 434e3b98b1..0000000000 --- a/target/linux/pxa/patches/004-skbuf_hack.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- linux-2.6.17/include/linux/skbuff.h 2006-09-20 16:13:42.000000000 -0700 -+++ linux-2.6.17-patched/include/linux/skbuff.h 2006-09-20 16:14:29.000000000 -0700 -@@ -239,6 +239,7 @@ - } nh; - - union { -+ struct ethhdr *ethernet; - unsigned char *raw; - } mac; - diff --git a/target/linux/pxa/patches/005-mtd.patch b/target/linux/pxa/patches/005-mtd.patch deleted file mode 100644 index 6156b6a930..0000000000 --- a/target/linux/pxa/patches/005-mtd.patch +++ /dev/null @@ -1,111 +0,0 @@ -diff -Nurb linux-2.6.17/drivers/mtd/chips/cfi_cmdset_0001.c linux-2.6.17-patched/drivers/mtd/chips/cfi_cmdset_0001.c ---- linux-2.6.17/drivers/mtd/chips/cfi_cmdset_0001.c 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/drivers/mtd/chips/cfi_cmdset_0001.c 2006-09-25 11:27:06.000000000 -0700 -@@ -40,7 +40,7 @@ - /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ - - // debugging, turns off buffer write mode if set to 1 --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - #define MANUFACTURER_INTEL 0x0089 - #define I82802AB 0x00ad -diff -Nurb linux-2.6.17/drivers/mtd/maps/lubbock-flash.c linux-2.6.17-patched/drivers/mtd/maps/lubbock-flash.c ---- linux-2.6.17/drivers/mtd/maps/lubbock-flash.c 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/drivers/mtd/maps/lubbock-flash.c 2006-09-25 10:50:08.000000000 -0700 -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - - - #define ROM_ADDR 0x00000000 -@@ -48,24 +49,27 @@ - .inval_cache = lubbock_map_inval_cache, - } }; - --static struct mtd_partition lubbock_partitions[] = { -+static struct mtd_partition lubbock_partitions[] = -+{ - { -- .name = "Bootloader", -- .size = 0x00040000, -- .offset = 0, -- .mask_flags = MTD_WRITEABLE /* force read-only */ -- },{ -- .name = "Kernel", -- .size = 0x00100000, -- .offset = 0x00040000, -- },{ -- .name = "Filesystem", -- .size = MTDPART_SIZ_FULL, -- .offset = 0x00140000 -- } -+ .name = "root", -+ .offset = 0x00410000 -+ }, -+ { -+ .name = "kernel", -+ .size = 0x00150000, -+ .offset = 0x000B0000 -+ }, -+ { -+ .name = "bootloader", -+ .size = 0x000B0000, -+ .offset = 0x00000000 -+ }, - }; - -+ - static struct mtd_info *mymtds[2]; -+static struct mtd_info *merged_mtd; - static struct mtd_partition *parsed_parts[2]; - static int nr_parsed_parts[2]; - -@@ -83,8 +87,8 @@ - printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n", - flashboot?"Flash":"ROM", flashboot); - -- lubbock_maps[flashboot^1].name = "Lubbock Application Flash"; -- lubbock_maps[flashboot].name = "Lubbock Boot ROM"; -+ lubbock_maps[flashboot^1].name = "Flash-1"; -+ lubbock_maps[flashboot].name = "Flash-0"; - - for (i = 0; i < 2; i++) { - lubbock_maps[i].virt = ioremap(lubbock_maps[i].phys, WINDOW_SIZE); -@@ -125,25 +129,23 @@ - if (!mymtds[0] && !mymtds[1]) - return ret; - -- for (i = 0; i < 2; i++) { -- if (!mymtds[i]) { -- printk(KERN_WARNING "%s is absent. Skipping\n", lubbock_maps[i].name); -- } else if (nr_parsed_parts[i]) { -- add_mtd_partitions(mymtds[i], parsed_parts[i], nr_parsed_parts[i]); -- } else if (!i) { -- printk("Using static partitions on %s\n", lubbock_maps[i].name); -- add_mtd_partitions(mymtds[i], lubbock_partitions, ARRAY_SIZE(lubbock_partitions)); -- } else { -- printk("Registering %s as whole device\n", lubbock_maps[i].name); -- add_mtd_device(mymtds[i]); -- } -- } -+ if (mymtds[0] && mymtds[1]) { -+ merged_mtd = mtd_concat_create(mymtds, 2, "Concated Flash #1 and #2"); -+ if(merged_mtd) -+ add_mtd_partitions(merged_mtd, lubbock_partitions, ARRAY_SIZE(lubbock_partitions)); -+ else -+ printk("YoKu: Failed to concate\n"); - return 0; -+ } - } - - static void __exit cleanup_lubbock(void) - { - int i; -+ -+ del_mtd_partitions(merged_mtd); -+ map_destroy(merged_mtd); -+ - for (i = 0; i < 2; i++) { diff --git a/target/linux/sibyte/Makefile b/target/linux/sibyte/Makefile deleted file mode 100644 index f4436a84cf..0000000000 --- a/target/linux/sibyte/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=mips -BOARD:=sibyte -BOARDNAME:=Broadcom/SiByte SB-1 -FEATURES:=broken - -LINUX_VERSION:=2.6.26.5 - -include $(INCLUDE_DIR)/target.mk - -$(eval $(call BuildTarget)) diff --git a/target/linux/sibyte/base-files/etc/config/network b/target/linux/sibyte/base-files/etc/config/network deleted file mode 100644 index 9b65652f06..0000000000 --- a/target/linux/sibyte/base-files/etc/config/network +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (C) 2006 OpenWrt.org - -config interface loopback - option ifname lo - option proto static - option ipaddr 127.0.0.1 - option netmask 255.0.0.0 - -config interface lan - option type bridge - option ifname "eth0 ath0" - option proto static - option ipaddr 192.168.1.1 - option netmask 255.255.255.0 diff --git a/target/linux/sibyte/base-files/etc/inittab b/target/linux/sibyte/base-files/etc/inittab deleted file mode 100644 index a6f4e17f01..0000000000 --- a/target/linux/sibyte/base-files/etc/inittab +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (C) 2006 OpenWrt.org - -::sysinit:/etc/init.d/rcS -duart/0::askfirst:/bin/ash --login -#tts/1::askfirst:/bin/ash --login diff --git a/target/linux/sibyte/config-default b/target/linux/sibyte/config-default deleted file mode 100644 index e431b86c0d..0000000000 --- a/target/linux/sibyte/config-default +++ /dev/null @@ -1,279 +0,0 @@ -# CONFIG_32BIT is not set -CONFIG_64BIT=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_POPULATES_NODE_MAP=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ARPD is not set -# CONFIG_ATM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BCM47XX is not set -CONFIG_BINFMT_ELF32=y -CONFIG_BITREVERSE=y -CONFIG_BLOCK_COMPAT=y -# CONFIG_BONDING is not set -CONFIG_BOOT_ELF32=y -CONFIG_BROADCOM_PHY=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_BT is not set -CONFIG_CEVT_SB1250=y -CONFIG_CFE=y -# CONFIG_CIFS_STATS is not set -CONFIG_CLASSIC_RCU=y -# CONFIG_CLS_U32_MARK is not set -# CONFIG_CLS_U32_PERF is not set -CONFIG_COMPAT=y -# CONFIG_CONFIGFS_FS is not set -CONFIG_CONNECTOR=m -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_LOONGSON2 is not set -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -CONFIG_CPU_SB1=y -# CONFIG_CPU_SB1_PASS_1 is not set -# CONFIG_CPU_SB1_PASS_2_112x is not set -# CONFIG_CPU_SB1_PASS_2_1250 is not set -# CONFIG_CPU_SB1_PASS_2_2 is not set -CONFIG_CPU_SB1_PASS_3=y -# CONFIG_CPU_SB1_PASS_4 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -CONFIG_CSRC_SB1250=y -# CONFIG_DM9000 is not set -CONFIG_DMA_COHERENT=y -# CONFIG_E1000E_ENABLED is not set -CONFIG_EARLY_PRINTK=y -# CONFIG_FIXED_PHY is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_FW_LOADER=m -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CMOS_UPDATE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -CONFIG_GENERIC_FIND_NEXT_BIT=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_HAVE_IDE=y -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=m -CONFIG_HZ=250 -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_I2C is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IDE is not set -# CONFIG_IEEE80211 is not set -CONFIG_INITRAMFS_ROOT_GID=0 -CONFIG_INITRAMFS_ROOT_UID=0 -CONFIG_INITRAMFS_SOURCE="../root" -CONFIG_INPUT=m -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_TARGET_HL is not set -# CONFIG_IP6_NF_TARGET_LOG is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IP_NF_ARPTABLES is not set -# CONFIG_IP_NF_MATCH_ADDRTYPE is not set -# CONFIG_IP_NF_TARGET_LOG is not set -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_ROUTE_VERBOSE is not set -CONFIG_IRQ_CPU=y -# CONFIG_ISDN is not set -# CONFIG_IWLWIFI_LEDS is not set -# CONFIG_LEDS_ALIX is not set -# CONFIG_LEMOTE_FULONG is not set -# CONFIG_LLC2 is not set -CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_MINI_FO=m -CONFIG_MIPS=y -CONFIG_MIPS32_COMPAT=y -# CONFIG_MIPS32_N32 is not set -CONFIG_MIPS32_O32=y -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_ONENAND is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PHRAM is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -CONFIG_MTD_PHYSMAP_LEN=0 -CONFIG_MTD_PHYSMAP_START=0x8000000 -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_IPGRE_BROADCAST is not set -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_N_HDLC is not set -CONFIG_PAGEFLAGS_EXTENDED=y -# CONFIG_PAGE_SIZE_16KB is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_64KB is not set -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PCSPKR_PLATFORM is not set -CONFIG_PHYLIB=y -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_SYNC_TTY is not set -# CONFIG_PROC_KCORE is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_REALTEK_PHY is not set -CONFIG_RESOURCES_64BIT=y -# CONFIG_RFKILL is not set -# CONFIG_RIO is not set -# CONFIG_RISCOM8 is not set -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_SB1250_MAC=y -# CONFIG_SB1XXX_CORELIS is not set -# CONFIG_SB1_CERR_STALL is not set -# CONFIG_SB1_CEX_ALWAYS_FATAL is not set -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_SERIAL_SB1250_DUART=y -CONFIG_SERIAL_SB1250_DUART_CONSOLE=y -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -CONFIG_SIBYTE_BCM1125H=y -CONFIG_SIBYTE_BCM112X=y -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_BUS_WATCHER is not set -# CONFIG_SIBYTE_CARMEL is not set -CONFIG_SIBYTE_CFE=y -# CONFIG_SIBYTE_CFE_CONSOLE is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_DMA_PAGEOPS is not set -CONFIG_SIBYTE_ENABLE_LDT_IF_PCI=y -CONFIG_SIBYTE_HAS_ZBUS_PROFILING=y -# CONFIG_SIBYTE_LITTLESUR is not set -CONFIG_SIBYTE_RHONE=y -CONFIG_SIBYTE_SB1xxx_SOC=y -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_TBPROF is not set -# CONFIG_SIMULATION is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_SOUND is not set -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -# CONFIG_SPECIALIX is not set -CONFIG_SSB_POSSIBLE=y -# CONFIG_STALDRV is not set -CONFIG_SWAP_IO_SPACE=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYS_HAS_CPU_SB1=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -CONFIG_TICK_ONESHOT=y -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_DEV is not set -# CONFIG_VIDEO_MEDIA is not set -# CONFIG_W1 is not set -# CONFIG_WATCHDOG is not set -CONFIG_WEAK_ORDERING=y -# CONFIG_WIRELESS_EXT is not set -# CONFIG_WLAN_80211 is not set -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/sibyte/image/Makefile b/target/linux/sibyte/image/Makefile deleted file mode 100644 index 43ac67629a..0000000000 --- a/target/linux/sibyte/image/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -# -# Copyright (C) 2007 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -#define Image/Prepare -# cp $(LINUX_DIR)/arch/arm/boot/zImage $(KDIR)/zImage -#endef - -define Image/BuildKernel - cp $(KDIR)/vmlinux $(BIN_DIR)/openwrt-$(BOARD)-vmlinux -endef - -define Image/Build - $(call Image/Build/$(1),$(1)) -endef - -define Image/Build/jffs2-64k - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=65536 conv=sync -endef - -define Image/Build/jffs2-128k - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync - $(call Image/Build/slug,$(1)) -endef - -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync - $(call Image/Build/slug,$(1)) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/storm/Makefile b/target/linux/storm/Makefile deleted file mode 100644 index abd6b0cc38..0000000000 --- a/target/linux/storm/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# Copyright (C) 2006-2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=storm -BOARDNAME:=Storm SL3512 -FEATURES:=squashfs pci broken - -LINUX_VERSION:=2.6.23.17 - -include $(INCLUDE_DIR)/target.mk - -define Target/Description - Build images for boards based on the Storm Semiconductor SL3512, eg. Wiligear WBD-111 -endef - -define Kernel/Configure - $(call Kernel/Configure/Default) - $(SED) 's,.*CONFIG_AEABI.*,$(if $(CONFIG_EABI_SUPPORT),CONFIG_AEABI=y,# CONFIG_AEABI is not set),' $(LINUX_DIR)/.config - $(if $(CONFIG_EABI_SUPPORT),echo '# CONFIG_OABI_COMPAT is not set' >> $(LINUX_DIR)/.config) -endef - -$(eval $(call BuildTarget)) diff --git a/target/linux/storm/config-default b/target/linux/storm/config-default deleted file mode 100644 index 2ff7f47b39..0000000000 --- a/target/linux/storm/config-default +++ /dev/null @@ -1,318 +0,0 @@ -# CONFIG_AEABI is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_SHARK is not set -CONFIG_ARCH_SL2312=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_ARCH_VERSATILE is not set -CONFIG_ARM=y -# CONFIG_ARPD is not set -# CONFIG_ARTHUR is not set -# CONFIG_ATM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BINFMT_AOUT is not set -CONFIG_BITREVERSE=y -# CONFIG_BLK_DEV is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_BONDING is not set -CONFIG_BOUNCE=y -CONFIG_BRIDGE=m -CONFIG_BRIDGE_NETFILTER=y -# CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_BT is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -# CONFIG_CIFS is not set -# CONFIG_CLS_U32_PERF is not set -CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 init=/etc/preinit mem=32M loglevel=8" -# CONFIG_CONFIGFS_FS is not set -CONFIG_CPU_32=y -CONFIG_CPU_32v4=y -CONFIG_CPU_ABRT_EV4=y -CONFIG_CPU_CACHE_FA=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_FA=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -CONFIG_CPU_FA526=y -CONFIG_CPU_FA_BTB=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_TLB_FA=y -# CONFIG_CRC_ITU_T is not set -# CONFIG_CRYPTO is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_INFO is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_SHIRQ is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_IOSCHED="noop" -CONFIG_DEFAULT_NOOP=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_DETECT_SOFTLOCKUP is not set -CONFIG_DEVPORT=y -# CONFIG_DM9000 is not set -CONFIG_ELF_CORE=y -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_EPOLL is not set -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_FAULT_INJECTION is not set -CONFIG_FORCED_INLINING=y -# CONFIG_FPE_FASTFPE is not set -# CONFIG_FPE_NWFPE is not set -CONFIG_FRAME_POINTER=y -# CONFIG_FUTEX is not set -# CONFIG_FW_LOADER is not set -CONFIG_GEMINI_GPIO_DEV=y -# CONFIG_GEMINI_IPI is not set -# CONFIG_GENERIC_CLOCKEVENTS is not set -# CONFIG_GENERIC_GPIO is not set -# CONFIG_GENERIC_TIME is not set -# CONFIG_HAMRADIO is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -# CONFIG_HFSPLUS_FS is not set -# CONFIG_HFS_FS is not set -CONFIG_HW_RANDOM=y -# CONFIG_I2C is not set -# CONFIG_IDE is not set -# CONFIG_IEEE80211 is not set -# CONFIG_IFB is not set -# CONFIG_IKCONFIG is not set -# CONFIG_IMQ is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_DIAG is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_BEET=m -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IPSEC_NAT_TRAVERSAL is not set -# CONFIG_IPV6 is not set -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -# CONFIG_ISDN is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JFFS2_RTIME is not set -# CONFIG_JFFS2_SUMMARY is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KMOD=y -CONFIG_LLC=m -# CONFIG_LLC2 is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_MINIX_FS is not set -# CONFIG_MISC_DEVICES is not set -# CONFIG_MSDOS_FS is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_I1=y -# CONFIG_MTD_CFI_I2 is not set -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_JEDECPROBE is not set -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_ONENAND is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -CONFIG_MTD_REDBOOT_PARTS=y -# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ROOTFS_ROOT_DEV is not set -# CONFIG_MTD_ROOTFS_SPLIT is not set -# CONFIG_MTD_SERIAL is not set -CONFIG_MTD_SL2312_CFI=y -# CONFIG_MTD_SL2312_SERIAL_ATMEL is not set -# CONFIG_MTD_SL2312_SERIAL_ST is not set -# CONFIG_MTD_SLRAM is not set -CONFIG_NETDEV_1000=y -# CONFIG_NET_ACT_GACT is not set -# CONFIG_NET_ACT_IPT is not set -# CONFIG_NET_ACT_MIRRED is not set -# CONFIG_NET_ACT_PEDIT is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set -# CONFIG_NET_EMATCH is not set -CONFIG_NET_GMAC=y -# CONFIG_NET_IPGRE is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_KEY is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_ESFQ is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_INGRESS is not set -# CONFIG_NET_SCH_PRIO is not set -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_RR is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_SL2312 is not set -CONFIG_NET_SL351X=y -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_NFSD is not set -# CONFIG_NFS_FS is not set -# CONFIG_NLS is not set -# CONFIG_NO_IDLE_HZ is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_NVRAM is not set -# CONFIG_OUTER_CACHE is not set -CONFIG_PACKET=m -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PCI=y -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_PCI_DEBUG is not set -CONFIG_PCI_SYSCALL=y -# CONFIG_PPP_MPPE is not set -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PRINTK_TIME=y -# CONFIG_PROVE_LOCKING is not set -# CONFIG_RCU_TORTURE_TEST is not set -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_SL2312=y -CONFIG_SERIAL_SL2312_CONSOLE=y -# CONFIG_SHMEM is not set -# CONFIG_SL2312_LPC is not set -# CONFIG_SL2312_MPAGE is not set -# CONFIG_SL2312_RECVFILE is not set -# CONFIG_SL2312_SHARE_PIN is not set -# CONFIG_SL2312_TSO is not set -# CONFIG_SL2312_USB is not set -CONFIG_SL3516_ASIC=y -# CONFIG_SMC91X is not set -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SOUND is not set -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_STANDALONE is not set -# CONFIG_SWAP is not set -# CONFIG_SYN_COOKIES is not set -CONFIG_SYSFS_DEPRECATED=y -# CONFIG_SYSVIPC is not set -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -# CONFIG_TICK_ONESHOT is not set -# CONFIG_TIMER_STATS is not set -CONFIG_TINY_SHMEM=y -# CONFIG_UDF_FS is not set -CONFIG_UID16=y -# CONFIG_USB_SUPPORT is not set -# CONFIG_USER_NS is not set -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VFAT_FS is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_DEV is not set -CONFIG_VLAN_8021Q=m -# CONFIG_W1 is not set -CONFIG_WATCHDOG_SL351X=y -# CONFIG_WLAN_80211 is not set -# CONFIG_XFRM_USER is not set -# CONFIG_XFS_FS is not set -# CONFIG_XIP_KERNEL is not set -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/storm/image/Makefile b/target/linux/storm/image/Makefile deleted file mode 100644 index b061c6d0ef..0000000000 --- a/target/linux/storm/image/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# Copyright (C) 2007 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Image/Prepare - cp $(LINUX_DIR)/arch/arm/boot/zImage $(KDIR)/zImage -endef - -define Image/BuildKernel - cp $(KDIR)/zImage $(BIN_DIR)/openwrt-$(BOARD)-zImage -# -# XXX - FIXME -# -# BIN_DIR=$(BIN_DIR) $(TOPDIR)/scripts/arm-magic.sh -endef - -define Image/Build - $(call Image/Build/$(1),$(1)) -endef - -define Image/Build/jffs2-64k - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=65536 conv=sync -endef - -define Image/Build/jffs2-128k - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync - $(call Image/Build/slug,$(1)) -endef - -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync - $(call Image/Build/slug,$(1)) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/storm/patches/001-arch.patch b/target/linux/storm/patches/001-arch.patch deleted file mode 100644 index b0461d44e3..0000000000 --- a/target/linux/storm/patches/001-arch.patch +++ /dev/null @@ -1,8864 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -220,6 +220,9 @@ - help - This enables support for the Cirrus EP93xx series of CPUs. - -+config ARCH_SL2312 -+ bool "SL2312" -+ - config ARCH_FOOTBRIDGE - bool "FootBridge" - select FOOTBRIDGE -@@ -414,6 +417,8 @@ - - source "arch/arm/mach-footbridge/Kconfig" - -+source "arch/arm/mach-sl2312/Kconfig" -+ - source "arch/arm/mach-integrator/Kconfig" - - source "arch/arm/mach-iop32x/Kconfig" -@@ -549,6 +554,16 @@ - config PCI_SYSCALL - def_bool PCI - -+config SL2312_LPC -+ bool "LPC Host Support" -+ depends on ARCH_SL2312 -+ help -+ -+config SL2312_LPC_IT8712 -+ bool "IT8712 Support" -+ depends on ARCH_SL2312 && SL2312_LPC -+ help -+ - # Select the host bridge type - config PCI_HOST_VIA82C505 - bool -@@ -988,6 +1003,10 @@ - source "drivers/mtd/Kconfig" - endif - -+if ARCH_SL2312 -+source "drivers/telephony/Kconfig" -+endif -+ - source "drivers/parport/Kconfig" - - source "drivers/pnp/Kconfig" -@@ -997,7 +1016,7 @@ - if PCMCIA || ARCH_CLPS7500 || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX \ - || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \ - || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \ -- || ARCH_IXP23XX -+ || ARCH_IXP23XX || ARCH_SL2312 - source "drivers/ide/Kconfig" - endif - ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -72,6 +72,7 @@ - tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi - tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi - tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi -+tune-$(CONFIG_CPU_FA52X) :=-mtune=arm9tdmi - tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 - tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 - tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale -@@ -111,6 +112,7 @@ - machine-$(CONFIG_ARCH_PXA) := pxa - machine-$(CONFIG_ARCH_L7200) := l7200 - machine-$(CONFIG_ARCH_INTEGRATOR) := integrator -+ machine-$(CONFIG_ARCH_SL2312) := sl2312 - textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 - machine-$(CONFIG_ARCH_CLPS711X) := clps711x - machine-$(CONFIG_ARCH_IOP32X) := iop32x ---- a/arch/arm/boot/compressed/Makefile -+++ b/arch/arm/boot/compressed/Makefile -@@ -19,6 +19,10 @@ - OBJS += head-shark.o ofw-shark.o - endif - -+ifeq ($(CONFIG_ARCH_SL2312),y) -+OBJS += head-sl2312.o -+endif -+ - ifeq ($(CONFIG_ARCH_L7200),y) - OBJS += head-l7200.o - endif ---- /dev/null -+++ b/arch/arm/boot/compressed/head-sl2312.S -@@ -0,0 +1,6 @@ -+#include -+#include -+ -+ .section ".start", "ax" -+ mov r7, #MACH_TYPE_SL2312 -+ ---- a/arch/arm/boot/compressed/head.S -+++ b/arch/arm/boot/compressed/head.S -@@ -57,6 +57,17 @@ - mov \rb, #0x50000000 - add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT - .endm -+/***************************************************** -+ * for Storlink SoC -+ *****************************************************/ -+#elif defined(CONFIG_ARCH_SL2312) -+ .macro loadsp, rb -+ mov \rb, #0x16000000 -+ .endm -+ .macro writeb, rb -+ strb \rb, [r3, #0] -+ .endm -+/****************************************************/ - #else - .macro loadsp, rb - addruart \rb -@@ -116,7 +127,28 @@ - .rept 8 - mov r0, r0 - .endr -- -+/***************************************************************************** -+ * for Storlink Soc -- on chip UART -+ *****************************************************************************/ -+#ifndef CONFIG_SERIAL_IT8712 // Jason test -+@ mov r3, #0x22000000 -+ mov r3, #0x42000000 -+ mov r11, #0x80 -+ strb r11, [r3, #0xc] -+ mov r11, #0x0 -+ strb r11, [r3, #0x4] -+#ifndef CONFIG_SL3516_ASIC -+ mov r11, #0x9C /*0x9c->19200 0x4E->38400 0x34->57600 */ -+#else -+ mov r11, #0x9C /* 0x61 for 30MHz on GeminiA chip*/ -+#endif -+ strb r11, [r3, #0x0] -+ mov r11, #0x03 -+ strb r11, [r3, #0xc] -+ mov r11, #0xFB -+ strb r11, [r3, #0x18] -+#endif -+/*****************************************************************************/ - b 1f - .word 0x016f2818 @ Magic numbers to help the loader - .word start @ absolute load/run zImage address -@@ -458,6 +490,39 @@ - mcr p15, 0, r0, c7, c5, 4 @ ISB - mov pc, r12 - -+/***************************************************************************** -+ * for Storlink Soc -- CPU cache -+ *****************************************************************************/ -+__fa526_cache_on: -+ mov r12, lr -+ bl __setup_mmu -+ mov r0, #0 -+ mcr p15, 0, r0, c7, c6, 0 @ Invalidate D cache -+ mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache -+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer -+ mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs -+ mcr p15, 0, r3, c2, c0, 0 @ load page table pointer -+ mov r0, #-1 -+ mcr p15, 0, r0, c3, c0, 0 @ load domain access register -+ mrc p15, 0, r0, c1, c0, 0 -+ mov r0, r0 -+ mov r0, r0 -+#ifndef CONFIG_CPU_DCACHE_DISABLE -+ orr r0, r0, #0x0004 @ .... .... .... .1.. -+#endif -+#ifndef CONFIG_CPU_ICACHE_DISABLE -+ orr r0, r0, #0x1000 @ ...1 .... .... .... -+#endif -+ -+#ifndef DEBUG -+ orr r0, r0, #0x0039 @ Write buffer, mmu -+#endif -+ mcr p15, 0, r0, c1, c0 -+ mov r0, r0 -+ mov r0, r0 -+ mov pc, r12 -+/********************************************************************************/ -+ - __arm6_mmu_cache_on: - mov r12, lr - bl __setup_mmu -@@ -625,6 +690,16 @@ - - @ These match on the architecture ID - -+/***************************************************************************** -+ * for Storlink Soc -- CPU architecture ID -+ *****************************************************************************/ -+ .word 0x66015261 @ FA526 -+ .word 0xff01fff1 -+ b __fa526_cache_on -+ b __fa526_cache_off -+ b __fa526_cache_flush -+/*****************************************************************************/ -+ - .word 0x00020000 @ ARMv4T - .word 0x000f0000 - b __armv4_mmu_cache_on -@@ -712,6 +787,23 @@ - mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB - mov pc, r12 - -+/***************************************************************************** -+ * for Storlink Soc -- CPU cache -+ *****************************************************************************/ -+__fa526_cache_off: -+ mrc p15, 0, r0, c1, c0 -+ bic r0, r0, #0x000d -+ mov r1, #0 -+ mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache -+ mcr p15, 0, r1, c7, c10, 4 @ drain WB -+ mcr p15, 0, r0, c1, c0 @ turn MMU and cache off -+ mov r0, #0 -+ mcr p15, 0, r0, c7, c5, 0 @ invalidate whole cache v4 -+ mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB v4 -+ mov pc, lr -+/*****************************************************************************/ -+ -+ - __arm6_mmu_cache_off: - mov r0, #0x00000030 @ ARM6 control reg. - b __armv3_mmu_cache_off -@@ -759,6 +851,17 @@ - mcr p15, 0, ip, c7, c10, 4 @ drain WB - mov pc, lr - -+/***************************************************************************** -+ * for Storlink Soc -- CPU cache -+ *****************************************************************************/ -+__fa526_cache_flush: -+ mov r1, #0 -+ mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache -+ mcr p15, 0, r1, c7, c5, 0 @ flush I cache -+ mcr p15, 0, r1, c7, c10, 4 @ drain WB -+ mov pc, lr -+/*****************************************************************************/ -+ - - __armv6_mmu_cache_flush: - mov r1, #0 ---- /dev/null -+++ b/arch/arm/boot/compressed/it8712.h -@@ -0,0 +1,25 @@ -+ -+#ifndef __IT8712_H__ -+#define __IT8712_H__ -+ -+#include "asm/arch/sl2312.h" -+ -+#define IT8712_IO_BASE SL2312_LPC_IO_BASE -+//#define IT8712_IO_BASE 0x27000000 -+// Device LDN -+#define LDN_SERIAL1 0x01 -+#define LDN_SERIAL2 0x02 -+#define LDN_PARALLEL 0x03 -+#define LDN_KEYBOARD 0x05 -+#define LDN_MOUSE 0x06 -+#define LDN_GPIO 0x07 -+ -+#define IT8712_UART1_PORT 0x3F8 -+#define IT8712_UART2_PORT 0x2F8 -+ -+#define IT8712_GPIO_BASE 0x800 // 0x800-0x804 for GPIO set1-set5 -+ -+void LPCSetConfig(char LdnNumber, char Index, char data); -+char LPCGetConfig(char LdnNumber, char Index); -+ -+#endif ---- a/arch/arm/boot/compressed/misc.c -+++ b/arch/arm/boot/compressed/misc.c -@@ -30,7 +30,7 @@ - #include - - #ifdef CONFIG_DEBUG_ICEDCC -- -+#include "it8712.h" - #ifdef CONFIG_CPU_V6 - - static void icedcc_putc(int ch) -@@ -69,6 +69,7 @@ - #define flush() do { } while (0) - #endif - -+#if 0 - static void putstr(const char *ptr) - { - char c; -@@ -81,11 +82,36 @@ - - flush(); - } -+#endif - - #endif - - #define __ptr_t void * - -+#ifdef CONFIG_SERIAL_IT8712 -+unsigned int it8712_uart_base; -+#define UART_RX 0 -+#define UART_TX 0 -+#define UART_DLL 0 -+#define UART_TRG 0 -+#define UART_DLM 1 -+#define UART_IER 1 -+#define UART_FCTR 1 -+#define UART_IIR 2 -+#define UART_FCR 2 -+#define UART_EFR 2 -+#define UART_LCR 3 -+#define UART_MCR 4 -+#define UART_LSR 5 -+#define UART_MSR 6 -+#define UART_SCR 7 -+#define UART_EMSR 7 -+void LPCEnterMBPnP(void); -+void LPCExitMBPnP(void); -+int SearchIT8712(void); -+int InitLPCInterface(void); -+#endif -+ - /* - * Optimised C version of memzero for the ARM. - */ -@@ -346,6 +372,9 @@ - decompress_kernel(ulg output_start, ulg free_mem_ptr_p, ulg free_mem_ptr_end_p, - int arch_id) - { -+#ifdef CONFIG_SERIAL_IT8712 -+ unsigned char *addr; -+#endif - output_data = (uch *)output_start; /* Points to kernel start */ - free_mem_ptr = free_mem_ptr_p; - free_mem_ptr_end = free_mem_ptr_end_p; -@@ -353,6 +382,33 @@ - - arch_decomp_setup(); - -+#ifdef CONFIG_SERIAL_IT8712 -+ -+ InitLPCInterface(); -+ LPCSetConfig(0, 0x02, 0x01); -+ LPCSetConfig(LDN_SERIAL1, 0x30, 0x1); -+ LPCSetConfig(LDN_SERIAL1, 0x23, 0x0); -+ it8712_uart_base = IT8712_IO_BASE; -+ it8712_uart_base += ((LPCGetConfig(LDN_SERIAL1, 0x60) << 8) + LPCGetConfig(LDN_SERIAL1, 0x61)); -+ -+ do { -+ addr = (unsigned char *)(it8712_uart_base + UART_LCR) ; -+ *addr = 0x80; -+ // Set Baud Rate -+ addr = (unsigned char *)(it8712_uart_base+UART_DLL); -+ *addr = 0x06 ; -+ addr = (unsigned char *)(it8712_uart_base+UART_DLM); -+ *addr = 0x00 ; -+ -+ addr = (unsigned char *)(it8712_uart_base+UART_LCR); // LCR -+ *addr = 0x07 ; -+ addr = (unsigned char *)(it8712_uart_base+UART_MCR); // MCR -+ *addr = 0x08 ; -+ addr = (unsigned char *)(it8712_uart_base+UART_FCR); // FCR -+ *addr = 0x01 ; -+ } while(0); -+#endif -+ - makecrc(); - putstr("Uncompressing Linux..."); - gunzip(); -@@ -374,4 +430,119 @@ - return 0; - } - #endif -+ -+#ifdef CONFIG_SERIAL_IT8712 -+ -+#define LPC_KEY_ADDR (unsigned char *)(SL2312_LPC_IO_BASE + 0x2e) -+#define LPC_DATA_ADDR (unsigned char *)(SL2312_LPC_IO_BASE + 0x2f) -+#define LPC_BUS_CTRL *( unsigned char*) (SL2312_LPC_HOST_BASE + 0) -+#define LPC_BUS_STATUS *( unsigned char*) (SL2312_LPC_HOST_BASE + 2) -+#define LPC_SERIAL_IRQ_CTRL *( unsigned char*) (SL2312_LPC_HOST_BASE + 4) -+ -+char LPCGetConfig(char LdnNumber, char Index) -+{ -+ char rtn; -+ unsigned char *addr ; -+ -+ LPCEnterMBPnP(); // Enter IT8712 MB PnP mode -+ -+ addr = LPC_KEY_ADDR; -+ *addr = 0x07 ; -+ -+ addr = LPC_DATA_ADDR; -+ *addr = LdnNumber ; -+ -+ addr = LPC_KEY_ADDR; -+ *addr = Index ; -+ -+ addr = LPC_DATA_ADDR ; -+ rtn = *addr ; -+ -+ LPCExitMBPnP(); -+ return rtn; -+ -+} -+ -+void LPCSetConfig(char LdnNumber, char Index, char data) -+{ -+ unsigned char *addr; -+ LPCEnterMBPnP(); // Enter IT8712 MB PnP mode -+ addr = LPC_KEY_ADDR; -+ *addr = 0x07; -+ addr = LPC_DATA_ADDR; -+ *addr = LdnNumber; -+ addr = LPC_KEY_ADDR; -+ *addr = Index; -+ addr = LPC_DATA_ADDR; -+ *addr = data; -+ -+ LPCExitMBPnP(); -+} -+ -+//unsigned char key[4] ; -+void LPCEnterMBPnP(void) -+{ -+ unsigned char *addr; -+ addr = LPC_KEY_ADDR; -+ unsigned char key[4] = {0x87, 0x01, 0x55, 0x55}; -+ -+ do { -+ *addr = key[0]; -+ *addr = key[1]; -+ *addr = key[2]; -+ *addr = key[3]; -+ }while(0); -+} -+ -+void LPCExitMBPnP(void) -+{ -+ unsigned char *addr; -+ addr = LPC_KEY_ADDR; -+ *addr = 0x02 ; -+ -+ addr = LPC_DATA_ADDR; -+ *addr = 0x02 ; -+} -+ -+int InitLPCInterface(void) -+{ -+ int i; -+ LPC_BUS_CTRL = 0xc0; -+ LPC_SERIAL_IRQ_CTRL = 0xc0; -+ -+ for(i=0;i<0x2000;i++) ; -+ -+ LPC_SERIAL_IRQ_CTRL = 0x80; -+ if (!SearchIT8712()) ; -+// while(1); -+ return 0; -+} -+ -+int SearchIT8712(void) -+{ -+ unsigned char Id1, Id2; -+ unsigned short Id; -+ unsigned char *addr; -+ -+ LPCEnterMBPnP(); -+ addr = LPC_KEY_ADDR; -+ *addr = 0x20 ; -+ addr = LPC_DATA_ADDR; -+ Id1 = *addr ; -+ -+ addr = LPC_KEY_ADDR; -+ *addr = 0x21 ; -+ addr = LPC_DATA_ADDR; -+ Id2 = *addr ; -+ -+ Id = (Id1 << 8) | Id2; -+ LPCExitMBPnP(); -+ -+ if (Id == 0x8712) -+ return 1; -+ else -+ return 0; -+} -+ -+#endif - ---- a/arch/arm/kernel/entry-armv.S -+++ b/arch/arm/kernel/entry-armv.S -@@ -18,6 +18,8 @@ - #include - #include - #include -+#include -+#include - #include - #include - ---- a/arch/arm/kernel/irq.c -+++ b/arch/arm/kernel/irq.c -@@ -40,6 +40,8 @@ - #include - #include - -+extern int fixup_irq(unsigned int irq); -+ - /* - * No architecture-specific irq_finish function defined in arm/arch/irqs.h. - */ -@@ -111,8 +113,11 @@ - asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs) - { - struct pt_regs *old_regs = set_irq_regs(regs); -- struct irq_desc *desc = irq_desc + irq; -+// struct irq_desc *desc = irq_desc + irq; -+ struct irq_desc *desc; - -+ irq = fixup_irq(irq); -+ desc = irq_desc + irq; - /* - * Some hardware gives randomly wrong interrupts. Rather - * than crashing, do something sensible. ---- a/arch/arm/kernel/process.c -+++ b/arch/arm/kernel/process.c -@@ -117,7 +117,7 @@ - void (*pm_idle)(void); - EXPORT_SYMBOL(pm_idle); - --void (*pm_power_off)(void); -+//void (*pm_power_off)(void); - EXPORT_SYMBOL(pm_power_off); - - void (*arm_pm_restart)(char str) = arm_machine_restart; -@@ -188,13 +188,37 @@ - - void machine_halt(void) - { -+ unsigned int reg_v; -+ -+ printk("arch_power_off\n"); -+ -+ reg_v = readl(IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04); -+ reg_v &= ~0x00000002; -+ reg_v |= 0x1; -+ mdelay(5); -+ // Power off -+ __raw_writel( reg_v, IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04); -+ - } - - - void machine_power_off(void) - { -- if (pm_power_off) -+ unsigned int reg_v; -+ -+// if (pm_power_off) -+ if (&pm_power_off!=NULL) - pm_power_off(); -+ -+ printk("arch_power_off\n"); -+ -+ reg_v = readl(IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04); -+ reg_v &= ~0x00000002; -+ reg_v |= 0x1; -+ mdelay(5); -+ // Power off -+ __raw_writel( reg_v, IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04); -+ - } - - void machine_restart(char * __unused) ---- a/arch/arm/kernel/time.c -+++ b/arch/arm/kernel/time.c -@@ -502,8 +502,13 @@ - - device_initcall(timer_init_sysfs); - -+extern unsigned int rtc_get_time_second(void); -+ - void __init time_init(void) - { -+#ifdef CONFIG_SL2312_RTC -+ xtime.tv_sec = rtc_get_time_second() ; -+#endif - #ifndef CONFIG_GENERIC_TIME - if (system_timer->offset == NULL) - system_timer->offset = dummy_gettimeoffset; ---- /dev/null -+++ b/arch/arm/mach-sl2312/Kconfig -@@ -0,0 +1,33 @@ -+ -+menu "SL2312" -+ -+config SL3516_ASIC -+ bool "SL3516 ASIC version" -+ depends on ARCH_SL2312 -+ help -+ This option to select AISC or FPGA -+config PCI -+ bool "SL2312 PCI" -+ depends on ARCH_SL2312 -+ help -+ This option to enable Storlink PCI controller -+ -+config SL2312_LPC -+ bool "SL2312 LPC" -+ depends on ARCH_SL2312 -+ help -+ This option to enable Low Pin Count controller -+ -+config SL2312_USB -+ bool "SL2312 USB" -+ depends on ARCH_SL2312 -+ help -+ This option to enable USB OTG host controller -+ -+config GEMINI_IPI -+ bool "Gemini IPI test" -+ depends on ARCH_SL2312 -+ help -+ Enable this option to test dual cpu Inter-Processor-Interrupt -+endmenu -+ ---- /dev/null -+++ b/arch/arm/mach-sl2312/Makefile -@@ -0,0 +1,16 @@ -+# -+# Makefile for the linux kernel. -+# -+ -+# Object file lists. -+ -+obj-y := arch.o irq.o mm.o time.o sl3516_device.o -+obj-m := -+obj-n := -+ -+ -+obj-$(CONFIG_PCI) += pci.o -+obj-$(CONFIG_SL2312_LPC) += lpc.o -+obj-$(CONFIG_SL2312_USB) += sl2312-otg.o # sl2312-otg-1.o -+obj-$(CONFIG_GEMINI_XOR_ACCE) += xor.o -+obj-$(CONFIG_GEMINI_IPI) += gemini_ipi.o ---- /dev/null -+++ b/arch/arm/mach-sl2312/Makefile.boot -@@ -0,0 +1,5 @@ -+ zreladdr-y := 0x00008000 -+params_phys-y := 0x00508100 -+#params_phys-y := 0x00008100 -+initrd_phys-y := 0x00800000 -+ ---- /dev/null -+++ b/arch/arm/mach-sl2312/arch.c -@@ -0,0 +1,72 @@ -+/* -+ * linux/arch/arm/mach-epxa10db/arch.c -+ * -+ * Copyright (C) 2000 Deep Blue Solutions Ltd -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+extern void sl2312_map_io(void); -+extern void sl2312_init_irq(void); -+extern unsigned long sl2312_gettimeoffset (void); -+extern void __init sl2312_time_init(void); -+ -+static struct sys_timer sl2312_timer = { -+ .init = sl2312_time_init, -+ .offset = sl2312_gettimeoffset, -+}; -+ -+static void __init -+sl2312_fixup(struct machine_desc *desc, struct tag *tags, -+ char **cmdline, struct meminfo *mi) -+{ -+ mi->nr_banks = 1; -+ mi->bank[0].start = 0; -+#ifdef CONFIG_GEMINI_IPI -+ mi->bank[0].size = (64*1024*1024); // 128M -+#else -+ mi->bank[0].size = (128*1024*1024); // 128M -+#endif -+ mi->bank[0].node = 0; -+} -+ -+/* MACHINE_START(SL2312, "GeminiA") -+ MAINTAINER("Storlink Semi") -+ BOOT_MEM(0x00000000, 0x90000000, 0xf0000000) -+ FIXUP(sl2312_fixup) -+ MAPIO(sl2312_map_io) -+ INITIRQ(sl2312_init_irq) -+ .timer = &sl2312_timer, -+MACHINE_END */ -+ -+MACHINE_START(SL2312, "GeminiA") -+ /* .phys_ram = 0x00000000, */ -+ .phys_io = 0x7fffc000, -+ .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc, -+ .boot_params = 0x100, -+ .fixup = sl2312_fixup, -+ .map_io = sl2312_map_io, -+ .init_irq = sl2312_init_irq, -+ .timer = &sl2312_timer, -+MACHINE_END ---- /dev/null -+++ b/arch/arm/mach-sl2312/gemini_ipi.c -@@ -0,0 +1,593 @@ -+/* -+ * FILE NAME sl_cir.c -+ * -+ * BRIEF MODULE DESCRIPTION -+ * IPI Driver for CPU1. -+ * -+ * Author: StorLink, Corp. -+ * Jason Lee -+ * -+ * Copyright 2002~2006 StorLink, Corp. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMit8712D TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMit8712D TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, writ8712 to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+ -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+ -+static int sl_ipi_debug = 1 ; -+#define DEB(x) if(sl_ipi_debug>=1) x -+ -+#define SRAM_PTR IO_ADDRESS(SL2312_SRAM_BASE) -+volatile JSCALE_REQ_T *req=(JSCALE_REQ_T*)SRAM_PTR; -+volatile JSCALE_RSP_T *rsp=(JSCALE_RSP_T*)(SRAM_PTR+0x20); -+ -+unsigned int jscale_status=0; -+ -+#define JSCALE_WAIT 0 -+#define XXXXXX_WAIT 1 -+#define MAX_WAIT_Q 8 -+wait_queue_head_t gemini_ipi_wait[MAX_WAIT_Q]; -+ -+#define DRAMCTL_DMA_CTL 0X20 -+#define DRAMCTL_DMA_SA 0X24 -+#define DRAMCTL_DMA_DA 0X28 -+#define DRAMCTL_DMA_CNT 0X2C -+#define MEMCPY_UNIT 0x40000 -+int hw_memcpy(const void *to, const void *from, unsigned int bytes) -+{ -+ unsigned int reg_a,reg_d; -+ int count = bytes,i=0; -+ -+ consistent_sync((unsigned int *)to, bytes, DMA_BIDIRECTIONAL); -+ consistent_sync((unsigned int *)from,bytes, DMA_TO_DEVICE); -+ -+ DEB(printk("hwmemcpy:count %d\n",count)); -+ while(count>0){ -+ // SA -+ reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_SA; -+ reg_d = (unsigned int )__virt_to_phys(from) + i*MEMCPY_UNIT; -+ DEB(printk("hwmemcpy:from 0x%08x\n",reg_d)); -+ writel(reg_d,reg_a); -+ // DA -+ reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_DA; -+ reg_d = (unsigned int )__virt_to_phys(to) + i*MEMCPY_UNIT; -+ writel(reg_d,reg_a); -+ DEB(printk("hwmemcpy:to 0x%08x\n",reg_d)); -+ // byte count -+ reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_CNT; -+ reg_d = (count>=MEMCPY_UNIT)?MEMCPY_UNIT:count; -+ writel(reg_d,reg_a); -+ // start DMA -+ reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_CTL; -+ writel(0x80000001,reg_a); -+ -+ do{ -+ cond_resched(); -+// msleep(4); -+ reg_d = readl(IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_CTL); -+ }while(reg_d&0x1); -+ -+ count -= MEMCPY_UNIT; -+ i++; -+ } -+ -+ return bytes; -+} -+ -+static irqreturn_t ipi_interrupt() -+{ -+ unsigned int id=getcpuid(),tmp; -+ -+ //dmac_inv_range(__phys_to_virt(SL2312_SRAM_BASE),__phys_to_virt(SHAREADDR)+0x2000); -+ -+ -+ // Clear Interrupt -+ if(id==CPU0) { -+ tmp = readl(CPU1_STATUS); -+ tmp &= ~CPU_IPI_BIT_MASK; -+ writel(tmp,CPU1_STATUS); -+ } -+ else{ -+ tmp = readl(CPU0_STATUS); -+ tmp &= ~CPU_IPI_BIT_MASK; -+ writel(tmp,CPU0_STATUS); -+ } -+ -+ // -+ DEB(printk("ipi interrupt:0x%x\n",rsp->status)); -+ switch(rsp->status){ -+ case JSCALE_STATUS_OK: -+ -+ break; -+ case JSCALE_UNKNOWN_MSG_TYPE: -+ -+ break; -+ case JSCALE_FAILED_FILE_SIZE: -+ -+ break; -+ case JSCALE_FAILED_MALLOC: -+ -+ break; -+ case JSCALE_FAILED_FORMAT: -+ -+ break; -+ case JSCALE_DECODE_ERROR: -+ -+ break; -+ -+ } -+ jscale_status = rsp->status; -+// wake_up(&gemini_ipi_wait[JSCALE_WAIT]); -+ -+ return IRQ_HANDLED; -+} -+ -+static int gemini_ipi_open(struct inode *inode, struct file *file) -+{ -+ DEB(printk("ipi open\n")); -+ return 0; -+} -+ -+ -+static int gemini_ipi_release(struct inode *inode, struct file *file) -+{ -+ DEB(printk("ipi release\n")); -+ return 0; -+} -+ -+ -+static int gemini_ipi_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ JSCALE_RSP_T tmp; -+ -+ switch(cmd) { -+ case GEMINI_IPI_JSCALE_REQ: -+ DEB(printk("ipi:ioctl jscale request %dX%d Q:%d\n",req->ScaledImageWidth,req->ScaledImageHeight,req->ScaledImageQuality)); -+ if (copy_from_user(req, (JSCALE_REQ_T *)arg, sizeof(JSCALE_REQ_T))) -+ return -EFAULT; -+ req->hdr.type = IPC_JSCALE_REQ_MSG; -+ req->hdr.length = sizeof(JSCALE_REQ_T); -+ req->input_location = CPU_1_DATA_OFFSET; -+ req->output_location = CPU_1_DATA_OFFSET; -+ break; -+ case GEMINI_IPI_JSCALE_STAT: -+ DEB(printk("ipi:ioctl jscale stat \n")); -+ if(jscale_status==JSCALE_BUSY){ // not yet -+ tmp.status = JSCALE_BUSY; -+ if (copy_to_user((JSCALE_RSP_T *)arg,&tmp, sizeof(JSCALE_RSP_T))) -+ return -EFAULT; -+ } -+ else{ // finish or error -+ if (copy_to_user((JSCALE_RSP_T *)arg,rsp, sizeof(JSCALE_RSP_T))) -+ return -EFAULT; -+ } -+ break; -+ default: -+ printk("IPI: Error IOCTL number\n"); -+ return -ENOIOCTLCMD; -+ } -+ -+ return 0; -+} -+ -+#define SRAM_SIZE 0x2000 -+static ssize_t gemini_ipi_write(struct file *file_p, const char *buf, size_t count, loff_t * ppos) -+{ -+ int i=0,tmp=0,j; -+ const char *ptr=(unsigned int)__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET); -+ DEB(printk("ipi:write 0x%x to 0x%x length:%d\n",&buf,ptr,count)); -+ memcpy(ptr,buf,count); -+ consistent_sync(ptr,count, DMA_TO_DEVICE); -+ //hw_memcpy(ptr,&buf,count); -+ -+/* if(count>SRAM_SIZE){ -+ for(i=0;i<(count/SRAM_SIZE);i++) -+ raid_memcpy(ptr+i*SRAM_SIZE,buf+i*SRAM_SIZE,SRAM_SIZE); -+ if(count%SRAM_SIZE) -+ raid_memcpy(ptr+i*SRAM_SIZE,buf+i*SRAM_SIZE,count%SRAM_SIZE); -+ } -+ else -+ raid_memcpy(ptr,buf,count); -+*/ -+ -+/* for(i=0;iSRAM_SIZE){ -+ for(i=0;i<(count/SRAM_SIZE);i++) -+ raid_memcpy(buf+i*SRAM_SIZE,p_mbox->message+i*SRAM_SIZE,SRAM_SIZE); -+ if(count%0xFFFF) -+ raid_memcpy(buf+i*SRAM_SIZE,p_mbox->message+i*SRAM_SIZE,length%SRAM_SIZE); -+ } -+ else -+ raid_memcpy(buf,p_mbox->message,length); -+*/ -+ return length; -+} -+ -+void do_mapping_read(struct address_space *mapping, -+ struct file_ra_state *_ra, -+ struct file *filp, -+ loff_t *ppos, -+ read_descriptor_t *desc, -+ read_actor_t actor) -+{ -+ struct inode *inode = mapping->host; -+ unsigned long index; -+ unsigned long end_index; -+ unsigned long offset; -+ unsigned long last_index; -+ unsigned long next_index; -+ unsigned long prev_index; -+ loff_t isize; -+ struct page *cached_page; -+ int error; -+ struct file_ra_state ra = *_ra; -+ -+ cached_page = NULL; -+ index = *ppos >> PAGE_CACHE_SHIFT; -+ next_index = index; -+ prev_index = ra.prev_page; -+ last_index = (*ppos + desc->count + PAGE_CACHE_SIZE-1) >> PAGE_CACHE_SHIFT; -+ offset = *ppos & ~PAGE_CACHE_MASK; -+ -+ isize = i_size_read(inode); -+ if (!isize) -+ goto out; -+ -+ end_index = (isize - 1) >> PAGE_CACHE_SHIFT; -+ for (;;) { -+ struct page *page; -+ unsigned long nr, ret; -+ -+ /* nr is the maximum number of bytes to copy from this page */ -+ nr = PAGE_CACHE_SIZE; -+ if (index >= end_index) { -+ if (index > end_index) -+ goto out; -+ nr = ((isize - 1) & ~PAGE_CACHE_MASK) + 1; -+ if (nr <= offset) { -+ goto out; -+ } -+ } -+ nr = nr - offset; -+ -+ cond_resched(); -+ if (index == next_index) -+ next_index = page_cache_readahead(mapping, &ra, filp, -+ index, last_index - index); -+ -+find_page: -+ page = find_get_page(mapping, index); -+ if (unlikely(page == NULL)) { -+ handle_ra_miss(mapping, &ra, index); -+ goto no_cached_page; -+ } -+ if (!PageUptodate(page)) -+ goto page_not_up_to_date; -+page_ok: -+ -+ /* If users can be writing to this page using arbitrary -+ * virtual addresses, take care about potential aliasing -+ * before reading the page on the kernel side. -+ */ -+ if (mapping_writably_mapped(mapping)) -+ flush_dcache_page(page); -+ -+ /* -+ * When (part of) the same page is read multiple times -+ * in succession, only mark it as accessed the first time. -+ */ -+ if (prev_index != index) -+ mark_page_accessed(page); -+ prev_index = index; -+ -+ /* -+ * Ok, we have the page, and it's up-to-date, so -+ * now we can copy it to user space... -+ * -+ * The actor routine returns how many bytes were actually used.. -+ * NOTE! This may not be the same as how much of a user buffer -+ * we filled up (we may be padding etc), so we can only update -+ * "pos" here (the actor routine has to update the user buffer -+ * pointers and the remaining count). -+ */ -+ ret = actor(desc, page, offset, nr); -+ offset += ret; -+ index += offset >> PAGE_CACHE_SHIFT; -+ offset &= ~PAGE_CACHE_MASK; -+ -+ page_cache_release(page); -+ if (ret == nr && desc->count) -+ continue; -+ goto out; -+ -+page_not_up_to_date: -+ /* Get exclusive access to the page ... */ -+ lock_page(page); -+ -+ /* Did it get unhashed before we got the lock? */ -+ if (!page->mapping) { -+ unlock_page(page); -+ page_cache_release(page); -+ continue; -+ } -+ -+ /* Did somebody else fill it already? */ -+ if (PageUptodate(page)) { -+ unlock_page(page); -+ goto page_ok; -+ } -+ -+readpage: -+ /* Start the actual read. The read will unlock the page. */ -+ error = mapping->a_ops->readpage(filp, page); -+ -+ if (unlikely(error)) -+ goto readpage_error; -+ -+ if (!PageUptodate(page)) { -+ lock_page(page); -+ if (!PageUptodate(page)) { -+ if (page->mapping == NULL) { -+ /* -+ * invalidate_inode_pages got it -+ */ -+ unlock_page(page); -+ page_cache_release(page); -+ goto find_page; -+ } -+ unlock_page(page); -+ error = -EIO; -+ goto readpage_error; -+ } -+ unlock_page(page); -+ } -+ -+ /* -+ * i_size must be checked after we have done ->readpage. -+ * -+ * Checking i_size after the readpage allows us to calculate -+ * the correct value for "nr", which means the zero-filled -+ * part of the page is not copied back to userspace (unless -+ * another truncate extends the file - this is desired though). -+ */ -+ isize = i_size_read(inode); -+ end_index = (isize - 1) >> PAGE_CACHE_SHIFT; -+ if (unlikely(!isize || index > end_index)) { -+ page_cache_release(page); -+ goto out; -+ } -+ -+ /* nr is the maximum number of bytes to copy from this page */ -+ nr = PAGE_CACHE_SIZE; -+ if (index == end_index) { -+ nr = ((isize - 1) & ~PAGE_CACHE_MASK) + 1; -+ if (nr <= offset) { -+ page_cache_release(page); -+ goto out; -+ } -+ } -+ nr = nr - offset; -+ goto page_ok; -+ -+readpage_error: -+ /* UHHUH! A synchronous read error occurred. Report it */ -+ desc->error = error; -+ page_cache_release(page); -+ goto out; -+ -+no_cached_page: -+ /* -+ * Ok, it wasn't cached, so we need to create a new -+ * page.. -+ */ -+ if (!cached_page) { -+ cached_page = page_cache_alloc_cold(mapping); -+ if (!cached_page) { -+ desc->error = -ENOMEM; -+ goto out; -+ } -+ } -+ error = add_to_page_cache_lru(cached_page, mapping, -+ index, GFP_KERNEL); -+ if (error) { -+ if (error == -EEXIST) -+ goto find_page; -+ desc->error = error; -+ goto out; -+ } -+ page = cached_page; -+ cached_page = NULL; -+ goto readpage; -+ } -+ -+out: -+ *_ra = ra; -+ -+ *ppos = ((loff_t) index << PAGE_CACHE_SHIFT) + offset; -+ if (cached_page) -+ page_cache_release(cached_page); -+ if (filp) -+ file_accessed(filp); -+} -+ -+int ipi_send_actor(read_descriptor_t * desc, struct page *page, unsigned long offset, unsigned long size) -+{ -+ ssize_t written; -+ unsigned long count = desc->count; -+ struct file *file = desc->arg.data; -+ unsigned int *ptr_to=(unsigned int)__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET) + desc->written; -+ void *ptr_from; -+ -+ if (size > count) -+ size = count; -+ -+ ptr_from = page_address(page)+offset; -+ written = memcpy(ptr_to,ptr_from,size); -+ -+ if (written < 0) { -+ desc->error = written; -+ written = 0; -+ } -+ desc->count = count - written; -+ desc->written += written; -+ return written; -+} -+ -+ssize_t gemini_ipi_sendfile(struct file *in_file, loff_t *ppos, -+ size_t count, read_actor_t actor, void *TARGET) -+{ -+ read_descriptor_t desc; -+ -+ if (!count) -+ return 0; -+ -+ desc.written = 0; -+ desc.count = count; -+ desc.arg.data = TARGET; -+ desc.error = 0; -+ -+ do_mapping_read(in_file->f_mapping,&in_file->f_ra,in_file, ppos, &desc, ipi_send_actor); -+ -+ if (desc.written) -+ return desc.written; -+ return desc.error; -+} -+static struct file_operations gemini_ipi_fops = { -+ .owner = THIS_MODULE, -+ .ioctl = gemini_ipi_ioctl, -+ .open = gemini_ipi_open, -+ .release= gemini_ipi_release, -+ .write = gemini_ipi_write, -+ .read = gemini_ipi_read, -+ .sendfile = gemini_ipi_sendfile, -+}; -+ -+#ifndef STORLINK_IPI -+#define STORLINK_IPI 242 // Documents/devices.txt suggest to use 240~255 for local driver!! -+#endif -+ -+static struct miscdevice gemini_ipi_miscdev = -+{ -+ STORLINK_IPI, -+ "slave_ipc", -+ &gemini_ipi_fops -+}; -+ -+int __init sl_ipi_init(void) -+{ -+ -+ printk("Gemini IPI Driver Initialization...\n"); -+ printk("REQ Head :0x%x(phy:0x%x)\n",(unsigned int)req,(unsigned int)SL2312_SRAM_BASE); -+ printk("RSP Head :0x%x(phy:0x%x)\n",(unsigned int)rsp,(unsigned int)SL2312_SRAM_BASE+0x20); -+ printk("Data buff:0x%x(phy:0x%x)\n",__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET),CPU_1_MEM_BASE+CPU_1_DATA_OFFSET); -+ -+ misc_register(&gemini_ipi_miscdev); -+ -+ if (request_irq(IRQ_CPU0_IP_IRQ_OFFSET, ipi_interrupt, SA_INTERRUPT, "ipi", NULL)) -+ printk("Error: Register IRQ for Storlink IPI failed\n"); -+ -+ return 0; -+} -+ -+void __exit sl_ipi_exit(void) -+{ -+ -+} -+ -+module_init(sl_ipi_init); -+module_exit(sl_ipi_exit); -+ -+MODULE_AUTHOR("Jason Lee "); -+MODULE_DESCRIPTION("Storlink IPI driver"); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/arch/arm/mach-sl2312/hw_xor.h -@@ -0,0 +1,573 @@ -+/* -+* linux/include/asm-arm/xor.h -+* -+* Copyright (C) 2001 Storlink Semi. -+* Jason Lee -+* -+*/ -+#include -+#include -+//#include -+ -+#undef BIG_ENDIAN -+#define CPU 0 -+#define DMA 1 -+ -+#define DESC_NO 8 -+#define TX_DESC_NUM DESC_NO -+#define RX_DESC_NUM DESC_NO -+ -+#define RAID_BASE_ADDR IO_ADDRESS(SL2312_RAID_BASE) -+ -+#define SRAM_PAR_0k 0 -+#define SRAM_PAR_4k 1 -+#define SRAM_PAR_8k 2 -+#define SRAM_PAR_16k 3 -+#define SRAM_PAR_SIZE SRAM_PAR_8k -+ -+#define RUNNING 0x1 -+#define COMPLETE 0x2 -+#define ERROR 0x4 -+ -+#define CMD_XOR 0x0 -+#define CMD_FILL 0x1 -+#define CMD_CPY 0x3 -+#define CMD_CHK 0x4 -+ -+enum RAID_DMA_REGISTER { -+ RAID_DMA_DEVICE_ID = 0xff00, -+ RAID_DMA_STATUS = 0xff04, -+ RAID_FCHDMA_CTRL = 0xff08, -+ RAID_FCHDMA_FIRST_DESC = 0xff0C, -+ RAID_FCHDMA_CURR_DESC = 0xff10, -+ RAID_STRDMA_CTRL = 0xff14, -+ RAID_STRDMA_FIRST_DESC = 0xff18, -+ RAID_STRDMA_CURR_DESC = 0xff1C, -+ RAID_TX_FLG_REG = 0xff24, -+ RAID_RX_FLG_REG = 0xff34, -+ RAID_PCR = 0xff50, -+ SMC_CMD_REG = 0xff60, -+ SMC_STATUS_REG = 0xff64 -+ }; -+ -+enum RAID_FUNC_MODE { -+ RAID_XOR = 0, -+ RAID_MIX = 2, -+ RAID_SRAM = 3, -+ RAID_ENDIAN = 4, -+ RAID_MEM_BLK = 5, -+ RAID_MEM2MEM = 7, -+ RAID_BUF_SIZE = 8, -+ RAID_ERR_TEST = 9, -+ RAID_BURST = 10, -+ RAID_BUS = 11 -+ }; -+ -+typedef struct reg_info { -+ int mask; -+ char err[32]; -+ int offset; -+} REG_INFO; -+ -+/********************************************************/ -+/* the definition of RAID DMA Module Register */ -+/********************************************************/ -+typedef union -+{ -+ unsigned int bit32; -+ struct bits_ff00 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int : 8; -+ unsigned int teytPerr : 4; /* define protocol error under tsPErrI*/ -+ unsigned int reytPerr : 14; /* define protocol error under rsPErrI */ -+ unsigned int device_id : 12; -+ unsigned int revision_id : 4; -+ #else -+ unsigned int revision_id : 4; -+ unsigned int device_id : 12; -+ unsigned int reytPerr : 14; /* define protocol error under rsPErrI */ -+ unsigned int teytPerr : 4; /* define protocol error under tsPErrI*/ -+ unsigned int : 8; -+ #endif -+ } bits; -+} RAID_DMA_DEVICE_ID_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bits_ff04 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int tsFinishI : 1; /* owner bit error interrupt */ -+ unsigned int tsDErrI : 1; /* AHB bus error interrupt */ -+ unsigned int tsPErrI : 1; /* RAID XOR fetch descriptor protocol error interrupt */ -+ unsigned int tsEODI : 1; /* RAID XOR fetch DMA end of descriptor interrupt */ -+ unsigned int tsEOFI : 1; /* RAID XOR fetch DMA end of frame interrupt */ -+ unsigned int rsFinishI : 1; /* owner bit error interrupt */ -+ unsigned int rsDErrI : 1; /* AHB bus error while RAID XOR store interrupt */ -+ unsigned int rsPErrI : 1; /* RAID XOR store descriptor protocol error interrupt */ -+ unsigned int rsEODI : 1; /* RAID XOR store DMA end of descriptor interrupt */ -+ unsigned int rsEOFI : 1; /* RAID XOR store DMA end of frame interrupt */ -+ unsigned int inter : 8; /* pattern check error interrupt */ -+ unsigned int : 5; -+ unsigned int Loopback : 1; /* loopback */ -+ unsigned int intEnable : 8; /*pattern check error interrupt enable */ -+ #else -+ unsigned int intEnable : 8; /*pattern check error interrupt enable */ -+ unsigned int Loopback : 1; /* loopback */ -+ unsigned int : 5; -+ unsigned int inter : 8; /* pattern check error interrupt */ -+ unsigned int rsEOFI : 1; /* RAID XOR store DMA end of frame interrupt */ -+ unsigned int rsEODI : 1; /* RAID XOR store DMA end of descriptor interrupt */ -+ unsigned int rsPErrI : 1; /* RAID XOR store descriptor protocol error interrupt */ -+ unsigned int rsDErrI : 1; /* AHB bus error while RAID XOR store interrupt */ -+ unsigned int rsFinishI : 1; /* owner bit error interrupt */ -+ unsigned int tsEOFI : 1; /* RAID XOR fetch DMA end of frame interrupt */ -+ unsigned int tsEODI : 1; /* RAID XOR fetch DMA end of descriptor interrupt */ -+ unsigned int tsPErrI : 1; /* RAID XOR fetch descriptor protocol error interrupt */ -+ unsigned int tsDErrI : 1; /* AHB bus error interrupt */ -+ unsigned int tsFinishI : 1; /* owner bit error interrupt */ -+ #endif -+ } bits; -+} RAID_DMA_STATUS_T; -+ -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bits_ff08 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int td_start : 1; /* Start DMA transfer */ -+ unsigned int td_continue : 1; /* Continue DMA operation */ -+ unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int : 1; -+ unsigned int td_prot : 4; /* DMA protection control */ -+ unsigned int td_burst_size : 2; /* DMA max burst size for every AHB request */ -+ unsigned int td_bus : 2; /* peripheral bus width */ -+ unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int : 14; -+ #else -+ unsigned int : 14; -+ unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int td_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */ -+ unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */ -+ unsigned int td_prot : 4; /* TxDMA protection control */ -+ unsigned int : 1; -+ unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int td_continue : 1; /* Continue DMA operation */ -+ unsigned int td_start : 1; /* Start DMA transfer */ -+ #endif -+ } bits; -+} RAID_TXDMA_CTRL_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bits_ff0c -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int td_first_des_ptr : 28;/* first descriptor address */ -+ unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */ -+ unsigned int : 3; -+ #else -+ unsigned int : 3; -+ unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */ -+ unsigned int td_first_des_ptr : 28;/* first descriptor address */ -+ #endif -+ } bits; -+} RAID_TXDMA_FIRST_DESC_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bits_ff10 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int ndar : 28; /* next descriptor address */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int : 1; -+ unsigned int sof_eof : 2; -+ #else -+ unsigned int sof_eof : 2; -+ unsigned int : 1; -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int ndar : 28; /* next descriptor address */ -+ #endif -+ } bits; -+} RAID_TXDMA_CURR_DESC_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bits_ff14 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int rd_start : 1; /* Start DMA transfer */ -+ unsigned int rd_continue : 1; /* Continue DMA operation */ -+ unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int : 1; -+ unsigned int rd_prot : 4; /* DMA protection control */ -+ unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */ -+ unsigned int rd_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */ -+ unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int : 14; -+ #else -+ unsigned int : 14; -+ unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int rd_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */ -+ unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */ -+ unsigned int rd_prot : 4; /* DMA protection control */ -+ unsigned int : 1; -+ unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int rd_continue : 1; /* Continue DMA operation */ -+ unsigned int rd_start : 1; /* Start DMA transfer */ -+ #endif -+ } bits; -+} RAID_RXDMA_CTRL_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bits_ff18 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int rd_first_des_ptr : 28;/* first descriptor address */ -+ unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */ -+ unsigned int : 3; -+ #else -+ unsigned int : 3; -+ unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */ -+ unsigned int rd_first_des_ptr : 28;/* first descriptor address */ -+ #endif -+ } bits; -+} RAID_RXDMA_FIRST_DESC_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bits_ff1c -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int ndar : 28; /* next descriptor address */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */ -+ unsigned int sof_eof : 2; -+ #else -+ unsigned int sof_eof : 2; -+ unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int ndar : 28; /* next descriptor address */ -+ #endif -+ } bits; -+} RAID_RXDMA_CURR_DESC_T; -+ -+typedef union -+{ -+ unsigned int bit32; -+ struct bits_ff50 -+ { -+ unsigned int pat : 32; /* data for pattern check */ -+ } bits; -+} RAID_PACR_T; -+ -+/******************************************************/ -+/* the definition of DMA Descriptor Register */ -+/******************************************************/ -+typedef struct raid_descriptor_t -+{ -+ union func_ctrl_t -+ { -+ unsigned int bit32; -+ struct bits_0000 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int own : 1; /* owner bit */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int raid_ctrl_status : 7; /* pass RAID XOR fetch/store control status to CPU */ -+ unsigned int desc_cnt : 6; -+ unsigned int buffer_size : 16; /* transfer buffer size associated with current description*/ -+ #else -+ unsigned int buffer_size : 16; /* transfer buffer size associated with current description*/ -+ unsigned int desc_cnt : 6; -+ unsigned int raid_ctrl_status : 7; /* pass RAID XOR fetch/store control status to CPU */ -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int own : 1; /* owner bit */ -+ #endif -+ } bits; -+ } func_ctrl; -+ -+ union flg_status_t -+ { -+ unsigned int bits32; -+ struct bit_004 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int bcc : 16; -+ unsigned int : 13 -+ unsigned int mode : 3; -+ #else -+ unsigned int mode : 3; -+ unsigned int : 13; -+ unsigned int bcc : 16; -+ #endif -+ } bits_cmd_status; -+ } flg_status; //Sanders -+ -+ unsigned int buf_addr; -+ -+ union next_desc_addr_t -+ { -+ unsigned int bits32; -+ struct bits_000c -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int ndar : 28; /* next descriptor address */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int : 1; -+ unsigned int sof_eof : 2; /* the position of the descriptor in chain */ -+ #else -+ unsigned int sof_eof : 2; /* the position of the descriptor in chain */ -+ unsigned int : 1; -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int ndar : 28; /* next descriptor address */ -+ #endif -+ } bits; -+ } next_desc_addr; -+} RAID_DESCRIPTOR_T; -+ -+/******************************************************/ -+/* the offset of RAID SMC register */ -+/******************************************************/ -+enum RAID_SMC_REGISTER { -+ RAID_SMC_CMD_REG = 0xff60, -+ RAID_SMC_STATUS_REG = 0xff64 -+ }; -+ -+/******************************************************/ -+/* the definition of RAID SMC module register */ -+/******************************************************/ -+typedef union -+{ -+ unsigned int bits32; -+ struct bits_ff60 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int pat_mode : 2; /* partition mode selection */ -+ unsigned int : 14; -+ unsigned int device_id : 12; -+ unsigned int revision_id : 4; -+ #else -+ unsigned int revision_id : 4; -+ unsigned int device_id : 12; -+ unsigned int : 14; -+ unsigned int pat_mode : 2; /* partition mode selection */ -+ #endif -+ } bits; -+} RAID_SMC_CMD; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bits_ff64 -+ { -+ #ifdef BIG_ENDIAN -+ unsigned int addr_err1 : 1; /* address is out of range for controller 1 */ -+ unsigned int ahb_err1 : 1; /* AHB bus error for controller 1 */ -+ unsigned int : 14; -+ unsigned int addr_err2 : 1; /* address is out of range for controller 2 */ -+ unsigned int ahb_err2 : 1; /* AHB bus error for controller 2 */ -+ unsigned int : 14; -+ #else -+ unsigned int : 14; -+ unsigned int ahb_err2 : 1; /* AHB bus error for controller 2 */ -+ unsigned int addr_err2 : 1; /* address is out of range for controller 2 */ -+ unsigned int : 14; -+ unsigned int ahb_err1 : 1; /* AHB bus error for controller 1 */ -+ unsigned int addr_err1 : 1; /* address is out of range for controller 1 */ -+ #endif -+ } bits; -+} RAID_SMC_STATUS; -+ -+typedef struct RAID_S -+{ -+ const char *device_name; -+ wait_queue_head_t wait; -+ unsigned int busy; -+ int irq; -+ unsigned int status; -+ RAID_DESCRIPTOR_T *tx_desc; /* point to virtual TX descriptor address */ -+ RAID_DESCRIPTOR_T *rx_desc; /* point ot virtual RX descriptor address */ -+ RAID_DESCRIPTOR_T *tx_cur_desc; /* current TX descriptor */ -+ RAID_DESCRIPTOR_T *rx_cur_desc; /* current RX descriptor */ -+ RAID_DESCRIPTOR_T *tx_finished_desc; -+ RAID_DESCRIPTOR_T *rx_finished_desc; -+ RAID_DESCRIPTOR_T *tx_first_desc; -+ RAID_DESCRIPTOR_T *rx_first_desc; -+ -+// unsigned int *tx_buf[TX_DESC_NUM]; -+ unsigned int *rx_desc_dma; // physical address of rx_descript -+ unsigned int *tx_desc_dma; // physical address of tx_descript -+ unsigned int *rx_bufs_dma; -+ unsigned int *tx_bufs_dma; -+ -+} RAID_T; -+ -+struct reg_ioctl -+{ -+ unsigned int reg_addr; -+ unsigned int val_in; -+ unsigned int val_out; -+}; -+ -+typedef struct dma_ctrl { -+ int sram; -+ int prot; -+ int burst; -+ int bus; -+ int endian; -+ int mode; -+} DMA_CTRL; -+ -+ -+#ifdef XOR_SW_FILL_IN -+ -+#define __XOR(a1, a2) a1 ^= a2 -+ -+#define GET_BLOCK_2(dst) \ -+ __asm__("ldmia %0, {%1, %2}" \ -+ : "=r" (dst), "=r" (a1), "=r" (a2) \ -+ : "0" (dst)) -+ -+#define GET_BLOCK_4(dst) \ -+ __asm__("ldmia %0, {%1, %2, %3, %4}" \ -+ : "=r" (dst), "=r" (a1), "=r" (a2), "=r" (a3), "=r" (a4) \ -+ : "0" (dst)) -+ -+#define XOR_BLOCK_2(src) \ -+ __asm__("ldmia %0!, {%1, %2}" \ -+ : "=r" (src), "=r" (b1), "=r" (b2) \ -+ : "0" (src)); \ -+ __XOR(a1, b1); __XOR(a2, b2); -+ -+#define XOR_BLOCK_4(src) \ -+ __asm__("ldmia %0!, {%1, %2, %3, %4}" \ -+ : "=r" (src), "=r" (b1), "=r" (b2), "=r" (b3), "=r" (b4) \ -+ : "0" (src)); \ -+ __XOR(a1, b1); __XOR(a2, b2); __XOR(a3, b3); __XOR(a4, b4) -+ -+#define PUT_BLOCK_2(dst) \ -+ __asm__ __volatile__("stmia %0!, {%2, %3}" \ -+ : "=r" (dst) \ -+ : "0" (dst), "r" (a1), "r" (a2)) -+ -+#define PUT_BLOCK_4(dst) \ -+ __asm__ __volatile__("stmia %0!, {%2, %3, %4, %5}" \ -+ : "=r" (dst) \ -+ : "0" (dst), "r" (a1), "r" (a2), "r" (a3), "r" (a4)) -+ -+static void -+xor_arm4regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) -+{ -+ unsigned int lines = bytes / sizeof(unsigned long) / 4; -+ register unsigned int a1 __asm__("r4"); -+ register unsigned int a2 __asm__("r5"); -+ register unsigned int a3 __asm__("r6"); -+ register unsigned int a4 __asm__("r7"); -+ register unsigned int b1 __asm__("r8"); -+ register unsigned int b2 __asm__("r9"); -+ register unsigned int b3 __asm__("ip"); -+ register unsigned int b4 __asm__("lr"); -+ -+ do { -+ GET_BLOCK_4(p1); -+ XOR_BLOCK_4(p2); -+ PUT_BLOCK_4(p1); -+ } while (--lines); -+} -+ -+static void -+xor_arm4regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, -+ unsigned long *p3) -+{ -+ unsigned int lines = bytes / sizeof(unsigned long) / 4; -+ register unsigned int a1 __asm__("r4"); -+ register unsigned int a2 __asm__("r5"); -+ register unsigned int a3 __asm__("r6"); -+ register unsigned int a4 __asm__("r7"); -+ register unsigned int b1 __asm__("r8"); -+ register unsigned int b2 __asm__("r9"); -+ register unsigned int b3 __asm__("ip"); -+ register unsigned int b4 __asm__("lr"); -+ -+ do { -+ GET_BLOCK_4(p1); -+ XOR_BLOCK_4(p2); -+ XOR_BLOCK_4(p3); -+ PUT_BLOCK_4(p1); -+ } while (--lines); -+} -+ -+static void -+xor_arm4regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, -+ unsigned long *p3, unsigned long *p4) -+{ -+ unsigned int lines = bytes / sizeof(unsigned long) / 2; -+ register unsigned int a1 __asm__("r8"); -+ register unsigned int a2 __asm__("r9"); -+ register unsigned int b1 __asm__("ip"); -+ register unsigned int b2 __asm__("lr"); -+ -+ do { -+ GET_BLOCK_2(p1); -+ XOR_BLOCK_2(p2); -+ XOR_BLOCK_2(p3); -+ XOR_BLOCK_2(p4); -+ PUT_BLOCK_2(p1); -+ } while (--lines); -+} -+ -+static void -+xor_arm4regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, -+ unsigned long *p3, unsigned long *p4, unsigned long *p5) -+{ -+ unsigned int lines = bytes / sizeof(unsigned long) / 2; -+ register unsigned int a1 __asm__("r8"); -+ register unsigned int a2 __asm__("r9"); -+ register unsigned int b1 __asm__("ip"); -+ register unsigned int b2 __asm__("lr"); -+ -+ do { -+ GET_BLOCK_2(p1); -+ XOR_BLOCK_2(p2); -+ XOR_BLOCK_2(p3); -+ XOR_BLOCK_2(p4); -+ XOR_BLOCK_2(p5); -+ PUT_BLOCK_2(p1); -+ } while (--lines); -+} -+#endif //XOR_SW_FILL_IN -+ ---- /dev/null -+++ b/arch/arm/mach-sl2312/irq.c -@@ -0,0 +1,202 @@ -+/* -+ * linux/arch/arm/mach-epxa10db/irq.c -+ * -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_PCI -+#include -+#endif -+ -+int fixup_irq(unsigned int irq) -+{ -+#ifdef CONFIG_PCI -+ if (irq == IRQ_PCI) { -+ return sl2312_pci_get_int_src(); -+ } -+#endif -+ return irq; -+} -+ -+static void sl2312_ack_irq(unsigned int irq) -+{ -+ __raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+} -+ -+static void sl2312_mask_irq(unsigned int irq) -+{ -+ unsigned int mask; -+ -+#ifdef CONFIG_PCI -+ if (irq >= PCI_IRQ_OFFSET) -+ { -+ mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ mask &= ~IRQ_PCI_MASK ; -+ __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ sl2312_pci_mask_irq(irq - PCI_IRQ_OFFSET); -+ } -+ else -+#endif -+ if(irq >= FIQ_OFFSET) -+ { -+ mask = __raw_readl(FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ mask &= ~(1 << (irq - FIQ_OFFSET)); -+ __raw_writel(mask, FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ } -+ else -+ { -+ mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ mask &= ~(1 << irq); -+ __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ } -+ -+} -+ -+static void sl2312_unmask_irq(unsigned int irq) -+{ -+ unsigned int mask; -+ -+#ifdef CONFIG_PCI -+ if (irq >= PCI_IRQ_OFFSET) -+ { -+ mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ mask |= IRQ_PCI_MASK ; -+ __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ sl2312_pci_unmask_irq(irq - PCI_IRQ_OFFSET); -+ } -+ else -+#endif -+ if(irq >= FIQ_OFFSET) -+ { -+ mask = __raw_readl(FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ mask |= (1 << (irq - FIQ_OFFSET)); -+ __raw_writel(mask, FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ } -+ else -+ { -+ mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ mask |= (1 << irq); -+ __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ } -+} -+ -+static struct irq_chip sl2312_level_irq = { -+ .ack = sl2312_mask_irq, -+ .mask = sl2312_mask_irq, -+ .unmask = sl2312_unmask_irq, -+// .set_type = ixp4xx_set_irq_type, -+}; -+ -+static struct irq_chip sl2312_edge_irq = { -+ .ack = sl2312_ack_irq, -+ .mask = sl2312_mask_irq, -+ .unmask = sl2312_unmask_irq, -+// .set_type = ixp4xx_set_irq_type, -+}; -+ -+static struct resource irq_resource = { -+ .name = "irq_handler", -+ .start = IO_ADDRESS(SL2312_INTERRUPT_BASE), -+ .end = IO_ADDRESS(FIQ_STATUS(SL2312_INTERRUPT_BASE))+4, -+}; -+ -+void __init sl2312_init_irq(void) -+{ -+ unsigned int i, mode, level; -+ -+ request_resource(&iomem_resource, &irq_resource); -+ -+ for (i = 0; i < NR_IRQS; i++) -+ { -+ if((i>=IRQ_TIMER1 && i<=IRQ_TIMER3)||(i>=IRQ_SERIRQ0 && i<=IRQ_SERIRQ_MAX)) -+ { -+ set_irq_chip(i, &sl2312_edge_irq); -+ set_irq_handler(i, handle_edge_irq); -+ } -+ else -+ { -+ set_irq_chip(i, &sl2312_level_irq); -+ set_irq_handler(i,handle_level_irq); -+ } -+ set_irq_flags(i, IRQF_VALID | IRQF_PROBE); -+ } -+ -+ /* Disable all interrupt */ -+ __raw_writel(0,IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ __raw_writel(0,FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ -+ /* Set interrupt mode */ -+ /* emac & ipsec type is level trigger and high active */ -+ mode = __raw_readl(IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ level = __raw_readl(IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ -+ mode &= ~IRQ_GMAC0_MASK; -+ level &= ~IRQ_GMAC0_MASK; -+ -+ mode &= ~IRQ_GMAC1_MASK; -+ level &= ~IRQ_GMAC1_MASK; -+ -+ mode &= ~IRQ_IPSEC_MASK; -+ level &= ~IRQ_IPSEC_MASK; -+ -+ // for IDE0,1, high active and level trigger -+ mode &= ~IRQ_IDE0_MASK; -+ level &= ~IRQ_IDE0_MASK; -+ mode &= ~IRQ_IDE1_MASK; -+ level &= ~IRQ_IDE1_MASK; -+ -+ -+ // for PCI, high active and level trigger -+ mode &= ~IRQ_PCI_MASK; -+ level &= ~IRQ_PCI_MASK; -+ -+ // for USB, high active and level trigger -+ mode &= ~IRQ_USB0_MASK; -+ level &= ~IRQ_USB0_MASK; -+ -+ mode &= ~IRQ_USB1_MASK; -+ level &= ~IRQ_USB1_MASK; -+ -+ // for LPC, high active and edge trigger -+ mode |= 0xffff0000; -+ level &= 0x0000ffff; -+ -+ // for GPIO, high active and level trigger -+ mode &= ~(IRQ_GPIO_MASK); -+ level &= ~(IRQ_GPIO_MASK); -+ -+ mode &= ~(IRQ_GPIO1_MASK); -+ level &= ~(IRQ_GPIO1_MASK); -+ -+ mode &= ~(IRQ_GPIO2_MASK); -+ level &= ~(IRQ_GPIO2_MASK); -+ -+ __raw_writel(mode,IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ __raw_writel(level,IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))); -+ -+} ---- /dev/null -+++ b/arch/arm/mach-sl2312/lpc.c -@@ -0,0 +1,125 @@ -+/* -+ * -+ * BRIEF MODULE DESCRIPTION -+ * ITE Semi IT8712 Super I/O functions. -+ * -+ * Copyright 2001 MontaVista Software Inc. -+ * Author: MontaVista Software, Inc. -+ * ppopov@mvista.com or source@mvista.com -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifndef TRUE -+#define TRUE 1 -+#endif -+ -+#ifndef FALSE -+#define FALSE 0 -+#endif -+ -+ -+// MB PnP configuration register -+#define LPC_KEY_ADDR (IO_ADDRESS(SL2312_LPC_IO_BASE) + 0x2e) -+#define LPC_DATA_ADDR (IO_ADDRESS(SL2312_LPC_IO_BASE) + 0x2f) -+ -+#define LPC_BUS_CTRL *(volatile unsigned char*) (IO_ADDRESS(SL2312_LPC_HOST_BASE) + 0) -+#define LPC_BUS_STATUS *(volatile unsigned char*) (IO_ADDRESS(SL2312_LPC_HOST_BASE) + 2) -+#define LPC_SERIAL_IRQ_CTRL *(volatile unsigned char*) (IO_ADDRESS(SL2312_LPC_HOST_BASE) + 4) -+ -+int it8712_exist; -+ -+static void LPCEnterMBPnP(void) -+{ -+ int i; -+ unsigned char key[4] = {0x87, 0x01, 0x55, 0x55}; -+ -+ for (i = 0; i<4; i++) -+ outb(key[i], LPC_KEY_ADDR); -+ -+} -+ -+static void LPCExitMBPnP(void) -+{ -+ outb(0x02, LPC_KEY_ADDR); -+ outb(0x02, LPC_DATA_ADDR); -+} -+ -+void LPCSetConfig(char LdnNumber, char Index, char data) -+{ -+ LPCEnterMBPnP(); // Enter IT8712 MB PnP mode -+ outb(0x07, LPC_KEY_ADDR); -+ outb(LdnNumber, LPC_DATA_ADDR); -+ outb(Index, LPC_KEY_ADDR); -+ outb(data, LPC_DATA_ADDR); -+ LPCExitMBPnP(); -+} -+ -+char LPCGetConfig(char LdnNumber, char Index) -+{ -+ char rtn; -+ -+ LPCEnterMBPnP(); // Enter IT8712 MB PnP mode -+ outb(0x07, LPC_KEY_ADDR); -+ outb(LdnNumber, LPC_DATA_ADDR); -+ outb(Index, LPC_KEY_ADDR); -+ rtn = inb(LPC_DATA_ADDR); -+ LPCExitMBPnP(); -+ return rtn; -+} -+ -+static int SearchIT8712(void) -+{ -+ unsigned char Id1, Id2; -+ unsigned short Id; -+ -+ LPCEnterMBPnP(); -+ outb(0x20, LPC_KEY_ADDR); /* chip id byte 1 */ -+ Id1 = inb(LPC_DATA_ADDR); -+ outb(0x21, LPC_KEY_ADDR); /* chip id byte 2 */ -+ Id2 = inb(LPC_DATA_ADDR); -+ Id = (Id1 << 8) | Id2; -+ LPCExitMBPnP(); -+ if (Id == 0x8712) -+ return TRUE; -+ else -+ return FALSE; -+} -+ -+int InitLPCInterface(void) -+{ -+ LPC_BUS_CTRL = 0xc0; -+ LPC_SERIAL_IRQ_CTRL = 0xc0; -+ mdelay(1); // wait for 1 serial IRQ cycle -+ LPC_SERIAL_IRQ_CTRL = 0x80; -+ it8712_exist = SearchIT8712(); -+ printk("IT8712 %s exist\n", it8712_exist?"":"doesn't"); -+ return 0; -+} -+ -+//__initcall(InitLPCInterface); ---- /dev/null -+++ b/arch/arm/mach-sl2312/mm.c -@@ -0,0 +1,80 @@ -+/* -+ * linux/arch/arm/mach-epxa10db/mm.c -+ * -+ * MM routines for Altera'a Epxa10db board -+ * -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* Page table mapping for I/O region */ -+static struct map_desc sl2312_io_desc[] __initdata = { -+#ifdef CONFIG_GEMINI_IPI -+{__phys_to_virt(CPU_1_MEM_BASE), __phys_to_pfn(CPU_1_MEM_BASE), SZ_64M, MT_MEMORY}, -+#endif -+{IO_ADDRESS(SL2312_SRAM_BASE), __phys_to_pfn(SL2312_SRAM_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_DRAM_CTRL_BASE), __phys_to_pfn(SL2312_DRAM_CTRL_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_GLOBAL_BASE), __phys_to_pfn(SL2312_GLOBAL_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_WAQTCHDOG_BASE), __phys_to_pfn(SL2312_WAQTCHDOG_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_UART_BASE), __phys_to_pfn(SL2312_UART_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_TIMER_BASE), __phys_to_pfn(SL2312_TIMER_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_LCD_BASE), __phys_to_pfn(SL2312_LCD_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_RTC_BASE), __phys_to_pfn(SL2312_RTC_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_SATA_BASE), __phys_to_pfn(SL2312_SATA_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_LPC_HOST_BASE), __phys_to_pfn(SL2312_LPC_HOST_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_LPC_IO_BASE), __phys_to_pfn(SL2312_LPC_IO_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_INTERRUPT_BASE), __phys_to_pfn(SL2312_INTERRUPT_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_INTERRUPT1_BASE), __phys_to_pfn(SL2312_INTERRUPT1_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_SSP_CTRL_BASE), __phys_to_pfn(SL2312_SSP_CTRL_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_POWER_CTRL_BASE), __phys_to_pfn(SL2312_POWER_CTRL_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_CIR_BASE), __phys_to_pfn(SL2312_CIR_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_GPIO_BASE), __phys_to_pfn(SL2312_GPIO_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_GPIO_BASE1), __phys_to_pfn(SL2312_GPIO_BASE1), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_GPIO_BASE2), __phys_to_pfn(SL2312_GPIO_BASE2), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_PCI_IO_BASE), __phys_to_pfn(SL2312_PCI_IO_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_PCI_MEM_BASE), __phys_to_pfn(SL2312_PCI_MEM_BASE), SZ_512K, MT_DEVICE}, -+#ifdef CONFIG_NET_SL351X -+{IO_ADDRESS(SL2312_TOE_BASE), __phys_to_pfn(SL2312_TOE_BASE) , SZ_512K, MT_DEVICE}, -+#endif -+{IO_ADDRESS(SL2312_GMAC0_BASE), __phys_to_pfn(SL2312_GMAC0_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_GMAC1_BASE), __phys_to_pfn(SL2312_GMAC1_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_SECURITY_BASE), __phys_to_pfn(SL2312_SECURITY_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_IDE0_BASE), __phys_to_pfn(SL2312_IDE0_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_IDE1_BASE), __phys_to_pfn(SL2312_IDE1_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_RAID_BASE), __phys_to_pfn(SL2312_RAID_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_FLASH_CTRL_BASE), __phys_to_pfn(SL2312_FLASH_CTRL_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_DRAM_CTRL_BASE), __phys_to_pfn(SL2312_DRAM_CTRL_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_GENERAL_DMA_BASE), __phys_to_pfn(SL2312_GENERAL_DMA_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_USB0_BASE), __phys_to_pfn(SL2312_USB_BASE), SZ_512K, MT_DEVICE}, -+{IO_ADDRESS(SL2312_USB1_BASE), __phys_to_pfn(SL2312_USB1_BASE), SZ_512K, MT_DEVICE}, -+{FLASH_VADDR(SL2312_FLASH_BASE), __phys_to_pfn(SL2312_FLASH_BASE), SZ_16M, MT_DEVICE}, -+}; -+ -+void __init sl2312_map_io(void) -+{ -+ iotable_init(sl2312_io_desc, ARRAY_SIZE(sl2312_io_desc)); -+} ---- /dev/null -+++ b/arch/arm/mach-sl2312/pci.c -@@ -0,0 +1,359 @@ -+/* -+ * linux/arch/arm/mach-sl2312/pci_sl2312.c -+ * -+ * PCI functions for sl2312 host PCI bridge -+ * -+ * Copyright (C) 2003 StorLink Corp. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+//#define DEBUG -+ -+// sl2312 PCI bridge access routines -+ -+#define PCI_IOSIZE_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE))) -+#define PCI_PROT_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x04)) -+#define PCI_CTRL_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x08)) -+#define PCI_SOFTRST_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x10)) -+#define PCI_CONFIG_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x28)) -+#define PCI_DATA_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x2C)) -+ -+static spinlock_t sl2312_pci_lock = SPIN_LOCK_UNLOCKED; -+// for initialize PCI devices -+struct resource pci_ioport_resource = { -+ .name = "PCI I/O Space", -+ .start = IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x100, -+ .end = IO_ADDRESS(SL2312_PCI_IO_BASE) + SZ_512K - 1, -+ .flags = IORESOURCE_IO, -+}; -+struct resource pci_iomem_resource = { -+ .name = "PCI Mem Space", -+ .start = SL2312_PCI_MEM_BASE, -+ .end = SL2312_PCI_MEM_BASE + SZ_128M - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static int sl2312_read_config(struct pci_bus *bus, unsigned int devfn, int where,int size, u32 *val) -+{ -+ unsigned long addr,data; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sl2312_pci_lock, flags); -+ addr = 0x80000000 | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | (where & ~3); -+ PCI_CONFIG_REG = addr; -+ data = PCI_DATA_REG; -+ -+ switch (size) { -+ case 1: -+ *val = (u8) (data >> ((where & 0x03) * 8)); -+ break; -+ case 2: -+ *val = (u16) (data >> ((where & 0x02) * 8)); -+ break; -+ case 4: -+ *val = data; -+ if ((where >= 0x10) && (where <= 0x24)) { -+ if ((*val & 0xfff00000) == SL2312_PCI_IO_BASE) { -+ *val &= 0x000fffff; -+ *val |= IO_ADDRESS(SL2312_PCI_IO_BASE); -+ } -+ } -+ break; -+ } -+ spin_unlock_irqrestore(&sl2312_pci_lock, flags); -+// printk("READ==>slot=%d fn=%d where=%d value=%x\n",PCI_SLOT(devfn),PCI_FUNC(devfn),where,*val); -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static int sl2312_write_config(struct pci_bus *bus, unsigned int devfn, int where,int size, u32 val) -+{ -+ unsigned long addr,data; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sl2312_pci_lock, flags); -+ addr = 0x80000000 | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | (where & ~3); -+ PCI_CONFIG_REG = addr; -+ data = PCI_DATA_REG; -+ -+ switch (size) { -+ case 1: -+ data &= ~(0xff << ((where & 0x03) * 8)); -+ data |= (val << ((where & 0x03) * 8)); -+ PCI_DATA_REG = data; -+ break; -+ case 2: -+ data &= ~(0xffff << ((where & 0x02) * 8)); -+ data |= (val << ((where & 0x02) * 8)); -+ PCI_DATA_REG = data; -+ break; -+ case 4: -+ if ((where >= 0x10) && (where <= 0x24)) { -+ if ((val & 0xfff00000) == IO_ADDRESS(SL2312_PCI_IO_BASE)) { -+ val &= 0x000fffff; -+ val |= SL2312_PCI_IO_BASE; -+ } -+ } -+ PCI_DATA_REG = val; -+ break; -+ } -+ spin_unlock_irqrestore(&sl2312_pci_lock, flags); -+ -+// printk("WRITE==> slot=%d fn=%d where=%d value=%x \n",PCI_SLOT(devfn),PCI_FUNC(devfn),where,val); -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static struct pci_ops sl2312_pci_ops = { -+ .read = sl2312_read_config, -+ .write = sl2312_write_config, -+}; -+ -+ -+int __init sl2312_pci_setup_resources(struct resource **resource) -+{ -+ PCI_IOSIZE_REG = 0; // 1M IO size -+ PCI_CTRL_REG = 0x06; -+ -+ resource[0] = &pci_ioport_resource; -+ resource[1] = &pci_iomem_resource; -+ resource[2] = NULL; -+ -+ return 1; -+} -+ -+//static int sl2312_pci_fault(unsigned long addr, struct pt_regs *regs) -+//{ -+// return 1; -+//} -+ -+ -+/********************************************************************** -+ * MASK(disable) PCI interrupt -+ * 0: PCI INTA, 1: PCI INTB, ... // for Linux interrupt routing -+ * 16: PERR // for PCI module internal use -+ * 17: SERR,.. respect to PCI CTRL2 REG -+ **********************************************************************/ -+void sl2312_pci_mask_irq(unsigned int irq) -+{ -+ struct pci_bus bus; -+ unsigned int tmp; -+ -+ bus.number = 0; -+ sl2312_read_config(&bus, 0, SL2312_PCI_CTRL2, 4, &tmp); -+ if (irq < 16) { // for linux int routing -+ tmp &= ~(1 << (irq + 16 + 6)); -+ } -+ else { -+ tmp &= ~(1 << irq); -+ } -+ sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp); -+} -+ -+/* UNMASK(enable) PCI interrupt */ -+void sl2312_pci_unmask_irq(unsigned int irq) -+{ -+ struct pci_bus bus; -+ unsigned int tmp; -+ -+ bus.number = 0; -+ sl2312_read_config(&bus, 0, SL2312_PCI_CTRL2, 4, &tmp); -+ if (irq < 16) { // for linux int routing -+ tmp |= (1 << (irq + 16 + 6)); -+ } -+ else { -+ tmp |= (1 << irq); -+ } -+ sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp); -+} -+ -+/* Get PCI interrupt source */ -+int sl2312_pci_get_int_src(void) -+{ -+ struct pci_bus bus; -+ unsigned int tmp=0; -+ -+ bus.number = 0; -+ sl2312_read_config(&bus, 0, SL2312_PCI_CTRL2, 4, &tmp); -+ if (tmp & (1 << 28)) { // PCI INTA -+ sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp); -+ return IRQ_PCI_INTA; -+ } -+ if (tmp & (1 << 29)) { // PCI INTB -+ sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp); -+ return IRQ_PCI_INTB; -+ } -+ if (tmp & (1 << 30)) { // PCI INTC -+ sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp); -+ return IRQ_PCI_INTC; -+ } -+ if (tmp & (1 << 31)) { // PCI INTD -+ sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp); -+ return IRQ_PCI_INTD; -+ } -+ // otherwise, it should be a PCI error -+ return IRQ_PCI; -+} -+ -+static irqreturn_t sl2312_pci_irq(int irq, void *devid) -+{ -+ struct irq_desc *desc; -+ struct irqaction *action; -+ int retval = 0; -+ -+ return 1; -+ -+ irq = sl2312_pci_get_int_src(); -+ desc = &irq_desc[irq]; -+ action = desc->action; -+ do { -+ retval |= action->handler(irq, devid); -+ action = action->next; -+ } while (action); -+ -+ return 1; -+} -+ -+//extern int (*external_fault)(unsigned long addr, struct pt_regs *regs); -+ -+void __init sl2312_pci_preinit(void) -+{ -+ struct pci_bus bus; -+ unsigned long flags; -+ unsigned int temp; -+ int ret; -+ -+ /* -+ * Hook in our fault handler for PCI errors -+ */ -+// external_fault = sl2312_pci_fault; -+ -+ spin_lock_irqsave(&sl2312_pci_lock, flags); -+ -+ /* -+ * Grab the PCI interrupt. -+ */ -+ ret = request_irq(IRQ_PCI, sl2312_pci_irq, 0, "sl2312 pci int", NULL); -+ if (ret) -+ printk(KERN_ERR "PCI: unable to grab PCI error " -+ "interrupt: %d\n", ret); -+ -+ spin_unlock_irqrestore(&sl2312_pci_lock, flags); -+ -+ // setup pci bridge -+ bus.number = 0; /* device 0, function 0 */ -+ temp = (SL2312_PCI_DMA_MEM1_BASE & 0xfff00000) | (SL2312_PCI_DMA_MEM1_SIZE << 16); -+ sl2312_write_config(&bus, 0, SL2312_PCI_MEM1_BASE_SIZE, 4, temp); -+} -+ -+/* -+ * No swizzle on SL2312 -+ */ -+static u8 __init sl2312_pci_swizzle(struct pci_dev *dev, u8 *pinp) -+{ -+ return PCI_SLOT(dev->devfn); -+} -+ -+/* -+ * map the specified device/slot/pin to an IRQ. This works out such -+ * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. -+ */ -+static int __init sl2312_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ int intnr = ((slot + (pin - 1)) & 3) + 4; /* the IRQ number of PCI bridge */ -+ -+ // printk("%s : slot = %d pin = %d \n",__func__,slot,pin); -+ switch (slot) -+ { -+ case 12: -+ if (pin==1) -+ { -+ intnr = 3; -+ } -+ else -+ { -+ intnr = 0; -+ } -+ break; -+ case 11: -+ intnr = (2 + (pin - 1)) & 3; -+ break; -+ case 10: -+ intnr = (1 + (pin - 1)) & 3; -+ break; -+ case 9: -+ intnr = (pin - 1) & 3; -+ break; -+ } -+// if (slot == 10) -+// intnr = (1 + (pin - 1)) & 3; -+// else if (slot == 9) -+// intnr = (pin - 1) & 3; -+ return (IRQ_PCI_INTA + intnr); -+} -+ -+struct pci_bus * __init sl2312_pci_scan_bus(int nr, struct pci_sys_data *sysdata) -+{ -+ return (pci_scan_bus(0, &sl2312_pci_ops, sysdata)); -+ -+} -+ -+int __init sl2312_pci_setup(int nr, struct pci_sys_data *sys) -+{ -+ int ret = 0; -+ -+ if (nr == 0) { -+ ret = sl2312_pci_setup_resources(sys->resource); -+ } -+ -+ return ret; -+} -+ -+ -+struct hw_pci sl2312_pci __initdata = { -+ .setup = sl2312_pci_setup, -+ .preinit = sl2312_pci_preinit, -+ .nr_controllers = 1, -+ .swizzle = sl2312_pci_swizzle, -+ .map_irq = sl2312_pci_map_irq, -+ .scan = sl2312_pci_scan_bus, -+}; -+ -+static int __init sl2312_pci_init(void) -+{ -+ if (machine_is_sl2312()) -+ pci_common_init(&sl2312_pci); -+ return 0; -+} -+ -+subsys_initcall(sl2312_pci_init); ---- /dev/null -+++ b/arch/arm/mach-sl2312/sl2312-otg-1.c -@@ -0,0 +1,64 @@ -+/* -+ * linux/arch/arm/mach-pxa/sl2312.c -+ * -+ * Author: Nicolas Pitre -+ * Created: Nov 05, 2002 -+ * Copyright: MontaVista Software Inc. -+ * -+ * Code specific to sl2312 aka Bulverde. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include "asm/arch/sl2312.h" -+#include "asm/arch/irqs.h" -+#include -+#include -+#include -+ -+/* -+ * device registration specific to sl2312. -+ */ -+ -+static u64 sl2312_dmamask_1 = 0xffffffffUL; -+ -+static struct resource sl2312_otg_resources_1[] = { -+ [0] = { -+ .start = 0x69000000, -+ .end = 0x69000fff, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = IRQ_USB1, -+ .end = IRQ_USB1, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device ehci_1_device = { -+ .name = "ehci-hcd-FOTG2XX", -+ .id = -1, -+ .dev = { -+ .dma_mask = &sl2312_dmamask_1, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .num_resources = ARRAY_SIZE(sl2312_otg_resources_1), -+ .resource = sl2312_otg_resources_1, -+}; -+ -+static struct platform_device *devices[] __initdata = { -+ &ehci_1_device, -+}; -+ -+static int __init sl2312_1_init(void) -+{ -+ return platform_add_devices(devices, ARRAY_SIZE(devices)); -+} -+ -+subsys_initcall(sl2312_1_init); ---- /dev/null -+++ b/arch/arm/mach-sl2312/sl2312-otg.c -@@ -0,0 +1,87 @@ -+/* -+ * linux/arch/arm/mach-pxa/sl2312.c -+ * -+ * Author: Nicolas Pitre -+ * Created: Nov 05, 2002 -+ * Copyright: MontaVista Software Inc. -+ * -+ * Code specific to sl2312 aka Bulverde. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include "asm/arch/sl2312.h" -+#include "asm/arch/irqs.h" -+#include -+#include -+#include -+ -+/* -+ * device registration specific to sl2312. -+ */ -+ -+static u64 sl2312_dmamask = 0xffffffffUL; -+ -+static struct resource sl2312_otg_resources_1[] = { -+ [0] = { -+ .start = 0x68000000, -+ .end = 0x68000fff, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = IRQ_USB0, -+ .end = IRQ_USB0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+static struct resource sl2312_otg_resources_2[] = { -+ [2] = { -+ .start = 0x69000000, -+ .end = 0x69000fff, -+ .flags = IORESOURCE_MEM, -+ }, -+ [3] = { -+ .start = IRQ_USB1, -+ .end = IRQ_USB1, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device ehci_device_1 = { -+ .name = "ehci-hcd-FOTG2XX", -+ .id = 1, -+ .dev = { -+ .dma_mask = &sl2312_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .num_resources = ARRAY_SIZE(sl2312_otg_resources_1), -+ .resource = sl2312_otg_resources_1, -+}; -+ -+static struct platform_device ehci_device_2 = { -+ .name = "ehci-hcd-FOTG2XX", -+ .id = 2, -+ .dev = { -+ .dma_mask = &sl2312_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .num_resources = ARRAY_SIZE(sl2312_otg_resources_2), -+ .resource = sl2312_otg_resources_2, -+}; -+ -+static struct platform_device *devices[] __initdata = { -+ &ehci_device_1, /* &ehci_device_2, */ -+}; -+ -+static int __init sl2312_init(void) -+{ -+ return platform_add_devices(devices, ARRAY_SIZE(devices)); -+} -+ -+subsys_initcall(sl2312_init); ---- /dev/null -+++ b/arch/arm/mach-sl2312/sl3516_device.c -@@ -0,0 +1,89 @@ -+/* -+ * linux/arch/arm/mach-2312/sl3516_device.c -+ * -+ * Author: Nicolas Pitre -+ * Created: Nov 05, 2002 -+ * Copyright: MontaVista Software Inc. -+ * -+ * Code specific to sl2312 aka Bulverde. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "asm/arch/sl2312.h" -+#include "asm/arch/irqs.h" -+#include -+#include -+ -+/* -+ * device registration specific to sl2312. -+ */ -+ -+static u64 sl3516_dmamask = 0xffffffffUL; -+ -+static struct resource sl3516_sata_resources[] = { -+ [0] = { -+ .start = 0x63400000, -+ .end = 0x63400040, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = IRQ_IDE1, -+ .end = IRQ_IDE1, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device sata_device = { -+ .name = "lepus-sata", -+ .id = -1, -+ .dev = { -+ .dma_mask = &sl3516_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .num_resources = ARRAY_SIZE(sl3516_sata_resources), -+ .resource = sl3516_sata_resources, -+}; -+ -+static struct resource sl3516_sata0_resources[] = { -+ [0] = { -+ .start = 0x63000000, -+ .end = 0x63000040, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = IRQ_IDE0, -+ .end = IRQ_IDE0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device sata0_device = { -+ .name = "lepus-sata0", -+ .id = -1, -+ .dev = { -+ .dma_mask = &sl3516_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ }, -+ .num_resources = ARRAY_SIZE(sl3516_sata0_resources), -+ .resource = sl3516_sata0_resources, -+}; -+ -+static struct platform_device *sata_devices[] __initdata = { -+ &sata_device, -+ &sata0_device, -+}; -+ -+static int __init sl3516_init(void) -+{ -+ return platform_add_devices(sata_devices, ARRAY_SIZE(sata_devices)); -+} -+ -+subsys_initcall(sl3516_init); ---- /dev/null -+++ b/arch/arm/mach-sl2312/time.c -@@ -0,0 +1,134 @@ -+/* -+ * linux/include/asm-arm/arch-epxa10db/time.h -+ * -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#define TIMER_TYPE (volatile unsigned int*) -+#include -+// #define FIQ_PLUS 1 -+ -+ -+/* -+ * IRQ handler for the timer -+ */ -+static irqreturn_t sl2312_timer_interrupt(int irq, void *dev_id) -+{ -+// unsigned int led; -+ // ...clear the interrupt -+#ifdef FIQ_PLUS -+ *((volatile unsigned int *)FIQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER1_MASK); -+#else -+ *((volatile unsigned int *)IRQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER2_MASK); -+#endif -+ -+#if 0 -+ if(!(jiffies % HZ)) -+ { -+ led = jiffies / HZ; -+// printk("ticks %x \n", led); -+ } -+ do_leds(); -+ do_timer(regs); -+ do_profile(regs); -+#endif -+ timer_tick(); -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction sl2312_timer_irq = { -+ .name = "SL2312 Timer Tick", -+ .flags = IRQF_DISABLED | IRQF_TIMER, -+ .handler = sl2312_timer_interrupt, -+}; -+ -+unsigned long sl2312_gettimeoffset (void) -+{ -+ return 0L; -+} -+ -+/* -+ * Set up timer interrupt, and return the current time in seconds. -+ */ -+void __init sl2312_time_init(void) -+{ -+ // For clock rate adjusting -+ unsigned int tick_rate=0; -+ -+#ifdef CONFIG_SL3516_ASIC -+ unsigned int clock_rate_base = 130000000; -+ unsigned int reg_v=0; -+ -+ //--> Add by jason for clock adjust -+ reg_v = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_STATUS))); -+ reg_v >>= 15; -+ tick_rate = (clock_rate_base + (reg_v & 0x07)*10000000); -+ -+ // FPGA use AHB bus tick rate -+ printk("Bus: %dMHz",tick_rate/1000000); -+ -+ tick_rate /= 6; // APB bus run AHB*(1/6) -+ -+ switch((reg_v>>3)&3){ -+ case 0: printk("(1/1)\n") ; -+ break; -+ case 1: printk("(3/2)\n") ; -+ break; -+ case 2: printk("(24/13)\n") ; -+ break; -+ case 3: printk("(2/1)\n") ; -+ break; -+ } -+ //<-- -+#else -+ printk("Bus: %dMHz(1/1)\n",CLOCK_TICK_RATE/1000000); // FPGA use 20MHz -+ tick_rate = CLOCK_TICK_RATE; -+#endif -+ -+ -+ /* -+ * Make irqs happen for the system timer -+ */ -+ // initialize timer interrupt -+ // low active and edge trigger -+#ifdef FIQ_PLUS -+ *((volatile unsigned int *)FIQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER1_MASK); -+ *((volatile unsigned int *)FIQ_LEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER1_MASK); -+ setup_irq(IRQ_TIMER1, &sl2312_timer_irq); -+ /* Start the timer */ -+ *TIMER_COUNT(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(tick_rate/HZ); -+ *TIMER_LOAD(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(tick_rate/HZ); -+ *TIMER_CR(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(TIMER_1_CR_ENABLE_MSK|TIMER_1_CR_INT_MSK); -+#else -+ *((volatile unsigned int *)IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER2_MASK); -+ *((volatile unsigned int *)IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER2_MASK); -+ setup_irq(IRQ_TIMER2, &sl2312_timer_irq); -+ /* Start the timer */ -+ *TIMER_COUNT(IO_ADDRESS(SL2312_TIMER2_BASE))=(unsigned int)(tick_rate/HZ); -+ *TIMER_LOAD(IO_ADDRESS(SL2312_TIMER2_BASE))=(unsigned int)(tick_rate/HZ); -+ *TIMER_CR(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(TIMER_2_CR_ENABLE_MSK|TIMER_2_CR_INT_MSK); -+#endif -+ -+} -+ -+ ---- /dev/null -+++ b/arch/arm/mach-sl2312/xor.c -@@ -0,0 +1,1200 @@ -+/* -+ * arch/arm/mach-sl2312/xor.c -+ * -+ * Support functions for the Gemini Soc. This is -+ * a HW XOR unit that is specifically designed for use with RAID5 -+ * applications. This driver provides an interface that is used by -+ * the Linux RAID stack. -+ * -+ * Original Author: Jason Lee -+ * -+ * Contributors:Sanders -+ Jason Lee -+ * -+ * -+ * Maintainer: Jason Lee -+ * -+ * Copyright (C) 2005 Storlink Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * -+ * History: (06/25/2005, DJ) Initial Creation -+ * -+ * Versing 1.0.0 Initial version -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * pick up local definitions -+ */ -+#define XOR_SW_FILL_IN -+#include "hw_xor.h" -+ -+ -+//#define XOR_DEBUG -+//#define XOR_TEST 1 -+#ifdef XOR_TEST -+#define TEST_ITERATION 1000 -+#define SPIN_WAIT 1 -+#endif -+#ifdef XOR_DEBUG -+#define DPRINTK(s, args...) printk("Gemini XOR: " s "\n", ## args) -+#define DENTER() DPRINTK("Entered...\n"); -+#define DEXIT() DPRINTK("Exited...\n"); -+#else -+#define DPRINTK(s, args...) -+#define DENTER() -+#define DEXIT() -+#endif -+ -+//#define SPIN_WAIT -+ -+/* globals */ -+static RAID_T tp; -+static RAID_TXDMA_CTRL_T txdma_ctrl; -+RAID_RXDMA_CTRL_T rxdma_ctrl; -+ -+//#ifndef SPIN_WAIT -+static spinlock_t raid_lock; -+//#endif -+ -+static unsigned int tx_desc_virtual_base; -+static unsigned int rx_desc_virtual_base; -+RAID_DESCRIPTOR_T *tx_desc_ptr; -+RAID_DESCRIPTOR_T *rx_desc_ptr; -+ -+/* static prototypes */ -+#define DMA_MALLOC(size,handle) pci_alloc_consistent(NULL,size,handle) -+#define DMA_MFREE(mem,size,handle) pci_free_consistent(NULL,size,mem,handle) -+ -+static int gemini_xor_init_desc(void); -+ -+static unsigned int raid_read_reg(unsigned int offset) -+{ -+ unsigned int reg_val; -+ -+ reg_val = readl(RAID_BASE_ADDR + offset); -+ return (reg_val); -+} -+ -+static void raid_write_reg(unsigned int offset,unsigned int data,unsigned int bit_mask) -+{ -+ unsigned int reg_val; -+ unsigned int *addr; -+ -+ reg_val = ( raid_read_reg(offset) & (~bit_mask) ) | (data & bit_mask); -+ addr = (unsigned int *)(RAID_BASE_ADDR + offset); -+ writel(reg_val,addr); -+ return; -+} -+ -+#ifndef SPIN_WAIT -+__inline__ void xor_queue_descriptor(void) -+{ -+ unsigned int flags,status=1; -+ -+ DPRINTK("Going to sleep"); -+ -+ while(status){ -+ yield(); -+ //schedule(); -+ spin_lock_irqsave(&raid_lock,flags); -+ status = tp.busy; -+ spin_unlock_irqrestore(&raid_lock, flags); -+ } -+// tp.status = COMPLETE; -+ DPRINTK("woken up!"); -+ -+} -+#endif -+ -+#ifdef SPIN_WAIT -+static void gemini_xor_isr(int d_n) -+#else -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28) -+static void gemini_xor_isr(int irq, void *dev_id, struct pt_regs *regs) -+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) -+static irqreturn_t gemini_xor_isr(int irq, void *dev_instance, struct pt_regs *regs) -+#endif -+#endif -+{ -+ -+ unsigned int err; -+ RAID_DMA_STATUS_T dma_status; -+// RAID_DESCRIPTOR_T *rdesc,*tdesc; -+// unsigned int *paddr; -+ -+ dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS); -+#ifdef SPIN_WAIT -+ while( (dma_status.bits32& (1<<31) ) ==0 ){ -+ udelay(1); -+ dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS); -+ } -+ -+/* tdesc = tp.tx_first_desc; -+ rdesc = tp.rx_first_desc; -+ for(d_n;d_n>0;d_n--){ -+ if( tdesc->func_ctrl.bits.own == DMA ){ -+ paddr = tdesc; -+ printk("error tx desc:0x%x\n",*paddr++); -+ printk("error tx desc:0x%x\n",*paddr++); -+ printk("error tx desc:0s%x\n",*paddr++); -+ printk("error tx desc:0x%x\n",*paddr); -+ while(1); -+ } -+ tdesc = (RAID_DESCRIPTOR_T *)((tdesc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ } -+ -+ if( rdesc->func_ctrl.bits.own == DMA ){ -+ paddr = rdesc; -+ printk("error rx desc:0x%x\n",*paddr++); -+ printk("error rx desc:0x%x\n",*paddr++); -+ printk("error rx desc:0s%x\n",*paddr++); -+ printk("error rx desc:0x%x\n",*paddr); -+ while(1); -+ } -+*/ -+#endif -+ -+ if(dma_status.bits32 & ((1<<31)|(1<<26))){ -+ // if no bug , we can turn off rx finish interrupt -+ dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS); -+ err = raid_read_reg(RAID_DMA_DEVICE_ID); -+ tp.busy = 0; -+ -+ if(err&0x00FF0000){ -+ tp.status = ERROR; -+ printk("XOR:%s error code %x\n",(err&0x00F00000)?"tx":"rx",err); -+ -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28) -+ return ; -+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) -+#ifndef SPIN_WAIT -+ return IRQ_RETVAL(IRQ_HANDLED); -+#endif -+#endif -+ } -+ // 16~19 rx error code -+ // 20~23 tx error codd -+ -+ dma_status.bits.tsFinishI = 1; -+ dma_status.bits.rsFinishI = 1; -+ raid_write_reg(RAID_DMA_STATUS, dma_status.bits32,0x84000000); // clear INT -+ -+// printk("xor %d\n",d_n); -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28) -+ return ; -+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) -+#ifndef SPIN_WAIT -+ return IRQ_RETVAL(IRQ_HANDLED); -+#endif -+#endif -+ } -+ -+ #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28) -+ return ; -+ #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) -+ #ifndef SPIN_WAIT -+ printk("XOR: DMA status register(0x%8x)\n",dma_status.bits32); -+ return IRQ_RETVAL(IRQ_HANDLED); -+ #endif -+ #endif -+} -+ -+void -+xor_gemini_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) -+{ -+ int status=0; -+ unsigned int flags; -+ -+ if(bytes > (1<<(SRAM_PAR_SIZE+11))){ -+ printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes); -+ } -+ -+ spin_lock_irqsave(&raid_lock,flags); -+ while(tp.status != COMPLETE){ -+ spin_unlock_irqrestore(&raid_lock, flags); -+ //printk("XOR yield2\n"); -+#ifdef XOR_SW_FILL_IN -+ xor_arm4regs_2(bytes,p1,p2); -+ return ; -+#else -+ yield(); -+#endif -+ } -+ spin_unlock_irqrestore(&raid_lock, flags); -+ tp.status = RUNNING; -+ -+ // flush the cache to memory before H/W XOR touches them -+ consistent_sync(p1, bytes, DMA_BIDIRECTIONAL); -+ consistent_sync(p2, bytes, DMA_TO_DEVICE); -+ -+ -+ tp.tx_desc = tp.tx_first_desc; -+ tp.rx_desc = tp.rx_first_desc; -+ if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){ -+ // prepare tx descript -+ raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff); -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 2; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00020000; -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ wmb(); -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p2); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 1; // last descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00010000; -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); // keep last descript -+ -+ wmb(); -+ // prepare rx descript -+ raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFf); -+ tp.rx_desc->buf_addr = (unsigned int)__pa(p1); -+ tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+ tp.rx_desc->flg_status.bits32 = 0; // link data from XOR -+// tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ -+ } -+ else{ -+ /* no free tx descriptor */ -+ printk("XOR:no free tx descript"); -+ return ; -+ } -+ -+ // change status -+// tp.status = RUNNING; -+ status = tp.busy = 1; -+ -+ // start tx DMA -+ rxdma_ctrl.bits.rd_start = 1; -+ // start rx DMA -+ txdma_ctrl.bits.td_start = 1; -+ -+ raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000); -+ raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000); -+ -+#ifdef SPIN_WAIT -+ gemini_xor_isr(2); -+#else -+ xor_queue_descriptor(); -+#endif -+ -+ tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*2) ; -+ tp.status = COMPLETE; -+// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ; -+// tp.rx_desc = tp.rx_first_desc ; -+// tp.rx_desc->func_ctrl.bits.own = DMA; -+ -+} -+ -+void -+xor_gemini_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, -+ unsigned long *p3) -+{ -+ int status=0; -+ unsigned int flags; -+ -+ if(bytes > (1<<(SRAM_PAR_SIZE+11))){ -+ printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes); -+ } -+ -+ spin_lock_irqsave(&raid_lock,flags); -+ if(tp.status != COMPLETE){ -+ spin_unlock_irqrestore(&raid_lock, flags); -+ //printk("XOR yield3\n"); -+#ifdef XOR_SW_FILL_IN -+ xor_arm4regs_3(bytes,p1,p2,p3); -+ return; -+#else -+ yield(); -+#endif -+ } -+ spin_unlock_irqrestore(&raid_lock, flags); -+ tp.status = RUNNING; -+ -+ // flush the cache to memory before H/W XOR touches them -+ consistent_sync(p1, bytes, DMA_BIDIRECTIONAL); -+ consistent_sync(p2, bytes, DMA_TO_DEVICE); -+ consistent_sync(p3, bytes, DMA_TO_DEVICE); -+ -+ tp.tx_desc = tp.tx_first_desc; -+ tp.rx_desc = tp.rx_first_desc; -+ if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){ -+ // prepare tx descript -+ raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff); -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 2; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00020000; -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p2); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x0000000; -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p3); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 1; // last descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00010000; -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); // keep last descript -+ -+ // prepare rx descript -+ raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFf); -+ tp.rx_desc->buf_addr = (unsigned int)__pa(p1); -+ tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+ tp.rx_desc->flg_status.bits32 = 0; // link data from XOR -+// tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ -+ } -+ else{ -+ /* no free tx descriptor */ -+ printk("XOR:no free tx descript \n"); -+ return ; -+ } -+ -+ // change status -+// tp.status = RUNNING; -+ status = tp.busy = 1; -+ -+ // start tx DMA -+ rxdma_ctrl.bits.rd_start = 1; -+ // start rx DMA -+ txdma_ctrl.bits.td_start = 1; -+ wmb(); -+ raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000); -+ raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000); -+ -+#ifdef SPIN_WAIT -+ gemini_xor_isr(3); -+#else -+ xor_queue_descriptor(); -+#endif -+ tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*3) | 0x0B; -+ tp.status = COMPLETE; -+// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) | 0x0B; -+ //tp.rx_desc = tp.rx_first_desc ; -+// tp.rx_desc->func_ctrl.bits.own = DMA; -+ -+} -+ -+void -+xor_gemini_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, -+ unsigned long *p3, unsigned long *p4) -+{ -+ int status=0; -+ unsigned int flags; -+ -+ if(bytes > (1<<(SRAM_PAR_SIZE+11))){ -+ printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes); -+ } -+ -+ spin_lock_irqsave(&raid_lock,flags); -+ if(tp.status != COMPLETE){ -+ spin_unlock_irqrestore(&raid_lock, flags); -+ //printk("S\n"); -+#ifdef XOR_SW_FILL_IN -+ xor_arm4regs_4(bytes,p1,p2,p3,p4); -+ return; -+#else -+ msleep(1); -+ yield(); -+#endif -+ } -+ spin_unlock_irqrestore(&raid_lock, flags); -+ -+ tp.status = RUNNING; -+ -+ // flush the cache to memory before H/W XOR touches them -+ consistent_sync(p1, bytes, DMA_BIDIRECTIONAL); -+ consistent_sync(p2, bytes, DMA_TO_DEVICE); -+ consistent_sync(p3, bytes, DMA_TO_DEVICE); -+ consistent_sync(p4, bytes, DMA_TO_DEVICE); -+ -+ tp.tx_desc = tp.tx_first_desc; -+ tp.rx_desc = tp.rx_first_desc; -+ if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){ -+ // prepare tx descript -+ raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff); -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 2; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00020000; -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_cur_desc->buf_addr = (unsigned int)__pa(p2); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00000000; -+ tp.tx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p3); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00000000; -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ -+ -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p4); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 1; // last descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00010000; -+// tp.tx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); // keep last descript -+ -+ // prepare rx descript -+ raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF); -+ tp.rx_desc->buf_addr = (unsigned int)__pa(p1); -+ tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+ tp.rx_desc->flg_status.bits32 = 0; // link data from XOR -+// tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ -+ } -+ else{ -+ /* no free tx descriptor */ -+ printk("XOR:no free tx descript"); -+ return ; -+ } -+ -+ // change status -+// tp.status = RUNNING; -+ status = tp.busy = 1; -+ -+ // start tx DMA -+ rxdma_ctrl.bits.rd_start = 1; -+ // start rx DMA -+ txdma_ctrl.bits.td_start = 1; -+ wmb(); -+ raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000); -+ raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000); -+ -+#ifdef SPIN_WAIT -+ gemini_xor_isr(4); -+#else -+ xor_queue_descriptor(); -+#endif -+ -+ tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*4) | 0x0B; -+ tp.status = COMPLETE; -+// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) | 0x0B; -+ //tp.rx_desc = tp.rx_first_desc ; -+// tp.rx_desc->func_ctrl.bits.own = DMA; -+ -+} -+ -+void -+xor_gemini_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, -+ unsigned long *p3, unsigned long *p4, unsigned long *p5) -+{ -+ -+ int status=0; -+ unsigned int flags; -+ -+ -+ if(bytes > (1<<(SRAM_PAR_SIZE+11))){ -+ printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes); -+ } -+ -+ spin_lock_irqsave(&raid_lock,flags); -+ while(tp.status != COMPLETE){ -+ spin_unlock_irqrestore(&raid_lock, flags); -+ //printk("XOR yield5\n"); -+#ifdef XOR_SW_FILL_IN -+ xor_arm4regs_5(bytes,p1,p2,p3,p4,p5); -+ return; -+#else -+ msleep(1); -+ yield(); -+#endif -+ } -+ spin_unlock_irqrestore(&raid_lock, flags); -+ tp.status = RUNNING; -+ -+ // flush the cache to memory before H/W XOR touches them -+ consistent_sync(p1, bytes, DMA_BIDIRECTIONAL); -+ consistent_sync(p2, bytes, DMA_TO_DEVICE); -+ consistent_sync(p3, bytes, DMA_TO_DEVICE); -+ consistent_sync(p4, bytes, DMA_TO_DEVICE); -+ consistent_sync(p5, bytes, DMA_TO_DEVICE); -+ -+ tp.tx_desc = tp.tx_first_desc; -+ tp.rx_desc = tp.rx_first_desc; -+ if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){ -+ // prepare tx descript -+ raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff); -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 2; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00020000; -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ wmb(); -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p2); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00000000; -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ wmb(); -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p3); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00000000; -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ wmb(); -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p4); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+ tp.tx_desc->flg_status.bits32 = 0x00000000; -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ wmb(); -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ -+ -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p5); // pysical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+// tp.tx_desc->flg_status.bits_cmd_status.bcc = 1; // last descript -+// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command -+// tp.tx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->flg_status.bits32 = 0x00010000; -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); -+ tp.tx_finished_desc = tp.tx_desc; // keep last descript -+ -+ // prepare rx descript -+ raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF); -+ tp.rx_desc->buf_addr = (unsigned int)__pa(p1); -+ tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+ tp.rx_desc->flg_status.bits32 = 0; // link data from XOR -+// tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ -+ } -+ else{ -+ /* no free tx descriptor */ -+ printk("XOR:no free tx descript"); -+ return ; -+ } -+ -+ // change status -+// tp.status = RUNNING; -+ status = tp.busy = 1; -+ -+ // start tx DMA -+ rxdma_ctrl.bits.rd_start = 1; -+ // start rx DMA -+ txdma_ctrl.bits.td_start = 1; -+ wmb(); -+ raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000); -+ raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000); -+ -+#ifdef SPIN_WAIT -+ gemini_xor_isr(5); -+#else -+ xor_queue_descriptor(); -+#endif -+ -+ tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*5) | 0x0B; -+ tp.status = COMPLETE; -+// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) | 0x0B; -+ //tp.rx_desc = tp.rx_first_desc ; -+// tp.rx_desc->func_ctrl.bits.own = DMA; -+ -+} -+ -+#ifdef XOR_TEST -+void -+raid_memset(unsigned int *p1, unsigned int pattern, unsigned int bytes) -+{ -+ int status=0,i; -+ -+ if(bytes > (1<<(SRAM_PAR_SIZE+11))){ -+ printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes); -+ } -+ -+ *p1 = pattern; -+ -+ // flush the cache to memory before H/W XOR touches them -+ consistent_sync(p1, bytes, DMA_BIDIRECTIONAL); -+ -+ while(tp.status != COMPLETE){ -+ DPRINTK("XOR yield\n"); -+ //schedule(); -+ yield(); -+ } -+ tp.status = RUNNING; -+ -+ tp.tx_desc = tp.tx_first_desc; -+ tp.rx_desc = tp.rx_first_desc; -+ if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){ -+ // prepare tx descript -+ raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xFFFFFFFF); -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = 4; /* total frame byte count */ -+ tp.tx_desc->flg_status.bits_cmd_status.bcc = bytes; // bytes to fill -+ tp.tx_desc->flg_status.bits_cmd_status.mode = CMD_FILL; // only support memory FILL command -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_desc->next_desc_addr.bits32 = 0x0000000b; -+// tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xFFFFFFF0)+tx_desc_virtual_base); -+ -+ // prepare rx descript -+ raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF); -+ tp.rx_desc->buf_addr = (unsigned int)__pa(p1); -+ tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+ tp.rx_desc->flg_status.bits32 = 0; // link data from XOR -+ tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+// tp.rx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.rx_cur_desc->next_desc_addr.bits32 & 0xfffffff0)+rx_desc_virtual_base); -+ tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ tp.rx_finished_desc = tp.rx_desc; -+ -+ } -+ else{ -+ /* no free tx descriptor */ -+ printk("XOR:no free tx descript"); -+ return ; -+ } -+ -+ // change status -+ //tp.status = RUNNING; -+ status = tp.busy = 1; -+ -+ // start tx DMA -+ rxdma_ctrl.bits.rd_start = 1; -+ // start rx DMA -+ txdma_ctrl.bits.td_start = 1; -+ -+ raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000); -+ raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000); -+ -+#ifdef SPIN_WAIT -+ gemini_xor_isr(2); -+#else -+ xor_queue_descriptor(); -+#endif -+ -+ for(i=1; i<(bytes/sizeof(int)); i++) { -+ if(p1[0]!=p1[i]){ -+ printk("pattern set error!\n"); -+ while(1); -+ } -+ } -+ -+ tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ; -+ tp.status = COMPLETE; -+// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ; -+ //tp.rx_desc = tp.rx_first_desc ; -+// tp.rx_desc->func_ctrl.bits.own = DMA; -+ -+} -+#endif -+ -+void -+raid_memcpy(unsigned int *to, unsigned int *from, unsigned int bytes) -+{ -+ int status=0,i; -+ -+ if(bytes > (1<<(SRAM_PAR_SIZE+11))){ -+ printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes); -+ } -+ -+ // flush the cache to memory before H/W XOR touches them -+ consistent_sync(to, bytes, DMA_BIDIRECTIONAL); -+ consistent_sync(from,bytes, DMA_TO_DEVICE); -+ -+ while(tp.status != COMPLETE){ -+ DPRINTK("XOR yield\n"); -+ //schedule(); -+ yield(); -+ } -+ tp.status = RUNNING; -+ -+ tp.tx_desc = tp.tx_first_desc; -+ tp.rx_desc = tp.rx_first_desc; -+ if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){ -+ // prepare tx descript -+ raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xFFFFFFFF); -+ tp.tx_desc->buf_addr = (unsigned int)__pa(from); // physical address -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+ tp.tx_desc->flg_status.bits32 = CMD_CPY; // only support memory FILL command -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_desc->next_desc_addr.bits32 = 0x0000000b; -+// tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xFFFFFFF0)+tx_desc_virtual_base); -+ -+ // prepare rx descript -+ raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF); -+ tp.rx_desc->buf_addr = (unsigned int)__pa(to); -+ tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */ -+ tp.rx_desc->flg_status.bits32 = 0; // link data from XOR -+ tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+// tp.rx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.rx_cur_desc->next_desc_addr.bits32 & 0xfffffff0)+rx_desc_virtual_base); -+ tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript -+ -+ } -+ else{ -+ /* no free tx descriptor */ -+ printk("XOR:no free tx descript"); -+ return ; -+ } -+ -+ // change status -+ //tp.status = RUNNING; -+ status = tp.busy = 1; -+ -+ // start tx DMA -+ rxdma_ctrl.bits.rd_start = 1; -+ // start rx DMA -+ txdma_ctrl.bits.td_start = 1; -+ -+ raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000); -+ raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000); -+ -+#ifdef SPIN_WAIT -+ gemini_xor_isr(2); -+#else -+ xor_queue_descriptor(); -+#endif -+ -+#ifdef XOR_TEST -+ for(i=1; i<(bytes/sizeof(int)); i++) { -+ if(to[i]!=from[i]){ -+ printk("pattern check error!\n"); -+ printk("offset=0x%x p1=%x p2=%x\n",i*4,to[i],from[i]); -+ while(1); -+ } -+ } -+#endif -+ -+ tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ; -+ tp.status = COMPLETE; -+// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ; -+ //tp.rx_desc = tp.rx_first_desc ; -+// tp.rx_desc->func_ctrl.bits.own = DMA; -+ -+} -+EXPORT_SYMBOL(raid_memcpy); -+ -+#ifdef XOR_TEST -+int -+raid_memchk(unsigned int *p1, unsigned int pattern, unsigned int bytes) -+{ -+ int status=0; -+ RAID_DMA_STATUS_T dma_status; -+ -+ if(bytes > (1<<(SRAM_PAR_SIZE+11))){ -+ printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes); -+ } -+ -+ status = ((pattern&0xFFFF)%bytes )/4; -+ p1[status] = pattern; -+ -+ while(tp.status != COMPLETE){ -+ DPRINTK("XOR yield\n"); -+ //schedule(); -+ yield(); -+ } -+ tp.status = RUNNING; -+ -+ // flush the cache to memory before H/W XOR touches them -+ consistent_sync(p1, bytes, DMA_BIDIRECTIONAL); -+ -+ tp.tx_desc = tp.tx_first_desc; -+ if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){ -+ // prepare tx descript -+ raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xFFFFFFFF); -+ tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address -+ tp.tx_desc->func_ctrl.bits.raid_ctrl_status = 0; -+ tp.tx_desc->func_ctrl.bits.buffer_size = bytes ; /* total frame byte count */ -+ tp.tx_desc->flg_status.bits32 = CMD_CHK; // only support memory FILL command -+ tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */ -+ tp.tx_desc->next_desc_addr.bits32 = 0x0000000b; -+// tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xFFFFFFF0)+tx_desc_virtual_base); -+ -+ } -+ else{ -+ /* no free tx descriptor */ -+ printk("XOR:no free tx descript"); -+ return -1; -+ } -+ -+ // change status -+ //tp.status = RUNNING; -+ status = tp.busy = 1; -+ -+ // start tx DMA -+ txdma_ctrl.bits.td_start = 1; -+ -+ raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000); -+// raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000); -+ -+#ifdef SPIN_WAIT -+ gemini_xor_isr(2); -+#else -+ xor_queue_descriptor(); -+#endif -+ -+// dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS); -+// if (dma_status.bits32 & (1<<15)) { -+ -+ if((tp.tx_first_desc->func_ctrl.bits.raid_ctrl_status & 0x2)) { -+ status = 1; -+// raid_write_reg(RAID_DMA_STATUS,0x00008000,0x00080000); -+ } -+ else{ -+ status = 0; -+ } -+ -+ tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ; -+ tp.status = COMPLETE; -+// tp.rx_desc->func_ctrl.bits.own = DMA; -+ return status ; -+} -+#endif -+ -+int __init gemini_xor_init(void) -+{ -+ unsigned int res; -+ unsigned int *paddr1,*paddr2,*paddr3,i; -+ unsigned volatile char *charact; -+ unsigned volatile short *two_char; -+ unsigned volatile int *four_char; -+ -+ // init descript -+ res = gemini_xor_init_desc(); -+ if(res) { -+ printk("Init RAID Descript Fail!!\n"); -+ return -res; -+ } -+ -+ tp.device_name = "Gemini XOR Acceleration"; -+ -+ // request irq -+#ifndef SPIN_WAIT -+ res = request_irq(IRQ_RAID, gemini_xor_isr, SA_INTERRUPT, tp.device_name, NULL); -+#endif -+ if(res){ -+ printk(KERN_ERR "%s: unable to request IRQ %d for " -+ "HW XOR %d\n", tp.device_name, IRQ_RAID, res); -+ return -EBUSY; -+ } -+ -+#ifdef XOR_TEST -+ -+RETEST: -+ paddr1 = kmalloc(0x1000,GFP_KERNEL); -+ paddr2 = kmalloc(0x1000,GFP_KERNEL); -+ paddr3 = kmalloc(0x1000,GFP_KERNEL); -+ for(i=0;ifunc_ctrl.bits.own = CPU; -+ tp.tx_desc->func_ctrl.bits.buffer_size = 0; -+ tp.tx_desc_dma = tp.tx_desc_dma + sizeof(RAID_DESCRIPTOR_T); -+// tp.tx_desc->next_desc_addr.bits32 = (unsigned int)tp.tx_desc_dma | 0x0B; -+ tp.tx_desc->next_desc_addr.bits32 = ((unsigned int)tx_first_desc_dma | 0x0B) + i*0x10; -+ tp.tx_desc = &tp.tx_desc[1]; -+ } -+ tp.tx_desc->func_ctrl.bits.own = DMA; -+ tp.tx_desc->next_desc_addr.bits32 = (unsigned int)tx_first_desc_dma|0x0b; -+ tp.tx_desc = tp.tx_cur_desc; -+ tp.tx_desc_dma = (unsigned int*)tx_first_desc_dma; -+ tp.tx_first_desc = tp.tx_desc ; -+ -+ tp.rx_cur_desc = tp.rx_desc; /* virtual address */ -+ tp.rx_finished_desc = tp.rx_desc; /* virtual address */ -+ rx_first_desc_dma = (dma_addr_t)tp.rx_desc_dma; /* physical address */ -+ for (i = 1; i < RX_DESC_NUM; i++) { -+ tp.rx_desc->func_ctrl.bits.own = DMA; -+ tp.rx_desc->func_ctrl.bits.buffer_size = 0; -+ tp.rx_desc_dma = tp.rx_desc_dma + sizeof(RAID_DESCRIPTOR_T); -+// tp.rx_desc->next_desc_addr.bits32 = (unsigned int)tp.rx_desc_dma | 0x0B; -+ tp.rx_desc->next_desc_addr.bits32 = ((unsigned int)rx_first_desc_dma | 0x0B) + i*0x10; -+ tp.rx_desc = &tp.rx_desc[1]; -+ } -+ tp.rx_desc->func_ctrl.bits.own = DMA; -+ tp.rx_desc->next_desc_addr.bits32 = rx_first_desc_dma|0x0b; -+ tp.rx_desc = tp.rx_cur_desc; -+ tp.rx_desc_dma = (unsigned int*)rx_first_desc_dma; -+ tp.rx_first_desc = tp.rx_desc ; -+ tp.busy = 0; -+ tp.status = COMPLETE; -+ -+ // Partition SRAM size -+ raid_write_reg(RAID_PCR, SRAM_PAR_SIZE,0x00000003); -+ -+ // config tx DMA controler -+ txdma_ctrl.bits32 = 0; -+ txdma_ctrl.bits.td_start = 0; -+ txdma_ctrl.bits.td_continue = 1; -+ txdma_ctrl.bits.td_chain_mode = 1; -+ txdma_ctrl.bits.td_prot = 0; -+ txdma_ctrl.bits.td_burst_size = 1; -+ txdma_ctrl.bits.td_bus = 3; -+ txdma_ctrl.bits.td_endian = 0; -+ txdma_ctrl.bits.td_finish_en = 1; -+ txdma_ctrl.bits.td_fail_en = 1; -+ txdma_ctrl.bits.td_perr_en = 1; -+ txdma_ctrl.bits.td_eod_en = 0; // enable tx descript -+ txdma_ctrl.bits.td_eof_en = 0; -+ raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0xFFFFFFFF); -+ -+ // config rx DMA controler -+ rxdma_ctrl.bits32 = 0; -+ rxdma_ctrl.bits.rd_start = 0; -+ rxdma_ctrl.bits.rd_continue = 1; -+ rxdma_ctrl.bits.rd_chain_mode = 1; -+ rxdma_ctrl.bits.rd_prot = 0; -+ rxdma_ctrl.bits.rd_burst_size = 1; -+ rxdma_ctrl.bits.rd_bus = 3; -+ rxdma_ctrl.bits.rd_endian = 0; -+ rxdma_ctrl.bits.rd_finish_en = 0; -+ rxdma_ctrl.bits.rd_fail_en = 1; -+ rxdma_ctrl.bits.rd_perr_en = 1; -+ rxdma_ctrl.bits.rd_eod_en = 0; -+ rxdma_ctrl.bits.rd_eof_en = 0; -+ raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0xFFFFFFFF); -+ -+ // enable interrupt -+ dma_status.bits32 = 3; // enable RpInt -+ raid_write_reg(RAID_DMA_STATUS, dma_status.bits32,0xFFFFFFFF); -+ -+ return 0; -+} -+ -+module_init(gemini_xor_init); -+module_exit(gemini_xor_exit); -+ ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -187,6 +187,26 @@ - Say Y if you want support for the ARM926T processor. - Otherwise, say N. - -+###### for Storlink SoC ###### -+config CPU_FA526 -+ bool "FA526 processor" -+ depends on ARCH_SL2312 -+ default y -+ select CPU_32v4 -+ select CPU_ABRT_EV4 -+ select CPU_CACHE_FA -+ select CPU_CACHE_VIVT -+ select CPU_CP15_MMU -+ select CPU_COPY_FA -+ select CPU_TLB_FA -+ select CPU_FA_BTB -+ help -+ The FA526 is a version of the ARM9 compatible processor, but with smaller -+ instruction and data caches. It is used in Storlink Sword device family. -+ -+ Say Y if you want support for the FA526 processor. -+ Otherwise, say N. -+ - # ARM940T - config CPU_ARM940T - bool "Support ARM940T processor" if ARCH_INTEGRATOR -@@ -461,6 +481,9 @@ - config CPU_CACHE_VIPT - bool - -+config CPU_CACHE_FA -+ bool -+ - if MMU - # The copy-page model - config CPU_COPY_V3 -@@ -475,6 +498,12 @@ - config CPU_COPY_V6 - bool - -+config CPU_COPY_FA -+ bool -+ -+config CPU_FA_BTB -+ bool -+ - # This selects the TLB model - config CPU_TLB_V3 - bool -@@ -534,6 +563,14 @@ - config IO_36 - bool - -+config CPU_TLB_FA -+ bool -+ help -+ //TODO -+ Faraday ARM FA526 architecture, unified TLB with writeback cache -+ and invalidate instruction cache entry. Branch target buffer is also -+ supported. -+ - comment "Processor Features" - - config ARM_THUMB -@@ -600,7 +637,7 @@ - - config CPU_DCACHE_WRITETHROUGH - bool "Force write through D-cache" -- depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE -+ depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE - default y if CPU_ARM925T - help - Say Y here to use the data cache in writethrough mode. Unless you ---- a/arch/arm/mm/Makefile -+++ b/arch/arm/mm/Makefile -@@ -32,6 +32,7 @@ - obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o - obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o - obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o -+obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o - - obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o - obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o -@@ -40,6 +41,7 @@ - obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o - obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o - obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o -+obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o - - obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o - obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o -@@ -47,6 +49,7 @@ - obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o - obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o - obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o -+obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o - - obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o - obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o -@@ -60,6 +63,7 @@ - obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o - obj-$(CONFIG_CPU_ARM940T) += proc-arm940.o - obj-$(CONFIG_CPU_ARM946E) += proc-arm946.o -+obj-$(CONFIG_CPU_FA526) += proc-fa526.o - obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o - obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o - obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o ---- /dev/null -+++ b/arch/arm/mm/cache-fa.S -@@ -0,0 +1,400 @@ -+/* -+ * linux/arch/arm/mm/cache-fa.S -+ * -+ * Copyright (C) 2005 Faraday Corp. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * Processors: FA520 FA526 FA626 -+ * 03/31/2005 : Luke Lee created, modified from cache-v4wb.S -+ * 04/06/2005 : 1. Read CR0-1 and determine the cache size dynamically, -+ * to suit all Faraday CPU series -+ * 2. Fixed all functions -+ * 04/08/2005 : insert CONFIG_CPU_ICACHE_DISABLE and CONFIG_CPU_DCACHE_DISABLE -+ * 04/12/2005 : TODO: make this processor dependent or a self-modifying code to -+ * inline cache len/size info into the instructions, as reading cache -+ * size and len info in memory could cause another cache miss. -+ * 05/05/2005 : Modify fa_flush_user_cache_range to comply APCS. -+ * 05/19/2005 : Adjust for boundary conditions. -+ */ -+#include -+#include -+#include -+#include -+#include "proc-macros.S" -+ -+#define CACHE_DLINESIZE 16 -+#ifdef CONFIG_SL3516_ASIC -+#define CACHE_DSIZE 8192 -+#else -+#define CACHE_DSIZE 16384 -+#endif -+#define CACHE_ILINESIZE 16 -+#define CACHE_ISIZE 16384 -+ -+/* Luke Lee 04/06/2005 ins begin */ -+/* -+ * initialize_cache_info() -+ * -+ * Automatic detection of DSIZE, DLEN, ISIZE, ILEN variables according to -+ * system register CR0-1 -+ * Destroyed register: r0, r1, r2, r3, ip -+ */ -+ .align -+ENTRY(fa_initialize_cache_info) -+ mov r3, #1 @ r3 always = 1 -+ adr ip, __fa_cache_ilen -+ -+ mrc p15, 0, r0, c0, c0, 1 -+ /* ILEN */ -+ and r1, r0, #3 @ bits [1:0] -+ add r1, r1, #3 @ cache line size is at least 8 bytes (2^3) -+ mov r2, r3, lsl r1 @ r2 = 1<= limit? -+ bhs __flush_whole_cache @ flush whole D cache -+ -+ //debug_Aaron -+ bic r0, r0, #CACHE_DLINESIZE-1 -+ mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate boundary D entry -+ bic r1, r1, #CACHE_DLINESIZE-1 -+ mcr p15, 0, r1, c7, c14, 1 @ clean and invalidate boundary D entry -+ -+ -+1: /* Luke Lee 04/06/2005 del 2 ins 5 */ -+ -+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -+ mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry -+#else -+ mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry -+#endif -+ /* Luke Lee 04/06/2005 mod 1 */ -+ add r0, r0, #CACHE_DLINESIZE -+ cmp r0, r1 -+ bls 1b @ Luke Lee 05/19/2005 -+#endif /* CONFIG_CPU_DCACHE_DISABLE */ -+ -+#ifndef CONFIG_CPU_FA_WB_DISABLE -+ tst r2, #VM_EXEC -+ /* Luke Lee 04/06/2005 mod 1 tofix todo : ne->eq */ -+ mcreq p15, 0, r4, c7, c10, 4 @ drain write buffer -+#endif -+ -+ /* Luke Lee 04/06/2005 ins block */ -+#ifdef CONFIG_CPU_FA_BTB -+ tst r2, #VM_EXEC -+ mov ip, #0 -+ mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB -+ nop -+ nop -+#endif -+ mov pc, lr -+ -+/* -+ * flush_kern_dcache_page(void *page) -+ * -+ * Ensure no D cache aliasing occurs, either with itself or -+ * the I cache -+ * -+ * - addr - page aligned address -+ */ -+ENTRY(fa_flush_kern_dcache_page) -+ add r1, r0, #PAGE_SZ -+ /* fall through */ -+ -+/* -+ * coherent_kern_range(start, end) -+ * -+ * Ensure coherency between the Icache and the Dcache in the -+ * region described by start. If you have non-snooping -+ * Harvard caches, you need to implement this function. -+ * -+ * - start - virtual start address -+ * - end - virtual end address -+ */ -+ENTRY(fa_coherent_kern_range) -+ /* fall through */ -+ -+/* -+ * coherent_user_range(start, end) -+ * -+ * Ensure coherency between the Icache and the Dcache in the -+ * region described by start. If you have non-snooping -+ * Harvard caches, you need to implement this function. -+ * -+ * - start - virtual start address -+ * - end - virtual end address -+ */ -+ENTRY(fa_coherent_user_range) -+ -+/* Luke Lee 04/06/2005 mod ok */ -+ /* Luke Lee 04/06/2005 ins 3 mod 1 */ -+ bic r0, r0, #CACHE_DLINESIZE-1 -+ -+ //debug_Aaron -+ bic r0, r0, #CACHE_DLINESIZE-1 -+ mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate boundary D entry -+ bic r1, r1, #CACHE_DLINESIZE-1 -+ mcr p15, 0, r1, c7, c14, 1 @ clean and invalidate boundary D entry -+ -+#if !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE)) -+1: /* Luke Lee 04/06/2005 del 2 ins 5 mod 1 */ -+#ifndef CONFIG_CPU_DCACHE_DISABLE -+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -+ mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry -+#else -+ mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry -+#endif -+#endif /* CONFIG_CPU_DCACHE_DISABLE */ -+ -+#ifndef CONFIG_CPU_ICACHE_DISABLE -+ mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry -+#endif -+ add r0, r0, #CACHE_DLINESIZE -+ cmp r0, r1 -+ bls 1b @ Luke Lee 05/19/2005 blo->bls -+#endif /* !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE)) */ -+ -+ mov ip, #0 -+#ifdef CONFIG_CPU_FA_BTB -+ mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB -+ nop -+ nop -+#endif -+ -+/* Luke Lee 04/08/2005 ins 1 skp 1 ins 1 */ -+#ifndef CONFIG_CPU_FA_WB_DISABLE -+ mcr p15, 0, ip, c7, c10, 4 @ drain WB -+#endif -+ -+ mov pc, lr -+ -+/* -+ * dma_inv_range(start, end) -+ * -+ * Invalidate (discard) the specified virtual address range. -+ * May not write back any entries. If 'start' or 'end' -+ * are not cache line aligned, those lines must be written -+ * back. -+ * -+ * - start - virtual start address -+ * - end - virtual end address -+ */ -+ENTRY(fa_dma_inv_range) -+ -+/* Luke Lee 04/06/2005 mod ok */ -+ -+#ifndef CONFIG_CPU_DCACHE_DISABLE -+ -+ //debug_Aaron -+ bic r0, r0, #CACHE_DLINESIZE-1 -+ mcr p15, 0, r0, c7, c6, 1 @ invalidate boundary D entry -+ bic r1, r1, #CACHE_DLINESIZE-1 -+ mcr p15, 0, r1, c7, c6, 1 @ invalidate boundary D entry -+ -+ /* Luke Lee 04/06/2005 ins 4 mod 2 */ -+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH -+ tst r0, #CACHE_DLINESIZE -1 -+ bic r0, r0, #CACHE_DLINESIZE -1 -+ -+//debug_Aaron -+ //mcrne p15, 0, r0, c7, c10, 1 @ clean boundary D entry -+ -+ /* Luke Lee 04/06/2005 mod 1 */ -+ /* Luke Lee 05/19/2005 always clean the end-point boundary mcrne->mcr */ -+ ////tst r1, #CACHE_DLINESIZE -1 -+ //mcr p15, 0, r1, c7, c10, 1 @ clean boundary D entry -+ /* Luke Lee 04/06/2005 ins 1 */ -+#else -+ bic r0, r0, #CACHE_DLINESIZE -1 -+#endif -+ -+//debug_Aaron -+1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry -+//1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry -+ -+ /* Luke Lee 04/06/2005 mod 1 */ -+ add r0, r0, #CACHE_DLINESIZE -+ cmp r0, r1 -+ bls 1b @ Luke Lee 05/19/2005 blo->bls -+#endif /* CONFIG_CPU_DCACHE_DISABLE */ -+ -+ /* Luke Lee 04/06/2005 ins 1 */ -+#ifndef CONFIG_CPU_FA_WB_DISABLE -+ mov r0, #0 -+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer -+#endif -+ -+ mov pc, lr -+ -+/* -+ * dma_clean_range(start, end) -+ * -+ * Clean (write back) the specified virtual address range. -+ * -+ * - start - virtual start address -+ * - end - virtual end address -+ */ -+ENTRY(fa_dma_clean_range) -+ -+/* Luke Lee 04/06/2005 mod ok */ -+#ifndef CONFIG_CPU_DCACHE_DISABLE -+ -+ //debug_Aaron -+ bic r0, r0, #CACHE_DLINESIZE-1 -+ mcr p15, 0, r0, c7, c10, 1 @ clean boundary D entry -+ bic r1, r1, #CACHE_DLINESIZE-1 -+ mcr p15, 0, r1, c7, c10, 1 @ clean boundary D entry -+ -+ /* Luke Lee 04/06/2005 ins 4 mod 2 */ -+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH -+ bic r0, r0, #CACHE_DLINESIZE - 1 -+ -+//debug_Aaron -+1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry -+//1: mcr p15, 0, r0, c7, c14, 1 @ clean D entry -+ add r0, r0, #CACHE_DLINESIZE -+ cmp r0, r1 -+ bls 1b @ Luke Lee 05/19/2005 blo->bls -+ /* Luke Lee 04/06/2005 ins 2 */ -+#endif -+#endif /* CONFIG_CPU_DCACHE_DISABLE */ -+ -+#ifndef CONFIG_CPU_FA_WB_DISABLE -+ mov r0, #0 -+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer -+#endif -+ -+ mov pc, lr -+ -+/* -+ * dma_flush_range(start, end) -+ * -+ * Clean and invalidate the specified virtual address range. -+ * -+ * - start - virtual start address -+ * - end - virtual end address -+ * -+ * This is actually the same as fa_coherent_kern_range() -+ */ -+ .globl fa_dma_flush_range -+ .set fa_dma_flush_range, fa_coherent_kern_range -+ -+ __INITDATA -+ -+ .type fa_cache_fns, #object -+ENTRY(fa_cache_fns) -+ .long fa_flush_kern_cache_all -+ .long fa_flush_user_cache_all -+ .long fa_flush_user_cache_range -+ .long fa_coherent_kern_range -+ .long fa_coherent_user_range -+ .long fa_flush_kern_dcache_page -+ .long fa_dma_inv_range -+ .long fa_dma_clean_range -+ .long fa_dma_flush_range -+ .size fa_cache_fns, . - fa_cache_fns ---- /dev/null -+++ b/arch/arm/mm/copypage-fa.S -@@ -0,0 +1,106 @@ -+/* -+ * linux/arch/arm/lib/copypage-fa.S -+ * -+ * Copyright (C) 2005 Faraday Corp. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * ASM optimised string functions -+ * 05/18/2005 : Luke Lee created, modified from copypage-v4wb.S -+ */ -+#include -+#include -+#include -+ -+ .text -+/* -+ * ARMv4 optimised copy_user_page for Faraday processors -+ * -+ * We flush the destination cache lines just before we write the data into the -+ * corresponding address. Since the Dcache is read-allocate, this removes the -+ * Dcache aliasing issue. The writes will be forwarded to the write buffer, -+ * and merged as appropriate. -+ * -+ * Note: We rely on all ARMv4 processors implementing the "invalidate D line" -+ * instruction. If your processor does not supply this, you have to write your -+ * own copy_user_page that does the right thing. -+ * -+ * copy_user_page(to,from,vaddr) -+ */ -+ .align 4 -+ENTRY(fa_copy_user_page) -+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -+ /* Write through */ -+ stmfd sp!, {r4, lr} @ 2 -+ mov r2, #PAGE_SZ/32 @ 1 -+ -+ ldmia r1!, {r3, r4, ip, lr} @ 4 -+1: stmia r0!, {r3, r4, ip, lr} @ 4 -+ ldmia r1!, {r3, r4, ip, lr} @ 4+1 -+ subs r2, r2, #1 @ 1 -+ stmia r0!, {r3, r4, ip, lr} @ 4 -+ ldmneia r1!, {r3, r4, ip, lr} @ 4 -+ bne 1b @ 1 -+ -+ mcr p15, 0, r2, c7, c7, 0 @ flush ID cache -+ ldmfd sp!, {r4, pc} @ 3 -+#else -+ /* Write back */ -+ stmfd sp!, {r4, lr} @ 2 -+ mov r2, #PAGE_SZ/32 @ 1 -+ -+1: ldmia r1!, {r3, r4, ip, lr} @ 4 -+ mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line -+ stmia r0!, {r3, r4, ip, lr} @ 4 -+ ldmia r1!, {r3, r4, ip, lr} @ 4 -+ mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line -+ stmia r0!, {r3, r4, ip, lr} @ 4 -+ subs r2, r2, #1 @ 1 -+ bne 1b -+ mcr p15, 0, r2, c7, c10, 4 @ 1 drain WB -+ ldmfd sp!, {r4, pc} @ 3 -+#endif -+ -+/* -+ * ARMv4 optimised clear_user_page -+ * -+ * Same story as above. -+ */ -+ .align 4 -+ENTRY(fa_clear_user_page) -+ str lr, [sp, #-4]! -+ mov r1, #PAGE_SZ/32 @ 1 -+ mov r2, #0 @ 1 -+ mov r3, #0 @ 1 -+ mov ip, #0 @ 1 -+ mov lr, #0 @ 1 -+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -+ /* Write through */ -+1: stmia r0!, {r2, r3, ip, lr} @ 4 -+ stmia r0!, {r2, r3, ip, lr} @ 4 -+ subs r1, r1, #1 @ 1 -+ bne 1b @ 1 -+ -+ mcr p15, 0, r1, c7, c7, 0 @ flush ID cache -+ ldr pc, [sp], #4 -+#else -+ /* Write back */ -+1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line -+ stmia r0!, {r2, r3, ip, lr} @ 4 -+ mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line -+ stmia r0!, {r2, r3, ip, lr} @ 4 -+ subs r1, r1, #1 @ 1 -+ bne 1b @ 1 -+ mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB -+ ldr pc, [sp], #4 -+#endif -+ -+ __INITDATA -+ -+ .type fa_user_fns, #object -+ENTRY(fa_user_fns) -+ .long fa_clear_user_page -+ .long fa_copy_user_page -+ .size fa_user_fns, . - fa_user_fns ---- a/arch/arm/mm/init.c -+++ b/arch/arm/mm/init.c -@@ -23,6 +23,7 @@ - - #include - #include -+#include - - #include "mm.h" - -@@ -252,6 +253,11 @@ - initrd_end = initrd_start + phys_initrd_size; - } - #endif -+#ifdef CONFIG_GEMINI_IPI -+ printk("CPU ID:%d\n",getcpuid()); -+// reserve_bootmem_node(NODE_DATA(0), 0x400000, 0x400000); //CPU0 space -+// reserve_bootmem_node(NODE_DATA(0), SHAREADDR, SHARE_MEM_SIZE); //share memory -+#endif - - /* - * Finally, reserve any node zero regions. ---- /dev/null -+++ b/arch/arm/mm/proc-fa526.S -@@ -0,0 +1,407 @@ -+/* -+ * linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526 -+ * -+ * Copyright (C) 2005 Faraday Corp. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * -+ * These are the low level assembler for performing cache and TLB -+ * functions on the fa526. -+ * -+ * Written by : Luke Lee -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "proc-macros.S" -+ -+#define CACHE_DLINESIZE 16 -+ -+ .text -+/* -+ * cpu_fa526_proc_init() -+ */ -+ENTRY(cpu_fa526_proc_init) -+ /* MMU is already ON here, ICACHE, DCACHE conditionally disabled */ -+ -+ mov r0, #1 -+ nop -+ nop -+ mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR -+ nop -+ nop -+ -+ mrc p15, 0, r0, c1, c0, 0 @ read ctrl register -+ -+#ifdef CONFIG_CPU_FA_BTB -+ orr r0, r0, #CR_Z -+#else -+ bic r0, r0, #CR_Z -+#endif -+#ifdef CONFIG_CPU_FA_WB_DISABLE -+ mov r1, #0 -+ mcr p15, 0, r1, c7, c10, 4 @ drain write buffer -+ nop -+ nop -+ bic r0, r0, #CR_W -+#else -+ orr r0, r0, #CR_W -+#endif -+#ifdef CONFIG_CPU_DCACHE_DISABLE -+ bic r0, r0, #CR_C -+#else -+ orr r0, r0, #CR_C -+#endif -+#ifdef CONFIG_CPU_ICACHE_DISABLE -+ bic r0, r0, #CR_I -+#else -+ orr r0, r0, #CR_I -+#endif -+ -+ nop -+ nop -+ mcr p15, 0, r0, c1, c0, 0 -+ nop -+ nop -+ -+ mov r5, lr -+ bl fa_initialize_cache_info @ destroy r0~r4 -+ mov pc, r5 @ return -+ -+ -+/* -+ * cpu_fa526_proc_fin() -+ */ -+ENTRY(cpu_fa526_proc_fin) -+ stmfd sp!, {lr} -+ mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE -+ msr cpsr_c, ip -+ -+ bl fa_flush_kern_cache_all -+ mrc p15, 0, r0, c1, c0, 0 @ ctrl register -+ bic r0, r0, #0x1000 @ ...i............ -+ bic r0, r0, #0x000e @ ............wca. -+ mcr p15, 0, r0, c1, c0, 0 @ disable caches -+ -+ nop -+ nop -+ ldmfd sp!, {pc} -+ -+/* -+ * cpu_fa526_reset(loc) -+ * -+ * Perform a soft reset of the system. Put the CPU into the -+ * same state as it would be if it had been reset, and branch -+ * to what would be the reset vector. -+ * -+ * loc: location to jump to for soft reset -+ */ -+ .align 4 -+ENTRY(cpu_fa526_reset) -+ mov ip, #0 -+ mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches -+#ifndef CONFIG_CPU_FA_WB_DISABLE -+ mcr p15, 0, ip, c7, c10, 4 @ drain WB -+#endif -+ mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs -+ mrc p15, 0, ip, c1, c0, 0 @ ctrl register -+ bic ip, ip, #0x000f @ ............wcam -+ bic ip, ip, #0x1100 @ ...i...s........ -+ -+ bic ip, ip, #0x0800 @ BTB off -+ mcr p15, 0, ip, c1, c0, 0 @ ctrl register -+ nop -+ nop -+ mov pc, r0 -+ -+/* -+ * cpu_fa526_do_idle() -+ */ -+ .align 4 -+ENTRY(cpu_fa526_do_idle) -+ -+#ifdef CONFIG_CPU_FA_IDLE -+ nop -+ nop -+ mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt (IDLE mode) -+#endif -+ mov pc, lr -+ -+ -+ENTRY(cpu_fa526_dcache_clean_area) -+ -+#ifndef CONFIG_CPU_DCACHE_DISABLE -+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH -+1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry -+ add r0, r0, #CACHE_DLINESIZE -+ subs r1, r1, #CACHE_DLINESIZE -+ bhi 1b -+#endif -+#endif -+ mov pc, lr -+ -+ -+/* =============================== PageTable ============================== */ -+ -+/* -+ * cpu_fa526_switch_mm(pgd) -+ * -+ * Set the translation base pointer to be as described by pgd. -+ * -+ * pgd: new page tables -+ */ -+ .align 4 -+ -+ .globl fault_address -+fault_address: -+ .long 0 -+ -+ENTRY(cpu_fa526_switch_mm) -+ -+ mov ip, #0 -+#ifndef CONFIG_CPU_DCACHE_DISABLE -+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -+ mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache -+#else -+ mcr p15, 0, ip, c7, c14, 0 @ Clean and invalidate whole DCache -+#endif -+#endif /*CONFIG_CPU_DCACHE_DISABLE*/ -+ -+#ifndef CONFIG_CPU_ICACHE_DISABLE -+ mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache -+#endif -+ -+#ifndef CONFIG_CPU_FA_WB_DISABLE -+ mcr p15, 0, ip, c7, c10, 4 @ drain WB -+#endif -+ -+#ifdef CONFIG_CPU_FA_BTB -+ mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed -+ nop -+ nop -+#endif -+ bic r0, r0, #0xff @ clear bits [7:0] -+ bic r0, r0, #0x3f00 @ clear bits [13:8] -+ mcr p15, 0, r0, c2, c0, 0 @ load page table pointer -+ mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB -+ nop -+ nop -+ mov pc, lr -+ -+/* -+ * cpu_fa526_set_pte_ext(ptep, pte, ext) -+ * -+ * Set a PTE and flush it out -+ */ -+ .align 4 -+ENTRY(cpu_fa526_set_pte_ext) -+ str r1, [r0], #-2048 @ linux version -+ -+ eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY -+ -+ bic r2, r1, #PTE_SMALL_AP_MASK -+ bic r2, r2, #PTE_TYPE_MASK -+ orr r2, r2, #PTE_TYPE_SMALL -+ -+ tst r1, #L_PTE_USER @ User? -+ orrne r2, r2, #PTE_SMALL_AP_URO_SRW -+ -+ tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? -+ orreq r2, r2, #PTE_SMALL_AP_UNO_SRW -+ -+ tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? -+ movne r2, #0 -+ -+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -+ eor r3, r2, #0x0a @ C & small page? 1010 -+ tst r3, #0x0b @ 1011 -+ biceq r2, r2, #4 -+#endif -+ str r2, [r0] @ hardware version -+ -+ mov r2, #0 -+ mcr p15, 0, r2, c7, c10, 0 @ clean D cache all -+ -+#ifndef CONFIG_CPU_FA_WB_DISABLE -+ mcr p15, 0, r2, c7, c10, 4 @ drain WB -+#endif -+#ifdef CONFIG_CPU_FA_BTB -+ mcr p15, 0, r2, c7, c5, 6 @ invalidate BTB -+ nop -+ nop -+#endif -+ mov pc, lr -+ -+ __INIT -+ -+ .type __fa526_setup, #function -+__fa526_setup: -+ /* On return of this routine, r0 must carry correct flags for CFG register */ -+ mov r0, #0 -+ mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 -+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 -+ mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 -+ -+ mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM -+ -+ mov r0, #1 -+ mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR -+ -+ mrc p15, 0, r0, c9, c1, 0 @ DScratchpad -+ bic r0, r0, #1 -+ mcr p15, 0, r0, c9, c1, 0 -+ mrc p15, 0, r0, c9, c1, 1 @ IScratchpad -+ bic r0, r0, #1 -+ mcr p15, 0, r0, c9, c1, 1 -+ -+ mov r0, #0 -+ mcr p15, 0, r0, c1, c1, 0 @ turn-off ECR -+ -+#ifdef CONFIG_CPU_FA_BTB -+ mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All -+ nop -+ nop -+#endif -+ -+ mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client -+ mcr p15, 0, r0, c3, c0 @ load domain access register -+ -+ mrc p15, 0, r0, c1, c0 @ get control register v4 -+ ldr r5, fa526_cr1_clear -+ bic r0, r0, r5 -+ ldr r5, fa526_cr1_set -+ orr r0, r0, r5 -+ -+#ifdef CONFIG_CPU_FA_BTB -+ orr r0, r0, #CR_Z -+#else -+ bic r0, r0, #CR_Z -+#endif -+#ifdef CONFIG_CPU_FA_WB_DISABLE -+ mov r12, #0 -+ mcr p15, 0, r12, c7, c10, 4 @ drain write buffer -+ nop -+ nop -+ bic r0, r0, #CR_W @ .... .... .... 1... -+#else -+ orr r0, r0, #CR_W -+#endif -+ -+ mov pc, lr -+ .size __fa526_setup, . - __fa526_setup -+ -+ /* -+ * .RVI ZFRS BLDP WCAM -+ * ..11 0001 .111 1101 -+ * -+ */ -+ .type fa526_cr1_clear, #object -+ .type fa526_cr1_set, #object -+fa526_cr1_clear: -+ .word 0x3f3f -+fa526_cr1_set: -+ .word 0x317D -+ -+ __INITDATA -+ -+/* -+ * Purpose : Function pointers used to access above functions - all calls -+ * come through these -+ */ -+ .type fa526_processor_functions, #object -+fa526_processor_functions: -+ .word v4_early_abort -+ .word cpu_fa526_proc_init -+ .word cpu_fa526_proc_fin -+ .word cpu_fa526_reset -+ .word cpu_fa526_do_idle -+ .word cpu_fa526_dcache_clean_area -+ .word cpu_fa526_switch_mm -+ .word cpu_fa526_set_pte_ext -+ .size fa526_processor_functions, . - fa526_processor_functions -+ -+ .section ".rodata" -+ -+ .type cpu_arch_name, #object -+cpu_arch_name: -+ .asciz "armv4" -+ .size cpu_arch_name, . - cpu_arch_name -+ -+ .type cpu_elf_name, #object -+cpu_elf_name: -+ .asciz "v4" -+ .size cpu_elf_name, . - cpu_elf_name -+ -+ .type cpu_fa526_name, #object -+cpu_fa526_name: -+ .ascii "FA526" -+#ifndef CONFIG_CPU_ICACHE_DISABLE -+ .ascii "i" -+#endif -+#ifndef CONFIG_CPU_DCACHE_DISABLE -+ .ascii "d" -+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -+ .ascii "(wt)" -+#else -+ .ascii "(wb)" -+#endif -+#endif -+ .ascii "\0" -+ .size cpu_fa526_name, . - cpu_fa526_name -+ -+ .align -+ -+ .section ".proc.info.init", #alloc, #execinstr -+ -+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -+#define __PMD_SECT_BUFFERABLE 0 -+#else -+#define __PMD_SECT_BUFFERABLE PMD_SECT_BUFFERABLE -+#endif -+ -+ .type __fa526_proc_info,#object -+__fa526_proc_info: -+ .long 0x66015261 -+ .long 0xff01fff1 -+ .long PMD_TYPE_SECT | \ -+ __PMD_SECT_BUFFERABLE | \ -+ PMD_SECT_CACHEABLE | \ -+ PMD_BIT4 | \ -+ PMD_SECT_AP_WRITE | \ -+ PMD_SECT_AP_READ -+ .long PMD_TYPE_SECT | \ -+ PMD_BIT4 | \ -+ PMD_SECT_AP_WRITE | \ -+ PMD_SECT_AP_READ -+ b __fa526_setup -+ .long cpu_arch_name -+ .long cpu_elf_name -+ .long HWCAP_SWP | HWCAP_HALF -+ .long cpu_fa526_name -+ .long fa526_processor_functions -+ .long fa_tlb_fns -+ .long fa_user_fns -+ .long fa_cache_fns -+ .size __fa526_proc_info, . - __fa526_proc_info -+ -+ ---- /dev/null -+++ b/arch/arm/mm/tlb-fa.S -@@ -0,0 +1,96 @@ -+/* -+ * linux/arch/arm/mm/tlb-fa.S -+ * -+ * Copyright (C) 2005 Faraday Corp. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * ARM architecture version 4, Faraday variation. -+ * This assume an unified TLBs, with a write buffer, and branch target buffer (BTB) -+ * -+ * Processors: FA520 FA526 FA626 -+ * 03/31/2005 : Created by Luke Lee, modified from tlb-v4wbi.S -+ * 05/06/2005 : Fixed buggy CPU versions that did not invalidate the associated -+ * data cache entries when invalidating TLB entries. -+ */ -+#include -+#include -+#include -+#include -+#include "proc-macros.S" -+ -+ -+/* -+ * flush_user_tlb_range(start, end, mm) -+ * -+ * Invalidate a range of TLB entries in the specified address space. -+ * -+ * - start - range start address -+ * - end - range end address -+ * - mm - mm_struct describing address space -+ */ -+ .align 4 -+ENTRY(fa_flush_user_tlb_range) -+ -+ vma_vm_mm ip, r2 -+ act_mm r3 @ get current->active_mm -+ eors r3, ip, r3 @ == mm ? -+ movne pc, lr @ no, we dont do anything -+ mov r3, #0 -+ -+#ifndef CONFIG_CPU_FA_WB_DISABLE -+ mcr p15, 0, r3, c7, c10, 4 @ drain WB -+#endif -+ -+ vma_vm_flags r2, r2 -+ bic r0, r0, #0x0ff -+ bic r0, r0, #0xf00 -+ -+1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry -+ add r0, r0, #PAGE_SZ -+ cmp r0, r1 -+ bls 1b @ Luke Lee 05/19/2005 blo -> bls -+ -+#ifdef CONFIG_CPU_FA_BTB -+ mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB -+ nop -+ nop -+#endif -+ mov pc, lr -+ -+ -+ENTRY(fa_flush_kern_tlb_range) -+ mov r3, #0 -+ -+ mcr p15, 0, r3, c7, c10, 0 @ clean Dcache all 06/03/2005 -+ -+#ifndef CONFIG_CPU_FA_WB_DISABLE -+ mcr p15, 0, r3, c7, c10, 4 @ drain WB -+#endif -+ -+ bic r0, r0, #0x0ff -+ bic r0, r0, #0xf00 -+1: -+ mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry -+ add r0, r0, #PAGE_SZ -+ cmp r0, r1 -+ bls 1b @ Luke Lee 05/19/2005 blo -> bls -+ -+#ifdef CONFIG_CPU_FA_BTB -+ mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB -+ nop -+ nop -+#endif -+ mov pc, lr -+ -+ -+ __INITDATA -+ -+ .type fa_tlb_fns, #object -+ENTRY(fa_tlb_fns) -+ .long fa_flush_user_tlb_range -+ .long fa_flush_kern_tlb_range -+ .long fa_tlb_flags -+ .size fa_tlb_fns, . - fa_tlb_fns ---- a/arch/arm/tools/mach-types -+++ b/arch/arm/tools/mach-types -@@ -208,7 +208,8 @@ - fester SA1100_FESTER FESTER 191 - gpi ARCH_GPI GPI 192 - smdk2410 ARCH_SMDK2410 SMDK2410 193 --i519 ARCH_I519 I519 194 -+#i519 ARCH_I519 I519 194 -+sl2312 ARCH_SL2312 SL2312 194 - nexio SA1100_NEXIO NEXIO 195 - bitbox SA1100_BITBOX BITBOX 196 - g200 SA1100_G200 G200 197 ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/SL_gpio.h -@@ -0,0 +1,59 @@ -+#define GPIO_MINOR_LAST 31 -+#define GPIO_MAJOR 120 // Experiemental -+ -+#define GPIO_IRQ_NBR 12 -+ -+#define GPIOBASEADDR (IO_ADDRESS(0x021000000)) -+ -+#define GPIODATAOUTOFF 0x00 -+#define GPIODATAINOFF 0x04 -+#define GPIOPINDIROFF 0x08 -+#define GPIOPINBYPASSOFF 0x0C -+#define GPIODATASETOFF 0x10 -+#define GPIODATACLEAROFF 0x14 -+#define GPIOPINPULLENBOFF 0x18 -+#define GPIOPINPULLTPOFF 0x1C -+#define GPIOINTRENBOFF 0x20 -+#define GPIOINTRRAWSOFF 0x24 -+#define GPIOINTRMASKEDSTATEOFF 0x28 -+#define GPIOINTRMASKOFF 0x2C -+#define GPIOINTRCLEAROFF 0x30 -+#define GPIOINTRTRIGGEROFF 0x34 -+#define GPIOINTRBOTHOFF 0x38 -+#define GPIOINTRRISENEGOFF 0x3C -+#define GPIOBNCEENBOFF 0x40 -+#define GPIOBNCEPRESOFF 0x44 -+ -+#define GPIO_IOCTRL_SETDIR 0x20 -+#define GPIO_IOCTRL_SET 0x40 -+#define GPIO_IOCTRL_CLEAR 0x50 -+#define GPIO_IOCTRL_ENBINT 0x60 -+#define GPIO_IOCTRL_MASKINT 0x70 -+#define GPIO_IOCTRL_LVLTRIG 0x75 -+#define GPIO_IOCTRL_EDGINT 0x77 -+#define GPIO_IOCTRL_EDGPOLINT 0x78 -+#define GPIO_IOCTRL_BYPASS 0x30 -+#define GPIO_IOCTRL_PRESCLK 0x80 -+#define GPIO_IOCTRL_CLKVAL 0x90 -+#define GPIO_IOCTRL_PULLENB 0xA0 -+#define GPIO_IOCTRL_PULLTYPE 0xA8 -+ -+ -+#define GPIO_MAJOR 120 /* experimental MAJOR number */ -+ // Minor - 0 : 31 gpio pins -+ -+#define GPIO_SET 0x01 -+#define GPIO_CLEAR 0x01 -+ -+#define GPIO_INPUT 0 -+#define GPIO_OUTPUT 1 -+#define GPIO_EDGEINTR 0 -+#define GPIO_EDGESINGL 0 -+#define GPIO_EDGEBOTH 1 -+#define GPIO_POSITIVE 0 -+#define GPIO_ENBINT 1 -+#define GPIO_DISABLEMASK 1 -+#define GPIO_PULLDOWN 0 -+#define GPIO_PULLUP 1 -+#define GPIO_ENABLEPULL 1 -+#define GPIO_DISABLEPULL 0 ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/debug-macro.S -@@ -0,0 +1,20 @@ -+/* linux/include/asm-arm/arch-ebsa110/debug-macro.S -+ * -+ * Debugging macro include header -+ * -+ * Copyright (C) 1994-1999 Russell King -+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+**/ -+ -+ .macro addruart,rx -+ mov \rx, #0x42000000 -+ .endm -+ -+#define UART_SHIFT 2 -+#define FLOW_CONTROL -+#include ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/dma.h -@@ -0,0 +1,28 @@ -+/* -+ * linux/include/asm-arm/arch-camelot/dma.h -+ * -+ * Copyright (C) 1997,1998 Russell King -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_DMA_H -+#define __ASM_ARCH_DMA_H -+ -+#define MAX_DMA_ADDRESS 0xffffffff -+ -+#define MAX_DMA_CHANNELS 0 -+ -+#endif /* _ASM_ARCH_DMA_H */ -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/entry-macro.S -@@ -0,0 +1,42 @@ -+/* -+ * include/asm-arm/arch-arm/entry-macro.S -+ * -+ * Low-level IRQ helper macros for ebsa110 platform. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+#include -+#include -+ -+ -+ .macro disable_fiq -+ .endm -+ -+ .macro get_irqnr_preamble, base, tmp -+ .endm -+ -+ .macro arch_ret_to_user, tmp1, tmp2 -+ .endm -+ -+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -+ ldr \irqstat, =IRQ_STATUS(IO_ADDRESS(SL2312_INTERRUPT_BASE)) -+ ldr \irqnr,[\irqstat] -+ cmp \irqnr,#0 -+ beq 2313f -+ mov \tmp,\irqnr -+ mov \irqnr,#0 -+2312: -+ tst \tmp, #1 -+ bne 2313f -+ add \irqnr, \irqnr, #1 -+ mov \tmp, \tmp, lsr #1 -+ cmp \irqnr, #31 -+ bcc 2312b -+2313: -+ .endm -+ -+ .macro irq_prio_table -+ .endm -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/flash.h -@@ -0,0 +1,83 @@ -+#ifndef __ASM_ARM_ARCH_FLASH_H -+#define __ASM_ARM_ARCH_FLASH_H -+ -+#define FLASH_START SL2312_FLASH_BASE -+#define SFLASH_SIZE 0x00400000 -+#define SPAGE_SIZE 0x200 -+#define BLOCK_ERASE 0x50 -+#define BUFFER1_READ 0x54 -+#define BUFFER2_READ 0x56 -+#define PAGE_ERASE 0x81 -+#define MAIN_MEMORY_PAGE_READ 0x52 -+#define MAIN_MEMORY_PROGRAM_BUFFER1 0x82 -+#define MAIN_MEMORY_PROGRAM_BUFFER2 0x85 -+#define BUFFER1_TO_MAIN_MEMORY 0x83 -+#define BUFFER2_TO_MAIN_MEMORY 0x86 -+#define MAIN_MEMORY_TO_BUFFER1 0x53 -+#define MAIN_MEMORY_TO_BUFFER2 0x55 -+#define BUFFER1_WRITE 0x84 -+#define BUFFER2_WRITE 0x87 -+#define AUTO_PAGE_REWRITE_BUFFER1 0x58 -+#define AUTO_PAGE_REWRITE_BUFFER2 0x59 -+#define READ_STATUS 0x57 -+ -+#define MAIN_MEMORY_PAGE_READ_SPI 0xD2 -+#define BUFFER1_READ_SPI 0xD4 -+#define BUFFER2_READ_SPI 0xD6 -+#define READ_STATUS_SPI 0xD7 -+ -+#define FLASH_ACCESS_OFFSET 0x00000010 -+#define FLASH_ADDRESS_OFFSET 0x00000014 -+#define FLASH_WRITE_DATA_OFFSET 0x00000018 -+#define FLASH_READ_DATA_OFFSET 0x00000018 -+#define SERIAL_FLASH_CHIP1_EN 0x00010000 // 16th bit = 1 -+#define SERIAL_FLASH_CHIP0_EN 0x00000000 // 16th bit = 0 -+#define AT45DB321_PAGE_SHIFT 0xa -+#define AT45DB642_PAGE_SHIFT 0xb -+#define CONTINUOUS_MODE 0x00008000 -+ -+#define FLASH_ACCESS_ACTION_OPCODE 0x0000 -+#define FLASH_ACCESS_ACTION_OPCODE_DATA 0x0100 -+#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS 0x0200 -+#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA 0x0300 -+#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_X_DATA 0x0400 -+#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_2X_DATA 0x0500 -+#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_3X_DATA 0x0600 -+#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA 0x0700 -+//#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_X_DATA 0x0600 -+//#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA 0x0700 -+ -+#define M25P80_PAGE_SIZE 0x100 -+#define M25P80_SECTOR_SIZE 0x10000 -+ -+ -+//#define M25P80_BULK_ERASE 1 -+//#define M25P80_SECTOR_ERASE 2 -+//#define M25P80_SECTOR_SIZE 0x10000 -+ -+#define M25P80_WRITE_ENABLE 0x06 -+#define M25P80_WRITE_DISABLE 0x04 -+#define M25P80_READ_STATUS 0x05 -+#define M25P80_WRITE_STATUS 0x01 -+#define M25P80_READ 0x03 -+#define M25P80_FAST_READ 0x0B -+#define M25P80_PAGE_PROGRAM 0x02 -+#define M25P80_SECTOR_ERASE 0xD8 -+#define M25P80_BULK_ERASE 0xC7 -+#define FLASH_ERR_OK 0x0 -+ -+extern void address_to_page(__u32, __u16 *, __u16 *); -+extern void main_memory_page_read(__u8, __u16, __u16, __u8 *); -+extern void buffer_to_main_memory(__u8, __u16); -+extern void main_memory_to_buffer(__u8, __u16); -+extern void main_memory_page_program(__u8, __u16, __u16, __u8); -+extern void atmel_flash_read_page(__u32, __u8 *, __u32); -+extern void atmel_erase_page(__u8, __u16); -+extern void atmel_read_status(__u8, __u8 *); -+extern void atmel_flash_program_page(__u32, __u8 *, __u32); -+extern void atmel_buffer_write(__u8, __u16, __u8); -+extern void flash_delay(void); -+ -+extern int m25p80_sector_erase(__u32 address, __u32 schip_en); -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/gemini_cir.h -@@ -0,0 +1,102 @@ -+#ifndef _ASM_ARCH_CIR_H -+#define _ASM_ARCH_CIR_H -+#include -+ -+#define VCR_KEY_POWER 0x613E609F -+#define TV1_KEY_POWER 0x40040100 -+#define TV1_KEY_POWER_EXT 0xBCBD -+#define RC5_KER_POWER 0x0CF3 -+ -+#define VCC_H_ACT_PER (16-1) -+#define VCC_L_ACT_PER (8-1) -+#define VCC_DATA_LEN (32-1) -+#define TV1_H_ACT_PER (8-1) -+#define TV1_L_ACT_PER (4-1) -+#define TV1_DATA_LEN (48-1) -+ -+#define VCC_BAUD 540 -+#define TV1_BAUD 430 -+#ifdef CONFIG_SL3516_ASIC -+#define EXT_CLK 60 -+#else -+#define EXT_CLK 20 -+#endif -+ -+#define NEC_PROTOCOL 0x0 -+#define RC5_PROTOCOL 0x1 -+#define VCC_PROTOCOL 0x0 -+#define TV1_PROTOCOL 0x01 -+ -+#ifndef SL2312_CIR_BASE -+#define SL2312_CIR_BASE 0x4C000000 -+#endif -+#define CIR_BASE_ADDR IO_ADDRESS(SL2312_CIR_BASE) -+#define STORLINK_CIR_ID 0x00010400 -+ -+#define CIR_IP_ID *(volatile unsigned int *)(CIR_BASE_ADDR + 0x00) -+#define CIR_CTR_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x04) -+#define CIR_STATUS_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x08) -+#define CIR_RX_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x0C) -+#define CIR_RX_EXT_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x10) -+#define CIR_PWR_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x14) -+#define CIR_PWR_EXT_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x18) -+#define CIR_TX_CTR_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x1C) -+#define CIR_TX_FEQ_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x20) -+#define CIR_TX_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x24) -+#define CIR_TX_EXT_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x28) -+ -+ -+#ifndef SL2312_POWER_CTRL_BASE -+#define SL2312_POWER_CTRL_BASE 0x4B000000 -+#endif -+ -+#ifndef PWR_BASE_ADDR -+#define PWR_BASE_ADDR IO_ADDRESS(SL2312_POWER_CTRL_BASE) -+#endif -+#define PWR_CTRL_ID *(unsigned int*)(PWR_BASE_ADDR+0x00) -+#define PWR_CTRL_REG *(unsigned int*)(PWR_BASE_ADDR+0x04) -+#define PWR_STATUS_REG *(unsigned int*)(PWR_BASE_ADDR+0x08) -+ -+ -+#define BIT(x) (1< -+ * -+ * Copyright 2005 Storlink Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#ifndef __GEMINI_GPIO_H -+#define __GEMINI_GPIO_H -+ -+#include -+ -+#define STATUS_HIGH 1 -+#define STATUS_LOW 0 -+#define DIRECT_OUT 1 -+#define DIRECT_IN 0 -+ -+#define EDGE_TRIG 0 -+#define RISING_EDGE 0 -+#define FALL_EDGE 1 -+#define SINGLE_EDGE 0 -+#define BOTH_EDGE 1 -+ -+#define LEVEL_TRIG 1 -+#define HIGH_ACTIVE 0 -+#define LOW_ACTIVE 1 -+ -+struct gemini_gpio_ioctl_data { -+ __u32 pin; -+ __u8 status; // status or pin direction -+ // 0: status low or Input -+ // 1: status high or Output -+ -+ /* these member are used to config GPIO interrupt parameter */ -+ __u8 use_default; // if not sure ,set this argument 1 -+ __u8 trig_type; // 0/1:edge/level triger ? -+ __u8 trig_polar; // 0/1:rising/falling high/low active ? -+ __u8 trig_both; // 0/1:single/both detect both ? -+}; -+ -+#define GEMINI_GPIO_IOCTL_BASE 'Z' -+ -+#define GEMINI_SET_GPIO_PIN_DIR _IOW (GEMINI_GPIO_IOCTL_BASE,16, struct gemini_gpio_ioctl_data) -+#define GEMINI_SET_GPIO_PIN_STATUS _IOW (GEMINI_GPIO_IOCTL_BASE,17, struct gemini_gpio_ioctl_data) -+#define GEMINI_GET_GPIO_PIN_STATUS _IOWR(GEMINI_GPIO_IOCTL_BASE,18, struct gemini_gpio_ioctl_data) -+#define GEMINI_WAIT_GPIO_PIN_INT _IOWR(GEMINI_GPIO_IOCTL_BASE,19, struct gemini_gpio_ioctl_data) -+ -+ -+extern void init_gpio_int(__u32 pin,__u8 trig_type,__u8 trig_polar,__u8 trig_both); -+extern int request_gpio_irq(int bit,void (*handler)(int),char level,char high,char both); -+extern int free_gpio_irq(int bit); -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/gemini_i2s.h -@@ -0,0 +1,169 @@ -+#ifndef __GEMINI_I2S_H__ -+#define __GEMINI_I2S_H__ -+#include -+#include -+#include -+ -+typedef __u16 UINT16; -+typedef __u32 UINT32; -+typedef __u8 UINT8; -+typedef __u8 BOOL; -+ -+/***************************************/ -+/* define GPIO module base address */ -+/***************************************/ -+#define DMA_CONTROL_PHY_BASE (IO_ADDRESS(SL2312_GENERAL_DMA_BASE)) -+#define DMA_CONTROL_SSP_BASE (IO_ADDRESS(SL2312_SSP_CTRL_BASE)) -+#define SSP_INT IRQ_SSP -+#define GPIO_BASE_ADDR (IO_ADDRESS(SL2312_GPIO_BASE)) -+#define GPIO_BASE_ADDR1 (IO_ADDRESS(SL2312_GPIO_BASE1)) -+#define GLOBAL_BASE (IO_ADDRESS(SL2312_GLOBAL_BASE)) -+ -+/* define read/write register utility */ -+#define READ_SSP_REG(offset) (__raw_readl(offset+DMA_CONTROL_SSP_BASE)) -+#define WRITE_SSP_REG(offset,val) (__raw_writel(val,offset+DMA_CONTROL_SSP_BASE)) -+ -+#define READ_GPIO_REG(offset) (__raw_readl(offset+GPIO_BASE_ADDR)) -+#define WRITE_GPIO_REG(offset,val) (__raw_writel(val,offset+GPIO_BASE_ADDR)) -+ -+#define READ_GPIO1_REG(offset) (__raw_readl(offset+GPIO_BASE_ADDR1)) -+#define WRITE_GPIO1_REG(offset,val) (__raw_writel(val,offset+GPIO_BASE_ADDR1)) -+ -+#define READ_DMA_REG(offset) (__raw_readl(offset+DMA_CONTROL_PHY_BASE)) -+#define WRITE_DMA_REG(offset,val) (__raw_writel(val,offset+DMA_CONTROL_PHY_BASE)) -+ -+#define READ_GLOBAL_REG(offset) (__raw_readl(offset+GLOBAL_BASE)) -+#define WRITE_GLOBAL_REG(offset,val) (__raw_writel(val,offset+GLOBAL_BASE)) -+ -+#define SSP_GPIO_INT IRQ_GPIO -+ -+#ifndef CONFIG_SL3516_ASIC -+#define SSP_GPIO_INT_BIT 0x00000400 //GPIO[10] : SLIC interrupt pin -+ -+#define GPIO_EECK 0x00000040 /* SCK: GPIO[06] */ -+#define GPIO_EECS 0x00000080 /* SCS: GPIO[07] */ -+#define GPIO_MISO 0x00000200 /* SDO: GPIO[09] receive from 6996*/ -+#define GPIO_MOSI 0x00000100 /* SDI: GPIO[08] send to 6996*/ -+#define GPIO_MISO_BIT 9 -+#else -+#define SSP_GPIO_INT_BIT 0x00000001 //GPIO[0] : SLIC interrupt pin -+ -+//#if 0 -+//#define GPIO_EECK 0x80000000 /* SCK: GPIO1[31] */ -+//#define GPIO_EECS 0x40000000 /* SCS: GPIO1[30] */ -+//#define GPIO_MISO 0x20000000 /* SDO: GPIO1[29] receive from 6996*/ -+//#define GPIO_MOSI 0x10000000 /* SDI: GPIO1[28] send to 6996*/ -+//#define GPIO_MISO_BIT 29 -+//#else -+//#define GPIO_EECK 0x00000100 /* SCK: GPIO1[08] */ -+//#define GPIO_EECS 0x08000000 /* SCS: GPIO1[27] */ -+//#define GPIO_MISO 0x00000080 /* SDO: GPIO1[07] receive from 6996*/ -+//#define GPIO_MOSI 0x00000200 /* SDI: GPIO1[09] send to 6996*/ -+//#define GPIO_MISO_BIT 7 -+//#endif -+#endif -+ -+ -+enum GPIO_REG -+{ -+ GPIO_DATA_OUT = 0x00, -+ GPIO_DATA_IN = 0x04, -+ GPIO_PIN_DIR = 0x08, -+ GPIO_BY_PASS = 0x0c, -+ GPIO_DATA_SET = 0x10, -+ GPIO_DATA_CLEAR = 0x14, -+ GPIO_INT_ENABLE = 0x20, -+ GPIO_INT_RAWSTATE = 0x24, -+ GPIO_INT_MASKSTATE = 0x28, -+ GPIO_INT_MASK = 0x2C, -+ GPIO_INT_CLEAR = 0x30, -+ GPIO_INT_TRIGGER = 0x34, -+ GPIO_INT_BOTH = 0x38, -+ GPIO_INT_POLARITY = 0x3C -+}; -+ -+typedef struct -+{ -+ UINT32 src_addr; -+ UINT32 dst_addr; -+ UINT32 llp; -+ UINT32 ctrl_size; -+ UINT32 owner; -+}DMA_LLP_t; -+ -+typedef struct -+{ -+ UINT32 owner; -+ UINT32 src_addr; -+ UINT32 ctrl_size; -+}IOCTL_LLP_t; -+ -+typedef unsigned char byte; -+typedef unsigned short word; -+typedef unsigned long dword; -+ -+/* DMA Registers */ -+#define DMA_INT 0x00000000 -+#define DMA_INT_TC 0x00000004 -+#define DMA_CFG 0x00000024 -+#define DMA_INT_TC_CLR 0x00000008 -+#define DMA_TC 0x00000014 -+#define DMA_CSR 0x00000024 -+#define DMA_SYNC 0x00000028 -+ -+#define DMA_CH2_CSR 0x00000140 -+#define DMA_CH2_CFG 0x00000144 -+#define DMA_CH2_SRC_ADDR 0x00000148 -+#define DMA_CH2_DST_ADDR 0x0000014c -+#define DMA_CH2_LLP 0x00000150 -+#define DMA_CH2_SIZE 0x00000154 -+ -+#define DMA_CH3_CSR 0x00000160 -+#define DMA_CH3_CFG 0x00000164 -+#define DMA_CH3_SRC_ADDR 0x00000168 -+#define DMA_CH3_DST_ADDR 0x0000016c -+#define DMA_CH3_LLP 0x00000170 -+#define DMA_CH3_SIZE 0x00000174 -+ -+#define SSP_DEVICE_ID 0x00 -+#define SSP_CTRL_STATUS 0x04 -+#define SSP_FRAME_CTRL 0x08 -+#define SSP_BAUD_RATE 0x0c -+#define SSP_FRAME_CTRL2 0x10 -+#define SSP_FIFO_CTRL 0x14 -+#define SSP_TX_SLOT_VALID0 0x18 -+#define SSP_TX_SLOT_VALID1 0x1c -+#define SSP_TX_SLOT_VALID2 0x20 -+#define SSP_TX_SLOT_VALID3 0x24 -+#define SSP_RX_SLOT_VALID0 0x28 -+#define SSP_RX_SLOT_VALID1 0x2c -+#define SSP_RX_SLOT_VALID2 0x30 -+#define SSP_RX_SLOT_VALID3 0x34 -+#define SSP_SLOT_SIZE0 0x38 -+#define SSP_SLOT_SIZE1 0x3c -+#define SSP_SLOT_SIZE2 0x40 -+#define SSP_SLOT_SIZE3 0x44 -+#define SSP_READ_PORT 0x48 -+#define SSP_WRITE_PORT 0x4c -+ -+ -+ -+#define SSP_I2S_INIT_BUF _IO ('q', 0x00) -+#define SSP_I2S_STOP_DMA _IO ('q', 0x01) -+#define SSP_I2S_FILE_LEN _IOW ('q', 0x2, int) -+/* -+#define SSP_GET_HOOK_STATUS _IOR ('q', 0xC0, int) -+#define SSP_GET_LINEFEED _IOR ('q', 0xC1, int) -+#define SSP_SET_LINEFEED _IOW ('q', 0xC2, int) -+#define SSP_GET_REG _IOWR ('q', 0xC3, struct Ssp_reg *) -+#define SSP_SET_REG _IOWR ('q', 0xC4, struct Ssp_reg *) -+#define SSP_GEN_OFFHOOK_TONE _IO ('q', 0xC5) -+#define SSP_GEN_BUSY_TONE _IO ('q', 0xC6) -+#define SSP_GEN_RINGBACK_TONE _IO ('q', 0xC7) -+#define SSP_GEN_CONGESTION_TONE _IO ('q', 0xC8) -+#define SSP_DISABLE_DIALTONE _IO ('q', 0xC9) -+#define SSP_PHONE_RING_START _IO ('q', 0xCA) -+*/ -+ -+ -+#endif //__GEMINI_I2S_H__ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/gemini_ssp.h -@@ -0,0 +1,263 @@ -+/****************************************************************************** -+ * gemini_ssp.h -+ * -+ * -+ *****************************************************************************/ -+ -+#include -+#include -+#include -+#include -+//#include "proslic.h" -+ -+typedef __u16 UINT16; -+typedef __u32 UINT32; -+typedef __u8 UINT8; -+typedef __u8 BOOL; -+ -+#define TRUE 1 -+#define FALSE 0 -+ -+/***************************************/ -+/* define GPIO module base address */ -+/***************************************/ -+#define DMA_CONTROL_PHY_BASE (IO_ADDRESS(SL2312_GENERAL_DMA_BASE)) -+#define DMA_CONTROL_SSP_BASE (IO_ADDRESS(SL2312_SSP_CTRL_BASE)) -+#define SSP_INT IRQ_SSP -+#define GPIO_BASE_ADDR (IO_ADDRESS(SL2312_GPIO_BASE)) -+#define GPIO_BASE_ADDR1 (IO_ADDRESS(SL2312_GPIO_BASE1)) -+#define GLOBAL_BASE (IO_ADDRESS(SL2312_GLOBAL_BASE)) -+ -+/* define read/write register utility */ -+#define READ_SSP_REG(offset) (__raw_readl(offset+DMA_CONTROL_SSP_BASE)) -+#define WRITE_SSP_REG(offset,val) (__raw_writel(val,offset+DMA_CONTROL_SSP_BASE)) -+ -+#define READ_GPIO_REG(offset) (__raw_readl(offset+GPIO_BASE_ADDR)) -+#define WRITE_GPIO_REG(offset,val) (__raw_writel(val,offset+GPIO_BASE_ADDR)) -+ -+#define READ_GPIO1_REG(offset) (__raw_readl(offset+GPIO_BASE_ADDR1)) -+#define WRITE_GPIO1_REG(offset,val) (__raw_writel(val,offset+GPIO_BASE_ADDR1)) -+ -+#define READ_DMA_REG(offset) (__raw_readl(offset+DMA_CONTROL_PHY_BASE)) -+#define WRITE_DMA_REG(offset,val) (__raw_writel(val,offset+DMA_CONTROL_PHY_BASE)) -+ -+#define READ_GLOBAL_REG(offset) (__raw_readl(offset+GLOBAL_BASE)) -+#define WRITE_GLOBAL_REG(offset,val) (__raw_writel(val,offset+GLOBAL_BASE)) -+ -+ -+#define SSP_GPIO_INT IRQ_GPIO -+ -+#ifndef CONFIG_SL3516_ASIC -+#define SSP_GPIO_INT_BIT 0x00000400 //GPIO[10] : SLIC interrupt pin -+ -+#define GPIO_EECK 0x00000040 /* SCK: GPIO[06] */ -+#define GPIO_EECS 0x00000080 /* SCS: GPIO[07] */ -+#define GPIO_MISO 0x00000200 /* SDO: GPIO[09] receive from 6996*/ -+#define GPIO_MOSI 0x00000100 /* SDI: GPIO[08] send to 6996*/ -+#define GPIO_MISO_BIT 9 -+#else -+#define SSP_GPIO_INT_BIT 0x00000001 //GPIO[0] : SLIC interrupt pin -+ -+//#if 0 -+//#define GPIO_EECK 0x80000000 /* SCK: GPIO1[31] */ -+//#define GPIO_EECS 0x40000000 /* SCS: GPIO1[30] */ -+//#define GPIO_MISO 0x20000000 /* SDO: GPIO1[29] receive from 6996*/ -+//#define GPIO_MOSI 0x10000000 /* SDI: GPIO1[28] send to 6996*/ -+//#define GPIO_MISO_BIT 29 -+//#else -+//#define GPIO_EECK 0x00000100 /* SCK: GPIO1[08] */ -+//#define GPIO_EECS 0x08000000 /* SCS: GPIO1[27] */ -+//#define GPIO_MISO 0x00000080 /* SDO: GPIO1[07] receive from 6996*/ -+//#define GPIO_MOSI 0x00000200 /* SDI: GPIO1[09] send to 6996*/ -+//#define GPIO_MISO_BIT 7 -+//#endif -+#endif -+ -+ -+enum GPIO_REG -+{ -+ GPIO_DATA_OUT = 0x00, -+ GPIO_DATA_IN = 0x04, -+ GPIO_PIN_DIR = 0x08, -+ GPIO_BY_PASS = 0x0c, -+ GPIO_DATA_SET = 0x10, -+ GPIO_DATA_CLEAR = 0x14, -+ GPIO_INT_ENABLE = 0x20, -+ GPIO_INT_RAWSTATE = 0x24, -+ GPIO_INT_MASKSTATE = 0x28, -+ GPIO_INT_MASK = 0x2C, -+ GPIO_INT_CLEAR = 0x30, -+ GPIO_INT_TRIGGER = 0x34, -+ GPIO_INT_BOTH = 0x38, -+ GPIO_INT_POLARITY = 0x3C -+}; -+ -+ -+#define SPI_ADD_LEN 7 // bits of Address -+#define SPI_DAT_LEN 8 // bits of Data -+ -+ -+ -+//#ifdef MIDWAY_DIAG -+#define DAISY_MODE 1 -+#if (DAISY_MODE==1) -+#define NUMBER_OF_CHAN 2 -+#else -+#define NUMBER_OF_CHAN 1 -+#endif -+#define LLP_SIZE 8 -+#define SBUF_SIZE 512 //0xff0 //2560 -+#define DBUF_SIZE SBUF_SIZE*NUMBER_OF_CHAN //0xff0 //2560 -+#define TBUF_SIZE (LLP_SIZE)*DBUF_SIZE -+#define DESC_NUM 1 -+#define DTMF_NUM 20 -+ -+/* define owner bit of SSP */ -+//data into SSP and transfer to AP==> SSP_Rx -+//data out of SSP and transfer to SLIC==> SSP_Tx -+#define CPU 0 -+#define DMA 1 -+ -+#define DMA_DEMO 0 -+#define DMA_NDEMO 1 -+//#define DMA_NONE 2 -+ -+enum exceptions { -+ PROSLICiNSANE, -+ TIMEoUTpOWERuP, -+ TIMEoUTpOWERdOWN, -+ POWERlEAK, -+ TIPoRrINGgROUNDsHORT, -+ POWERaLARMQ1, -+ POWERaLARMQ2, -+ POWERaLARMQ3, -+ POWERaLARMQ4, -+ POWERaLARMQ5, -+ OWERaLARMQ6, -+ CM_CAL_ERR -+}; -+ -+typedef struct -+{ -+ UINT32 src_addr; -+ UINT32 dst_addr; -+ UINT32 llp; -+ UINT32 ctrl_size; -+}DMA_LLP_t; -+ -+typedef struct { -+ unsigned int own ; -+ char *tbuf; -+ //UINT32 *LinkAddrT; -+ DMA_LLP_t LLPT[LLP_SIZE]; -+}DMA_Tx_t; -+ -+typedef struct { -+ unsigned int own ; -+ char *rbuf; -+ //UINT32 *LinkAddrR; -+ DMA_LLP_t LLPR[LLP_SIZE]; -+}DMA_Rx_t; -+ -+//typedef struct { -+// //UINT32 init_stat; -+// struct chipStruct chipData ; /* Represents a proslics state, cached information, and timers */ -+// struct phone_device p; -+// -+// -+//}SSP_SLIC; -+ -+ -+ -+/* DMA Registers */ -+#define DMA_INT 0x00000000 -+#define DMA_INT_TC 0x00000004 -+#define DMA_CFG 0x00000024 -+#define DMA_INT_TC_CLR 0x00000008 -+#define DMA_TC 0x00000014 -+#define DMA_CSR 0x00000024 -+#define DMA_SYNC 0x00000028 -+ -+#define DMA_CH2_CSR 0x00000140 -+#define DMA_CH2_CFG 0x00000144 -+#define DMA_CH2_SRC_ADDR 0x00000148 -+#define DMA_CH2_DST_ADDR 0x0000014c -+#define DMA_CH2_LLP 0x00000150 -+#define DMA_CH2_SIZE 0x00000154 -+ -+#define DMA_CH3_CSR 0x00000160 -+#define DMA_CH3_CFG 0x00000164 -+#define DMA_CH3_SRC_ADDR 0x00000168 -+#define DMA_CH3_DST_ADDR 0x0000016c -+#define DMA_CH3_LLP 0x00000170 -+#define DMA_CH3_SIZE 0x00000174 -+ -+#define SSP_DEVICE_ID 0x00 -+#define SSP_CTRL_STATUS 0x04 -+#define SSP_FRAME_CTRL 0x08 -+#define SSP_BAUD_RATE 0x0c -+#define SSP_FRAME_CTRL2 0x10 -+#define SSP_FIFO_CTRL 0x14 -+#define SSP_TX_SLOT_VALID0 0x18 -+#define SSP_TX_SLOT_VALID1 0x1c -+#define SSP_TX_SLOT_VALID2 0x20 -+#define SSP_TX_SLOT_VALID3 0x24 -+#define SSP_RX_SLOT_VALID0 0x28 -+#define SSP_RX_SLOT_VALID1 0x2c -+#define SSP_RX_SLOT_VALID2 0x30 -+#define SSP_RX_SLOT_VALID3 0x34 -+#define SSP_SLOT_SIZE0 0x38 -+#define SSP_SLOT_SIZE1 0x3c -+#define SSP_SLOT_SIZE2 0x40 -+#define SSP_SLOT_SIZE3 0x44 -+#define SSP_READ_PORT 0x48 -+#define SSP_WRITE_PORT 0x4c -+ -+ -+void printFreq_Revision(int num); -+void SLIC_SPI_write(int num, UINT8 ,UINT8); -+UINT8 SLIC_SPI_read(int num, UINT8); -+void SLIC_SPI_write_bit(char); -+void SLIC_SPI_ind_write(int num, UINT8, UINT16); -+UINT16 SLIC_SPI_ind_read(int num, UINT8); -+void SLIC_SPI_CS_enable(UINT8); -+unsigned int SLIC_SPI_read_bit(void); -+void SLIC_SPI_pre_st(void); -+UINT32 ssp_init(void); -+UINT16 SLIC_SPI_get_identifier(int num); -+int selfTest(int num); -+void exception (int num, enum exceptions e); -+int SLIC_init(int num); -+UINT8 version(int num); -+UINT8 chipType (int num); -+void SLIC_init_ind_reg_set(int num); -+UINT8 powerUp(int num); -+UINT8 powerLeakTest(int num); -+void SLIC_init_reg_set(int num); -+int calibrate(int num); -+void goActive(int num); -+void clearInterrupts(int num); -+void setState(int num, int); -+UINT8 loopStatus(int num); -+int verifyIndirectRegisters(int num); -+int verifyIndirectReg(int num, UINT8 , UINT16); -+void sendProSLICID(int num); -+void disableOscillators(int num); -+UINT8 checkSum(int num, char * string ); -+void fskInitialization (int num); -+void fskByte(int num, UINT8 c); -+void waitForInterrupt (int num); -+//void findNumber(void); -+UINT8 dtmfAction(int num); -+UINT8 digit(int num); -+void interrupt_init(void); -+//void gemini_slic_isr (int ); -+int groundShort(int num); -+void clearAlarmBits(int num); -+void stopRinging(int num); -+void activateRinging(int num); -+void initializeLoopDebounceReg(int num); -+void busyJapan(int num) ; -+void ringBackJapan(int num) ; -+void stateMachine(int num); -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/hardware.h -@@ -0,0 +1,47 @@ -+/* -+ * linux/include/asm-arm/arch-epxa10/hardware.h -+ * -+ * This file contains the hardware definitions of the Integrator. -+ * -+ * Copyright (C) 1999 ARM Limited. -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include -+ -+#define pcibios_assign_all_busses() 1 -+ -+/* -+ * Where in virtual memory the IO devices (timers, system controllers -+ * and so on) -+ * -+ * macro to get at IO space when running virtually -+*/ -+ -+#define IO_ADDRESS(x) (((x&0xfff00000)>>4)|(x & 0x000fffff)|0xF0000000) -+#define FLASH_VBASE 0xFE000000 -+#define FLASH_SIZE 0x1000000// 8M -+#define FLASH_START SL2312_FLASH_BASE -+#define FLASH_VADDR(x) ((x & 0x00ffffff)|0xFE000000) // flash virtual address -+ -+#define PCIBIOS_MIN_IO 0x100 // 0x000-0x100 AHB reg and PCI config, data -+#define PCIBIOS_MIN_MEM 0 -+ -+#endif -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/int_ctrl.h -@@ -0,0 +1,171 @@ -+/* -+ * -+ * This file contains the register definitions for the Excalibur -+ * Timer TIMER00. -+ * -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __INT_CTRL_H -+#define __INT_CTRL_H -+ -+#define PCI_IRQ_OFFSET 64 /* PCI start IRQ number */ -+#define FIQ_OFFSET 32 -+ -+#define IRQ_SOURCE(base_addr) (INT_CTRL_TYPE(base_addr + 0x00)) -+#define IRQ_MASK(base_addr) (INT_CTRL_TYPE (base_addr + 0x04 )) -+#define IRQ_CLEAR(base_addr) (INT_CTRL_TYPE (base_addr + 0x08 )) -+#define IRQ_TMODE(base_addr) (INT_CTRL_TYPE (base_addr + 0x0C )) -+#define IRQ_TLEVEL(base_addr) (INT_CTRL_TYPE (base_addr + 0x10 )) -+#define IRQ_STATUS(base_addr) (INT_CTRL_TYPE (base_addr + 0x14 )) -+#define FIQ_SOURCE(base_addr) (INT_CTRL_TYPE (base_addr + 0x20 )) -+#define FIQ_MASK(base_addr) (INT_CTRL_TYPE (base_addr + 0x24 )) -+#define FIQ_CLEAR(base_addr) (INT_CTRL_TYPE (base_addr + 0x28 )) -+#define FIQ_TMODE(base_addr) (INT_CTRL_TYPE (base_addr + 0x2C )) -+#define FIQ_LEVEL(base_addr) (INT_CTRL_TYPE (base_addr + 0x30 )) -+#define FIQ_STATUS(base_addr) (INT_CTRL_TYPE (base_addr + 0x34 )) -+ -+#ifdef CONFIG_SL3516_ASIC -+#define IRQ_SERIRQ0_OFFSET 30 -+#define IRQ_PCID_OFFSET 29 -+#define IRQ_PCIC_OFFSET 28 -+#define IRQ_PCIB_OFFSET 27 -+#define IRQ_PWR_OFFSET 26 -+#define IRQ_CIR_OFFSET 25 -+#define IRQ_GPIO2_OFFSET 24 -+#define IRQ_GPIO1_OFFSET 23 -+#define IRQ_GPIO_OFFSET 22 -+#define IRQ_SSP_OFFSET 21 -+#define IRQ_LPC_OFFSET 20 -+#define IRQ_LCD_OFFSET 19 -+#define IRQ_UART_OFFSET 18 -+#define IRQ_RTC_OFFSET 17 -+#define IRQ_TIMER3_OFFSET 16 -+#define IRQ_TIMER2_OFFSET 15 -+#define IRQ_TIMER1_OFFSET 14 -+#define IRQ_FLASH_OFFSET 12 -+#define IRQ_USB1_OFFSET 11 -+#define IRQ_USB0_OFFSET 10 -+#define IRQ_DMA_OFFSET 9 -+#define IRQ_PCI_OFFSET 8 -+#define IRQ_IPSEC_OFFSET 7 -+#define IRQ_RAID_OFFSET 6 -+#define IRQ_IDE1_OFFSET 5 -+#define IRQ_IDE0_OFFSET 4 -+#define IRQ_WATCHDOG_OFFSET 3 -+#define IRQ_GMAC1_OFFSET 2 -+#define IRQ_GMAC0_OFFSET 1 -+#define IRQ_CPU0_IP_IRQ_OFFSET 0 -+ -+#define IRQ_SERIRQ0_MASK (1<<30) -+#define IRQ_PCID_MASK (1<<29) -+#define IRQ_PCIC_MASK (1<<28) -+#define IRQ_PCIB_MASK (1<<27) -+#define IRQ_PWR_MASK (1<<26) -+#define IRQ_CIR_MASK (1<<25) -+#define IRQ_GPIO2_MASK (1<<24) -+#define IRQ_GPIO1_MASK (1<<23) -+#define IRQ_GPIO_MASK (1<<22) -+#define IRQ_SSP_MASK (1<<21) -+#define IRQ_LPC_MASK (1<<20) -+#define IRQ_LCD_MASK (1<<19) -+#define IRQ_UART_MASK (1<<18) -+#define IRQ_RTC_MASK (1<<17) -+#define IRQ_TIMER3_MASK (1<<16) -+#define IRQ_TIMER2_MASK (1<<15) -+#define IRQ_TIMER1_MASK (1<<14) -+#define IRQ_FLASH_MASK (1<<12) -+#define IRQ_USB1_MASK (1<<11) -+#define IRQ_USB0_MASK (1<<10) -+#define IRQ_DMA_MASK (1<< 9) -+#define IRQ_PCI_MASK (1<< 8) -+#define IRQ_IPSEC_MASK (1<< 7) -+#define IRQ_RAID_MASK (1<< 6) -+#define IRQ_IDE1_MASK (1<< 5) -+#define IRQ_IDE0_MASK (1<< 4) -+#define IRQ_WATCHDOG_MASK (1<< 3) -+#define IRQ_GMAC1_MASK (1<< 2) -+#define IRQ_GMAC0_MASK (1<< 1) -+#define IRQ_CPU0_IP_IRQ_MASK (1<< 0) -+#else -+#define IRQ_SERIRQ0_OFFSET 30 -+#define IRQ_PCID_OFFSET 29 -+#define IRQ_PCIC_OFFSET 28 -+#define IRQ_PCIB_OFFSET 27 -+#define IRQ_PWR_OFFSET 26 -+#define IRQ_CIR_OFFSET 25 -+#define IRQ_GPIO2_OFFSET 24 -+#define IRQ_GPIO1_OFFSET 23 -+#define IRQ_GPIO_OFFSET 22 -+#define IRQ_SSP_OFFSET 21 -+#define IRQ_LPC_OFFSET 20 -+#define IRQ_LCD_OFFSET 19 -+#define IRQ_UART_OFFSET 18 -+#define IRQ_RTC_OFFSET 17 -+#define IRQ_TIMER3_OFFSET 16 -+#define IRQ_TIMER2_OFFSET 15 -+#define IRQ_TIMER1_OFFSET 14 -+#define IRQ_FLASH_OFFSET 12 -+#define IRQ_USB1_OFFSET 11 -+#define IRQ_USB0_OFFSET 10 -+#define IRQ_DMA_OFFSET 9 -+#define IRQ_PCI_OFFSET 8 -+#define IRQ_IPSEC_OFFSET 7 -+#define IRQ_RAID_OFFSET 6 -+#define IRQ_IDE1_OFFSET 5 -+#define IRQ_IDE0_OFFSET 4 -+#define IRQ_WATCHDOG_OFFSET 3 -+#define IRQ_GMAC1_OFFSET 2 -+#define IRQ_GMAC0_OFFSET 1 -+#define IRQ_CPU0_IP_IRQ_OFFSET 0 -+ -+#define IRQ_SERIRQ0_MASK (1<<30) -+#define IRQ_PCID_MASK (1<<29) -+#define IRQ_PCIC_MASK (1<<28) -+#define IRQ_PCIB_MASK (1<<27) -+#define IRQ_PWR_MASK (1<<26) -+#define IRQ_CIR_MASK (1<<25) -+#define IRQ_GPIO2_MASK (1<<24) -+#define IRQ_GPIO1_MASK (1<<23) -+#define IRQ_GPIO_MASK (1<<22) -+#define IRQ_SSP_MASK (1<<21) -+#define IRQ_LPC_MASK (1<<20) -+#define IRQ_LCD_MASK (1<<19) -+#define IRQ_UART_MASK (1<<18) -+#define IRQ_RTC_MASK (1<<17) -+#define IRQ_TIMER3_MASK (1<<16) -+#define IRQ_TIMER2_MASK (1<<15) -+#define IRQ_TIMER1_MASK (1<<14) -+#define IRQ_FLASH_MASK (1<<12) -+#define IRQ_USB1_MASK (1<<11) -+#define IRQ_USB0_MASK (1<<10) -+#define IRQ_DMA_MASK (1<< 9) -+#define IRQ_PCI_MASK (1<< 8) -+#define IRQ_IPSEC_MASK (1<< 7) -+#define IRQ_RAID_MASK (1<< 6) -+#define IRQ_IDE1_MASK (1<< 5) -+#define IRQ_IDE0_MASK (1<< 4) -+#define IRQ_WATCHDOG_MASK (1<< 3) -+#define IRQ_GMAC1_MASK (1<< 2) -+#define IRQ_GMAC0_MASK (1<< 1) -+#define IRQ_CPU0_IP_IRQ_MASK (1<< 0) -+#endif -+ -+ -+#endif /* __INT_CTRL_H */ -+ -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/io.h -@@ -0,0 +1,50 @@ -+/* -+ * linux/include/asm-arm/arch-epxa10db/io.h -+ * -+ * Copyright (C) 1999 ARM Limited -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARM_ARCH_IO_H -+#define __ASM_ARM_ARCH_IO_H -+ -+#define IO_SPACE_LIMIT 0xffffffff -+ -+ -+/* -+ * Generic virtual read/write -+ */ -+/* -+#define __arch_getw(a) (*(volatile unsigned short *)(a)) -+#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -+*/ -+/*#define outsw __arch_writesw -+#define outsl __arch_writesl -+#define outsb __arch_writesb -+#define insb __arch_readsb -+#define insw __arch_readsw -+#define insl __arch_readsl*/ -+ -+#define __io(a) (a) -+#define __mem_pci(a) (a) -+/* -+#define __arch_getw(a) (*(volatile unsigned short *)(a)) -+#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -+*/ -+#define iomem_valid_addr(off,size) (1) -+#define iomem_to_phys(off) (off) -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/ipi.h -@@ -0,0 +1,189 @@ -+/* -+ * linux/include/asm-arm/arch-sl2312/system.h -+ * -+ * Copyright (C) 1999 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_IPI_H -+#define __ASM_ARCH_IPI_H -+#include -+ -+//#define spin_lock(x) spin_lock_dt(x) -+//#define spin_unlock(x) spin_unlock_dt(x) -+ -+#define SWAP_OFFSET 0x400000 -+#define SWAP_SIZE 0x400000 -+ -+#define SHARE_MEM_ADDR 0x2000000 -+#define SHARE_MEM_SIZE 1024*1024 -+ -+ -+//--> Add by jason for IPI testing -+// memory layout for maste & slave bin -+#define MASTERTEXT 0x8000 -+#define SLAVETEXT 0x108000 -+#define SHARESIZE 0x4000 -+#define SHAREADDR SHARE_MEM_ADDR // starting 8M -+ -+// CPU1 reset release -+#define GLOBAL_BASE IO_ADDRESS(0x40000000) -+#define GLOBAL_SOFTRESET (GLOBAL_BASE + 0x0C) -+#define CPU1_RESET_BIT_MASK 0x40000000 -+ -+// IPI , need to redefine the folliwing, bug -+#define CPU0_STATUS (GLOBAL_BASE + 0x0038) -+#define CPU1_STATUS (GLOBAL_BASE + 0x003C) -+#define CPU_IPI_BIT_MASK 0x80000000 -+ -+/* Your basic SMP spinlocks, allowing only a single CPU anywhere -+*/ -+typedef struct { -+ volatile unsigned int lock; -+} spinlock_dt; -+ -+ -+#define MASTER_BIT 0x01 -+#define SLAVE_BIT 0x02 -+#define HEART_BIT 0x04 -+#define IPI0_IRQ_BIT 0x08 -+#define IPI0_FIQ_BIT 0x10 -+#define IPI1_IRQ_BIT 0x20 -+#define IPI1_FIQ_BIT 0x40 -+ -+#define IRQ 0 -+#define FIQ 1 -+#define DONE 0xff -+ -+#define CPU0 0x0 -+#define CPU1 0x1 -+ -+#define MAXCHAR 128*1024 -+typedef struct { -+ int flag; -+ int uart_flag; -+ int cnt; -+ spinlock_dt lk; -+ char message[MAXCHAR]; -+}s_mailbox; -+ -+// JScale proj definition -+typedef struct { -+ u16 type; // message Type -+ u16 length; // message length, including message header -+} IPC_MSG_HDR_T; -+ -+typedef struct{ -+ IPC_MSG_HDR_T hdr; -+ u32 input_location; -+ u32 input_size; -+ u32 output_location; -+ u16 ScaledImageWidth; -+ u16 ScaledImageHeight; -+ u8 ScaledImageQuality; -+ u8 MaintainResultionRatio; -+ u8 TwoStepScaling; -+ u8 InputFormat; -+ u8 verbose; -+ u8 reserved[3]; -+} JSCALE_REQ_T; -+ -+typedef struct{ -+ IPC_MSG_HDR_T hdr; -+ u32 status; -+ u32 code; -+ u32 output_size; -+} JSCALE_RSP_T; -+ -+#define IPC_JSCALE_REQ_MSG 0 // JScale request from CPU-0 to CPU-1 -+#define IPC_JSCALE_RSP_MSG 1 // JScale response from CPU-1 to CPU-0 -+ -+enum { -+ JSCALE_STATUS_OK = 0, -+ JSCALE_UNKNOWN_MSG_TYPE, -+ JSCALE_FAILED_FILE_SIZE, -+ JSCALE_FAILED_MALLOC, -+ JSCALE_FAILED_FORMAT, -+ JSCALE_DECODE_ERROR, -+ JSCALE_BUSY, -+}; -+// <-- JScale -+ -+#define GEMINI_IPI_IOCTL_BASE 'Z' -+#define GEMINI_IPI_JSCALE_REQ _IOW (GEMINI_IPI_IOCTL_BASE,0,JSCALE_REQ_T) -+#define GEMINI_IPI_JSCALE_STAT _IOR (GEMINI_IPI_IOCTL_BASE,1,JSCALE_RSP_T) -+ -+ -+/* -+* Simple spin lock operations. -+* -+*/ -+ -+#define spin_is_locked_dt(x)((x)->lock != 0) -+ -+static inline int test_and_set_dt(spinlock_dt *lock) -+{ -+unsigned long tmp; -+__asm__ __volatile__( -+"swp %0, %2, [%1]\n" -+: "=&r" (tmp) -+: "r" (&lock->lock), "r" (1) -+: "cc", "memory"); -+ -+return tmp; -+} -+ -+static inline void spin_lock_dt(spinlock_dt *lock) -+{ -+ -+unsigned long tmp; -+__asm__ __volatile__( -+"1: ldr %0, [%1]\n" -+"teq %0, #0\n" -+"swpeq %0, %2, [%1]\n" -+" teqeq %0, #0\n" -+" bne 1b" -+ : "=&r" (tmp) -+ : "r" (&lock->lock), "r" (1) -+ : "cc", "memory"); -+} -+ -+static inline void spin_unlock_dt(spinlock_dt *lock) -+{ -+ __asm__ __volatile__( -+" str %1, [%0]" -+ : -+ : "r" (&lock->lock), "r" (0) -+ : "cc", "memory"); -+} -+ -+static inline int getcpuid(void) -+{ -+ int cpuid; -+ -+ __asm__( -+"mrc p8, 0, r0, c0, c0, 0\n" -+"mov %0, r0" -+ :"=r"(cpuid) -+ : -+ :"r0"); -+ return (cpuid & 0x07); -+} -+ -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/irq.h -@@ -0,0 +1,23 @@ -+/* -+ * linux/include/asm-arm/arch-sl2312/irq.h -+ * -+ * Copyright (C) 1999 ARM Limited -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+ // Since we have PCI interrupt which the interrupt line is pseudo -+ // we need do some fixup -+int fixup_irq(int irq); ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/irqs.h -@@ -0,0 +1,102 @@ -+/* -+ * linux/include/asm-arm/arch-camelot/irqs.h -+ * -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+/* Use the Excalibur chip definitions */ -+#define INT_CTRL_TYPE -+#include "asm/arch/int_ctrl.h" -+ -+#ifdef CONFIG_SL3516_ASIC -+#define IRQ_SERIRQ_MAX 31 -+#define IRQ_SERIRQ1 31 -+#define IRQ_SERIRQ0 30 -+#define IRQ_PCID 29 -+#define IRQ_PCIC 28 -+#define IRQ_PCIB 27 -+#define IRQ_PWR 26 -+#define IRQ_CIR 25 -+#define IRQ_GPIO2 24 -+#define IRQ_GPIO1 23 -+#define IRQ_GPIO 22 -+#define IRQ_SSP 21 -+#define IRQ_LPC 20 -+#define IRQ_LCD 19 -+#define IRQ_UART 18 -+#define IRQ_RTC 17 -+#define IRQ_TIMER3 16 -+#define IRQ_TIMER2 15 -+#define IRQ_TIMER1 14 -+#define IRQ_FLASH 12 -+#define IRQ_USB1 11 -+#define IRQ_USB0 10 -+#define IRQ_DMA 9 -+#define IRQ_PCI 8 -+#define IRQ_IPSEC 7 -+#define IRQ_RAID 6 -+#define IRQ_IDE1 5 -+#define IRQ_IDE0 4 -+#define IRQ_WATCHDOG 3 -+#define IRQ_GMAC1 2 -+#define IRQ_GMAC0 1 -+#define IRQ_CPU0_IP_IRQ 0 -+#else -+#define IRQ_SERIRQ_MAX 31 -+#define IRQ_SERIRQ1 31 -+#define IRQ_SERIRQ0 30 -+#define IRQ_PCID 29 -+#define IRQ_PCIC 28 -+#define IRQ_PCIB 27 -+#define IRQ_PWR 26 -+#define IRQ_CIR 25 -+#define IRQ_GPIO2 24 -+#define IRQ_GPIO1 23 -+#define IRQ_GPIO 22 -+#define IRQ_SSP 21 -+#define IRQ_LPC 20 -+#define IRQ_LCD 19 -+#define IRQ_UART 18 -+#define IRQ_RTC 17 -+#define IRQ_TIMER3 16 -+#define IRQ_TIMER2 15 -+#define IRQ_TIMER1 14 -+#define IRQ_FLASH 12 -+#define IRQ_USB1 11 -+#define IRQ_USB0 10 -+#define IRQ_DMA 9 -+#define IRQ_PCI 8 -+#define IRQ_IPSEC 7 -+#define IRQ_RAID 6 -+#define IRQ_IDE1 5 -+#define IRQ_IDE0 4 -+#define IRQ_WATCHDOG 3 -+#define IRQ_GMAC1 2 -+#define IRQ_GMAC0 1 -+#endif -+ -+#define ARCH_TIMER_IRQ IRQ_TIMER2 /* for MV 4.0 */ -+ -+#define IRQ_PCI_INTA PCI_IRQ_OFFSET + 0 -+#define IRQ_PCI_INTB PCI_IRQ_OFFSET + 1 -+#define IRQ_PCI_INTC PCI_IRQ_OFFSET + 2 -+#define IRQ_PCI_INTD PCI_IRQ_OFFSET + 3 -+ -+#define NR_IRQS (IRQ_PCI_INTD + 4) -+ -+ -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/it8712.h -@@ -0,0 +1,24 @@ -+ -+#ifndef __IT8712_H__ -+#define __IT8712_H__ -+ -+#include "asm/arch/sl2312.h" -+ -+#define IT8712_IO_BASE SL2312_LPC_IO_BASE -+// Device LDN -+#define LDN_SERIAL1 0x01 -+#define LDN_SERIAL2 0x02 -+#define LDN_PARALLEL 0x03 -+#define LDN_KEYBOARD 0x05 -+#define LDN_MOUSE 0x06 -+#define LDN_GPIO 0x07 -+ -+#define IT8712_UART1_PORT 0x3F8 -+#define IT8712_UART2_PORT 0x2F8 -+ -+#define IT8712_GPIO_BASE 0x800 // 0x800-0x804 for GPIO set1-set5 -+ -+void LPCSetConfig(char LdnNumber, char Index, char data); -+char LPCGetConfig(char LdnNumber, char Index); -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/memory.h -@@ -0,0 +1,38 @@ -+/* -+ * linux/include/asm-arm/arch-sl2312/memory.h -+ * -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_MMU_H -+#define __ASM_ARCH_MMU_H -+ -+/* -+ * Physical DRAM offset. -+ */ -+#define PHYS_OFFSET UL(0x00000000) -+ -+/* -+ * Virtual view <-> DMA view memory address translations -+ * virt_to_bus: Used to translate the virtual address to an -+ * address suitable to be passed to set_dma_addr -+ * bus_to_virt: Used to convert an address for DMA operations -+ * to an address that the kernel can use. -+ */ -+#define __virt_to_bus(x) (x - PAGE_OFFSET + /*SDRAM_BASE*/0) -+#define __bus_to_virt(x) (x - /*SDRAM_BASE*/0 + PAGE_OFFSET) -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/param.h -@@ -0,0 +1,20 @@ -+/* -+ * linux/include/asm-arm/arch-epxa10db/param.h -+ * -+ * Copyright (C) 1999 ARM Limited -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/pci.h -@@ -0,0 +1,18 @@ -+ -+#ifndef __SL2312_PCI_H__ -+#define __SL2312_PCI_H__ -+ -+#define SL2312_PCI_PMC 0x40 -+#define SL2312_PCI_PMCSR 0x44 -+#define SL2312_PCI_CTRL1 0x48 -+#define SL2312_PCI_CTRL2 0x4c -+#define SL2312_PCI_MEM1_BASE_SIZE 0x50 -+#define SL2312_PCI_MEM2_BASE_SIZE 0x54 -+#define SL2312_PCI_MEM3_BASE_SIZE 0x58 -+ -+ -+void sl2312_pci_mask_irq(unsigned int irq); -+void sl2312_pci_unmask_irq(unsigned int irq); -+int sl2312_pci_get_int_src(void); -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/platform.h -@@ -0,0 +1,7 @@ -+#ifndef PLATFORM_H -+#define PLATFORM_H -+#include "sl2312.h" -+ -+#define MAXIRQNUM 68 -+#endif -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/preempt.h -@@ -0,0 +1,63 @@ -+/* -+ * include/asm-arm/arch-sl2312/preempt.h -+ * -+ * Timing support for preempt-stats, kfi, ilatency patches -+ * -+ * Author: dsingleton -+ * -+ * 2001-2004 (c) MontaVista Software, Inc. This file is licensed under -+ * the terms of the GNU General Public License version 2. This program -+ * is licensed "as is" without any warranty of any kind, whether express -+ * or implied. -+ */ -+ -+#ifndef _ASM_ARCH_PREEMT_H -+#define _ASM_ARCH_PREEMT_H -+ -+#include -+#include -+ -+static inline unsigned long clock_diff(unsigned long start, unsigned long stop) -+{ -+ return (start - stop); -+} -+ -+static inline unsigned int readclock(void) -+{ -+ unsigned int x; -+ -+ x = readl(IO_ADDRESS(SL2312_TIMER2_BASE)); -+ return x; -+} -+ -+static inline unsigned __ticks_per_usec(void) -+{ -+#ifdef CONFIG_SL3516_ASIC -+ unsigned int ahb_clock_rate_base=130; /* unit = MHz*/ -+ unsigned int reg_v=0; -+ unsigned int ticks_usec; -+ -+ reg_v = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+4))); -+ reg_v >>=15; -+ ticks_usec = (ahb_clock_rate_base + (reg_v & 0x07)*10)>>2; -+ -+#else -+ unsigned int ticks_usec=20; -+#endif -+ -+ return ticks_usec; -+} -+ -+/* -+ * timer 1 runs @ 6Mhz 6 ticks = 1 microsecond -+ * and is configed as a count down timer. -+ */ -+#define TICKS_PER_USEC __ticks_per_usec() -+#define ARCH_PREDEFINES_TICKS_PER_USEC -+ -+#define clock_to_usecs(x) ((x) / TICKS_PER_USEC) -+ -+#define INTERRUPTS_ENABLED(x) (!(x & PSR_I_BIT)) -+ -+#endif -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/sl2312.h -@@ -0,0 +1,254 @@ -+#ifndef __sl2312_h -+#define __sl2312_h -+ -+/**************************************************************************** -+ * Copyright Storlink Corp 2002-2003. All rights reserved. * -+ *--------------------------------------------------------------------------* -+ * Name:board.s * -+ * Description: SL231x specfic define * -+ * Author: Plus Chen * -+ * Version: 0.9 Create -+ ****************************************************************************/ -+ -+/* -+ CPE address map; -+ -+ +==================================================== -+ 0x00000000 | FLASH -+ 0x0FFFFFFF | -+ |==================================================== -+ 0x10000000 | SDRAM -+ 0x1FFFFFFF | -+ |==================================================== -+ 0x20000000 | Global Registers 0x20000000-0x20FFFFFF -+ | EMAC and DMA 0x21000000-0x21FFFFFF -+ | UART Module 0x22000000-0x22FFFFFF -+ | Timer Module 0x23000000-0x23FFFFFF -+ | Interrupt Module 0x24000000-0x24FFFFFF -+ | RTC Module 0x25000000-0x25FFFFFF -+ | LPC Host Controller 0x26000000-0x26FFFFFF -+ | LPC Peripherial IO 0x27000000-0x27FFFFFF -+ | WatchDog Timer 0x28000000-0x28FFFFFF -+ 0x2FFFFFFF | Reserved 0x29000000-0x29FFFFFF -+ |===================================================== -+ 0x30000000 | PCI IO, Configuration Registers -+ 0x3FFFFFFF | -+ |===================================================== -+ 0x40000000 | PCI Memory -+ 0x4FFFFFFF | -+ |===================================================== -+ 0x50000000 | Ethernet MAC and DMA 0x50000000-0x50FFFFFF -+ | Security and DMA 0x51000000-0x51FFFFFF -+ | IDE Channel 0 Register 0x52000000-0x527FFFFF -+ | IDE Channel 1 Register 0x52800000-0x52FFFFFF -+ | USB Register 0x53000000-0x53FFFFFF -+ | Flash Controller 0x54000000-0x54FFFFFF -+ | DRAM Controller 0x55000000-0x55FFFFFF -+ 0x5FFFFFFF | Reserved 0x56000000-0x5FFFFFFF -+ |===================================================== -+ 0x60000000 | Reserved -+ 0x6FFFFFFF | -+ |===================================================== -+ 0x70000000 | FLASH shadow Memory -+ 0x7FFFFFFF | -+ |===================================================== -+ 0x80000000 | Big Endian of memory 0x00000000-0x7FFFFFFF -+ 0xFFFFFFFF | -+ +===================================================== -+*/ -+ -+ -+ -+/*------------------------------------------------------------------------------- -+ Memory Map definitions -+-------------------------------------------------------------------------------- */ -+#define TEST 1 -+#if 0 -+ -+static inline int GETCPUID() -+{ -+ int cpuid; -+ __asm__( -+"mrc p8, 0, r0, c0, c0, 0\n" -+"mov %0, r0" -+ :"=r"(cpuid) -+ : -+ :"r0"); -+ return (cpuid & 0x07); -+} -+#endif -+#define SL2312_SRAM_BASE 0x70000000 // SRAM base after remap -+#define SL2312_DRAM_BASE 0x00000000 // DRAM base after remap -+#define SL2312_RAM_BASE 0x10000000 // RAM code base before remap -+#define SL2312_FLASH_BASE 0x30000000 -+#define SL2312_ROM_BASE 0x30000000 -+#define SL2312_GLOBAL_BASE 0x40000000 -+#define SL2312_WAQTCHDOG_BASE 0x41000000 -+#define SL2312_UART_BASE 0x42000000 -+#define SL2312_TIMER_BASE 0x43000000 -+#define SL2312_LCD_BASE 0x44000000 -+#define SL2312_RTC_BASE 0x45000000 -+#define SL2312_SATA_BASE 0x46000000 -+#define SL2312_LPC_HOST_BASE 0x47000000 -+#define SL2312_LPC_IO_BASE 0x47800000 -+// #define SL2312_INTERRUPT_BASE 0x48000000 -+#define SL2312_INTERRUPT0_BASE 0x48000000 -+#define SL2312_INTERRUPT1_BASE 0x49000000 -+//#define SL2312_INTERRUPT_BASE ((getcpuid()==0)?SL2312_INTERRUPT0_BASE:SL2312_INTERRUPT1_BASE) -+#define SL2312_INTERRUPT_BASE 0x48000000 -+#define SL2312_SSP_CTRL_BASE 0x4A000000 -+#define SL2312_POWER_CTRL_BASE 0x4B000000 -+#define SL2312_CIR_BASE 0x4C000000 -+#define SL2312_GPIO_BASE 0x4D000000 -+#define SL2312_GPIO_BASE1 0x4E000000 -+#define SL2312_GPIO_BASE2 0x4F000000 -+#define SL2312_PCI_IO_BASE 0x50000000 -+#define SL2312_PCI_MEM_BASE 0x58000000 -+#ifdef CONFIG_NET_SL351X -+#define SL2312_TOE_BASE 0x60000000 -+#define SL2312_GMAC0_BASE 0x6000A000 -+#define SL2312_GMAC1_BASE 0x6000E000 -+#else -+#define SL2312_GMAC0_BASE 0x60000000 -+#define SL2312_GMAC1_BASE 0x61000000 -+#endif -+#define SL2312_SECURITY_BASE 0x62000000 -+#define SL2312_IDE0_BASE 0x63000000 -+#define SL2312_IDE1_BASE 0x63400000 -+#define SL2312_RAID_BASE 0x64000000 -+#define SL2312_FLASH_CTRL_BASE 0x65000000 -+#define SL2312_DRAM_CTRL_BASE 0x66000000 -+#define SL2312_GENERAL_DMA_BASE 0x67000000 -+#define SL2312_USB_BASE 0x68000000 -+#define SL2312_USB0_BASE 0x68000000 -+#define SL2312_USB1_BASE 0x69000000 -+#define SL2312_FLASH_SHADOW 0x30000000 -+#define SL2312_BIG_ENDIAN_BASE 0x80000000 -+ -+#ifdef CONFIG_GEMINI_IPI -+#define CPU_1_MEM_BASE 0x4000000 // 64 MB -+#define CPU_1_DATA_OFFSET 0x4000000-0x300000 // Offset 61 MB -+#endif -+ -+#define SL2312_TIMER1_BASE SL2312_TIMER_BASE -+#define SL2312_TIMER2_BASE (SL2312_TIMER_BASE + 0x10) -+#define SL2312_TIMER3_BASE (SL2312_TIMER_BASE + 0x20) -+ -+#define SL2312_PCI_DMA_MEM1_BASE 0x00000000 -+#define SL2312_PCI_DMA_MEM2_BASE 0x00000000 -+#define SL2312_PCI_DMA_MEM3_BASE 0x00000000 -+#define SL2312_PCI_DMA_MEM1_SIZE 7 -+#define SL2312_PCI_DMA_MEM2_SIZE 6 -+#define SL2312_PCI_DMA_MEM3_SIZE 6 -+ -+/*------------------------------------------------------------------------------- -+ Global Module -+---------------------------------------------------------------------------------*/ -+#define GLOBAL_ID 0x00 -+#define GLOBAL_CHIP_ID 0x002311 -+#define GLOBAL_CHIP_REV 0xA0 -+#define GLOBAL_STATUS 0x04 -+#define GLOBAL_CONTROL 0x1C -+#define GLOBAL_REMAP_BIT 0x01 -+#define GLOBAL_RESET_REG 0x0C -+#define GLOBAL_MISC_REG 0x30 -+#define PFLASH_SHARE_BIT 0x02 -+ -+#define GLOBAL_RESET (1<<31) -+#define RESET_CPU1 (1<<30) -+#define RESET_SATA1 (1<<27) -+#define RESET_SATA0 (1<<26) -+#define RESET_CIR (1<<25) -+#define RESET_EXT_DEV (1<<24) -+#define RESET_WD (1<<23) -+#define RESET_GPIO2 (1<<22) -+#define RESET_GPIO1 (1<<21) -+#define RESET_GPIO0 (1<<20) -+#define RESET_SSP (1<<19) -+#define RESET_UART (1<<18) -+#define RESET_TIMER (1<<17) -+#define RESET_RTC (1<<16) -+#define RESET_INT0 (1<<15) -+#define RESET_INT1 (1<<14) -+#define RESET_LCD (1<<13) -+#define RESET_LPC (1<<12) -+#define RESET_APB (1<<11) -+#define RESET_DMA (1<<10) -+#define RESET_USB1 (1<<9 ) -+#define RESET_USB0 (1<<8 ) -+#define RESET_PCI (1<<7 ) -+#define RESET_GMAC1 (1<<6 ) -+#define RESET_GMAC0 (1<<5 ) -+#define RESET_IPSEC (1<<4 ) -+#define RESET_RAID (1<<3 ) -+#define RESET_IDE (1<<2 ) -+#define RESET_FLASH (1<<1 ) -+#define RESET_DRAM (1<<0 ) -+ -+ -+ -+ -+ -+ -+ -+ -+/*------------------------------------------------------------------------------- -+ DRAM Module -+---------------------------------------------------------------------------------*/ -+#define DRAM_SIZE_32M 0x2000000 -+#define DRAM_SIZE_64M 0x4000000 -+#define DRAM_SIZE_128M 0x8000000 -+ -+#define DRAM_SIZE DRAM_SIZE_128M -+ -+#define DRAM_SDRMR 0x00 -+#define SDRMR_DISABLE_DLL 0x80010000 -+ -+/*------------------------------------------------------------------------------ -+ Share Pin Flag -+--------------------------------------------------------------------------------*/ -+#ifdef CONFIG_SL2312_SHARE_PIN -+#define FLASH_SHARE_BIT 0 -+#define UART_SHARE_BIT 1 -+#define EMAC_SHARE_BIT 2 -+#define IDE_RW_SHARE_BIT 3 -+#define IDE_CMD_SHARE_BIT 4 -+#endif -+/*------------------------------------------------------------------------------- -+ System Clock -+---------------------------------------------------------------------------------*/ -+ -+#ifndef SYS_CLK -+#ifdef CONFIG_SL3516_ASIC -+#define SYS_CLK 150000000 -+#else -+#define SYS_CLK 20000000 -+#endif -+#endif -+ -+#define AHB_CLK SYS_CLK -+#define MAX_TIMER 3 -+#ifndef APB_CLK -+#ifdef CONFIG_SL3516_ASIC -+#define APB_CLK (SYS_CLK / 6) -+#else -+#define APB_CLK SYS_CLK -+#endif -+#endif -+ -+#ifdef CONFIG_SL3516_ASIC -+#define UART_CLK 48000000 // 30000000 for GeminiA chip, else 48000000 -+#else -+#define UART_CLK 48000000 -+#endif -+ -+#define SL2312_BAUD_115200 (UART_CLK / 1843200) -+#define SL2312_BAUD_57600 (UART_CLK / 921600) -+#define SL2312_BAUD_38400 (UART_CLK / 614400) -+#define SL2312_BAUD_19200 (UART_CLK / 307200) -+#define SL2312_BAUD_14400 (UART_CLK / 230400) -+#define SL2312_BAUD_9600 (UART_CLK / 153600) -+ -+#endif -+ -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/sl2312_ipsec.h -@@ -0,0 +1,684 @@ -+#ifndef _IPSEC_DIAG_H -+#define _IPSEC_DIAG_H -+ -+#include -+ -+#define BIG_ENDIAN 0 -+ -+#define IPSEC_TEST 0 -+#define ZERO_COPY 1 -+ -+#define UINT unsigned int -+#define BYTE unsigned char -+ -+/* define cipher algorithm */ -+enum CIPHER { -+ DES_ECB_E =20, -+ TDES_ECB_E =21, -+ AES_ECB_E =22, -+ DES_CBC_E =24, -+ TDES_CBC_E =25, -+ AES_CBC_E =26, -+ -+ DES_ECB_D =27, -+ TDES_ECB_D =28, -+ AES_ECB_D =29, -+ DES_CBC_D =31, -+ TDES_CBC_D =32, -+ AES_CBC_D =33, -+ A_SHA1 =12, -+ A_HMAC_SHA1 =13, -+ A_MD5 =14, -+ A_HMAC_MD5 =15, -+}; -+ -+// opMode -+#define CIPHER_ENC 0x1 -+#define CIPHER_DEC 0x3 -+#define AUTH 0x4 -+#define ENC_AUTH 0x5 -+#define AUTH_DEC 0x7 -+ -+// cipherAlgorithm -+#define CBC_DES 0x4 -+#define CBC_3DES 0x5 -+#define CBC_AES 0x6 -+#define ECB_DES 0x0 -+#define ECB_3DES 0x1 -+#define ECB_AES 0x2 -+ -+// authAlgorithm -+#define SHA1 0 -+#define MD5 1 -+#define HMAC_SHA1 2 -+#define HMAC_MD5 3 -+#define FCS 4 -+ -+//cipher mode -+#define ECB 0 -+#define CBC 1 -+ -+// authMode -+#define AUTH_APPEND 0 -+#define AUTH_CHKVAL 1 -+ -+/******************************************************/ -+/* the offset of IPSEC DMA register */ -+/******************************************************/ -+enum IPSEC_DMA_REGISTER { -+ IPSEC_DMA_DEVICE_ID = 0xff00, -+ IPSEC_DMA_STATUS = 0xff04, -+ IPSEC_TXDMA_CTRL = 0xff08, -+ IPSEC_TXDMA_FIRST_DESC = 0xff0c, -+ IPSEC_TXDMA_CURR_DESC = 0xff10, -+ IPSEC_RXDMA_CTRL = 0xff14, -+ IPSEC_RXDMA_FIRST_DESC = 0xff18, -+ IPSEC_RXDMA_CURR_DESC = 0xff1c, -+ IPSEC_TXDMA_BUF_ADDR = 0xff28, -+ IPSEC_RXDMA_BUF_ADDR = 0xff38, -+ IPSEC_RXDMA_BUF_SIZE = 0xff30, -+}; -+ -+#define IPSEC_STATUS_REG 0x00a8 -+#define IPSEC_RAND_NUM_REG 0x00ac -+ -+/******************************************************/ -+/* the field definition of IPSEC DMA Module Register */ -+/******************************************************/ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff00 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int p_wclk : 4; /* DMA_APB write clock period */ -+ unsigned int p_rclk : 4; /* DMA_APB read clock period */ -+ unsigned int : 8; -+ unsigned int device_id : 12; -+ unsigned int revision_id : 4; -+#else -+ unsigned int revision_id : 4; -+ unsigned int device_id : 12; -+ unsigned int : 8; -+ unsigned int p_rclk : 4; /* DMA_APB read clock period */ -+ unsigned int p_wclk : 4; /* DMA_APB write clock period */ -+#endif -+ } bits; -+} IPSEC_DMA_DEVICE_ID_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff04 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int ts_finish : 1; /* finished tx interrupt */ -+ unsigned int ts_derr : 1; /* AHB Bus Error while tx */ -+ unsigned int ts_perr : 1; /* Tx Descriptor protocol error */ -+ unsigned int ts_eodi : 1; /* TxDMA end of descriptor interrupt */ -+ unsigned int ts_eofi : 1; /* TxDMA end of frame interrupt */ -+ unsigned int rs_finish : 1; /* finished rx interrupt */ -+ unsigned int rs_derr : 1; /* AHB Bus Error while rx */ -+ unsigned int rs_perr : 1; /* Rx Descriptor protocol error */ -+ unsigned int rs_eodi : 1; /* RxDMA end of descriptor interrupt */ -+ unsigned int rs_eofi : 1; /* RxDMA end of frame interrupt */ -+ unsigned int intr : 8; /* Peripheral interrupt */ -+ unsigned int dma_reset : 1; /* write 1 to this bit will cause DMA HClk domain soft reset */ -+ unsigned int peri_reset : 1; /* write 1 to this bit will cause DMA PClk domain soft reset */ -+ unsigned int : 3; -+ unsigned int loop_back : 1; /* loopback TxDMA to RxDMA */ -+ unsigned int intr_enable : 8; /* Peripheral Interrupt Enable */ -+#else -+ unsigned int intr_enable : 8; /* Peripheral Interrupt Enable */ -+ unsigned int loop_back : 1; /* loopback TxDMA to RxDMA */ -+ unsigned int : 3; -+ unsigned int peri_reset : 1; /* write 1 to this bit will cause DMA PClk domain soft reset */ -+ unsigned int dma_reset : 1; /* write 1 to this bit will cause DMA HClk domain soft reset */ -+ unsigned int intr : 8; /* Peripheral interrupt */ -+ unsigned int rs_eofi : 1; /* RxDMA end of frame interrupt */ -+ unsigned int rs_eodi : 1; /* RxDMA end of descriptor interrupt */ -+ unsigned int rs_perr : 1; /* Rx Descriptor protocol error */ -+ unsigned int rs_derr : 1; /* AHB Bus Error while rx */ -+ unsigned int rs_finish : 1; /* finished rx interrupt */ -+ unsigned int ts_eofi : 1; /* TxDMA end of frame interrupt */ -+ unsigned int ts_eodi : 1; /* TxDMA end of descriptor interrupt */ -+ unsigned int ts_perr : 1; /* Tx Descriptor protocol error */ -+ unsigned int ts_derr : 1; /* AHB Bus Error while tx */ -+ unsigned int ts_finish : 1; /* finished tx interrupt */ -+#endif -+ } bits; -+} IPSEC_DMA_STATUS_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff08 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int td_start : 1; /* Start DMA transfer */ -+ unsigned int td_continue : 1; /* Continue DMA operation */ -+ unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int : 1; -+ unsigned int td_prot : 4; /* TxDMA protection control */ -+ unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */ -+ unsigned int td_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */ -+ unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int : 14; -+#else -+ unsigned int : 14; -+ unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int td_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */ -+ unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */ -+ unsigned int td_prot : 4; /* TxDMA protection control */ -+ unsigned int : 1; -+ unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int td_continue : 1; /* Continue DMA operation */ -+ unsigned int td_start : 1; /* Start DMA transfer */ -+#endif -+ } bits; -+} IPSEC_TXDMA_CTRL_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff0c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int td_first_des_ptr : 28;/* first descriptor address */ -+ unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */ -+ unsigned int : 3; -+#else -+ unsigned int : 3; -+ unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */ -+ unsigned int td_first_des_ptr : 28;/* first descriptor address */ -+#endif -+ } bits; -+} IPSEC_TXDMA_FIRST_DESC_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff10 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int ndar : 28; /* next descriptor address */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */ -+ unsigned int sof_eof : 2; -+#else -+ unsigned int sof_eof : 2; -+ unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int ndar : 28; /* next descriptor address */ -+#endif -+ } bits; -+} IPSEC_TXDMA_CURR_DESC_T; -+ -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff14 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int rd_start : 1; /* Start DMA transfer */ -+ unsigned int rd_continue : 1; /* Continue DMA operation */ -+ unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int : 1; -+ unsigned int rd_prot : 4; /* DMA protection control */ -+ unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */ -+ unsigned int rd_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */ -+ unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int : 14; -+#else -+ unsigned int : 14; -+ unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int rd_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */ -+ unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */ -+ unsigned int rd_prot : 4; /* DMA protection control */ -+ unsigned int : 1; -+ unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int rd_continue : 1; /* Continue DMA operation */ -+ unsigned int rd_start : 1; /* Start DMA transfer */ -+#endif -+ } bits; -+} IPSEC_RXDMA_CTRL_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff18 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int rd_first_des_ptr : 28;/* first descriptor address */ -+ unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */ -+ unsigned int : 3; -+#else -+ unsigned int : 3; -+ unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */ -+ unsigned int rd_first_des_ptr : 28;/* first descriptor address */ -+#endif -+ } bits; -+} IPSEC_RXDMA_FIRST_DESC_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff1c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int ndar : 28; /* next descriptor address */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */ -+ unsigned int sof_eof : 2; -+#else -+ unsigned int sof_eof : 2; -+ unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int ndar : 28; /* next descriptor address */ -+#endif -+ } bits; -+} IPSEC_RXDMA_CURR_DESC_T; -+ -+ -+ -+/******************************************************/ -+/* the field definition of IPSEC module Register */ -+/******************************************************/ -+typedef union -+{ -+ unsigned int id; -+ struct bit_0000 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int device_id : 28; -+ unsigned int revision_id : 4; -+#else -+ unsigned int revision_id : 4; -+ unsigned int device_id : 28; -+#endif -+ } bits; -+} IPSEC_ID_T; -+ -+typedef union -+{ -+ unsigned int control; -+ struct bit_0004 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int op_mode : 4; /* Operation Mode for the IPSec Module */ -+ unsigned int : 1; -+ unsigned int cipher_algorithm : 3; -+ unsigned int aesnk : 4; /* AES Key Size */ -+ unsigned int mix_key_sel : 1; /* 0:use rCipherKey0-3 1:use Key Mixer */ -+ unsigned int : 2; -+ unsigned int fcs_stream_copy : 1; /* enable authentication stream copy */ -+ unsigned int auth_mode : 1; /* 0-Append or 1-Check Authentication Result */ -+ unsigned int auth_algorithm : 3; -+ unsigned int : 1; -+ unsigned int auth_check_len : 3; /* Number of 32-bit words to be check or appended */ -+ /* by the authentication module */ -+ unsigned int process_id : 8; /* Used to identify process.This number will be */ -+ /* copied to the descriptor status of received packet*/ -+#else -+ unsigned int process_id : 8; /* Used to identify process.This number will be */ -+ /* copied to the descriptor status of received packet*/ -+ unsigned int auth_check_len : 3; /* Number of 32-bit words to be check or appended */ -+ /* by the authentication module */ -+ unsigned int : 1; -+ unsigned int auth_algorithm : 3; -+ unsigned int auth_mode : 1; /* 0-Append or 1-Check Authentication Result */ -+ unsigned int fcs_stream_copy : 1; /* enable authentication stream copy */ -+ unsigned int : 2; -+ unsigned int mix_key_sel : 1; /* 0:use rCipherKey0-3 1:use Key Mixer */ -+ unsigned int aesnk : 4; /* AES Key Size */ -+ unsigned int cipher_algorithm : 3; -+ unsigned int : 1; -+ unsigned int op_mode : 4; /* Operation Mode for the IPSec Module */ -+#endif -+ } bits; -+} IPSEC_CONTROL_T; -+ -+ -+typedef union -+{ -+ unsigned int cipher_packet; -+ struct bit_0008 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int cipher_header_len : 16; /* The header length to be skipped by the cipher */ -+ unsigned int cipher_algorithm_len : 16; /* The length of message body to be encrypted/decrypted */ -+#else -+ unsigned int cipher_algorithm_len : 16; /* The length of message body to be encrypted/decrypted */ -+ unsigned int cipher_header_len : 16; /* The header length to be skipped by the cipher */ -+#endif -+ } bits; -+} IPSEC_CIPHER_PACKET_T; -+ -+typedef union -+{ -+ unsigned int auth_packet; -+ struct bit_000c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int auth_header_len : 16; /* The header length that is to be skipped by the authenticator */ -+ unsigned int auth_algorithm_len : 16; /* The length of message body that is to be authenticated */ -+#else -+ unsigned int auth_algorithm_len : 16; /* The length of message body that is to be authenticated */ -+ unsigned int auth_header_len : 16; /* The header length that is to be skipped by the authenticator */ -+#endif -+ } bits; -+} IPSEC_AUTH_PACKET_T; -+ -+typedef union -+{ -+ unsigned int status; -+ struct bit_00a8 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int auth_cmp_rslt : 1; /* Authentication Compare result */ -+ unsigned int wep_crc_ok : 1; /* WEP ICV compare result */ -+ unsigned int tkip_mic_ok : 1; /* TKIP Mic compare result */ -+ unsigned int ccm_mic_ok : 1; /* CCM Mic compare result */ -+ unsigned int : 16; -+ unsigned int parser_err_code: 4; /* Authentication Compare result */ -+ unsigned int auth_err_code : 4; /* Authentication module error code */ -+ unsigned int cipher_err_code: 4; /* Cipher module erroe code */ -+#else -+ unsigned int cipher_err_code: 4; /* Cipher module erroe code */ -+ unsigned int auth_err_code : 4; /* Authentication module error code */ -+ unsigned int parser_err_code: 4; /* Authentication Compare result */ -+ unsigned int : 16; -+ unsigned int ccm_mic_ok : 1; /* CCM Mic compare result */ -+ unsigned int tkip_mic_ok : 1; /* TKIP Mic compare result */ -+ unsigned int wep_crc_ok : 1; /* WEP ICV compare result */ -+ unsigned int auth_cmp_rslt : 1; /* Authentication Compare result */ -+#endif -+ } bits; -+} IPSEC_STATUS_T; -+ -+ -+ -+/************************************************************************/ -+/* IPSec Descriptor Format */ -+/************************************************************************/ -+typedef struct descriptor_t -+{ -+ union frame_control_t -+ { -+ unsigned int bits32; -+ struct bits_0000 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int : 1; /* authentication compare result */ -+ unsigned int : 6; /* checksum[15:8] */ -+ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ -+ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ -+#else -+ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ -+ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ -+ unsigned int : 6; /* checksum[15:8] */ -+ unsigned int : 1; /* authentication compare result */ -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ -+#endif -+ } bits; -+ } frame_ctrl; -+ -+ union flag_status_t -+ { -+ unsigned int bits32; -+ struct bits_0004 -+ { -+#if (BIG_ENDIAN==1) -+// unsigned int checksum : 8; /* checksum[7:0] */ -+ unsigned int : 4; -+ unsigned int auth_result: 1; -+ unsigned int wep_crc_ok : 1; -+ unsigned int tkip_mic_ok: 1; -+ unsigned int ccmp_mic_ok: 1; -+ unsigned int process_id : 8; -+ unsigned int frame_count:16; -+#else -+ unsigned int frame_count:16; -+ unsigned int process_id : 8; -+ unsigned int ccmp_mic_ok: 1; -+ unsigned int tkip_mic_ok: 1; -+ unsigned int wep_crc_ok : 1; -+ unsigned int auth_result: 1; -+ unsigned int : 4; -+// unsigned int checksum : 8; /* checksum[7:0] */ -+#endif -+ } bits_rx_status; -+ -+ struct bits_0005 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int : 8; -+ unsigned int process_id : 8; -+ unsigned int frame_count:16; -+#else -+ unsigned int frame_count:16; -+ unsigned int process_id : 8; -+ unsigned int : 8; -+#endif -+ } bits_tx_status; -+ -+ struct bits_0006 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int :22; -+ unsigned int tqflag :10; -+#else -+ unsigned int tqflag :10; -+ unsigned int :22; -+#endif -+ } bits_tx_flag; -+ } flag_status; -+ -+ unsigned int buf_adr; /* data buffer address */ -+ -+ union next_desc_t -+ { -+ unsigned int next_descriptor; -+ struct bits_000c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int ndar :28; /* next descriptor address */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int dec : 1; /* AHB bus address. 0-increment; 1-decrement */ -+ unsigned int sof_eof : 2; /* 00-the linking descriptor 01-the last descriptor of a frame*/ -+ /* 10-the first descriptor of a frame 11-only one descriptor for a frame*/ -+#else -+ unsigned int sof_eof : 2; /* 00-the linking descriptor 01-the last descriptor of a frame*/ -+ /* 10-the first descriptor of a frame 11-only one descriptor for a frame*/ -+ unsigned int dec : 1; /* AHB bus address. 0-increment; 1-decrement */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int ndar :28; /* next descriptor address */ -+#endif -+ } bits; -+ } next_desc; -+} IPSEC_DESCRIPTOR_T; -+ -+ -+typedef struct IPSEC_S -+{ -+ unsigned char *tx_bufs; -+ unsigned char *rx_bufs; -+ IPSEC_DESCRIPTOR_T *tx_desc; /* point to virtual TX descriptor address*/ -+ IPSEC_DESCRIPTOR_T *rx_desc; /* point to virtual RX descriptor address*/ -+ IPSEC_DESCRIPTOR_T *tx_cur_desc; /* point to current TX descriptor */ -+ IPSEC_DESCRIPTOR_T *rx_cur_desc; /* point to current RX descriptor */ -+ IPSEC_DESCRIPTOR_T *tx_finished_desc; -+ IPSEC_DESCRIPTOR_T *rx_finished_desc; -+ dma_addr_t rx_desc_dma; /* physical RX descriptor address */ -+ dma_addr_t tx_desc_dma; /* physical TX descriptor address */ -+ dma_addr_t rx_bufs_dma; /* physical RX descriptor address */ -+ dma_addr_t tx_bufs_dma; /* physical TX descriptor address */ -+} IPSEC_T; -+ -+ -+/*=====================================================================================================*/ -+/* Data Structure of IPSEC Control Packet */ -+/*=====================================================================================================*/ -+typedef struct IPSEC_ECB_AUTH_S -+{ -+ IPSEC_CONTROL_T control; /* control parameter */ -+ IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */ -+ IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */ -+ unsigned char cipher_key[8*4]; -+ unsigned char auth_check_val[5*4]; -+} IPSEC_ECB_AUTH_T; -+ -+typedef struct IPSEC_CBC_AUTH_S -+{ -+ IPSEC_CONTROL_T control; /* control parameter */ -+ IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */ -+ IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */ -+ unsigned char cipher_iv[4*4]; -+ unsigned char cipher_key[8*4]; -+ unsigned char auth_check_val[5*4]; -+} IPSEC_CBC_AUTH_T; -+ -+typedef struct IPSEC_ECB_HMAC_AUTH_S -+{ -+ IPSEC_CONTROL_T control; /* control parameter */ -+ IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */ -+ IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */ -+ unsigned char cipher_key[8*4]; -+ unsigned char auth_key[16*4]; -+ unsigned char auth_check_val[5*4]; -+} IPSEC_ECB_AUTH_HMAC_T; -+ -+typedef struct IPSEC_CBC_HMAC_AUTH_S -+{ -+ IPSEC_CONTROL_T control; /* control parameter */ -+ IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */ -+ IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */ -+ unsigned char cipher_iv[4*4]; -+ unsigned char cipher_key[8*4]; -+ unsigned char auth_key[16*4]; -+ unsigned char auth_check_val[5*4]; -+} IPSEC_CBC_AUTH_HMAC_T; -+ -+typedef struct IPSEC_HMAC_AUTH_S -+{ -+ IPSEC_CONTROL_T control; /* control parameter */ -+ IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */ -+ unsigned char auth_key[16*4]; -+ unsigned char auth_check_val[5*4]; -+} IPSEC_HMAC_AUTH_T; -+ -+typedef union -+{ -+ unsigned char auth_pkt[28]; -+ -+ struct IPSEC_AUTH_S -+ { -+ IPSEC_CONTROL_T control; /* control parameter(4-byte) */ -+ IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter(4-byte) */ -+ unsigned char auth_check_val[5*4]; -+ } var; -+} IPSEC_AUTH_T; -+ -+typedef struct IPSEC_CIPHER_CBC_S -+{ -+ IPSEC_CONTROL_T control; /* control parameter */ -+ IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */ -+ unsigned char cipher_iv[4*4]; -+ unsigned char cipher_key[8*4]; -+} IPSEC_CIPHER_CBC_T; -+ -+typedef struct IPSEC_CIPHER_ECB_S -+{ -+ IPSEC_CONTROL_T control; /* control parameter */ -+ IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */ -+ unsigned char cipher_key[8*4]; -+} IPSEC_CIPHER_ECB_T; -+ -+ -+/**************************************************************************** -+ * Structure Definition * -+ ****************************************************************************/ -+struct IPSEC_PACKET_S -+{ -+ unsigned int op_mode; /* CIPHER_ENC(1),CIPHER_DEC(3),AUTH(4),ENC_AUTH(5),AUTH_DEC(7) */ -+ unsigned int cipher_algorithm; /* ECB_DES(0),ECB_3DES(1),ECB_AES(2),CBC_DES(4),CBC_3DES(5),CBC_AES(6) */ -+ unsigned int auth_algorithm; /* SHA1(0),MD5(1),HMAC_SHA1(2),HMAC_MD5(3),FCS(4) */ -+ unsigned int auth_result_mode; /* AUTH_APPEND(0),AUTH_CHKVAL(1) */ -+ unsigned int process_id; /* Used to identify the process */ -+ unsigned int auth_header_len; /* Header length to be skipped by the authenticator */ -+ unsigned int auth_algorithm_len; /* Length of message body that is to be authenticated */ -+ unsigned int cipher_header_len; /* Header length to be skipped by the cipher */ -+ unsigned int cipher_algorithm_len; /* Length of message body to be encrypted or decrypted */ -+ unsigned char iv[16]; /* Initial vector used for DES,3DES,AES */ -+ unsigned int iv_size; /* Initial vector size */ -+ unsigned char auth_key[64]; /* authentication key */ -+ unsigned int auth_key_size; /* authentication key size */ -+ unsigned char cipher_key[32]; /* cipher key */ -+ unsigned int cipher_key_size; /* cipher key size */ -+ struct scatterlist *in_packet; /* input_packet buffer pointer */ -+ //unsigned char *in_packet; /* input_packet buffer pointer */ -+ unsigned int pkt_len; /* input total packet length */ -+ unsigned char auth_checkval[20]; /* Authentication check value/FCS check value */ -+ struct IPSEC_PACKET_S *next,*prev; /* pointer to next/previous operation to perform on buffer */ -+ void (*callback)(struct IPSEC_PACKET_S *); /* function to call when done authentication/cipher */ -+ unsigned char *out_packet; /* output_packet buffer pointer */ -+ //struct scatterlist *out_packet; /* output_packet buffer pointer */ -+ unsigned int out_pkt_len; /* output total packet length */ -+ unsigned int auth_cmp_result; /* authentication compare result */ -+ unsigned int checksum; /* checksum value */ -+ unsigned int status; /* ipsec return status. 0:success, others:fail */ -+#if (IPSEC_TEST == 1) -+ unsigned char *sw_packet; /* for test only */ -+ unsigned int sw_pkt_len; /* for test only */ -+#endif -+} ; -+ -+/***************************************************************************** -+ * Function : ipsec_crypto_hw_process -+ * Description : This function processes H/W authentication and cipher. -+ * Input : op_info - the authentication and cipher information for IPSec module. -+ * Output : none. -+ * Return : 0 - success, others - failure. -+ *****************************************************************************/ -+int ipsec_crypto_hw_process(struct IPSEC_PACKET_S *op_info); -+ -+int ipsec_get_cipher_algorithm(unsigned char *alg_name,unsigned int alg_mode); -+int ipsec_get_auth_algorithm(unsigned char *alg_name,unsigned int alg_mode); -+#if 0 -+void ipsec_sw_authentication(char *data,unsigned int data_len,char *authkey,char authAlgorithm,char *auth_result); -+void ipsec_sw_cipher(unsigned char *pt,unsigned int pt_len, unsigned char *cipher_key, unsigned int key_size, -+ unsigned char *iv,unsigned int cipherAlgorithm,unsigned char *ct); -+void ipsec_sw_auth_cipher(unsigned int op_mode,char *data,unsigned int data_len, -+ BYTE *auth_key,char authAlgorithm,char *auth_result, -+ char *pt, unsigned int pt_len,char *cipher_key, int key_size, -+ char *iv, char cipherAlgorithm,char *ct); -+#endif -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/sl_random.h -@@ -0,0 +1,2 @@ -+#define RANDOM_ADD (IO_ADDRESS (0x051000000) + 0x0AC) -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/system.h -@@ -0,0 +1,54 @@ -+/* -+ * linux/include/asm-arm/arch-sl2312/system.h -+ * -+ * Copyright (C) 1999 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_SYSTEM_H -+#define __ASM_ARCH_SYSTEM_H -+ -+#include -+#include -+#include -+#include -+ -+static void arch_idle(void) -+{ -+ /* -+ * This should do all the clock switching -+ * and wait for interrupt tricks -+ */ -+ cpu_do_idle(); -+} -+ -+extern __inline__ void arch_reset(char mode) -+{ -+ __raw_writel( (int) GLOBAL_RESET|RESET_CPU1, IO_ADDRESS(SL2312_GLOBAL_BASE) + GLOBAL_RESET_REG); -+} -+ -+ -+void (*pm_power_off)(void); -+//{ -+// printk("arch_power_off\n"); -+ -+ // Power off -+// __raw_writel( (int) 0x00000001, IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04); -+ -+//} -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/timer.h -@@ -0,0 +1,53 @@ -+/* -+ * -+ * This file contains the register definitions for the Excalibur -+ * Timer TIMER00. -+ * -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __TIMER_H -+#define __TIMER_H -+ -+/* -+ * Register definitions for the timers -+ */ -+ -+#define TIMER_COUNT(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x00 )) -+#define TIMER_LOAD(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x04 )) -+#define TIMER_MATCH1(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x08 )) -+#define TIMER_MATCH2(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x0C )) -+#define TIMER_CR(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x30 )) -+#define TIMER_1_CR_ENABLE_MSK (0x00000001) -+#define TIMER_1_CR_ENABLE_OFST (0) -+#define TIMER_1_CR_CLOCK_MSK (0x00000002) -+#define TIMER_1_CR_CLOCK_OFST (1) -+#define TIMER_1_CR_INT_MSK (0x00000004) -+#define TIMER_1_CR_INT_OFST (2) -+#define TIMER_2_CR_ENABLE_MSK (0x00000008) -+#define TIMER_2_CR_ENABLE_OFST (3) -+#define TIMER_2_CR_CLOCK_MSK (0x00000010) -+#define TIMER_2_CR_CLOCK_OFST (4) -+#define TIMER_2_CR_INT_MSK (0x00000020) -+#define TIMER_2_CR_INT_OFST (5) -+#define TIMER_3_CR_ENABLE_MSK (0x00000040) -+#define TIMER_3_CR_ENABLE_OFST (6) -+#define TIMER_3_CR_CLOCK_MSK (0x00000080) -+#define TIMER_3_CR_CLOCK_OFST (7) -+#define TIMER_3_CR_INT_MSK (0x00000100) -+#define TIMER_3_CR_INT_OFST (8) -+ -+#endif /* __TIMER00_H */ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/timex.h -@@ -0,0 +1,29 @@ -+/* -+ * linux/include/asm-arm/arch-epxa10db/timex.h -+ * -+ * Excalibur timex specifications -+ * -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+/* -+ * ?? -+ */ -+#include -+ -+#define CLOCK_TICK_RATE APB_CLK -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/uart.h -@@ -0,0 +1,100 @@ -+/* * -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __UART_H -+#define __UART_H -+ -+/* -+ * Register definitions for the UART -+ */ -+ -+#define UART_TX_FIFO_SIZE (15) -+ -+#define UART_RBR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x00)) // read -+#define UART_THR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x00)) // write -+#define UART_IER(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x04)) -+#define UART_IER_MS (0x08) -+#define UART_IER_RLS (0x04) -+#define UART_IER_TE (0x02) -+#define UART_IER_DR (0x01) -+#define UART_IIR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x08)) // read -+#define UART_IIR_NONE (0x01) /* No interrupt pending */ -+#define UART_IIR_RLS (0x06) /* Receive Line Status */ -+#define UART_IIR_DR (0x04) /* Receive Data Ready */ -+#define UART_IIR_TIMEOUT (0x0c) /* Receive Time Out */ -+#define UART_IIR_TE (0x02) /* THR Empty */ -+#define UART_IIR_MODEM (0x00) /* Modem Status */ -+#define UART_FCR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x08)) // write -+#define UART_FCR_FE (0x01) /* FIFO Enable */ -+#define UART_FCR_RXFR (0x02) /* Rx FIFO Reset */ -+#define UART_FCR_TXFR (0x04) /* Tx FIFO Reset */ -+#define UART_FCR_FIFO_1C (0x00) -+#define UART_FCR_FIFO_4C (0x40) -+#define UART_FCR_FIFO_8C (0x80) -+#define UART_FCR_FIFO_14C (0xC0) -+#define UART_LCR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x0C)) -+#define UART_LCR_MSK (0x03) -+#define UART_LCR_LEN5 (0x00) -+#define UART_LCR_LEN6 (0x01) -+#define UART_LCR_LEN7 (0x02) -+#define UART_LCR_LEN8 (0x03) -+#define UART_LCR_STOP (0x04) -+#define UART_LCR_EVEN (0x18) /* Even Parity */ -+#define UART_LCR_ODD (0x08) /* Odd Parity */ -+#define UART_LCR_PE (0x08) /* Parity Enable */ -+#define UART_LCR_SETBREAK (0x40) /* Set Break condition */ -+#define UART_LCR_STICKPARITY (0x20) /* Stick Parity Enable */ -+#define UART_LCR_DLAB (0x80) /* Divisor Latch Access Bit */ -+#define UART_MCR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x10)) -+#define UART_MCR_DTR (0x1) /* Data Terminal Ready */ -+#define UART_MCR_RTS (0x2) /* Request to Send */ -+#define UART_MCR_OUT1 (0x4) /* output 1 */ -+#define UART_MCR_OUT2 (0x8) /* output2 or global interrupt enable */ -+#define UART_MCR_LPBK (0x10) /* loopback mode */ -+#define UART_MCR_MASK (0xE3) -+#define UART_LSR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x14)) -+#define UART_LSR_DR (0x01) /* Data Ready */ -+#define UART_LSR_OE (0x02) /* Overrun Error */ -+#define UART_LSR_PE (0x04) /* Parity Error */ -+#define UART_LSR_FE (0x08) /* Framing Error */ -+#define UART_LSR_BI (0x10) /* Break Interrupt */ -+#define UART_LSR_THRE (0x20) /* THR Empty */ -+#define UART_LSR_TE (0x40) /* Transmitte Empty */ -+#define UART_LSR_DE (0x80) /* FIFO Data Error */ -+#define UART_MSR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x18)) -+#define UART_MSR_DELTACTS (0x01) /* Delta CTS */ -+#define UART_MSR_DELTADSR (0x02) /* Delta DSR */ -+#define UART_MSR_TERI (0x04) /* Trailing Edge RI */ -+#define UART_MSR_DELTACD (0x08) /* Delta CD */ -+#define UART_MSR_CTS (0x10) /* Clear To Send */ -+#define UART_MSR_DSR (0x20) /* Data Set Ready */ -+#define UART_MSR_RI (0x40) /* Ring Indicator */ -+#define UART_MSR_DCD (0x80) /* Data Carrier Detect */ -+#define UART_SPR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x1C)) -+#define UART_DIV_LO(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x0)) -+#define UART_DIV_HI(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x4)) -+#define UART_PSR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x8)) -+#define UART_MDR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x20)) -+#define UART_MDR_SERIAL (0x0) -+ -+#define UART_MSR_DDCD 0x08 /* Delta DCD */ -+#define UART_MSR_DDSR 0x02 /* Delta DSR */ -+#define UART_MSR_DCTS 0x01 /* Delta CTS */ -+#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ -+ -+ -+#endif /* __UART_H */ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/uncompress.h -@@ -0,0 +1,94 @@ -+/* -+ * linux/include/asm-arm/arch-epxa10db/uncompress.h -+ * -+ * Copyright (C) 1999 ARM Limited -+ * Copyright (C) 2001 Altera Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include "asm/arch/platform.h" -+#include "asm/arch/hardware.h" -+#define UART_TYPE (volatile unsigned int*) -+#ifndef CONFIG_SERIAL_IT8712 -+#include "asm/arch/uart.h" -+#endif -+extern unsigned int it8712_uart_base; -+ -+/* -+ * This does not append a newline -+ */ -+static void putstr(const char *s) -+{ -+ -+#ifdef CONFIG_SERIAL_IT8712 -+ -+ unsigned char *base,*status,stat; -+ int i ; -+ -+ status = (unsigned char*)it8712_uart_base + 5; -+ base = (unsigned char*)it8712_uart_base ; -+ -+ while (*s) { -+ -+ stat = *status; -+ while (!(stat&0x20)) { // check status -+ for(i=0;i<0x10;i++) ; -+ status = (unsigned char*)it8712_uart_base + 5; -+ stat = *status ; -+ } -+ -+ *base = *s; -+ barrier(); -+ -+ if (*s == '\n') { -+ stat = *status; -+ while (!(stat&0x20)) { // check status -+ for(i=0;i<0x10;i++) ; -+ status = (unsigned char*)it8712_uart_base + 5; -+ stat = *status ; -+ } -+ -+ barrier(); -+ *base = '\r'; -+ } -+ s++; -+ } -+ -+#else -+ while (*s) { -+ while (!(*UART_LSR(SL2312_UART_BASE) & -+ UART_LSR_THRE)); -+ barrier(); -+ -+ *UART_THR(SL2312_UART_BASE) = *s; -+ -+ if (*s == '\n') { -+ while (!(*UART_LSR(SL2312_UART_BASE) & -+ UART_LSR_THRE)); -+ barrier(); -+ -+ *UART_THR(SL2312_UART_BASE) = '\r'; -+ } -+ s++; -+ } -+#endif -+} -+ -+/* -+ * nothing to do -+ */ -+#define arch_decomp_setup() -+ -+#define arch_decomp_wdog() ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/vmalloc.h -@@ -0,0 +1,36 @@ -+/* -+ * linux/include/asm-arm/arch-epxa10db/vmalloc.h -+ * -+ * Copyright (C) 2000 Russell King. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+/* -+ * Just any arbitrary offset to the start of the vmalloc VM area: the -+ * current 8MB value just means that there will be a 8MB "hole" after the -+ * physical memory until the kernel virtual memory starts. That means that -+ * any out-of-bounds memory accesses will hopefully be caught. -+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced -+ * area for the same reason. ;) -+ */ -+#define VMALLOC_OFFSET (8*1024*1024) -+#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) -+#define VMALLOC_VMADDR(x) ((unsigned long)(x)) -+#define VMALLOC_END (PAGE_OFFSET + 0x10000000) -+ -+//#define MODULE_START (PAGE_OFFSET - 16*1048576) -+//#define MODULE_END (PAGE_OFFSET) -+ ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/watchdog.h -@@ -0,0 +1,58 @@ -+#ifndef __WATCHDOG_H -+#define __WATCHDOG_H -+ -+#define WATCHDOG_BASE (IO_ADDRESS (SL2312_WAQTCHDOG_BASE)) -+#define WATCHDOG_COUNTER (WATCHDOG_BASE + 0x00) -+#define WATCHDOG_LOAD (WATCHDOG_BASE + 0x04) -+#define WATCHDOG_RESTART (WATCHDOG_BASE + 0x08) -+#define WATCHDOG_CR (WATCHDOG_BASE + 0x0C) -+#define WATCHDOG_STATUS (WATCHDOG_BASE + 0x10) -+#define WATCHDOG_CLEAR (WATCHDOG_BASE + 0x14) -+#define WATCHDOG_INTRLEN (WATCHDOG_BASE + 0x18) -+ -+#define WATCHDOG_WDENABLE_MSK (0x00000001) -+#define WATCHDOG_WDENABLE_OFST (0) -+#define WATCHDOG_WDRST_MSK (0x00000002) -+#define WATCHDOG_WDRST_OFST (1) -+#define WATCHDOG_WDINTR_MSK (0x00000004) -+#define WATCHDOG_WDINTR_OFST (2) -+#define WATCHDOG_WDEXT_MSK (0x00000008) -+#define WATCHDOG_WDEXT_OFST (3) -+#define WATCHDOG_WDCLOCK_MSK (0x00000010) -+#define WATCHDOG_WDCLOCK_OFST (4) -+#define WATCHDOG_CR_MASK (0x0000001F) -+ -+#define WATCHDOG_CLEAR_STATUS 0x1 -+#define WATCHDOG_ENABLE 1 -+#define WATCHDOG_DISABLE 0 -+#define WATCHDOG_RESTART_VALUE 0x5AB9 -+ -+#define WATCHDOG_MINOR 130 -+ -+#define WATCHDOG_IOCTRL_DISABLE 0x01 -+#define WATCHDOG_IOCTRL_SETTIME 0x02 -+#define WATCHDOG_IOCTRL_ENABLE 0x03 -+#define WATCHDOG_IOCTRL_RESTART 0x04 -+ -+#define WATCHDOG_TIMEOUT_SCALE APB_CLK -+#define WATCHDOG_TIMEOUT_MARGIN 30 -+#define WATCHDOG_DRIVER_OPEN 1 -+#define WATCHDOG_DRIVER_CLOSE 0 -+ -+ -+static void watchdog_disable(void); -+static void watchdog_enable(void); -+static int watchdog_open(struct inode *, struct file *); -+static int watchdog_release(struct inode *, struct file *); -+static ssize_t watchdog_read(struct file *, char *, size_t, loff_t *); -+static ssize_t watchdog_write(struct file *, const char *, size_t, loff_t *); -+static int watchdog_ioctl(struct inode *, struct file *, unsigned int, unsigned long); -+#ifdef WATCHDOG_TEST -+static void watchdog_fire(int, void *, struct pt_regs *); -+#endif -+ -+ -+ -+ -+ -+#endif ---- /dev/null -+++ b/include/asm-arm/arch-sl2312/xor.h -@@ -0,0 +1,29 @@ -+/* -+ * include/asm-arm/arch-sl2312/xor.h -+ * -+ * Copyright (C) 2005 Storlink Corp. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef _ASM_ARCH_XOR_H -+#define _ASM_ARCH_XOR_H -+ -+/* -+ * Function prototypes -+ */ -+void xor_gemini_2(unsigned long bytes, unsigned long *p1, unsigned long *p2); -+ -+void xor_gemini_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, -+ unsigned long *p3); -+ -+void xor_gemini_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, -+ unsigned long *p3, unsigned long *p4); -+ -+void xor_gemini_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, -+ unsigned long *p3, unsigned long *p4, unsigned long *p5); -+ -+#endif /* _ASM_ARCH_XOR_H */ -+ ---- a/include/asm-arm/cacheflush.h -+++ b/include/asm-arm/cacheflush.h -@@ -46,6 +46,18 @@ - # define MULTI_CACHE 1 - #endif - -+/*********************************************************************** -+ * Storlink SoC -- Cache -+ ***********************************************************************/ -+#if defined(CONFIG_CPU_FA526) -+# ifdef _CACHE -+# define MULTI_CACHE 1 -+# else -+# define _CACHE fa -+# endif -+#endif -+/***********************************************************************/ -+ - #if defined(CONFIG_CPU_ARM926T) - # ifdef _CACHE - # define MULTI_CACHE 1 ---- a/include/asm-arm/page.h -+++ b/include/asm-arm/page.h -@@ -74,6 +74,18 @@ - # endif - #endif - -+/*********************************************************************** -+ * Storlink SoC -- flash -+ ***********************************************************************/ -+#ifdef CONFIG_CPU_COPY_FA -+# ifdef _USER -+# define MULTI_USER 1 -+# else -+# define _USER fa -+# endif -+#endif -+/***********************************************************************/ -+ - #ifdef CONFIG_CPU_SA1100 - # ifdef _USER - # define MULTI_USER 1 ---- a/include/asm-arm/proc-fns.h -+++ b/include/asm-arm/proc-fns.h -@@ -89,6 +89,14 @@ - # define CPU_NAME cpu_arm922 - # endif - # endif -+# ifdef CONFIG_CPU_FA526 -+# ifdef CPU_NAME -+# undef MULTI_CPU -+# define MULTI_CPU -+# else -+# define CPU_NAME cpu_fa526 -+# endif -+# endif - # ifdef CONFIG_CPU_ARM925T - # ifdef CPU_NAME - # undef MULTI_CPU ---- a/include/asm-arm/tlbflush.h -+++ b/include/asm-arm/tlbflush.h -@@ -39,6 +39,8 @@ - #define TLB_V6_D_ASID (1 << 17) - #define TLB_V6_I_ASID (1 << 18) - -+#define TLB_DINVAL (1 << 28) -+#define TLB_BTB (1 << 29) - #define TLB_DCLEAN (1 << 30) - #define TLB_WB (1 << 31) - -@@ -52,6 +54,7 @@ - * v4wb - ARMv4 with write buffer without I TLB flush entry instruction - * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction - * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction -+ * fa - ARMv4 with write buffer with UTLB and branch target buffer (BTB) - */ - #undef _TLB - #undef MULTI_TLB -@@ -86,6 +89,44 @@ - # define v4_always_flags (-1UL) - #endif - -+#ifdef CONFIG_CPU_FA_BTB -+#define __TLB_BTB TLB_BTB -+#else -+#define __TLB_BTB 0 -+#endif -+ -+#ifdef CONFIG_CPU_FA_WB_DISABLE -+#define __TLB_WB 0 -+#else -+#define __TLB_WB TLB_WB -+#endif -+ -+/* Fix buggy CPU which doesn't invalidate Dcache properly */ -+#ifdef CONFIG_CPU_FA520 -+#define __TLB_DINVAL TLB_DINVAL -+#elif defined(CONFIG_CPU_FA526) -+//#define __TLB_DINVAL TLB_DINVAL -+#define __TLB_DINVAL 0 -+#else -+#define __TLB_DINVAL 0 -+#endif -+ -+#define fa_tlb_flags (__TLB_WB | __TLB_BTB | __TLB_DINVAL | TLB_DCLEAN | \ -+ TLB_V4_U_FULL | TLB_V4_U_PAGE) -+ -+#ifdef CONFIG_CPU_TLB_FA -+# define fa_possible_flags fa_tlb_flags -+# define fa_always_flags fa_tlb_flags -+# ifdef _TLB -+# define MULTI_TLB 1 -+# else -+# define _TLB fa -+# endif -+#else -+# define fa_possible_flags 0 -+# define fa_always_flags (-1UL) -+#endif -+ - #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ - TLB_V4_I_FULL | TLB_V4_D_FULL | \ - TLB_V4_I_PAGE | TLB_V4_D_PAGE) -@@ -246,12 +287,14 @@ - v4_possible_flags | \ - v4wbi_possible_flags | \ - v4wb_possible_flags | \ -+ fa_possible_flags | \ - v6wbi_possible_flags) - - #define always_tlb_flags (v3_always_flags & \ - v4_always_flags & \ - v4wbi_always_flags & \ - v4wb_always_flags & \ -+ fa_always_flags & \ - v6wbi_always_flags) - - #define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) -@@ -261,6 +304,9 @@ - const int zero = 0; - const unsigned int __tlb_flag = __cpu_tlb_flags; - -+ if (tlb_flag(TLB_DINVAL)) -+ asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero)); -+ - if (tlb_flag(TLB_WB)) - dsb(); - -@@ -281,6 +327,13 @@ - dsb(); - isb(); - } -+ -+ if (tlb_flag(TLB_BTB)) -+ { -+ asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero)); -+ asm("mov r0, r0" : : ); -+ asm("mov r0, r0" : : ); -+ } - } - - static inline void local_flush_tlb_mm(struct mm_struct *mm) -@@ -289,6 +342,9 @@ - const int asid = ASID(mm); - const unsigned int __tlb_flag = __cpu_tlb_flags; - -+ if (tlb_flag(TLB_DINVAL)) -+ asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero)); -+ - if (tlb_flag(TLB_WB)) - dsb(); - -@@ -317,6 +373,14 @@ - asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); - dsb(); - } -+ -+ if (tlb_flag(TLB_BTB)) -+ { -+ asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero)); -+ asm("mov r0, r0" : : ); -+ asm("mov r0, r0" : : ); -+ } -+ - } - - static inline void -@@ -327,6 +391,9 @@ - - uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); - -+ if (tlb_flag(TLB_DINVAL)) -+ asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero)); // clean & invalidate data cache all -+ - if (tlb_flag(TLB_WB)) - dsb(); - -@@ -357,6 +424,13 @@ - asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); - dsb(); - } -+ -+ if (tlb_flag(TLB_BTB)) -+ { -+ asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero)); -+ asm("mov r0, r0" : : ); -+ asm("mov r0, r0" : : ); -+ } - } - - static inline void local_flush_tlb_kernel_page(unsigned long kaddr) -@@ -366,6 +440,9 @@ - - kaddr &= PAGE_MASK; - -+ if (tlb_flag(TLB_DINVAL)) -+ asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero)); -+ - if (tlb_flag(TLB_WB)) - dsb(); - -@@ -386,6 +463,12 @@ - asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); - if (tlb_flag(TLB_V6_I_PAGE)) - asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); -+ if (tlb_flag(TLB_BTB)) -+ { -+ asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero)); -+ asm("mov r0, r0" : : ); -+ asm("mov r0, r0" : : ); -+ } - - if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | - TLB_V6_I_PAGE | TLB_V6_D_PAGE | -@@ -412,6 +495,7 @@ - */ - static inline void flush_pmd_entry(pmd_t *pmd) - { -+ const unsigned int zero = 0; - const unsigned int __tlb_flag = __cpu_tlb_flags; - - if (tlb_flag(TLB_DCLEAN)) -@@ -419,15 +503,30 @@ - : : "r" (pmd) : "cc"); - if (tlb_flag(TLB_WB)) - dsb(); -+ -+ if (tlb_flag(TLB_BTB)) // Luke Lee 05/16/2005 -+ { -+ asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero)); -+ asm("mov r0, r0" : : ); -+ asm("mov r0, r0" : : ); -+ } - } - - static inline void clean_pmd_entry(pmd_t *pmd) - { -+ const unsigned int zero = 0; // Luke Lee 05/16/2005 ins 1 - const unsigned int __tlb_flag = __cpu_tlb_flags; - - if (tlb_flag(TLB_DCLEAN)) - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" - : : "r" (pmd) : "cc"); -+ -+ if (tlb_flag(TLB_BTB)) // Luke Lee 05/16/2005 -+ { -+ asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero)); -+ asm("mov r0, r0" : : ); -+ asm("mov r0, r0" : : ); -+ } - } - - #undef tlb_flag ---- a/include/asm-arm/xor.h -+++ b/include/asm-arm/xor.h -@@ -139,3 +139,18 @@ - xor_speed(&xor_block_8regs); \ - xor_speed(&xor_block_32regs); \ - } while (0) -+ -+#ifdef CONFIG_GEMINI_XOR_ACCE -+#include -+static struct xor_block_template xor_block_gemini = { -+ .name = "gemini xor acceleration", -+ .do_2 = xor_gemini_2, -+ .do_3 = xor_gemini_3, -+ .do_4 = xor_gemini_4, -+ .do_5 = xor_gemini_5,}; -+#undef XOR_TRY_TEMPLATES -+#define XOR_TRY_TEMPLATES \ -+ do { \ -+ xor_speed(&xor_block_gemini); \ -+ } while (0) -+#endif ---- a/include/linux/apm_bios.h -+++ b/include/linux/apm_bios.h -@@ -217,4 +217,24 @@ - #define APM_IOC_STANDBY _IO('A', 1) - #define APM_IOC_SUSPEND _IO('A', 2) - -+// add by jason for power control -+struct pwc_ioctl_data { -+ unsigned int action; // sword struct -+ unsigned int data; // stand shutdown time for PWC_SET_SHUT_TIME -+ // stand shutdown source for PWC_WAIT_BTN -+}; -+ -+#define POWEROFF 0x01 -+#define RESTORE_DEFAULT 0x02 -+#define SYSTEM_REBOOT 0x04 -+ -+#define PWR_SRC_CIR 0x10 -+#define PWR_SRC_RTC 0x20 -+#define PWR_SRC_BTN 0x40 -+ -+#define PWC_IOCTL_BASE 'A' // use linux APM ioctl -+#define PWC_SET_SHUT_TIME _IOW('A', 16, struct pwc_ioctl_data) -+#define PWC_WAIT_BTN _IOR('A', 17, struct pwc_ioctl_data) -+#define PWC_SHUTDOWN _IO ('A', 18) -+ - #endif /* LINUX_APM_H */ ---- a/kernel/time.c -+++ b/kernel/time.c -@@ -76,6 +76,7 @@ - * why not move it into the appropriate arch directory (for those - * architectures that need it). - */ -+extern void rtc_set_time_second(unsigned int second); - - asmlinkage long sys_stime(time_t __user *tptr) - { -@@ -87,6 +88,10 @@ - - tv.tv_nsec = 0; - -+#ifdef CONFIG_SL2312_RTC -+ rtc_set_time_second(tv.tv_sec); -+#endif -+ - err = security_settime(&tv, NULL); - if (err) - return err; diff --git a/target/linux/storm/patches/002-gmac.patch b/target/linux/storm/patches/002-gmac.patch deleted file mode 100644 index d6632ba381..0000000000 --- a/target/linux/storm/patches/002-gmac.patch +++ /dev/null @@ -1,18615 +0,0 @@ ---- /dev/null -+++ b/drivers/net/sl2312_emac.c -@@ -0,0 +1,4604 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BIG_ENDIAN 0 -+ -+#define GMAC_DEBUG 0 -+ -+#define GMAC_PHY_IF 2 -+ -+/* define PHY address */ -+#define HPHY_ADDR 0x01 -+#define GPHY_ADDR 0x02 -+ -+#define CONFIG_ADM_6999 1 -+/* define chip information */ -+#define DRV_NAME "SL2312" -+#define DRV_VERSION "0.1.1" -+#define SL2312_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION -+ -+/* define TX/RX descriptor parameter */ -+#define MAX_ETH_FRAME_SIZE 1920 -+#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE -+#define TX_DESC_NUM 128 -+#define TX_BUF_TOT_LEN (TX_BUF_SIZE * TX_DESC_NUM) -+#define RX_BUF_SIZE MAX_ETH_FRAME_SIZE -+#define RX_DESC_NUM 256 -+#define RX_BUF_TOT_LEN (RX_BUF_SIZE * RX_DESC_NUM) -+#define MAX_ISR_WORK 20 -+ -+unsigned int int_status = 0; -+ -+/* define GMAC base address */ -+#define GMAC_PHYSICAL_BASE_ADDR (SL2312_GMAC_BASE) -+#define GMAC_BASE_ADDR (IO_ADDRESS(GMAC_PHYSICAL_BASE_ADDR)) -+#define GMAC_GLOBAL_BASE_ADDR (IO_ADDRESS(SL2312_GLOBAL_BASE)) -+ -+#define GMAC0_BASE (IO_ADDRESS(SL2312_GMAC0_BASE)) -+#define GMAC1_BASE (IO_ADDRESS(SL2312_GMAC1_BASE)) -+ -+/* memory management utility */ -+#define DMA_MALLOC(size,handle) pci_alloc_consistent(NULL,size,handle) -+#define DMA_MFREE(mem,size,handle) pci_free_consistent(NULL,size,mem,handle) -+ -+//#define gmac_read_reg(offset) (readl(GMAC_BASE_ADDR + offset)) -+//#define gmac_write_reg(offset,data,mask) writel( (gmac_read_reg(offset)&~mask) |(data&mask),(GMAC_BASE_ADDR+offset)) -+ -+/* define owner bit */ -+#define CPU 0 -+#define DMA 1 -+ -+#define ACTIVE 1 -+#define NONACTIVE 0 -+ -+#define CONFIG_SL_NAPI -+ -+#ifndef CONFIG_SL2312_MPAGE -+#define CONFIG_SL2312_MPAGE -+#endif -+ -+#ifdef CONFIG_SL2312_MPAGE -+#include -+#include -+#include -+#endif -+ -+#ifndef CONFIG_TXINT_DISABLE -+//#define CONFIG_TXINT_DISABLE -+#endif -+ -+enum phy_state -+{ -+ LINK_DOWN = 0, -+ LINK_UP = 1 -+}; -+ -+ -+/* transmit timeout value */ -+#define TX_TIMEOUT (6*HZ) -+ -+/***************************************/ -+/* the offset address of GMAC register */ -+/***************************************/ -+enum GMAC_REGISTER { -+ GMAC_STA_ADD0 = 0x0000, -+ GMAC_STA_ADD1 = 0x0004, -+ GMAC_STA_ADD2 = 0x0008, -+ GMAC_RX_FLTR = 0x000c, -+ GMAC_MCAST_FIL0 = 0x0010, -+ GMAC_MCAST_FIL1 = 0x0014, -+ GMAC_CONFIG0 = 0x0018, -+ GMAC_CONFIG1 = 0x001c, -+ GMAC_CONFIG2 = 0x0020, -+ GMAC_BNCR = 0x0024, -+ GMAC_RBNR = 0x0028, -+ GMAC_STATUS = 0x002c, -+ GMAC_IN_DISCARDS= 0x0030, -+ GMAC_IN_ERRORS = 0x0034, -+ GMAC_IN_MCAST = 0x0038, -+ GMAC_IN_BCAST = 0x003c, -+ GMAC_IN_MAC1 = 0x0040, -+ GMAC_IN_MAC2 = 0x0044 -+}; -+ -+/*******************************************/ -+/* the offset address of GMAC DMA register */ -+/*******************************************/ -+enum GMAC_DMA_REGISTER { -+ GMAC_DMA_DEVICE_ID = 0xff00, -+ GMAC_DMA_STATUS = 0xff04, -+ GMAC_TXDMA_CTRL = 0xff08, -+ GMAC_TXDMA_FIRST_DESC = 0xff0c, -+ GMAC_TXDMA_CURR_DESC = 0xff10, -+ GMAC_RXDMA_CTRL = 0xff14, -+ GMAC_RXDMA_FIRST_DESC = 0xff18, -+ GMAC_RXDMA_CURR_DESC = 0xff1c, -+}; -+ -+/*******************************************/ -+/* the register structure of GMAC */ -+/*******************************************/ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit1_0004 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int sta_add2_l16 : 16; /* station MAC address2 bits 15 to 0 */ -+ unsigned int sta_add1_h16 : 16; /* station MAC address1 bits 47 to 32 */ -+#else -+ unsigned int sta_add1_h16 : 16; /* station MAC address1 bits 47 to 32 */ -+ unsigned int sta_add2_l16 : 16; /* station MAC address2 bits 15 to 0 */ -+#endif -+ } bits; -+} GMAC_STA_ADD1_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit1_000c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int : 27; -+ unsigned int error : 1; /* enable receive of all error frames */ -+ unsigned int promiscuous : 1; /* enable receive of all frames */ -+ unsigned int broadcast : 1; /* enable receive of broadcast frames */ -+ unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */ -+ unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */ -+#else -+ unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */ -+ unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */ -+ unsigned int broadcast : 1; /* enable receive of broadcast frames */ -+ unsigned int promiscuous : 1; /* enable receive of all frames */ -+ unsigned int error : 1; /* enable receive of all error frames */ -+ unsigned int : 27; -+#endif -+ } bits; -+} GMAC_RX_FLTR_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit1_0018 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int : 10; -+ unsigned int inv_rx_clk : 1; /* Inverse RX Clock */ -+ unsigned int rising_latch : 1; -+ unsigned int rx_tag_remove : 1; /* Remove Rx VLAN tag */ -+ unsigned int ipv6_tss_rx_en : 1; /* IPv6 TSS RX enable */ -+ unsigned int ipv4_tss_rx_en : 1; /* IPv4 TSS RX enable */ -+ unsigned int rgmii_en : 1; /* RGMII in-band status enable */ -+ unsigned int tx_fc_en : 1; /* TX flow control enable */ -+ unsigned int rx_fc_en : 1; /* RX flow control enable */ -+ unsigned int sim_test : 1; /* speed up timers in simulation */ -+ unsigned int dis_col : 1; /* disable 16 collisions abort function */ -+ unsigned int dis_bkoff : 1; /* disable back-off function */ -+ unsigned int max_len : 3; /* maximum receive frame length allowed */ -+ unsigned int adj_ifg : 4; /* adjust IFG from 96+/-56 */ -+ unsigned int : 1; /* reserved */ -+ unsigned int loop_back : 1; /* transmit data loopback enable */ -+ unsigned int dis_rx : 1; /* disable receive */ -+ unsigned int dis_tx : 1; /* disable transmit */ -+#else -+ unsigned int dis_tx : 1; /* disable transmit */ -+ unsigned int dis_rx : 1; /* disable receive */ -+ unsigned int loop_back : 1; /* transmit data loopback enable */ -+ unsigned int : 1; /* reserved */ -+ unsigned int adj_ifg : 4; /* adjust IFG from 96+/-56 */ -+ unsigned int max_len : 3; /* maximum receive frame length allowed */ -+ unsigned int dis_bkoff : 1; /* disable back-off function */ -+ unsigned int dis_col : 1; /* disable 16 collisions abort function */ -+ unsigned int sim_test : 1; /* speed up timers in simulation */ -+ unsigned int rx_fc_en : 1; /* RX flow control enable */ -+ unsigned int tx_fc_en : 1; /* TX flow control enable */ -+ unsigned int rgmii_en : 1; /* RGMII in-band status enable */ -+ unsigned int ipv4_tss_rx_en : 1; /* IPv4 TSS RX enable */ -+ unsigned int ipv6_tss_rx_en : 1; /* IPv6 TSS RX enable */ -+ unsigned int rx_tag_remove : 1; /* Remove Rx VLAN tag */ -+ unsigned int rising_latch : 1; -+ unsigned int inv_rx_clk : 1; /* Inverse RX Clock */ -+ unsigned int : 10; -+#endif -+ } bits; -+} GMAC_CONFIG0_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit1_001c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int : 28; -+ unsigned int buf_size : 4; /* per packet buffer size */ -+#else -+ unsigned int buf_size : 4; /* per packet buffer size */ -+ unsigned int : 28; -+#endif -+ } bits; -+} GMAC_CONFIG1_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit1_0020 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int rel_threshold : 16; /* flow control release threshold */ -+ unsigned int set_threshold : 16; /* flow control set threshold */ -+#else -+ unsigned int set_threshold : 16; /* flow control set threshold */ -+ unsigned int rel_threshold : 16; /* flow control release threshold */ -+#endif -+ } bits; -+} GMAC_CONFIG2_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit1_0024 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int : 16; -+ unsigned int buf_num : 16; /* return buffer number from software */ -+#else -+ unsigned int buf_num : 16; /* return buffer number from software */ -+ unsigned int : 16; -+#endif -+ } bits; -+} GMAC_BNCR_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit1_0028 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int : 16; -+ unsigned int buf_remain : 16; /* remaining buffer number */ -+#else -+ unsigned int buf_remain : 16; /* remaining buffer number */ -+ unsigned int : 16; -+#endif -+ } bits; -+} GMAC_RBNR_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit1_002c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int : 25; -+ unsigned int mii_rmii : 2; /* PHY interface type */ -+ unsigned int phy_mode : 1; /* PHY interface mode in 10M-bps */ -+ unsigned int duplex : 1; /* duplex mode */ -+ unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */ -+ unsigned int link : 1; /* link status */ -+#else -+ unsigned int link : 1; /* link status */ -+ unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */ -+ unsigned int duplex : 1; /* duplex mode */ -+ unsigned int phy_mode : 1; /* PHY interface mode in 10M-bps */ -+ unsigned int mii_rmii : 2; /* PHY interface type */ -+ unsigned int : 25; -+#endif -+ } bits; -+} GMAC_STATUS_T; -+ -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit1_009 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int : 10; -+ unsigned int tx_fail : 1; /* Tx fail interrupt */ -+ unsigned int cnt_full : 1; /* MIB counters half full interrupt */ -+ unsigned int rx_pause_on : 1; /* received pause on frame interrupt */ -+ unsigned int tx_pause_on : 1; /* transmit pause on frame interrupt */ -+ unsigned int rx_pause_off : 1; /* received pause off frame interrupt */ -+ unsigned int tx_pause_off : 1; /* received pause off frame interrupt */ -+ unsigned int rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */ -+ unsigned int tx_underrun : 1; /* GMAC Tx FIFO underrun interrupt */ -+ unsigned int : 6; -+ unsigned int m_tx_fail : 1; /* Tx fail interrupt mask */ -+ unsigned int m_cnt_full : 1; /* MIB counters half full interrupt mask */ -+ unsigned int m_rx_pause_on : 1; /* received pause on frame interrupt mask */ -+ unsigned int m_tx_pause_on : 1; /* transmit pause on frame interrupt mask */ -+ unsigned int m_rx_pause_off : 1; /* received pause off frame interrupt mask */ -+ unsigned int m_tx_pause_off : 1; /* received pause off frame interrupt mask */ -+ unsigned int m_rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt mask */ -+ unsigned int m_tx_underrun : 1; /* GMAC Tx FIFO underrun interrupt mask */ -+#else -+ unsigned int m_tx_underrun : 1; /* GMAC Tx FIFO underrun interrupt mask */ -+ unsigned int m_rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt mask */ -+ unsigned int m_tx_pause_off : 1; /* received pause off frame interrupt mask */ -+ unsigned int m_rx_pause_off : 1; /* received pause off frame interrupt mask */ -+ unsigned int m_tx_pause_on : 1; /* transmit pause on frame interrupt mask */ -+ unsigned int m_rx_pause_on : 1; /* received pause on frame interrupt mask */ -+ unsigned int m_cnt_full : 1; /* MIB counters half full interrupt mask */ -+ unsigned int m_tx_fail : 1; /* Tx fail interrupt mask */ -+ unsigned int : 6; -+ unsigned int tx_underrun : 1; /* GMAC Tx FIFO underrun interrupt */ -+ unsigned int rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */ -+ unsigned int tx_pause_off : 1; /* received pause off frame interrupt */ -+ unsigned int rx_pause_off : 1; /* received pause off frame interrupt */ -+ unsigned int tx_pause_on : 1; /* transmit pause on frame interrupt */ -+ unsigned int rx_pause_on : 1; /* received pause on frame interrupt */ -+ unsigned int cnt_full : 1; /* MIB counters half full interrupt */ -+ unsigned int tx_fail : 1; /* Tx fail interrupt */ -+ unsigned int : 10; -+#endif -+ } bits; -+} GMAC_INT_MASK_T; -+ -+ -+/*******************************************/ -+/* the register structure of GMAC DMA */ -+/*******************************************/ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff00 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int : 7; /* reserved */ -+ unsigned int s_ahb_err : 1; /* Slave AHB bus error */ -+ unsigned int tx_err_code : 4; /* TxDMA error code */ -+ unsigned int rx_err_code : 4; /* RxDMA error code */ -+ unsigned int device_id : 12; -+ unsigned int revision_id : 4; -+#else -+ unsigned int revision_id : 4; -+ unsigned int device_id : 12; -+ unsigned int rx_err_code : 4; /* RxDMA error code */ -+ unsigned int tx_err_code : 4; /* TxDMA error code */ -+ unsigned int s_ahb_err : 1; /* Slave AHB bus error */ -+ unsigned int : 7; /* reserved */ -+#endif -+ } bits; -+} GMAC_DMA_DEVICE_ID_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff04 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int ts_finish : 1; /* finished tx interrupt */ -+ unsigned int ts_derr : 1; /* AHB Bus Error while tx */ -+ unsigned int ts_perr : 1; /* Tx Descriptor protocol error */ -+ unsigned int ts_eodi : 1; /* TxDMA end of descriptor interrupt */ -+ unsigned int ts_eofi : 1; /* TxDMA end of frame interrupt */ -+ unsigned int rs_finish : 1; /* finished rx interrupt */ -+ unsigned int rs_derr : 1; /* AHB Bus Error while rx */ -+ unsigned int rs_perr : 1; /* Rx Descriptor protocol error */ -+ unsigned int rs_eodi : 1; /* RxDMA end of descriptor interrupt */ -+ unsigned int rs_eofi : 1; /* RxDMA end of frame interrupt */ -+ unsigned int : 1; /* Tx fail interrupt */ -+ unsigned int cnt_full : 1; /* MIB counters half full interrupt */ -+ unsigned int rx_pause_on : 1; /* received pause on frame interrupt */ -+ unsigned int tx_pause_on : 1; /* transmit pause on frame interrupt */ -+ unsigned int rx_pause_off : 1; /* received pause off frame interrupt */ -+ unsigned int tx_pause_off : 1; /* received pause off frame interrupt */ -+ unsigned int rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */ -+ unsigned int link_change : 1; /* GMAC link changed Interrupt for RGMII mode */ -+ unsigned int : 1; -+ unsigned int : 1; -+ unsigned int : 3; -+ unsigned int loop_back : 1; /* loopback TxDMA to RxDMA */ -+ unsigned int : 1; /* Tx fail interrupt mask */ -+ unsigned int m_cnt_full : 1; /* MIB counters half full interrupt mask */ -+ unsigned int m_rx_pause_on : 1; /* received pause on frame interrupt mask */ -+ unsigned int m_tx_pause_on : 1; /* transmit pause on frame interrupt mask */ -+ unsigned int m_rx_pause_off : 1; /* received pause off frame interrupt mask */ -+ unsigned int m_tx_pause_off : 1; /* received pause off frame interrupt mask */ -+ unsigned int m_rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt mask */ -+ unsigned int m_link_change : 1; /* GMAC link changed Interrupt mask for RGMII mode */ -+#else -+ unsigned int m_link_change : 1; /* GMAC link changed Interrupt mask for RGMII mode */ -+ unsigned int m_rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt mask */ -+ unsigned int m_tx_pause_off : 1; /* received pause off frame interrupt mask */ -+ unsigned int m_rx_pause_off : 1; /* received pause off frame interrupt mask */ -+ unsigned int m_tx_pause_on : 1; /* transmit pause on frame interrupt mask */ -+ unsigned int m_rx_pause_on : 1; /* received pause on frame interrupt mask */ -+ unsigned int m_cnt_full : 1; /* MIB counters half full interrupt mask */ -+ unsigned int : 1; /* Tx fail interrupt mask */ -+ unsigned int loop_back : 1; /* loopback TxDMA to RxDMA */ -+ unsigned int : 3; -+ unsigned int : 1; -+ unsigned int : 1; -+ unsigned int link_change : 1; /* GMAC link changed Interrupt for RGMII mode */ -+ unsigned int rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */ -+ unsigned int tx_pause_off : 1; /* received pause off frame interrupt */ -+ unsigned int rx_pause_off : 1; /* received pause off frame interrupt */ -+ unsigned int tx_pause_on : 1; /* transmit pause on frame interrupt */ -+ unsigned int rx_pause_on : 1; /* received pause on frame interrupt */ -+ unsigned int cnt_full : 1; /* MIB counters half full interrupt */ -+ unsigned int : 1; /* Tx fail interrupt */ -+ unsigned int rs_eofi : 1; /* RxDMA end of frame interrupt */ -+ unsigned int rs_eodi : 1; /* RxDMA end of descriptor interrupt */ -+ unsigned int rs_perr : 1; /* Rx Descriptor protocol error */ -+ unsigned int rs_derr : 1; /* AHB Bus Error while rx */ -+ unsigned int rs_finish : 1; /* finished rx interrupt */ -+ unsigned int ts_eofi : 1; /* TxDMA end of frame interrupt */ -+ unsigned int ts_eodi : 1; /* TxDMA end of descriptor interrupt */ -+ unsigned int ts_perr : 1; /* Tx Descriptor protocol error */ -+ unsigned int ts_derr : 1; /* AHB Bus Error while tx */ -+ unsigned int ts_finish : 1; /* finished tx interrupt */ -+#endif -+ } bits; -+} GMAC_DMA_STATUS_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff08 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int td_start : 1; /* Start DMA transfer */ -+ unsigned int td_continue : 1; /* Continue DMA operation */ -+ unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int : 1; -+ unsigned int td_prot : 4; /* TxDMA protection control */ -+ unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */ -+ unsigned int td_bus : 2; /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */ -+ unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int : 14; -+#else -+ unsigned int : 14; -+ unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int td_bus : 2; /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */ -+ unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */ -+ unsigned int td_prot : 4; /* TxDMA protection control */ -+ unsigned int : 1; -+ unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int td_continue : 1; /* Continue DMA operation */ -+ unsigned int td_start : 1; /* Start DMA transfer */ -+#endif -+ } bits; -+} GMAC_TXDMA_CTRL_T; -+ -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff0c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int td_first_des_ptr : 28;/* first descriptor address */ -+ unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */ -+ unsigned int : 3; -+#else -+ unsigned int : 3; -+ unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */ -+ unsigned int td_first_des_ptr : 28;/* first descriptor address */ -+#endif -+ } bits; -+} GMAC_TXDMA_FIRST_DESC_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff10 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int ndar : 28; /* next descriptor address */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int : 1; -+ unsigned int sof_eof : 2; -+#else -+ unsigned int sof_eof : 2; -+ unsigned int : 1; -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int ndar : 28; /* next descriptor address */ -+#endif -+ } bits; -+} GMAC_TXDMA_CURR_DESC_T; -+ -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff14 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int rd_start : 1; /* Start DMA transfer */ -+ unsigned int rd_continue : 1; /* Continue DMA operation */ -+ unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int : 1; -+ unsigned int rd_prot : 4; /* DMA protection control */ -+ unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */ -+ unsigned int rd_bus : 2; /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */ -+ unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int : 14; -+#else -+ unsigned int : 14; -+ unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ -+ unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ -+ unsigned int rd_bus : 2; /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */ -+ unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */ -+ unsigned int rd_prot : 4; /* DMA protection control */ -+ unsigned int : 1; -+ unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ -+ unsigned int rd_continue : 1; /* Continue DMA operation */ -+ unsigned int rd_start : 1; /* Start DMA transfer */ -+#endif -+ } bits; -+} GMAC_RXDMA_CTRL_T; -+ -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff18 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int rd_first_des_ptr : 28;/* first descriptor address */ -+ unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */ -+ unsigned int : 3; -+#else -+ unsigned int : 3; -+ unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */ -+ unsigned int rd_first_des_ptr : 28;/* first descriptor address */ -+#endif -+ } bits; -+} GMAC_RXDMA_FIRST_DESC_T; -+ -+typedef union -+{ -+ unsigned int bits32; -+ struct bit2_ff1c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int ndar : 28; /* next descriptor address */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int : 1; -+ unsigned int sof_eof : 2; -+#else -+ unsigned int sof_eof : 2; -+ unsigned int : 1; -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int ndar : 28; /* next descriptor address */ -+#endif -+ } bits; -+} GMAC_RXDMA_CURR_DESC_T; -+ -+ -+/********************************************/ -+/* Descriptor Format */ -+/********************************************/ -+ -+typedef struct descriptor_t -+{ -+ union frame_control_t -+ { -+ unsigned int bits32; -+ struct bits_0000 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int csum_state : 3; /* checksum error status */ -+ unsigned int vlan_tag : 1; /* 802.1q vlan tag packet */ -+ unsigned int frame_state: 3; /* reference Rx Status1 */ -+ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ -+ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ -+#else -+ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ -+ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ -+ unsigned int frame_state: 3; /* reference Rx Status1 */ -+ unsigned int vlan_tag : 1; /* 802.1q vlan tag packet */ -+ unsigned int csum_state : 3; /* checksum error status */ -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ -+#endif -+ } bits_rx; -+ -+ struct bits_0001 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int : 6; -+ unsigned int success_tx : 1; /* successful transmitted */ -+ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ -+ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ -+#else -+ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ -+ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ -+ unsigned int success_tx : 1; /* successful transmitted */ -+ unsigned int : 6; -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ -+#endif -+ } bits_tx_in; -+ -+ struct bits_0002 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int : 2; -+ unsigned int udp_csum_en: 1; /* TSS UDP checksum enable */ -+ unsigned int tcp_csum_en: 1; /* TSS TCP checksum enable */ -+ unsigned int ipv6_tx_en : 1; /* TSS IPv6 TX enable */ -+ unsigned int ip_csum_en : 1; /* TSS IPv4 IP Header checksum enable */ -+ unsigned int vlan_enable: 1; /* VLAN TIC insertion enable */ -+ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ -+ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ -+#else -+ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ -+ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ -+ unsigned int vlan_enable: 1; /* VLAN TIC insertion enable */ -+ unsigned int ip_csum_en : 1; /* TSS IPv4 IP Header checksum enable */ -+ unsigned int ipv6_tx_en : 1; /* TSS IPv6 TX enable */ -+ unsigned int tcp_csum_en: 1; /* TSS TCP checksum enable */ -+ unsigned int udp_csum_en: 1; /* TSS UDP checksum enable */ -+ unsigned int : 2; -+ unsigned int perr : 1; /* protocol error during processing this descriptor */ -+ unsigned int derr : 1; /* data error during processing this descriptor */ -+ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ -+#endif -+ } bits_tx_out; -+ -+ } frame_ctrl; -+ -+ union flag_status_t -+ { -+ unsigned int bits32; -+ struct bits_0004 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int priority : 3; /* user priority extracted from receiving frame*/ -+ unsigned int cfi : 1; /* cfi extracted from receiving frame*/ -+ unsigned int vlan_id :12; /* VLAN ID extracted from receiving frame */ -+ unsigned int frame_count:16; /* received frame byte count,include CRC,not include VLAN TIC */ -+#else -+ unsigned int frame_count:16; /* received frame byte count,include CRC,not include VLAN TIC */ -+ unsigned int vlan_id :12; /* VLAN ID extracted from receiving frame */ -+ unsigned int cfi : 1; /* cfi extracted from receiving frame*/ -+ unsigned int priority : 3; /* user priority extracted from receiving frame*/ -+#endif -+ } bits_rx_status; -+ -+ struct bits_0005 -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int priority : 3; /* user priority to transmit*/ -+ unsigned int cfi : 1; /* cfi to transmit*/ -+ unsigned int vlan_id :12; /* VLAN ID to transmit */ -+ unsigned int frame_count:16; /* total tx frame byte count */ -+#else -+ unsigned int frame_count:16; /* total tx frame byte count */ -+ unsigned int vlan_id :12; /* VLAN ID to transmit */ -+ unsigned int cfi : 1; /* cfi to transmit*/ -+ unsigned int priority : 3; /* user priority to transmit*/ -+#endif -+ } bits_tx_flag; -+ } flag_status; -+ -+ unsigned int buf_adr; /* data buffer address */ -+ -+ union next_desc_t -+ { -+ unsigned int next_descriptor; -+ struct bits_000c -+ { -+#if (BIG_ENDIAN==1) -+ unsigned int ndar :28; /* next descriptor address */ -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int : 1; -+ unsigned int sof_eof : 2; /* 00-the linking descriptor 01-the last descriptor of a frame*/ -+ /* 10-the first descriptor of a frame 11-only one descriptor for a frame*/ -+#else -+ unsigned int sof_eof : 2; /* 00-the linking descriptor 01-the last descriptor of a frame*/ -+ /* 10-the first descriptor of a frame 11-only one descriptor for a frame*/ -+ unsigned int : 1; -+ unsigned int eofie : 1; /* end of frame interrupt enable */ -+ unsigned int ndar :28; /* next descriptor address */ -+#endif -+ } bits; -+ } next_desc; -+} GMAC_DESCRIPTOR_T; -+ -+typedef struct gmac_conf { -+ struct net_device *dev; -+ int portmap; -+ int vid; -+ int flag; /* 1: active 0: non-active */ -+} sys_gmac_conf; -+ -+struct gmac_private { -+ unsigned char *tx_bufs; /* Tx bounce buffer region. */ -+ unsigned char *rx_bufs; -+ GMAC_DESCRIPTOR_T *tx_desc; /* point to virtual TX descriptor address*/ -+ GMAC_DESCRIPTOR_T *rx_desc; /* point to virtual RX descriptor address*/ -+ GMAC_DESCRIPTOR_T *tx_cur_desc; /* point to current TX descriptor */ -+ GMAC_DESCRIPTOR_T *rx_cur_desc; /* point to current RX descriptor */ -+ GMAC_DESCRIPTOR_T *tx_finished_desc; -+ GMAC_DESCRIPTOR_T *rx_finished_desc; -+ unsigned long cur_tx; -+ unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */ -+ unsigned int tx_flag; -+ unsigned long dirty_tx; -+ unsigned char *tx_buf[TX_DESC_NUM]; /* Tx bounce buffers */ -+ dma_addr_t tx_desc_dma; /* physical TX descriptor address */ -+ dma_addr_t rx_desc_dma; /* physical RX descriptor address */ -+ dma_addr_t tx_bufs_dma; /* physical TX descriptor address */ -+ dma_addr_t rx_bufs_dma; /* physical RX descriptor address */ -+ struct net_device_stats stats; -+ pid_t thr_pid; -+ wait_queue_head_t thr_wait; -+ struct completion thr_exited; -+ spinlock_t lock; -+ int time_to_die; -+ unsigned int tx_desc_hdr[GMAC_PHY_IF]; /* the descriptor which sw can fill */ -+ unsigned int tx_desc_tail[GMAC_PHY_IF]; /* the descriptor which is not cleaned yet */ -+}; -+ -+ -+struct reg_ioctl_data { -+ unsigned int reg_addr; /* the register address */ -+ unsigned int val_in; /* data write to the register */ -+ unsigned int val_out; /* data read from the register */ -+}; -+ -+#ifdef CONFIG_SL2312_MPAGE -+typedef struct tx_data_t { -+ int freeable; // 1 when it's skb. it can be freed in tx interrupt handler -+ struct sk_buff* skb; // skb -+ int desc_in_use; // 1 when the desc is in use. 0 when desc is available. -+ long end_seq; // to find out packets are in seq. -+ // so this value is the seq of next packet. -+} tx_data; -+#endif -+ -+/************************************************************* -+ * Global Variable -+ *************************************************************/ -+struct semaphore sem_gmac; /* semaphore for share pins issue */ -+ -+/************************************************************* -+ * Static Global Variable -+ *************************************************************/ -+// static unsigned int MAC_BASE_ADDR = GMAC0_BASE; -+static unsigned int gmac_base_addr[GMAC_PHY_IF] = {GMAC0_BASE,GMAC1_BASE}; -+static unsigned int gmac_irq[GMAC_PHY_IF] = {IRQ_GMAC0,IRQ_GMAC1}; -+static struct net_device *gmac_dev[GMAC_PHY_IF]; -+ -+static unsigned int FLAG_SWITCH=0; /* if 1-->switch chip presented. if 0-->switch chip unpresented */ -+static unsigned int flow_control_enable[GMAC_PHY_IF] = {1,1}; -+static unsigned int pre_phy_status[GMAC_PHY_IF] = {LINK_DOWN,LINK_DOWN}; -+static unsigned int tx_desc_virtual_base[GMAC_PHY_IF]; -+static unsigned int rx_desc_virtual_base[GMAC_PHY_IF]; -+static unsigned int full_duplex = 1; -+static unsigned int speed = 1; -+#ifdef CONFIG_SL2312_MPAGE -+static tx_data tx_skb[GMAC_PHY_IF][TX_DESC_NUM]; -+#else -+static struct sk_buff *tx_skb[GMAC_PHY_IF][TX_DESC_NUM]; -+#endif -+static struct sk_buff *rx_skb[GMAC_PHY_IF][RX_DESC_NUM]; -+static unsigned int tx_desc_start_adr[GMAC_PHY_IF]; -+static unsigned int rx_desc_start_adr[GMAC_PHY_IF]; -+static unsigned char eth0_mac[6]= {0x00,0x50,0xc2,0x2b,0xd3,0x25}; -+static unsigned char eth1_mac[6]= {0x00,0x50,0xc2,0x2b,0xdf,0xfe}; -+static unsigned int next_tick = 3 * HZ; -+ -+static unsigned int phy_addr[GMAC_PHY_IF] = {0x01,0x02}; /* define PHY address */ -+ -+DECLARE_WAIT_QUEUE_HEAD(gmac_queue); -+//static wait_queue_t wait; -+ -+struct gmac_conf VLAN_conf[] = { -+#ifdef CONFIG_ADM_6999 -+ { (struct net_device *)0,0x7F,1 }, -+ { (struct net_device *)0,0x80,2 } -+#endif -+#ifdef CONFIG_ADM_6996 -+ { (struct net_device *)0,0x0F,1 }, -+ { (struct net_device *)0,0x10,2 } -+#endif -+}; -+ -+#define NUM_VLAN_IF (sizeof(VLAN_conf)/sizeof(struct gmac_conf)) -+ -+ -+/************************************************/ -+/* GMAC function declare */ -+/************************************************/ -+ -+unsigned int mii_read(unsigned char phyad,unsigned char regad); -+void mii_write(unsigned char phyad,unsigned char regad,unsigned int value); -+static void gmac_set_phy_status(struct net_device *dev); -+static void gmac_get_phy_status(struct net_device *dev); -+static int gmac_phy_thread (void *data); -+static int gmac_set_mac_address(struct net_device *dev, void *addr); -+static void gmac_tx_timeout(struct net_device *dev); -+static void gmac_tx_packet_complete(struct net_device *dev); -+static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev); -+static void gmac_set_rx_mode(struct net_device *dev); -+static void gmac_rx_packet(struct net_device *dev); -+static int gmac_open (struct net_device *dev); -+static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); -+ -+static unsigned int gmac_get_dev_index(struct net_device *dev); -+static unsigned int gmac_select_interface(struct net_device *dev); -+ -+#ifdef CONFIG_SL2312_MPAGE -+int printk_all(int dev_index, struct gmac_private* tp); -+#endif -+ -+/****************************************/ -+/* SPI Function Declare */ -+/****************************************/ -+void SPI_write(unsigned char addr,unsigned int value); -+unsigned int SPI_read(unsigned char table,unsigned char addr); -+void SPI_write_bit(char bit_EEDO); -+unsigned int SPI_read_bit(void); -+void SPI_default(void); -+void SPI_reset(unsigned char rstype,unsigned char port_cnt); -+void SPI_pre_st(void); -+void SPI_CS_enable(unsigned char enable); -+void SPI_Set_VLAN(unsigned char LAN,unsigned int port_mask); -+void SPI_Set_tag(unsigned int port,unsigned tag); -+void SPI_Set_PVID(unsigned int PVID,unsigned int port_mask); -+unsigned int SPI_Get_PVID(unsigned int port); -+void SPI_mac_lock(unsigned int port, unsigned char lock); -+void SPI_get_port_state(unsigned int port); -+void SPI_port_enable(unsigned int port,unsigned char enable); -+unsigned int SPI_get_identifier(void); -+void SPI_get_status(unsigned int port); -+ -+/****************************************/ -+/* VLAN Function Declare */ -+/****************************************/ -+int getVLANfromdev (struct net_device *dev ); -+struct net_device * getdevfromVLAN( int VID); -+ -+ -+ -+/************************************************/ -+/* function body */ -+/************************************************/ -+#if 0 -+void hw_memcpy(void *to,const void *from,unsigned long n) -+{ -+ writel(from,SL2312_DRAM_CTRL_BASE+0x20); /* set source address */ -+ writel(to,SL2312_DRAM_CTRL_BASE+0x24); /* set destination address */ -+ writel(n,SL2312_DRAM_CTRL_BASE+0x28); /* set byte count */ -+ writel(0x00000001,SL2312_DRAM_CTRL_BASE+0x2c); -+ while (readl(SL2312_DRAM_CTRL_BASE+0x2c)); -+} -+#endif -+ -+static unsigned int gmac_read_reg(unsigned int addr) -+{ -+ unsigned int reg_val; -+// unsigned int flags; -+// spinlock_t lock; -+ -+// spin_lock_irqsave(&lock, flags); -+ reg_val = readl(addr); // Gary Chen -+// spin_unlock_irqrestore(&lock, flags); -+ return (reg_val); -+} -+ -+static void gmac_write_reg(unsigned int addr,unsigned int data,unsigned int bit_mask) -+{ -+ unsigned int reg_val; -+ //unsigned int *addr; -+// unsigned int flags; -+// spinlock_t lock; -+ -+// spin_lock_irqsave(&lock, flags); -+ reg_val = ( gmac_read_reg(addr) & (~bit_mask) ) | (data & bit_mask); -+ writel(reg_val,addr); -+// spin_unlock_irqrestore(&lock, flags); -+ return; -+} -+ -+ -+static void gmac_sw_reset(struct net_device *dev) -+{ -+ unsigned int index; -+ unsigned int reg_val; -+ -+ index = gmac_get_dev_index(dev); -+ if (index==0) -+ reg_val = readl(GMAC_GLOBAL_BASE_ADDR+0x0c) | 0x00000020; /* GMAC0 S/W reset */ -+ else -+ reg_val = readl(GMAC_GLOBAL_BASE_ADDR+0x0c) | 0x00000040; /* GMAC1 S/W reset */ -+ -+ writel(reg_val,GMAC_GLOBAL_BASE_ADDR+0x0c); -+ return; -+} -+ -+static void gmac_get_mac_address(void) -+{ -+#ifdef CONFIG_MTD -+ extern int get_vlaninfo(vlaninfo* vlan); -+ static vlaninfo vlan[2]; -+ -+ if (get_vlaninfo(&vlan[0])) -+ { -+ memcpy(eth0_mac,vlan[0].mac,6); -+ VLAN_conf[0].vid = vlan[0].vlanid; -+ VLAN_conf[0].portmap = vlan[0].vlanmap; -+ memcpy(eth1_mac,vlan[1].mac,6); -+ VLAN_conf[1].vid = vlan[1].vlanid; -+ VLAN_conf[1].portmap = vlan[1].vlanmap; -+ } -+#else -+ unsigned int reg_val; -+ -+ reg_val = readl(IO_ADDRESS(SL2312_SECURITY_BASE)+0xac); -+ eth0_mac[4] = (reg_val & 0xff00) >> 8; -+ eth0_mac[5] = reg_val & 0x00ff; -+ reg_val = readl(IO_ADDRESS(SL2312_SECURITY_BASE)+0xac); -+ eth1_mac[4] = (reg_val & 0xff00) >> 8; -+ eth1_mac[5] = reg_val & 0x00ff; -+#endif -+ return; -+} -+ -+static unsigned int gmac_get_dev_index(struct net_device *dev) -+{ -+ unsigned int i; -+ -+ /* get device index number */ -+ for (i=0;iMII 1->GMII 2->RGMII(10/100) 3->RGMII(1000) */ -+ else -+ phy_mode = 2; /* 0->MII 1->GMII 2->RGMII(10/100) 3->RGMII(1000) */ -+ -+ /* set PHY operation mode */ -+ status = (phy_mode<<5) | 0x11 | (full_duplex<<3) | (speed<<1); -+ gmac_write_reg(gmac_base_addr[index] + GMAC_STATUS,status ,0x0000007f); -+ -+ /* set station MAC address1 and address2 */ -+ if (index==0) -+ memcpy(&sock.sa_data[0],ð0_mac[0],6); -+ else -+ memcpy(&sock.sa_data[0],ð1_mac[0],6); -+ gmac_set_mac_address(dev,(void *)&sock); -+ -+ /* set RX_FLTR register to receive all multicast packet */ -+ gmac_write_reg(gmac_base_addr[index] + GMAC_RX_FLTR,0x0000001F,0x0000001f); -+ //gmac_write_reg(gmac_base_addr[index] + GMAC_RX_FLTR,0x00000007,0x0000001f); -+ -+ /* set per packet buffer size */ -+ config1.bits32 = 0; -+ config1.bits.buf_size = 11; /* buffer size = 2048-byte */ -+ gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG1,config1.bits32,0x0000000f); -+ -+ /* set flow control threshold */ -+ config2_val.bits32 = 0; -+ config2_val.bits.set_threshold = RX_DESC_NUM/4; -+ config2_val.bits.rel_threshold = RX_DESC_NUM*3/4; -+ gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG2,config2_val.bits32,0xffffffff); -+ -+ /* init remaining buffer number register */ -+ rbnr_val.bits32 = 0; -+ rbnr_val.bits.buf_remain = RX_DESC_NUM; -+ rbnr_mask.bits32 = 0; -+ rbnr_mask.bits.buf_remain = 0xffff; -+ gmac_write_reg(gmac_base_addr[index] + GMAC_RBNR,rbnr_val.bits32,rbnr_mask.bits32); -+ -+ /* disable TX/RX and disable internal loop back */ -+ config0.bits32 = 0; -+ config0_mask.bits32 = 0; -+ config0.bits.max_len = 2; -+ if (flow_control_enable[index]==1) -+ { -+ config0.bits.tx_fc_en = 1; /* enable tx flow control */ -+ config0.bits.rx_fc_en = 1; /* enable rx flow control */ -+ printk("Enable MAC Flow Control...\n"); -+ } -+ else -+ { -+ config0.bits.tx_fc_en = 0; /* disable tx flow control */ -+ config0.bits.rx_fc_en = 0; /* disable rx flow control */ -+ printk("Disable MAC Flow Control...\n"); -+ } -+ config0.bits.dis_rx = 1; /* disable rx */ -+ config0.bits.dis_tx = 1; /* disable tx */ -+ config0.bits.loop_back = 0; /* enable/disable GMAC loopback */ -+ config0.bits.inv_rx_clk = 0; -+ config0.bits.rising_latch = 1; -+ config0.bits.ipv4_tss_rx_en = 1; /* enable H/W to check ip checksum */ -+ config0.bits.ipv6_tss_rx_en = 1; /* enable H/W to check ip checksum */ -+ -+ config0_mask.bits.max_len = 7; -+ config0_mask.bits.tx_fc_en = 1; -+ config0_mask.bits.rx_fc_en = 1; -+ config0_mask.bits.dis_rx = 1; -+ config0_mask.bits.dis_tx = 1; -+ config0_mask.bits.loop_back = 1; -+ config0_mask.bits.inv_rx_clk = 1; -+ config0_mask.bits.rising_latch = 1; -+ config0_mask.bits.ipv4_tss_rx_en = 1; -+ config0_mask.bits.ipv6_tss_rx_en = 1; -+ gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32); -+ -+ return (0); -+} -+ -+static void gmac_enable_tx_rx(struct net_device *dev) -+{ -+ GMAC_CONFIG0_T config0,config0_mask; -+ int dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ /* enable TX/RX */ -+ config0.bits32 = 0; -+ config0_mask.bits32 = 0; -+ config0.bits.dis_rx = 0; /* enable rx */ -+ config0.bits.dis_tx = 0; /* enable tx */ -+ config0_mask.bits.dis_rx = 1; -+ config0_mask.bits.dis_tx = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32); -+} -+ -+static void gmac_disable_tx_rx(struct net_device *dev) -+{ -+ GMAC_CONFIG0_T config0,config0_mask; -+ int dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ /* enable TX/RX */ -+ config0.bits32 = 0; -+ config0_mask.bits32 = 0; -+ config0.bits.dis_rx = 1; /* disable rx */ -+ config0.bits.dis_tx = 1; /* disable tx */ -+ config0_mask.bits.dis_rx = 1; -+ config0_mask.bits.dis_tx = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32); -+} -+ -+#ifdef CONFIG_SL_NAPI -+static int gmac_rx_poll_ga(struct net_device *dev, int *budget) -+{ -+ struct gmac_private *tp = dev->priv; -+ struct sk_buff *skb; -+ GMAC_RXDMA_CTRL_T rxdma_ctrl,rxdma_ctrl_mask; -+ GMAC_RXDMA_FIRST_DESC_T rxdma_busy; -+ GMAC_DESCRIPTOR_T *rx_desc; -+ unsigned int pkt_size; -+ unsigned int desc_count; -+ unsigned int vid; -+// unsigned int priority; -+ unsigned int own; -+ unsigned int good_frame = 0; -+ unsigned int index; -+ unsigned int dev_index; -+ int work = 0; -+ int work_done = 0; -+ int quota = min(dev->quota, *budget); -+ -+ dev_index = gmac_select_interface(dev); -+ -+ for (;;) -+ { -+ own = tp->rx_cur_desc->frame_ctrl.bits32 >> 31; -+ if (own == CPU) /* check owner bit */ -+ { -+ rx_desc = tp->rx_cur_desc; -+#if (GMAC_DEBUG==1) -+ /* check error interrupt */ -+ if ( (rx_desc->frame_ctrl.bits_rx.derr==1)||(rx_desc->frame_ctrl.bits_rx.perr==1) ) -+ { -+ printk("%s::Rx Descriptor Processing Error !!!\n",__func__); -+ } -+#endif -+ /* get frame information from the first descriptor of the frame */ -+ pkt_size = rx_desc->flag_status.bits_rx_status.frame_count - 4; /*total byte count in a frame*/ -+#if (GMAC_DEBUG==1) -+ priority = rx_desc->flag_status.bits_rx_status.priority; /* 802.1p priority */ -+#endif -+ vid = rx_desc->flag_status.bits_rx_status.vlan_id; /* 802.1q vlan id */ -+ if (vid == 0) -+ { -+ vid = 1; /* default vlan */ -+ } -+ desc_count = rx_desc->frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */ -+ -+ if (rx_desc->frame_ctrl.bits_rx.frame_state == 0x000) /* good frame */ -+ { -+ tp->stats.rx_bytes += pkt_size; -+ tp->stats.rx_packets++; -+ good_frame = 1; -+ } -+ else -+ { -+ tp->stats.rx_errors++; -+ good_frame = 0; -+ printk("RX status: 0x%x\n",rx_desc->frame_ctrl.bits_rx.frame_state); -+ } -+ } -+ else -+ { -+ work_done = 1; -+ break; /* Rx process is completed */ -+ } -+ -+ if (good_frame == 1) -+ { -+ /* get rx skb buffer index */ -+ index = ((unsigned int)tp->rx_cur_desc - rx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ if (rx_skb[dev_index][index]) -+ { -+ skb_reserve (rx_skb[dev_index][index], 2); /* 16 byte align the IP fields. */ -+ rx_skb[dev_index][index]->dev = dev; -+ rx_skb[dev_index][index]->ip_summed = CHECKSUM_UNNECESSARY; -+ skb_put(rx_skb[dev_index][index],pkt_size); -+ rx_skb[dev_index][index]->protocol = eth_type_trans(rx_skb[dev_index][index],dev); /* set skb protocol */ -+ netif_rx(rx_skb[dev_index][index]); /* socket rx */ -+ dev->last_rx = jiffies; -+ -+ /* allocate rx skb buffer */ -+ if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL) /* allocate socket buffer */ -+ { -+ printk("%s::skb buffer allocation fail !\n",__func__); -+ } -+ rx_skb[dev_index][index] = skb; -+ tp->rx_cur_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02; /* insert two bytes in the beginning of rx data */ -+ } -+ else -+ { -+ printk("%s::rx skb index error !\n",__func__); -+ } -+ } -+ -+ tp->rx_cur_desc->frame_ctrl.bits_rx.own = DMA; /* release rx descriptor to DMA */ -+ /* point to next rx descriptor */ -+ tp->rx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->rx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+rx_desc_virtual_base[dev_index]); -+ -+ /* release buffer to Remaining Buffer Number Register */ -+ if (flow_control_enable[dev_index] ==1) -+ { -+// gmac_write_reg(gmac_base_addr[dev_index] + GMAC_BNCR,desc_count,0x0000ffff); -+ writel(desc_count,(unsigned int *)(gmac_base_addr[dev_index] + GMAC_BNCR)); -+ } -+ -+ if (work++ >= quota ) -+ { -+ break; -+ } -+ } -+ -+ /* if RX DMA process is stoped , restart it */ -+ rxdma_busy.bits.rd_first_des_ptr = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC); -+ if (rxdma_busy.bits.rd_busy == 0) -+ { -+ rxdma_ctrl.bits32 = 0; -+ rxdma_ctrl.bits.rd_start = 1; /* start RX DMA transfer */ -+ rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */ -+ rxdma_ctrl_mask.bits32 = 0; -+ rxdma_ctrl_mask.bits.rd_start = 1; -+ rxdma_ctrl_mask.bits.rd_continue = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32); -+ } -+ -+ dev->quota -= work; -+ *budget -= work; -+ if (work_done==1) -+ { -+ /* Receive descriptor is empty now */ -+ netif_rx_complete(dev); -+ /* enable receive interrupt */ -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,0x0007c000,0x0007c000); /* enable rx interrupt */ -+ return 0; -+ } -+ else -+ { -+ return -1; -+ } -+} -+ -+static int gmac_rx_poll_gb(struct net_device *dev, int *budget) -+{ -+ struct gmac_private *tp = dev->priv; -+ struct sk_buff *skb; -+ GMAC_RXDMA_CTRL_T rxdma_ctrl,rxdma_ctrl_mask; -+ GMAC_RXDMA_FIRST_DESC_T rxdma_busy; -+ GMAC_DESCRIPTOR_T *rx_desc; -+ unsigned int pkt_size; -+ unsigned int desc_count; -+ unsigned int vid; -+// unsigned int priority; -+ unsigned int own; -+ unsigned int good_frame = 0; -+ unsigned int index; -+ unsigned int dev_index; -+ int work = 0; -+ int work_done = 0; -+ int quota = min(dev->quota, *budget); -+ -+ dev_index = gmac_select_interface(dev); -+ -+ for (;;) -+ { -+ own = tp->rx_cur_desc->frame_ctrl.bits32 >> 31; -+ if (own == CPU) /* check owner bit */ -+ { -+ rx_desc = tp->rx_cur_desc; -+#if (GMAC_DEBUG==1) -+ /* check error interrupt */ -+ if ( (rx_desc->frame_ctrl.bits_rx.derr==1)||(rx_desc->frame_ctrl.bits_rx.perr==1) ) -+ { -+ printk("%s::Rx Descriptor Processing Error !!!\n",__func__); -+ } -+#endif -+ /* get frame information from the first descriptor of the frame */ -+ pkt_size = rx_desc->flag_status.bits_rx_status.frame_count - 4; /*total byte count in a frame*/ -+#if (GMAC_DEBUG==1) -+ priority = rx_desc->flag_status.bits_rx_status.priority; /* 802.1p priority */ -+#endif -+ vid = rx_desc->flag_status.bits_rx_status.vlan_id; /* 802.1q vlan id */ -+ if (vid == 0) -+ { -+ vid = 1; /* default vlan */ -+ } -+ desc_count = rx_desc->frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */ -+ -+ if (rx_desc->frame_ctrl.bits_rx.frame_state == 0x000) /* good frame */ -+ { -+ tp->stats.rx_bytes += pkt_size; -+ tp->stats.rx_packets++; -+ good_frame = 1; -+ } -+ else -+ { -+ tp->stats.rx_errors++; -+ good_frame = 0; -+ printk("RX status: 0x%x\n",rx_desc->frame_ctrl.bits_rx.frame_state); -+ } -+ } -+ else -+ { -+ work_done = 1; -+ break; /* Rx process is completed */ -+ } -+ -+ if (good_frame == 1) -+ { -+ /* get rx skb buffer index */ -+ index = ((unsigned int)tp->rx_cur_desc - rx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ if (rx_skb[dev_index][index]) -+ { -+ skb_reserve (rx_skb[dev_index][index], 2); /* 16 byte align the IP fields. */ -+ rx_skb[dev_index][index]->dev = dev; -+ rx_skb[dev_index][index]->ip_summed = CHECKSUM_UNNECESSARY; -+ skb_put(rx_skb[dev_index][index],pkt_size); -+ rx_skb[dev_index][index]->protocol = eth_type_trans(rx_skb[dev_index][index],dev); /* set skb protocol */ -+ netif_rx(rx_skb[dev_index][index]); /* socket rx */ -+ dev->last_rx = jiffies; -+ -+ /* allocate rx skb buffer */ -+ if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL) /* allocate socket buffer */ -+ { -+ printk("%s::skb buffer allocation fail !\n",__func__); -+ } -+ rx_skb[dev_index][index] = skb; -+ tp->rx_cur_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02; /* insert two bytes in the beginning of rx data */ -+ } -+ else -+ { -+ printk("%s::rx skb index error !\n",__func__); -+ } -+ } -+ -+ tp->rx_cur_desc->frame_ctrl.bits_rx.own = DMA; /* release rx descriptor to DMA */ -+ /* point to next rx descriptor */ -+ tp->rx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->rx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+rx_desc_virtual_base[dev_index]); -+ -+ /* release buffer to Remaining Buffer Number Register */ -+ if (flow_control_enable[dev_index] ==1) -+ { -+// gmac_write_reg(gmac_base_addr[dev_index] + GMAC_BNCR,desc_count,0x0000ffff); -+ writel(desc_count,(unsigned int *)(gmac_base_addr[dev_index] + GMAC_BNCR)); -+ } -+ -+ if (work++ >= quota ) -+ { -+ break; -+ } -+ } -+ -+ /* if RX DMA process is stoped , restart it */ -+ rxdma_busy.bits.rd_first_des_ptr = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC); -+ if (rxdma_busy.bits.rd_busy == 0) -+ { -+ rxdma_ctrl.bits32 = 0; -+ rxdma_ctrl.bits.rd_start = 1; /* start RX DMA transfer */ -+ rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */ -+ rxdma_ctrl_mask.bits32 = 0; -+ rxdma_ctrl_mask.bits.rd_start = 1; -+ rxdma_ctrl_mask.bits.rd_continue = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32); -+ } -+ -+ dev->quota -= work; -+ *budget -= work; -+ if (work_done==1) -+ { -+ /* Receive descriptor is empty now */ -+ netif_rx_complete(dev); -+ /* enable receive interrupt */ -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,0x0007c000,0x0007c000); /* enable rx interrupt */ -+ return 0; -+ } -+ else -+ { -+ return -1; -+ } -+} -+ -+#endif -+ -+static void gmac_rx_packet(struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ struct sk_buff *skb; -+ GMAC_RXDMA_CTRL_T rxdma_ctrl,rxdma_ctrl_mask; -+ GMAC_RXDMA_FIRST_DESC_T rxdma_busy; -+ GMAC_DESCRIPTOR_T *rx_desc; -+ unsigned int pkt_size; -+ unsigned int desc_count; -+ unsigned int vid; -+// unsigned int priority; -+ unsigned int own; -+ unsigned int good_frame = 0; -+ unsigned int i,index; -+ unsigned int dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ for (i=0;i<256;i++) -+ { -+ own = tp->rx_cur_desc->frame_ctrl.bits32 >> 31; -+ if (own == CPU) /* check owner bit */ -+ { -+ rx_desc = tp->rx_cur_desc; -+#if (GMAC_DEBUG==1) -+ /* check error interrupt */ -+ if ( (rx_desc->frame_ctrl.bits_rx.derr==1)||(rx_desc->frame_ctrl.bits_rx.perr==1) ) -+ { -+ printk("%s::Rx Descriptor Processing Error !!!\n",__func__); -+ } -+#endif -+ /* get frame information from the first descriptor of the frame */ -+ pkt_size = rx_desc->flag_status.bits_rx_status.frame_count - 4; /*total byte count in a frame*/ -+#if (GMAC_DEBUG==1) -+ priority = rx_desc->flag_status.bits_rx_status.priority; /* 802.1p priority */ -+#endif -+ vid = rx_desc->flag_status.bits_rx_status.vlan_id; /* 802.1q vlan id */ -+ if (vid == 0) -+ { -+ vid = 1; /* default vlan */ -+ } -+ desc_count = rx_desc->frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */ -+ -+ if (rx_desc->frame_ctrl.bits_rx.frame_state == 0x000) /* good frame */ -+ { -+ tp->stats.rx_bytes += pkt_size; -+ tp->stats.rx_packets++; -+ good_frame = 1; -+ } -+ else -+ { -+ tp->stats.rx_errors++; -+ good_frame = 0; -+ printk("RX status: 0x%x\n",rx_desc->frame_ctrl.bits_rx.frame_state); -+ } -+ } -+ else -+ { -+ break; /* Rx process is completed */ -+ } -+ -+ if (good_frame == 1) -+ { -+ /* get rx skb buffer index */ -+ index = ((unsigned int)tp->rx_cur_desc - rx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ if (rx_skb[dev_index][index]) -+ { -+ skb_reserve (rx_skb[dev_index][index], 2); /* 16 byte align the IP fields. */ -+ rx_skb[dev_index][index]->dev = dev; -+ rx_skb[dev_index][index]->ip_summed = CHECKSUM_UNNECESSARY; -+ skb_put(rx_skb[dev_index][index],pkt_size); -+ rx_skb[dev_index][index]->protocol = eth_type_trans(rx_skb[dev_index][index],dev); /* set skb protocol */ -+ netif_rx(rx_skb[dev_index][index]); /* socket rx */ -+ dev->last_rx = jiffies; -+ -+ /* allocate rx skb buffer */ -+ if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL) /* allocate socket buffer */ -+ { -+ printk("%s::skb buffer allocation fail !\n",__func__); -+ } -+ rx_skb[dev_index][index] = skb; -+ tp->rx_cur_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02; /* insert two bytes in the beginning of rx data */ -+ } -+ else -+ { -+ printk("%s::rx skb index error !\n",__func__); -+ } -+ } -+ -+ tp->rx_cur_desc->frame_ctrl.bits_rx.own = DMA; /* release rx descriptor to DMA */ -+ /* point to next rx descriptor */ -+ tp->rx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->rx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+rx_desc_virtual_base[dev_index]); -+ -+ /* release buffer to Remaining Buffer Number Register */ -+ if (flow_control_enable[dev_index] ==1) -+ { -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_BNCR,desc_count,0x0000ffff); -+ } -+ } -+ -+ /* if RX DMA process is stoped , restart it */ -+ rxdma_busy.bits.rd_first_des_ptr = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC); -+ if (rxdma_busy.bits.rd_busy == 0) -+ { -+ rxdma_ctrl.bits32 = 0; -+ rxdma_ctrl.bits.rd_start = 1; /* start RX DMA transfer */ -+ rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */ -+ rxdma_ctrl_mask.bits32 = 0; -+ rxdma_ctrl_mask.bits.rd_start = 1; -+ rxdma_ctrl_mask.bits.rd_continue = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32); -+ } -+} -+ -+#ifdef CONFIG_SL2312_MPAGE -+static inline void free_tx_buf(int dev_index, int desc_index) -+{ -+ if (tx_skb[dev_index][desc_index].freeable && -+ tx_skb[dev_index][desc_index].skb) { -+ struct sk_buff* skb = tx_skb[dev_index][desc_index].skb; -+ //printk("free_skb %x, len %d\n", skb, skb->len); -+#ifdef CONFIG_TXINT_DISABLE -+ dev_kfree_skb(skb); -+#else -+ dev_kfree_skb_irq(skb); -+#endif -+ tx_skb[dev_index][desc_index].skb = 0; -+ } -+} -+ -+#ifdef CONFIG_TXINT_DISABLE -+static void gmac_tx_packet_complete(struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ GMAC_DESCRIPTOR_T *tx_hw_complete_desc, *next_desc; -+ unsigned int desc_cnt=0; -+ unsigned int i,index,dev_index; -+ unsigned int tx_current_descriptor = 0; -+ // int own_dma = 0; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ if (tx_skb[dev_index][index].desc_in_use && tp->tx_finished_desc->frame_ctrl.bits_tx_in.own == CPU) { -+ free_tx_buf(dev_index, index); -+ tx_skb[dev_index][index].desc_in_use = 0; -+ } -+ next_desc = (GMAC_DESCRIPTOR_T*)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]); -+ -+ for (;;) { -+ tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0)+ tx_desc_virtual_base[dev_index]); -+ if (next_desc == tx_hw_complete_desc) -+ break; -+ if (next_desc->frame_ctrl.bits_tx_in.own == CPU) { -+ if (next_desc->frame_ctrl.bits_tx_in.success_tx == 1) { -+ tp->stats.tx_bytes += next_desc->flag_status.bits_tx_flag.frame_count; -+ tp->stats.tx_packets ++; -+ } else { -+ tp->stats.tx_errors++; -+ } -+ desc_cnt = next_desc->frame_ctrl.bits_tx_in.desc_count; -+ for (i=1; iframe_ctrl.bits_tx_in.own = CPU; -+ free_tx_buf(dev_index, index); -+ tx_skb[dev_index][index].desc_in_use = 0; -+ tp->tx_desc_tail[dev_index] = (tp->tx_desc_tail[dev_index] +1) & (TX_DESC_NUM-1); -+ /* release Tx descriptor to CPU */ -+ next_desc = (GMAC_DESCRIPTOR_T *)((next_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]); -+ } -+ /* get tx skb buffer index */ -+ index = ((unsigned int)next_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ /* free skb buffer */ -+ next_desc->frame_ctrl.bits_tx_in.own = CPU; -+ free_tx_buf(dev_index, index); -+ tx_skb[dev_index][index].desc_in_use = 0; -+ tp->tx_desc_tail[dev_index] = (tp->tx_desc_tail[dev_index] +1) & (TX_DESC_NUM-1); -+ tp->tx_finished_desc = next_desc; -+// printk("finish tx_desc index %d\n", index); -+ next_desc = (GMAC_DESCRIPTOR_T *)((next_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]); -+ } -+ else -+ break; -+ } -+ if (netif_queue_stopped(dev)) -+ { -+ netif_wake_queue(dev); -+ } -+ -+} -+#else -+static void gmac_tx_packet_complete(struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ GMAC_DESCRIPTOR_T *tx_hw_complete_desc; -+ unsigned int desc_cnt=0; -+ unsigned int i,index,dev_index; -+ unsigned int tx_current_descriptor = 0; -+ // int own_dma = 0; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ -+ /* check tx status and accumulate tx statistics */ -+ for (;;) -+ { -+ -+ for (i=0;i<1000;i++) -+ { -+ tx_current_descriptor = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC); -+ if ( ((tx_current_descriptor & 0x00000003)==0x00000003) || /* only one descriptor */ -+ ((tx_current_descriptor & 0x00000003)==0x00000001) ) /* the last descriptor */ -+ { -+ break; -+ } -+ udelay(1); -+ } -+ if (i==1000) -+ { -+// gmac_dump_register(dev); -+// printk("%s: tx current descriptor = %x \n",__func__,tx_current_descriptor); -+// printk_all(dev_index, tp); -+ continue; -+ } -+ -+ /* get tx H/W completed descriptor virtual address */ -+ tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((tx_current_descriptor & 0xfffffff0)+ tx_desc_virtual_base[dev_index]); -+// tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0)+ tx_desc_virtual_base[dev_index]); -+ if (tp->tx_finished_desc == tx_hw_complete_desc ) // || -+ //tx_skb[dev_index][index].desc_in_use ) /* complete tx processing */ -+ { -+ break; -+ } -+ -+ for (;;) -+ { -+ if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.own == CPU) -+ { -+ #if (GMAC_DEBUG==1) -+ if ( (tp->tx_finished_desc->frame_ctrl.bits_tx_in.derr) || -+ (tp->tx_finished_desc->frame_ctrl.bits_tx_in.perr) ) -+ { -+ printk("%s::Descriptor Processing Error !!!\n",__func__); -+ } -+ #endif -+ if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.success_tx == 1) -+ { -+ tp->stats.tx_bytes += tp->tx_finished_desc->flag_status.bits_tx_flag.frame_count; -+ tp->stats.tx_packets ++; -+ } -+ else -+ { -+ tp->stats.tx_errors++; -+ } -+ desc_cnt = tp->tx_finished_desc->frame_ctrl.bits_tx_in.desc_count; -+ for (i=1; itx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ tp->tx_finished_desc->frame_ctrl.bits_tx_in.own = CPU; -+ free_tx_buf(dev_index, index); -+ tx_skb[dev_index][index].desc_in_use = 0; -+ /* release Tx descriptor to CPU */ -+ tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]); -+ } -+ /* get tx skb buffer index */ -+ index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ /* free skb buffer */ -+ tp->tx_finished_desc->frame_ctrl.bits_tx_in.own = CPU; -+ free_tx_buf(dev_index, index); -+ tx_skb[dev_index][index].desc_in_use = 0; -+ tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]); -+ -+ if (tp->tx_finished_desc == tx_hw_complete_desc ) -+ { -+ break; -+ } -+ } -+ else -+ { -+ break; -+ } -+ } -+ } -+ -+ if (netif_queue_stopped(dev)) -+ { -+ netif_wake_queue(dev); -+ } -+ -+} -+#endif -+#else -+ -+static void gmac_tx_packet_complete(struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ GMAC_DESCRIPTOR_T *tx_hw_complete_desc; -+ unsigned int desc_cnt=0; -+ unsigned int i,index,dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ /* get tx H/W completed descriptor virtual address */ -+ tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0)+ tx_desc_virtual_base[dev_index]); -+ /* check tx status and accumulate tx statistics */ -+ for (;;) -+ { -+ if (tp->tx_finished_desc == tx_hw_complete_desc) /* complete tx processing */ -+ { -+ break; -+ } -+ if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.own == CPU) -+ { -+#if (GMAC_DEBUG==1) -+ if ( (tp->tx_finished_desc->frame_ctrl.bits_tx_in.derr) || -+ (tp->tx_finished_desc->frame_ctrl.bits_tx_in.perr) ) -+ { -+ printk("%s::Descriptor Processing Error !!!\n",__func__); -+ } -+#endif -+ if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.success_tx == 1) -+ { -+ tp->stats.tx_bytes += tp->tx_finished_desc->flag_status.bits_tx_flag.frame_count; -+ tp->stats.tx_packets ++; -+ } -+ else -+ { -+ tp->stats.tx_errors++; -+ } -+ desc_cnt = tp->tx_finished_desc->frame_ctrl.bits_tx_in.desc_count; -+ for (i=1; itx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ /* free skb buffer */ -+ if (tx_skb[dev_index][index]) -+ { -+ dev_kfree_skb_irq(tx_skb[dev_index][index]); -+ } -+ /* release Tx descriptor to CPU */ -+ tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]); -+ tp->tx_finished_desc->frame_ctrl.bits_tx_in.own = CPU; -+ } -+ /* get tx skb buffer index */ -+ index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ /* free skb buffer */ -+ if (tx_skb[dev_index][index]) -+ { -+ dev_kfree_skb_irq(tx_skb[dev_index][index]); -+ } -+ tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]); -+ } -+ } -+ -+ if (netif_queue_stopped(dev)) -+ { -+ netif_wake_queue(dev); -+ } -+ -+} -+ -+ -+#endif -+ -+#if 0 -+static void gmac_weird_interrupt(struct net_device *dev) -+{ -+ gmac_dump_register(dev); -+} -+#endif -+ -+/* The interrupt handler does all of the Rx thread work and cleans up -+ after the Tx thread. */ -+static irqreturn_t gmac_interrupt (int irq, void *dev_instance, struct pt_regs *regs) -+{ -+ struct net_device *dev = (struct net_device *)dev_instance; -+ GMAC_RXDMA_FIRST_DESC_T rxdma_busy; -+// GMAC_TXDMA_FIRST_DESC_T txdma_busy; -+// GMAC_TXDMA_CTRL_T txdma_ctrl,txdma_ctrl_mask; -+ GMAC_RXDMA_CTRL_T rxdma_ctrl,rxdma_ctrl_mask; -+ GMAC_DMA_STATUS_T status; -+ unsigned int i,dev_index; -+ int handled = 0; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ handled = 1; -+ -+#ifdef CONFIG_SL_NAPI -+ disable_irq(gmac_irq[dev_index]); /* disable GMAC interrupt */ -+ -+ status.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS); /* read DMA status */ -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS,status.bits32,status.bits32); /* clear DMA status */ -+ -+ if (status.bits.rx_overrun == 1) -+ { -+ printk("%s::RX Overrun !!!%d\n",__func__,gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RBNR)); -+ gmac_dump_register(dev); -+ /* if RX DMA process is stoped , restart it */ -+ rxdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC) ; -+ if (rxdma_busy.bits.rd_busy == 0) -+ { -+ /* restart Rx DMA process */ -+ rxdma_ctrl.bits32 = 0; -+ rxdma_ctrl.bits.rd_start = 1; /* start RX DMA transfer */ -+ rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */ -+ rxdma_ctrl_mask.bits32 = 0; -+ rxdma_ctrl_mask.bits.rd_start = 1; -+ rxdma_ctrl_mask.bits.rd_continue = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32); -+ } -+ } -+ -+ /* process rx packet */ -+ if (netif_running(dev) && ((status.bits.rs_eofi==1)||(status.bits.rs_finish==1))) -+ { -+ if (likely(netif_rx_schedule_prep(dev))) -+ { -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,0,0x0007c000); /* disable rx interrupt */ -+ __netif_rx_schedule(dev); -+ } -+ } -+#ifndef CONFIG_TXINT_DISABLE -+ /* process tx packet */ -+ if (netif_running(dev) && ((status.bits.ts_eofi==1)||(status.bits.ts_finish==1))) -+ { -+ gmac_tx_packet_complete(dev); -+ } -+#endif -+ -+ enable_irq(gmac_irq[dev_index]); /* enable GMAC interrupt */ -+ return IRQ_RETVAL(handled); -+#endif -+ -+ /* disable GMAC interrupt */ -+ disable_irq(gmac_irq[dev_index]); -+ for (i=0;ipriv; -+ GMAC_TXDMA_CURR_DESC_T tx_desc; -+ GMAC_RXDMA_CURR_DESC_T rx_desc; -+ GMAC_TXDMA_CTRL_T txdma_ctrl,txdma_ctrl_mask; -+ GMAC_RXDMA_CTRL_T rxdma_ctrl,rxdma_ctrl_mask; -+ GMAC_DMA_STATUS_T dma_status,dma_status_mask; -+ int dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ /* program TxDMA Current Descriptor Address register for first descriptor */ -+ tx_desc.bits32 = (unsigned int)(tp->tx_desc_dma); -+ tx_desc.bits.eofie = 1; -+ tx_desc.bits.sof_eof = 0x03; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC,tx_desc.bits32,0xffffffff); -+ gmac_write_reg(gmac_base_addr[dev_index] + 0xff2c,tx_desc.bits32,0xffffffff); /* tx next descriptor address */ -+ -+ /* program RxDMA Current Descriptor Address register for first descriptor */ -+ rx_desc.bits32 = (unsigned int)(tp->rx_desc_dma); -+ rx_desc.bits.eofie = 1; -+ rx_desc.bits.sof_eof = 0x03; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CURR_DESC,rx_desc.bits32,0xffffffff); -+ gmac_write_reg(gmac_base_addr[dev_index] + 0xff3c,rx_desc.bits32,0xffffffff); /* rx next descriptor address */ -+ -+ /* enable GMAC interrupt & disable loopback */ -+ dma_status.bits32 = 0; -+ dma_status.bits.loop_back = 0; /* disable DMA loop-back mode */ -+// dma_status.bits.m_tx_fail = 1; -+ dma_status.bits.m_cnt_full = 1; -+ dma_status.bits.m_rx_pause_on = 1; -+ dma_status.bits.m_tx_pause_on = 1; -+ dma_status.bits.m_rx_pause_off = 1; -+ dma_status.bits.m_tx_pause_off = 1; -+ dma_status.bits.m_rx_overrun = 1; -+ dma_status.bits.m_link_change = 1; -+ dma_status_mask.bits32 = 0; -+ dma_status_mask.bits.loop_back = 1; -+// dma_status_mask.bits.m_tx_fail = 1; -+ dma_status_mask.bits.m_cnt_full = 1; -+ dma_status_mask.bits.m_rx_pause_on = 1; -+ dma_status_mask.bits.m_tx_pause_on = 1; -+ dma_status_mask.bits.m_rx_pause_off = 1; -+ dma_status_mask.bits.m_tx_pause_off = 1; -+ dma_status_mask.bits.m_rx_overrun = 1; -+ dma_status_mask.bits.m_link_change = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS,dma_status.bits32,dma_status_mask.bits32); -+ -+ /* program tx dma control register */ -+ txdma_ctrl.bits32 = 0; -+ txdma_ctrl.bits.td_start = 0; /* start TX DMA transfer */ -+ txdma_ctrl.bits.td_continue = 0; /* continue Tx DMA operation */ -+ txdma_ctrl.bits.td_chain_mode = 1; /* chain mode */ -+ txdma_ctrl.bits.td_prot = 0; -+ txdma_ctrl.bits.td_burst_size = 2; /* DMA burst size for every AHB request */ -+ txdma_ctrl.bits.td_bus = 2; /* peripheral bus width */ -+ txdma_ctrl.bits.td_endian = 0; /* little endian */ -+#ifdef CONFIG_TXINT_DISABLE -+ txdma_ctrl.bits.td_finish_en = 0; /* DMA finish event interrupt disable */ -+#else -+ txdma_ctrl.bits.td_finish_en = 1; /* DMA finish event interrupt enable */ -+#endif -+ txdma_ctrl.bits.td_fail_en = 1; /* DMA fail interrupt enable */ -+ txdma_ctrl.bits.td_perr_en = 1; /* protocol failure interrupt enable */ -+ txdma_ctrl.bits.td_eod_en = 0; /* disable Tx End of Descriptor Interrupt */ -+ //txdma_ctrl.bits.td_eod_en = 0; /* disable Tx End of Descriptor Interrupt */ -+#ifdef CONFIG_TXINT_DISABLE -+ txdma_ctrl.bits.td_eof_en = 0; /* end of frame interrupt disable */ -+#else -+ txdma_ctrl.bits.td_eof_en = 1; /* end of frame interrupt enable */ -+#endif -+ txdma_ctrl_mask.bits32 = 0; -+ txdma_ctrl_mask.bits.td_start = 1; -+ txdma_ctrl_mask.bits.td_continue = 1; -+ txdma_ctrl_mask.bits.td_chain_mode = 1; -+ txdma_ctrl_mask.bits.td_prot = 15; -+ txdma_ctrl_mask.bits.td_burst_size = 3; -+ txdma_ctrl_mask.bits.td_bus = 3; -+ txdma_ctrl_mask.bits.td_endian = 1; -+ txdma_ctrl_mask.bits.td_finish_en = 1; -+ txdma_ctrl_mask.bits.td_fail_en = 1; -+ txdma_ctrl_mask.bits.td_perr_en = 1; -+ txdma_ctrl_mask.bits.td_eod_en = 1; -+ //txdma_ctrl_mask.bits.td_eod_en = 1; -+ txdma_ctrl_mask.bits.td_eof_en = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,txdma_ctrl.bits32,txdma_ctrl_mask.bits32); -+ -+ /* program rx dma control register */ -+ rxdma_ctrl.bits32 = 0; -+ rxdma_ctrl.bits.rd_start = 1; /* start RX DMA transfer */ -+ rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */ -+ rxdma_ctrl.bits.rd_chain_mode = 1; /* chain mode */ -+ rxdma_ctrl.bits.rd_prot = 0; -+ rxdma_ctrl.bits.rd_burst_size = 2; /* DMA burst size for every AHB request */ -+ rxdma_ctrl.bits.rd_bus = 2; /* peripheral bus width */ -+ rxdma_ctrl.bits.rd_endian = 0; /* little endian */ -+ rxdma_ctrl.bits.rd_finish_en = 1; /* DMA finish event interrupt enable */ -+ rxdma_ctrl.bits.rd_fail_en = 1; /* DMA fail interrupt enable */ -+ rxdma_ctrl.bits.rd_perr_en = 1; /* protocol failure interrupt enable */ -+ rxdma_ctrl.bits.rd_eod_en = 0; /* disable Rx End of Descriptor Interrupt */ -+ rxdma_ctrl.bits.rd_eof_en = 1; /* end of frame interrupt enable */ -+ rxdma_ctrl_mask.bits32 = 0; -+ rxdma_ctrl_mask.bits.rd_start = 1; -+ rxdma_ctrl_mask.bits.rd_continue = 1; -+ rxdma_ctrl_mask.bits.rd_chain_mode = 1; -+ rxdma_ctrl_mask.bits.rd_prot = 15; -+ rxdma_ctrl_mask.bits.rd_burst_size = 3; -+ rxdma_ctrl_mask.bits.rd_bus = 3; -+ rxdma_ctrl_mask.bits.rd_endian = 1; -+ rxdma_ctrl_mask.bits.rd_finish_en = 1; -+ rxdma_ctrl_mask.bits.rd_fail_en = 1; -+ rxdma_ctrl_mask.bits.rd_perr_en = 1; -+ rxdma_ctrl_mask.bits.rd_eod_en = 1; -+ rxdma_ctrl_mask.bits.rd_eof_en = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32); -+ return; -+} -+ -+static void gmac_hw_stop(struct net_device *dev) -+{ -+ GMAC_TXDMA_CTRL_T txdma_ctrl,txdma_ctrl_mask; -+ GMAC_RXDMA_CTRL_T rxdma_ctrl,rxdma_ctrl_mask; -+ int dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ /* program tx dma control register */ -+ txdma_ctrl.bits32 = 0; -+ txdma_ctrl.bits.td_start = 0; -+ txdma_ctrl.bits.td_continue = 0; -+ txdma_ctrl_mask.bits32 = 0; -+ txdma_ctrl_mask.bits.td_start = 1; -+ txdma_ctrl_mask.bits.td_continue = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,txdma_ctrl.bits32,txdma_ctrl_mask.bits32); -+ /* program rx dma control register */ -+ rxdma_ctrl.bits32 = 0; -+ rxdma_ctrl.bits.rd_start = 0; /* stop RX DMA transfer */ -+ rxdma_ctrl.bits.rd_continue = 0; /* stop continue RX DMA operation */ -+ rxdma_ctrl_mask.bits32 = 0; -+ rxdma_ctrl_mask.bits.rd_start = 1; -+ rxdma_ctrl_mask.bits.rd_continue = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32); -+} -+ -+static int gmac_init_desc_buf(struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ struct sk_buff *skb; -+ dma_addr_t tx_first_desc_dma=0; -+ dma_addr_t rx_first_desc_dma=0; -+ dma_addr_t rx_first_buf_dma=0; -+ unsigned int i,index; -+ -+ printk("Descriptor buffer init......\n"); -+ -+ /* get device index number */ -+ index = gmac_get_dev_index(dev); -+#ifdef CONFIG_SL2312_MPAGE -+ for (i=0; itx_desc = DMA_MALLOC(TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(dma_addr_t *)&tp->tx_desc_dma); -+ tx_desc_virtual_base[index] = (unsigned int)tp->tx_desc - (unsigned int)tp->tx_desc_dma; -+ memset(tp->tx_desc,0x00,TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T)); -+ tp->rx_desc = DMA_MALLOC(RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(dma_addr_t *)&tp->rx_desc_dma); -+ rx_desc_virtual_base[index] = (unsigned int)tp->rx_desc - (unsigned int)tp->rx_desc_dma; -+ memset(tp->rx_desc,0x00,RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T)); -+ tx_desc_start_adr[index] = (unsigned int)tp->tx_desc; /* for tx skb index calculation */ -+ rx_desc_start_adr[index] = (unsigned int)tp->rx_desc; /* for rx skb index calculation */ -+ printk("tx_desc = %08x\n",(unsigned int)tp->tx_desc); -+ printk("rx_desc = %08x\n",(unsigned int)tp->rx_desc); -+ printk("tx_desc_dma = %08x\n",tp->tx_desc_dma); -+ printk("rx_desc_dma = %08x\n",tp->rx_desc_dma); -+ -+ if (tp->tx_desc==0x00 || tp->rx_desc==0x00) -+ { -+ free_irq(dev->irq, dev); -+ -+ if (tp->tx_desc) -+ DMA_MFREE(tp->tx_desc, TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),tp->tx_desc_dma); -+ if (tp->rx_desc) -+ DMA_MFREE(tp->rx_desc, RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),tp->rx_desc_dma); -+ return -ENOMEM; -+ } -+ -+ /* TX descriptors initial */ -+ tp->tx_cur_desc = tp->tx_desc; /* virtual address */ -+ tp->tx_finished_desc = tp->tx_desc; /* virtual address */ -+ tx_first_desc_dma = tp->tx_desc_dma; /* physical address */ -+ for (i = 1; i < TX_DESC_NUM; i++) -+ { -+ tp->tx_desc->frame_ctrl.bits_tx_out.own = CPU; /* set owner to CPU */ -+ tp->tx_desc->frame_ctrl.bits_tx_out.buffer_size = TX_BUF_SIZE; /* set tx buffer size for descriptor */ -+ tp->tx_desc_dma = tp->tx_desc_dma + sizeof(GMAC_DESCRIPTOR_T); /* next tx descriptor DMA address */ -+ tp->tx_desc->next_desc.next_descriptor = tp->tx_desc_dma | 0x0000000b; -+ tp->tx_desc = &tp->tx_desc[1] ; /* next tx descriptor virtual address */ -+ } -+ /* the last descriptor will point back to first descriptor */ -+ tp->tx_desc->frame_ctrl.bits_tx_out.own = CPU; -+ tp->tx_desc->frame_ctrl.bits_tx_out.buffer_size = TX_BUF_SIZE; -+ tp->tx_desc->next_desc.next_descriptor = tx_first_desc_dma | 0x0000000b; -+ tp->tx_desc = tp->tx_cur_desc; -+ tp->tx_desc_dma = tx_first_desc_dma; -+ -+ /* RX descriptors initial */ -+ tp->rx_cur_desc = tp->rx_desc; /* virtual address */ -+ rx_first_desc_dma = tp->rx_desc_dma; /* physical address */ -+ for (i = 1; i < RX_DESC_NUM; i++) -+ { -+ if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL) /* allocate socket buffer */ -+ { -+ printk("%s::skb buffer allocation fail !\n",__func__); -+ } -+ rx_skb[index][i-1] = skb; -+ tp->rx_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02; /* insert two bytes in the beginning of rx data */ -+ tp->rx_desc->frame_ctrl.bits_rx.own = DMA; /* set owner bit to DMA */ -+ tp->rx_desc->frame_ctrl.bits_rx.buffer_size = RX_BUF_SIZE; /* set rx buffer size for descriptor */ -+ tp->rx_bufs_dma = tp->rx_bufs_dma + RX_BUF_SIZE; /* point to next buffer address */ -+ tp->rx_desc_dma = tp->rx_desc_dma + sizeof(GMAC_DESCRIPTOR_T); /* next rx descriptor DMA address */ -+ tp->rx_desc->next_desc.next_descriptor = tp->rx_desc_dma | 0x0000000b; -+ tp->rx_desc = &tp->rx_desc[1]; /* next rx descriptor virtual address */ -+ } -+ /* the last descriptor will point back to first descriptor */ -+ if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL) /* allocate socket buffer */ -+ { -+ printk("%s::skb buffer allocation fail !\n",__func__); -+ } -+ rx_skb[index][i-1] = skb; -+ tp->rx_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02; /* insert two bytes in the beginning of rx data */ -+ tp->rx_desc->frame_ctrl.bits_rx.own = DMA; -+ tp->rx_desc->frame_ctrl.bits_rx.buffer_size = RX_BUF_SIZE; -+ tp->rx_desc->next_desc.next_descriptor = rx_first_desc_dma | 0x0000000b; -+ tp->rx_desc = tp->rx_cur_desc; -+ tp->rx_desc_dma = rx_first_desc_dma; -+ tp->rx_bufs_dma = rx_first_buf_dma; -+ -+ for (i=0; itx_desc_hdr[i] = 0; -+ tp->tx_desc_tail[i] = 0; -+ } -+ return (0); -+} -+ -+static int gmac_clear_counter (struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ unsigned int dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+// tp = gmac_dev[index]->priv; -+ /* clear counter */ -+ gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_DISCARDS); -+ gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_ERRORS); -+ tp->stats.tx_bytes = 0; -+ tp->stats.tx_packets = 0; -+ tp->stats.tx_errors = 0; -+ tp->stats.rx_bytes = 0; -+ tp->stats.rx_packets = 0; -+ tp->stats.rx_errors = 0; -+ tp->stats.rx_dropped = 0; -+ return (0); -+} -+ -+static int gmac_open (struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ int retval; -+ -+ gmac_select_interface(dev); -+ -+ /* chip reset */ -+ gmac_sw_reset(dev); -+ -+ /* allocates tx/rx descriptor and buffer memory */ -+ gmac_init_desc_buf(dev); -+ -+ /* get mac address from FLASH */ -+ gmac_get_mac_address(); -+ -+ /* set PHY register to start autonegition process */ -+ gmac_set_phy_status(dev); -+ -+ /* GMAC initialization */ -+ if (gmac_init_chip(dev)) -+ { -+ printk (KERN_ERR "GMAC init fail\n"); -+ } -+ -+ /* start DMA process */ -+ gmac_hw_start(dev); -+ -+ /* enable tx/rx register */ -+ gmac_enable_tx_rx(dev); -+ -+ /* clear statistic counter */ -+ gmac_clear_counter(dev); -+ -+ netif_start_queue (dev); -+ -+ /* hook ISR */ -+ retval = request_irq (dev->irq, gmac_interrupt, SA_INTERRUPT, dev->name, dev); -+ if (retval) -+ return retval; -+ -+ if(!FLAG_SWITCH) -+ { -+ init_waitqueue_head (&tp->thr_wait); -+ init_completion(&tp->thr_exited); -+ -+ tp->time_to_die = 0; -+ tp->thr_pid = kernel_thread (gmac_phy_thread, dev, CLONE_FS | CLONE_FILES); -+ if (tp->thr_pid < 0) -+ { -+ printk (KERN_WARNING "%s: unable to start kernel thread\n",dev->name); -+ } -+ } -+ return (0); -+} -+ -+static int gmac_close(struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ unsigned int i,dev_index; -+ unsigned int ret; -+ -+ dev_index = gmac_get_dev_index(dev); -+ -+ /* stop tx/rx packet */ -+ gmac_disable_tx_rx(dev); -+ -+ /* stop the chip's Tx and Rx DMA processes */ -+ gmac_hw_stop(dev); -+ -+ netif_stop_queue(dev); -+ -+ /* disable interrupts by clearing the interrupt mask */ -+ synchronize_irq(); -+ free_irq(dev->irq,dev); -+ -+ DMA_MFREE(tp->tx_desc, TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(unsigned int)tp->tx_desc_dma); -+ DMA_MFREE(tp->rx_desc, RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(unsigned int)tp->rx_desc_dma); -+ -+#ifdef CONFIG_SL2312_MPAGE -+// kfree(tx_skb); -+#endif -+ -+ for (i=0;ithr_pid >= 0) -+ { -+ tp->time_to_die = 1; -+ wmb(); -+ ret = kill_proc (tp->thr_pid, SIGTERM, 1); -+ if (ret) -+ { -+ printk (KERN_ERR "%s: unable to signal thread\n", dev->name); -+ return ret; -+ } -+// wait_for_completion (&tp->thr_exited); -+ } -+ } -+ -+ return (0); -+} -+ -+#ifdef CONFIG_SL2312_MPAGE -+int printk_all(int dev_index, struct gmac_private* tp) -+{ -+ int i=0; -+ unsigned int tx_current_descriptor = 0; -+ int hw_index; -+ int fi; -+ GMAC_DESCRIPTOR_T* tmp_desc; -+ -+ GMAC_DESCRIPTOR_T* cur_desc=tp->tx_cur_desc; -+ fi = ((unsigned int)cur_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ printk("tmp_desc %x, id %d\n", (int)cur_desc, fi); -+ -+ tmp_desc = (GMAC_DESCRIPTOR_T*)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0) + tx_desc_virtual_base[dev_index]); -+ hw_index = ((unsigned int)tmp_desc - tx_desc_start_adr[dev_index])/ sizeof(GMAC_DESCRIPTOR_T); -+ printk("hd_desc %x, ind %d, fin desc %x\n",(int)tmp_desc, hw_index, (int)tp->tx_finished_desc); -+ -+ for (i=0; i ", fi, hw_index); -+ printk("fc %8x ", tmp_desc->frame_ctrl.bits32); -+ printk("fs %8x ", tmp_desc->flag_status.bits32); -+ printk("fb %8x ", tmp_desc->buf_adr); -+ printk("fd %8x\n", tmp_desc->next_desc.next_descriptor); -+ tmp_desc = (GMAC_DESCRIPTOR_T*)((tmp_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]); -+ fi = ((unsigned int)tmp_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ } -+ tx_current_descriptor = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC); -+ printk("%s: tx current descriptor = %x \n",__func__,tx_current_descriptor); -+ printk("%s: interrupt status = %x \n",__func__,int_status); -+ return 0; -+} -+ -+int cleanup_desc(int dev_index, struct gmac_private* tp) -+{ -+ int i=0; -+ int index = ((unsigned int)tp->tx_cur_desc - tx_desc_start_adr[dev_index])/sizeof(GMAC_DESCRIPTOR_T); -+ GMAC_DESCRIPTOR_T* fill_desc = tp->tx_cur_desc; -+ -+ for (i=0; i< TX_DESC_NUM; i++) -+ { -+ fill_desc->frame_ctrl.bits_tx_out.own = CPU; -+ fill_desc->frame_ctrl.bits_tx_out.buffer_size = TX_BUF_SIZE; -+ tx_skb[dev_index][index].desc_in_use = 0; -+ free_tx_buf(dev_index, index); -+ printk("cleanup di %d\n", index); -+ fill_desc = (GMAC_DESCRIPTOR_T*)((fill_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]); -+ index++; -+ if (index > TX_DESC_NUM) -+ index = 0; -+ } -+ return 1; -+} -+ -+size_t get_available_tx_desc(struct net_device* dev, int dev_index) -+{ -+ struct gmac_private *tp = dev->priv; -+ unsigned int desc_hdr = tp->tx_desc_hdr[dev_index]; -+ unsigned int desc_tail = tp->tx_desc_tail[dev_index]; -+ int available_desc_num = (TX_DESC_NUM - desc_hdr + desc_tail) & (TX_DESC_NUM-1); -+ if (!available_desc_num) { -+ if (tx_skb[dev_index][desc_hdr].desc_in_use) -+ return 0; -+ else -+ return TX_DESC_NUM; -+ } -+ return available_desc_num; -+} -+ -+int check_free_tx_desc(int dev_index, int n, GMAC_DESCRIPTOR_T* desc) -+{ -+ int i,index; -+ GMAC_DESCRIPTOR_T* tmp_desc = desc; -+ -+ if (n > TX_DESC_NUM) -+ return 0; -+ -+ index = ((unsigned int)tmp_desc - tx_desc_start_adr[dev_index])/sizeof(GMAC_DESCRIPTOR_T); -+ for (i=0; i> 12) & 0x000F) -+ -+inline int fill_in_desc(int dev_index, GMAC_DESCRIPTOR_T *desc, char* data, int len, int total_len, int sof, int freeable, int ownership, struct sk_buff* skb) -+{ -+ int index = ((unsigned int)desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ -+ if (desc->frame_ctrl.bits_tx_in.own == CPU) -+ { -+ tx_skb[dev_index][index].freeable = freeable; -+ if ((sof & 0x01) && skb) { -+ tx_skb[dev_index][index].skb = skb; -+ } -+ else -+ tx_skb[dev_index][index].skb = 0; -+ -+ if (sof != 2) -+ tx_skb[dev_index][index].desc_in_use = 1; -+ else -+ tx_skb[dev_index][index].desc_in_use = 0; -+ -+ consistent_sync(data, len, PCI_DMA_TODEVICE); -+ desc->buf_adr = (unsigned int)__pa(data); -+ desc->frame_ctrl.bits_tx_out.buffer_size = len; -+ desc->flag_status.bits_tx_flag.frame_count = total_len; -+ desc->next_desc.bits.eofie = 1; -+ desc->next_desc.bits.sof_eof = sof; -+ desc->frame_ctrl.bits_tx_out.vlan_enable = 0; -+ desc->frame_ctrl.bits_tx_out.ip_csum_en = 1; /* TSS IPv4 IP header checksum enable */ -+ desc->frame_ctrl.bits_tx_out.ipv6_tx_en = 1; /* TSS IPv6 tx enable */ -+ desc->frame_ctrl.bits_tx_out.tcp_csum_en = 1; /* TSS TCP checksum enable */ -+ desc->frame_ctrl.bits_tx_out.udp_csum_en = 1; /* TSS UDP checksum enable */ -+ wmb(); -+ desc->frame_ctrl.bits_tx_out.own = ownership; -+// consistent_sync(desc, sizeof(GMAC_DESCRIPTOR_T), PCI_DMA_TODEVICE); -+ } -+ return 0; -+} -+#endif -+ -+static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ GMAC_TXDMA_CTRL_T tx_ctrl,tx_ctrl_mask; -+ GMAC_TXDMA_FIRST_DESC_T txdma_busy; -+ unsigned int len = skb->len; -+ unsigned int dev_index; -+ static unsigned int pcount = 0; -+#ifdef CONFIG_SL2312_MPAGE -+ GMAC_DESCRIPTOR_T *fill_desc; -+ int snd_pages = skb_shinfo(skb)->nr_frags; /* get number of descriptor */ -+ int desc_needed = 1; // for jumbo packet, one descriptor is enough. -+ int header_len = skb->len; -+ struct iphdr *ip_hdr; -+ struct tcphdr *tcp_hdr; -+ int tcp_hdr_len; -+ int data_len; -+ int prv_index; -+ long seq_num; -+ int first_desc_index; -+ int ownership, freeable; -+ int eof; -+ int i=0; -+#endif -+#ifdef CONFIG_TXINT_DISABLE -+ int available_desc_cnt = 0; -+#endif -+ -+ dev_index = gmac_select_interface(dev); -+ -+#ifdef CONFIG_TXINT_DISABLE -+ available_desc_cnt = get_available_tx_desc(dev, dev_index); -+ -+ if (available_desc_cnt < (TX_DESC_NUM >> 2)) { -+ gmac_tx_packet_complete(dev); -+ } -+#endif -+ -+#ifdef CONFIG_SL2312_MPAGE -+ -+ fill_desc = tp->tx_cur_desc; -+ if(!fill_desc) { -+ printk("cur_desc is NULL!\n"); -+ return -1; -+ } -+ -+ if (storlink_ctl.recvfile==2) -+ { -+ printk("snd_pages=%d skb->len=%d\n",snd_pages,skb->len); -+ } -+ -+ if (snd_pages) -+ desc_needed += snd_pages; /* decriptors needed for this large packet */ -+ -+ if (!check_free_tx_desc(dev_index, desc_needed, fill_desc)) { -+ printk("no available desc!\n"); -+ gmac_dump_register(dev); -+ printk_all(dev_index, tp); -+ tp->stats.tx_dropped++; -+ if (pcount++ > 10) -+ { -+ for (;;); -+ } -+ return -1; -+ } -+ -+ first_desc_index = ((unsigned int)fill_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ -+ /* check if the tcp packet is in order*/ -+ ip_hdr = (struct iphdr*) &(skb->data[14]); -+ tcp_hdr = (struct tcphdr*) &(skb->data[14+ip_hdr->ihl * 4]); -+ tcp_hdr_len = TCPHDRLEN(tcp_hdr) * 4; -+ data_len = skb->len - 14 - ip_hdr->ihl *4 - tcp_hdr_len; -+ -+ prv_index = first_desc_index-1; -+ if (prv_index <0) -+ prv_index += TX_DESC_NUM; -+ seq_num = ntohl(tcp_hdr->seq); -+ -+ if (snd_pages) -+ { -+ // calculate header length -+ // check fragment total length and header len = skb len - frag len -+ // or parse the header. -+ for (i=0; ifrags[i]; -+ header_len -= frag->size; -+ } -+ ownership = CPU; -+ freeable = 0; -+ /* fill header into first descriptor */ -+ fill_in_desc(dev_index, fill_desc, skb->data, header_len, len, 2, freeable, ownership, 0); -+ fill_desc = (GMAC_DESCRIPTOR_T*)((fill_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]); -+ tx_skb[dev_index][first_desc_index].end_seq = seq_num + data_len; -+ -+ eof = 0; -+ ownership = DMA; -+ for (i=0; ifrags[i]; -+ int start_pos = frag->page_offset; -+ char* data_buf = page_address(frag->page); -+ int data_size = frag->size; -+ int cur_index; -+ -+ if (i == snd_pages-1) -+ { -+ eof=1; -+ freeable = 1; -+ } -+ fill_in_desc(dev_index, fill_desc, data_buf+(start_pos), data_size, -+ len, eof, freeable, ownership, skb); -+ cur_index = ((unsigned int)fill_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ -+ fill_desc = (GMAC_DESCRIPTOR_T*)((fill_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]); -+ } -+ /* pass the ownership of the first descriptor to hardware */ -+// disable_irq(gmac_irq[dev_index]); -+ tx_skb[dev_index][first_desc_index].desc_in_use = 1; -+ wmb(); -+ tp->tx_cur_desc->frame_ctrl.bits_tx_out.own = DMA; -+// consistent_sync(tp->tx_cur_desc, sizeof(GMAC_DESCRIPTOR_T), PCI_DMA_TODEVICE); -+ tp->tx_cur_desc = fill_desc; -+ dev->trans_start = jiffies; -+// enable_irq(gmac_irq[dev_index]); -+ } -+ else if ( tp->tx_cur_desc->frame_ctrl.bits_tx_out.own == CPU ) -+ { -+// tx_skb[dev_index][first_desc_index].end_seq = seq_num + data_len; -+// disable_irq(gmac_irq[dev_index]); -+ fill_in_desc(dev_index, tp->tx_cur_desc, skb->data, skb->len, skb->len, 3, 1, DMA, skb); -+// enable_irq(gmac_irq[dev_index]); -+ //consistent_sync(tp->tx_cur_desc, sizeof(GMAC_DESCRIPTOR_T), PCI_DMA_TODEVICE); -+ tp->tx_cur_desc = (GMAC_DESCRIPTOR_T*)((tp->tx_cur_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]); -+ dev->trans_start = jiffies; -+ } -+ else -+ { -+ printk("gmac tx drop!\n"); -+ tp->stats.tx_dropped++; -+ return -1; -+ } -+ -+#ifdef CONFIG_TXINT_DISABLE -+ tp->tx_desc_hdr[dev_index] = (tp->tx_desc_hdr[dev_index] + desc_needed) & (TX_DESC_NUM-1); -+#endif -+ -+#else -+ if ((tp->tx_cur_desc->frame_ctrl.bits_tx_out.own == CPU) && (len < TX_BUF_SIZE)) -+ { -+ index = ((unsigned int)tp->tx_cur_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T); -+ tx_skb[dev_index][index] = skb; -+ consistent_sync(skb->data,skb->len,PCI_DMA_TODEVICE); -+ tp->tx_cur_desc->buf_adr = (unsigned int)__pa(skb->data); -+ tp->tx_cur_desc->flag_status.bits_tx_flag.frame_count = len; /* total frame byte count */ -+ tp->tx_cur_desc->next_desc.bits.sof_eof = 0x03; /*only one descriptor*/ -+ tp->tx_cur_desc->frame_ctrl.bits_tx_out.buffer_size = len; /* descriptor byte count */ -+ tp->tx_cur_desc->frame_ctrl.bits_tx_out.vlan_enable = 0; -+ tp->tx_cur_desc->frame_ctrl.bits_tx_out.ip_csum_en = 0; /* TSS IPv4 IP header checksum enable */ -+ tp->tx_cur_desc->frame_ctrl.bits_tx_out.ipv6_tx_en = 0 ; /* TSS IPv6 tx enable */ -+ tp->tx_cur_desc->frame_ctrl.bits_tx_out.tcp_csum_en = 0; /* TSS TCP checksum enable */ -+ tp->tx_cur_desc->frame_ctrl.bits_tx_out.udp_csum_en = 0; /* TSS UDP checksum enable */ -+ wmb(); -+ tp->tx_cur_desc->frame_ctrl.bits_tx_out.own = DMA; /* set owner bit */ -+ tp->tx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]); -+ dev->trans_start = jiffies; -+ } -+ else -+ { -+ /* no free tx descriptor */ -+ dev_kfree_skb(skb); -+ netif_stop_queue(dev); -+ tp->stats.tx_dropped++; -+ return (-1); -+ } -+#endif -+ /* if TX DMA process is stoped , restart it */ -+ txdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_FIRST_DESC); -+ if (txdma_busy.bits.td_busy == 0) -+ { -+ /* restart DMA process */ -+ tx_ctrl.bits32 = 0; -+ tx_ctrl.bits.td_start = 1; -+ tx_ctrl.bits.td_continue = 1; -+ tx_ctrl_mask.bits32 = 0; -+ tx_ctrl_mask.bits.td_start = 1; -+ tx_ctrl_mask.bits.td_continue = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,tx_ctrl.bits32,tx_ctrl_mask.bits32); -+ } -+ return (0); -+} -+ -+ -+struct net_device_stats * gmac_get_stats(struct net_device *dev) -+{ -+ struct gmac_private *tp = dev->priv; -+ unsigned long flags; -+ unsigned int pkt_drop; -+ unsigned int pkt_error; -+ unsigned int dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+ -+// if (storlink_ctl.recvfile==3) -+// { -+// printk("GMAC_GLOBAL_BASE_ADDR=%x\n", readl(GMAC_GLOBAL_BASE_ADDR+0x30)); -+// gmac_dump_register(dev); -+// printk_all(0, dev); -+// } -+ -+ if (netif_running(dev)) -+ { -+ /* read H/W counter */ -+ spin_lock_irqsave(&tp->lock,flags); -+ pkt_drop = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_DISCARDS); -+ pkt_error = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_ERRORS); -+ tp->stats.rx_dropped = tp->stats.rx_dropped + pkt_drop; -+ tp->stats.rx_errors = tp->stats.rx_errors + pkt_error; -+ spin_unlock_irqrestore(&tp->lock,flags); -+ } -+ return &tp->stats; -+} -+ -+static unsigned const ethernet_polynomial = 0x04c11db7U; -+static inline u32 ether_crc (int length, unsigned char *data) -+{ -+ int crc = -1; -+ unsigned int i; -+ unsigned int crc_val=0; -+ -+ while (--length >= 0) { -+ unsigned char current_octet = *data++; -+ int bit; -+ for (bit = 0; bit < 8; bit++, current_octet >>= 1) -+ crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ? -+ ethernet_polynomial : 0); -+ } -+ crc = ~crc; -+ for (i=0;i<32;i++) -+ { -+ crc_val = crc_val + (((crc << i) & 0x80000000) >> (31-i)); -+ } -+ return crc_val; -+} -+ -+static void gmac_set_rx_mode(struct net_device *dev) -+{ -+ GMAC_RX_FLTR_T filter; -+ unsigned int mc_filter[2]; /* Multicast hash filter */ -+ int bit_nr; -+ unsigned int i, dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+ -+// printk("%s : dev->flags = %x \n",__func__,dev->flags); -+// dev->flags |= IFF_ALLMULTI; /* temp */ -+ filter.bits32 = 0; -+ filter.bits.error = 0; -+ if (dev->flags & IFF_PROMISC) -+ { -+ filter.bits.error = 1; -+ filter.bits.promiscuous = 1; -+ filter.bits.broadcast = 1; -+ filter.bits.multicast = 1; -+ filter.bits.unicast = 1; -+ mc_filter[1] = mc_filter[0] = 0xffffffff; -+ } -+ else if (dev->flags & IFF_ALLMULTI) -+ { -+ filter.bits.promiscuous = 1; -+ filter.bits.broadcast = 1; -+ filter.bits.multicast = 1; -+ filter.bits.unicast = 1; -+ mc_filter[1] = mc_filter[0] = 0xffffffff; -+ } -+ else -+ { -+ struct dev_mc_list *mclist; -+ -+ filter.bits.promiscuous = 1; -+ filter.bits.broadcast = 1; -+ filter.bits.multicast = 1; -+ filter.bits.unicast = 1; -+ mc_filter[1] = mc_filter[0] = 0; -+ for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;i++, mclist = mclist->next) -+ { -+ bit_nr = ether_crc(ETH_ALEN,mclist->dmi_addr) & 0x0000003f; -+ if (bit_nr < 32) -+ { -+ mc_filter[0] = mc_filter[0] | (1<dev_addr[i] = sock->sa_data[i]; -+ } -+ -+ reg_val = dev->dev_addr[0] + (dev->dev_addr[1]<<8) + (dev->dev_addr[2]<<16) + (dev->dev_addr[3]<<24); -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_STA_ADD0,reg_val,0xffffffff); -+ reg_val = dev->dev_addr[4] + (dev->dev_addr[5]<<8) ; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_STA_ADD1,reg_val,0x0000ffff); -+ memcpy(ð0_mac[0],&dev->dev_addr[0],6); -+ printk("Storlink %s address = ",dev->name); -+ printk("%02x",dev->dev_addr[0]); -+ printk("%02x",dev->dev_addr[1]); -+ printk("%02x",dev->dev_addr[2]); -+ printk("%02x",dev->dev_addr[3]); -+ printk("%02x",dev->dev_addr[4]); -+ printk("%02x\n",dev->dev_addr[5]); -+ -+ return (0); -+} -+ -+static void gmac_tx_timeout(struct net_device *dev) -+{ -+ GMAC_TXDMA_CTRL_T tx_ctrl,tx_ctrl_mask; -+ GMAC_TXDMA_FIRST_DESC_T txdma_busy; -+ int dev_index; -+ -+ dev_index = gmac_select_interface(dev); -+ -+ /* if TX DMA process is stoped , restart it */ -+ txdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_FIRST_DESC); -+ if (txdma_busy.bits.td_busy == 0) -+ { -+ /* restart DMA process */ -+ tx_ctrl.bits32 = 0; -+ tx_ctrl.bits.td_start = 1; -+ tx_ctrl.bits.td_continue = 1; -+ tx_ctrl_mask.bits32 = 0; -+ tx_ctrl_mask.bits.td_start = 1; -+ tx_ctrl_mask.bits.td_continue = 1; -+ gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,tx_ctrl.bits32,tx_ctrl_mask.bits32); -+ } -+ netif_wake_queue(dev); -+ return; -+} -+ -+static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -+{ -+ int rc = 0; -+ unsigned char *hwa = rq->ifr_ifru.ifru_hwaddr.sa_data; -+ -+ if (!netif_running(dev)) -+ { -+ printk("Before changing the H/W address,please down the device.\n"); -+ return -EINVAL; -+ } -+ -+ switch (cmd) { -+ case SIOCETHTOOL: -+ break; -+ -+ case SIOCSIFHWADDR: -+ gmac_set_mac_address(dev,hwa); -+ break; -+ -+ case SIOCGMIIPHY: /* Get the address of the PHY in use. */ -+ case SIOCDEVPRIVATE: /* binary compat, remove in 2.5 */ -+ break; -+ -+ case SIOCGMIIREG: /* Read the specified MII register. */ -+ case SIOCDEVPRIVATE+1: -+ break; -+ -+ case SIOCSMIIREG: /* Write the specified MII register */ -+ case SIOCDEVPRIVATE+2: -+ break; -+ -+ default: -+ rc = -EOPNOTSUPP; -+ break; -+ } -+ -+ return rc; -+} -+ -+static void gmac_cleanup_module(void) -+{ -+ int i; -+ -+ for (i=0;ipriv; -+ -+ dev[i]->base_addr = gmac_base_addr[i]; -+ dev[i]->irq = gmac_irq[i]; -+ dev[i]->open = gmac_open; -+ dev[i]->stop = gmac_close; -+ dev[i]->hard_start_xmit = gmac_start_xmit; -+ dev[i]->get_stats = gmac_get_stats; -+ dev[i]->set_multicast_list = gmac_set_rx_mode; -+ dev[i]->set_mac_address = gmac_set_mac_address; -+ dev[i]->do_ioctl = gmac_netdev_ioctl; -+ dev[i]->tx_timeout = gmac_tx_timeout; -+ dev[i]->watchdog_timeo = TX_TIMEOUT; -+ dev[i]->features |= NETIF_F_SG|NETIF_F_HW_CSUM|NETIF_F_TSO; -+#ifdef CONFIG_SL_NAPI -+ printk("NAPI driver is enabled.\n"); -+ if (i==0) -+ { -+ dev[i]->poll = gmac_rx_poll_ga; -+ dev[i]->weight = 64; -+ } -+ else -+ { -+ dev[i]->poll = gmac_rx_poll_gb; -+ dev[i]->weight = 64; -+ } -+#endif -+ -+ if (register_netdev(dev[i])) -+ { -+ gmac_cleanup_module(); -+ return(-1); -+ } -+ } -+ -+#ifdef CONFIG_SL3516_ASIC -+{ -+ unsigned int val; -+ -+ /* set GMAC global register */ -+ val = readl(GMAC_GLOBAL_BASE_ADDR+0x10); -+ val = val | 0x005a0000; -+ writel(val,GMAC_GLOBAL_BASE_ADDR+0x10); -+ writel(0x07f007f0,GMAC_GLOBAL_BASE_ADDR+0x1c); -+ writel(0x77770000,GMAC_GLOBAL_BASE_ADDR+0x20); -+ writel(0x77770000,GMAC_GLOBAL_BASE_ADDR+0x24); -+ val = readl(GMAC_GLOBAL_BASE_ADDR+0x04); -+ if((val&(1<<20))==0){ // GMAC1 enable -+ val = readl(GMAC_GLOBAL_BASE_ADDR+0x30); -+ val = (val & 0xe7ffffff) | 0x08000000; -+ writel(val,GMAC_GLOBAL_BASE_ADDR+0x30); -+ } -+ -+} -+#endif -+ -+// printk("%s: dev0=%x dev1=%x \n",__func__,dev[0],dev[1]); -+// FLAG_SWITCH = 0 ; -+// FLAG_SWITCH = SPI_get_identifier(); -+// if(FLAG_SWITCH) -+// { -+// printk("Configure ADM699X...\n"); -+// SPI_default(); //Add by jason for ADM699X configuration -+// } -+ return (0); -+} -+ -+ -+module_init(gmac_init_module); -+module_exit(gmac_cleanup_module); -+ -+static int gmac_phy_thread (void *data) -+{ -+ struct net_device *dev = data; -+ struct gmac_private *tp = dev->priv; -+ unsigned long timeout; -+ -+ daemonize("%s", dev->name); -+ allow_signal(SIGTERM); -+// reparent_to_init(); -+// spin_lock_irq(¤t->sigmask_lock); -+// sigemptyset(¤t->blocked); -+// recalc_sigpending(current); -+// spin_unlock_irq(¤t->sigmask_lock); -+// strncpy (current->comm, dev->name, sizeof(current->comm) - 1); -+// current->comm[sizeof(current->comm) - 1] = '\0'; -+ -+ while (1) -+ { -+ timeout = next_tick; -+ do -+ { -+ timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout); -+ } while (!signal_pending (current) && (timeout > 0)); -+ -+ if (signal_pending (current)) -+ { -+// spin_lock_irq(¤t->sigmask_lock); -+ flush_signals(current); -+// spin_unlock_irq(¤t->sigmask_lock); -+ } -+ -+ if (tp->time_to_die) -+ break; -+ -+// printk("%s : Polling PHY Status...%x\n",__func__,dev); -+ rtnl_lock (); -+ gmac_get_phy_status(dev); -+ rtnl_unlock (); -+ } -+ complete_and_exit (&tp->thr_exited, 0); -+} -+ -+static void gmac_set_phy_status(struct net_device *dev) -+{ -+ GMAC_STATUS_T status; -+ unsigned int reg_val; -+ unsigned int i = 0; -+ unsigned int index; -+ -+ if (FLAG_SWITCH==1) -+ { -+ return; /* GMAC connects to a switch chip, not PHY */ -+ } -+ -+ index = gmac_get_dev_index(dev); -+ -+ if (index == 0) -+ { -+// mii_write(phy_addr[index],0x04,0x0461); /* advertisement 10M full duplex, pause capable on */ -+// mii_write(phy_addr[index],0x04,0x0421); /* advertisement 10M half duplex, pause capable on */ -+ mii_write(phy_addr[index],0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */ -+// mii_write(phy_addr[index],0x04,0x04a1); /* advertisement 100M half duplex, pause capable on */ -+#ifdef CONFIG_SL3516_ASIC -+ mii_write(phy_addr[index],0x09,0x0300); /* advertisement 1000M full duplex, pause capable on */ -+// mii_write(phy_addr[index],0x09,0x0000); /* advertisement 1000M full duplex, pause capable on */ -+#endif -+ } -+ else -+ { -+// mii_write(phy_addr[index],0x04,0x0461); /* advertisement 10M full duplex, pause capable on */ -+// mii_write(phy_addr[index],0x04,0x0421); /* advertisement 10M half duplex, pause capable on */ -+ mii_write(phy_addr[index],0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */ -+// mii_write(phy_addr[index],0x04,0x04a1); /* advertisement 100M half duplex, pause capable on */ -+#ifdef CONFIG_SL3516_ASIC -+// mii_write(phy_addr[index],0x09,0x0000); /* advertisement no 1000M */ -+ mii_write(phy_addr[index],0x09,0x0300); /* advertisement 1000M full duplex, pause capable on */ -+#endif -+ } -+ -+ mii_write(phy_addr[index],0x00,0x1200); /* Enable and Restart Auto-Negotiation */ -+ mii_write(phy_addr[index],0x18,0x0041); /* Enable Active led */ -+ while (((reg_val=mii_read(phy_addr[index],0x01)) & 0x00000004)!=0x04) -+ { -+ i++; -+ if (i > 30) -+ { -+ break; -+ } -+ msleep(100); -+ } -+ if (i>30) -+ { -+ pre_phy_status[index] = LINK_DOWN; -+ clear_bit(__LINK_STATE_START, &dev->state); -+ netif_stop_queue(dev); -+ storlink_ctl.link = 0; -+ printk("Link Down (%04x) ",reg_val); -+ } -+ else -+ { -+ pre_phy_status[index] = LINK_UP; -+ set_bit(__LINK_STATE_START, &dev->state); -+ netif_wake_queue(dev); -+ storlink_ctl.link = 1; -+ printk("Link Up (%04x) ",reg_val); -+ } -+ -+ status.bits32 = 0; -+ reg_val = mii_read(phy_addr[index],10); -+ printk("reg_val0 = %x \n",reg_val); -+ if ((reg_val & 0x0800) == 0x0800) -+ { -+ status.bits.duplex = 1; -+ status.bits.speed = 2; -+ printk(" 1000M/Full \n"); -+ } -+ else if ((reg_val & 0x0400) == 0x0400) -+ { -+ status.bits.duplex = 0; -+ status.bits.speed = 2; -+ printk(" 1000M/Half \n"); -+ } -+ else -+ { -+ reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5; -+ printk("reg_val1 = %x \n",reg_val); -+ if ((reg_val & 0x08)==0x08) /* 100M full duplex */ -+ { -+ status.bits.duplex = 1; -+ status.bits.speed = 1; -+ printk(" 100M/Full \n"); -+ } -+ else if ((reg_val & 0x04)==0x04) /* 100M half duplex */ -+ { -+ status.bits.duplex = 0; -+ status.bits.speed = 1; -+ printk(" 100M/Half \n"); -+ } -+ else if ((reg_val & 0x02)==0x02) /* 10M full duplex */ -+ { -+ status.bits.duplex = 1; -+ status.bits.speed = 0; -+ printk(" 10M/Full \n"); -+ } -+ else if ((reg_val & 0x01)==0x01) /* 10M half duplex */ -+ { -+ status.bits.duplex = 0; -+ status.bits.speed = 0; -+ printk(" 100M/Half \n"); -+ } -+ } -+ -+ reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5; -+ if ((reg_val & 0x20)==0x20) -+ { -+ flow_control_enable[index] = 1; -+ printk("Flow Control Enable. \n"); -+ } -+ else -+ { -+ flow_control_enable[index] = 0; -+ printk("Flow Control Disable. \n"); -+ } -+ full_duplex = status.bits.duplex; -+ speed = status.bits.speed; -+} -+ -+static void gmac_get_phy_status(struct net_device *dev) -+{ -+ GMAC_CONFIG0_T config0,config0_mask; -+ GMAC_STATUS_T status; -+ unsigned int reg_val; -+ unsigned int index; -+ -+ index = gmac_select_interface(dev); -+ -+ status.bits32 = 0; -+ status.bits.phy_mode = 1; -+ -+#ifdef CONFIG_SL3516_ASIC -+ status.bits.mii_rmii = 2; /* default value for ASIC version */ -+// status.bits.speed = 1; -+#else -+ if (index==0) -+ status.bits.mii_rmii = 0; -+ else -+ status.bits.mii_rmii = 2; -+#endif -+ -+ /* read PHY status register */ -+ reg_val = mii_read(phy_addr[index],0x01); -+ if ((reg_val & 0x0024) == 0x0024) /* link is established and auto_negotiate process completed */ -+ { -+ /* read PHY Auto-Negotiation Link Partner Ability Register */ -+ reg_val = mii_read(phy_addr[index],10); -+ if ((reg_val & 0x0800) == 0x0800) -+ { -+ status.bits.mii_rmii = 3; /* RGMII 1000Mbps mode */ -+ status.bits.duplex = 1; -+ status.bits.speed = 2; -+ } -+ else if ((reg_val & 0x0400) == 0x0400) -+ { -+ status.bits.mii_rmii = 3; /* RGMII 1000Mbps mode */ -+ status.bits.duplex = 0; -+ status.bits.speed = 2; -+ } -+ else -+ { -+ reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5; -+ if ((reg_val & 0x08)==0x08) /* 100M full duplex */ -+ { -+ status.bits.mii_rmii = 2; /* RGMII 10/100Mbps mode */ -+ status.bits.duplex = 1; -+ status.bits.speed = 1; -+ } -+ else if ((reg_val & 0x04)==0x04) /* 100M half duplex */ -+ { -+ status.bits.mii_rmii = 2; /* RGMII 10/100Mbps mode */ -+ status.bits.duplex = 0; -+ status.bits.speed = 1; -+ } -+ else if ((reg_val & 0x02)==0x02) /* 10M full duplex */ -+ { -+ status.bits.mii_rmii = 2; /* RGMII 10/100Mbps mode */ -+ status.bits.duplex = 1; -+ status.bits.speed = 0; -+ } -+ else if ((reg_val & 0x01)==0x01) /* 10M half duplex */ -+ { -+ status.bits.mii_rmii = 2; /* RGMII 10/100Mbps mode */ -+ status.bits.duplex = 0; -+ status.bits.speed = 0; -+ } -+ } -+ status.bits.link = LINK_UP; /* link up */ -+ netif_wake_queue(dev); -+ -+ reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5; -+ if ((reg_val & 0x20)==0x20) -+ { -+ if (flow_control_enable[index] == 0) -+ { -+ config0.bits32 = 0; -+ config0_mask.bits32 = 0; -+ config0.bits.tx_fc_en = 1; /* enable tx flow control */ -+ config0.bits.rx_fc_en = 1; /* enable rx flow control */ -+ config0_mask.bits.tx_fc_en = 1; -+ config0_mask.bits.rx_fc_en = 1; -+ gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32); -+// printk("eth%d Flow Control Enable. \n",index); -+ } -+ flow_control_enable[index] = 1; -+ } -+ else -+ { -+ if (flow_control_enable[index] == 1) -+ { -+ config0.bits32 = 0; -+ config0_mask.bits32 = 0; -+ config0.bits.tx_fc_en = 0; /* disable tx flow control */ -+ config0.bits.rx_fc_en = 0; /* disable rx flow control */ -+ config0_mask.bits.tx_fc_en = 1; -+ config0_mask.bits.rx_fc_en = 1; -+ gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32); -+// printk("eth%d Flow Control Disable. \n",index); -+ } -+ flow_control_enable[index] = 0; -+ } -+ -+ if (pre_phy_status[index] == LINK_DOWN) -+ { -+ gmac_enable_tx_rx(dev); -+ pre_phy_status[index] = LINK_UP; -+ set_bit(__LINK_STATE_START, &dev->state); -+ storlink_ctl.link = 1; -+// printk("eth%d Link Up ...\n",index); -+ } -+ } -+ else -+ { -+ status.bits.link = LINK_DOWN; /* link down */ -+ netif_stop_queue(dev); -+ flow_control_enable[index] = 0; -+ storlink_ctl.link = 0; -+ if (pre_phy_status[index] == LINK_UP) -+ { -+ gmac_disable_tx_rx(dev); -+ pre_phy_status[index] = LINK_DOWN; -+ clear_bit(__LINK_STATE_START, &dev->state); -+// printk("eth%d Link Down ...\n",index); -+ } -+ -+ } -+ -+ reg_val = gmac_read_reg(gmac_base_addr[index] + GMAC_STATUS); -+ if (reg_val != status.bits32) -+ { -+ gmac_write_reg(gmac_base_addr[index] + GMAC_STATUS,status.bits32,0x0000007f); -+ } -+} -+ -+/***************************************/ -+/* define GPIO module base address */ -+/***************************************/ -+#define GPIO_BASE_ADDR (IO_ADDRESS(SL2312_GPIO_BASE)) -+ -+/* define GPIO pin for MDC/MDIO */ -+ -+// for gemini ASIC -+#ifdef CONFIG_SL3516_ASIC -+#define H_MDC_PIN 22 -+#define H_MDIO_PIN 21 -+#define G_MDC_PIN 22 -+#define G_MDIO_PIN 21 -+#else -+#define H_MDC_PIN 3 -+#define H_MDIO_PIN 2 -+#define G_MDC_PIN 0 -+#define G_MDIO_PIN 1 -+#endif -+ -+//#define GPIO_MDC 0x80000000 -+//#define GPIO_MDIO 0x00400000 -+ -+static unsigned int GPIO_MDC = 0; -+static unsigned int GPIO_MDIO = 0; -+static unsigned int GPIO_MDC_PIN = 0; -+static unsigned int GPIO_MDIO_PIN = 0; -+ -+// For PHY test definition!! -+#define LPC_EECK 0x02 -+#define LPC_EDIO 0x04 -+#define LPC_GPIO_SET 3 -+#define LPC_BASE_ADDR IO_ADDRESS(IT8712_IO_BASE) -+#define inb_gpio(x) inb(LPC_BASE_ADDR + IT8712_GPIO_BASE + x) -+#define outb_gpio(x, y) outb(y, LPC_BASE_ADDR + IT8712_GPIO_BASE + x) -+ -+enum GPIO_REG -+{ -+ GPIO_DATA_OUT = 0x00, -+ GPIO_DATA_IN = 0x04, -+ GPIO_PIN_DIR = 0x08, -+ GPIO_BY_PASS = 0x0c, -+ GPIO_DATA_SET = 0x10, -+ GPIO_DATA_CLEAR = 0x14, -+}; -+/***********************/ -+/* MDC : GPIO[31] */ -+/* MDIO: GPIO[22] */ -+/***********************/ -+ -+/*************************************************** -+* All the commands should have the frame structure: -+*

-+****************************************************/
-+
-+/*****************************************************************
-+* Inject a bit to NWay register through CSR9_MDC,MDIO
-+*******************************************************************/
-+void mii_serial_write(char bit_MDO) // write data into mii PHY
-+{
-+#if 0 //def CONFIG_SL2312_LPC_IT8712
-+	unsigned char iomode,status;
-+
-+	iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
-+	iomode |= (LPC_EECK|LPC_EDIO) ;				// Set EECK,EDIO,EECS output
-+	LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
-+
-+	if(bit_MDO)
-+	{
-+		status = inb_gpio( LPC_GPIO_SET);
-+		status |= LPC_EDIO ;		//EDIO high
-+		outb_gpio(LPC_GPIO_SET, status);
-+	}
-+	else
-+	{
-+		status = inb_gpio( LPC_GPIO_SET);
-+		status &= ~(LPC_EDIO) ;		//EDIO low
-+		outb_gpio(LPC_GPIO_SET, status);
-+	}
-+
-+	status |= LPC_EECK ;		//EECK high
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	status &= ~(LPC_EECK) ;		//EECK low
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+#else
-+    unsigned int addr;
-+    unsigned int value;
-+
-+    addr = GPIO_BASE_ADDR + GPIO_PIN_DIR;
-+    value = readl(addr) | GPIO_MDC | GPIO_MDIO; /* set MDC/MDIO Pin to output */
-+    writel(value,addr);
-+    if(bit_MDO)
-+    {
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+        writel(GPIO_MDIO,addr); /* set MDIO to 1 */
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+        writel(GPIO_MDC,addr); /* set MDC to 1 */
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+        writel(GPIO_MDC,addr); /* set MDC to 0 */
-+    }
-+    else
-+    {
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+        writel(GPIO_MDIO,addr); /* set MDIO to 0 */
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+        writel(GPIO_MDC,addr); /* set MDC to 1 */
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+        writel(GPIO_MDC,addr); /* set MDC to 0 */
-+    }
-+
-+#endif
-+}
-+
-+/**********************************************************************
-+* read a bit from NWay register through CSR9_MDC,MDIO
-+***********************************************************************/
-+unsigned int mii_serial_read(void) // read data from mii PHY
-+{
-+#if 0 //def CONFIG_SL2312_LPC_IT8712
-+  	unsigned char iomode,status;
-+	unsigned int value ;
-+
-+	iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
-+	iomode &= ~(LPC_EDIO) ;		// Set EDIO input
-+	iomode |= (LPC_EECK) ;		// Set EECK,EECS output
-+	LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
-+
-+	status = inb_gpio( LPC_GPIO_SET);
-+	status |= LPC_EECK ;		//EECK high
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	status &= ~(LPC_EECK) ;		//EECK low
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	value = inb_gpio( LPC_GPIO_SET);
-+
-+	value = value>>2 ;
-+	value &= 0x01;
-+
-+	return value ;
-+
-+#else
-+    unsigned int *addr;
-+    unsigned int value;
-+
-+    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_PIN_DIR);
-+    value = readl(addr) & ~GPIO_MDIO; //0xffbfffff;   /* set MDC to output and MDIO to input */
-+    writel(value,addr);
-+
-+    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_SET);
-+    writel(GPIO_MDC,addr); /* set MDC to 1 */
-+    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+    writel(GPIO_MDC,addr); /* set MDC to 0 */
-+
-+    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_IN);
-+    value = readl(addr);
-+    value = (value & (1<> GPIO_MDIO_PIN;
-+    return(value);
-+
-+#endif
-+}
-+
-+/***************************************
-+* preamble + ST
-+***************************************/
-+void mii_pre_st(void)
-+{
-+    unsigned char i;
-+
-+    for(i=0;i<32;i++) // PREAMBLE
-+        mii_serial_write(1);
-+    mii_serial_write(0); // ST
-+    mii_serial_write(1);
-+}
-+
-+
-+/******************************************
-+* Read MII register
-+* phyad -> physical address
-+* regad -> register address
-+***************************************** */
-+unsigned int mii_read(unsigned char phyad,unsigned char regad)
-+{
-+    unsigned int i,value;
-+    unsigned int bit;
-+
-+    if (phyad == GPHY_ADDR)
-+    {
-+        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
-+        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
-+    }
-+    else
-+    {
-+        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
-+        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
-+    }
-+    GPIO_MDC = (1<>(4-i)) & 0x01) ? 1 :0 ;
-+        mii_serial_write(bit);
-+    }
-+
-+    for (i=0;i<5;i++) { // REGAD
-+        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
-+        mii_serial_write(bit);
-+    }
-+
-+    mii_serial_read(); // TA_Z
-+//    if((bit=mii_serial_read()) !=0 ) // TA_0
-+//    {
-+//        return(0);
-+//    }
-+    value=0;
-+    for (i=0;i<16;i++) { // READ DATA
-+        bit=mii_serial_read();
-+        value += (bit<<(15-i)) ;
-+    }
-+
-+    mii_serial_write(0); // dumy clock
-+    mii_serial_write(0); // dumy clock
-+//printk("%s: phy_addr=%x reg_addr=%x value=%x \n",__func__,phyad,regad,value);
-+    return(value);
-+}
-+
-+/******************************************
-+* Write MII register
-+* phyad -> physical address
-+* regad -> register address
-+* value -> value to be write
-+***************************************** */
-+void mii_write(unsigned char phyad,unsigned char regad,unsigned int value)
-+{
-+    unsigned int i;
-+    char bit;
-+
-+printk("%s: phy_addr=%x reg_addr=%x value=%x \n",__func__,phyad,regad,value);
-+    if (phyad == GPHY_ADDR)
-+    {
-+        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
-+        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
-+    }
-+    else
-+    {
-+        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
-+        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
-+    }
-+    GPIO_MDC = (1<>(4-i)) & 0x01) ? 1 :0 ;
-+        mii_serial_write(bit);
-+    }
-+
-+    for (i=0;i<5;i++) { // REGAD
-+        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
-+        mii_serial_write(bit);
-+    }
-+    mii_serial_write(1); // TA_1
-+    mii_serial_write(0); // TA_0
-+
-+    for (i=0;i<16;i++) { // OUT DATA
-+        bit= ((value>>(15-i)) & 0x01) ? 1 : 0 ;
-+        mii_serial_write(bit);
-+    }
-+    mii_serial_write(0); // dumy clock
-+    mii_serial_write(0); // dumy clock
-+}
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+/*				NOTES
-+ *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
-+ *
-+ *               Start  OP	    *
-+ *     Function   Bit  Code  Address**  Data     Description
-+ *     -------------------------------------------------------------------
-+ *     READ        1    10   A7 - A0             Reads data stored in memory,
-+ *                                               starting at specified address
-+ *     EWEN        1    00   11XXXXXX            Write enable must precede
-+ *                                               all programming modes
-+ *     ERASE       1    11   A7 - A0             Erase register A7A6A5A4A3A2A1A0
-+ *     WRITE       1    01   A7 - A0   D15 - D0  Writes register
-+ *     ERAL        1    00   10XXXXXX            Erase all registers
-+ *     WRAL        1    00   01XXXXXX  D15 - D0  Writes to all registers
-+ *     EWDS        1    00   00XXXXXX            Disables all programming
-+ *                                               instructions
-+ *    *Note: A value of X for address is a don't care condition.
-+ *    **Note: There are 8 address bits for the 93C56/66 chips unlike
-+ *	      the 93C46/26/06 chips which have 6 address bits.
-+ *
-+ *   The 93Cx6 has a four wire interface: clock, chip select, data in, and
-+ *   data out.While the ADM6996 uning three interface: clock, chip select,and data line.
-+ *   The input and output are the same pin. ADM6996 can only recognize the write cmd.
-+ *   In order to perform above functions, you need
-+ *   1. to enable the chip select .
-+ *   2. send one clock of dummy clock
-+ *   3. send start bit and opcode
-+ *   4. send 8 bits address and 16 bits data
-+ *   5. to disable the chip select.
-+ *							Jason Lee 2003/07/30
-+ */
-+
-+/***************************************/
-+/* define GPIO module base address     */
-+/***************************************/
-+#define GPIO_EECS	     0x00400000		/*   EECS: GPIO[22]   */
-+//#define GPIO_MOSI	     0x20000000         /*   EEDO: GPIO[29]   send to 6996*/
-+#define GPIO_MISO	     0x40000000         /*   EEDI: GPIO[30]   receive from 6996*/
-+#define GPIO_EECK	     0x80000000         /*   EECK: GPIO[31]   */
-+
-+#define ADM_EECS		0x01
-+#define ADM_EECK		0x02
-+#define ADM_EDIO		0x04
-+/*************************************************************
-+* SPI protocol for ADM6996 control
-+**************************************************************/
-+#define SPI_OP_LEN	     0x03		// the length of start bit and opcode
-+#define SPI_OPWRITE	     0X05		// write
-+#define SPI_OPREAD	     0X06		// read
-+#define SPI_OPERASE	     0X07		// erase
-+#define SPI_OPWTEN	     0X04		// write enable
-+#define SPI_OPWTDIS	     0X04		// write disable
-+#define SPI_OPERSALL	     0X04		// erase all
-+#define SPI_OPWTALL	     0X04		// write all
-+
-+#define SPI_ADD_LEN	     8			// bits of Address
-+#define SPI_DAT_LEN	     16			// bits of Data
-+#define ADM6996_PORT_NO	     6			// the port number of ADM6996
-+#define ADM6999_PORT_NO	     9			// the port number of ADM6999
-+#ifdef CONFIG_ADM_6996
-+	#define ADM699X_PORT_NO		ADM6996_PORT_NO
-+#endif
-+#ifdef CONFIG_ADM_6999
-+	#define ADM699X_PORT_NO		ADM6999_PORT_NO
-+#endif
-+#define LPC_GPIO_SET		3
-+#define LPC_BASE_ADDR			IO_ADDRESS(IT8712_IO_BASE)
-+
-+extern int it8712_exist;
-+
-+#define inb_gpio(x)			inb(LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
-+#define outb_gpio(x, y)		outb(y, LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
-+
-+/****************************************/
-+/*	Function Declare		*/
-+/****************************************/
-+/*
-+void SPI_write(unsigned char addr,unsigned int value);
-+unsigned int SPI_read(unsigned char table,unsigned char addr);
-+void SPI_write_bit(char bit_EEDO);
-+unsigned int SPI_read_bit(void);
-+void SPI_default(void);
-+void SPI_reset(unsigned char rstype,unsigned char port_cnt);
-+void SPI_pre_st(void);
-+void SPI_CS_enable(unsigned char enable);
-+void SPI_Set_VLAN(unsigned char LAN,unsigned int port_mask);
-+void SPI_Set_tag(unsigned int port,unsigned tag);
-+void SPI_Set_PVID(unsigned int PVID,unsigned int port_mask);
-+void SPI_mac_lock(unsigned int port, unsigned char lock);
-+void SPI_get_port_state(unsigned int port);
-+void SPI_port_enable(unsigned int port,unsigned char enable);
-+
-+void SPI_get_status(unsigned int port);
-+*/
-+
-+struct PORT_CONFIG
-+{
-+	unsigned char auto_negotiation;	// 0:Disable	1:Enable
-+	unsigned char speed;		// 0:10M	1:100M
-+	unsigned char duplex;		// 0:Half	1:Full duplex
-+	unsigned char Tag;		// 0:Untag	1:Tag
-+	unsigned char port_disable;	// 0:port enable	1:disable
-+	unsigned char pvid;		// port VLAN ID 0001
-+	unsigned char mdix;		// Crossover judgement. 0:Disable 1:Enable
-+	unsigned char mac_lock;		// MAC address Lock 0:Disable 1:Enable
-+};
-+
-+struct PORT_STATUS
-+{
-+	unsigned char link;		// 0:not link	1:link established
-+	unsigned char speed;		// 0:10M	1:100M
-+	unsigned char duplex;		// 0:Half	1:Full duplex
-+	unsigned char flow_ctl;		// 0:flow control disable 1:enable
-+	unsigned char mac_lock;		// MAC address Lock 0:Disable 1:Enable
-+	unsigned char port_disable;	// 0:port enable	1:disable
-+
-+	// Serial Management
-+	unsigned long rx_pac_count;		//receive packet count
-+	unsigned long rx_pac_byte;		//receive packet byte count
-+	unsigned long tx_pac_count;		//transmit packet count
-+	unsigned long tx_pac_byte;		//transmit packet byte count
-+	unsigned long collision_count;		//error count
-+	unsigned long error_count ;
-+
-+	unsigned long rx_pac_count_overflow;		//overflow flag
-+	unsigned long rx_pac_byte_overflow;
-+	unsigned long tx_pac_count_overflow;
-+	unsigned long tx_pac_byte_overflow;
-+	unsigned long collision_count_overflow;
-+	unsigned long error_count_overflow;
-+};
-+
-+struct PORT_CONFIG port_config[ADM699X_PORT_NO];	// 0~3:LAN , 4:WAN , 5:MII
-+static struct PORT_STATUS port_state[ADM699X_PORT_NO];
-+
-+/******************************************
-+* SPI_write
-+* addr -> Write Address
-+* value -> value to be write
-+***************************************** */
-+void SPI_write(unsigned char addr,unsigned int value)
-+{
-+	int     i;
-+	char    bit;
-+#ifdef CONFIG_IT8712_GPIO
-+	char    status;
-+#else
-+    int     ad1;
-+#endif
-+
-+#ifdef CONFIG_IT8712_GPIO
-+	status = inb_gpio(LPC_GPIO_SET);
-+	status &= ~(ADM_EDIO) ;		//EDIO low
-+	outb_gpio(LPC_GPIO_SET, status);
-+#else
-+   	ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+	writel(GPIO_MISO,ad1); /* set MISO to 0 */
-+#endif
-+	SPI_CS_enable(1);
-+
-+	SPI_write_bit(0);       //dummy clock
-+
-+	//send write command (0x05)
-+	for(i=SPI_OP_LEN-1;i>=0;i--)
-+	{
-+		bit = (SPI_OPWRITE>>i)& 0x01;
-+		SPI_write_bit(bit);
-+	}
-+	// send 8 bits address (MSB first, LSB last)
-+	for(i=SPI_ADD_LEN-1;i>=0;i--)
-+	{
-+		bit = (addr>>i)& 0x01;
-+		SPI_write_bit(bit);
-+	}
-+	// send 16 bits data (MSB first, LSB last)
-+	for(i=SPI_DAT_LEN-1;i>=0;i--)
-+	{
-+		bit = (value>>i)& 0x01;
-+		SPI_write_bit(bit);
-+	}
-+
-+	SPI_CS_enable(0);	// CS low
-+
-+	for(i=0;i<0xFFF;i++) ;
-+#ifdef CONFIG_IT8712_GPIO
-+	status = inb_gpio(LPC_GPIO_SET);
-+	status &= ~(ADM_EDIO) ;		//EDIO low
-+	outb_gpio(LPC_GPIO_SET, status);
-+#else
-+   	ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+	writel(GPIO_MISO,ad1); /* set MISO to 0 */
-+#endif
-+}
-+
-+
-+/************************************
-+* SPI_write_bit
-+* bit_EEDO -> 1 or 0 to be written
-+************************************/
-+void SPI_write_bit(char bit_EEDO)
-+{
-+#ifdef CONFIG_IT8712_GPIO
-+	unsigned char iomode,status;
-+
-+	iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
-+	iomode |= (ADM_EECK|ADM_EDIO|ADM_EECS) ;				// Set EECK,EDIO,EECS output
-+	LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
-+
-+	if(bit_EEDO)
-+	{
-+		status = inb_gpio( LPC_GPIO_SET);
-+		status |= ADM_EDIO ;		//EDIO high
-+		outb_gpio(LPC_GPIO_SET, status);
-+	}
-+	else
-+	{
-+		status = inb_gpio( LPC_GPIO_SET);
-+		status &= ~(ADM_EDIO) ;		//EDIO low
-+		outb_gpio(LPC_GPIO_SET, status);
-+	}
-+
-+	status |= ADM_EECK ;		//EECK high
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	status &= ~(ADM_EECK) ;		//EECK low
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+#else
-+	unsigned int addr;
-+	unsigned int value;
-+
-+	addr = (GPIO_BASE_ADDR + GPIO_PIN_DIR);
-+	value = readl(addr) |GPIO_EECK |GPIO_MISO ;   /* set EECK/MISO Pin to output */
-+	writel(value,addr);
-+	if(bit_EEDO)
-+	{
-+		addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+		writel(GPIO_MISO,addr); /* set MISO to 1 */
-+		writel(GPIO_EECK,addr); /* set EECK to 1 */
-+		addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+		writel(GPIO_EECK,addr); /* set EECK to 0 */
-+	}
-+	else
-+	{
-+		addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+		writel(GPIO_MISO,addr); /* set MISO to 0 */
-+		addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+		writel(GPIO_EECK,addr); /* set EECK to 1 */
-+		addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+		writel(GPIO_EECK,addr); /* set EECK to 0 */
-+	}
-+
-+	return ;
-+#endif
-+}
-+
-+/**********************************************************************
-+* read a bit from ADM6996 register
-+***********************************************************************/
-+unsigned int SPI_read_bit(void) // read data from
-+{
-+#ifdef CONFIG_IT8712_GPIO
-+	unsigned char iomode,status;
-+	unsigned int value ;
-+
-+	iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
-+	iomode &= ~(ADM_EDIO) ;		// Set EDIO input
-+	iomode |= (ADM_EECS|ADM_EECK) ;		// Set EECK,EECS output
-+	LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
-+
-+	status = inb_gpio( LPC_GPIO_SET);
-+	status |= ADM_EECK ;		//EECK high
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	status &= ~(ADM_EECK) ;		//EECK low
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	value = inb_gpio( LPC_GPIO_SET);
-+
-+	value = value>>2 ;
-+	value &= 0x01;
-+
-+	return value ;
-+#else
-+	unsigned int addr;
-+	unsigned int value;
-+
-+	addr = (GPIO_BASE_ADDR + GPIO_PIN_DIR);
-+	value = readl(addr) & (~GPIO_MISO);   // set EECK to output and MISO to input
-+	writel(value,addr);
-+
-+	addr =(GPIO_BASE_ADDR + GPIO_DATA_SET);
-+	writel(GPIO_EECK,addr); // set EECK to 1
-+	addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+	writel(GPIO_EECK,addr); // set EECK to 0
-+
-+	addr = (GPIO_BASE_ADDR + GPIO_DATA_IN);
-+	value = readl(addr) ;
-+	value = value >> 30;
-+	return value ;
-+#endif
-+}
-+
-+/******************************************
-+* SPI_default
-+* EEPROM content default value
-+*******************************************/
-+void SPI_default(void)
-+{
-+	int i;
-+#ifdef CONFIG_ADM_6999
-+	SPI_write(0x11,0xFF30);
-+	for(i=1;i<8;i++)
-+		SPI_write(i,0x840F);
-+
-+	SPI_write(0x08,0x880F);			//port 8 Untag, PVID=2
-+	SPI_write(0x09,0x881D);			//port 9 Tag, PVID=2 ,10M
-+	SPI_write(0x14,0x017F);			//Group 0~6,8 as VLAN 1
-+	SPI_write(0x15,0x0180);			//Group 7,8 as VLAN 2
-+#endif
-+
-+#ifdef CONFIG_ADM_6996
-+	SPI_write(0x11,0xFF30);
-+	SPI_write(0x01,0x840F);			//port 0~3 Untag ,PVID=1 ,100M ,duplex
-+	SPI_write(0x03,0x840F);
-+	SPI_write(0x05,0x840F);
-+	SPI_write(0x07,0x840F);
-+	SPI_write(0x08,0x880F);			//port 4 Untag, PVID=2
-+	SPI_write(0x09,0x881D);			//port 5 Tag, PVID=2 ,10M
-+	SPI_write(0x14,0x0155);			//Group 0~3,5 as VLAN 1
-+	SPI_write(0x15,0x0180);			//Group 4,5 as VLAN 2
-+
-+#endif
-+
-+	for(i=0x16;i<=0x22;i++)
-+		SPI_write((unsigned char)i,0x0000);		// clean VLAN¡@map 3~15
-+
-+	for (i=0;i reset type
-+*	    0:reset all count for 'port_cnt' port
-+*	    1:reset specified count 'port_cnt'
-+* port_cnt   ->  port number or counter index
-+***************************************************/
-+void SPI_reset(unsigned char rstype,unsigned char port_cnt)
-+{
-+
-+	int i;
-+#ifdef CONFIG_IT8712_GPIO
-+    char status;
-+#else
-+	int ad1;
-+#endif
-+	char bit;
-+
-+#ifdef CONFIG_IT8712_GPIO
-+	status = inb_gpio(LPC_GPIO_SET);
-+	status &= ~(ADM_EDIO) ;		//EDIO low
-+	outb_gpio(LPC_GPIO_SET, status);
-+#else
-+   	ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+	writel(GPIO_MISO,ad1); /* set MISO to 0 */
-+#endif
-+
-+	SPI_CS_enable(0);	// CS low
-+
-+	SPI_pre_st(); // PRE+ST
-+	SPI_write_bit(0); // OP
-+	SPI_write_bit(1);
-+
-+	SPI_write_bit(1);		// Table select, must be 1 -> reset Counter
-+
-+	SPI_write_bit(0);		// Device Address
-+	SPI_write_bit(0);
-+
-+	rstype &= 0x01;
-+	SPI_write_bit(rstype);		// Reset type 0:clear dedicate port's all counters 1:clear dedicate counter
-+
-+	for (i=5;i>=0;i--) 		// port or cnt index
-+	{
-+		bit = port_cnt >> i ;
-+		bit &= 0x01 ;
-+		SPI_write_bit(bit);
-+	}
-+
-+	SPI_write_bit(0); 		// dumy clock
-+	SPI_write_bit(0); 		// dumy clock
-+
-+#ifdef CONFIG_IT8712_GPIO
-+	status = inb_gpio(LPC_GPIO_SET);
-+	status &= ~(ADM_EDIO) ;		//EDIO low
-+	outb_gpio(LPC_GPIO_SET, status);
-+#else
-+   	ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+	writel(GPIO_MISO,ad1); /* set MISO to 0 */
-+#endif
-+}
-+
-+/*****************************************************
-+* SPI_pre_st
-+* preambler: 32 bits '1'   start bit: '01'
-+*****************************************************/
-+void SPI_pre_st(void)
-+{
-+	int i;
-+
-+	for(i=0;i<32;i++) // PREAMBLE
-+		SPI_write_bit(1);
-+	SPI_write_bit(0); // ST
-+	SPI_write_bit(1);
-+}
-+
-+
-+/***********************************************************
-+* SPI_CS_enable
-+* before access ,you have to enable Chip Select. (pull high)
-+* When fisish, you should pull low !!
-+*************************************************************/
-+void SPI_CS_enable(unsigned char enable)
-+{
-+#ifdef CONFIG_IT8712_GPIO
-+
-+	unsigned char iomode,status;
-+
-+	iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
-+	iomode |= (ADM_EECK|ADM_EDIO|ADM_EECS) ;				// Set EECK,EDIO,EECS output
-+	LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
-+
-+
-+	status = inb_gpio( LPC_GPIO_SET);
-+	if(enable)
-+		status |= ADM_EECS ;		//EECS high
-+	else
-+		status &= ~(ADM_EECS) ;	//EECS low
-+
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+
-+	status |= ADM_EECK ;		//EECK high
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	status &= ~(ADM_EECK) ;		//EECK low
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+#else
-+	unsigned int addr,value;
-+
-+	addr = (GPIO_BASE_ADDR + GPIO_PIN_DIR);
-+	value = readl(addr) |GPIO_EECS |GPIO_EECK;   /* set EECS/EECK Pin to output */
-+	writel(value,addr);
-+
-+	if(enable)
-+	{
-+		addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+		writel(GPIO_EECS,addr); /* set EECS to 1 */
-+
-+	}
-+	else
-+	{
-+		addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+		writel(GPIO_EECS,addr); /* set EECS to 0 */
-+		addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+		writel(GPIO_EECK,addr); /* set EECK to 1 */	// at least one clock after CS low
-+		addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+		writel(GPIO_EECK,addr); /* set EECK to 0 */
-+	}
-+#endif
-+}
-+
-+/*********************************************************
-+* SPI_Set_VLAN: group ports as VLAN
-+* LAN  -> VLAN number : 0~16
-+* port_mask -> ports which would group as LAN
-+* 	       ex. 0x03 = 0000 0011
-+*			port 0 and port 1
-+*********************************************************/
-+void SPI_Set_VLAN(unsigned char LAN,unsigned int port_mask)
-+{
-+	unsigned int i,value=0;
-+	unsigned reg_add = 0x13 + LAN ;
-+
-+	for(i=0;i>= 1;
-+	}
-+
-+	SPI_write(reg_add,value);
-+}
-+
-+
-+/*******************************************
-+* SPI_Set_tag
-+* port -> port number to set tag or untag
-+* tag  -> 0/set untag,  1/set tag
-+* In general, tag is for MII port. LAN and
-+* WAN port is configed as untag!!
-+********************************************/
-+void SPI_Set_tag(unsigned int port,unsigned tag)
-+{
-+	unsigned int regadd,value;
-+
-+	// mapping port's register !! (0,1,2,3,4,5) ==> (1,3,5,7,8,9)
-+	if(port<=3)
-+		regadd=2*port+1;
-+	else if(port==4) regadd = 8 ;
-+	else regadd = 9 ;
-+
-+
-+	value = SPI_read(0,regadd);		//read original setting
-+
-+	if(tag)
-+		value |= 0x0010 ;		// set tag
-+	else
-+		value &= 0xFFEF ;		// set untag
-+
-+	SPI_write(regadd,value);		// write back!!
-+}
-+
-+/************************************************
-+* SPI_Set_PVID
-+* PVID -> PVID number :
-+* port_mask -> ports which would group as LAN
-+* 	       ex. 0x0F = 0000 1111 ==> port 0~3
-+************************************************/
-+void SPI_Set_PVID(unsigned int PVID,unsigned int port_mask)
-+{
-+	unsigned int i,value=0;
-+
-+	PVID &= 0x000F ;
-+
-+	for(i=0;i>= 1;
-+	}
-+}
-+
-+
-+/************************************************
-+* SPI_get_PVID
-+* port -> which ports to VID
-+************************************************/
-+unsigned int SPI_Get_PVID(unsigned int port)
-+{
-+	unsigned int value=0;
-+
-+	if (port>=ADM6996_PORT_NO)
-+		return 0;
-+
-+	switch(port)
-+	{
-+		case 0:
-+			value = SPI_read(0,0x01);	// read original value
-+			value &= 0x3C00 ;		// get VID
-+			value = value >> 10 ;		// Shift
-+			break;
-+		case 1:
-+			value = SPI_read(0,0x03);
-+			value &= 0x3C00 ;
-+			value = value >> 10 ;
-+			break;
-+		case 2:
-+			value = SPI_read(0,0x05);
-+			value &= 0x3C00 ;
-+			value = value >> 10 ;
-+			break;
-+		case 3:
-+			value = SPI_read(0,0x07);
-+			value &= 0x3C00 ;
-+			value = value >> 10 ;
-+			break;
-+		case 4:
-+			value = SPI_read(0,0x08);
-+			value &= 0x3C00 ;
-+			value = value >> 10 ;
-+			break;
-+		case 5:
-+			value = SPI_read(0,0x09);
-+			value &= 0x3C00 ;
-+			value = value >> 10 ;
-+			break;
-+	}
-+	return value ;
-+}
-+
-+
-+/**********************************************
-+* SPI_mac_clone
-+* port -> the port which will lock or unlock
-+* lock -> 0/the port will be unlock
-+*	  1/the port will be locked
-+**********************************************/
-+void SPI_mac_lock(unsigned int port, unsigned char lock)
-+{
-+	unsigned int i,value=0;
-+
-+	value = SPI_read(0,0x12);		// read original
-+
-+	for(i=0;i 0: if DA == pause then drop and stop mac learning
-+*	     1: if DA == pause ,then forward it
-+***************************************************/
-+void SPI_pause_cmd_forward(unsigned char forward)
-+{
-+	unsigned int value=0;
-+
-+	value = SPI_read(0,0x2C);		// read original setting
-+	if(forward)
-+		value |= 0x2000;		// set bit[13] '1'
-+	else
-+		value &= 0xDFFF;		// set bit[13] '0'
-+
-+	SPI_write(0x2C,value);
-+
-+}
-+
-+
-+/************************************************
-+* SPI_read
-+* table -> which table to be read: 1/count  0/EEPROM
-+* addr  -> Address to be read
-+* return : Value of the register
-+*************************************************/
-+unsigned int SPI_read(unsigned char table,unsigned char addr)
-+{
-+	int i ;
-+	unsigned int value=0;
-+	unsigned int bit;
-+#ifdef CONFIG_IT8712_GPIO
-+	unsigned char status;
-+#else
-+    unsigned int ad1;
-+#endif
-+
-+#ifdef CONFIG_IT8712_GPIO
-+	status = inb_gpio(LPC_GPIO_SET);
-+	status &= ~(ADM_EDIO) ;		//EDIO low
-+	outb_gpio(LPC_GPIO_SET, status);
-+#else
-+   	ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+	writel(GPIO_MISO,ad1); /* set MISO to 0 */
-+#endif
-+
-+	SPI_CS_enable(0);
-+
-+	SPI_pre_st(); // PRE+ST
-+	SPI_write_bit(1); // OPCODE '10' for read
-+	SPI_write_bit(0);
-+
-+	(table==1) ? SPI_write_bit(1) : SPI_write_bit(0) ;	// table select
-+
-+	SPI_write_bit(0);		// Device Address
-+	SPI_write_bit(0);
-+
-+
-+	// send 7 bits address to be read
-+	for (i=6;i>=0;i--) {
-+		bit= ((addr>>i) & 0x01) ? 1 :0 ;
-+		SPI_write_bit(bit);
-+	}
-+
-+
-+	// turn around
-+	SPI_read_bit(); // TA_Z
-+
-+	value=0;
-+	for (i=31;i>=0;i--) { // READ DATA
-+		bit=SPI_read_bit();
-+		value |= bit << i ;
-+	}
-+
-+	SPI_read_bit(); // dumy clock
-+	SPI_read_bit(); // dumy clock
-+
-+	if(!table)					// EEPROM, only fetch 16 bits data
-+	{
-+	    if(addr&0x01)				// odd number content (register,register-1)
-+		    value >>= 16 ;			// so we remove the rear 16bits
-+	    else					// even number content (register+1,register),
-+		    value &= 0x0000FFFF ;		// so we keep the rear 16 bits
-+	}
-+
-+
-+	SPI_CS_enable(0);
-+
-+#ifdef CONFIG_IT8712_GPIO
-+	status = inb_gpio(LPC_GPIO_SET);
-+	status &= ~(ADM_EDIO) ;		//EDIO low
-+	outb_gpio(LPC_GPIO_SET, status);
-+#else
-+   	ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+	writel(GPIO_MISO,ad1); /* set MISO to 0 */
-+#endif
-+
-+	return(value);
-+
-+}
-+
-+
-+
-+/**************************************************
-+* SPI_port_en
-+* port -> Number of port to config
-+* enable -> 1/ enable this port
-+*	    0/ disable this port
-+**************************************************/
-+void SPI_port_enable(unsigned int port,unsigned char enable)
-+{
-+	unsigned int reg_val ;
-+	unsigned char reg_add ;
-+
-+	if(port<=3)
-+		reg_add=2*port+1;
-+	else if(port==4) reg_add = 8 ;
-+	else reg_add = 9 ;
-+
-+	reg_val = SPI_read(0,reg_add);
-+	if(enable)
-+	{
-+		reg_val &= 0xFFDF ;
-+		SPI_write(reg_add,reg_val);
-+	}
-+	else
-+	{
-+		reg_val |= 0x0020 ;
-+		SPI_write(reg_add,reg_val);
-+	}
-+}
-+
-+/********************************************************
-+* get port status
-+* port -> specify the port number to get configuration
-+*********************************************************/
-+void SPI_get_status(unsigned int port)
-+{
-+/*	unsigned int reg_val,add_offset[6];
-+	struct PORT_STATUS *status;
-+	status = &port_state[port];
-+
-+	if(port>(ADM6996_PORT_NO-1))
-+		return ;
-+
-+	// Link estabilish , speed, deplex, flow control ?
-+	if(port < 5 )
-+	{
-+		reg_val = SPI_read(1, 1) ;
-+		if(port < 4)
-+			reg_val >>= port*8 ;
-+		else
-+			reg_val >>=28 ;
-+		status->link = reg_val & 0x00000001 ;
-+		status->speed = reg_val  & 0x00000002 ;
-+		status->duplex = reg_val & 0x00000004 ;
-+		status->flow_ctl = reg_val & 0x00000008 ;
-+	}
-+	else if(port ==5 )
-+	{
-+		reg_val = SPI_read(1, 2) ;
-+		status->link = reg_val & 0x00000001 ;
-+		status->speed = reg_val  & 0x00000002 ;
-+		status->duplex = reg_val & 0x00000008 ;
-+		status->flow_ctl = reg_val & 0x00000010 ;
-+	}
-+
-+	//   Mac Lock ?
-+	reg_val = SPI_read(0,0x12);
-+	switch(port)
-+	{
-+		case 0:	status->mac_lock = reg_val & 0x00000001;
-+		case 1:	status->mac_lock = reg_val & 0x00000004;
-+		case 2:	status->mac_lock = reg_val & 0x00000010;
-+		case 3:	status->mac_lock = reg_val & 0x00000040;
-+		case 4:	status->mac_lock = reg_val & 0x00000080;
-+		case 5:	status->mac_lock = reg_val & 0x00000100;
-+	}
-+
-+	// port enable ?
-+	add_offset[0] = 0x01 ;		add_offset[1] = 0x03 ;
-+	add_offset[2] = 0x05 ;		add_offset[3] = 0x07 ;
-+	add_offset[4] = 0x08 ;		add_offset[5] = 0x09 ;
-+	reg_val = SPI_read(0,add_offset[port]);
-+	status->port_disable = reg_val & 0x0020;
-+
-+
-+	//  Packet Count ...
-+	add_offset[0] = 0x04 ;		add_offset[1] = 0x06 ;
-+	add_offset[2] = 0x08 ;		add_offset[3] = 0x0a ;
-+	add_offset[4] = 0x0b ;		add_offset[5] = 0x0c ;
-+
-+	reg_val = SPI_read(1,add_offset[port]);
-+	status->rx_pac_count = reg_val ;
-+	reg_val = SPI_read(1,add_offset[port]+9);
-+	status->rx_pac_byte = reg_val ;
-+	reg_val = SPI_read(1,add_offset[port]+18);
-+	status->tx_pac_count = reg_val ;
-+	reg_val = SPI_read(1,add_offset[port]+27);
-+	status->tx_pac_byte = reg_val ;
-+	reg_val = SPI_read(1,add_offset[port]+36);
-+	status->collision_count = reg_val ;
-+	reg_val = SPI_read(1,add_offset[port]+45);
-+	status->error_count = reg_val ;
-+	reg_val = SPI_read(1, 0x3A);
-+	switch(port)
-+	{
-+		case 0:	status->rx_pac_count_overflow = reg_val & 0x00000001;
-+			status->rx_pac_byte_overflow = reg_val & 0x00000200 ;
-+		case 1:	status->rx_pac_count_overflow = reg_val & 0x00000004;
-+			status->rx_pac_byte_overflow = reg_val & 0x00000800 ;
-+		case 2:	status->rx_pac_count_overflow = reg_val & 0x00000010;
-+			status->rx_pac_byte_overflow = reg_val & 0x00002000 ;
-+		case 3:	status->rx_pac_count_overflow = reg_val & 0x00000040;;
-+			status->rx_pac_byte_overflow = reg_val & 0x00008000 ;
-+		case 4:	status->rx_pac_count_overflow = reg_val & 0x00000080;
-+			status->rx_pac_byte_overflow = reg_val & 0x00010000 ;
-+		case 5:	status->rx_pac_count_overflow = reg_val & 0x00000100;
-+			status->rx_pac_byte_overflow = reg_val & 0x00020000 ;
-+	}
-+
-+	reg_val = SPI_read(1, 0x3B);
-+	switch(port)
-+	{
-+		case 0:	status->tx_pac_count_overflow = reg_val & 0x00000001;
-+			status->tx_pac_byte_overflow  = reg_val & 0x00000200 ;
-+		case 1:	status->tx_pac_count_overflow  = reg_val & 0x00000004;
-+			status->tx_pac_byte_overflow  = reg_val & 0x00000800 ;
-+		case 2:	status->tx_pac_count_overflow  = reg_val & 0x00000010;
-+			status->tx_pac_byte_overflow  = reg_val & 0x00002000 ;
-+		case 3:	status->tx_pac_count_overflow  = reg_val & 0x00000040;;
-+			status->tx_pac_byte_overflow  = reg_val & 0x00008000 ;
-+		case 4:	status->tx_pac_count_overflow  = reg_val & 0x00000080;
-+			status->tx_pac_byte_overflow  = reg_val & 0x00010000 ;
-+		case 5:	status->tx_pac_count_overflow  = reg_val & 0x00000100;
-+			status->tx_pac_byte_overflow  = reg_val & 0x00020000 ;
-+	}
-+*/
-+
-+	unsigned int reg_val;
-+	struct PORT_STATUS *status;
-+	status = &port_state[port];
-+
-+	if(port>=ADM6999_PORT_NO)
-+		return ;
-+
-+	// Link estabilish , speed, deplex, flow control ?
-+	if(port < ADM6999_PORT_NO-1 )
-+	{
-+		reg_val = SPI_read(1, 0x01) ;
-+		reg_val = reg_val >> port*4 ;
-+		status->link = reg_val & 0x00000001 ;
-+		status->speed = reg_val  & 0x00000002 ;
-+		status->duplex = reg_val & 0x00000004 ;
-+		status->flow_ctl = reg_val & 0x00000008 ;
-+	}
-+	else if(port == (ADM6999_PORT_NO-1) )
-+	{
-+		reg_val = SPI_read(1, 0x02) ;
-+		status->link = reg_val & 0x00000001 ;
-+		status->speed = reg_val  & 0x00000002 ;
-+		status->duplex = reg_val & 0x00000008 ;
-+		status->flow_ctl = reg_val & 0x00000010 ;
-+	}
-+
-+	// Mac Lock ?
-+	reg_val = SPI_read(0,0x12);
-+	reg_val = reg_val >> port ;
-+	reg_val = reg_val & 0x01 ;
-+	status->mac_lock = reg_val ? 0x01:0x00 ;
-+
-+	// port enable ?
-+	reg_val = SPI_read(0,(unsigned char)port+1);
-+	status->port_disable = reg_val & 0x0020;
-+
-+	//  Packet Count ...
-+	reg_val = SPI_read(1,(unsigned char)port+0x04);
-+	status->rx_pac_count = reg_val ;
-+	reg_val = SPI_read(1,(unsigned char)port+0x0D);
-+	status->rx_pac_byte = reg_val ;
-+	reg_val = SPI_read(1,(unsigned char)port+0x16);
-+	status->tx_pac_count = reg_val ;
-+	reg_val = SPI_read(1,(unsigned char)port+0x1F);
-+	status->tx_pac_byte = reg_val ;
-+	reg_val = SPI_read(1,(unsigned char)port+0x28);
-+	status->collision_count = reg_val ;
-+	reg_val = SPI_read(1,(unsigned char)port+0x31);
-+	status->error_count = reg_val ;
-+	reg_val = SPI_read(1, 0x3A);
-+	reg_val = reg_val >> port ;
-+	status->rx_pac_count_overflow = reg_val & 0x00000001;
-+	reg_val = reg_val >> 0x09 ;
-+	status->rx_pac_byte_overflow = reg_val & 0x00000001 ;
-+
-+	reg_val = SPI_read(1, 0x3B);
-+	reg_val = reg_val >> port ;
-+	status->tx_pac_count_overflow = reg_val & 0x00000001;
-+	reg_val = reg_val >> 0x09 ;
-+	status->tx_pac_byte_overflow  = reg_val & 0x00000001 ;
-+
-+	reg_val = SPI_read(1, 0x3C);
-+	reg_val = reg_val >> port ;
-+	status->collision_count_overflow = reg_val & 0x00000001;
-+	reg_val = reg_val >> 0x09 ;
-+	status->error_count_overflow  = reg_val & 0x00000001 ;
-+
-+}
-+
-+unsigned int SPI_get_identifier(void)
-+{
-+	unsigned int flag=0;
-+
-+#ifdef CONFIG_IT8712_GPIO
-+
-+	if (!it8712_exist) {
-+		return -ENODEV;
-+	}
-+	printk("it8712_gpio init\n");
-+
-+	/* initialize registers */
-+	// switch all multi-function pins to GPIO
-+	LPCSetConfig(LDN_GPIO, 0x28, 0xff);
-+
-+	// set simple I/O base address
-+	LPCSetConfig(LDN_GPIO, 0x62, IT8712_GPIO_BASE >> 8);
-+	LPCSetConfig(LDN_GPIO, 0x63, (unsigned char) IT8712_GPIO_BASE >> 8);
-+
-+	// select GPIO to simple I/O
-+	LPCSetConfig(LDN_GPIO, 0xc3, 0xff);
-+
-+	// enable internal pull-up
-+	LPCSetConfig(LDN_GPIO, 0xbb, 0xff);
-+
-+#endif
-+
-+	flag = SPI_read(1,0x00);
-+	printk("Get ADM identifier %6x\n",flag);
-+	if ((flag & 0xFFFF0) == 0x21120) {
-+		printk("ADM699X Found\n");
-+		return 1;
-+	}
-+	else {
-+		printk("ADM699X not Found\n");
-+		return 0;
-+	}
-+}
-+
---- /dev/null
-+++ b/drivers/net/sl351x_crc16.c
-@@ -0,0 +1,93 @@
-+/****************************************************************************
-+* Name			: sl351x_crc16.c
-+* Description	:
-+*		Implement CRC16
-+*		refer to RFC1662
-+* History
-+*
-+*	Date		Writer		Description
-+*	-----------	-----------	-------------------------------------------------
-+*	09/14/2005	Gary Chen	Create
-+*
-+****************************************************************************/
-+
-+#define INITFCS16		0xffff  /* Initial FCS value */
-+#define GOODFCS16		0xf0b8  /* Good final FCS value */
-+#define SWAP_WORD(x)	(unsigned short)((((unsigned short)x & 0x00FF) << 8) |	\
-+										 (((unsigned short)x & 0xFF00) >> 8))
-+
-+/*----------------------------------------------------------------------
-+* 	x**0 + x**5 + x**12 + x**16
-+*----------------------------------------------------------------------*/
-+static const unsigned short crc16_tbl[256] = {
-+      0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
-+      0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
-+      0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
-+      0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
-+      0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
-+      0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
-+      0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
-+      0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
-+      0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
-+      0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
-+      0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
-+      0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
-+      0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
-+      0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
-+      0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
-+      0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
-+      0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
-+      0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
-+      0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
-+      0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
-+      0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
-+      0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
-+      0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
-+      0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
-+      0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
-+      0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
-+      0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
-+      0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
-+      0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
-+      0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
-+      0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
-+      0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
-+};
-+
-+/*----------------------------------------------------------------------
-+* hash_crc16
-+*----------------------------------------------------------------------*/
-+unsigned short hash_crc16(unsigned short crc, unsigned char *datap, unsigned long len)
-+{
-+    while (len--)
-+    {
-+        crc = (crc >> 8) ^ crc16_tbl[(crc ^ (*datap++)) & 0xff];
-+    }
-+
-+    return (crc);
-+
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_check_crc16
-+*----------------------------------------------------------------------*/
-+unsigned long hash_check_crc16(unsigned char *datap, unsigned long len)
-+{
-+    unsigned short crc;
-+
-+    crc = hash_crc16(INITFCS16, datap, len );
-+    return (crc == GOODFCS16) ?  0 : 1;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_gen_crc16
-+*----------------------------------------------------------------------*/
-+unsigned short hash_gen_crc16(unsigned char *datap, unsigned long len)
-+{
-+    unsigned short crc;
-+
-+    crc = hash_crc16(INITFCS16, datap, len);
-+    crc ^= 0xffff;
-+
-+    return(SWAP_WORD(crc));
-+}
---- /dev/null
-+++ b/drivers/net/sl351x_gmac.c
-@@ -0,0 +1,5622 @@
-+/**************************************************************************
-+* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
-+*--------------------------------------------------------------------------
-+* Name			: sl351x_gmac.c
-+* Description	:
-+*		Ethernet device driver for Storlink SL351x FPGA
-+*
-+* History
-+*
-+*	Date		Writer		Description
-+*	-----------	-----------	-------------------------------------------------
-+*	08/22/2005	Gary Chen	Create and implement
-+*   27/10/2005  CH Hsu      Porting to Linux
-+*
-+****************************************************************************/
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+
-+#define	 MIDWAY
-+#define	 SL_LEPUS
-+#define VITESSE_G5SWITCH	1
-+
-+#ifndef CONFIG_SL351x_RXTOE
-+//#define CONFIG_SL351x_RXTOE	1
-+#endif
-+#undef CONFIG_SL351x_RXTOE
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#ifdef CONFIG_SL351x_SYSCTL
-+#include 
-+#endif
-+
-+#ifdef CONFIG_SL351x_RXTOE
-+#include 
-+#include 
-+#include 
-+#include 
-+#endif
-+
-+// #define SL351x_TEST_WORKAROUND
-+#ifdef CONFIG_SL351x_NAT
-+#define CONFIG_SL_NAPI					1
-+#endif
-+#define GMAX_TX_INTR_DISABLED			1
-+#define DO_HW_CHKSUM					1
-+#define ENABLE_TSO						1
-+#define GMAC_USE_TXQ0					1
-+// #define NAT_WORKAROUND_BY_RESET_GMAC	1
-+// #define HW_RXBUF_BY_KMALLOC			1
-+//#define _DUMP_TX_TCP_CONTENT	1
-+#define	br_if_ioctl						1
-+#define GMAC_LEN_1_2_ISSUE				1
-+
-+#define GMAC_EXISTED_FLAG			0x5566abcd
-+#define CONFIG_MAC_NUM				GMAC_NUM
-+#define GMAC0_BASE					TOE_GMAC0_BASE
-+#define GMAC1_BASE					TOE_GMAC1_BASE
-+#define PAUSE_SET_HW_FREEQ			(TOE_HW_FREEQ_DESC_NUM / 2)
-+#define PAUSE_REL_HW_FREEQ			((TOE_HW_FREEQ_DESC_NUM / 2) + 10)
-+#define DEFAULT_RXQ_MAX_CNT			256
-+#ifdef	L2_jumbo_frame
-+#define TCPHDRLEN(tcp_hdr)  ((ntohs(*((__u16 *)tcp_hdr + 6)) >> 12) & 0x000F)
-+#endif
-+
-+/* define chip information */
-+#define DRV_NAME					"SL351x"
-+#define DRV_VERSION					"0.1.4"
-+#define SL351x_DRIVER_NAME  		DRV_NAME " Giga Ethernet driver " DRV_VERSION
-+
-+#define toe_gmac_enable_interrupt(irq)	enable_irq(irq)
-+#define toe_gmac_disable_interrupt(irq)	disable_irq(irq)
-+
-+#ifdef SL351x_GMAC_WORKAROUND
-+#define GMAC_SHORT_FRAME_THRESHOLD		10
-+static struct timer_list gmac_workround_timer_obj;
-+void sl351x_poll_gmac_hanged_status(u32 data);
-+#ifdef CONFIG_SL351x_NAT
-+//#define IxscriptMate_1518				1
-+	void sl351x_nat_workaround_init(void);
-+	#ifndef NAT_WORKAROUND_BY_RESET_GMAC
-+		static void sl351x_nat_workaround_handler(void);
-+	#endif
-+#endif
-+#endif
-+
-+#ifdef GMAC_LEN_1_2_ISSUE
-+	#define _DEBUG_PREFETCH_NUM	256
-+static	int	_debug_prefetch_cnt;
-+static	char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
-+#endif
-+/*************************************************************
-+ *         Global Variable
-+ *************************************************************/
-+static int	gmac_initialized = 0;
-+TOE_INFO_T toe_private_data;
-+//static int		do_again = 0;
-+spinlock_t gmac_fq_lock;
-+unsigned int FLAG_SWITCH;
-+
-+static unsigned int     	next_tick = 3 * HZ;
-+static unsigned char    	eth_mac[CONFIG_MAC_NUM][6]= {{0x00,0x11,0x11,0x87,0x87,0x87}, {0x00,0x22,0x22,0xab,0xab,0xab}};
-+
-+#undef CONFIG_SL351x_RXTOE
-+extern NAT_CFG_T nat_cfg;
-+
-+/************************************************/
-+/*                 function declare             */
-+/************************************************/
-+static int gmac_set_mac_address(struct net_device *dev, void *addr);
-+static unsigned int gmac_get_phy_vendor(int phy_addr);
-+static void gmac_set_phy_status(struct net_device *dev);
-+void gmac_get_phy_status(struct net_device *dev);
-+static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
-+static void gmac_tx_timeout(struct net_device *dev);
-+static int gmac_phy_thread (void *data);
-+struct net_device_stats * gmac_get_stats(struct net_device *dev);
-+static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev);
-+static void gmac_set_rx_mode(struct net_device *dev);
-+static irqreturn_t toe_gmac_interrupt (int irq, void *dev_instance);
-+static void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp);
-+unsigned int mii_read(unsigned char phyad,unsigned char regad);
-+void mii_write(unsigned char phyad,unsigned char regad,unsigned int value);
-+void mac_init_drv(void);
-+
-+static void toe_init_free_queue(void);
-+static void toe_init_swtx_queue(void);
-+static void toe_init_default_queue(void);
-+#ifdef CONFIG_SL351x_RXTOE
-+static void toe_init_interrupt_queue(void);
-+#endif
-+static void toe_init_interrupt_config(void);
-+static void toe_gmac_sw_reset(void);
-+static int toe_gmac_init_chip(struct net_device *dev);
-+static void toe_gmac_enable_tx_rx(struct net_device* dev);
-+static void toe_gmac_disable_tx_rx(struct net_device *dev);
-+static void toe_gmac_hw_start(struct net_device *dev);
-+static void toe_gmac_hw_stop(struct net_device *dev);
-+static int toe_gmac_clear_counter(struct net_device *dev);
-+static void toe_init_gmac(struct net_device *dev);
-+static  void toe_gmac_tx_complete(GMAC_INFO_T *tp, unsigned int tx_qid, struct net_device *dev, int interrupt);
-+#ifdef CONFIG_SL_NAPI
-+static int gmac_rx_poll(struct net_device *dev, int *budget);
-+// static void toe_gmac_disable_rx(struct net_device *dev);
-+// static void toe_gmac_enable_rx(struct net_device *dev);
-+#endif
-+
-+u32 mac_read_dma_reg(int mac, unsigned int offset);
-+void mac_write_dma_reg(int mac, unsigned int offset, u32 data);
-+void mac_stop_txdma(struct net_device *dev);
-+void mac_get_sw_tx_weight(struct net_device *dev, char *weight);
-+void mac_set_sw_tx_weight(struct net_device *dev, char *weight);
-+void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
-+void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
-+static inline void toe_gmac_fill_free_q(void);
-+
-+#ifdef VITESSE_G5SWITCH
-+extern int Get_Set_port_status(void);
-+extern int SPI_default(void);
-+extern unsigned int SPI_get_identifier(void);
-+void gmac_get_switch_status(struct net_device *dev);
-+unsigned int Giga_switch=0;
-+unsigned int switch_port_no=0;
-+unsigned int ever_dwon=0;
-+#endif
-+
-+/************************************************/
-+/*            GMAC function declare             */
-+/************************************************/
-+static int gmac_open (struct net_device *dev);
-+static int gmac_close (struct net_device *dev);
-+static void gmac_cleanup_module(void);
-+static void gmac_get_mac_address(void);
-+
-+#ifdef CONFIG_SL351x_NAT
-+static void toe_init_hwtx_queue(void);
-+extern void sl351x_nat_init(void);
-+extern void sl351x_nat_input(struct sk_buff *skb, int port, void *l3off, void *l4off);
-+extern int sl351x_nat_output(struct sk_buff *skb, int port);
-+extern int sl351x_nat_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
-+#endif
-+
-+#ifdef CONFIG_SL351x_RXTOE
-+extern void set_toeq_hdr(struct toe_conn* connection, TOE_INFO_T* toe, struct net_device *dev);
-+extern void sl351x_toe_init(void);
-+extern void toe_gmac_handle_toeq(struct net_device *dev, GMAC_INFO_T* tp, __u32 status);
-+extern struct toe_conn* init_toeq(int ipver, void* iph, struct tcphdr* tcp_hdr, TOE_INFO_T* toe, unsigned char* l2hdr);
-+#endif
-+
-+int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2);
-+void mac_set_rule_enable_bit(int mac, int rule, int data);
-+int mac_set_rule_action(int mac, int rule, int data);
-+int mac_get_MRxCRx(int mac, int rule, int ctrlreg);
-+void mac_set_MRxCRx(int mac, int rule, int ctrlreg, u32 data);
-+
-+/*----------------------------------------------------------------------
-+*	Ethernet Driver init
-+*----------------------------------------------------------------------*/
-+
-+static int __init gmac_init_module(void)
-+{
-+	GMAC_INFO_T 		*tp;
-+	struct net_device	*dev;
-+	int 		i,j;
-+	unsigned int	chip_id;
-+//	unsigned int chip_version;
-+
-+#ifdef CONFIG_SL3516_ASIC
-+{
-+    unsigned int    val;
-+    /* set GMAC global register */
-+    val = readl(GMAC_GLOBAL_BASE_ADDR+0x10);
-+    val = val | 0x005f0000;
-+    writel(val,GMAC_GLOBAL_BASE_ADDR+0x10);
-+//    writel(0xb737b737,GMAC_GLOBAL_BASE_ADDR+0x1c); //For Socket Board
-+    writel(0x77777777,GMAC_GLOBAL_BASE_ADDR+0x20);
-+//    writel(0xa737b747,GMAC_GLOBAL_BASE_ADDR+0x1c);//For Mounting Board
-+
-+	//debug_Aaron
-+    //writel(0xa7f0a7f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For Mounting Board
-+    writel(0xa7f0b7f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For Mounting Board
-+
-+    writel(0x77777777,GMAC_GLOBAL_BASE_ADDR+0x24);
-+	writel(0x09200030,GMAC_GLOBAL_BASE_ADDR+0x2C);
-+	val = readl(GMAC_GLOBAL_BASE_ADDR+0x04);
-+	if((val&(1<<20))==0){           // GMAC1 enable
-+ 		val = readl(GMAC_GLOBAL_BASE_ADDR+0x30);
-+		val = (val & 0xe7ffffff) | 0x08000000;
-+		writel(val,GMAC_GLOBAL_BASE_ADDR+0x30);
-+	}
-+}
-+#endif
-+
-+#ifdef VITESSE_G5SWITCH
-+	Giga_switch = SPI_get_identifier();
-+	if(Giga_switch)
-+		switch_port_no = SPI_default();
-+#endif
-+
-+	chip_id = readl(GMAC_GLOBAL_BASE_ADDR+0x0);
-+	if (chip_id == 0x3512C1)
-+	{
-+		writel(0x5787a5f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For 3512 Switch Board
-+		writel(0x55557777,GMAC_GLOBAL_BASE_ADDR+0x20);//For 3512 Switch Board
-+	}
-+//#endif
-+
-+	mac_init_drv();
-+
-+	printk (KERN_INFO SL351x_DRIVER_NAME " built at %s %s\n", __DATE__, __TIME__);
-+
-+//	init_waitqueue_entry(&wait, current);
-+
-+	// printk("GMAC Init......\n");
-+
-+	i = 0;
-+	for(j = 0; idev = NULL;
-+		if (tp->existed != GMAC_EXISTED_FLAG) continue;
-+
-+		dev = alloc_etherdev(0);
-+		if (dev == NULL)
-+		{
-+			printk (KERN_ERR "Can't allocate ethernet device #%d .\n",i);
-+			return -ENOMEM;
-+		}
-+
-+		dev->priv=tp;
-+		tp->dev = dev;
-+
-+		SET_MODULE_OWNER(dev);
-+
-+		// spin_lock_init(&tp->lock);
-+		spin_lock_init(&gmac_fq_lock);
-+		dev->base_addr = tp->base_addr;
-+		dev->irq = tp->irq;
-+	    dev->open = gmac_open;
-+	    dev->stop = gmac_close;
-+		dev->hard_start_xmit = gmac_start_xmit;
-+		dev->get_stats = gmac_get_stats;
-+		dev->set_multicast_list = gmac_set_rx_mode;
-+		dev->set_mac_address = gmac_set_mac_address;
-+		dev->do_ioctl = gmac_netdev_ioctl;
-+		dev->tx_timeout = gmac_tx_timeout;
-+		dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
-+#ifdef	L2_jumbo_frame
-+		dev->mtu = 2018; //2002  ,2018
-+#endif
-+		if (tp->port_id == 0)
-+			dev->tx_queue_len = TOE_GMAC0_SWTXQ_DESC_NUM;
-+		else
-+			dev->tx_queue_len = TOE_GMAC1_SWTXQ_DESC_NUM;
-+
-+#ifdef DO_HW_CHKSUM
-+		dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
-+#ifdef ENABLE_TSO
-+		dev->features |= NETIF_F_TSO;
-+#endif
-+#endif
-+#ifdef CONFIG_SL_NAPI
-+        dev->poll = gmac_rx_poll;
-+        dev->weight = 64;
-+#endif
-+
-+		if (register_netdev(dev))
-+		{
-+			gmac_cleanup_module();
-+			return(-1);
-+		}
-+	}
-+
-+
-+//	FLAG_SWITCH = 0 ;
-+//	FLAG_SWITCH = SPI_get_identifier();
-+//	if(FLAG_SWITCH)
-+//	{
-+//		printk("Configure ADM699X...\n");
-+//		SPI_default();	//Add by jason for ADM699X configuration
-+//	}
-+	return (0);
-+}
-+
-+/*----------------------------------------------------------------------
-+*	gmac_cleanup_module
-+*----------------------------------------------------------------------*/
-+
-+static void gmac_cleanup_module(void)
-+{
-+    int i;
-+
-+#ifdef SL351x_GMAC_WORKAROUND
-+	del_timer(&gmac_workround_timer_obj);
-+#endif
-+
-+    for (i=0;igmac[0].base_addr = GMAC0_BASE;
-+		toe->gmac[1].base_addr = GMAC1_BASE;
-+		toe->gmac[0].dma_base_addr = TOE_GMAC0_DMA_BASE;
-+		toe->gmac[1].dma_base_addr = TOE_GMAC1_DMA_BASE;
-+        toe->gmac[0].auto_nego_cfg = 1;
-+        toe->gmac[1].auto_nego_cfg = 1;
-+#ifdef CONFIG_SL3516_ASIC
-+        toe->gmac[0].speed_cfg = GMAC_SPEED_1000;
-+        toe->gmac[1].speed_cfg = GMAC_SPEED_1000;
-+#else
-+		toe->gmac[0].speed_cfg = GMAC_SPEED_100;
-+        toe->gmac[1].speed_cfg = GMAC_SPEED_100;
-+#endif
-+        toe->gmac[0].full_duplex_cfg = 1;
-+        toe->gmac[1].full_duplex_cfg = 1;
-+#ifdef CONFIG_SL3516_ASIC
-+        toe->gmac[0].phy_mode = GMAC_PHY_RGMII_1000;
-+        toe->gmac[1].phy_mode = GMAC_PHY_RGMII_1000;
-+#else
-+		toe->gmac[0].phy_mode = GMAC_PHY_RGMII_100;
-+        toe->gmac[1].phy_mode = GMAC_PHY_RGMII_100;
-+#endif
-+        toe->gmac[0].port_id = GMAC_PORT0;
-+        toe->gmac[1].port_id = GMAC_PORT1;
-+        toe->gmac[0].phy_addr = 0x1;
-+        toe->gmac[1].phy_addr = 2;
-+//      toe->gmac[0].irq = SL2312_INTERRUPT_GMAC0;
-+		toe->gmac[0].irq =1;
-+//      toe->gmac[1].irq = SL2312_INTERRUPT_GMAC1;
-+		toe->gmac[1].irq =2;
-+        toe->gmac[0].mac_addr1 = ð_mac[0][0];
-+        toe->gmac[1].mac_addr1 = ð_mac[1][0];
-+
-+		for (i=0; igmac[i].base_addr, GMAC_STA_ADD2, 0x55aa55aa, 0xffffffff);
-+			data = gmac_read_reg(toe->gmac[i].base_addr, GMAC_STA_ADD2);
-+			if (data == 0x55aa55aa)
-+			{
-+#ifdef VITESSE_G5SWITCH
-+				if(Giga_switch && (i==1)){
-+					toe->gmac[i].existed = GMAC_EXISTED_FLAG;
-+					break;
-+				}
-+#endif
-+				phy_vendor = gmac_get_phy_vendor(toe->gmac[i].phy_addr);
-+				if (phy_vendor != 0 && phy_vendor != 0xffffffff)
-+					toe->gmac[i].existed = GMAC_EXISTED_FLAG;
-+			}
-+		}
-+
-+		// Write GLOBAL_QUEUE_THRESHOLD_REG
-+		threshold.bits32 = 0;
-+		threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
-+		                                        TOE_SW_FREEQ_DESC_NUM/2;
-+		threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256/4 :
-+		                                        TOE_HW_FREEQ_DESC_NUM/4;
-+		threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256/4 :
-+		                                        TOE_TOE_DESC_NUM/4;
-+		threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256/4 :
-+		                                        TOE_INTR_DESC_NUM/4;
-+		writel(threshold.bits32, TOE_GLOBAL_BASE + GLOBAL_QUEUE_THRESHOLD_REG);
-+
-+		FLAG_SWITCH = 0;
-+		toe_gmac_sw_reset();
-+		toe_init_free_queue();
-+		toe_init_swtx_queue();
-+#ifdef CONFIG_SL351x_NAT
-+		toe_init_hwtx_queue();
-+#endif
-+		toe_init_default_queue();
-+#ifdef CONFIG_SL351x_RXTOE
-+		toe_init_interrupt_queue();
-+#endif
-+		toe_init_interrupt_config();
-+
-+#if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
-+		sl351x_hash_init();
-+#else
-+	{
-+		volatile u32 *dp1, *dp2, dword;
-+
-+		dp1 = (volatile u32 *) TOE_V_BIT_BASE;
-+		dp2 = (volatile u32 *) TOE_A_BIT_BASE;
-+
-+		for (i=0; isw_freeq_desc_base_dma) ;
-+	sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
-+	if (!desc_buf)
-+	{
-+		printk("%s::DMA_MALLOC fail !\n",__func__);
-+		return;
-+	}
-+	memset((void *)desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
-+
-+	// DMA Queue Base & Size
-+	writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
-+			TOE_GLOBAL_BASE + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
-+
-+	// init descriptor base
-+	toe->swfq_desc_base = desc_buf;
-+
-+	// SW Free Queue Read/Write Pointer
-+	rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
-+	rwptr_reg.bits.rptr = 0;
-+	toe->fq_rx_rwptr.bits32 = rwptr_reg.bits32;
-+	writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+
-+	// SW Free Queue Descriptors
-+	for (i=0; iword0.bits.buffer_size = SW_RX_BUF_SIZE;
-+		sw_desc_ptr->word1.bits.sw_id = i;	// used to locate skb
-+		if ( (skb = dev_alloc_skb(SW_RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
-+		{
-+			printk("%s::skb buffer allocation fail !\n",__func__); while(1);
-+		}
-+		REG32(skb->data) = (unsigned int)skb;
-+		skb_reserve(skb, SKB_RESERVE_BYTES);
-+		// toe->rx_skb[i] = skb;
-+		sw_desc_ptr->word2.buf_adr = (unsigned int)__pa(skb->data);
-+//   		consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
-+   		sw_desc_ptr++;
-+	}
-+
-+#ifdef CONFIG_SL351x_NAT
-+	if (sizeof(skb->cb) < 64)
-+	{
-+			printk("==> %s:: sk structure is incorrect -->Change to cb[64] !\n",__func__); while(1);
-+	}
-+	// init hardware free queues
-+	desc_buf = (unsigned int)DMA_MALLOC((TOE_HW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T)),
-+						(dma_addr_t *)&toe->hw_freeq_desc_base_dma) ;
-+	desc_ptr = (GMAC_RXDESC_T *)desc_buf;
-+	if (!desc_buf)
-+	{
-+		printk("%s::DMA_MALLOC fail !\n",__func__);
-+		return;
-+	}
-+	memset((void *)desc_buf, 0, TOE_HW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
-+
-+	// DMA Queue Base & Size
-+	writel((toe->hw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_HW_FREEQ_DESC_POWER,
-+			TOE_GLOBAL_BASE + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
-+
-+	// init descriptor base
-+	toe->hwfq_desc_base = desc_buf;
-+
-+	// HW Free Queue Read/Write Pointer
-+	rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
-+	rwptr_reg.bits.rptr = 0;
-+	writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
-+#ifndef HW_RXBUF_BY_KMALLOC
-+	buf_ptr = (unsigned int)DMA_MALLOC(TOE_HW_FREEQ_DESC_NUM * HW_RX_BUF_SIZE,
-+						(dma_addr_t *)&toe->hwfq_buf_base_dma);
-+#else
-+	buf_ptr = (unsigned int)kmalloc(TOE_HW_FREEQ_DESC_NUM * HW_RX_BUF_SIZE, GFP_KERNEL);
-+	toe->hwfq_buf_base_dma = __pa(buf_ptr);
-+#endif
-+	if (!buf_ptr)
-+	{
-+		printk("===> %s::Failed to allocate HW TxQ Buffers!\n",__func__);
-+		while(1);	// could not be happened, if happened, adjust the buffer descriptor number
-+		return;
-+	}
-+
-+	toe->hwfq_buf_base = buf_ptr;
-+	toe->hwfq_buf_end_dma = toe->hwfq_buf_base_dma + (TOE_HW_FREEQ_DESC_NUM * HW_RX_BUF_SIZE);
-+	buf_ptr = (unsigned int)toe->hwfq_buf_base_dma;
-+	for (i=0; iword0.bits.buffer_size = HW_RX_BUF_SIZE;
-+		desc_ptr->word1.bits.sw_id = i;
-+		desc_ptr->word2.buf_adr = (unsigned int)buf_ptr;
-+//   		consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
-+   		// consistent_sync((unsigned int)buf_ptr, HW_RX_BUF_SIZE, PCI_DMA_TODEVICE);
-+   		desc_ptr++;
-+   		buf_ptr += HW_RX_BUF_SIZE;
-+	}
-+#else
-+	// DMA Queue Base & Size
-+	writel((0) | TOE_SW_FREEQ_DESC_POWER,
-+			TOE_GLOBAL_BASE + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
-+	rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
-+	rwptr_reg.bits.rptr = 0;
-+	writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
-+
-+#endif
-+}
-+/*----------------------------------------------------------------------
-+*	toe_init_swtx_queue
-+*	(2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
-+*		GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
-+*	(2) Initialize DMA Read/Write pointer for
-+*		GMAC 0/1 SW TX Q0-5
-+*----------------------------------------------------------------------*/
-+static void toe_init_swtx_queue(void)
-+{
-+	int 				i;
-+	TOE_INFO_T			*toe;
-+	DMA_RWPTR_T			rwptr_reg;
-+	unsigned int 		rwptr_addr;
-+	unsigned int		desc_buf;
-+
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+
-+	// GMAC-0, SW-TXQ
-+	// The GMAC-0 and GMAC-0 maybe have different descriptor number
-+	// so, not use for instruction
-+	desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
-+						(dma_addr_t *)&toe->gmac[0].swtxq_desc_base_dma) ;
-+	toe->gmac[0].swtxq_desc_base = desc_buf;
-+	if (!desc_buf)
-+	{
-+		printk("%s::DMA_MALLOC fail !\n",__func__);
-+		return	;
-+	}
-+	memset((void *)desc_buf, 0,	TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
-+	writel((toe->gmac[0].swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC0_SWTXQ_DESC_POWER,
-+			TOE_GMAC0_DMA_BASE+ GMAC_SW_TX_QUEUE_BASE_REG);
-+
-+	// GMAC0 SW TX Q0-Q5
-+	rwptr_reg.bits.wptr = 0;
-+	rwptr_reg.bits.rptr = 0;
-+	rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_SW_TX_QUEUE0_PTR_REG;
-+	for (i=0; igmac[0].swtxq[i].rwptr_reg = rwptr_addr;
-+		toe->gmac[0].swtxq[i].desc_base = desc_buf;
-+		toe->gmac[0].swtxq[i].total_desc_num = TOE_GMAC0_SWTXQ_DESC_NUM;
-+		desc_buf += TOE_GMAC0_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
-+		writel(rwptr_reg.bits32, rwptr_addr);
-+		rwptr_addr+=4;
-+	}
-+
-+	// GMAC-1, SW-TXQ
-+	desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC1_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
-+						(dma_addr_t *)&toe->gmac[1].swtxq_desc_base_dma) ;
-+	toe->gmac[1].swtxq_desc_base = desc_buf;
-+	if (!desc_buf)
-+	{
-+		printk("%s::DMA_MALLOC fail !\n",__func__);
-+		return	;
-+	}
-+	memset((void *)desc_buf, 0,	TOE_GMAC1_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
-+	writel((toe->gmac[1].swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC1_SWTXQ_DESC_POWER,
-+			TOE_GMAC1_DMA_BASE+ GMAC_SW_TX_QUEUE_BASE_REG);
-+
-+
-+	// GMAC1 SW TX Q0-Q5
-+	rwptr_reg.bits.wptr = 0;
-+	rwptr_reg.bits.rptr = 0;
-+	rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_SW_TX_QUEUE0_PTR_REG;
-+	for (i=0; igmac[1].swtxq[i].rwptr_reg = rwptr_addr;
-+		toe->gmac[1].swtxq[i].desc_base = desc_buf;
-+		toe->gmac[1].swtxq[i].total_desc_num = TOE_GMAC1_SWTXQ_DESC_NUM;
-+		desc_buf += TOE_GMAC1_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
-+		writel(rwptr_reg.bits32, rwptr_addr);
-+		rwptr_addr+=4;
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+*	toe_init_hwtx_queue
-+*	(2) Initialize the GMAC 0/1 HW TXQ Queue Descriptor Base Address & size
-+*		GMAC_HW_TX_QUEUE_BASE_REG(0x0054)
-+*	(2) Initialize DMA Read/Write pointer for
-+*		GMAC 0/1 HW TX Q0-5
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL351x_NAT
-+static void toe_init_hwtx_queue(void)
-+{
-+	int 				i;
-+	TOE_INFO_T			*toe;
-+	DMA_RWPTR_T			rwptr_reg;
-+	unsigned int 		rwptr_addr;
-+	unsigned int		desc_buf;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	// GMAC-0, HW-TXQ
-+	// The GMAC-0 and GMAC-0 maybe have different descriptor number
-+	// so, not use for instruction
-+	desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC0_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
-+						(dma_addr_t *)&toe->gmac[0].hwtxq_desc_base_dma) ;
-+	toe->gmac[0].hwtxq_desc_base = desc_buf;
-+	if (!desc_buf)
-+	{
-+		printk("%s::DMA_MALLOC fail !\n",__func__);
-+		return	;
-+	}
-+	memset((void *)desc_buf, 0,	TOE_GMAC0_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
-+	writel((toe->gmac[0].hwtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC0_HWTXQ_DESC_POWER,
-+			TOE_GMAC0_DMA_BASE+ GMAC_HW_TX_QUEUE_BASE_REG);
-+
-+	// GMAC0 HW TX Q0-Q5
-+	rwptr_reg.bits.wptr = 0;
-+	rwptr_reg.bits.rptr = 0;
-+	rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
-+	for (i=0; igmac[0].hwtxq[i].desc_base = desc_buf;
-+		desc_buf += TOE_GMAC0_HWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
-+		writel(rwptr_reg.bits32, rwptr_addr);
-+		rwptr_addr+=4;
-+	}
-+
-+	// GMAC-1, HW-TXQ
-+	desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC1_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
-+						(dma_addr_t *)&toe->gmac[1].hwtxq_desc_base_dma) ;
-+	toe->gmac[1].hwtxq_desc_base = desc_buf;
-+	if (!desc_buf)
-+	{
-+		printk("%s::DMA_MALLOC fail !\n",__func__);
-+		return	;
-+	}
-+	memset((void *)desc_buf, 0,	TOE_GMAC1_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
-+	writel((toe->gmac[1].hwtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC1_HWTXQ_DESC_POWER,
-+			TOE_GMAC1_DMA_BASE+ GMAC_HW_TX_QUEUE_BASE_REG);
-+
-+	// GMAC1 HW TX Q0-Q5
-+	rwptr_reg.bits.wptr = 0;
-+	rwptr_reg.bits.rptr = 0;
-+	rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
-+	for (i=0; igmac[1].hwtxq[i].desc_base = desc_buf;
-+		desc_buf += TOE_GMAC1_HWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
-+		writel(rwptr_reg.bits32, rwptr_addr);
-+		rwptr_addr+=4;
-+	}
-+}
-+#endif
-+
-+/*----------------------------------------------------------------------
-+*	toe_init_default_queue
-+*	(1) Initialize the default 0/1 Queue Header
-+*		Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
-+*				  TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
-+*	(2)	Initialize Descriptors of Default Queue 0/1
-+*----------------------------------------------------------------------*/
-+static void toe_init_default_queue(void)
-+{
-+	TOE_INFO_T				*toe;
-+	volatile NONTOE_QHDR_T	*qhdr;
-+	GMAC_RXDESC_T			*desc_ptr;
-+	DMA_SKB_SIZE_T			skb_size;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T)),
-+											(dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
-+	if (!desc_ptr)
-+	{
-+		printk("%s::DMA_MALLOC fail !\n",__func__);
-+		return	;
-+	}
-+	memset((void *)desc_ptr, 0, TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T));
-+	toe->gmac[0].default_desc_base = (unsigned int)desc_ptr;
-+	toe->gmac[0].default_desc_num = TOE_DEFAULT_Q0_DESC_NUM;
-+	qhdr = (volatile NONTOE_QHDR_T *)TOE_DEFAULT_Q0_HDR_BASE;
-+	qhdr->word0.base_size = ((unsigned int)toe->gmac[0].default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q0_DESC_POWER;
-+	qhdr->word1.bits32 = 0;
-+	toe->gmac[0].rx_rwptr.bits32 = 0;
-+	toe->gmac[0].default_qhdr = (NONTOE_QHDR_T *)qhdr;
-+	desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q1_DESC_NUM * sizeof(GMAC_RXDESC_T)),
-+											(dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
-+	if (!desc_ptr)
-+	{
-+		printk("%s::DMA_MALLOC fail !\n",__func__);
-+		return	;
-+	}
-+	memset((void *)desc_ptr, 0, TOE_DEFAULT_Q1_DESC_NUM * sizeof(GMAC_RXDESC_T));
-+	toe->gmac[1].default_desc_base = (unsigned int)desc_ptr;
-+	toe->gmac[1].default_desc_num = TOE_DEFAULT_Q1_DESC_NUM;
-+	qhdr = (volatile NONTOE_QHDR_T *)TOE_DEFAULT_Q1_HDR_BASE;
-+	qhdr->word0.base_size = ((unsigned int)toe->gmac[1].default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q1_DESC_POWER;
-+	qhdr->word1.bits32 = 0;
-+	toe->gmac[1].rx_rwptr.bits32 = 0;
-+	toe->gmac[1].default_qhdr = (NONTOE_QHDR_T *)qhdr;
-+
-+	skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
-+	skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
-+	writel(skb_size.bits32, TOE_GLOBAL_BASE + GLOBAL_DMA_SKB_SIZE_REG);
-+}
-+
-+/*----------------------------------------------------------------------
-+*	toe_init_interrupt_queue
-+*	(1) Initialize the Interrupt Queue Header
-+*		Register: TOE_INTR_Q_HDR_BASE (0x60002080)
-+*	(2)	Initialize Descriptors of Interrupt Queues
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL351x_RXTOE
-+static void toe_init_interrupt_queue(void)
-+{
-+	TOE_INFO_T				*toe;
-+	volatile NONTOE_QHDR_T	*qhdr;
-+	INTR_QHDR_T				*desc_ptr;
-+	// unsigned int			desc_buf_addr;
-+	int						i;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	desc_ptr = (INTR_QHDR_T *)DMA_MALLOC((TOE_INTR_QUEUE_NUM * TOE_INTR_DESC_NUM * sizeof(INTR_QHDR_T)),
-+											(dma_addr_t *)&toe->intr_desc_base_dma);
-+	if (!desc_ptr)
-+	{
-+		printk("%s::DMA_MALLOC interrupt queue fail !\n",__func__);
-+		return	;
-+	}
-+	/*
-+	desc_buf_addr = (unsigned int)DMA_MALLOC((TOE_INTR_DESC_NUM * sizeof(TOE_QHDR_T)),
-+												(dma_addr_t *)&toe->intr_buf_base_dma);
-+	if (!desc_buf_addr)
-+	{
-+		printk("%s::DMA_MALLOC interrupt desc fail !\n",__func__);
-+		return	;
-+	}*/
-+	printk("#### %s::Intr Q desc %x\n", __func__, (u32)desc_ptr);
-+
-+	memset((void *)desc_ptr, 0, TOE_INTR_QUEUE_NUM * TOE_INTR_DESC_NUM * sizeof(INTR_QHDR_T));
-+//	memset((void *)desc_buf_addr, 0, TOE_INTR_DESC_NUM * sizeof(TOE_QHDR_T));
-+	toe->intr_desc_base = (unsigned int)desc_ptr;
-+	toe->intr_desc_num = TOE_INTR_DESC_NUM;
-+
-+	qhdr = (volatile NONTOE_QHDR_T *)TOE_INTR_Q_HDR_BASE;
-+//	intrq = (INTRQ_INFO_T*) &toe->intrq[0];
-+	for (i=0; iword0.base_size = ((unsigned int)toe->intr_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_INTR_DESC_POWER;
-+		qhdr->word1.bits32 = 0;
-+		desc_ptr += TOE_INTR_DESC_NUM;
-+	}
-+}
-+
-+#endif
-+
-+/*----------------------------------------------------------------------
-+*	toe_init_interrupt_config
-+*	Interrupt Select Registers are used to map interrupt to int0 or int1
-+*	Int0 and int1 are wired to CPU 0/1 GMAC 0/1
-+* 	Interrupt Device Inteface data are used to pass device info to
-+*		upper device deiver or store status/statistics
-+*	ISR handler
-+*		(1) If status bit ON but masked, the prinf error message (bug issue)
-+*		(2) If select bits are for me, handle it, else skip to let
-+*			the other ISR handles it.
-+*  Notes:
-+*		GMACx init routine (for eCOS) or open routine (for Linux)
-+*       enable the interrupt bits only which are selected for him.
-+*
-+*	Default Setting:
-+*		GMAC0 intr bits ------>	int0 ----> eth0
-+*		GMAC1 intr bits ------> int1 ----> eth1
-+*		TOE intr -------------> int0 ----> eth0
-+*		Classification Intr --> int0 ----> eth0
-+*		Default Q0 -----------> int0 ----> eth0
-+*		Default Q1 -----------> int1 ----> eth1
-+*----------------------------------------------------------------------*/
-+static void toe_init_interrupt_config(void)
-+{
-+	// clear all status bits
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+	// Init select registers
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+
-+	// disable all interrupt
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_0_REG);
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_2_REG);
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_3_REG);
-+	writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+}
-+
-+/*----------------------------------------------------------------------
-+*	toe_init_gmac
-+*----------------------------------------------------------------------*/
-+static void toe_init_gmac(struct net_device *dev)
-+{
-+	GMAC_INFO_T		*tp = dev->priv;
-+	TOE_INFO_T		*toe;
-+	u32 			data;
-+
-+	if (!gmac_initialized)
-+		return ;
-+
-+	if (!tp->existed)
-+		return;
-+
-+	tp->dev = dev;
-+	tp->flow_control_enable = 1;
-+	tp->pre_phy_status = LINK_DOWN;
-+	tp->full_duplex_status = tp->full_duplex_cfg;
-+	tp->speed_status = tp->speed_status;
-+
-+#if 0
-+   /* get mac address from FLASH */
-+    gmac_get_mac_address();
-+#endif
-+
-+    /* set PHY register to start autonegition process */
-+    gmac_set_phy_status(dev);
-+
-+	/* GMAC initialization */
-+	if ( toe_gmac_init_chip(dev) )
-+	{
-+		printk ("GMAC %d init fail\n", tp->port_id);
-+	}
-+
-+    /* clear statistic counter */
-+    toe_gmac_clear_counter(dev);
-+
-+	memset((void *)&tp->ifStatics, 0, sizeof(struct net_device_stats));
-+
-+	/* -----------------------------------------------------------
-+	Enable GMAC interrupt & disable loopback
-+	Notes:
-+		GMACx init routine (for eCOS) or open routine (for Linux)
-+		enable the interrupt bits only which are selected for him.
-+	--------------------------------------------------------------*/
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+
-+	// Enable Interrupt Bits
-+	if (tp->port_id == 0)
-+	{
-+		tp->intr0_selected =	GMAC0_TXDERR_INT_BIT	 | GMAC0_TXPERR_INT_BIT		|
-+	                         	GMAC0_RXDERR_INT_BIT	 | GMAC0_RXPERR_INT_BIT		|
-+	                            GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
-+	                            GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
-+	                            GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
-+	                            GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
-+	                            GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
-+	                            GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
-+
-+#ifdef GMAX_TX_INTR_DISABLED
-+	    tp->intr0_enabled =		0;
-+#else
-+	    tp->intr0_enabled =		GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
-+#endif
-+
-+	    tp->intr1_selected =	TOE_IQ_ALL_BITS			 | TOE_CLASS_RX_INT_BITS	|
-+	    						GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
-+	    						GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
-+	    						DEFAULT_Q0_INT_BIT;
-+	    tp->intr1_enabled = 	DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
-+	    tp->intr2_selected = 	0xffffffff;	 // TOE Queue 32-63 FUUL Intr
-+	    tp->intr2_enabled = 	0xffffffff;
-+	    tp->intr3_selected = 	0xffffffff;	 // TOE Queue 0-31 FUUL Intr
-+	    tp->intr3_enabled = 	0xffffffff;
-+	    tp->intr4_selected = 	GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
-+	    						HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
-+	    tp->intr4_enabled = 	GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
-+
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG) & ~tp->intr1_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG) & ~tp->intr2_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG) & ~tp->intr3_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) & ~tp->intr4_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+	}
-+	else
-+	{
-+		tp->intr0_selected =	GMAC1_TXDERR_INT_BIT	 | GMAC1_TXPERR_INT_BIT		|
-+	                         	GMAC1_RXDERR_INT_BIT	 | GMAC1_RXPERR_INT_BIT		|
-+	                            GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
-+	                            GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
-+	                            GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
-+	                            GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
-+	                            GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
-+	                            GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
-+#ifdef GMAX_TX_INTR_DISABLED
-+	    tp->intr0_enabled =		0;
-+#else
-+	    tp->intr0_enabled =		GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
-+#endif
-+
-+	    tp->intr1_selected =	DEFAULT_Q1_INT_BIT;
-+	    tp->intr1_enabled = 	DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
-+	    tp->intr2_selected = 	0;	 // TOE Queue 32-63 FUUL Intr
-+	    tp->intr2_enabled = 	0;
-+	    tp->intr3_selected = 	0;	 // TOE Queue 0-31 FUUL Intr
-+	    tp->intr3_enabled = 	0;
-+	    tp->intr4_selected = 	GMAC1_INT_BITS;
-+	    tp->intr4_enabled = 	GMAC1_INT_BITS;
-+
-+	    if (toe->gmac[0].existed != GMAC_EXISTED_FLAG)
-+	    {
-+	    	tp->intr1_selected	|= 	TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS	|
-+	    						  	GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
-+	    						  	GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT;
-+	    	tp->intr1_enabled	|= 	TOE_IQ_ALL_BITS;
-+	    	tp->intr2_selected	|= 	0xffffffff;	 // TOE Queue 32-63 FUUL Intr
-+	    	tp->intr2_enabled	|= 	0xffffffff;
-+	    	tp->intr3_selected	|= 	0xffffffff;	 // TOE Queue 0-31 FUUL Intr
-+	    	tp->intr3_enabled	|= 	0xffffffff;
-+	    	tp->intr4_selected 	|= 	CLASS_RX_FULL_INT_BITS |
-+	    							HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
-+	    	tp->intr4_enabled	|= 	SWFQ_EMPTY_INT_BIT;
-+		}
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) | tp->intr0_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG) | tp->intr1_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG) | tp->intr2_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG) | tp->intr3_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
-+	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) | tp->intr4_selected;
-+	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+	}
-+
-+	// enable only selected bits
-+	gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_0_REG,
-+					tp->intr0_enabled, tp->intr0_selected);
-+	gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_1_REG,
-+					tp->intr1_enabled, tp->intr1_selected);
-+	gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_2_REG,
-+					tp->intr2_enabled, tp->intr2_selected);
-+	gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_3_REG,
-+					tp->intr3_enabled, tp->intr3_selected);
-+	gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
-+					tp->intr4_enabled, tp->intr4_selected);
-+
-+    /* start DMA process */
-+	toe_gmac_hw_start(dev);
-+
-+    /* enable tx/rx register */
-+    toe_gmac_enable_tx_rx(dev);
-+
-+//	toe_gmac_enable_interrupt(tp->irq);
-+
-+    return ;
-+}
-+
-+
-+/*----------------------------------------------------------------------
-+* toe_gmac_sw_reset
-+*----------------------------------------------------------------------*/
-+static void toe_gmac_sw_reset(void)
-+{
-+	unsigned int	reg_val;
-+	reg_val = readl(GMAC_GLOBAL_BASE_ADDR+GLOBAL_RESET_REG) | 0x00000060;   /* GMAC0 S/W reset */
-+    writel(reg_val,GMAC_GLOBAL_BASE_ADDR+GLOBAL_RESET_REG);
-+    udelay(100);
-+    return;
-+}
-+
-+/*----------------------------------------------------------------------
-+*	toe_gmac_init_chip
-+*----------------------------------------------------------------------*/
-+static int toe_gmac_init_chip(struct net_device *dev)
-+{
-+	GMAC_INFO_T 	*tp = dev->priv;
-+	GMAC_CONFIG2_T	config2_val;
-+	GMAC_CONFIG0_T	config0,config0_mask;
-+	GMAC_CONFIG1_T	config1;
-+	#ifdef CONFIG_SL351x_NAT
-+	GMAC_CONFIG3_T	config3_val;
-+	#endif
-+	GMAC_TX_WCR0_T	hw_weigh;
-+	GMAC_TX_WCR1_T	sw_weigh;
-+//	GMAC_HASH_ENABLE_REG0_T hash_ctrl;
-+//
-+#if 0 /* mac address will be set in late_initcall */
-+	struct sockaddr sock;
-+	// GMAC_AHB_WEIGHT_T	ahb_weight, ahb_weight_mask;
-+
-+
-+	/* set station MAC address1 and address2 */
-+	memcpy(&sock.sa_data[0],ð_mac[tp->port_id][0],6);
-+	gmac_set_mac_address(dev,(void *)&sock);
-+#endif
-+
-+	/* set RX_FLTR register to receive all multicast packet */
-+	gmac_write_reg(tp->base_addr, GMAC_RX_FLTR, 0x00000007,0x0000001f);
-+	//    gmac_write_reg(tp->base_addr, GMAC_RX_FLTR, 0x00000007,0x0000001f);
-+	//gmac_write_reg(tp->base_addr, GMAC_RX_FLTR,0x00000007,0x0000001f);
-+
-+	/* set per packet buffer size */
-+	//	config1.bits32 = 0x002004;	//next version
-+	/* set flow control threshold */
-+	config1.bits32 = 0;
-+	config1.bits.set_threshold = 32 / 2;
-+	config1.bits.rel_threshold = 32 / 4 * 3;
-+	gmac_write_reg(tp->base_addr, GMAC_CONFIG1, config1.bits32, 0xffffffff);
-+
-+	/* set flow control threshold */
-+	config2_val.bits32 = 0;
-+	config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM/2;
-+	config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM*3/4;
-+	gmac_write_reg(tp->base_addr, GMAC_CONFIG2, config2_val.bits32,0xffffffff);
-+
-+	#ifdef CONFIG_SL351x_NAT
-+	/* set HW free queue flow control threshold */
-+	config3_val.bits32 = 0;
-+	config3_val.bits.set_threshold = PAUSE_SET_HW_FREEQ;
-+	config3_val.bits.rel_threshold = PAUSE_REL_HW_FREEQ;
-+	gmac_write_reg(tp->base_addr, GMAC_CONFIG3, config3_val.bits32,0xffffffff);
-+	#endif
-+	/* set_mcast_filter mask*/
-+	//	gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,0x0,0xffffffff);
-+	//  gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,0x0,0xffffffff);
-+
-+	/* disable TX/RX and disable internal loop back */
-+	config0.bits32 = 0;
-+	config0_mask.bits32 = 0;
-+
-+	//debug_Aaron
-+#ifdef	L2_jumbo_frame
-+	config0.bits.max_len = 5;
-+#else
-+	config0.bits.max_len = 2;
-+#endif
-+
-+	if (tp->flow_control_enable==1)
-+	{
-+		config0.bits.tx_fc_en = 1; /* enable tx flow control */
-+		config0.bits.rx_fc_en = 1; /* enable rx flow control */
-+		printk("Enable MAC Flow Control...\n");
-+	}
-+	else
-+	{
-+		config0.bits.tx_fc_en = 0; /* disable tx flow control */
-+		config0.bits.rx_fc_en = 0; /* disable rx flow control */
-+		printk("Disable MAC Flow Control...\n");
-+	}
-+	config0.bits.dis_rx = 1;  /* disable rx */
-+	config0.bits.dis_tx = 1;  /* disable tx */
-+	config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
-+	config0.bits.rx_err_detect = 1;
-+	config0.bits.rgmii_en = 0;
-+	config0.bits.rgmm_edge = 1;
-+	config0.bits.rxc_inv = 0;
-+	config0.bits.ipv4_rx_chksum = 1;  /* enable H/W to check ip checksum */
-+	config0.bits.ipv6_rx_chksum = 1;  /* enable H/W to check ip checksum */
-+	config0.bits.port0_chk_hwq = 1;	// GaryChen 3/24/2006 2:26PM
-+	config0.bits.port1_chk_hwq = 1;	// GaryChen 3/24/2006 2:26PM
-+	config0.bits.port0_chk_toeq = 1;
-+	config0.bits.port1_chk_toeq = 1;
-+	config0.bits.port0_chk_classq = 1;
-+	config0.bits.port1_chk_classq = 1;
-+
-+	config0_mask.bits.max_len = 7;
-+	config0_mask.bits.tx_fc_en = 1;
-+	config0_mask.bits.rx_fc_en = 1;
-+	config0_mask.bits.dis_rx = 1;
-+	config0_mask.bits.dis_tx = 1;
-+	config0_mask.bits.loop_back = 1;
-+	config0_mask.bits.rgmii_en = 1;
-+	config0_mask.bits.rgmm_edge = 1;
-+	config0_mask.bits.rxc_inv = 1;
-+	config0_mask.bits.ipv4_rx_chksum = 1;
-+	config0_mask.bits.ipv6_rx_chksum = 1;
-+	config0_mask.bits.port0_chk_hwq = 1;
-+	config0_mask.bits.port1_chk_hwq = 1;
-+	config0_mask.bits.port0_chk_toeq = 1;
-+	config0_mask.bits.port1_chk_toeq = 1;
-+	config0_mask.bits.port0_chk_classq = 1;
-+	config0_mask.bits.port1_chk_classq = 1;
-+	config0_mask.bits.rx_err_detect = 1;
-+
-+	#if 0
-+	config0.bits.dis_rx = 1;  /* disable rx */
-+	config0.bits.dis_tx = 1;  /* disable tx */
-+	config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
-+	config0.bits.txc_inv = 0;
-+	config0.bits.rgmii_en = 0;
-+	config0.bits.rgmm_edge = 1;
-+	config0.bits.rxc_inv = 1;
-+	config0.bits.ipv4_tss_rx_en = 1;  /* enable H/W to check ip checksum */
-+	config0.bits.ipv6_tss_rx_en = 1;  /* enable H/W to check ip checksum */
-+
-+	config0_mask.bits.max_len = 3;
-+	config0_mask.bits.tx_fc_en = 1;
-+	config0_mask.bits.rx_fc_en = 1;
-+	config0_mask.bits.dis_rx = 1;
-+	config0_mask.bits.dis_tx = 1;
-+	config0_mask.bits.loop_back = 1;
-+	config0_mask.bits.rgmii_en = 1;
-+	config0_mask.bits.rgmm_edge = 1;
-+	config0_mask.bits.txc_inv = 1;
-+	config0_mask.bits.rxc_inv = 1;
-+	config0_mask.bits.ipv4_tss_rx_en = 1;
-+	config0_mask.bits.ipv6_tss_rx_en = 1;
-+	#endif
-+
-+	gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
-+
-+	#if 1
-+	hw_weigh.bits32 = 0;
-+	hw_weigh.bits.hw_tq3 = 1;
-+	hw_weigh.bits.hw_tq2 = 1;
-+	hw_weigh.bits.hw_tq1 = 1;
-+	hw_weigh.bits.hw_tq0 = 1;
-+	gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_0_REG, hw_weigh.bits32, 0xffffffff);
-+
-+	sw_weigh.bits32 = 0;
-+	sw_weigh.bits.sw_tq5 = 1;
-+	sw_weigh.bits.sw_tq4 = 1;
-+	sw_weigh.bits.sw_tq3 = 1;
-+	sw_weigh.bits.sw_tq2 = 1;
-+	sw_weigh.bits.sw_tq1 = 1;
-+	sw_weigh.bits.sw_tq0 = 1;
-+	gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_1_REG, sw_weigh.bits32, 0xffffffff);
-+	#endif
-+
-+	#if 0
-+	ahb_weight.bits32 = 0;
-+	ahb_weight_mask.bits32 = 0;
-+	ahb_weight.bits.rx_weight = 1;
-+	ahb_weight.bits.tx_weight = 1;
-+	ahb_weight.bits.hash_weight = 1;
-+	ahb_weight.bits.pre_req = 0x1f;
-+	ahb_weight.bits.tqDV_threshold = 0;
-+	ahb_weight_mask.bits.rx_weight = 0x1f;
-+	ahb_weight_mask.bits.tx_weight = 0x1f;
-+	ahb_weight_mask.bits.hash_weight = 0x1f;
-+	ahb_weight_mask.bits.pre_req = 0x1f;
-+	ahb_weight_mask.bits.tqDV_threshold = 0x1f;
-+	gmac_write_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG, ahb_weight.bits32, ahb_weight_mask.bits32);
-+	#endif
-+
-+	#if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
-+	gmac_write_reg(tp->dma_base_addr, GMAC_SPR0, IPPROTO_TCP, 0xffffffff);
-+	#endif
-+	#ifdef CONFIG_SL351x_NAT
-+	gmac_write_reg(tp->dma_base_addr, GMAC_SPR1, IPPROTO_UDP, 0xffffffff);
-+	gmac_write_reg(tp->dma_base_addr, GMAC_SPR2, IPPROTO_GRE, 0xffffffff);
-+	gmac_write_reg(tp->dma_base_addr, GMAC_SPR3, 0xff, 0xffffffff);
-+	gmac_write_reg(tp->dma_base_addr, GMAC_SPR4, 0xff, 0xffffffff);
-+	gmac_write_reg(tp->dma_base_addr, GMAC_SPR5, 0xff, 0xffffffff);
-+	gmac_write_reg(tp->dma_base_addr, GMAC_SPR6, 0xff, 0xffffffff);
-+	gmac_write_reg(tp->dma_base_addr, GMAC_SPR7, 0xff, 0xffffffff);
-+
-+	sl351x_nat_init();
-+	#endif
-+
-+	#ifdef CONFIG_SL351x_RXTOE
-+	/* setup matching rule to TOE */
-+	sl351x_toe_init();
-+	#endif
-+
-+	// for A1 ASIC version
-+//	hash_ctrl.bits32 = 0;
-+//	hash_ctrl.bits.timing = 6;
-+//	gmac_write_reg(tp->dma_base_addr, GMAC_HASH_ENGINE_REG0, hash_ctrl.bits32, 0xffffffff);
-+
-+	return (0);
-+}
-+
-+/*----------------------------------------------------------------------
-+*	toe_gmac_enable_tx_rx
-+*----------------------------------------------------------------------*/
-+static void toe_gmac_enable_tx_rx(struct net_device *dev)
-+{
-+	GMAC_INFO_T		*tp = dev->priv;
-+	GMAC_CONFIG0_T	config0,config0_mask;
-+
-+    /* enable TX/RX */
-+    config0.bits32 = 0;
-+    config0_mask.bits32 = 0;
-+    config0.bits.dis_rx = 0;  /* enable rx */
-+    config0.bits.dis_tx = 0;  /* enable tx */
-+    config0_mask.bits.dis_rx = 1;
-+    config0_mask.bits.dis_tx = 1;
-+    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
-+}
-+/*----------------------------------------------------------------------
-+*	toe_gmac_disable_rx
-+*----------------------------------------------------------------------*/
-+#if 0
-+static void toe_gmac_disable_rx(struct net_device *dev)
-+{
-+	GMAC_INFO_T		*tp = dev->priv;
-+	GMAC_CONFIG0_T	config0,config0_mask;
-+
-+    /* enable TX/RX */
-+    config0.bits32 = 0;
-+    config0_mask.bits32 = 0;
-+    config0.bits.dis_rx = 1;  /* disable rx */
-+//    config0.bits.dis_tx = 1;  /* disable tx */
-+    config0_mask.bits.dis_rx = 1;
-+//     config0_mask.bits.dis_tx = 1;
-+    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
-+}
-+#endif
-+/*----------------------------------------------------------------------
-+*	toe_gmac_enable_rx
-+*----------------------------------------------------------------------*/
-+#if 0
-+static void toe_gmac_enable_rx(struct net_device *dev)
-+{
-+	GMAC_INFO_T		*tp = dev->priv;
-+	GMAC_CONFIG0_T	config0,config0_mask;
-+
-+    /* enable TX/RX */
-+    config0.bits32 = 0;
-+    config0_mask.bits32 = 0;
-+    config0.bits.dis_rx = 0;  /* enable rx */
-+//    config0.bits.dis_tx = 0;  /* enable tx */
-+    config0_mask.bits.dis_rx = 1;
-+//    config0_mask.bits.dis_tx = 1;
-+    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
-+}
-+#endif
-+/*----------------------------------------------------------------------
-+*	toe_gmac_disable_tx_rx
-+*----------------------------------------------------------------------*/
-+static void toe_gmac_disable_tx_rx(struct net_device *dev)
-+{
-+	GMAC_INFO_T		*tp = dev->priv;
-+	GMAC_CONFIG0_T	config0,config0_mask;
-+
-+    /* enable TX/RX */
-+    config0.bits32 = 0;
-+    config0_mask.bits32 = 0;
-+    config0.bits.dis_rx = 1;  /* disable rx */
-+    config0.bits.dis_tx = 1;  /* disable tx */
-+    config0_mask.bits.dis_rx = 1;
-+    config0_mask.bits.dis_tx = 1;
-+    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
-+}
-+
-+/*----------------------------------------------------------------------
-+*	toe_gmac_hw_start
-+*----------------------------------------------------------------------*/
-+static void toe_gmac_hw_start(struct net_device *dev)
-+{
-+	GMAC_INFO_T				*tp = (GMAC_INFO_T *)dev->priv;
-+	GMAC_DMA_CTRL_T			dma_ctrl, dma_ctrl_mask;
-+
-+
-+    /* program dma control register */
-+	dma_ctrl.bits32 = 0;
-+	dma_ctrl.bits.rd_enable = 1;
-+	dma_ctrl.bits.td_enable = 1;
-+	dma_ctrl.bits.loopback = 0;
-+	dma_ctrl.bits.drop_small_ack = 0;
-+	dma_ctrl.bits.rd_prot = 0;
-+	dma_ctrl.bits.rd_burst_size = 3;
-+	dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
-+	dma_ctrl.bits.rd_bus = 3;
-+	dma_ctrl.bits.td_prot = 0;
-+	dma_ctrl.bits.td_burst_size = 3;
-+	dma_ctrl.bits.td_bus = 3;
-+
-+	dma_ctrl_mask.bits32 = 0;
-+	dma_ctrl_mask.bits.rd_enable = 1;
-+	dma_ctrl_mask.bits.td_enable = 1;
-+	dma_ctrl_mask.bits.loopback = 1;
-+	dma_ctrl_mask.bits.drop_small_ack = 1;
-+	dma_ctrl_mask.bits.rd_prot = 3;
-+	dma_ctrl_mask.bits.rd_burst_size = 3;
-+	dma_ctrl_mask.bits.rd_insert_bytes = 3;
-+	dma_ctrl_mask.bits.rd_bus = 3;
-+	dma_ctrl_mask.bits.td_prot = 0x0f;
-+	dma_ctrl_mask.bits.td_burst_size = 3;
-+	dma_ctrl_mask.bits.td_bus = 3;
-+
-+	gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
-+
-+    return;
-+}
-+
-+/*----------------------------------------------------------------------
-+*	toe_gmac_hw_stop
-+*----------------------------------------------------------------------*/
-+static void toe_gmac_hw_stop(struct net_device *dev)
-+{
-+	GMAC_INFO_T			*tp = (GMAC_INFO_T *)dev->priv;
-+	GMAC_DMA_CTRL_T		dma_ctrl, dma_ctrl_mask;
-+
-+    /* program dma control register */
-+	dma_ctrl.bits32 = 0;
-+	dma_ctrl.bits.rd_enable = 0;
-+	dma_ctrl.bits.td_enable = 0;
-+
-+	dma_ctrl_mask.bits32 = 0;
-+	dma_ctrl_mask.bits.rd_enable = 1;
-+	dma_ctrl_mask.bits.td_enable = 1;
-+
-+	gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
-+}
-+
-+/*----------------------------------------------------------------------
-+*	toe_gmac_clear_counter
-+*----------------------------------------------------------------------*/
-+static int toe_gmac_clear_counter (struct net_device *dev)
-+{
-+	GMAC_INFO_T	*tp = (GMAC_INFO_T *)dev->priv;
-+
-+    /* clear counter */
-+    gmac_read_reg(tp->base_addr, GMAC_IN_DISCARDS);
-+    gmac_read_reg(tp->base_addr, GMAC_IN_ERRORS);
-+    gmac_read_reg(tp->base_addr, GMAC_IN_MCAST);
-+    gmac_read_reg(tp->base_addr, GMAC_IN_BCAST);
-+    gmac_read_reg(tp->base_addr, GMAC_IN_MAC1);
-+    gmac_read_reg(tp->base_addr, GMAC_IN_MAC2);
-+		tp->ifStatics.tx_bytes = 0;
-+		tp->ifStatics.tx_packets = 0;
-+		tp->ifStatics.tx_errors = 0;
-+		tp->ifStatics.rx_bytes = 0;
-+		tp->ifStatics.rx_packets = 0;
-+		tp->ifStatics.rx_errors = 0;
-+		tp->ifStatics.rx_dropped = 0;
-+	return (0);
-+}
-+
-+
-+/*----------------------------------------------------------------------
-+*	toe_gmac_tx_complete
-+*----------------------------------------------------------------------*/
-+static  void toe_gmac_tx_complete(GMAC_INFO_T *tp, unsigned int tx_qid,
-+   										struct net_device *dev, int interrupt)
-+{
-+	volatile GMAC_TXDESC_T	*curr_desc;
-+	GMAC_TXDESC_0_T			word0;
-+	GMAC_TXDESC_1_T			word1;
-+	unsigned int			desc_count;
-+//	struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
-+	GMAC_SWTXQ_T			*swtxq;
-+	DMA_RWPTR_T				rwptr;
-+
-+	/* get tx H/W completed descriptor virtual address */
-+	/* check tx status and accumulate tx statistics */
-+	swtxq = &tp->swtxq[tx_qid];
-+	swtxq->intr_cnt++;
-+	for (;;)
-+	{
-+		rwptr.bits32 = readl(swtxq->rwptr_reg);
-+		if (rwptr.bits.rptr == swtxq->finished_idx)
-+			break;
-+    	curr_desc = (volatile GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
-+//   		consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
-+		word0.bits32 = curr_desc->word0.bits32;
-+		word1.bits32 = curr_desc->word1.bits32;
-+
-+		if (word0.bits.status_tx_ok)
-+		{
-+			tp->ifStatics.tx_bytes += word1.bits.byte_count;
-+			desc_count = word0.bits.desc_count;
-+			if (desc_count==0)
-+			{
-+				printk("%s::Desc 0x%x = 0x%x, desc_count=%d\n",__func__, (u32)curr_desc, word0.bits32, desc_count);
-+				while(1);
-+			}
-+			while (--desc_count)
-+			{
-+				word0.bits.status_tx_ok = 0;
-+				curr_desc->word0.bits32 = word0.bits32;
-+				swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
-+				curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
-+				word0.bits32 = curr_desc->word0.bits32;
-+#ifdef _DUMP_TX_TCP_CONTENT
-+				if (curr_desc->word0.bits.buffer_size < 16)
-+				{
-+					int a;
-+					char *datap;
-+					printk("\t Tx Finished Desc 0x%x Len %d Addr 0x%08x: ", (u32)curr_desc, curr_desc->word0.bits.buffer_size, curr_desc->word2.buf_adr);
-+					datap = (char *)__va(curr_desc->word2.buf_adr);
-+					for (a=0; a<8 && aword0.bits.buffer_size; a++, datap++)
-+					{
-+						printk("0x%02x ", *datap);
-+					}
-+					printk("\n");
-+				}
-+#endif
-+			}
-+
-+			word0.bits.status_tx_ok = 0;
-+			if (swtxq->tx_skb[swtxq->finished_idx])
-+			{
-+				if (interrupt)
-+					dev_kfree_skb_irq(swtxq->tx_skb[swtxq->finished_idx]);
-+				else
-+					dev_kfree_skb(swtxq->tx_skb[swtxq->finished_idx]);
-+				swtxq->tx_skb[swtxq->finished_idx] = NULL;
-+			}
-+			curr_desc->word0.bits32 = word0.bits32;
-+  			swtxq->curr_finished_desc = (GMAC_TXDESC_T *)curr_desc;
-+ 			swtxq->total_finished++;
-+  			tp->ifStatics.tx_packets++;
-+			swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
-+		}
-+		else
-+		{
-+			// tp->ifStatics.tx_errors++;
-+			// printk("%s::Tx Descriptor is !!!\n",__func__);
-+			// wait ready by breaking
-+			break;
-+		}
-+	}
-+
-+	if (netif_queue_stopped(dev))
-+	{
-+		netif_wake_queue(dev);
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+*	gmac_start_xmit
-+*----------------------------------------------------------------------*/
-+static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
-+{
-+	GMAC_INFO_T 			*tp= dev->priv;
-+//	static unsigned int     pcount = 0;
-+//	unsigned int			tx_qid;
-+    DMA_RWPTR_T				rwptr;
-+	volatile GMAC_TXDESC_T	*curr_desc;
-+	int 					snd_pages = skb_shinfo(skb)->nr_frags + 1;  /* get number of descriptor */
-+	int 					frag_id = 0;
-+	int 					len, total_len = skb->len;
-+	struct net_device_stats *isPtr;
-+	unsigned int			free_desc;
-+	GMAC_SWTXQ_T			*swtxq;
-+	register unsigned long	word0, word1, word2, word3;
-+	unsigned short			wptr, rptr;
-+#ifdef	L2_jumbo_frame
-+	int header_len = skb->len;
-+	struct iphdr	*ip_hdr;
-+    struct tcphdr	*tcp_hdr;
-+    int             tcp_hdr_len;
-+    unsigned char 	*ptr;
-+    int             data_len,a;
-+    unsigned int    val;
-+#endif
-+
-+#ifdef GMAC_LEN_1_2_ISSUE
-+	int						total_pages;
-+	total_pages = snd_pages;
-+#endif
-+
-+	isPtr = (struct net_device_stats *)&tp->ifStatics;
-+#if 1
-+	if (skb->len >= 0x10000)
-+	{
-+//		spin_unlock(&tp->tx_mutex);
-+		isPtr->tx_dropped++;
-+		printk("%s::[GMAC %d] skb->len %d >= 64K\n", __func__, tp->port_id, skb->len);
-+		netif_stop_queue(dev);
-+		return 1;
-+    }
-+#endif
-+
-+#if 0
-+	if (storlink_ctl.recvfile==2)
-+	{
-+	    printk("snd_pages=%d skb->len=%d\n",snd_pages,skb->len);
-+	}
-+#endif
-+
-+#ifdef GMAC_USE_TXQ0
-+	#define tx_qid 	0
-+#endif
-+
-+	swtxq = &tp->swtxq[tx_qid];
-+
-+//	spin_lock(&tp->tx_mutex);
-+    rwptr.bits32 = readl(swtxq->rwptr_reg);
-+	wptr = rwptr.bits.wptr;
-+	rptr = rwptr.bits.rptr;
-+
-+	// check finished desc or empty BD
-+	// cannot check by read ptr of RW PTR register,
-+	// because the HW complete to send but the SW may NOT handle it
-+#ifndef	GMAX_TX_INTR_DISABLED
-+	if (wptr >= swtxq->finished_idx)
-+		free_desc = swtxq->total_desc_num - wptr - 1 + swtxq->finished_idx;
-+	else
-+		free_desc = swtxq->finished_idx - wptr - 1;
-+
-+	if (free_desc < snd_pages)
-+	{
-+//		spin_unlock(&tp->tx_mutex);
-+		isPtr->tx_dropped++;
-+//		printk("GMAC %d No available descriptor!\n", tp->port_id);
-+		netif_stop_queue(dev);
-+		return 1;
-+    }
-+#else
-+	toe_gmac_tx_complete(tp, tx_qid, dev, 0);
-+
-+	if (wptr >= swtxq->finished_idx)
-+		free_desc = swtxq->total_desc_num - wptr - 1 + swtxq->finished_idx;
-+	else
-+		free_desc = swtxq->finished_idx - wptr - 1;
-+	if (free_desc < snd_pages)
-+	{
-+//		spin_unlock(&tp->tx_mutex);
-+		isPtr->tx_dropped++;
-+//		printk("GMAC %d No available descriptor!\n", tp->port_id);
-+		netif_stop_queue(dev);
-+		return 1;
-+    }
-+
-+#if 0
-+	printk("1: free_desc=%d, wptr=%d, finished_idx=%d\n", free_desc, wptr, swtxq->finished_idx);
-+	if ((free_desc < (snd_pages << 2)) ||
-+	    (free_desc < (swtxq->total_desc_num >> 2)))
-+	{
-+		printk("2: free_desc = %d\n", free_desc);
-+		toe_gmac_tx_complete(tp, tx_qid, dev, 0);
-+		rwptr.bits32 = readl(swtxq->rwptr_reg);
-+		wptr = rwptr.bits.wptr;
-+		if (wptr>= swtxq->finished_idx)
-+			free_desc = swtxq->total_desc_num - wptr -1 + swtxq->finished_idx;
-+		else
-+			free_desc = swtxq->finished_idx - wptr - 1;
-+	}
-+#endif
-+#endif
-+
-+#ifdef	L2_jumbo_frame
-+//		data_len = skb->len - 14 - ip_hdr->ihl *4 - tcp_hdr_len;
-+//		if ((skb->nh.iph->protocol == __constant_htons(ETH_P_IP)) && ((skb->nh.iph->protocol & 0x00ff)  == IPPROTO_TCP))
-+//		if (skb->nh.iph->protocol == 0x006 && (skb->nh.iph->protocol == __constant_htons(ETH_P_IP)))
-+		if (((skb->nh.iph->protocol & 0x00ff)  == IPPROTO_TCP))
-+		{
-+				ip_hdr = (struct iphdr*)(skb->nh.iph);
-+				tcp_hdr = (struct tcphdr*)(skb->h.th);
-+				tcp_hdr_len = TCPHDRLEN(tcp_hdr) * 4;
-+				tcp_hdr_len = TCPHDRLEN(tcp_hdr) * 4;
-+
-+				if ((skb->h.th->syn) && (tcp_hdr_len > 20))
-+				{
-+					ptr = (unsigned char *)(tcp_hdr+1);
-+					if ((ptr[0] == 0x02) && (ptr[1] == 0x04) && (ptr[2] == 0x07) && (ptr[3] == 0xba)) // 0x07 aa=2016-54=1962  ,0x07ba=2032-54=1978
-+					{
-+						ptr[2]=0x20;	//23
-+						ptr[3]=0x00;   	//00
-+						printk("-----> Change MSS to 8K \n" );
-+					}
-+				}
-+		}
-+//		if ((ip_hdr->protocol & 0x00ff) != IPPROTO_TCP)
-+//		if ((tcp_hdr_len > 20) && (skb->h.th->syn))
-+#endif
-+
-+
-+#if 0
-+	if (snd_pages > 1)
-+		printk("-----> snd_pages=%d\n", snd_pages);
-+	if (total_len > 1514)
-+	{
-+		printk("-----> total_len=%d\n", total_len);
-+	}
-+#endif
-+
-+    while (snd_pages)
-+    {
-+    	char *pkt_datap;
-+
-+    	curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
-+//		consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
-+#if 0
-+//#if (GMAC_DEBUG==1)
-+    	// if curr_desc->word2.buf_adr !=0 means that the ISR does NOT handle it
-+    	// if (curr_desc->word2.buf_adr)
-+    	if (swtxq->tx_skb[wptr])
-+    	{
-+    		printk("Error! Stop due to TX descriptor's buffer is not freed!\n");
-+    		while(1);
-+    		dev_kfree_skb(swtxq->tx_skb[wptr]);
-+    		swtxq->tx_skb[wptr] = NULL;
-+		}
-+#endif
-+
-+		if (frag_id == 0)
-+		{
-+#if 0
-+			int i;
-+			pkt_datap = skb->data;
-+			len = total_len;
-+			for (i=0; inr_frags; i++)
-+			{
-+				skb_frag_t* frag = &skb_shinfo(skb)->frags[i];
-+				len -= frag->size;
-+			}
-+#else
-+			pkt_datap = skb->data;
-+			len = total_len - skb->data_len;
-+#endif
-+		}
-+		else
-+		{
-+			skb_frag_t* frag = &skb_shinfo(skb)->frags[frag_id-1];
-+			pkt_datap = page_address(frag->page) + frag->page_offset;
-+			len = frag->size;
-+			if (len > total_len)
-+			{
-+				printk("===> Fatal Error! Send Frag size %d > Total Size %d!!!!!\n",
-+					len, total_len);
-+			}
-+		}
-+
-+		/* set TX descriptor */
-+		/* copy packet to descriptor buffer address */
-+		// curr_desc->word0.bits32 = len;    /* total frame byte count */
-+		word0 = len;
-+#ifdef	L2_jumbo_frame
-+		word3 = (dev->mtu+14) | EOFIE_BIT;  //2016 ,2032
-+#else
-+		word3 = 1514 | EOFIE_BIT;
-+#endif
-+
-+#ifdef DO_HW_CHKSUM
-+#ifdef	L2_jumbo_frame
-+		if (total_len >= (dev->mtu+14) && (skb->nh.iph->protocol == 0x011) && skb->nh.iph && (skb->nh.iph->frag_off & __constant_htons(0x3fff)))
-+#else
-+		if (total_len <= 1514 && ip_hdr(skb) && (ip_hdr(skb)->frag_off & __constant_htons(0x3fff)))
-+#endif
-+			word1  = total_len |
-+					TSS_IP_CHKSUM_BIT  |
-+					TSS_IPV6_ENABLE_BIT |
-+					TSS_MTU_ENABLE_BIT;
-+		else
-+			word1 = total_len |
-+					TSS_UDP_CHKSUM_BIT |
-+					TSS_TCP_CHKSUM_BIT |
-+					TSS_IP_CHKSUM_BIT  |
-+					TSS_IPV6_ENABLE_BIT |
-+					TSS_MTU_ENABLE_BIT;
-+#else
-+		word1 = total_len | TSS_MTU_ENABLE_BIT;
-+#endif
-+		word2 = (unsigned long)__pa(pkt_datap);
-+
-+		if (frag_id == 0)
-+		{
-+			word3 |= SOF_BIT;	// SOF
-+		}
-+
-+		if (snd_pages == 1)
-+		{
-+			word3 |= EOF_BIT;	// EOF
-+			swtxq->tx_skb[wptr] = skb;
-+#ifdef CONFIG_SL351x_NAT
-+			if (nat_cfg.enabled && sl351x_nat_output(skb, tp->port_id))
-+				word1 |= TSS_IP_FIXED_LEN_BIT;
-+#endif
-+		}
-+		else
-+			swtxq->tx_skb[wptr] = NULL;
-+		// word1 |= TSS_IP_FIXED_LEN_BIT;
-+#if 1
-+#ifdef CONFIG_SL351x_RXTOE
-+		// check if this frame has the mission to enable toe hash entry..
-+		// if rx_max_pktsize ==0, do not enable RXTOE
-+		if (TCP_SKB_CB(skb)->connection && storlink_ctl.rx_max_pktsize) {
-+			set_toeq_hdr(TCP_SKB_CB(skb)->connection, &toe_private_data, dev);
-+		}
-+#endif
-+#endif
-+#ifdef _DUMP_TX_TCP_CONTENT
-+		if (len < 16 && frag_id && skb->h.th && (skb->h.th->source == __constant_htons(445) || skb->h.th->source == __constant_htons(139)))
-+		{
-+			int a;
-+			char *datap;
-+			printk("Tx Desc 0x%x Frag %d Len %d [IP-ID 0x%x] 0x%08x: ", (u32)curr_desc, frag_id, len, htons(skb->nh.iph->id), (u32)pkt_datap);
-+			datap = (char *)pkt_datap;
-+			for (a=0; a<8 && a= _DEBUG_PREFETCH_NUM)
-+				_debug_prefetch_cnt = 0;
-+		}
-+#endif
-+
-+		consistent_sync((void *)pkt_datap, len, PCI_DMA_TODEVICE);
-+		wmb();
-+		curr_desc->word0.bits32 = word0;
-+		curr_desc->word1.bits32 = word1;
-+		curr_desc->word2.bits32 = word2;
-+		curr_desc->word3.bits32 = word3;
-+		swtxq->curr_tx_desc = (GMAC_TXDESC_T *)curr_desc;
-+//		consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_TODEVICE);
-+#ifdef _DUMP_TX_TCP_CONTENT
-+		if (len < 16 && frag_id && skb->h.th && (skb->h.th->source == __constant_htons(445) || skb->h.th->source == __constant_htons(139)))
-+		{
-+			int a;
-+			char *datap;
-+			printk("\t 0x%08x: ", (u32)pkt_datap);
-+			datap = (char *)pkt_datap;
-+			for (a=0; a<8 && atotal_desc_num);
-+		frag_id++;
-+		snd_pages--;
-+	}
-+
-+    swtxq->total_sent++;
-+	SET_WPTR(swtxq->rwptr_reg, wptr);
-+	dev->trans_start = jiffies;
-+
-+
-+	// printk("MAC %d Qid %d rwptr = 0x%x, curr_desc=0x%x\n", skb->tx_port_id, tx_qid, rwptr.bits32, curr_desc);
-+//#ifdef	GMAX_TX_INTR_DISABLED
-+//		toe_gmac_tx_complete(tp, tx_qid, dev, 0);
-+//#endif
-+	return (0);
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_set_mac_address
-+*----------------------------------------------------------------------*/
-+
-+static int gmac_set_mac_address(struct net_device *dev, void *addr)
-+{
-+	GMAC_INFO_T		*tp= dev->priv;
-+	struct sockaddr *sock;
-+	unsigned int    reg_val;
-+    unsigned int    i;
-+
-+	sock = (struct sockaddr *) addr;
-+	for (i = 0; i < 6; i++)
-+	{
-+		dev->dev_addr[i] = sock->sa_data[i];
-+	}
-+
-+    reg_val = dev->dev_addr[0] + (dev->dev_addr[1]<<8) + (dev->dev_addr[2]<<16) + (dev->dev_addr[3]<<24);
-+    gmac_write_reg(tp->base_addr,GMAC_STA_ADD0,reg_val,0xffffffff);
-+    reg_val = dev->dev_addr[4] + (dev->dev_addr[5]<<8);
-+    gmac_write_reg(tp->base_addr,GMAC_STA_ADD1,reg_val,0x0000ffff);
-+	memcpy(ð_mac[tp->port_id][0],&dev->dev_addr[0],6);
-+
-+    printk("Storlink %s address = ",dev->name);
-+    printk("%02x",dev->dev_addr[0]);
-+    printk("%02x",dev->dev_addr[1]);
-+    printk("%02x",dev->dev_addr[2]);
-+    printk("%02x",dev->dev_addr[3]);
-+    printk("%02x",dev->dev_addr[4]);
-+    printk("%02x\n",dev->dev_addr[5]);
-+
-+    return (0);
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_get_mac_address
-+*	get mac address from FLASH
-+*----------------------------------------------------------------------*/
-+static void gmac_get_mac_address(void)
-+{
-+#ifdef CONFIG_MTD
-+	extern int get_vlaninfo(vlaninfo* vlan);
-+    static vlaninfo    vlan[2];
-+
-+    if (get_vlaninfo(&vlan[0]))
-+    {
-+        memcpy((void *)ð_mac[0][0],vlan[0].mac,6);
-+        // VLAN_conf[0].vid = vlan[0].vlanid;
-+        // VLAN_conf[0].portmap = vlan[0].vlanmap;
-+        memcpy((void *)ð_mac[1][0],vlan[1].mac,6);
-+        // VLAN_conf[1].vid = vlan[1].vlanid;
-+        // VLAN_conf[1].portmap = vlan[1].vlanmap;
-+    }
-+#else
-+    unsigned int reg_val;
-+
-+    reg_val = readl(IO_ADDRESS(TOE_GMAC0_BASE)+0xac);
-+    eth_mac[0][4] = (reg_val & 0xff00) >> 8;
-+    eth_mac[0][5] = reg_val & 0x00ff;
-+    reg_val = readl(IO_ADDRESS(SL2312_SECURITY_BASE)+0xac);
-+    eth_mac[1][4] = (reg_val & 0xff00) >> 8;
-+    eth_mac[1][5] = reg_val & 0x00ff;
-+#endif
-+    return;
-+}
-+
-+
-+/*----------------------------------------------------------------------
-+* mac_stop_txdma
-+*----------------------------------------------------------------------*/
-+void mac_stop_txdma(struct net_device *dev)
-+{
-+	GMAC_INFO_T				*tp = (GMAC_INFO_T *)dev->priv;
-+	GMAC_DMA_CTRL_T			dma_ctrl, dma_ctrl_mask;
-+	GMAC_TXDMA_FIRST_DESC_T	txdma_busy;
-+
-+	// wait idle
-+	do
-+	{
-+		txdma_busy.bits32 = gmac_read_reg(tp->dma_base_addr, GMAC_DMA_TX_FIRST_DESC_REG);
-+	} while (txdma_busy.bits.td_busy);
-+
-+    /* program dma control register */
-+	dma_ctrl.bits32 = 0;
-+	dma_ctrl.bits.rd_enable = 0;
-+	dma_ctrl.bits.td_enable = 0;
-+
-+	dma_ctrl_mask.bits32 = 0;
-+	dma_ctrl_mask.bits.rd_enable = 1;
-+	dma_ctrl_mask.bits.td_enable = 1;
-+
-+	gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_start_txdma
-+*----------------------------------------------------------------------*/
-+void mac_start_txdma(struct net_device *dev)
-+{
-+	GMAC_INFO_T			*tp = (GMAC_INFO_T *)dev->priv;
-+	GMAC_DMA_CTRL_T		dma_ctrl, dma_ctrl_mask;
-+
-+    /* program dma control register */
-+	dma_ctrl.bits32 = 0;
-+	dma_ctrl.bits.rd_enable = 1;
-+	dma_ctrl.bits.td_enable = 1;
-+
-+	dma_ctrl_mask.bits32 = 0;
-+	dma_ctrl_mask.bits.rd_enable = 1;
-+	dma_ctrl_mask.bits.td_enable = 1;
-+
-+	gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
-+}
-+
-+
-+/*----------------------------------------------------------------------
-+* gmac_get_stats
-+*----------------------------------------------------------------------*/
-+
-+struct net_device_stats * gmac_get_stats(struct net_device *dev)
-+{
-+    GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
-+    // unsigned int        flags;
-+    unsigned int        pkt_drop;
-+    unsigned int        pkt_error;
-+
-+    if (netif_running(dev))
-+    {
-+        /* read H/W counter */
-+        // spin_lock_irqsave(&tp->lock,flags);
-+        pkt_drop = gmac_read_reg(tp->base_addr,GMAC_IN_DISCARDS);
-+        pkt_error = gmac_read_reg(tp->base_addr,GMAC_IN_ERRORS);
-+        tp->ifStatics.rx_dropped = tp->ifStatics.rx_dropped + pkt_drop;
-+        tp->ifStatics.rx_errors = tp->ifStatics.rx_errors + pkt_error;
-+        // spin_unlock_irqrestore(&tp->lock,flags);
-+    }
-+    return &tp->ifStatics;
-+}
-+
-+
-+
-+/*----------------------------------------------------------------------
-+* mac_get_sw_tx_weight
-+*----------------------------------------------------------------------*/
-+void mac_get_sw_tx_weight(struct net_device *dev, char *weight)
-+{
-+	GMAC_TX_WCR1_T	sw_weigh;
-+    GMAC_INFO_T		*tp = (GMAC_INFO_T *)dev->priv;
-+
-+	sw_weigh.bits32 = gmac_read_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_1_REG);
-+
-+	weight[0] = sw_weigh.bits.sw_tq0;
-+   	weight[1] = sw_weigh.bits.sw_tq1;
-+   	weight[2] = sw_weigh.bits.sw_tq2;
-+   	weight[3] = sw_weigh.bits.sw_tq3;
-+   	weight[4] = sw_weigh.bits.sw_tq4;
-+   	weight[5] = sw_weigh.bits.sw_tq5;
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_set_sw_tx_weight
-+*----------------------------------------------------------------------*/
-+void mac_set_sw_tx_weight(struct net_device *dev, char *weight)
-+{
-+	GMAC_TX_WCR1_T	sw_weigh;
-+    GMAC_INFO_T		*tp = (GMAC_INFO_T *)dev->priv;
-+
-+	sw_weigh.bits32 = 0;
-+	sw_weigh.bits.sw_tq0 = weight[0];
-+   	sw_weigh.bits.sw_tq1 = weight[1];
-+   	sw_weigh.bits.sw_tq2 = weight[2];
-+   	sw_weigh.bits.sw_tq3 = weight[3];
-+   	sw_weigh.bits.sw_tq4 = weight[4];
-+   	sw_weigh.bits.sw_tq5 = weight[5];
-+
-+	gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_1_REG, sw_weigh.bits32, 0xffffffff);
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_get_hw_tx_weight
-+*----------------------------------------------------------------------*/
-+void mac_get_hw_tx_weight(struct net_device *dev, char *weight)
-+{
-+	GMAC_TX_WCR0_T	hw_weigh;
-+    GMAC_INFO_T		*tp = (GMAC_INFO_T *)dev->priv;
-+
-+	hw_weigh.bits32 = gmac_read_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_0_REG);
-+
-+	weight[0] = hw_weigh.bits.hw_tq0;
-+   	weight[1] = hw_weigh.bits.hw_tq1;
-+   	weight[2] = hw_weigh.bits.hw_tq2;
-+   	weight[3] = hw_weigh.bits.hw_tq3;
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_set_hw_tx_weight
-+*----------------------------------------------------------------------*/
-+void mac_set_hw_tx_weight(struct net_device *dev, char *weight)
-+{
-+	GMAC_TX_WCR0_T	hw_weigh;
-+    GMAC_INFO_T		*tp = (GMAC_INFO_T *)dev->priv;
-+
-+	hw_weigh.bits32 = 0;
-+	hw_weigh.bits.hw_tq0 = weight[0];
-+   	hw_weigh.bits.hw_tq1 = weight[1];
-+   	hw_weigh.bits.hw_tq2 = weight[2];
-+   	hw_weigh.bits.hw_tq3 = weight[3];
-+
-+	gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_0_REG, hw_weigh.bits32, 0xffffffff);
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_start_tx_dma
-+*----------------------------------------------------------------------*/
-+int mac_start_tx_dma(int mac)
-+{
-+	GMAC_DMA_CTRL_T dma_ctrl, dma_ctrl_mask;
-+
-+	dma_ctrl.bits32 = 0;
-+	dma_ctrl.bits.td_enable = 1;
-+
-+	dma_ctrl_mask.bits32 = 0;
-+	dma_ctrl_mask.bits.td_enable = 1;
-+
-+	if (mac == 0)
-+    	gmac_write_reg(TOE_GMAC0_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
-+	else
-+    	gmac_write_reg(TOE_GMAC1_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
-+	return	1;
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_stop_tx_dma
-+*----------------------------------------------------------------------*/
-+int mac_stop_tx_dma(int mac)
-+{
-+	GMAC_DMA_CTRL_T dma_ctrl, dma_ctrl_mask;
-+
-+	dma_ctrl.bits32 = 0;
-+	dma_ctrl.bits.td_enable = 0;
-+
-+	dma_ctrl_mask.bits32 = 0;
-+	dma_ctrl_mask.bits.td_enable = 1;
-+
-+	if (mac == 0)
-+    	gmac_write_reg(TOE_GMAC0_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
-+	else
-+    	gmac_write_reg(TOE_GMAC1_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
-+	return	1;
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_read_reg(int mac, unsigned int offset)
-+*----------------------------------------------------------------------*/
-+unsigned int mac_read_reg(int mac, unsigned int offset)
-+{
-+	switch (mac)
-+	{
-+		case 0:
-+			return gmac_read_reg(TOE_GMAC0_BASE, offset);
-+		case 1:
-+			return gmac_read_reg(TOE_GMAC1_BASE, offset);
-+		default:
-+			return 0;
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_write_reg
-+*----------------------------------------------------------------------*/
-+void mac_write_reg(int mac, unsigned int offset, unsigned data)
-+{
-+	switch (mac)
-+	{
-+		case 0:
-+			gmac_write_reg(GMAC0_BASE, offset, data, 0xffffffff);
-+			break;
-+		case 1:
-+			gmac_write_reg(GMAC1_BASE, offset, data, 0xffffffff);
-+			break;
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_read_dma_reg(int mac, unsigned int offset)
-+*----------------------------------------------------------------------*/
-+u32 mac_read_dma_reg(int mac, unsigned int offset)
-+{
-+	switch (mac)
-+	{
-+		case 0:
-+			return gmac_read_reg(TOE_GMAC0_DMA_BASE, offset);
-+		case 1:
-+			return gmac_read_reg(TOE_GMAC1_DMA_BASE, offset);
-+		default:
-+			return 0;
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_write_dma_reg
-+*----------------------------------------------------------------------*/
-+void mac_write_dma_reg(int mac, unsigned int offset, u32 data)
-+{
-+	switch (mac)
-+	{
-+		case 0:
-+			gmac_write_reg(TOE_GMAC0_DMA_BASE, offset, data, 0xffffffff);
-+			break;
-+		case 1:
-+			gmac_write_reg(TOE_GMAC1_DMA_BASE, offset, data, 0xffffffff);
-+			break;
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* ether_crc
-+*----------------------------------------------------------------------*/
-+static unsigned const ethernet_polynomial = 0x04c11db7U;
-+static unsigned int ether_crc (int length, unsigned char *data)
-+{
-+	int crc = -1;
-+	unsigned int i;
-+	unsigned int crc_val=0;
-+
-+	while (--length >= 0) {
-+		unsigned char current_octet = *data++;
-+		int bit;
-+		for (bit = 0; bit < 8; bit++, current_octet >>= 1)
-+			crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
-+			     ethernet_polynomial : 0);
-+	}
-+	crc = ~crc;
-+	for (i=0;i<32;i++)
-+	{
-+		crc_val = crc_val + (((crc << i) & 0x80000000) >> (31-i));
-+	}
-+	return crc_val;
-+}
-+
-+
-+
-+/*----------------------------------------------------------------------
-+* mac_set_rx_mode
-+*----------------------------------------------------------------------*/
-+void mac_set_rx_mode(int pid, unsigned int data)
-+{
-+	unsigned int	base;
-+
-+	base = (pid == 0) ? GMAC0_BASE : GMAC1_BASE;
-+
-+    gmac_write_reg(base, GMAC_RX_FLTR, data, 0x0000001f);
-+    return;
-+}
-+
-+
-+/*----------------------------------------------------------------------
-+* gmac_open
-+*----------------------------------------------------------------------*/
-+
-+static int gmac_open (struct net_device *dev)
-+{
-+	GMAC_INFO_T  *tp = (GMAC_INFO_T *)dev->priv;
-+	int    					retval;
-+	TOE_INFO_T				*toe;
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+
-+    /* hook ISR */
-+	retval = request_irq (dev->irq, toe_gmac_interrupt, IRQF_DISABLED, dev->name, dev);
-+	if (retval)
-+		return retval;
-+
-+	toe_init_gmac(dev);
-+
-+	if(!FLAG_SWITCH)
-+	{
-+    	init_waitqueue_head (&tp->thr_wait);
-+    	init_completion(&tp->thr_exited);
-+
-+    	tp->time_to_die = 0;
-+    	tp->thr_pid = kernel_thread (gmac_phy_thread, dev, CLONE_FS | CLONE_FILES);
-+    	if (tp->thr_pid < 0)
-+    	{
-+    		printk (KERN_WARNING "%s: unable to start kernel thread\n",dev->name);
-+    	}
-+    }
-+
-+	tp->operation = 1;
-+
-+   	netif_start_queue (dev);
-+
-+	return (0);
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_close
-+*----------------------------------------------------------------------*/
-+static int gmac_close(struct net_device *dev)
-+{
-+    TOE_INFO_T			*toe;
-+// 	GMAC_RXDESC_T		*sw_desc_ptr,*desc_ptr;
-+// 	unsigned int		buf_ptr;
-+	GMAC_INFO_T 	*tp = dev->priv;
-+	unsigned int		ret;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+
-+	tp->operation = 0;
-+
-+    netif_stop_queue(dev);
-+    mdelay(20);
-+
-+    /* stop tx/rx packet */
-+    toe_gmac_disable_tx_rx(dev);
-+    mdelay(20);
-+
-+    /* stop the chip's Tx and Rx DMA processes */
-+	toe_gmac_hw_stop(dev);
-+
-+	toe_gmac_disable_interrupt(tp->irq);
-+
-+    /* disable interrupts by clearing the interrupt mask */
-+    synchronize_irq();
-+    free_irq(dev->irq,dev);
-+
-+//	DMA_MFREE(sw_desc_ptr, (TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),(dma_addr_t *)&toe->sw_freeq_desc_base_dma);
-+//	DMA_MFREE(desc_ptr, TOE_HW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),(dma_addr_t *)&toe->hw_freeq_desc_base_dma);
-+//	DMA_MFREE(buf_ptr, TOE_HW_FREEQ_DESC_NUM) * HW_RX_BUF_SIZE),(dma_addr_t *)&toe->hwfq_buf_base_dma);
-+//	DMA_MFREE(toe->gmac[0].swtxq_desc_base , TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[0].swtxq_desc_base_dma);
-+//	DMA_MFREE(toe->gmac[1].swtxq_desc_base , TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[1].swtxq_desc_base_dma);
-+//	DMA_MFREE(toe->gmac[0].hwtxq_desc_base_dma , TOE_GMAC0_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[0].hwtxq_desc_base_dma);
-+//	DMA_MFREE(toe->gmac[1].hwtxq_desc_base_dma , TOE_GMAC0_SWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[1].hwtxq_desc_base_dma);
-+//	DMA_MFREE(toe->gmac[0].default_desc_base_dma ,TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
-+//	DMA_MFREE(toe->gmac[1].default_desc_base_dma , TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
-+//	DMA_MFREE(toe->intr_desc_base_dma , TOE_INTR_QUEUE_NUM * TOE_INTR_DESC_NUM * sizeof(GMAC_RXDESC_T),(dma_addr_t *)&toe->intr_desc_base_dma);
-+//	DMA_MFREE(toe->intr_buf_base_dma , TOE_INTR_DESC_NUM * sizeof(TOE_QHDR_T),(dma_addr_t *)&toe->intr_buf_base_dma);
-+
-+	if(!FLAG_SWITCH)
-+	{
-+    	if (tp->thr_pid >= 0)
-+    	{
-+		    tp->time_to_die = 1;
-+    		wmb();
-+    		ret = kill_proc (tp->thr_pid, SIGTERM, 1);
-+    		if (ret)
-+    		{
-+    			printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
-+    			return ret;
-+    		}
-+//    		wait_for_completion (&tp->thr_exited);
-+    	}
-+    }
-+
-+    return (0);
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_gmac_fill_free_q
-+* allocate buffers for free queue.
-+*----------------------------------------------------------------------*/
-+static inline void toe_gmac_fill_free_q(void)
-+{
-+	struct sk_buff	*skb;
-+	volatile DMA_RWPTR_T	fq_rwptr;
-+	volatile GMAC_RXDESC_T	*fq_desc;
-+	unsigned long	flags;
-+	// unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
-+
-+	fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+	spin_lock_irqsave(&gmac_fq_lock, flags);
-+	//while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
-+	//				TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
-+	while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
-+					TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
-+		if ((skb = dev_alloc_skb(SW_RX_BUF_SIZE)) == NULL) {
-+			printk("%s::skb allocation fail!\n", __func__);
-+			//while(1);
-+			break;
-+		}
-+		REG32(skb->data) = (unsigned int)skb;
-+		skb_reserve(skb, SKB_RESERVE_BYTES);
-+		// fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+		fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
-+			TOE_SW_FREEQ_DESC_NUM);
-+		fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base+fq_rwptr.bits.wptr;
-+		fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
-+		SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
-+		toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
-+	}
-+	spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+}
-+// EXPORT_SYMBOL(toe_gmac_fill_free_q);
-+
-+/*----------------------------------------------------------------------
-+* toe_gmac_interrupt
-+*----------------------------------------------------------------------*/
-+static irqreturn_t toe_gmac_interrupt (int irq, void *dev_instance)
-+{
-+	struct net_device   *dev = (struct net_device *)dev_instance;
-+	TOE_INFO_T			*toe;
-+	GMAC_INFO_T 		*tp = (GMAC_INFO_T *)dev->priv;
-+	unsigned int		status0;
-+	unsigned int		status1;
-+	unsigned int		status2;
-+	unsigned int		status3;
-+	unsigned int		status4;
-+
-+//	struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+//	handle NAPI
-+#ifdef CONFIG_SL_NAPI
-+if (storlink_ctl.pauseoff == 1)
-+{
-+/* disable GMAC interrupt */
-+    //toe_gmac_disable_interrupt(tp->irq);
-+
-+//	isPtr->interrupts++;
-+	/* read Interrupt status */
-+	status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
-+	status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
-+	status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
-+	status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
-+	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+	// prompt warning if status bit ON but not enabled
-+#if 0
-+	if (status0 & ~tp->intr0_enabled)
-+		printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
-+				status0, tp->intr0_enabled);
-+	if (status1 & ~tp->intr1_enabled)
-+		printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
-+				status1, tp->intr1_enabled);
-+	if (status2 & ~tp->intr2_enabled)
-+		printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
-+				status2, tp->intr2_enabled);
-+	if (status3 & ~tp->intr3_enabled)
-+		printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
-+				status3, tp->intr3_enabled);
-+	if (status4 & ~tp->intr4_enabled)
-+		printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
-+				status4, tp->intr4_enabled);
-+#endif
-+
-+	if (status0)
-+		writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
-+	if (status1)
-+		writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
-+	if (status2)
-+		writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
-+	if (status3)
-+		writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
-+	if (status4)
-+		writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
-+#if 0
-+	/* handle freeq interrupt first */
-+	if (status4 & tp->intr4_enabled) {
-+		if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
-+		{
-+			// unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+			//gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
-+			//	tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
-+
-+			if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
-+				toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
-+			if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
-+				toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
-+			printk("\nfreeq int\n");
-+			toe_gmac_fill_free_q();
-+			tp->sw_fq_empty_cnt++;
-+
-+		}
-+	}
-+#endif
-+	// Interrupt Status 1
-+	if (status1 & tp->intr1_enabled)
-+	{
-+		#define G1_INTR0_BITS	(GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
-+		#define G0_INTR0_BITS	(GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
-+		// Handle GMAC 0/1 HW Tx queue 0-3 EOF events
-+		// Only count
-+		// TOE, Classification, and default queues interrupts are handled by ISR
-+		// because they should pass packets to upper layer
-+		if (tp->port_id == 0)
-+		{
-+			if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
-+			{
-+				if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
-+					tp->hwtxq[3].eof_cnt++;
-+				if (status1 & GMAC0_HWTQ02_EOF_INT_BIT)
-+					tp->hwtxq[2].eof_cnt++;
-+				if (status1 & GMAC0_HWTQ01_EOF_INT_BIT)
-+					tp->hwtxq[1].eof_cnt++;
-+				if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
-+					tp->hwtxq[0].eof_cnt++;
-+			}
-+				if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
-+				{
-+					if (likely(netif_rx_schedule_prep(dev)))
-+        			{
-+        				unsigned int data32;
-+        				// disable GMAC-0 rx interrupt
-+        				// class-Q & TOE-Q are implemented in future
-+        				//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+        				//data32 &= ~DEFAULT_Q0_INT_BIT;
-+						//writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+						//printk("\%s: DEFAULT_Q0_INT_BIT===================>>>>>>>>>>>>\n",__func__);
-+						writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
-+						//tp->total_q_cnt_napi=0;
-+						//rx_time = jiffies;
-+						//rx_old_bytes = isPtr->rx_bytes;
-+            			__netif_rx_schedule(dev);
-+        			}
-+			}
-+		}
-+		else if (tp->port_id == 1)
-+		{
-+			if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
-+			{
-+				if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
-+					tp->hwtxq[3].eof_cnt++;
-+				if (status1 & GMAC1_HWTQ12_EOF_INT_BIT)
-+					tp->hwtxq[2].eof_cnt++;
-+				if (status1 & GMAC1_HWTQ11_EOF_INT_BIT)
-+					tp->hwtxq[1].eof_cnt++;
-+				if (status1 & GMAC1_HWTQ10_EOF_INT_BIT)
-+					tp->hwtxq[0].eof_cnt++;
-+			}
-+
-+			if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
-+			{
-+				if (likely(netif_rx_schedule_prep(dev)))
-+        		{
-+        			unsigned int data32;
-+         			// disable GMAC-0 rx interrupt
-+        			// class-Q & TOE-Q are implemented in future
-+        			//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+        			//data32 &= ~DEFAULT_Q1_INT_BIT;
-+					//writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+					//printk("\%s: 1111111111--->DEFAULT_Q1_INT_BIT===================>>>>>>>>>>>>\n",__func__);
-+					writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
-+					//tp->total_q_cnt_napi=0;
-+					//rx_time = jiffies;
-+					//rx_old_bytes = isPtr->rx_bytes;
-+           			__netif_rx_schedule(dev);
-+        		}
-+			}
-+		}
-+	}
-+
-+	// Interrupt Status 0
-+	if (status0 & tp->intr0_enabled)
-+	{
-+		#define ERR_INTR_BITS	(GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |	\
-+								 GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |	\
-+								 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |	\
-+								 GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT)
-+
-+		if (status0 &  ERR_INTR_BITS)
-+		{
-+			if ((status0 & GMAC0_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXDERR_INT_BIT))
-+			{
-+				tp->txDerr_cnt[0]++;
-+				printk("GMAC0 TX AHB Bus Error!\n");
-+			}
-+			if ((status0 & GMAC0_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXPERR_INT_BIT))
-+			{
-+				tp->txPerr_cnt[0]++;
-+				printk("GMAC0 Tx Descriptor Protocol Error!\n");
-+			}
-+			if ((status0 & GMAC1_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXDERR_INT_BIT))
-+			{
-+				tp->txDerr_cnt[1]++;
-+				printk("GMAC1 Tx AHB Bus Error!\n");
-+			}
-+			if ((status0 & GMAC1_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXPERR_INT_BIT))
-+			{
-+				tp->txPerr_cnt[1]++;
-+				printk("GMAC1 Tx Descriptor Protocol Error!\n");
-+			}
-+
-+			if ((status0 & GMAC0_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXDERR_INT_BIT))
-+			{
-+				tp->RxDerr_cnt[0]++;
-+				printk("GMAC0 Rx AHB Bus Error!\n");
-+			}
-+			if ((status0 & GMAC0_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXPERR_INT_BIT))
-+			{
-+				tp->RxPerr_cnt[0]++;
-+				printk("GMAC0 Rx Descriptor Protocol Error!\n");
-+			}
-+			if ((status0 & GMAC1_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXDERR_INT_BIT))
-+			{
-+				tp->RxDerr_cnt[1]++;
-+				printk("GMAC1 Rx AHB Bus Error!\n");
-+			}
-+			if ((status0 & GMAC1_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXPERR_INT_BIT))
-+			{
-+				tp->RxPerr_cnt[1]++;
-+				printk("GMAC1 Rx Descriptor Protocol Error!\n");
-+			}
-+		}
-+
-+#ifndef	GMAX_TX_INTR_DISABLED
-+		if (tp->port_id == 1 &&	netif_running(dev) &&
-+			(((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
-+			||
-+			((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT))))
-+		{
-+			toe_gmac_tx_complete(&toe_private_data.gmac[1], 0, dev, 1);
-+		}
-+
-+		if (tp->port_id == 0 &&	netif_running(dev) &&
-+			(((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
-+			||
-+			((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT))))
-+		{
-+			toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
-+		}
-+#endif
-+	}
-+	// Interrupt Status 4
-+	if (status4 & tp->intr4_enabled)
-+	{
-+		#define G1_INTR4_BITS		(0xff000000)
-+		#define G0_INTR4_BITS		(0x00ff0000)
-+
-+		if (tp->port_id == 0)
-+		{
-+			if ((status4 & G0_INTR4_BITS) && (tp->intr4_enabled & G0_INTR4_BITS))
-+			{
-+				if (status4 & GMAC0_RESERVED_INT_BIT)
-+					printk("GMAC0_RESERVED_INT_BIT is ON\n");
-+				if (status4 & GMAC0_MIB_INT_BIT)
-+					tp->mib_full_cnt++;
-+				if (status4 & GMAC0_RX_PAUSE_ON_INT_BIT)
-+					tp->rx_pause_on_cnt++;
-+				if (status4 & GMAC0_TX_PAUSE_ON_INT_BIT)
-+					tp->tx_pause_on_cnt++;
-+				if (status4 & GMAC0_RX_PAUSE_OFF_INT_BIT)
-+					tp->rx_pause_off_cnt++;
-+				if (status4 & GMAC0_TX_PAUSE_OFF_INT_BIT)
-+					tp->rx_pause_off_cnt++;
-+				if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
-+					tp->rx_overrun_cnt++;
-+				if (status4 & GMAC0_STATUS_CHANGE_INT_BIT)
-+					tp->status_changed_cnt++;
-+			}
-+		}
-+		else if (tp->port_id == 1)
-+		{
-+			if ((status4 & G1_INTR4_BITS) && (tp->intr4_enabled & G1_INTR4_BITS))
-+			{
-+				if (status4 & GMAC1_RESERVED_INT_BIT)
-+					printk("GMAC1_RESERVED_INT_BIT is ON\n");
-+				if (status4 & GMAC1_MIB_INT_BIT)
-+					tp->mib_full_cnt++;
-+				if (status4 & GMAC1_RX_PAUSE_ON_INT_BIT)
-+				{
-+					printk("Gmac pause on\n");
-+					tp->rx_pause_on_cnt++;
-+				}
-+				if (status4 & GMAC1_TX_PAUSE_ON_INT_BIT)
-+				{
-+					printk("Gmac pause on\n");
-+					tp->tx_pause_on_cnt++;
-+				}
-+				if (status4 & GMAC1_RX_PAUSE_OFF_INT_BIT)
-+				{
-+					printk("Gmac pause off\n");
-+					tp->rx_pause_off_cnt++;
-+				}
-+				if (status4 & GMAC1_TX_PAUSE_OFF_INT_BIT)
-+				{
-+					printk("Gmac pause off\n");
-+					tp->rx_pause_off_cnt++;
-+				}
-+				if (status4 & GMAC1_RX_OVERRUN_INT_BIT)
-+				{
-+					//printk("Gmac Rx Overrun \n");
-+					tp->rx_overrun_cnt++;
-+				}
-+				if (status4 & GMAC1_STATUS_CHANGE_INT_BIT)
-+					tp->status_changed_cnt++;
-+			}
-+		}
-+	}
-+
-+	//toe_gmac_enable_interrupt(tp->irq);
-+#ifdef IxscriptMate_1518
-+	if (storlink_ctl.pauseoff == 1)
-+	{
-+		GMAC_CONFIG0_T config0;
-+		config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
-+		config0.bits.dis_rx = 0;
-+		writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+		config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
-+		config0.bits.dis_rx = 0;
-+		writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+	}
-+#endif
-+//	 enable_irq(gmac_irq[dev_index]);
-+	//printk("gmac_interrupt complete!\n\n");
-+//	return IRQ_RETVAL(handled);
-+	return	IRQ_RETVAL(1);
-+}
-+else
-+{
-+#endif	//endif NAPI
-+
-+
-+	/* disable GMAC interrupt */
-+    toe_gmac_disable_interrupt(tp->irq);
-+
-+//	isPtr->interrupts++;
-+	/* read Interrupt status */
-+	status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
-+	status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
-+	status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
-+	status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
-+	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+	// prompt warning if status bit ON but not enabled
-+#if 0
-+	if (status0 & ~tp->intr0_enabled)
-+		printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
-+				status0, tp->intr0_enabled);
-+	if (status1 & ~tp->intr1_enabled)
-+		printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
-+				status1, tp->intr1_enabled);
-+	if (status2 & ~tp->intr2_enabled)
-+		printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
-+				status2, tp->intr2_enabled);
-+	if (status3 & ~tp->intr3_enabled)
-+		printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
-+				status3, tp->intr3_enabled);
-+	if (status4 & ~tp->intr4_enabled)
-+		printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
-+				status4, tp->intr4_enabled);
-+#endif
-+#define	INTERRUPT_SELECT			1
-+	if (status0)
-+		writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
-+	if (status1)
-+		writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
-+	if (status2)
-+		writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
-+	if (status3)
-+		writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
-+	if (status4)
-+		writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+	/* handle freeq interrupt first */
-+	if (status4 & tp->intr4_enabled) {
-+		if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
-+		{
-+			// unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+			//gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
-+			//	tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
-+
-+			//gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
-+			//	SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
-+			if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
-+				toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
-+			if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
-+				toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
-+			printk("\nfreeq int\n");
-+			toe_gmac_fill_free_q();
-+			tp->sw_fq_empty_cnt++;
-+
-+			gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
-+				SWFQ_EMPTY_INT_BIT);
-+		}
-+	}
-+
-+	// Interrupt Status 1
-+	if (status1 & tp->intr1_enabled)
-+	{
-+		#define G1_INTR0_BITS	(GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
-+		#define G0_INTR0_BITS	(GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
-+		// Handle GMAC 0/1 HW Tx queue 0-3 EOF events
-+		// Only count
-+		// TOE, Classification, and default queues interrupts are handled by ISR
-+		// because they should pass packets to upper layer
-+		if (tp->port_id == 0)
-+		{
-+#ifndef	INTERRUPT_SELECT
-+			if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
-+			{
-+				if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
-+					tp->hwtxq[3].eof_cnt++;
-+				if (status1 & GMAC0_HWTQ02_EOF_INT_BIT)
-+					tp->hwtxq[2].eof_cnt++;
-+				if (status1 & GMAC0_HWTQ01_EOF_INT_BIT)
-+					tp->hwtxq[1].eof_cnt++;
-+				if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
-+					tp->hwtxq[0].eof_cnt++;
-+#endif	//INTERRUPT_SELECT
-+#ifndef	INTERRUPT_SELECT
-+			}
-+#endif	//INTERRUPT_SELECT
-+			if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
-+			{
-+				tp->default_q_intr_cnt++;
-+				toe_gmac_handle_default_rxq(dev, tp);
-+			}
-+#ifdef CONFIG_SL351x_RXTOE
-+			if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
-+			    (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
-+				//printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
-+				toe_gmac_handle_toeq(dev, tp, status1);
-+				//toe_gmac_handle_toeq(dev, toe, tp, status1);
-+			}
-+#endif
-+		}
-+		else if (tp->port_id == 1)
-+		{
-+#ifndef	INTERRUPT_SELECT
-+			if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
-+			{
-+				if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
-+					tp->hwtxq[3].eof_cnt++;
-+				if (status1 & GMAC1_HWTQ12_EOF_INT_BIT)
-+					tp->hwtxq[2].eof_cnt++;
-+				if (status1 & GMAC1_HWTQ11_EOF_INT_BIT)
-+					tp->hwtxq[1].eof_cnt++;
-+				if (status1 & GMAC1_HWTQ10_EOF_INT_BIT)
-+					tp->hwtxq[0].eof_cnt++;
-+#endif	//INTERRUPT_SELECT
-+#ifndef	INTERRUPT_SELECT
-+			}
-+#endif	//INTERRUPT_SELECT
-+			if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
-+			{
-+				tp->default_q_intr_cnt++;
-+				toe_gmac_handle_default_rxq(dev, tp);
-+			}
-+#ifdef CONFIG_SL351x_RXTOE
-+			if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
-+			    (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
-+				//printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
-+				toe_gmac_handle_toeq(dev, tp, status1);
-+				//toe_gmac_handle_toeq(dev, toe, tp, status1);
-+			}
-+#endif
-+		}
-+	}
-+
-+
-+	// Interrupt Status 0
-+	if (status0 & tp->intr0_enabled)
-+	{
-+
-+		#define ERR_INTR_BITS	(GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |	\
-+								 GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |	\
-+								 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |	\
-+								 GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT)
-+#ifndef	INTERRUPT_SELECT
-+		if (status0 &  ERR_INTR_BITS)
-+		{
-+			if ((status0 & GMAC0_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXDERR_INT_BIT))
-+			{
-+				tp->txDerr_cnt[0]++;
-+				printk("GMAC0 TX AHB Bus Error!\n");
-+			}
-+			if ((status0 & GMAC0_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXPERR_INT_BIT))
-+			{
-+				tp->txPerr_cnt[0]++;
-+				printk("GMAC0 Tx Descriptor Protocol Error!\n");
-+			}
-+			if ((status0 & GMAC1_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXDERR_INT_BIT))
-+			{
-+				tp->txDerr_cnt[1]++;
-+				printk("GMAC1 Tx AHB Bus Error!\n");
-+			}
-+			if ((status0 & GMAC1_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXPERR_INT_BIT))
-+			{
-+				tp->txPerr_cnt[1]++;
-+				printk("GMAC1 Tx Descriptor Protocol Error!\n");
-+			}
-+
-+			if ((status0 & GMAC0_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXDERR_INT_BIT))
-+			{
-+				tp->RxDerr_cnt[0]++;
-+				printk("GMAC0 Rx AHB Bus Error!\n");
-+			}
-+			if ((status0 & GMAC0_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXPERR_INT_BIT))
-+			{
-+				tp->RxPerr_cnt[0]++;
-+				printk("GMAC0 Rx Descriptor Protocol Error!\n");
-+			}
-+			if ((status0 & GMAC1_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXDERR_INT_BIT))
-+			{
-+				tp->RxDerr_cnt[1]++;
-+				printk("GMAC1 Rx AHB Bus Error!\n");
-+			}
-+			if ((status0 & GMAC1_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXPERR_INT_BIT))
-+			{
-+				tp->RxPerr_cnt[1]++;
-+				printk("GMAC1 Rx Descriptor Protocol Error!\n");
-+			}
-+		}
-+#endif	//INTERRUPT_SELECT
-+#ifndef	GMAX_TX_INTR_DISABLED
-+		if (tp->port_id == 1 &&	netif_running(dev) &&
-+			(((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
-+			||
-+			((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT))))
-+		{
-+			toe_gmac_tx_complete(&toe_private_data.gmac[1], 0, dev, 1);
-+		}
-+
-+		if (tp->port_id == 0 &&	netif_running(dev) &&
-+			(((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
-+			||
-+			((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT))))
-+		{
-+			toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
-+		}
-+#endif
-+		// clear enabled status bits
-+	}
-+	// Interrupt Status 4
-+#ifndef	INTERRUPT_SELECT
-+	if (status4 & tp->intr4_enabled)
-+	{
-+		#define G1_INTR4_BITS		(0xff000000)
-+		#define G0_INTR4_BITS		(0x00ff0000)
-+
-+		if (tp->port_id == 0)
-+		{
-+			if ((status4 & G0_INTR4_BITS) && (tp->intr4_enabled & G0_INTR4_BITS))
-+			{
-+				if (status4 & GMAC0_RESERVED_INT_BIT)
-+					printk("GMAC0_RESERVED_INT_BIT is ON\n");
-+				if (status4 & GMAC0_MIB_INT_BIT)
-+					tp->mib_full_cnt++;
-+				if (status4 & GMAC0_RX_PAUSE_ON_INT_BIT)
-+					tp->rx_pause_on_cnt++;
-+				if (status4 & GMAC0_TX_PAUSE_ON_INT_BIT)
-+					tp->tx_pause_on_cnt++;
-+				if (status4 & GMAC0_RX_PAUSE_OFF_INT_BIT)
-+					tp->rx_pause_off_cnt++;
-+				if (status4 & GMAC0_TX_PAUSE_OFF_INT_BIT)
-+					tp->rx_pause_off_cnt++;
-+				if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
-+					tp->rx_overrun_cnt++;
-+				if (status4 & GMAC0_STATUS_CHANGE_INT_BIT)
-+					tp->status_changed_cnt++;
-+			}
-+		}
-+		else if (tp->port_id == 1)
-+		{
-+			if ((status4 & G1_INTR4_BITS) && (tp->intr4_enabled & G1_INTR4_BITS))
-+			{
-+				if (status4 & GMAC1_RESERVED_INT_BIT)
-+					printk("GMAC1_RESERVED_INT_BIT is ON\n");
-+				if (status4 & GMAC1_MIB_INT_BIT)
-+					tp->mib_full_cnt++;
-+				if (status4 & GMAC1_RX_PAUSE_ON_INT_BIT)
-+				{
-+					//printk("Gmac pause on\n");
-+					tp->rx_pause_on_cnt++;
-+				}
-+				if (status4 & GMAC1_TX_PAUSE_ON_INT_BIT)
-+				{
-+					//printk("Gmac pause on\n");
-+					tp->tx_pause_on_cnt++;
-+				}
-+				if (status4 & GMAC1_RX_PAUSE_OFF_INT_BIT)
-+				{
-+					//printk("Gmac pause off\n");
-+					tp->rx_pause_off_cnt++;
-+				}
-+				if (status4 & GMAC1_TX_PAUSE_OFF_INT_BIT)
-+				{
-+					//printk("Gmac pause off\n");
-+					tp->rx_pause_off_cnt++;
-+				}
-+				if (status4 & GMAC1_RX_OVERRUN_INT_BIT)
-+				{
-+					//printk("Gmac Rx Overrun \n");
-+					tp->rx_overrun_cnt++;
-+				}
-+				if (status4 & GMAC1_STATUS_CHANGE_INT_BIT)
-+					tp->status_changed_cnt++;
-+			}
-+		}
-+#if 0
-+		if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
-+		{
-+			// unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+//			mac_stop_rxdma(tp->sc);
-+			gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
-+				tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
-+
-+			gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
-+				SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
-+			toe_gmac_fill_free_q();
-+			tp->sw_fq_empty_cnt++;
-+
-+			gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
-+				SWFQ_EMPTY_INT_BIT);
-+//#if 0
-+/*			if (netif_running(dev))
-+				toe_gmac_handle_default_rxq(dev, tp);
-+			printk("SWFQ_EMPTY_INT_BIT is ON!\n");	// should not be happened */
-+//#endif
-+		}
-+#endif
-+	}
-+#endif	//INTERRUPT_SELECT
-+	toe_gmac_enable_interrupt(tp->irq);
-+//enable gmac rx function when do RFC 2544
-+#ifdef IxscriptMate_1518
-+	if (storlink_ctl.pauseoff == 1)
-+	{
-+		GMAC_CONFIG0_T config0;
-+		config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
-+		config0.bits.dis_rx = 0;
-+		writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+		config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
-+		config0.bits.dis_rx = 0;
-+		writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+	}
-+#endif
-+	//printk("gmac_interrupt complete!\n\n");
-+//	return IRQ_RETVAL(handled);
-+	return	IRQ_RETVAL(1);
-+#ifdef CONFIG_SL_NAPI
-+}
-+#endif
-+}
-+
-+/*----------------------------------------------------------------------
-+*	toe_gmac_handle_default_rxq
-+*	(1) Get rx Buffer for default Rx queue
-+*	(2) notify or call upper-routine to handle it
-+*	(3) get a new buffer and insert it into SW free queue
-+*	(4) Note: The SW free queue Read-Write Pointer should be locked when accessing
-+*----------------------------------------------------------------------*/
-+//static inline void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
-+static void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
-+{
-+	TOE_INFO_T			*toe;
-+    GMAC_RXDESC_T   	*curr_desc;
-+	struct sk_buff 		*skb;
-+    DMA_RWPTR_T			rwptr;
-+	unsigned int 		pkt_size;
-+	int					max_cnt;
-+	unsigned int        desc_count;
-+	unsigned int        good_frame, chksum_status, rx_status;
-+	struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
-+
-+//when do ixia RFC 2544 test and packet size is select 1518 bytes,disable gmace rx function immediately after one interrupt come in.
-+#ifdef IxscriptMate_1518
-+	if (storlink_ctl.pauseoff == 1)
-+	{
-+		GMAC_CONFIG0_T config0;
-+		config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
-+		config0.bits.dis_rx = 1;
-+		writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+		config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
-+		config0.bits.dis_rx = 1;
-+		writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+	}
-+#endif
-+	rwptr.bits32 = readl(&tp->default_qhdr->word1);
-+#if 0
-+	if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
-+	{
-+		mac_stop_txdma((struct net_device *)tp->dev);
-+		printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
-+				rwptr.bits32, tp->rx_rwptr.bits.rptr);
-+		while(1);
-+	}
-+#endif
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	max_cnt = DEFAULT_RXQ_MAX_CNT;
-+	while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr)
-+//	while (rwptr.bits.rptr != rwptr.bits.wptr)
-+	{
-+//if packet size is not 1518 for RFC 2544,enable gmac rx function.The other packet size have RX workaround.
-+#ifdef IxscriptMate_1518
-+    	if (storlink_ctl.pauseoff == 1)
-+		{
-+			if (pkt_size != 1514)
-+			{
-+						GMAC_CONFIG0_T config0;
-+						config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
-+						config0.bits.dis_rx = 0;
-+						writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+						config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
-+						config0.bits.dis_rx = 0;
-+						writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+			}
-+		}
-+#endif
-+    	curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
-+//		consistent_sync(curr_desc, sizeof(GMAC_RXDESC_T), PCI_DMA_FROMDEVICE);
-+		tp->default_q_cnt++;
-+    	tp->rx_curr_desc = (unsigned int)curr_desc;
-+    	rx_status = curr_desc->word0.bits.status;
-+    	chksum_status = curr_desc->word0.bits.chksum_status;
-+    	tp->rx_status_cnt[rx_status]++;
-+    	tp->rx_chksum_cnt[chksum_status]++;
-+        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
-+		desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
-+		good_frame=1;
-+		if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
-+			|| (pkt_size < 60)
-+		    || (chksum_status & 0x4)
-+			|| rx_status)
-+		{
-+			good_frame = 0;
-+			if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
-+				printk("%s::derr (GMAC-%d)!!!\n", __func__, tp->port_id);
-+			if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
-+				printk("%s::perr (GMAC-%d)!!!\n", __func__, tp->port_id);
-+			if (rx_status)
-+			{
-+				if (rx_status == 4 || rx_status == 7)
-+					isPtr->rx_crc_errors++;
-+//				printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
-+			}
-+#ifdef SL351x_GMAC_WORKAROUND
-+			else if (pkt_size < 60)
-+			{
-+				if (tp->short_frames_cnt < GMAC_SHORT_FRAME_THRESHOLD)
-+					tp->short_frames_cnt++;
-+				if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
-+				{
-+					GMAC_CONFIG0_T config0;
-+					config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
-+					config0.bits.dis_rx = 1;
-+					writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+					config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
-+					config0.bits.dis_rx = 1;
-+					writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+				}
-+			}
-+#endif
-+//			if (chksum_status)
-+//				printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
-+			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
-+			dev_kfree_skb_irq(skb);
-+		}
-+		if (good_frame)
-+		{
-+			if (curr_desc->word0.bits.drop)
-+				printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
-+//			if (chksum_status)
-+//				printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
-+
-+	    	/* get frame information from the first descriptor of the frame */
-+#ifdef SL351x_GMAC_WORKAROUND
-+			if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
-+			{
-+				GMAC_CONFIG0_T config0;
-+				config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
-+				config0.bits.dis_rx = 0;
-+				writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+				config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
-+				config0.bits.dis_rx = 0;
-+				writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+			}
-+			tp->short_frames_cnt = 0;
-+#endif
-+			isPtr->rx_packets++;
-+			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr - SKB_RESERVE_BYTES)));
-+			if (!skb)
-+			{
-+				printk("Fatal Error!!skb==NULL\n");
-+				goto next_rx;
-+			}
-+			tp->curr_rx_skb = skb;
-+			// consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
-+
-+	//		curr_desc->word2.buf_adr = 0;
-+
-+			skb_reserve (skb, RX_INSERT_BYTES);	/* 16 byte align the IP fields. */
-+			skb_put(skb, pkt_size);
-+			skb->dev = dev;
-+			if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
-+			{
-+				skb->ip_summed = CHECKSUM_UNNECESSARY;
-+#ifdef CONFIG_SL351x_NAT
-+				if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
-+				{
-+					struct iphdr	*ip_hdr;
-+					ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
-+					sl351x_nat_input(skb,
-+									tp->port_id,
-+									(void *)curr_desc->word3.bits.l3_offset,
-+								  	(void *)curr_desc->word3.bits.l4_offset);
-+				}
-+#endif
-+				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
-+#if 0
-+#ifdef CONFIG_SL351x_RXTOE
-+				if (storlink_ctl.rx_max_pktsize) {
-+					struct iphdr	*ip_hdr;
-+					struct tcphdr	*tcp_hdr;
-+					int ip_hdrlen;
-+
-+ 					ip_hdr = (struct iphdr*)&(skb->data[0]);
-+					if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
-+					   ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
-+						ip_hdrlen = ip_hdr->ihl << 2;
-+						tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
-+						if (tcp_hdr->syn) {
-+							struct toe_conn* connection = init_toeq(ip_hdr->version,
-+									ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
-+							TCP_SKB_CB(skb)->connection = connection;
-+							//	hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
-+							//		printk("%s::skb data %x, conn %x, mode %x\n",
-+							//			__func__, skb->data, connection, connection->mode);
-+						}
-+					}
-+				}
-+#endif
-+#endif
-+			}
-+			else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
-+			{
-+				skb->ip_summed = CHECKSUM_UNNECESSARY;
-+#ifdef CONFIG_SL351x_NAT
-+				if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
-+				{
-+					struct iphdr		*ip_hdr;
-+					//struct tcphdr		*tcp_hdr;
-+					ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
-+					//tcp_hdr = (struct tcphdr *)&(skb->data[curr_desc->word3.bits.l4_offset]);
-+					if (ip_hdr->protocol == IPPROTO_UDP)
-+					{
-+						sl351x_nat_input(skb,
-+										tp->port_id,
-+										(void *)curr_desc->word3.bits.l3_offset,
-+								  		(void *)curr_desc->word3.bits.l4_offset);
-+					}
-+					else if (ip_hdr->protocol == IPPROTO_GRE)
-+					{
-+						sl351x_nat_input(skb,
-+									tp->port_id,
-+									(void *)curr_desc->word3.bits.l3_offset,
-+								  	(void *)curr_desc->word3.bits.l4_offset);
-+					}
-+				}
-+#endif
-+				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
-+			}
-+			else
-+			{
-+				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
-+			}
-+
-+			netif_rx(skb);  /* socket rx */
-+			dev->last_rx = jiffies;
-+
-+			isPtr->rx_bytes += pkt_size;
-+
-+        }
-+
-+next_rx:
-+		// advance one for Rx default Q 0/1
-+		rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
-+		SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
-+     	tp->rx_rwptr.bits32 = rwptr.bits32;
-+
-+		toe_gmac_fill_free_q();
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_get_phy_vendor
-+*----------------------------------------------------------------------*/
-+static unsigned int gmac_get_phy_vendor(int phy_addr)
-+{
-+    unsigned int	reg_val;
-+    reg_val=(mii_read(phy_addr,0x02) << 16) + mii_read(phy_addr,0x03);
-+    return reg_val;
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_set_phy_status
-+*----------------------------------------------------------------------*/
-+void gmac_set_phy_status(struct net_device *dev)
-+{
-+	GMAC_INFO_T *tp = dev->priv;
-+	GMAC_STATUS_T   status;
-+	unsigned int    reg_val, ability,wan_port_id;
-+	unsigned int    i = 0;
-+
-+#ifdef VITESSE_G5SWITCH
-+	if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1)){
-+#if 0
-+		rcv_mask = SPI_read(2,0,0x10);			// Receive mask
-+		rcv_mask |= 0x4F;
-+		for(i=0;i<4;i++){
-+			reg_val = BIT(26)|(i<<21)|(10<<16);
-+			SPI_write(3,0,1,reg_val);
-+			msleep(10);
-+			reg_val = SPI_read(3,0,2);
-+			if(reg_val & 0x0c00){
-+				printk("Port%d:Giga mode\n",i);
-+				SPI_write(1,i,0x00,0x300701B1);
-+				SPI_write(1,i,0x00,0x10070181);
-+				switch_pre_link[i]=LINK_UP;
-+				switch_pre_speed[i]=GMAC_SPEED_1000;
-+			}
-+			else{
-+				reg_val = BIT(26)|(i<<21)|(5<<16);
-+				SPI_write(3,0,1,reg_val);
-+				msleep(10);
-+				ability = (reg_val = SPI_read(3,0,2)&0x5e0) >>5;
-+				if ((ability & 0x0C)) /* 100M full duplex */
-+				{
-+					SPI_write(1,i,0x00,0x30050472);
-+					SPI_write(1,i,0x00,0x10050442);
-+					printk("Port%d:100M\n",i);
-+					switch_pre_link[i]=LINK_UP;
-+				switch_pre_speed[i]=GMAC_SPEED_100;
-+				}
-+				else if((ability & 0x03)) /* 10M full duplex */
-+				{
-+					SPI_write(1,i,0x00,0x30050473);
-+					SPI_write(1,i,0x00,0x10050443);
-+					printk("Port%d:10M\n",i);
-+					switch_pre_link[i]=LINK_UP;
-+					switch_pre_speed[i]=GMAC_SPEED_10;
-+				}
-+				else{
-+					SPI_write(1,i,0x00,BIT(16));			// disable RX
-+					SPI_write(5,0,0x0E,BIT(i));			// dicard packet
-+					while((SPI_read(5,0,0x0C)&BIT(i))==0)		// wait to be empty
-+						msleep(1);
-+
-+					SPI_write(1,i,0x00,0x20000030);			// PORT_RST
-+					switch_pre_link[i]=LINK_DOWN;
-+					switch_pre_speed[i]=GMAC_SPEED_10;
-+					rcv_mask &= ~BIT(i);
-+					SPI_write(2,0,0x10,rcv_mask);			// Disable Receive
-+				}
-+			}
-+		}
-+#endif
-+		gmac_get_switch_status(dev);
-+		gmac_write_reg(tp->base_addr, GMAC_STATUS, 0x7d, 0x0000007f);
-+//		SPI_write(2,0,0x10,rcv_mask);			// Enable Receive
-+		return ;
-+	}
-+#endif
-+
-+	reg_val = gmac_get_phy_vendor(tp->phy_addr);
-+	printk("GMAC-%d Addr %d Vendor ID: 0x%08x\n", tp->port_id, tp->phy_addr, reg_val);
-+
-+	switch (tp->phy_mode)
-+	{
-+		case GMAC_PHY_GMII:
-+		mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
-+		#ifdef CONFIG_SL3516_ASIC
-+		mii_write(tp->phy_addr,0x09,0x0300); /* advertise 1000M full/half duplex */
-+		#else
-+		mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M full/half duplex */
-+		#endif
-+		break;
-+		case GMAC_PHY_RGMII_100:
-+		mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
-+		mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M */
-+		break;
-+		case GMAC_PHY_RGMII_1000:
-+		mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
-+		#ifdef CONFIG_SL3516_ASIC
-+		mii_write(tp->phy_addr,0x09,0x0300); /* advertise 1000M full/half duplex */
-+		#else
-+		mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M full/half duplex */
-+		#endif
-+		break;
-+		case GMAC_PHY_MII:
-+		default:
-+		mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
-+		mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M */
-+		break;
-+	}
-+
-+	mii_write(tp->phy_addr,0x18,0x0041);	// Phy active led
-+	if (tp->auto_nego_cfg)
-+	{
-+		reg_val = 0x1200 | (1 << 15);
-+		mii_write(tp->phy_addr,0x00,reg_val); /* Enable and Restart Auto-Negotiation */
-+		mdelay(500);
-+		reg_val &= ~(1 << 15);
-+		mii_write(tp->phy_addr, 0x00, reg_val);
-+	}
-+	else
-+	{
-+		reg_val = 0;
-+		reg_val |= (tp->full_duplex_cfg) ? (1 << 8) : 0;
-+		reg_val |= (tp->speed_cfg == GMAC_SPEED_1000) ? (1 << 6) : 0;
-+		reg_val |= (tp->speed_cfg == GMAC_SPEED_100) ? (1 << 13) : 0;
-+		mii_write(tp->phy_addr, 0x00, reg_val);
-+		mdelay(100);
-+
-+		reg_val |= (1 << 15);	// Reset PHY;
-+		mii_write(tp->phy_addr, 0x00, reg_val);
-+	}
-+
-+	status.bits32 = 0;
-+	/* set PHY operation mode */
-+	status.bits.mii_rmii = tp->phy_mode;
-+	status.bits.reserved = 1;
-+	mdelay(100);
-+	while (((reg_val=mii_read(tp->phy_addr,0x01)) & 0x00000004)!=0x04)
-+	{
-+		msleep(100);
-+		i++;
-+		if (i > 30)
-+		break;
-+	}
-+	if (i>30)
-+	{
-+		tp->pre_phy_status = LINK_DOWN;
-+		status.bits.link = LINK_DOWN;
-+		//		clear_bit(__LINK_STATE_START, &dev->state);
-+		printk("Link Down (0x%04x) ", reg_val);
-+		if(Giga_switch == 1)
-+		{
-+				wan_port_id = 1;
-+#ifdef CONFIG_SL351x_SYSCTL
-+				storlink_ctl.link[ wan_port_id] = 0;
-+#endif
-+		}
-+		else
-+		{
-+#ifdef CONFIG_SL351x_SYSCTL
-+				storlink_ctl.link[ tp->port_id] = 0;
-+#endif
-+		}
-+	}
-+	else
-+	{
-+		tp->pre_phy_status = LINK_UP;
-+		status.bits.link = LINK_UP;
-+		//		set_bit(__LINK_STATE_START, &dev->state);
-+		printk("Link Up (0x%04x) ",reg_val);
-+		if(Giga_switch == 1)
-+		{
-+				wan_port_id = 1;
-+#ifdef CONFIG_SL351x_SYSCTL
-+				storlink_ctl.link[ wan_port_id] = 1;
-+#endif
-+		}
-+		else
-+		{
-+#ifdef CONFIG_SL351x_SYSCTL
-+				storlink_ctl.link[ tp->port_id] = 1;
-+#endif
-+		}
-+	}
-+	//    value = mii_read(PHY_ADDR,0x05);
-+
-+	ability = (mii_read(tp->phy_addr,0x05) & 0x05E0) >> 5;
-+
-+	//#ifdef CONFIG_SL3516_ASIC
-+	reg_val = mii_read(tp->phy_addr,10);
-+	printk("MII REG 10 = 0x%x\n",reg_val);
-+
-+	if ((reg_val & 0x0800) == 0x0800)
-+	{
-+		status.bits.duplex = 1;
-+		status.bits.speed = 2;
-+		if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
-+		status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
-+
-+		printk(" 1000M/Full \n");
-+	}
-+	else if ((reg_val & 0x0400) == 0x0400)
-+	{
-+		status.bits.duplex = 0;
-+		status.bits.speed = 2;
-+		if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
-+		status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
-+
-+		printk(" 1000M/Half \n");
-+	}
-+	//#endif
-+	else
-+	{
-+		#ifdef CONFIG_SL3516_ASIC
-+		if (status.bits.mii_rmii == GMAC_PHY_RGMII_1000)
-+		status.bits.mii_rmii = GMAC_PHY_RGMII_100;
-+		#endif
-+		printk("MII REG 5 (bit 5:15) = 0x%x\n", ability);
-+		if ((ability & 0x08)==0x08) /* 100M full duplex */
-+		{
-+			status.bits.duplex = 1;
-+			status.bits.speed = 1;
-+			printk(" 100M/Full\n");
-+
-+		}
-+		else if ((ability & 0x04)==0x04) /* 100M half duplex */
-+		{
-+			status.bits.duplex = 0;
-+			status.bits.speed = 1;
-+			printk(" 100M/Half\n");
-+
-+		}
-+		else if ((ability & 0x02)==0x02) /* 10M full duplex */
-+		{
-+			status.bits.duplex = 1;
-+			status.bits.speed = 0;
-+			printk(" 10M/Full\n");
-+
-+		}
-+		else if ((ability & 0x01)==0x01) /* 10M half duplex */
-+		{
-+			status.bits.duplex = 0;
-+			status.bits.speed = 0;
-+			printk(" 10M/Half\n");
-+
-+		}
-+	}
-+	if ((ability & 0x20)==0x20)
-+	{
-+		tp->flow_control_enable = 1;
-+		printk("Flow Control Enable.\n");
-+	}
-+	else
-+	{
-+		tp->flow_control_enable = 0;
-+		printk("Flow Control Disable.\n");
-+	}
-+	tp->full_duplex_status = status.bits.duplex;
-+	tp->speed_status = status.bits.speed;
-+	if (!tp->auto_nego_cfg)
-+	{
-+		status.bits.duplex = tp->full_duplex_cfg;
-+		status.bits.speed = tp->speed_cfg;
-+	}
-+	toe_gmac_disable_tx_rx(dev);
-+	mdelay(10);
-+	gmac_write_reg(tp->base_addr, GMAC_STATUS, status.bits32, 0x0000007f);
-+	toe_gmac_enable_tx_rx(dev);
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_phy_thread
-+*----------------------------------------------------------------------*/
-+static int gmac_phy_thread (void *data)
-+{
-+	struct net_device   *dev = data;
-+	GMAC_INFO_T *tp = dev->priv;
-+	unsigned long       timeout;
-+
-+    daemonize("%s", dev->name);
-+	allow_signal(SIGTERM);
-+//	reparent_to_init();
-+//	spin_lock_irq(¤t->sigmask_lock);
-+//	sigemptyset(¤t->blocked);
-+//	recalc_sigpending(current);
-+//	spin_unlock_irq(¤t->sigmask_lock);
-+//	strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
-+//	current->comm[sizeof(current->comm) - 1] = '\0';
-+
-+	while (1)
-+	{
-+	    timeout = next_tick;
-+		do
-+		{
-+			timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
-+		} while (!signal_pending (current) && (timeout > 0));
-+
-+		if (signal_pending (current))
-+		{
-+//			spin_lock_irq(¤t->sigmask_lock);
-+			flush_signals(current);
-+//			spin_unlock_irq(¤t->sigmask_lock);
-+		}
-+
-+		if (tp->time_to_die)
-+			break;
-+
-+		// printk("%s : Polling MAC %d PHY Status...\n",__func__, tp->port_id);
-+		rtnl_lock ();
-+		if (tp->auto_nego_cfg){
-+#ifdef VITESSE_G5SWITCH
-+        		if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1))
-+	        		gmac_get_switch_status(dev);
-+        		else
-+#endif
-+        			gmac_get_phy_status(dev); //temp remove
-+        	}
-+		rtnl_unlock ();
-+	}
-+	complete_and_exit (&tp->thr_exited, 0);
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_get_switch_status
-+*----------------------------------------------------------------------*/
-+#ifdef VITESSE_G5SWITCH
-+void gmac_get_switch_status(struct net_device *dev)
-+{
-+	GMAC_INFO_T *tp = dev->priv;
-+	GMAC_CONFIG0_T	config0,config0_mask;
-+	unsigned int	switch_port_id;
-+	int get_link=0;
-+
-+	get_link = Get_Set_port_status();
-+	if(get_link){				// link
-+		if(ever_dwon){
-+			ever_dwon = 0;
-+			toe_gmac_enable_tx_rx(dev);
-+			netif_wake_queue(dev);
-+			set_bit(__LINK_STATE_START, &dev->state);
-+		}
-+	}
-+	else{					// all down
-+		//printk("All link down\n");
-+		ever_dwon=1;
-+		netif_stop_queue(dev);
-+		toe_gmac_disable_tx_rx(dev);
-+		clear_bit(__LINK_STATE_START, &dev->state);
-+	}
-+
-+	if ( tp->port_id == 1 )
-+		switch_port_id = 0;
-+#ifdef CONFIG_SL351x_SYSCTL
-+	if (get_link)
-+	{
-+		storlink_ctl.link[switch_port_id] = 1;
-+	}
-+	else
-+	{
-+		storlink_ctl.link[switch_port_id] = 0;
-+	}
-+	if (storlink_ctl.pauseoff == 1)
-+		{
-+			if (tp->flow_control_enable == 1)
-+			{
-+				config0.bits32 = 0;
-+				config0_mask.bits32 = 0;
-+				config0.bits.tx_fc_en = 0; /* disable tx flow control */
-+				config0.bits.rx_fc_en = 0; /* disable rx flow control */
-+				config0_mask.bits.tx_fc_en = 1;
-+				config0_mask.bits.rx_fc_en = 1;
-+				gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
-+				printk("Disable SWITCH Flow Control...\n");
-+			}
-+				tp->flow_control_enable = 0;
-+		}
-+		else
-+#endif
-+		{
-+			if (tp->flow_control_enable == 0)
-+			{
-+				config0.bits32 = 0;
-+				config0_mask.bits32 = 0;
-+				config0.bits.tx_fc_en = 1; /* enable tx flow control */
-+				config0.bits.rx_fc_en = 1; /* enable rx flow control */
-+				config0_mask.bits.tx_fc_en = 1;
-+				config0_mask.bits.rx_fc_en = 1;
-+				gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
-+				printk("Enable SWITCH Flow Control...\n");
-+			}
-+			tp->flow_control_enable = 1;
-+		}
-+	return ;
-+
-+}
-+#endif
-+
-+/*----------------------------------------------------------------------
-+* gmac_get_phy_status
-+*----------------------------------------------------------------------*/
-+void gmac_get_phy_status(struct net_device *dev)
-+{
-+	GMAC_INFO_T *tp = dev->priv;
-+	GMAC_CONFIG0_T	config0,config0_mask;
-+	GMAC_STATUS_T   status, old_status;
-+	unsigned int    reg_val,ability,wan_port_id;
-+
-+	old_status.bits32 = status.bits32 = gmac_read_reg(tp->base_addr, GMAC_STATUS);
-+
-+
-+	/* read PHY status register */
-+	reg_val = mii_read(tp->phy_addr,0x01);
-+	if ((reg_val & 0x0024) == 0x0024) /* link is established and auto_negotiate process completed */
-+	{
-+		ability = (mii_read(tp->phy_addr,0x05) & 0x05E0) >> 5;
-+		/* read PHY Auto-Negotiation Link Partner Ability Register */
-+		#ifdef CONFIG_SL3516_ASIC
-+		reg_val = mii_read(tp->phy_addr,10);
-+		if ((reg_val & 0x0800) == 0x0800)
-+		{
-+			status.bits.duplex = 1;
-+			status.bits.speed = 2;
-+			if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
-+			status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
-+		}
-+		else if ((reg_val & 0x0400) == 0x0400)
-+		{
-+			status.bits.duplex = 0;
-+			status.bits.speed = 2;
-+			if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
-+			status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
-+		}
-+		else
-+		#endif
-+		{
-+			#ifdef CONFIG_SL3516_ASIC
-+			if (status.bits.mii_rmii == GMAC_PHY_RGMII_1000)
-+			status.bits.mii_rmii = GMAC_PHY_RGMII_100;
-+			#endif
-+			if ((ability & 0x08)==0x08) /* 100M full duplex */
-+			{
-+				status.bits.duplex = 1;
-+				status.bits.speed = 1;
-+			}
-+			else if ((ability & 0x04)==0x04) /* 100M half duplex */
-+			{
-+				status.bits.duplex = 0;
-+				status.bits.speed = 1;
-+			}
-+			else if ((ability & 0x02)==0x02) /* 10M full duplex */
-+			{
-+				status.bits.duplex = 1;
-+				status.bits.speed = 0;
-+			}
-+			else if ((ability & 0x01)==0x01) /* 10M half duplex */
-+			{
-+				status.bits.duplex = 0;
-+				status.bits.speed = 0;
-+			}
-+		}
-+		status.bits.link = LINK_UP; /* link up */
-+		if(Giga_switch==1)
-+		{
-+				wan_port_id = 1;
-+#ifdef CONFIG_SL351x_SYSCTL
-+				storlink_ctl.link[ wan_port_id] = 1;
-+		}
-+		else
-+		{
-+				storlink_ctl.link[ tp->port_id] = 1;
-+#endif
-+		}
-+		if ((ability & 0x20)==0x20)
-+		{
-+			if (tp->flow_control_enable == 0)
-+			{
-+				config0.bits32 = 0;
-+				config0_mask.bits32 = 0;
-+				config0.bits.tx_fc_en = 1; /* enable tx flow control */
-+				config0.bits.rx_fc_en = 1; /* enable rx flow control */
-+				config0_mask.bits.tx_fc_en = 1;
-+				config0_mask.bits.rx_fc_en = 1;
-+				gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
-+				printk("GMAC-%d Flow Control Enable.\n", tp->port_id);
-+			}
-+			tp->flow_control_enable = 1;
-+		}
-+		else
-+		{
-+			if (tp->flow_control_enable == 1)
-+			{
-+				config0.bits32 = 0;
-+				config0_mask.bits32 = 0;
-+				config0.bits.tx_fc_en = 0; /* disable tx flow control */
-+				config0.bits.rx_fc_en = 0; /* disable rx flow control */
-+				config0_mask.bits.tx_fc_en = 1;
-+				config0_mask.bits.rx_fc_en = 1;
-+				gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
-+				printk("GMAC-%d Flow Control Disable.\n", tp->port_id);
-+			}
-+			tp->flow_control_enable = 0;
-+		}
-+
-+		if (tp->pre_phy_status == LINK_DOWN)
-+		{
-+			printk("GMAC-%d LINK_UP......\n",tp->port_id);
-+			tp->pre_phy_status = LINK_UP;
-+		}
-+	}
-+	else
-+	{
-+		status.bits.link = LINK_DOWN; /* link down */
-+		if(Giga_switch == 1)
-+		{
-+				wan_port_id = 1;
-+#ifdef CONFIG_SL351x_SYSCTL
-+				storlink_ctl.link[ wan_port_id] = 0;
-+		}
-+		else
-+		{
-+				storlink_ctl.link[ tp->port_id] = 0;
-+#endif
-+		}
-+		if (tp->pre_phy_status == LINK_UP)
-+		{
-+			printk("GMAC-%d LINK_Down......\n",tp->port_id);
-+			tp->pre_phy_status = LINK_DOWN;
-+		}
-+	}
-+
-+	tp->full_duplex_status = status.bits.duplex;
-+	tp->speed_status = status.bits.speed;
-+	if (!tp->auto_nego_cfg)
-+	{
-+		status.bits.duplex = tp->full_duplex_cfg;
-+		status.bits.speed = tp->speed_cfg;
-+	}
-+
-+	if (old_status.bits32 != status.bits32)
-+	{
-+		netif_stop_queue(dev);
-+		toe_gmac_disable_tx_rx(dev);
-+		clear_bit(__LINK_STATE_START, &dev->state);
-+		printk("GMAC-%d Change Status Bits 0x%x-->0x%x\n",tp->port_id, old_status.bits32, status.bits32);
-+		mdelay(10); // let GMAC consume packet
-+		gmac_write_reg(tp->base_addr, GMAC_STATUS, status.bits32, 0x0000007f);
-+		if (status.bits.link == LINK_UP)
-+		{
-+			toe_gmac_enable_tx_rx(dev);
-+			netif_wake_queue(dev);
-+			set_bit(__LINK_STATE_START, &dev->state);
-+		}
-+	}
-+}
-+
-+/***************************************/
-+/* define GPIO module base address     */
-+/***************************************/
-+#define GPIO_BASE_ADDR  (IO_ADDRESS(SL2312_GPIO_BASE))
-+#define GPIO_BASE_ADDR1  (IO_ADDRESS(SL2312_GPIO_BASE1))
-+
-+/* define GPIO pin for MDC/MDIO */
-+#ifdef CONFIG_SL3516_ASIC
-+#define H_MDC_PIN           22
-+#define H_MDIO_PIN          21
-+#define G_MDC_PIN           22
-+#define G_MDIO_PIN          21
-+#else
-+#define H_MDC_PIN           3
-+#define H_MDIO_PIN          2
-+#define G_MDC_PIN           0
-+#define G_MDIO_PIN          1
-+#endif
-+
-+//#define GPIO_MDC             0x80000000
-+//#define GPIO_MDIO            0x00400000
-+
-+static unsigned int GPIO_MDC = 0;
-+static unsigned int GPIO_MDIO = 0;
-+static unsigned int GPIO_MDC_PIN = 0;
-+static unsigned int GPIO_MDIO_PIN = 0;
-+
-+// For PHY test definition!!
-+#define LPC_EECK		0x02
-+#define LPC_EDIO		0x04
-+#define LPC_GPIO_SET		3
-+#define LPC_BASE_ADDR		IO_ADDRESS(IT8712_IO_BASE)
-+#define inb_gpio(x)		inb(LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
-+#define outb_gpio(x, y)		outb(y, LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
-+
-+enum GPIO_REG
-+{
-+    GPIO_DATA_OUT   = 0x00,
-+    GPIO_DATA_IN    = 0x04,
-+    GPIO_PIN_DIR    = 0x08,
-+    GPIO_BY_PASS    = 0x0c,
-+    GPIO_DATA_SET   = 0x10,
-+    GPIO_DATA_CLEAR = 0x14,
-+};
-+/***********************/
-+/*    MDC : GPIO[31]   */
-+/*    MDIO: GPIO[22]   */
-+/***********************/
-+
-+/***************************************************
-+* All the commands should have the frame structure:
-+*

-+****************************************************/
-+
-+/*****************************************************************
-+* Inject a bit to NWay register through CSR9_MDC,MDIO
-+*******************************************************************/
-+void mii_serial_write(char bit_MDO) // write data into mii PHY
-+{
-+#ifdef CONFIG_SL2312_LPC_IT8712
-+	unsigned char iomode,status;
-+
-+	iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
-+	iomode |= (LPC_EECK|LPC_EDIO) ;				// Set EECK,EDIO,EECS output
-+	LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
-+
-+	if(bit_MDO)
-+	{
-+		status = inb_gpio( LPC_GPIO_SET);
-+		status |= LPC_EDIO ;		//EDIO high
-+		outb_gpio(LPC_GPIO_SET, status);
-+	}
-+	else
-+	{
-+		status = inb_gpio( LPC_GPIO_SET);
-+		status &= ~(LPC_EDIO) ;		//EDIO low
-+		outb_gpio(LPC_GPIO_SET, status);
-+	}
-+
-+	status |= LPC_EECK ;		//EECK high
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	status &= ~(LPC_EECK) ;		//EECK low
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+#else
-+    unsigned int addr;
-+    unsigned int value;
-+
-+    addr = GPIO_BASE_ADDR + GPIO_PIN_DIR;
-+    value = readl(addr) | GPIO_MDC | GPIO_MDIO; /* set MDC/MDIO Pin to output */
-+    writel(value,addr);
-+    if(bit_MDO)
-+    {
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+        writel(GPIO_MDIO,addr); /* set MDIO to 1 */
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+        writel(GPIO_MDC,addr); /* set MDC to 1 */
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+        writel(GPIO_MDC,addr); /* set MDC to 0 */
-+    }
-+    else
-+    {
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+        writel(GPIO_MDIO,addr); /* set MDIO to 0 */
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
-+        writel(GPIO_MDC,addr); /* set MDC to 1 */
-+        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+        writel(GPIO_MDC,addr); /* set MDC to 0 */
-+    }
-+
-+#endif
-+}
-+
-+/**********************************************************************
-+* read a bit from NWay register through CSR9_MDC,MDIO
-+***********************************************************************/
-+unsigned int mii_serial_read(void) // read data from mii PHY
-+{
-+#ifdef CONFIG_SL2312_LPC_IT8712
-+  	unsigned char iomode,status;
-+	unsigned int value ;
-+
-+	iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
-+	iomode &= ~(LPC_EDIO) ;		// Set EDIO input
-+	iomode |= (LPC_EECK) ;		// Set EECK,EECS output
-+	LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
-+
-+	status = inb_gpio( LPC_GPIO_SET);
-+	status |= LPC_EECK ;		//EECK high
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	status &= ~(LPC_EECK) ;		//EECK low
-+	outb_gpio(LPC_GPIO_SET, status);
-+
-+	value = inb_gpio( LPC_GPIO_SET);
-+
-+	value = value>>2 ;
-+	value &= 0x01;
-+
-+	return value ;
-+
-+#else
-+    unsigned int *addr;
-+    unsigned int value;
-+
-+    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_PIN_DIR);
-+    value = readl(addr) & ~GPIO_MDIO; //0xffbfffff;   /* set MDC to output and MDIO to input */
-+    writel(value,addr);
-+
-+    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_SET);
-+    writel(GPIO_MDC,addr); /* set MDC to 1 */
-+    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
-+    writel(GPIO_MDC,addr); /* set MDC to 0 */
-+
-+    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_IN);
-+    value = readl(addr);
-+    value = (value & (1<> GPIO_MDIO_PIN;
-+    return(value);
-+
-+#endif
-+}
-+
-+/***************************************
-+* preamble + ST
-+***************************************/
-+void mii_pre_st(void)
-+{
-+    unsigned char i;
-+
-+    for(i=0;i<32;i++) // PREAMBLE
-+        mii_serial_write(1);
-+    mii_serial_write(0); // ST
-+    mii_serial_write(1);
-+}
-+
-+
-+/******************************************
-+* Read MII register
-+* phyad -> physical address
-+* regad -> register address
-+***************************************** */
-+unsigned int mii_read(unsigned char phyad,unsigned char regad)
-+{
-+    unsigned int i,value;
-+    unsigned int bit;
-+
-+    if (phyad == GPHY_ADDR)
-+    {
-+        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
-+        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
-+    }
-+    else
-+    {
-+        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
-+        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
-+    }
-+    GPIO_MDC = (1<>(4-i)) & 0x01) ? 1 :0 ;
-+        mii_serial_write(bit);
-+    }
-+
-+    for (i=0;i<5;i++) { // REGAD
-+        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
-+        mii_serial_write(bit);
-+    }
-+
-+    mii_serial_read(); // TA_Z
-+//    if((bit=mii_serial_read()) !=0 ) // TA_0
-+//    {
-+//        return(0);
-+//    }
-+    value=0;
-+    for (i=0;i<16;i++) { // READ DATA
-+        bit=mii_serial_read();
-+        value += (bit<<(15-i)) ;
-+    }
-+
-+    mii_serial_write(0); // dumy clock
-+    mii_serial_write(0); // dumy clock
-+
-+	//printk("%s: phy_addr=0x%x reg_addr=0x%x value=0x%x \n",__func__,phyad,regad,value);
-+    return(value);
-+}
-+
-+/******************************************
-+* Write MII register
-+* phyad -> physical address
-+* regad -> register address
-+* value -> value to be write
-+***************************************** */
-+void mii_write(unsigned char phyad,unsigned char regad,unsigned int value)
-+{
-+    unsigned int i;
-+    char bit;
-+
-+	printk("%s: phy_addr=0x%x reg_addr=0x%x value=0x%x \n",__func__,phyad,regad,value);
-+    if (phyad == GPHY_ADDR)
-+    {
-+        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
-+        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
-+    }
-+    else
-+    {
-+        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
-+        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
-+    }
-+    GPIO_MDC = (1<>(4-i)) & 0x01) ? 1 :0 ;
-+        mii_serial_write(bit);
-+    }
-+
-+    for (i=0;i<5;i++) { // REGAD
-+        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
-+        mii_serial_write(bit);
-+    }
-+    mii_serial_write(1); // TA_1
-+    mii_serial_write(0); // TA_0
-+
-+    for (i=0;i<16;i++) { // OUT DATA
-+        bit= ((value>>(15-i)) & 0x01) ? 1 : 0 ;
-+        mii_serial_write(bit);
-+    }
-+    mii_serial_write(0); // dumy clock
-+    mii_serial_write(0); // dumy clock
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_set_rx_mode
-+*----------------------------------------------------------------------*/
-+static void gmac_set_rx_mode(struct net_device *dev)
-+{
-+    GMAC_RX_FLTR_T      filter;
-+	unsigned int        mc_filter[2];	/* Multicast hash filter */
-+    int                 bit_nr;
-+	unsigned int        i;
-+	GMAC_INFO_T 		*tp = dev->priv;
-+
-+//    printk("%s : dev->flags = %x \n",__func__,dev->flags);
-+//    dev->flags |= IFF_ALLMULTI;  /* temp */
-+    filter.bits32 = 0;
-+    filter.bits.error = 0;
-+	if (dev->flags & IFF_PROMISC)
-+	{
-+	    filter.bits.error = 1;
-+        filter.bits.promiscuous = 1;
-+        filter.bits.broadcast = 1;
-+        filter.bits.multicast = 1;
-+        filter.bits.unicast = 1;
-+		mc_filter[1] = mc_filter[0] = 0xffffffff;
-+	}
-+	else if (dev->flags & IFF_ALLMULTI)
-+	{
-+//        filter.bits.promiscuous = 1;
-+        filter.bits.broadcast = 1;
-+        filter.bits.multicast = 1;
-+        filter.bits.unicast = 1;
-+		mc_filter[1] = mc_filter[0] = 0xffffffff;
-+	}
-+	else
-+	{
-+		struct dev_mc_list *mclist;
-+
-+//        filter.bits.promiscuous = 1;
-+        filter.bits.broadcast = 1;
-+        filter.bits.multicast = 1;
-+        filter.bits.unicast = 1;
-+		mc_filter[1] = mc_filter[0] = 0;
-+		for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;i++, mclist = mclist->next)
-+		{
-+            bit_nr = ether_crc(ETH_ALEN,mclist->dmi_addr) & 0x0000003f;
-+            if (bit_nr < 32)
-+            {
-+                mc_filter[0] = mc_filter[0] | (1<base_addr,GMAC_RX_FLTR,filter.bits32,0xffffffff);  //chech base address!!!
-+    gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,mc_filter[0],0xffffffff);
-+    gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,mc_filter[1],0xffffffff);
-+    return;
-+}
-+
-+#ifdef CONFIG_SL_NAPI
-+/*----------------------------------------------------------------------
-+* gmac_rx_poll
-+*----------------------------------------------------------------------*/
-+static int gmac_rx_poll(struct net_device *dev, int *budget)
-+{
-+	TOE_INFO_T			*toe;
-+    GMAC_RXDESC_T   	*curr_desc;
-+	struct sk_buff 		*skb;
-+    DMA_RWPTR_T			rwptr;
-+	unsigned int 		pkt_size;
-+	unsigned int        desc_count;
-+	unsigned int        good_frame, chksum_status, rx_status;
-+	int                 rx_pkts_num = 0;
-+	int                 quota = min(dev->quota, *budget);
-+	GMAC_INFO_T			*tp = (GMAC_INFO_T *)dev->priv;
-+	unsigned int		status4;
-+	volatile DMA_RWPTR_T	fq_rwptr;
-+	int					max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
-+	//unsigned long		rx_old_bytes;
-+	struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
-+	//unsigned long long	rx_time;
-+
-+
-+
-+#if 1
-+	if (do_again)
-+	{
-+			toe_gmac_fill_free_q();
-+			status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+			fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+			//printk("\n%s:: do_again toe_gmac_fill_free_q =======>status4=0x%x =====fq_rwptr =0x%8x======>JKJKJKJKJKJKJKJKJ \n", __func__,status4,fq_rwptr.bits32);
-+			if (fq_rwptr.bits.wptr != fq_rwptr.bits.rptr)
-+			{
-+						//status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+						do_again =0;
-+						//netif_rx_complete(dev);
-+						gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,	0x1);
-+						fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+						rwptr.bits32 = readl(&tp->default_qhdr->word1);
-+			}
-+			else
-+				return 1;
-+	}
-+#endif
-+	rwptr.bits32 = readl(&tp->default_qhdr->word1);
-+#if 0
-+	if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
-+	{
-+		mac_stop_txdma((struct net_device *)tp->dev);
-+		printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
-+				rwptr.bits32, tp->rx_rwptr.bits.rptr);
-+		while(1);
-+	}
-+#endif
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+
-+	fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+	//printk("%s:---Before-------------->Default Queue HW RW ptr (0x%8x),   fq_rwptr =0x%8x \n",__func__,rwptr.bits32,fq_rwptr.bits32 );
-+	//printk("%s:---Before while   rx_pkts_num=%d------rx_finished_idx=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rx_finished_idx,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
-+//	while ((--max_cnt) && (rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
-+
-+	while ((rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
-+	{
-+
-+    	curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
-+		tp->default_q_cnt++;
-+    	tp->rx_curr_desc = (unsigned int)curr_desc;
-+    	rx_status = curr_desc->word0.bits.status;
-+    	chksum_status = curr_desc->word0.bits.chksum_status;
-+    	tp->rx_status_cnt[rx_status]++;
-+    	tp->rx_chksum_cnt[chksum_status]++;
-+        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
-+		desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
-+		good_frame=1;
-+		if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
-+			|| (pkt_size < 60)
-+		    || (chksum_status & 0x4)
-+		    || rx_status )
-+//			|| rx_status || (rwptr.bits.rptr > rwptr.bits.wptr ))
-+		{
-+			good_frame = 0;
-+			if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
-+				printk("%s::derr (GMAC-%d)!!!\n", __func__, tp->port_id);
-+			if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
-+				printk("%s::perr (GMAC-%d)!!!\n", __func__, tp->port_id);
-+			if (rx_status)
-+			{
-+				if (rx_status == 4 || rx_status == 7)
-+					isPtr->rx_crc_errors++;
-+//				printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
-+			}
-+#ifdef SL351x_GMAC_WORKAROUND
-+			else if (pkt_size < 60)
-+			{
-+				if (tp->short_frames_cnt < GMAC_SHORT_FRAME_THRESHOLD)
-+					tp->short_frames_cnt++;
-+				if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
-+				{
-+					GMAC_CONFIG0_T config0;
-+					config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
-+					config0.bits.dis_rx = 1;
-+					writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+					config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
-+					config0.bits.dis_rx = 1;
-+					writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+				}
-+			}
-+#endif
-+//			if (chksum_status)
-+//				printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
-+			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
-+			dev_kfree_skb_irq(skb);
-+		}
-+		if (good_frame)
-+		{
-+			if (curr_desc->word0.bits.drop)
-+				printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
-+//			if (chksum_status)
-+//				printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
-+
-+#ifdef SL351x_GMAC_WORKAROUND
-+			if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
-+			{
-+				GMAC_CONFIG0_T config0;
-+				config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
-+				config0.bits.dis_rx = 0;
-+				writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+				config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
-+				config0.bits.dis_rx = 0;
-+				writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+			}
-+			tp->short_frames_cnt = 0;
-+#endif
-+	    	/* get frame information from the first descriptor of the frame */
-+			isPtr->rx_packets++;
-+			//consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
-+			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
-+			tp->curr_rx_skb = skb;
-+	//		curr_desc->word2.buf_adr = 0;
-+
-+		    //skb_reserve (skb, SKB_RESERVE_BYTES);
-+			skb_reserve (skb, RX_INSERT_BYTES);	/* 2 byte align the IP fields. */
-+			//if ((skb->tail+pkt_size) > skb->end )
-+			//printk("%s::------------->Here skb->len=%d,pkt_size= %d,skb->head=0x%x,skb->tail= 0x%x, skb->end= 0x%x\n", __func__, skb->len, pkt_size,skb->head,skb->tail,skb->end);
-+			skb_put(skb, pkt_size);
-+
-+
-+			skb->dev = dev;
-+			if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
-+			{
-+				skb->ip_summed = CHECKSUM_UNNECESSARY;
-+#ifdef CONFIG_SL351x_NAT
-+				if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
-+				{
-+					struct iphdr	*ip_hdr;
-+					ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
-+					sl351x_nat_input(skb,
-+									tp->port_id,
-+									(void *)curr_desc->word3.bits.l3_offset,
-+								  	(void *)curr_desc->word3.bits.l4_offset);
-+				}
-+#endif
-+				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
-+#if 0
-+#ifdef CONFIG_SL351x_RXTOE
-+				if (storlink_ctl.rx_max_pktsize) {
-+					struct iphdr	*ip_hdr;
-+					struct tcphdr	*tcp_hdr;
-+					int ip_hdrlen;
-+
-+ 					ip_hdr = (struct iphdr*)&(skb->data[0]);
-+					if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
-+					   ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
-+						ip_hdrlen = ip_hdr->ihl << 2;
-+						tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
-+						if (tcp_hdr->syn) {
-+							struct toe_conn* connection = init_toeq(ip_hdr->version,
-+									ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
-+							TCP_SKB_CB(skb)->connection = connection;
-+							//	hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
-+							//		printk("%s::skb data %x, conn %x, mode %x\n",
-+							//			__func__, skb->data, connection, connection->mode);
-+						}
-+					}
-+				}
-+#endif
-+#endif
-+			}
-+			else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
-+			{
-+				skb->ip_summed = CHECKSUM_UNNECESSARY;
-+#ifdef CONFIG_SL351x_NAT
-+				if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
-+				{
-+					struct iphdr	*ip_hdr;
-+					ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
-+					if (ip_hdr->protocol == IPPROTO_UDP)
-+					{
-+						sl351x_nat_input(skb,
-+										tp->port_id,
-+										(void *)curr_desc->word3.bits.l3_offset,
-+								  		(void *)curr_desc->word3.bits.l4_offset);
-+					}
-+					else if (ip_hdr->protocol == IPPROTO_GRE)
-+					{
-+						sl351x_nat_input(skb,
-+									tp->port_id,
-+									(void *)curr_desc->word3.bits.l3_offset,
-+								  	(void *)curr_desc->word3.bits.l4_offset);
-+					}
-+				}
-+#endif
-+				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
-+			}
-+			else
-+			{
-+				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
-+			}
-+			//netif_rx(skb);  /* socket rx */
-+			netif_receive_skb(skb); //For NAPI
-+			dev->last_rx = jiffies;
-+
-+			isPtr->rx_bytes += pkt_size;
-+			//printk("------------------->isPtr->rx_bytes = %d\n",isPtr->rx_bytes);
-+
-+
-+        }
-+		// advance one for Rx default Q 0/1
-+		rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
-+		SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
-+     	tp->rx_rwptr.bits32 = rwptr.bits32;
-+		rx_pkts_num++;
-+		//rwptr.bits32 = readl(&tp->default_qhdr->word1);//try read default_qhdr again
-+		//fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+		//printk("%s:---Loop  -------->rx_pkts_num=%d------------>Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits32,fq_rwptr.bits32 );
-+#if 0
-+		if ((status4 & 0x1) == 0)
-+		{
-+			//if (!((dev->last_rx <= (rx_time + 2)) &&  (isPtr->rx_bytes > (rx_old_bytes + 1000000 ))))
-+			if (tp->total_q_cnt_napi < 1024)
-+			{
-+				tp->total_q_cnt_napi++;
-+				toe_gmac_fill_free_q();  //for iperf test disable
-+			}
-+			//else
-+				//printk("%s:---isPtr->rx_bytes =%u , rx_old_bytes =%u\n",__func__,isPtr->rx_bytes,rx_old_bytes );
-+
-+		}
-+#endif
-+		//rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
-+		//printk("%s:---Loop  -------->rx_pkts_num=%d----rwptr.bits.rptr=0x%x-------->Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits32,fq_rwptr.bits32 );
-+		//printk("%s:---Loop  rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
-+	}
-+	// advance one for Rx default Q 0/1
-+
-+		//rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
-+		//SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
-+     	//tp->rx_rwptr.bits32 = rwptr.bits32;
-+     	//rwptr.bits.rptr = rwptr.bits.rptr;
-+
-+	dev->quota -= rx_pkts_num;
-+	*budget -= rx_pkts_num;
-+
-+	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);//try read SWFQ empty again
-+	//fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+	rwptr.bits32 = readl(&tp->default_qhdr->word1); //try read default_qhdr again
-+	//printk("%s:---After    rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
-+//	if (rwptr.bits.rptr > rwptr.bits.wptr )
-+//			{
-+				//toe_gmac_disable_rx(dev);
-+				//wait_event_interruptible_timeout(freeq_wait,
-+					//(rx_pkts_num == 100), CMTP_INTEROP_TIMEOUT);
-+				//printk("\n%s:: return 22222=======> rx_pkts_num =%d,   rwptr.bits.rptr=%d,   rwptr.bits.wptr = %d ====---------=======>JKJKJKJKJK\n",
-+					//__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
-+//				return 1;
-+//			}
-+
-+	if (rwptr.bits.rptr == rwptr.bits.wptr)
-+	{
-+		unsigned int data32;
-+			//printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr]   rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
-+
-+	    /* Receive descriptor is empty now */
-+#if 1
-+     if (status4 & 0x1)
-+   			{
-+   				do_again =1;
-+   				//writel(0x40400000, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_4_REG); //disable SWFQ empty interrupt
-+   				//toe_gmac_disable_interrupt(tp->irq);
-+   				tp->sw_fq_empty_cnt++;
-+   				//toe_gmac_disable_rx(dev);
-+   				writel(0x07960202, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+				writel(0x07960202, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+   				//printk("\n%s ::  freeq int-----tp->sw_fq_empty_cnt  =%d---------====================----------------->\n",__func__,tp->sw_fq_empty_cnt);
-+   				//while ((fq_rwptr.bits.wptr >= (fq_rwptr.bits.rptr+256)) || (fq_rwptr.bits.wptr <= (fq_rwptr.bits.rptr+256)))
-+   				//{
-+   					//gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
-+					//0x1);
-+				//printk("\n%s::fq_rwptr.wrptr = %x =======> ===========>here \n", __func__,fq_rwptr.bits32);
-+				//if ((status4 & 0x1) == 0)
-+					//break;
-+				 return 1;
-+				//}
-+
-+			}
-+#endif
-+        //toe_gmac_fill_free_q();
-+        netif_rx_complete(dev);
-+        // enable GMAC-0 rx interrupt
-+        // class-Q & TOE-Q are implemented in future
-+        //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+        //if (tp->port_id == 0)
-+        	//data32 |= DEFAULT_Q0_INT_BIT;
-+        //else
-+        	//data32 |= DEFAULT_Q1_INT_BIT;
-+        //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+		writel(0x3, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
-+		//printk("\n%s::netif_rx_complete-->  rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x ====---------=======>JKJKJKJKJK\n",
-+		//__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
-+        writel(0x07960200, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+		writel(0x07960200, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+        return 0;
-+    }
-+    else
-+    {
-+        //printk("\n%s:: return 1 -->status4= 0x%x,rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x  ======> \n", __func__,status4,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
-+        return 1;
-+    }
-+}
-+#endif
-+
-+/*----------------------------------------------------------------------
-+* gmac_tx_timeout
-+*----------------------------------------------------------------------*/
-+void gmac_tx_timeout(struct net_device *dev)
-+{
-+	GMAC_INFO_T				*tp = (GMAC_INFO_T *)dev->priv;
-+
-+#ifdef CONFIG_SL351x_SYSCTL
-+	if (tp->operation && storlink_ctl.link[tp->port_id])
-+#else
-+	if (tp->operation)
-+#endif
-+	{
-+		netif_wake_queue(dev);
-+	}
-+}
-+
-+
-+
-+/*----------------------------------------------------------------------
-+* mac_set_rule_reg
-+*----------------------------------------------------------------------*/
-+int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2)
-+{
-+	int		total_key_dwords;
-+
-+	total_key_dwords = 1;
-+
-+	if (reg0 & MR_L2_BIT)
-+	{
-+		if (reg0 & MR_DA_BIT) total_key_dwords += 2;
-+		if (reg0 & MR_SA_BIT) total_key_dwords += 2;
-+		if ((reg0 & MR_DA_BIT) && ( reg0 & MR_SA_BIT)) total_key_dwords--;
-+		if (reg0 & (MR_PPPOE_BIT | MR_VLAN_BIT)) total_key_dwords++;
-+	}
-+	if (reg0 & MR_L3_BIT)
-+	{
-+		if (reg0 & (MR_IP_HDR_LEN_BIT | MR_TOS_TRAFFIC_BIT | MR_SPR_BITS))
-+			total_key_dwords++;
-+		if (reg0 & MR_FLOW_LABLE_BIT) total_key_dwords++;
-+		if ((reg0 & MR_IP_VER_BIT) == 0) // IPv4
-+		{
-+			if (reg1 & 0xff000000) total_key_dwords += 1;
-+			if (reg1 & 0x00ff0000) total_key_dwords += 1;
-+		}
-+		else
-+		{
-+			if (reg1 & 0xff000000) total_key_dwords += 4;
-+			if (reg1 & 0x00ff0000) total_key_dwords += 4;
-+		}
-+	}
-+	if (reg0 & MR_L4_BIT)
-+	{
-+		if (reg1 & 0x0000f000) total_key_dwords += 1;
-+		if (reg1 & 0x00000f00) total_key_dwords += 1;
-+		if (reg1 & 0x000000f0) total_key_dwords += 1;
-+		if (reg1 & 0x0000000f) total_key_dwords += 1;
-+		if (reg2 & 0xf0000000) total_key_dwords += 1;
-+		if (reg2 & 0x0f000000) total_key_dwords += 1;
-+	}
-+	if (reg0 & MR_L7_BIT)
-+	{
-+		if (reg2 & 0x00f00000) total_key_dwords += 1;
-+		if (reg2 & 0x000f0000) total_key_dwords += 1;
-+		if (reg2 & 0x0000f000) total_key_dwords += 1;
-+		if (reg2 & 0x00000f00) total_key_dwords += 1;
-+		if (reg2 & 0x000000f0) total_key_dwords += 1;
-+		if (reg2 & 0x0000000f) total_key_dwords += 1;
-+	}
-+
-+	if (total_key_dwords > HASH_MAX_KEY_DWORD)
-+		return -1;
-+
-+	if (total_key_dwords == 0 && enabled)
-+		return -2;
-+
-+	mac_set_rule_enable_bit(mac, rule, 0);
-+	if (enabled)
-+	{
-+		mac_set_MRxCRx(mac, rule, 0, reg0);
-+		mac_set_MRxCRx(mac, rule, 1, reg1);
-+		mac_set_MRxCRx(mac, rule, 2, reg2);
-+		mac_set_rule_action(mac, rule, total_key_dwords);
-+		mac_set_rule_enable_bit(mac, rule, enabled);
-+	}
-+	else
-+	{
-+		mac_set_rule_action(mac, rule, 0);
-+	}
-+	return total_key_dwords;
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_get_rule_enable_bit
-+*----------------------------------------------------------------------*/
-+int mac_get_rule_enable_bit(int mac, int rule)
-+{
-+	switch (rule)
-+	{
-+		case 0: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) >> 15) & 1);
-+		case 1: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) >> 31) & 1);
-+		case 2: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) >> 15) & 1);
-+		case 3: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) >> 31) & 1);
-+		default: return 0;
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_set_rule_enable_bit
-+*----------------------------------------------------------------------*/
-+void mac_set_rule_enable_bit(int mac, int rule, int data)
-+{
-+	u32 reg;
-+
-+	if (data & ~1)
-+		return;
-+
-+	switch (rule)
-+	{
-+		case 0:
-+			reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(1<<15)) | (data << 15);
-+			mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg);
-+			break;
-+		case 1:
-+			reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(1<<31)) | (data << 31);
-+			mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg);
-+			break;
-+		case 2:
-+			reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(1<<15)) | (data << 15);
-+			mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1, reg);
-+			break;
-+		case 3:
-+			reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(1<<31)) | (data << 31);
-+			mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1, reg);
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_set_rule_action
-+*----------------------------------------------------------------------*/
-+int mac_set_rule_action(int mac, int rule, int data)
-+{
-+	u32 reg;
-+
-+	if (data > 32)
-+		return -1;
-+
-+	if (data)
-+		data = (data << 6) | (data + HASH_ACTION_DWORDS);
-+	switch (rule)
-+	{
-+		case 0:
-+			reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(0x7ff));
-+			mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg | data);
-+			break;
-+		case 1:
-+			reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(0x7ff<<16));
-+			mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg | (data << 16));
-+			break;
-+		case 2:
-+			reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(0x7ff));
-+			mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1,  reg | data);
-+			break;
-+		case 3:
-+			reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(0x7ff<<16));
-+			mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1, reg | (data << 16));
-+			break;
-+		default:
-+			return -1;
-+	}
-+
-+	return 0;
-+}
-+/*----------------------------------------------------------------------
-+* mac_get_MRxCRx
-+*----------------------------------------------------------------------*/
-+int mac_get_MRxCRx(int mac, int rule, int ctrlreg)
-+{
-+	int reg;
-+
-+	switch (rule)
-+	{
-+		case 0: reg = GMAC_MR0CR0 + ctrlreg * 4; break;
-+		case 1: reg = GMAC_MR1CR0 + ctrlreg * 4; break;
-+		case 2: reg = GMAC_MR2CR0 + ctrlreg * 4; break;
-+		case 3: reg = GMAC_MR3CR0 + ctrlreg * 4; break;
-+		default: return 0;
-+	}
-+	return mac_read_dma_reg(mac, reg);
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_set_MRxCRx
-+*----------------------------------------------------------------------*/
-+void mac_set_MRxCRx(int mac, int rule, int ctrlreg, u32 data)
-+{
-+	int reg;
-+
-+	switch (rule)
-+	{
-+		case 0: reg = GMAC_MR0CR0 + ctrlreg * 4; break;
-+		case 1: reg = GMAC_MR1CR0 + ctrlreg * 4; break;
-+		case 2: reg = GMAC_MR2CR0 + ctrlreg * 4; break;
-+		case 3: reg = GMAC_MR3CR0 + ctrlreg * 4; break;
-+		default: return;
-+	}
-+	mac_write_dma_reg(mac, reg, data);
-+}
-+
-+/*----------------------------------------------------------------------
-+* mac_set_rule_priority
-+*----------------------------------------------------------------------*/
-+void mac_set_rule_priority(int mac, int p0, int p1, int p2, int p3)
-+{
-+	int 			i;
-+	GMAC_MRxCR0_T	reg[4];
-+
-+	for (i=0; i<4; i++)
-+		reg[i].bits32 = mac_get_MRxCRx(mac, i, 0);
-+
-+	reg[0].bits.priority = p0;
-+	reg[1].bits.priority = p1;
-+	reg[2].bits.priority = p2;
-+	reg[3].bits.priority = p3;
-+
-+	for (i=0; i<4; i++)
-+		mac_set_MRxCRx(mac, i, 0, reg[i].bits32);
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_netdev_ioctl
-+*----------------------------------------------------------------------*/
-+static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-+{
-+	int 				rc = 0;
-+    unsigned char		*hwa = rq->ifr_ifru.ifru_hwaddr.sa_data;
-+
-+#ifdef br_if_ioctl
-+    struct 				ethtool_cmd ecmd; 	//br_if.c will call this ioctl
-+	GMAC_INFO_T 		*tp = dev->priv;
-+#endif
-+
-+#ifdef 	CONFIG_SL351x_NAT
-+	if (cmd == SIOCDEVPRIVATE)
-+		return sl351x_nat_ioctl(dev, rq, cmd);
-+#endif
-+
-+	switch (cmd) {
-+	case SIOCETHTOOL:
-+#ifdef br_if_ioctl  	//br_if.c will call this ioctl
-+		if (!netif_running(dev))
-+		{
-+			printk("Before changing the H/W address,please down the device.\n");
-+			return -EINVAL;
-+		}
-+		memset((void *) &ecmd, 0, sizeof (ecmd));
-+           	    ecmd.supported =
-+                	SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII |
-+                    SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
-+                    SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
-+         		    ecmd.port = PORT_TP;
-+            	    ecmd.transceiver = XCVR_EXTERNAL;
-+            	    ecmd.phy_address = tp->phy_addr;
-+            	    switch (tp->speed_status)
-+            	    {
-+            	    case GMAC_SPEED_10: ecmd.speed = SPEED_10; break;
-+             	    case GMAC_SPEED_100: ecmd.speed = SPEED_100; break;
-+            	    case GMAC_SPEED_1000: ecmd.speed = SPEED_1000; break;
-+            	    default: ecmd.speed = SPEED_10; break;
-+            	   }
-+            	    ecmd.duplex = tp->full_duplex_status ? DUPLEX_FULL : DUPLEX_HALF;
-+            	    ecmd.advertising = ADVERTISED_TP;
-+            	    ecmd.advertising |= ADVERTISED_Autoneg;
-+           	    ecmd.autoneg = AUTONEG_ENABLE;
-+                    if (copy_to_user(rq->ifr_data, &ecmd, sizeof (ecmd)))
-+                  	return -EFAULT;
-+#endif
-+
-+        break;
-+
-+    case SIOCSIFHWADDR:
-+		if (!netif_running(dev))
-+		{
-+			printk("Before changing the H/W address,please down the device.\n");
-+			return -EINVAL;
-+		}
-+        gmac_set_mac_address(dev,hwa);
-+        break;
-+
-+	case SIOCGMIIPHY:	/* Get the address of the PHY in use. */
-+        break;
-+
-+	case SIOCGMIIREG:	/* Read the specified MII register. */
-+		break;
-+
-+	case SIOCSMIIREG:	/* Write the specified MII register */
-+		break;
-+
-+	default:
-+		rc = -EOPNOTSUPP;
-+		break;
-+	}
-+
-+	return rc;
-+}
-+
-+#ifdef SL351x_GMAC_WORKAROUND
-+
-+#define GMAC_TX_STATE_OFFSET	0x60
-+#define GMAC_RX_STATE_OFFSET	0x64
-+#define GMAC_POLL_HANGED_NUM	200
-+#define GMAC_RX_HANGED_STATE	0x4b2000
-+#define GMAC_RX_HANGED_MASK		0xdff000
-+#define GMAC_TX_HANGED_STATE	0x34012
-+#define GMAC_TX_HANGED_MASK		0xfffff
-+#define TOE_GLOBAL_REG_SIZE		(0x78/sizeof(u32))
-+#define TOE_DMA_REG_SIZE		(0xd0/sizeof(u32))
-+#define TOE_GMAC_REG_SIZE		(0x30/sizeof(u32))
-+#define GMAC0_RX_HANG_BIT		(1 << 0)
-+#define GMAC0_TX_HANG_BIT		(1 << 1)
-+#define GMAC1_RX_HANG_BIT		(1 << 2)
-+#define GMAC1_TX_HANG_BIT		(1 << 3)
-+
-+int		gmac_in_do_workaround;
-+#if 0
-+int		debug_cnt, poll_max_cnt;
-+#endif
-+u32		gmac_workaround_cnt[4];
-+u32		toe_global_reg[TOE_GLOBAL_REG_SIZE];
-+u32		toe_dma_reg[GMAC_NUM][TOE_DMA_REG_SIZE];
-+u32		toe_gmac_reg[GMAC_NUM][TOE_GMAC_REG_SIZE];
-+u32		gmac_short_frame_workaround_cnt[2];
-+
-+static void sl351x_gmac_release_buffers(void);
-+static void sl351x_gmac_release_swtx_q(void);
-+static void sl351x_gmac_release_rx_q(void);
-+#ifdef _TOEQ_CLASSQ_READY_
-+static void sl351x_gmac_release_class_q(void);
-+static void sl351x_gmac_release_toe_q(void);
-+static void sl351x_gmac_release_intr_q(void);
-+#endif
-+static void sl351x_gmac_release_sw_free_q(void);
-+static void sl351x_gmac_release_hw_free_q(void);
-+#ifdef CONFIG_SL351x_NAT
-+static int get_free_desc_cnt(unsigned long rwptr, int total);
-+static void sl351x_gmac_release_hwtx_q(void);
-+u32     sl351x_nat_workaround_cnt;
-+#endif
-+void sl351x_gmac_save_reg(void);
-+void sl351x_gmac_restore_reg(void);
-+
-+
-+/*----------------------------------------------------------------------
-+* 	sl351x_poll_gmac_hanged_status
-+* 	- Called by timer routine, period 10ms
-+*	- If (state != 0 && state == prev state && )
-+*----------------------------------------------------------------------*/
-+void sl351x_poll_gmac_hanged_status(u32 data)
-+{
-+	int 			i;
-+	u32 			state;
-+	TOE_INFO_T		*toe;
-+	GMAC_INFO_T		*tp;
-+	u32				hanged_state;
-+	// int				old_operation[GMAC_NUM];
-+#ifdef CONFIG_SL351x_NAT
-+	u32				hw_free_cnt;
-+#endif
-+
-+	if (gmac_in_do_workaround)
-+		return;
-+
-+	gmac_in_do_workaround = 1;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	hanged_state = 0;
-+
-+#ifdef SL351x_TEST_WORKAROUND
-+	if (toe->gmac[0].operation || toe->gmac[1].operation)
-+	{
-+		debug_cnt++;
-+		if (debug_cnt == (30 * HZ))
-+		{
-+			debug_cnt = 0;
-+			hanged_state = GMAC0_RX_HANG_BIT;
-+			goto do_workaround;
-+		}
-+	}
-+#endif
-+	if (toe->gmac[0].operation)
-+		hanged_state |= GMAC0_RX_HANG_BIT | GMAC0_TX_HANG_BIT;
-+
-+#if (GMAC_NUM > 1)
-+	if (toe->gmac[1].operation)
-+		hanged_state |= GMAC1_RX_HANG_BIT | GMAC1_TX_HANG_BIT;
-+#endif
-+
-+	for (i=0; i 1)
-+		if (hanged_state & GMAC1_RX_HANG_BIT)
-+		{
-+			state = readl(TOE_GMAC1_BASE + GMAC_RX_STATE_OFFSET) & GMAC_RX_HANGED_MASK;
-+			if (state != GMAC_RX_HANGED_STATE)
-+				hanged_state &= ~GMAC1_RX_HANG_BIT;
-+		}
-+		if (hanged_state & GMAC1_TX_HANG_BIT)
-+		{
-+			state = readl(TOE_GMAC1_BASE + GMAC_TX_STATE_OFFSET) & GMAC_TX_HANGED_MASK;
-+			if (state != GMAC_TX_HANGED_STATE)
-+				hanged_state &= ~GMAC1_TX_HANG_BIT;
-+		}
-+#endif
-+		if (!hanged_state)
-+		{
-+#if 0
-+			if (i < poll_max_cnt)
-+				poll_max_cnt = i;
-+#endif
-+			if (toe->gmac[0].short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
-+			{
-+				gmac_short_frame_workaround_cnt[0]++;
-+				toe->gmac[0].short_frames_cnt = 0;
-+				goto do_workaround;
-+			}
-+#if (GMAC_NUM > 1)
-+			if (toe->gmac[1].short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
-+			{
-+				gmac_short_frame_workaround_cnt[1]++;
-+				toe->gmac[1].short_frames_cnt = 0;
-+				goto do_workaround;
-+			}
-+#endif
-+
-+#ifdef CONFIG_SL351x_NAT
-+			hw_free_cnt = readl(TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
-+			hw_free_cnt = get_free_desc_cnt(hw_free_cnt, TOE_HW_FREEQ_DESC_NUM);
-+#ifdef NAT_WORKAROUND_BY_RESET_GMAC
-+			if (readl(TOE_GLOBAL_BASE + 0x4084) && (hw_free_cnt <= PAUSE_SET_HW_FREEQ))
-+			{
-+				sl351x_nat_workaround_cnt++;
-+				goto do_workaround;
-+			}
-+#else
-+			if (readl(TOE_GLOBAL_BASE + 0x4084) && (hw_free_cnt <= (PAUSE_SET_HW_FREEQ*2)))
-+			{
-+				sl351x_nat_workaround_cnt++;
-+				sl351x_nat_workaround_handler();
-+			}
-+#endif
-+#endif
-+			gmac_in_do_workaround = 0;
-+			add_timer(&gmac_workround_timer_obj);
-+			return;
-+		}
-+	}
-+
-+do_workaround:
-+
-+	gmac_initialized = 0;
-+	if (hanged_state)
-+	{
-+		if (hanged_state & GMAC0_RX_HANG_BIT) gmac_workaround_cnt[0]++;
-+		if (hanged_state & GMAC0_TX_HANG_BIT) gmac_workaround_cnt[1]++;
-+		if (hanged_state & GMAC1_RX_HANG_BIT) gmac_workaround_cnt[2]++;
-+		if (hanged_state & GMAC1_TX_HANG_BIT) gmac_workaround_cnt[3]++;
-+	}
-+
-+	for (i=0; igmac[i];
-+		// old_operation[i] = tp->operation;
-+		if (tp->operation)
-+		{
-+			netif_stop_queue(tp->dev);
-+			clear_bit(__LINK_STATE_START, &tp->dev->state);
-+			toe_gmac_disable_interrupt(tp->irq);
-+			toe_gmac_disable_tx_rx(tp->dev);
-+			toe_gmac_hw_stop(tp->dev);
-+		}
-+	}
-+
-+	// clear all status bits
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
-+	writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+#if 0
-+	if ((hanged_state & GMAC0_RX_HANG_BIT) &&
-+		(readl(TOE_GMAC0_DMA_BASE + 0xdc) & 0xf0))
-+	{
-+		struct sk_buff *skb;
-+		unsigned int buf;
-+		buf = readl(TOE_GMAC0_DMA_BASE + 0x68) & ~3;
-+#ifdef CONFIG_SL351x_NAT
-+		if (buf < toe->hwfq_buf_base_dma || buf > toe->hwfq_buf_end_dma)
-+#endif
-+		{
-+			skb = (struct sk_buff *)(REG32(buf - SKB_RESERVE_BYTES));
-+			printk("GMAC-0 free a loss SKB 0x%x\n", (u32)skb);
-+			dev_kfree_skb(skb);
-+		}
-+	}
-+	if ((hanged_state & GMAC1_RX_HANG_BIT)  &&
-+		(readl(TOE_GMAC1_DMA_BASE + 0xdc) & 0xf0))
-+	{
-+		struct sk_buff *skb;
-+		unsigned int buf;
-+		buf = readl(TOE_GMAC1_DMA_BASE + 0x68) & ~3;
-+#ifdef CONFIG_SL351x_NAT
-+		if (buf < toe->hwfq_buf_base_dma || buf > toe->hwfq_buf_end_dma)
-+#endif
-+		{
-+			skb = (struct sk_buff *)(REG32(buf - SKB_RESERVE_BYTES));
-+			printk("GMAC-1 free a loss SKB 0x%x\n", (u32)skb);
-+			dev_kfree_skb(skb);
-+		}
-+	}
-+#endif
-+
-+	sl351x_gmac_release_buffers();
-+	sl351x_gmac_save_reg();
-+	toe_gmac_sw_reset();
-+	sl351x_gmac_restore_reg();
-+
-+	if (toe->gmac[0].default_qhdr->word1.bits32)
-+	{
-+		// printk("===> toe->gmac[0].default_qhdr->word1 = 0x%x\n", toe->gmac[0].default_qhdr->word1);
-+		sl351x_gmac_release_rx_q();
-+		writel(0, &toe->gmac[0].default_qhdr->word1);
-+	}
-+	if (toe->gmac[1].default_qhdr->word1.bits32)
-+	{
-+		// printk("===> toe->gmac[1].default_qhdr->word1 = 0x%x\n", toe->gmac[1].default_qhdr->word1);
-+		sl351x_gmac_release_rx_q();
-+		writel(0, &toe->gmac[1].default_qhdr->word1);
-+	}
-+
-+	gmac_initialized = 1;
-+
-+#ifdef 	CONFIG_SL351x_NAT
-+	writel(0, TOE_GLOBAL_BASE + 0x4084);
-+#endif
-+
-+	for (i=0; igmac[i];
-+ 		if (tp->operation)
-+ 		{
-+			toe_gmac_enable_interrupt(tp->irq);
-+			toe_gmac_hw_start(tp->dev);
-+			toe_gmac_enable_tx_rx(tp->dev);
-+			netif_wake_queue(tp->dev);
-+			set_bit(__LINK_STATE_START, &tp->dev->state);
-+		}
-+	}
-+
-+	gmac_in_do_workaround = 0;
-+	add_timer(&gmac_workround_timer_obj);
-+}
-+
-+/*----------------------------------------------------------------------
-+*	get_free_desc_cnt
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL351x_NAT
-+static int get_free_desc_cnt(unsigned long rwptr, int total)
-+{
-+	unsigned short wptr = rwptr & 0xffff;
-+	unsigned short rptr = rwptr >> 16;
-+
-+	if (wptr >= rptr)
-+		return (total - wptr + rptr);
-+	else
-+		return (rptr - wptr);
-+}
-+#endif
-+/*----------------------------------------------------------------------
-+* 	sl351x_gmac_release_buffers
-+*----------------------------------------------------------------------*/
-+static void sl351x_gmac_release_buffers(void)
-+{
-+	// Free buffers & Descriptors in all SW Tx Queues
-+	sl351x_gmac_release_swtx_q();
-+
-+	// Free buffers in Default Rx Queues
-+	sl351x_gmac_release_rx_q();
-+
-+#ifdef _TOEQ_CLASSQ_READY_
-+	// Free buffers in Classification Queues
-+	sl351x_gmac_release_class_q();
-+
-+	// Free buffers in TOE Queues
-+	sl351x_gmac_release_toe_q();
-+
-+	// Free buffers in Interrupt Queues
-+	sl351x_gmac_release_intr_q();
-+#endif
-+
-+	// Free buffers & descriptors in SW free queue
-+	sl351x_gmac_release_sw_free_q();
-+
-+	// Free buffers & descriptors in HW free queue
-+	sl351x_gmac_release_hw_free_q();
-+
-+#ifdef CONFIG_SL351x_NAT
-+	// Free buffers & descriptors in HW free queue
-+	sl351x_gmac_release_hwtx_q();
-+#endif
-+}
-+/*----------------------------------------------------------------------
-+* 	sl351x_gmac_release_swtx_q
-+*----------------------------------------------------------------------*/
-+static void sl351x_gmac_release_swtx_q(void)
-+{
-+	int				i, j;
-+	GMAC_TXDESC_T	*curr_desc;
-+	unsigned int	desc_count;
-+	TOE_INFO_T		*toe;
-+	GMAC_INFO_T		*tp;
-+	GMAC_SWTXQ_T	*swtxq;
-+	DMA_RWPTR_T		rwptr;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	tp = (GMAC_INFO_T *)&toe->gmac[0];
-+	for (i=0; iexisted) continue;
-+		swtxq = (GMAC_SWTXQ_T *)&tp->swtxq[0];
-+		for (j=0; jrwptr_reg);
-+				if (rwptr.bits.rptr == swtxq->finished_idx)
-+				break;
-+				curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
-+				// if (curr_desc->word0.bits.status_tx_ok)
-+				{
-+					desc_count = curr_desc->word0.bits.desc_count;
-+					while (--desc_count)
-+					{
-+						curr_desc->word0.bits.status_tx_ok = 0;
-+						swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
-+						curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
-+					}
-+
-+					curr_desc->word0.bits.status_tx_ok = 0;
-+					if (swtxq->tx_skb[swtxq->finished_idx])
-+					{
-+						dev_kfree_skb_irq(swtxq->tx_skb[swtxq->finished_idx]);
-+						swtxq->tx_skb[swtxq->finished_idx] = NULL;
-+					}
-+				}
-+				swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
-+			}
-+			writel(0, swtxq->rwptr_reg);
-+			swtxq->finished_idx = 0;
-+		}
-+	}
-+
-+}
-+/*----------------------------------------------------------------------
-+* 	sl351x_gmac_release_rx_q
-+*----------------------------------------------------------------------*/
-+static void sl351x_gmac_release_rx_q(void)
-+{
-+	int				i;
-+	TOE_INFO_T		*toe;
-+	GMAC_INFO_T		*tp;
-+	DMA_RWPTR_T		rwptr;
-+	volatile GMAC_RXDESC_T	*curr_desc;
-+	struct sk_buff			*skb;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	tp = (GMAC_INFO_T *)&toe->gmac[0];
-+	for (i=0; iexisted) continue;
-+		rwptr.bits32 = readl(&tp->default_qhdr->word1);
-+		while (rwptr.bits.rptr != rwptr.bits.wptr)
-+		{
-+			curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
-+			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
-+			dev_kfree_skb_irq(skb);
-+			rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
-+			SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
-+			rwptr.bits32 = readl(&tp->default_qhdr->word1);
-+		}  // while
-+		writel(0, &tp->default_qhdr->word1);
-+		tp->rx_rwptr.bits32 = 0;
-+	} // for
-+
-+}
-+/*----------------------------------------------------------------------
-+* 	sl351x_gmac_release_class_q
-+*----------------------------------------------------------------------*/
-+#ifdef _TOEQ_CLASSQ_READY_
-+static void sl351x_gmac_release_class_q(void)
-+{
-+	int				i;
-+	TOE_INFO_T		*toe;
-+	CLASSQ_INFO_T	*classq;
-+	DMA_RWPTR_T		rwptr;
-+	volatile GMAC_RXDESC_T	*curr_desc;
-+	struct sk_buff			*skb;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	classq = (CLASSQ_INFO_T *)&toe->classq[0];
-+	for (i=0; iqhdr->word1);
-+		while (rwptr.bits.rptr != rwptr.bits.wptr)
-+		{
-+			curr_desc = (GMAC_RXDESC_T *)classq->desc_base + rwptr.bits.rptr;
-+			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
-+			dev_kfree_skb_irq(skb);
-+			rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, classq->desc_num);
-+			SET_RPTR(&classq->qhdr->word1, rwptr.bits.rptr);
-+			rwptr.bits32 = readl(&classq->qhdr->word1);
-+		}  // while
-+		writel(0, &classq->qhdr->word1);
-+		classq->rwptr.bits32 = 0;
-+	} // for
-+
-+}
-+#endif
-+/*----------------------------------------------------------------------
-+* 	sl351x_gmac_release_toe_q
-+*----------------------------------------------------------------------*/
-+#ifdef _TOEQ_CLASSQ_READY_
-+static void sl351x_gmac_release_toe_q(void)
-+{
-+	int				i;
-+	TOE_INFO_T		*toe;
-+	TOEQ_INFO_T		*toeq_info;
-+	TOE_QHDR_T		*toe_qhdr;
-+	DMA_RWPTR_T		rwptr;
-+	volatile GMAC_RXDESC_T	*curr_desc;
-+	unsigned int	rptr, wptr;
-+	GMAC_RXDESC_T	*toe_curr_desc;
-+	struct sk_buff			*skb;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	toe_qhdr = (TOE_QHDR_T *)TOE_TOE_QUE_HDR_BASE;
-+	for (i=0; itoeq[i];
-+		wptr = toe_qhdr->word1.bits.wptr;
-+		rptr = toe_qhdr->word1.bits.rptr;
-+		while (rptr != wptr)
-+		{
-+			toe_curr_desc = (GMAC_RXDESC_T *)toeq_info->desc_base + rptr;
-+			skb = (struct sk_buff *)(REG32(__va(toe_curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
-+			dev_kfree_skb_irq(skb);
-+			rptr = RWPTR_ADVANCE_ONE(rptr, toeq_info->desc_num);
-+			SET_RPTR(&toe_qhdr->word1.bits32, rptr);
-+			wptr = toe_qhdr->word1.bits.wptr;
-+			rptr = toe_qhdr->word1.bits.rptr;
-+		}
-+		toe_qhdr->word1.bits32 = 0;
-+		toeq_info->rwptr.bits32 = 0;
-+	}
-+}
-+#endif
-+/*----------------------------------------------------------------------
-+* 	sl351x_gmac_release_intr_q
-+*----------------------------------------------------------------------*/
-+#ifdef _TOEQ_CLASSQ_READY_
-+static void sl351x_gmac_release_intr_q(void)
-+{
-+}
-+#endif
-+/*----------------------------------------------------------------------
-+* 	sl351x_gmac_release_sw_free_q
-+*----------------------------------------------------------------------*/
-+static void sl351x_gmac_release_sw_free_q(void)
-+{
-+	TOE_INFO_T				*toe;
-+	volatile DMA_RWPTR_T	fq_rwptr;
-+	volatile GMAC_RXDESC_T	*fq_desc;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+
-+	while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr)
-+	{
-+		struct sk_buff *skb;
-+		if ((skb = dev_alloc_skb(SW_RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
-+		{
-+			printk("%s::skb buffer allocation fail !\n",__func__); while(1);
-+		}
-+		// *(unsigned int *)(skb->data) = (unsigned int)skb;
-+		REG32(skb->data) = (unsigned long)skb;
-+		skb_reserve(skb, SKB_RESERVE_BYTES);
-+
-+		fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
-+		fq_desc = (volatile GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
-+		fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
-+		SET_WPTR(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
-+		fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+	}
-+
-+	toe->fq_rx_rwptr.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
-+	toe->fq_rx_rwptr.bits.rptr = 0;
-+	writel(toe->fq_rx_rwptr.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+
-+}
-+/*----------------------------------------------------------------------
-+* 	sl351x_gmac_release_hw_free_q
-+*----------------------------------------------------------------------*/
-+static void sl351x_gmac_release_hw_free_q(void)
-+{
-+	DMA_RWPTR_T			rwptr_reg;
-+
-+#ifdef CONFIG_SL351x_NAT
-+	int					i;
-+	TOE_INFO_T			*toe;
-+	GMAC_RXDESC_T		*desc_ptr;
-+	unsigned int		buf_ptr;
-+
-+	toe = (TOE_INFO_T *)&toe_private_data;
-+	desc_ptr = (GMAC_RXDESC_T *)toe->hwfq_desc_base;
-+	buf_ptr = (unsigned int)toe->hwfq_buf_base_dma;
-+	for (i=0; iword0.bits.buffer_size = HW_RX_BUF_SIZE;
-+		desc_ptr->word1.bits.sw_id = i;
-+		desc_ptr->word2.buf_adr = (unsigned int)buf_ptr;
-+   		desc_ptr++;
-+   		buf_ptr += HW_RX_BUF_SIZE;
-+	}
-+#endif
-+	rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
-+	rwptr_reg.bits.rptr = 0;
-+	writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
-+}
-+
-+/*----------------------------------------------------------------------
-+* 	sl351x_gmac_release_hw_free_q
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL351x_NAT
-+static void sl351x_gmac_release_hwtx_q(void)
-+{
-+	int				i;
-+	unsigned int	rwptr_addr;
-+
-+	rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
-+	for (i=0; ihwfq_desc_base;
-+	buf_ptr = (unsigned int)toe->hwfq_buf_base_dma;
-+	for (i=0; iword0.bits.buffer_size = HW_RX_BUF_SIZE;
-+		desc_ptr->word1.bits.sw_id = i;
-+		desc_ptr->word2.buf_adr = (unsigned int)buf_ptr;
-+		desc_ptr++;
-+		buf_ptr += HW_RX_BUF_SIZE;
-+	}
-+	rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
-+	rwptr.bits.wptr = RWPTR_RECEDE_ONE(rwptr.bits.rptr, TOE_HW_FREEQ_DESC_NUM);
-+	writel(rwptr.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
-+	writel(0, TOE_GLOBAL_BASE + 0x4084);
-+
-+	// Enable Rx of GMAC-0 & 1
-+	config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
-+	config0.bits.dis_rx = 0;
-+	writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+	config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
-+	config0.bits.dis_rx = 0;
-+	writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
-+}
-+#endif
-+#endif // CONFIG_SL351x_NAT
-+
-+#endif // SL351x_GMAC_WORKAROUND
-+
-+/* get the mac addresses from flash
-+ *can't do this in module_init because mtd driver is initialized after ethernet
-+ */
-+static __init int sl351x_mac_address_init(void)
-+{
-+	GMAC_INFO_T		*tp;
-+	struct sockaddr sock;
-+	int i;
-+
-+	/* get mac address from FLASH */
-+	gmac_get_mac_address();
-+
-+	for (i = 0; i < GMAC_NUM; i++) {
-+		tp = (GMAC_INFO_T *)&toe_private_data.gmac[i];
-+		memcpy(&sock.sa_data[0],ð_mac[tp->port_id][0],6);
-+		gmac_set_mac_address(tp->dev,(void *)&sock);
-+	}
-+
-+        return 0;
-+}
-+late_initcall(sl351x_mac_address_init);
-+
-+
---- /dev/null
-+++ b/drivers/net/sl351x_hash.c
-@@ -0,0 +1,713 @@
-+/**************************************************************************
-+* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
-+*--------------------------------------------------------------------------
-+* Name			: sl351x_hash.c
-+* Description	:
-+*		Handle Storlink SL351x Hash Functions
-+*
-+* History
-+*
-+*	Date		Writer		Description
-+*----------------------------------------------------------------------------
-+*	03/13/2006	Gary Chen	Create and implement
-+*
-+****************************************************************************/
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#define	 MIDWAY
-+#define	 SL_LEPUS
-+
-+#include 
-+#include 
-+#include 
-+
-+#ifndef RXTOE_DEBUG
-+#define RXTOE_DEBUG
-+#endif
-+#undef RXTOE_DEBUG
-+
-+/*----------------------------------------------------------------------
-+* Definition
-+*----------------------------------------------------------------------*/
-+#define	hash_printf				printk
-+
-+#define HASH_TIMER_PERIOD		(30)	// seconds
-+#define HASH_ILLEGAL_INDEX		0xffff
-+
-+/*----------------------------------------------------------------------
-+* Variables
-+*----------------------------------------------------------------------*/
-+u32					hash_nat_owner_bits[HASH_TOTAL_ENTRIES/32];
-+char 				hash_tables[HASH_TOTAL_ENTRIES][HASH_MAX_BYTES] __attribute__ ((aligned(16)));
-+static struct timer_list hash_timer_obj;
-+LIST_HEAD(hash_timeout_list);
-+
-+/*----------------------------------------------------------------------
-+* Functions
-+*----------------------------------------------------------------------*/
-+void dm_long(u32 location, int length);
-+static void hash_timer_func(u32 data);
-+
-+/*----------------------------------------------------------------------
-+* hash_init
-+*----------------------------------------------------------------------*/
-+void sl351x_hash_init(void)
-+{
-+	int i;
-+	volatile u32 *dp1, *dp2, dword;
-+
-+	dp1 = (volatile u32 *) TOE_V_BIT_BASE;
-+	dp2 = (volatile u32 *) TOE_A_BIT_BASE;
-+
-+	for (i=0; iindex, 1);
-+//	printk("Dump hash key!\n");
-+//	dump_hash_key(entry);
-+	return entry->index;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_set_valid_flag
-+*----------------------------------------------------------------------*/
-+void hash_set_valid_flag(int index, int valid)
-+{
-+	register u32 reg32;
-+
-+	reg32 = TOE_V_BIT_BASE + (index/32) * 4;
-+
-+	if (valid)
-+	{
-+		writel(readl(reg32) | (1 << (index%32)), reg32);
-+	}
-+	else
-+	{
-+		writel(readl(reg32) & ~(1 << (index%32)), reg32);
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_set_nat_owner_flag
-+*----------------------------------------------------------------------*/
-+void hash_set_nat_owner_flag(int index, int valid)
-+{
-+	if (valid)
-+	{
-+		hash_nat_owner_bits[index/32] |= (1 << (index % 32));
-+	}
-+	else
-+	{
-+		hash_nat_owner_bits[index/32] &= ~(1 << (index % 32));
-+	}
-+}
-+
-+
-+/*----------------------------------------------------------------------
-+* hash_build_keys
-+*----------------------------------------------------------------------*/
-+int hash_build_keys(u32 *destp, HASH_ENTRY_T *entry)
-+{
-+	u32 	data;
-+	unsigned char 	*cp;
-+	int				i, j;
-+	unsigned short 	index;
-+	int 			total;
-+
-+	memset((void *)destp, 0, HASH_MAX_BYTES);
-+	cp = (unsigned char *)destp;
-+
-+	if (entry->key_present.port || entry->key_present.Ethertype)
-+	{
-+		HASH_PUSH_WORD(cp, entry->key.Ethertype);		// word 0
-+		HASH_PUSH_BYTE(cp, entry->key.port);			// Byte 2
-+		HASH_PUSH_BYTE(cp, 0);							// Byte 3
-+	}
-+	else
-+	{
-+		HASH_PUSH_DWORD(cp, 0);
-+	}
-+
-+	if (entry->key_present.da || entry->key_present.sa)
-+	{
-+		unsigned char mac[4];
-+		if (entry->key_present.da)
-+		{
-+			for (i=0; i<4; i++)
-+				HASH_PUSH_BYTE(cp, entry->key.da[i]);
-+		}
-+		mac[0] = (entry->key_present.da) ? entry->key.da[4] : 0;
-+		mac[1] = (entry->key_present.da) ? entry->key.da[5] : 0;
-+		mac[2] = (entry->key_present.sa) ? entry->key.sa[0] : 0;
-+		mac[3] = (entry->key_present.sa) ? entry->key.sa[1] : 0;
-+		data = mac[0] + (mac[1]<<8) + (mac[2]<<16) + (mac[3]<<24);
-+		HASH_PUSH_DWORD(cp, data);
-+		if (entry->key_present.sa)
-+		{
-+			for (i=2; i<6; i++)
-+				HASH_PUSH_BYTE(cp, entry->key.sa[i]);
-+		}
-+	}
-+
-+	if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
-+	{
-+		HASH_PUSH_WORD(cp, entry->key.vlan_id);		// low word
-+		HASH_PUSH_WORD(cp, entry->key.pppoe_sid);	// high word
-+	}
-+	if (entry->key_present.ipv4_hdrlen || entry->key_present.ip_tos || entry->key_present.ip_protocol)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.ip_protocol);		// Byte 0
-+		HASH_PUSH_BYTE(cp, entry->key.ip_tos);			// Byte 1
-+		HASH_PUSH_BYTE(cp, entry->key.ipv4_hdrlen);		// Byte 2
-+		HASH_PUSH_BYTE(cp, 0);							// Byte 3
-+	}
-+
-+	if (entry->key_present.ipv6_flow_label)
-+	{
-+		HASH_PUSH_DWORD(cp, entry->key.ipv6_flow_label);	// low word
-+	}
-+	if (entry->key_present.sip)
-+	{
-+		// input (entry->key.sip[i]) is network-oriented
-+		// output (hash key) is host-oriented
-+		for (i=3; i>=0; i--)
-+			HASH_PUSH_BYTE(cp, entry->key.sip[i]);
-+		if (entry->key.ipv6)
-+		{
-+			for (i=4; i<16; i+=4)
-+			{
-+				for (j=i+3; j>=i; j--)
-+					HASH_PUSH_BYTE(cp, entry->key.sip[j]);
-+			}
-+		}
-+	}
-+	if (entry->key_present.dip)
-+	{
-+		// input (entry->key.sip[i]) is network-oriented
-+		// output (hash key) is host-oriented
-+		for (i=3; i>=0; i--)
-+			HASH_PUSH_BYTE(cp, entry->key.dip[i]);
-+		if (entry->key.ipv6)
-+		{
-+			for (i=4; i<16; i+=4)
-+			{
-+				for (j=i+3; j>=i; j--)
-+					HASH_PUSH_BYTE(cp, entry->key.dip[j]);
-+			}
-+		}
-+	}
-+
-+	if (entry->key_present.l4_bytes_0_3)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
-+	}
-+	if (entry->key_present.l4_bytes_4_7)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[4]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[5]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[6]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[7]);
-+	}
-+	if (entry->key_present.l4_bytes_8_11)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[8]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[9]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[10]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[11]);
-+	}
-+	if (entry->key_present.l4_bytes_12_15)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[12]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[13]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[14]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[15]);
-+	}
-+	if (entry->key_present.l4_bytes_16_19)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[16]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[17]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[18]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[19]);
-+	}
-+	if (entry->key_present.l4_bytes_20_23)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[20]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[21]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[22]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[23]);
-+	}
-+	if (entry->key_present.l7_bytes_0_3)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[0]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[1]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[2]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[3]);
-+	}
-+	if (entry->key_present.l7_bytes_4_7)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[4]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[5]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[6]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[7]);
-+	}
-+	if (entry->key_present.l7_bytes_8_11)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[8]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[9]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[10]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[11]);
-+	}
-+	if (entry->key_present.l7_bytes_12_15)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[12]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[13]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[14]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[15]);
-+	}
-+	if (entry->key_present.l7_bytes_16_19)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[16]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[17]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[18]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[19]);
-+	}
-+	if (entry->key_present.l7_bytes_20_23)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[20]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[21]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[22]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[23]);
-+	}
-+
-+	// get hash index
-+	total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
-+
-+	if (total > HASH_MAX_KEY_DWORD)
-+	{
-+		//hash_printf("Total key words (%d) is too large (> %d)!\n",
-+		//				total, HASH_MAX_KEY_DWORD);
-+		return -1;
-+	}
-+
-+	if (entry->key_present.port || entry->key_present.Ethertype)
-+		index = hash_gen_crc16((unsigned char *)destp, total * 4);
-+	else
-+	{
-+		if (total == 1)
-+		{
-+			hash_printf("No key is assigned!\n");
-+			return -1;
-+		}
-+
-+		index = hash_gen_crc16((unsigned char *)(destp+1), (total-1) * 4);
-+	}
-+
-+	entry->index = index & HASH_BITS_MASK;
-+
-+	//hash_printf("Total key words = %d, Hash Index= %d\n",
-+	//				total, entry->index);
-+
-+	cp = (unsigned char *)destp;
-+	cp+=3;
-+	HASH_PUSH_BYTE(cp, entry->rule);	// rule
-+
-+	entry->total_dwords = total;
-+
-+	return total;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_build_nat_keys
-+*----------------------------------------------------------------------*/
-+void hash_build_nat_keys(u32 *destp, HASH_ENTRY_T *entry)
-+{
-+	unsigned char 	*cp;
-+	int				i;
-+	unsigned short 	index;
-+	int 			total;
-+
-+	memset((void *)destp, 0, HASH_MAX_BYTES);
-+
-+	cp = (unsigned char *)destp + 2;
-+	HASH_PUSH_BYTE(cp, entry->key.port);
-+	cp++;
-+
-+	if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
-+	{
-+		HASH_PUSH_WORD(cp, entry->key.vlan_id);		// low word
-+		HASH_PUSH_WORD(cp, entry->key.pppoe_sid);	// high word
-+	}
-+
-+	HASH_PUSH_BYTE(cp, entry->key.ip_protocol);
-+	cp+=3;
-+
-+	// input (entry->key.sip[i]) is network-oriented
-+	// output (hash key) is host-oriented
-+	for (i=3; i>=0; i--)
-+		HASH_PUSH_BYTE(cp, entry->key.sip[i]);
-+
-+	// input (entry->key.sip[i]) is network-oriented
-+	// output (hash key) is host-oriented
-+	for (i=3; i>=0; i--)
-+		HASH_PUSH_BYTE(cp, entry->key.dip[i]);
-+
-+	HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
-+	HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
-+	HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
-+	HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
-+
-+	// get hash index
-+	total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
-+
-+	index = hash_gen_crc16((unsigned char *)destp, total * 4);
-+	entry->index = index & ((1 << HASH_BITS) - 1);
-+
-+	cp = (unsigned char *)destp;
-+	cp+=3;
-+	HASH_PUSH_BYTE(cp, entry->rule);	// rule
-+
-+	entry->total_dwords = total;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_build_toe_keys
-+*----------------------------------------------------------------------*/
-+int hash_build_toe_keys(u32 *destp, HASH_ENTRY_T *entry)
-+{
-+	unsigned long	data;
-+	unsigned char	*cp;
-+	unsigned short	index;
-+	int	i;
-+	int total;
-+	//printk("%s\n", __func__);
-+	memset((void*)destp, 0, HASH_MAX_BYTES);
-+	cp = (unsigned char*)destp;
-+
-+	if(entry->key_present.port || entry->key_present.Ethertype) {
-+		data = (entry->key.port << 16) + entry->key.Ethertype;
-+		HASH_PUSH_DWORD(cp, data);
-+	} else
-+		HASH_PUSH_DWORD(cp, 0);
-+
-+	if (entry->key_present.da || entry->key_present.sa) {
-+		unsigned char	mac[4];
-+		if (entry->key_present.da) {
-+			data = (entry->key.da[0]) + (entry->key.da[1] << 8) +
-+				   (entry->key.da[2] << 16) + (entry->key.da[3] <<24);
-+			HASH_PUSH_DWORD(cp, data);
-+		}
-+		mac[0] = (entry->key_present.da) ? entry->key.da[4] : 0;
-+		mac[1] = (entry->key_present.da) ? entry->key.da[5] : 0;
-+		mac[2] = (entry->key_present.sa) ? entry->key.sa[0] : 0;
-+		mac[3] = (entry->key_present.sa) ? entry->key.sa[1] : 0;
-+		data = mac[0] + (mac[1]<<8) + (mac[2]<<16) + (mac[3]<<24);
-+		HASH_PUSH_DWORD(cp, data);
-+		if (entry->key_present.sa) {
-+			data = (entry->key.sa[2]) + (entry->key.sa[3] << 8) +
-+				   (entry->key.sa[4] << 16) + (entry->key.sa[5] <<24);
-+			HASH_PUSH_DWORD(cp, data);
-+		}
-+	}
-+
-+	if (entry->key_present.ip_protocol) {
-+		unsigned char ip_protocol;
-+		ip_protocol = entry->key.ip_protocol;
-+		data = ip_protocol;
-+		HASH_PUSH_DWORD(cp, data);
-+	}
-+
-+	if (entry->key_present.ipv6_flow_label) {
-+		unsigned long flow_label;
-+		flow_label  = entry->key.ipv6_flow_label;
-+		data = flow_label & 0xfffff;
-+		HASH_PUSH_DWORD(cp, data);
-+	}
-+
-+	if (entry->key_present.sip)	{
-+		{
-+			data = IPIV(entry->key.sip[0], entry->key.sip[1],
-+					entry->key.sip[2], entry->key.sip[3]);
-+			HASH_PUSH_DWORD(cp, data);
-+			if (entry->key.ipv6) {
-+				for (i=4; i<16; i+=4) {
-+					data = IPIV(entry->key.sip[i+0], entry->key.sip[i+1],
-+							entry->key.sip[i+2], entry->key.sip[i+3]);
-+					HASH_PUSH_DWORD(cp, data);
-+				}
-+			}
-+		}
-+	}
-+
-+	if (entry->key_present.dip)	{
-+		{
-+			data = IPIV(entry->key.dip[0], entry->key.dip[1],
-+						entry->key.dip[2], entry->key.dip[3]);
-+			HASH_PUSH_DWORD(cp, data);
-+			if (entry->key.ipv6) {
-+				for (i=4; i<16; i+=4) {
-+					data = IPIV(entry->key.dip[i+0], entry->key.dip[i+1],
-+								entry->key.dip[i+2], entry->key.dip[i+3]);
-+					HASH_PUSH_DWORD(cp, data);
-+				}
-+			}
-+		}
-+	}
-+	if (entry->key_present.l4_bytes_0_3)
-+	{
-+		unsigned char *datap;
-+		datap = &entry->key.l4_bytes[0];
-+		data = 	datap[0] + 	(datap[1] << 8) + (datap[2] << 16) + (datap[3] << 24);
-+		HASH_PUSH_DWORD(cp, data);
-+	}
-+	if (entry->key_present.l7_bytes_0_3)
-+	{
-+		unsigned char *datap;
-+		datap = &entry->key.l7_bytes[0];
-+		data = 	datap[0] + 	(datap[1] << 8) + (datap[2] << 16) + (datap[3] << 24);
-+		HASH_PUSH_DWORD(cp, data);
-+	}
-+	if (entry->key_present.l7_bytes_4_7)
-+	{
-+		unsigned char *datap;
-+		datap = &entry->key.l7_bytes[4];
-+		data = 	datap[0] + 	(datap[1] << 8) + (datap[2] << 16) + (datap[3] << 24);
-+		HASH_PUSH_DWORD(cp, data);
-+	}
-+
-+	total = (unsigned long)((unsigned long)cp - (unsigned long)destp) / (sizeof(u32));
-+	if (total > HASH_MAX_KEY_DWORD) {
-+		//printf("Total key words (%d) is too large (> %d)!\n",
-+		//		total, HASH_MAX_KEY_DWORD);
-+		return -1;
-+	}
-+	index = hash_gen_crc16((unsigned char*)(destp + 1), (total-1)*4);
-+	entry->index = index & ((1 << HASH_BITS)-1);
-+
-+	cp = (unsigned char*) destp;
-+	cp += 3;
-+	HASH_PUSH_BYTE(cp, entry->rule);
-+	entry->total_dwords = total;
-+	return total;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_add_toe_entry
-+*----------------------------------------------------------------------*/
-+int hash_add_toe_entry(HASH_ENTRY_T *entry)
-+{
-+	int	rc;
-+	u32	key[HASH_MAX_DWORDS];
-+
-+	rc = hash_build_toe_keys((u32 *)&key, entry);
-+	if (rc < 0)
-+		return -1;
-+	hash_write_entry(entry, (unsigned char*) &key[0]);
-+	//hash_dump_entry(entry->index);
-+//	hash_set_valid_flag(entry->index, 1);
-+//	printk("Dump hash key!\n");
-+//	dump_hash_key(entry);
-+	return entry->index;
-+}
-+
-+
-+/*----------------------------------------------------------------------
-+* hash_write_entry
-+*----------------------------------------------------------------------*/
-+int hash_write_entry(HASH_ENTRY_T *entry, unsigned char *key)
-+{
-+	int		i;
-+	u32		*srcep, *destp, *destp2;
-+
-+	srcep = (u32 *)key;
-+	destp2 = destp = (u32 *)&hash_tables[entry->index][0];
-+
-+	for (i=0; i<(entry->total_dwords); i++, srcep++, destp++)
-+		*destp = *srcep;
-+
-+	srcep = (u32 *)&entry->action;
-+	*destp++ = *srcep;
-+
-+	srcep = (u32 *)&entry->param;
-+	for (i=0; i<(sizeof(ENTRY_PARAM_T)/sizeof(*destp)); i++, srcep++, destp++)
-+		*destp = *srcep;
-+
-+	memset(destp, 0, (HASH_MAX_DWORDS-entry->total_dwords-HASH_ACTION_DWORDS) * sizeof(u32));
-+
-+	consistent_sync(destp2, (entry->total_dwords+HASH_ACTION_DWORDS) * 4, PCI_DMA_TODEVICE);
-+	return 0;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_timer_func
-+*----------------------------------------------------------------------*/
-+static void hash_timer_func(u32 data)
-+{
-+	int					i, j, idx;
-+	volatile u32		*own_p, *valid_p;
-+	u32					own_bits, a_bits;
-+	int					period = HASH_TIMER_PERIOD;
-+
-+	valid_p = (volatile u32 *)TOE_V_BIT_BASE;
-+	own_p = (volatile u32 *)hash_nat_owner_bits;
-+	for (i=0, idx=0; i<(HASH_TOTAL_ENTRIES/32); i++, own_p++, valid_p++, idx+=32)
-+	{
-+		a_bits = readl(TOE_A_BIT_BASE + (i*4));
-+		own_bits = *own_p;
-+		if (own_bits)
-+		{
-+			for (j=0; own_bits && j<32; j++)
-+			{
-+				if (own_bits & 1)
-+				{
-+					short *counter_p, *interval_p;
-+					NAT_HASH_ENTRY_T	*nat_entry;
-+					GRE_HASH_ENTRY_T	*gre_entry;
-+					nat_entry = (NAT_HASH_ENTRY_T *)hash_get_entry(idx+j);
-+					gre_entry = (GRE_HASH_ENTRY_T *)nat_entry;
-+					if (nat_entry->key.ip_protocol == IPPROTO_GRE)
-+					{
-+						counter_p = (short *)&gre_entry->tmo.counter;
-+						interval_p = (short *)&gre_entry->tmo.interval;
-+					}
-+					else
-+					{
-+						counter_p = (short *)&nat_entry->tmo.counter;
-+						interval_p = (short *)&nat_entry->tmo.interval;
-+					}
-+					if (a_bits & 1)
-+					{
-+						*counter_p = *interval_p;
-+					}
-+					else
-+					{
-+						*counter_p -= HASH_TIMER_PERIOD;
-+						if (*counter_p <= 0)
-+						{
-+							*valid_p &= ~(1 << j);		// invalidate it
-+							*own_p &= ~(1 << j);		// release ownership for NAT
-+							*counter_p = 0;
-+							// hash_printf("%lu %s: Clear hash index: %d\n", jiffies/HZ, __func__, i*32+j);
-+						}
-+						else if (period > *counter_p)
-+						{
-+							period = *counter_p;
-+						}
-+					}
-+				}
-+				a_bits >>= 1;
-+				own_bits >>=1;
-+			}
-+		}
-+	}
-+
-+	hash_timer_obj.expires = jiffies + (period * HZ);
-+	add_timer((struct timer_list *)data);
-+}
-+
-+/*----------------------------------------------------------------------
-+* dm_long
-+*----------------------------------------------------------------------*/
-+void dm_long(u32 location, int length)
-+{
-+	u32		*start_p, *curr_p, *end_p;
-+	u32		*datap, data;
-+	int		i;
-+
-+	//if (length > 1024)
-+	//	length = 1024;
-+
-+	start_p = (u32 *)location;
-+	end_p = (u32 *)location + length;
-+	curr_p = (u32 *)((u32)location & 0xfffffff0);
-+	datap = (u32 *)location;
-+	while (curr_p < end_p)
-+	{
-+		hash_printf("0x%08x: ",(u32)curr_p & 0xfffffff0);
-+		for (i=0; i<4; i++)
-+		{
-+			if (curr_p < start_p || curr_p >= end_p)
-+               hash_printf("         ");
-+			else
-+			{
-+				data = *datap;
-+				hash_printf("%08X ", data);
-+			}
-+			if (i==1)
-+              hash_printf("- ");
-+
-+			curr_p++;
-+			datap++;
-+		}
-+        hash_printf("\n");
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_dump_entry
-+*----------------------------------------------------------------------*/
-+void hash_dump_entry(int index)
-+{
-+	hash_printf("Hash Index %d:\n", index);
-+	dm_long((u32)&hash_tables[index][0], HASH_MAX_DWORDS);
-+}
-+
-+
---- /dev/null
-+++ b/drivers/net/sl351x_nat.c
-@@ -0,0 +1,1736 @@
-+/****************************************************************************
-+* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
-+*----------------------------------------------------------------------------
-+* Name			: sl351x_nat.c
-+* Description	:
-+*		Handle Storlink SL351x NAT Functions
-+*
-+*
-+* Packet Flow:
-+*
-+*            (xmit)+<--- SW NAT -->+(xmit)
-+*                  |       ^^      |
-+*                  |       ||      |
-+*                  |       ||      |
-+*   Client <---> GMAC-x  HW-NAT  GMAC-y  <---> Server
-+*
-+*
-+* History
-+*
-+*	Date		Writer		Description
-+*----------------------------------------------------------------------------
-+*	03/13/2006	Gary Chen	Create and implement
-+*
-+*
-+****************************************************************************/
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#define	 MIDWAY
-+#define	 SL_LEPUS
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#ifdef CONFIG_NETFILTER
-+// #include 
-+#include 
-+#endif
-+
-+//#define NAT_DEBUG_MSG		1
-+#define _NOT_CHECK_SIP_DIP
-+//#define	SL351x_NAT_TEST_BY_SMARTBITS		1	// Initialize 32 hash entries and test by SmartBITS
-+#define VITESSE_G5SWITCH	1
-+
-+#ifdef CONFIG_SL351x_NAT
-+
-+/*----------------------------------------------------------------------
-+* Definition
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL3516_ASIC
-+#define CONFIG_SL351x_NAT_TCP_UDP
-+#define CONFIG_SL351x_NAT_GRE
-+#define CONFIG_SL351x_TCP_UDP_RULE_ID	0
-+#define CONFIG_SL351x_GRE_RULE_ID		1
-+#else
-+#define CONFIG_SL351x_NAT_TCP_UDP
-+//#define CONFIG_SL351x_NAT_GRE
-+#define CONFIG_SL351x_TCP_UDP_RULE_ID	0
-+#define CONFIG_SL351x_GRE_RULE_ID		0
-+#endif
-+
-+#define	nat_printf					printk
-+#define NAT_FTP_CTRL_PORT 			(21)	// TCP
-+#define NAT_H323_PORT				(1720)	// TCP
-+#define NAT_T120_PORT				(1503)	// TCP
-+#define NAT_PPTP_PORT				(1723)	// TCP
-+#define NAT_TFTP_PORT 				(69)	// UDP
-+#define NAT_DNS_PORT 				(53)	// UDP
-+#define NAT_NTP_PORT				(123)	// UDP
-+#define NAT_RAS_PORT				(1719)	// UDP
-+#define NAT_BOOTP67_PORT			(67)	// UDP
-+#define NAT_BOOTP68_PORT			(68)	// UDP
-+
-+#define NAT_TCP_PORT_MAX			64
-+#define NAT_UDP_PORT_MAX			64
-+
-+#define GRE_PROTOCOL				(0x880b)
-+#define GRE_PROTOCOL_SWAP			__constant_htons(0x880b)
-+
-+#ifdef VITESSE_G5SWITCH
-+extern int Giga_switch;
-+#endif
-+
-+typedef struct
-+{
-+	u16		flags_ver;
-+	u16		protocol;
-+	u16		payload_length;
-+	u16		call_id;
-+	u32		seq;
-+	u32		ack;
-+} GRE_PKTHDR_T;
-+
-+/*----------------------------------------------------------------------
-+* NAT Configuration
-+*
-+* Note: Any change for network setting, the NAT configuration should
-+*       be changed also.
-+*	cfg->lan_port	0 if GMAC-0, 1: if GMAC-1
-+*	cfg->wan_port	0 if GMAC-0, 1: if GMAC-1
-+*	cfg->lan_ipaddr, cfg->lan_gateway, cfg->lan_netmask
-+*	cfg->wan_ipaddr, cfg->wan_gateway, cfg->wan_netmask
-+*
-+*----------------------------------------------------------------------*/
-+NAT_CFG_T 		nat_cfg;
-+static int		nat_initialized;
-+u32 			nat_collision;
-+
-+#ifdef CONFIG_SL351x_NAT_TCP_UDP
-+static u16		fixed_tcp_port_list[]={NAT_FTP_CTRL_PORT,
-+							   			NAT_H323_PORT,
-+							   			// NAT_T120_PORT,
-+							   			NAT_PPTP_PORT,
-+										0};
-+static u16		fixed_udp_port_list[]={NAT_DNS_PORT,
-+									  	NAT_NTP_PORT,
-+									  	NAT_TFTP_PORT,
-+										NAT_RAS_PORT,
-+									  	NAT_BOOTP67_PORT,
-+									  	NAT_BOOTP68_PORT,
-+									   	0};
-+#endif
-+
-+// #define _HAVE_DYNAMIC_PORT_LIST
-+#ifdef _HAVE_DYNAMIC_PORT_LIST
-+static u16		dynamic_tcp_port_list[NAT_TCP_PORT_MAX+1];
-+static u16		dynamic_udp_port_list[NAT_UDP_PORT_MAX+1]};
-+#endif
-+
-+/*----------------------------------------------------------------------
-+* Functions
-+*----------------------------------------------------------------------*/
-+int sl351x_nat_tcp_udp_output(struct sk_buff *skb, int port);
-+int sl351x_nat_udp_output(struct sk_buff *skb, int port);
-+int sl351x_nat_gre_output(struct sk_buff *skb, int port);
-+
-+extern int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2);
-+extern void hash_dump_entry(int index);
-+extern void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
-+extern void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
-+
-+#ifdef SL351x_NAT_TEST_BY_SMARTBITS
-+static void nat_init_test_entry(void);
-+#endif
-+/*----------------------------------------------------------------------
-+* sl351x_nat_init
-+*	initialize a NAT matching rule
-+*	Called by SL351x Driver
-+*		key		: port, protocol, Sip, Dip, Sport, Dport
-+*		Action	: Srce Q: HW Free Queue,
-+*				  Dest Q: HW TxQ
-+*				  Change DA
-+*				  Change SA
-+*                 Change Sip or Dip
-+*    			  Change Sport or Dport
-+*----------------------------------------------------------------------*/
-+void sl351x_nat_init(void)
-+{
-+	int					rc;
-+	GMAC_MRxCR0_T		mrxcr0;
-+	GMAC_MRxCR1_T		mrxcr1;
-+	GMAC_MRxCR2_T		mrxcr2;
-+	NAT_CFG_T			*cfg;
-+
-+	if (nat_initialized)
-+		return;
-+
-+	nat_initialized = 1;
-+
-+	if ((sizeof(NAT_HASH_ENTRY_T) > HASH_MAX_BYTES) ||
-+		(sizeof(GRE_HASH_ENTRY_T) > HASH_MAX_BYTES))
-+	{
-+		nat_printf("NAT_HASH_ENTRY_T structure Size is too larger!\n");
-+		while(1);
-+	}
-+
-+	cfg = (NAT_CFG_T *)&nat_cfg;
-+	memset((void *)cfg, 0, sizeof(NAT_CFG_T));
-+#ifdef _HAVE_DYNAMIC_PORT_LIST
-+	memset((void *)dynamic_tcp_port_list, 0, sizeof(dynamic_tcp_port_list));
-+	memset((void *)dynamic_udp_port_list, 0, sizeof(dynamic_udp_port_list));
-+#endif
-+
-+#ifdef VITESSE_G5SWITCH
-+	if(Giga_switch)
-+	{
-+		cfg->enabled			= 1;
-+		cfg->tcp_udp_rule_id 	= CONFIG_SL351x_TCP_UDP_RULE_ID;
-+		cfg->gre_rule_id 		= CONFIG_SL351x_GRE_RULE_ID;
-+		cfg->lan_port			= 1;
-+		cfg->wan_port			= 0;
-+		cfg->default_hw_txq 	= 3;
-+		cfg->tcp_tmo_interval 	= 60;
-+		cfg->udp_tmo_interval 	= 180;
-+		cfg->gre_tmo_interval 	= 60;
-+	}
-+	else
-+	{
-+		cfg->enabled			= 1;
-+		cfg->tcp_udp_rule_id 	= CONFIG_SL351x_TCP_UDP_RULE_ID;
-+		cfg->gre_rule_id 		= CONFIG_SL351x_GRE_RULE_ID;
-+		cfg->lan_port			= 0;
-+		cfg->wan_port			= 1;
-+		cfg->default_hw_txq 	= 3;
-+		cfg->tcp_tmo_interval 	= 60;
-+		cfg->udp_tmo_interval 	= 180;
-+		cfg->gre_tmo_interval 	= 60;
-+
-+	}
-+#endif
-+
-+#if 1	//	debug purpose
-+	cfg->ipcfg[0].total				= 1;
-+	cfg->ipcfg[0].entry[0].ipaddr	= IPIV(192,168,2,92);
-+	cfg->ipcfg[0].entry[0].netmask	= IPIV(255,255,255,0);
-+	cfg->ipcfg[1].total				= 1;
-+	cfg->ipcfg[1].entry[0].ipaddr	= IPIV(192,168,1,200);
-+	cfg->ipcfg[1].entry[0].netmask	= IPIV(255,255,255,0);
-+#endif
-+
-+#if 1
-+	cfg->xport.total = 0;
-+#else
-+	cfg->xport.total = 4;
-+
-+	// H.323/H.225 Call setup
-+	cfg->xport.entry[0].protocol = IPPROTO_TCP;
-+	cfg->xport.entry[0].sport_start = 0;
-+	cfg->xport.entry[0].sport_end = 0;
-+	cfg->xport.entry[0].dport_start = 1720;
-+	cfg->xport.entry[0].dport_end = 1720;
-+	cfg->xport.entry[1].protocol = IPPROTO_TCP;
-+	cfg->xport.entry[1].sport_start = 1720;
-+	cfg->xport.entry[1].sport_end = 1720;
-+	cfg->xport.entry[1].dport_start = 0;
-+	cfg->xport.entry[1].dport_end = 0;
-+
-+	// RAS Setup
-+	cfg->xport.entry[2].protocol = IPPROTO_UDP;
-+	cfg->xport.entry[2].sport_start = 0;
-+	cfg->xport.entry[2].sport_end = 0;
-+	cfg->xport.entry[2].dport_start = 1719;
-+	cfg->xport.entry[2].dport_end = 1719;
-+	cfg->xport.entry[3].protocol = IPPROTO_UDP;
-+	cfg->xport.entry[3].sport_start = 1719;
-+	cfg->xport.entry[3].sport_end = 1719;
-+	cfg->xport.entry[3].dport_start = 0;
-+	cfg->xport.entry[3].dport_end = 0;
-+#endif
-+
-+#ifdef CONFIG_SL351x_NAT_TCP_UDP
-+	mrxcr0.bits32 = 0;
-+	mrxcr1.bits32 = 0;
-+	mrxcr2.bits32 = 0;
-+	mrxcr0.bits.port = 1;
-+	mrxcr0.bits.l3 = 1;
-+	mrxcr0.bits.l4 = 1;
-+	mrxcr1.bits.sip = 1;
-+	mrxcr1.bits.dip = 1;
-+	mrxcr1.bits.l4_byte0_15 = 0x0f;	// Byte 0-3
-+	mrxcr0.bits.sprx = 3;
-+
-+	rc = mac_set_rule_reg(cfg->lan_port, cfg->tcp_udp_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
-+	if (rc < 0)
-+	{
-+		nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->lan_port, cfg->tcp_udp_rule_id);
-+	}
-+
-+	if (cfg->lan_port != cfg->wan_port)
-+	{
-+		rc = mac_set_rule_reg(cfg->wan_port, cfg->tcp_udp_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
-+		if (rc < 0)
-+		{
-+			nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->wan_port, cfg->tcp_udp_rule_id);
-+		}
-+	}
-+#endif
-+
-+#ifdef CONFIG_SL351x_NAT_GRE
-+	mrxcr0.bits32 = 0;
-+	mrxcr1.bits32 = 0;
-+	mrxcr2.bits32 = 0;
-+	mrxcr0.bits.port = 1;
-+	mrxcr0.bits.l3 = 1;
-+	mrxcr0.bits.l4 = 1;
-+	mrxcr1.bits.sip = 1;
-+	mrxcr1.bits.dip = 1;
-+	mrxcr1.bits.l4_byte0_15 = 0xcc;	// Byte 2, 3, 6, 7
-+	mrxcr0.bits.sprx = 4;			// see GMAC driver about SPR
-+
-+	rc = mac_set_rule_reg(cfg->lan_port, cfg->gre_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
-+	if (rc < 0)
-+	{
-+		nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->lan_port, cfg->gre_rule_id);
-+	}
-+
-+	if (cfg->lan_port != cfg->wan_port)
-+	{
-+		rc = mac_set_rule_reg(cfg->wan_port, cfg->gre_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
-+		if (rc < 0)
-+		{
-+			nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->wan_port, cfg->gre_rule_id);
-+		}
-+	}
-+#endif
-+
-+#ifdef SL351x_NAT_TEST_BY_SMARTBITS
-+	nat_init_test_entry();
-+#endif
-+}
-+
-+/*----------------------------------------------------------------------
-+* nat_build_keys
-+*	Note: To call this routine, the key->rule_id MUST be zero
-+*----------------------------------------------------------------------*/
-+static inline int nat_build_keys(NAT_KEY_T *key)
-+{
-+	return hash_gen_crc16((unsigned char *)key, NAT_KEY_SIZE) & HASH_BITS_MASK;
-+}
-+
-+/*----------------------------------------------------------------------
-+* gre_build_keys
-+*	Note: To call this routine, the key->rule_id MUST be zero
-+*----------------------------------------------------------------------*/
-+static inline int gre_build_keys(GRE_KEY_T *key)
-+{
-+	return hash_gen_crc16((unsigned char *)key, GRE_KEY_SIZE) & HASH_BITS_MASK;
-+}
-+
-+/*----------------------------------------------------------------------
-+* nat_write_hash_entry
-+*----------------------------------------------------------------------*/
-+static inline int nat_write_hash_entry(int index, void *hash_entry)
-+{
-+	int		i;
-+	u32		*srcep, *destp, *destp2;
-+
-+	srcep = (u32 *)hash_entry;
-+	destp = destp2 = (u32 *)&hash_tables[index][0];
-+
-+	for (i=0; i<(NAT_HASH_ENTRY_SIZE/sizeof(u32)); i++)
-+		*destp++ = *srcep++;
-+
-+	consistent_sync(destp2, NAT_HASH_ENTRY_SIZE, PCI_DMA_TODEVICE);
-+	return 0;
-+}
-+
-+/*----------------------------------------------------------------------
-+* gre_write_hash_entry
-+*----------------------------------------------------------------------*/
-+static inline int gre_write_hash_entry(int index, void *hash_entry)
-+{
-+	int		i;
-+	u32		*srcep, *destp, *destp2;
-+
-+	srcep = (u32 *)hash_entry;
-+	destp = destp2 = (u32 *)&hash_tables[index][0];
-+
-+	for (i=0; i<(GRE_HASH_ENTRY_SIZE/sizeof(u32)); i++)
-+		*destp++ = *srcep++;
-+
-+	consistent_sync(destp2, GRE_HASH_ENTRY_SIZE, PCI_DMA_TODEVICE);
-+	return 0;
-+}
-+
-+/*----------------------------------------------------------------------
-+* sl351x_nat_find_ipcfg
-+*	return NULL if not found
-+*----------------------------------------------------------------------*/
-+static NAT_IP_ENTRY_T *sl351x_nat_find_ipcfg(u32 ipaddr, int port)
-+{
-+	int				i;
-+	NAT_IP_ENTRY_T	*ipcfg;
-+
-+	ipcfg = (NAT_IP_ENTRY_T *)&nat_cfg.ipcfg[port].entry[0];
-+	for (i=0; iipaddr)
-+		{
-+			return ipcfg;
-+		}
-+	}
-+	return NULL;
-+}
-+
-+/*----------------------------------------------------------------------
-+* sl351x_nat_assign_qid
-+*----------------------------------------------------------------------*/
-+static int sl351x_nat_assign_qid(u8 proto, u32 sip, u32 dip, u16 sport, u16 dport)
-+{
-+	int 				i, total, qid;
-+	NAT_WRULE_ENTRY_T	*entry;
-+
-+	for (qid = 0; qidprotocol || entry->protocol==proto)
-+			{
-+				//if (!entry->sip_start && !entry->dip_start && !entry->sport_start && !entry->dport_start)
-+				//	continue; // UI take care
-+				if (entry->sip_start && !((sip >= entry->sip_start) &&
-+									   (sip <= entry->sip_end)))
-+					continue;
-+				if (entry->dip_start && !((dip >= entry->dip_start) &&
-+									   (dip <= entry->dip_end)))
-+					continue;
-+				if (entry->sport_start && !((sport >= entry->sport_start) &&
-+									   (sport <= entry->sport_end)))
-+					continue;
-+				if (entry->dport_start && !((dport >= entry->dport_start)
-+					 			       && (dport <= entry->dport_end)))
-+					continue;
-+				return qid;
-+			}
-+		}
-+	}
-+	return nat_cfg.default_hw_txq;
-+}
-+
-+/*----------------------------------------------------------------------
-+* sl351x_nat_input
-+*	Handle NAT input frames
-+*	Called by SL351x Driver - Handle Default Rx Queue
-+*	Notes: The caller must make sure that the l3off & l4offset should not be zero.
-+*	SL351x NAT Frames should meet the following conditions:
-+*	1. TCP or UDP frame
-+*	2. Cannot be special ALGs ports which TCP/UDP data is updated
-+*	3. LAN-IN Frames:
-+*		Source IP is in the LAN subnet and Destination is not in the LAN subnet
-+*	4. WAN-IN Frames
-+*		Destination IP is in the WAN port IP
-+*
-+*	Example Ports
-+*	1. TCP/UDP data is updated
-+*		(a) FTP Control Packet
-+*		(b) VoIP Packets
-+*		(c) etc. (add in future)
-+*	2. UDP Low packet rate, not worth
-+*		(b) TFTP Destination Port is 69
-+*		(b) DNS  53
-+*		(c) NTP  123
-+*		(d) etc. (add in future)
-+*----------------------------------------------------------------------*/
-+void sl351x_nat_input(struct sk_buff *skb, int port, void *l3off, void *l4off)
-+{
-+	int 				i, found;
-+	u32					sip, dip;
-+	u16					sport, dport;
-+	struct ethhdr		*ether_hdr;
-+	struct iphdr		*ip_hdr;
-+	struct tcphdr		*tcp_hdr;
-+	struct pppoe_hdr	*pppoe_hdr;
-+	NAT_CB_T			*nat_cb;
-+	u8					proto, pppoe_frame=0;
-+	NAT_CFG_T			*cfg;
-+	u16					ppp_proto;
-+	NAT_IP_ENTRY_T		*ipcfg;
-+	NAT_XPORT_ENTRY_T	*xentry;
-+	GRE_PKTHDR_T		*gre_hdr;
-+#ifdef CONFIG_SL351x_NAT_TCP_UDP
-+	u16 				*port_ptr;
-+#endif
-+
-+	cfg = (NAT_CFG_T *)&nat_cfg;
-+	if (!cfg->enabled || !cfg->ipcfg[port].total)
-+		return;
-+
-+	ip_hdr = (struct iphdr *)&(skb->data[(u32)l3off]);
-+	proto = ip_hdr->protocol;
-+
-+	tcp_hdr = (struct tcphdr *)&(skb->data[(u32)l4off]);
-+	gre_hdr = (GRE_PKTHDR_T *)tcp_hdr;
-+	sport = ntohs(tcp_hdr->source);
-+	dport = ntohs(tcp_hdr->dest);
-+
-+	sip = ntohl(ip_hdr->saddr);
-+	dip = ntohl(ip_hdr->daddr);
-+
-+	if (dip == IPIV(255,255,255,255))
-+		return;
-+
-+	if (port == cfg->lan_port)
-+	{
-+		ipcfg = (NAT_IP_ENTRY_T *)&cfg->ipcfg[port].entry[0];
-+		for (i=0, found=0; iipcfg[port].total; i++, ipcfg++)
-+		{
-+			u32 subnet = ipcfg->ipaddr & ipcfg->netmask;
-+			if (((sip & ipcfg->netmask) == subnet) &&
-+				((dip & ipcfg->netmask) != subnet))
-+			{
-+				found = 1;
-+				break;
-+			}
-+		}
-+		if (!found)
-+			return;
-+	}
-+	else
-+	{
-+#ifndef _NOT_CHECK_SIP_DIP	// enable it if know and get the wan ip address
-+		if (!sl351x_nat_find_ipcfg(dip, port))
-+		{
-+			printk("WAN->LAN Incorrect Dip %d.%d.%d.%d\n", HIPQUAD(dip));
-+			return;
-+		}
-+#endif
-+		ether_hdr = (struct ethhdr *)skb->data;
-+		pppoe_hdr = (struct pppoe_hdr *)(ether_hdr + 1);
-+		ppp_proto = *(u16 *)&pppoe_hdr->tag[0];
-+		if (ether_hdr->h_proto == __constant_htons(ETH_P_PPP_SES)	// 0x8864
-+			&& ppp_proto == __constant_htons(PPP_IP) )				// 0x21
-+		{
-+			pppoe_frame = 1;
-+		}
-+	}
-+
-+#ifdef CONFIG_SL351x_NAT_TCP_UDP
-+	if (proto == IPPROTO_TCP)
-+	{
-+#ifdef	NAT_DEBUG_MSG
-+		nat_printf("From   GMAC-%d: 0x%-4X TCP %d.%d.%d.%d [%d] --> %d.%d.%d.%d [%d]",
-+				port, ntohs(ip_hdr->id),
-+				NIPQUAD(ip_hdr->saddr), sport,
-+				NIPQUAD(ip_hdr->daddr), dport);
-+		if (tcp_flag_word(tcp_hdr) & TCP_FLAG_SYN) nat_printf(" SYN");
-+		if (tcp_flag_word(tcp_hdr) & TCP_FLAG_FIN) nat_printf(" FIN");
-+		if (tcp_flag_word(tcp_hdr) & TCP_FLAG_RST) nat_printf(" RST");
-+		if (tcp_flag_word(tcp_hdr) & TCP_FLAG_ACK) nat_printf(" ACK");
-+		nat_printf("\n");
-+#endif
-+		// if (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN | TCP_FLAG_FIN | TCP_FLAG_RST))
-+		if (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN))
-+		{
-+			return;
-+		}
-+		port_ptr = fixed_tcp_port_list;
-+		for (i=0; *port_ptr; i++, port_ptr++)
-+		{
-+			if (sport == *port_ptr || dport == *port_ptr)
-+				return;
-+		}
-+#ifdef _HAVE_DYNAMIC_PORT_LIST
-+		port_ptr = dynamic_tcp_port_list;
-+		for (i=0; *port_ptr; i++, port_ptr++)
-+		{
-+			if (sport == *port_ptr || dport == *port_ptr)
-+				return;
-+		}
-+#endif
-+	}
-+	else if (proto == IPPROTO_UDP)
-+	{
-+#ifdef	NAT_DEBUG_MSG
-+		nat_printf("From   GMAC-%d: 0x%-4X UDP %d.%d.%d.%d [%d] --> %d.%d.%d.%d [%d]",
-+				port, ntohs(ip_hdr->id),
-+				NIPQUAD(ip_hdr->saddr), sport,
-+				NIPQUAD(ip_hdr->daddr), dport);
-+		nat_printf("\n");
-+#endif
-+		port_ptr = fixed_udp_port_list;
-+		for (i=0; *port_ptr; i++, port_ptr++)
-+		{
-+			if (sport == *port_ptr || dport == *port_ptr)
-+				return;
-+		}
-+#ifdef _HAVE_DYNAMIC_PORT_LIST
-+		port_ptr = dynamic_udp_port_list;
-+		for (i=0; *port_ptr; i++, port_ptr++)
-+		{
-+			if (sport == *port_ptr || dport == *port_ptr)
-+				return;
-+		}
-+#endif
-+	}
-+	else
-+#endif	// CONFIG_SL351x_NAT_TCP_UDP
-+#ifdef CONFIG_SL351x_NAT_GRE
-+	if (proto == IPPROTO_GRE)
-+	{
-+		if (gre_hdr->protocol != GRE_PROTOCOL_SWAP)
-+			return;
-+#ifdef	NAT_DEBUG_MSG
-+		nat_printf("From   GMAC-%d: 0x%-4X GRE %d.%d.%d.%d [%d] --> %d.%d.%d.%d",
-+				port, ntohs(ip_hdr->id),
-+				NIPQUAD(ip_hdr->saddr), ntohs(gre_hdr->call_id),
-+				NIPQUAD(ip_hdr->daddr));
-+		nat_printf("\n");
-+#endif
-+	}
-+	else
-+#endif
-+		return;
-+
-+
-+	// check xport list
-+	xentry = (NAT_XPORT_ENTRY_T *)&cfg->xport.entry[0];
-+	for (i=0; ixport.total; i++, xentry++)
-+	{
-+		if (!xentry->protocol || xentry->protocol == proto)
-+		{
-+			//if (!xentry->sport_start && !xentry->dport_start) // UI take care
-+			//	continue;
-+			if (xentry->sport_start && !((sport >= xentry->sport_start) &&
-+									   (sport <= xentry->sport_end)))
-+				continue;
-+			if (xentry->dport_start && !((dport >= xentry->dport_start)
-+					 			       && (dport <= xentry->dport_end)))
-+				continue;
-+			return;
-+		}
-+	}
-+
-+	nat_cb = NAT_SKB_CB(skb);
-+	if (((u32)nat_cb & 3))
-+	{
-+		nat_printf("%s ERROR! nat_cb is not alignment!!!!!!\n", __func__);
-+		return;
-+	}
-+	nat_cb->tag = NAT_CB_TAG;
-+	memcpy(nat_cb->sa, skb->data+6, 6);
-+	nat_cb->sip = ip_hdr->saddr;
-+	nat_cb->dip = ip_hdr->daddr;
-+	if (proto == IPPROTO_GRE)
-+	{
-+		nat_cb->sport = gre_hdr->protocol;
-+		nat_cb->dport = gre_hdr->call_id;
-+	}
-+	else
-+	{
-+		nat_cb->sport = tcp_hdr->source;
-+		nat_cb->dport = tcp_hdr->dest;
-+	}
-+	nat_cb->pppoe_frame = pppoe_frame;
-+}
-+
-+/*----------------------------------------------------------------------
-+* sl351x_nat_output
-+*	Handle NAT output frames
-+*	Called by SL351x Driver - Transmit
-+*
-+*	1. If not SL351x NAT frames, return FALSE
-+*	2. LAN-to-WAN frames
-+*		(1) Sip must be WAN IP
-+*	3. If TCP SY/RST/FIN frame, return
-+*	4. Build the hash key and get the hash index
-+*	5. If V-Bit is ON, return.
-+*	6. Write hash entry and validate it
-+*
-+*----------------------------------------------------------------------*/
-+int sl351x_nat_output(struct sk_buff *skb, int port)
-+{
-+	struct iphdr		*ip_hdr;
-+	u8					proto;
-+	NAT_CB_T			*nat_cb;
-+
-+	nat_cb = NAT_SKB_CB(skb);
-+	if (nat_cb->tag != NAT_CB_TAG)
-+		return 0;
-+
-+	if (((u32)nat_cb & 3))
-+	{
-+		nat_printf("%s ERROR! nat_cb is not alignment!!!!!!\n", __func__);
-+		return 0;
-+	}
-+	ip_hdr = (struct iphdr *)skb->h.ipiph;
-+	proto = ip_hdr->protocol;
-+
-+	switch (proto)
-+	{
-+		case IPPROTO_TCP:
-+		case IPPROTO_UDP:
-+			return sl351x_nat_tcp_udp_output(skb, port);
-+		case IPPROTO_GRE:
-+			return sl351x_nat_gre_output(skb, port);
-+	}
-+	return 0;
-+}
-+
-+/*----------------------------------------------------------------------
-+* sl351x_nat_tcp_udp_output
-+*	Handle NAT TCP/UDP output frames
-+*----------------------------------------------------------------------*/
-+int sl351x_nat_tcp_udp_output(struct sk_buff *skb, int port)
-+{
-+	u32					sip, dip;
-+	struct ethhdr		*ether_hdr;
-+	struct iphdr		*ip_hdr;
-+	struct tcphdr		*tcp_hdr;
-+	struct pppoe_hdr	*pppoe_hdr;
-+	NAT_CB_T			*nat_cb;
-+	NAT_CFG_T			*cfg;
-+	u8					proto;
-+	u16					sport, dport, ppp_proto;
-+	u32					hash_data[HASH_MAX_DWORDS];
-+	NAT_HASH_ENTRY_T	*hash_entry;
-+	int					hash_index;
-+	struct ip_conntrack *nat_ip_conntrack;
-+	enum ip_conntrack_info ctinfo;
-+
-+	nat_cb = NAT_SKB_CB(skb);
-+	cfg = (NAT_CFG_T *)&nat_cfg;
-+
-+	ether_hdr = (struct ethhdr *)skb->data;
-+	ip_hdr = (struct iphdr *)skb->h.ipiph;
-+	tcp_hdr = (struct tcphdr *)((u32)ip_hdr + (ip_hdr->ihl<<2));
-+	sip = ntohl(ip_hdr->saddr);
-+	dip = ntohl(ip_hdr->daddr);
-+	proto = ip_hdr->protocol;
-+	sport = ntohs(tcp_hdr->source);
-+	dport = ntohs(tcp_hdr->dest);
-+
-+#ifdef	NAT_DEBUG_MSG
-+	{
-+		nat_printf("To   GMAC-%d: 0x%-4X [%d] %d.%d.%d.%d [%d] --> %d.%d.%d.%d [%d]",
-+				port, ntohs(ip_hdr->id), proto,
-+				NIPQUAD(ip_hdr->saddr), sport,
-+				NIPQUAD(ip_hdr->daddr), dport);
-+		if (proto == IPPROTO_TCP)
-+		{
-+			if (tcp_flag_word(tcp_hdr) & TCP_FLAG_SYN) nat_printf(" SYN");
-+			if (tcp_flag_word(tcp_hdr) & TCP_FLAG_FIN) nat_printf(" FIN");
-+			if (tcp_flag_word(tcp_hdr) & TCP_FLAG_RST) nat_printf(" RST");
-+			if (tcp_flag_word(tcp_hdr) & TCP_FLAG_ACK) nat_printf(" ACK");
-+		}
-+		nat_printf("\n");
-+	}
-+#endif
-+	nat_ip_conntrack = ip_conntrack_get(skb, &ctinfo);
-+	if (!nat_ip_conntrack)
-+	{
-+		nat_printf("IP conntrack info is not found!\n");
-+		return 0;
-+	}
-+	// nat_printf("nat_ip_conntrack = 0x%x, status=0x%lx, ctinfo=%d\n", (u32)nat_ip_conntrack, nat_ip_conntrack->status, ctinfo);
-+	// if (nat_ip_conntrack->master || nat_ip_conntrack->helper)
-+	if (nat_ip_conntrack->helper)
-+	{
-+		nat_printf("Sport=%d Dport=%d master=0x%x, helper=0x%x\n", sport, dport, (u32)nat_ip_conntrack->master, (u32)nat_ip_conntrack->helper);
-+		return 0;
-+	}
-+
-+	//if (proto == IPPROTO_TCP && !(nat_ip_conntrack->status & IPS_ASSURED))
-+	//	return 0;
-+
-+#ifdef	NAT_DEBUG_MSG
-+	nat_printf("nat_ip_conntrack=0x%x, nat_cb->state=%d\n", (u32)nat_ip_conntrack, nat_cb->state);
-+	nat_printf("lan2wan_hash_index=%d,  wan2lan_hash_index=%d\n", nat_ip_conntrack->lan2wan_hash_index, nat_ip_conntrack->wan2lan_hash_index);
-+	nat_printf("lan2wan_collision=%d, wan2lan_collision=%d\n", nat_ip_conntrack->lan2wan_collision, nat_ip_conntrack->wan2lan_collision);
-+#endif
-+	if (proto == IPPROTO_TCP)
-+	{
-+		if (nat_cb->state >= TCP_CONNTRACK_FIN_WAIT && nat_cb->state <= TCP_CONNTRACK_CLOSE)
-+		{
-+			if 	(nat_ip_conntrack->lan2wan_hash_index)
-+			{
-+#ifdef	NAT_DEBUG_MSG
-+				nat_printf("Invalidate LAN->WAN hash entry %d\n", nat_ip_conntrack->lan2wan_hash_index - 1);
-+#endif
-+				hash_nat_disable_owner(nat_ip_conntrack->lan2wan_hash_index - 1);
-+				hash_invalidate_entry(nat_ip_conntrack->lan2wan_hash_index - 1);
-+				nat_ip_conntrack->lan2wan_hash_index = 0;
-+			}
-+			if 	(nat_ip_conntrack->wan2lan_hash_index)
-+			{
-+#ifdef	NAT_DEBUG_MSG
-+				nat_printf("Invalidate WAN->LAN hash entry %d\n", nat_ip_conntrack->wan2lan_hash_index - 1);
-+#endif
-+				hash_nat_disable_owner(nat_ip_conntrack->wan2lan_hash_index - 1);
-+				hash_invalidate_entry(nat_ip_conntrack->wan2lan_hash_index - 1);
-+				nat_ip_conntrack->wan2lan_hash_index = 0;
-+			}
-+			return 0;
-+
-+		}
-+		else if (nat_cb->state != TCP_CONNTRACK_ESTABLISHED)
-+		{
-+			return 0;
-+		}
-+	}
-+	if (proto == IPPROTO_TCP && (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN | TCP_FLAG_FIN | TCP_FLAG_RST)))
-+	// if (proto == IPPROTO_TCP &&  (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN)))
-+		return 0;
-+
-+	hash_entry = (NAT_HASH_ENTRY_T *)&hash_data;
-+	if (port == cfg->wan_port)	// LAN-to-WAN
-+	{
-+		if (nat_ip_conntrack->lan2wan_hash_index || nat_ip_conntrack->lan2wan_collision)
-+			return 0;
-+#ifndef _NOT_CHECK_SIP_DIP	// enable it if know and get the wan ip address
-+		if (!sl351x_nat_find_ipcfg(sip, port))
-+		{
-+			printk("LAN->WAN Incorrect Sip %d.%d.%d.%d\n", HIPQUAD(sip));
-+			return 0;
-+		}
-+#endif
-+		// Note: unused fields (including rule_id) MUST be zero
-+		hash_entry->key.Ethertype 	= 0;
-+		hash_entry->key.port_id 	= cfg->lan_port;
-+		hash_entry->key.rule_id 	= 0;
-+		hash_entry->key.ip_protocol = proto;
-+		hash_entry->key.reserved1 	= 0;
-+		hash_entry->key.reserved2 	= 0;
-+		hash_entry->key.sip 		= ntohl(nat_cb->sip);
-+		hash_entry->key.dip 		= ntohl(nat_cb->dip);
-+		hash_entry->key.sport 		= nat_cb->sport;
-+		hash_entry->key.dport 		= nat_cb->dport;
-+
-+		hash_index = nat_build_keys(&hash_entry->key);
-+
-+#ifdef NAT_DEBUG_LAN_HASH_TIMEOUT
-+		if (hash_get_nat_owner_flag(hash_index))
-+			return 0;
-+#endif
-+		if (hash_get_valid_flag(hash_index))
-+		{
-+			nat_ip_conntrack->lan2wan_collision = 1;
-+			nat_collision++;
-+#if 0
-+			if (proto == IPPROTO_TCP && (tcp_flag_word(tcp_hdr) & (TCP_FLAG_FIN | TCP_FLAG_RST)))
-+			{
-+				if (memcmp((void *)&hash_entry->key, hash_get_entry(hash_index), sizeof(NAT_KEY_T)) == 0)
-+				{
-+   					hash_nat_disable_owner(hash_index);
-+ 					hash_invalidate_entry(hash_index); // Must last one, else HW Tx fast SW
-+ 					// nat_printf("Invalidate nat hash entry %d\n", hash_index);
-+ 				}
-+			}
-+#endif
-+			return 0;
-+		}
-+
-+		// write hash entry
-+		hash_entry->key.rule_id = cfg->tcp_udp_rule_id;
-+		memcpy(hash_entry->param.da, skb->data, 6);
-+		memcpy(hash_entry->param.sa, skb->data+6, 6);
-+		hash_entry->param.Sip = sip;
-+		hash_entry->param.Dip = dip;
-+		hash_entry->param.Sport = sport;
-+		hash_entry->param.Dport = dport;
-+		hash_entry->param.vlan = 0;
-+		hash_entry->param.sw_id = 0;
-+		hash_entry->param.mtu = 0;
-+		// check PPPoE
-+		pppoe_hdr = (struct pppoe_hdr *)(ether_hdr + 1);
-+		ppp_proto = *(u16 *)&pppoe_hdr->tag[0];
-+		if (ether_hdr->h_proto == __constant_htons(ETH_P_PPP_SES)	// 0x8864
-+			&& ppp_proto == __constant_htons(PPP_IP) )				// 0x21
-+		{
-+			hash_entry->action.dword = NAT_PPPOE_LAN2WAN_ACTIONS;
-+			hash_entry->param.pppoe = htons(pppoe_hdr->sid);
-+		}
-+		else
-+		{
-+			hash_entry->action.dword = NAT_LAN2WAN_ACTIONS;
-+			hash_entry->param.pppoe = 0;
-+		}
-+		hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(proto, sip, dip, sport, dport);
-+		hash_entry->action.bits.dest_qid +=	(cfg->wan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
-+		hash_entry->tmo.counter = hash_entry->tmo.interval =
-+						(proto == IPPROTO_TCP) ? cfg->tcp_tmo_interval : cfg->udp_tmo_interval;
-+		nat_write_hash_entry(hash_index, hash_entry);
-+		// nat_printf("%lu Validate a LAN hash entry %d\n", jiffies/HZ, hash_index);
-+		// hash_dump_entry(hash_index);
-+		hash_nat_enable_owner(hash_index);
-+		hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
-+ 		nat_ip_conntrack->lan2wan_hash_index = hash_index + 1;
-+ 		nat_ip_conntrack->hw_nat |= 1;
-+		return 0;
-+	}
-+	else // WAN-to-LAN
-+	{
-+		if (nat_ip_conntrack->wan2lan_hash_index || nat_ip_conntrack->wan2lan_collision)
-+			return 0;
-+
-+		// Note: unused fields (including rule_id) MUST be zero
-+		hash_entry->key.Ethertype 	= 0;
-+		hash_entry->key.port_id 	= cfg->wan_port;
-+		hash_entry->key.rule_id 	= 0;
-+		hash_entry->key.ip_protocol = proto;
-+		hash_entry->key.reserved1 	= 0;
-+		hash_entry->key.reserved2 	= 0;
-+		hash_entry->key.sip 		= ntohl(nat_cb->sip);
-+		hash_entry->key.dip 		= ntohl(nat_cb->dip);
-+		hash_entry->key.sport 		= nat_cb->sport;
-+		hash_entry->key.dport 		= nat_cb->dport;
-+
-+		hash_index = nat_build_keys(&hash_entry->key);
-+
-+#ifdef NAT_DEBUG_WAN_HASH_TIMEOUT
-+		if (hash_get_nat_owner_flag(hash_index))
-+			return 0;
-+#endif
-+		if (hash_get_valid_flag(hash_index))
-+		{
-+			nat_ip_conntrack->wan2lan_collision = 1;
-+			nat_collision++;
-+#if 0
-+			if (proto == IPPROTO_TCP && (tcp_flag_word(tcp_hdr) & (TCP_FLAG_FIN | TCP_FLAG_RST)))
-+			{
-+				if (memcmp((void *)&hash_entry->key, hash_get_entry(hash_index), sizeof(NAT_KEY_T)) == 0)
-+				{
-+   					hash_nat_disable_owner(hash_index);
-+ 					hash_invalidate_entry(hash_index); // Must last one, else HW Tx fast SW
-+  					// nat_printf("Invalidate nat hash entry %d\n", hash_index);
-+				}
-+			}
-+#endif
-+			return 0;
-+		}
-+
-+		// write hash entry
-+		hash_entry->key.rule_id = cfg->tcp_udp_rule_id;
-+		memcpy(hash_entry->param.da, skb->data, 6);
-+		memcpy(hash_entry->param.sa, skb->data+6, 6);
-+		hash_entry->param.Sip = sip;
-+		hash_entry->param.Dip = dip;
-+		hash_entry->param.Sport = sport;
-+		hash_entry->param.Dport = dport;
-+		hash_entry->param.vlan = 0;
-+		hash_entry->param.pppoe = 0;
-+		hash_entry->param.sw_id = 0;
-+		hash_entry->param.mtu = 0;
-+		hash_entry->action.dword = (nat_cb->pppoe_frame) ? NAT_PPPOE_WAN2LAN_ACTIONS : NAT_WAN2LAN_ACTIONS;
-+		hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(proto, sip, dip, sport, dport);
-+		hash_entry->action.bits.dest_qid += (cfg->lan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;;
-+		hash_entry->tmo.counter = hash_entry->tmo.interval =
-+						(proto == IPPROTO_TCP) ? cfg->tcp_tmo_interval : cfg->udp_tmo_interval;
-+		nat_write_hash_entry(hash_index, hash_entry);
-+
-+		// nat_printf("%lu Validate a WAN hash entry %d\n", jiffies/HZ, hash_index);
-+		// hash_dump_entry(hash_index);
-+   		hash_nat_enable_owner(hash_index);
-+ 		hash_validate_entry(hash_index); // Must last one, else HW Tx fast SW
-+ 		nat_ip_conntrack->wan2lan_hash_index = hash_index + 1;
-+ 		nat_ip_conntrack->hw_nat |= 2;
-+		return 0;
-+	}
-+	return 0;
-+}
-+
-+/*----------------------------------------------------------------------
-+* sl351x_nat_gre_output
-+*	Handle NAT GRE output frames
-+*----------------------------------------------------------------------*/
-+int sl351x_nat_gre_output(struct sk_buff *skb, int port)
-+{
-+	u32					sip, dip;
-+	struct ethhdr		*ether_hdr;
-+	struct iphdr		*ip_hdr;
-+	struct pppoe_hdr	*pppoe_hdr;
-+	GRE_PKTHDR_T		*gre_hdr;
-+	NAT_CB_T			*nat_cb;
-+	NAT_CFG_T			*cfg;
-+	u16					ppp_proto;
-+	u32					hash_data[HASH_MAX_DWORDS];
-+	GRE_HASH_ENTRY_T	*hash_entry;
-+	int					hash_index;
-+	struct ip_conntrack *nat_ip_conntrack;
-+	enum ip_conntrack_info ctinfo;
-+
-+	nat_cb = NAT_SKB_CB(skb);
-+	cfg = (NAT_CFG_T *)&nat_cfg;
-+
-+	ether_hdr = (struct ethhdr *)skb->data;
-+	ip_hdr = (struct iphdr *)skb->h.ipiph;
-+	gre_hdr = (GRE_PKTHDR_T *)((u32)ip_hdr + (ip_hdr->ihl<<2));
-+	sip = ntohl(ip_hdr->saddr);
-+	dip = ntohl(ip_hdr->daddr);
-+
-+#ifdef	NAT_DEBUG_MSG
-+	{
-+		nat_printf("To   GMAC-%d: 0x%-4X GRE %d.%d.%d.%d [%d] --> %d.%d.%d.%d",
-+				port, ntohs(ip_hdr->id),
-+				NIPQUAD(ip_hdr->saddr), ntohs(gre_hdr->call_id),
-+				NIPQUAD(ip_hdr->daddr));
-+		nat_printf("\n");
-+	}
-+#endif
-+	nat_ip_conntrack = ip_conntrack_get(skb, &ctinfo);
-+	if (nat_ip_conntrack)
-+	{
-+		// if (nat_ip_conntrack->master || nat_ip_conntrack->helper)
-+		if (nat_ip_conntrack->helper)
-+		{
-+			nat_printf("GRE Call-ID=%d, master=0x%x, helper=0x%x\n", ntohs(gre_hdr->call_id), (u32)nat_ip_conntrack->master, (u32)nat_ip_conntrack->helper);
-+			return 0;
-+		}
-+		if (!(nat_ip_conntrack->status & IPS_ASSURED))
-+			return 0;
-+	}
-+
-+	hash_entry = (GRE_HASH_ENTRY_T *)&hash_data;
-+	if (port == cfg->wan_port)	// LAN-to-WAN
-+	{
-+#ifdef _NOT_CHECK_SIP_DIP	// enable it if know and get the wan ip address
-+		if (!sl351x_nat_find_ipcfg(sip, port))
-+		{
-+			printk("LAN->WAN Incorrect Sip %d.%d.%d.%d\n", HIPQUAD(sip));
-+			return 0;
-+		}
-+#endif
-+		// Note: unused fields (including rule_id) MUST be zero
-+		hash_entry->key.Ethertype 	= 0;
-+		hash_entry->key.port_id 	= cfg->lan_port;
-+		hash_entry->key.rule_id 	= 0;
-+		hash_entry->key.ip_protocol = IPPROTO_GRE;
-+		hash_entry->key.reserved1 	= 0;
-+		hash_entry->key.reserved2 	= 0;
-+		hash_entry->key.reserved3 	= 0;
-+		hash_entry->key.reserved4 	= 0;
-+		hash_entry->key.sip 		= ntohl(nat_cb->sip);
-+		hash_entry->key.dip 		= ntohl(nat_cb->dip);
-+		hash_entry->key.protocol	= nat_cb->sport;
-+		hash_entry->key.call_id 	= nat_cb->dport;
-+
-+		hash_index = gre_build_keys(&hash_entry->key);
-+
-+#ifdef NAT_DEBUG_LAN_HASH_TIMEOUT
-+		if (hash_get_nat_owner_flag(hash_index))
-+			return 0;
-+#endif
-+		if (hash_get_valid_flag(hash_index))
-+		{
-+			return 0;
-+		}
-+
-+		// write hash entry
-+		hash_entry->key.rule_id = cfg->gre_rule_id;
-+		memcpy(hash_entry->param.da, skb->data, 6);
-+		memcpy(hash_entry->param.sa, skb->data+6, 6);
-+		hash_entry->param.Sip = sip;
-+		hash_entry->param.Dip = dip;
-+		hash_entry->param.Sport = 0;
-+		hash_entry->param.Dport = ntohs(gre_hdr->call_id);
-+		hash_entry->param.vlan = 0;
-+		hash_entry->param.sw_id = 0;
-+		hash_entry->param.mtu = 0;
-+		// check PPPoE
-+		pppoe_hdr = (struct pppoe_hdr *)(ether_hdr + 1);
-+		ppp_proto = *(u16 *)&pppoe_hdr->tag[0];
-+		if (ether_hdr->h_proto == __constant_htons(ETH_P_PPP_SES)	// 0x8864
-+			&& ppp_proto == __constant_htons(PPP_IP) )				// 0x21
-+		{
-+			hash_entry->action.dword = NAT_PPPOE_PPTP_LAN2WAN_ACTIONS;
-+			hash_entry->param.pppoe = htons(pppoe_hdr->sid);
-+		}
-+		else
-+		{
-+			hash_entry->action.dword = NAT_PPTP_LAN2WAN_ACTIONS;
-+			hash_entry->param.pppoe = 0;
-+		}
-+		hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(IPPROTO_GRE, sip, dip, 0, ntohs(gre_hdr->call_id));
-+		hash_entry->action.bits.dest_qid +=	(cfg->wan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
-+		hash_entry->tmo.counter = hash_entry->tmo.interval = cfg->gre_tmo_interval;
-+		gre_write_hash_entry(hash_index, hash_entry);
-+		// nat_printf("%lu Validate a LAN hash entry %d\n", jiffies/HZ, hash_index);
-+		// hash_dump_entry(hash_index);
-+		hash_nat_enable_owner(hash_index);
-+		hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
-+		return 0;
-+	}
-+	else // WAN-to-LAN
-+	{
-+		// Note: unused fields (including rule_id) MUST be zero
-+		hash_entry->key.Ethertype 	= 0;
-+		hash_entry->key.port_id 	= cfg->wan_port;
-+		hash_entry->key.rule_id 	= 0;
-+		hash_entry->key.ip_protocol = IPPROTO_GRE;
-+		hash_entry->key.reserved1 	= 0;
-+		hash_entry->key.reserved2 	= 0;
-+		hash_entry->key.reserved3 	= 0;
-+		hash_entry->key.reserved4 	= 0;
-+		hash_entry->key.sip 		= ntohl(nat_cb->sip);
-+		hash_entry->key.dip 		= ntohl(nat_cb->dip);
-+		hash_entry->key.protocol	= nat_cb->sport;
-+		hash_entry->key.call_id		= nat_cb->dport;
-+
-+		hash_index = gre_build_keys(&hash_entry->key);
-+
-+#ifdef NAT_DEBUG_WAN_HASH_TIMEOUT
-+		if (hash_get_nat_owner_flag(hash_index))
-+			return 0;
-+#endif
-+		if (hash_get_valid_flag(hash_index))
-+		{
-+			return 0;
-+		}
-+
-+		// write hash entry
-+		hash_entry->key.rule_id = cfg->gre_rule_id;
-+		memcpy(hash_entry->param.da, skb->data, 6);
-+		memcpy(hash_entry->param.sa, skb->data+6, 6);
-+		hash_entry->param.Sip = sip;
-+		hash_entry->param.Dip = dip;
-+		hash_entry->param.Sport = 0;
-+		hash_entry->param.Dport = ntohs(gre_hdr->call_id);
-+		hash_entry->param.vlan = 0;
-+		hash_entry->param.pppoe = 0;
-+		hash_entry->param.sw_id = 0;
-+		hash_entry->param.mtu = 0;
-+		hash_entry->action.dword = (nat_cb->pppoe_frame) ? NAT_PPPOE_PPTP_WAN2LAN_ACTIONS : NAT_PPTP_WAN2LAN_ACTIONS;
-+		hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(IPPROTO_GRE, sip, dip, 0, ntohs(gre_hdr->call_id));
-+		hash_entry->action.bits.dest_qid += (cfg->lan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;;
-+		hash_entry->tmo.counter = hash_entry->tmo.interval = cfg->gre_tmo_interval;
-+		gre_write_hash_entry(hash_index, hash_entry);
-+
-+		// nat_printf("%lu Validate a WAN hash entry %d\n", jiffies/HZ, hash_index);
-+		// hash_dump_entry(hash_index);
-+   		hash_nat_enable_owner(hash_index);
-+ 		hash_validate_entry(hash_index); // Must last one, else HW Tx fast SW
-+		return 0;
-+	}
-+	return 0;
-+}
-+
-+
-+#ifdef _HAVE_DYNAMIC_PORT_LIST
-+/*----------------------------------------------------------------------
-+* sl_nat_add_port
-+*----------------------------------------------------------------------*/
-+void sl_nat_add_port(u8 protocol, u16 port)
-+{
-+	int 	i;
-+	u16		*port_ptr;
-+
-+	if (protocol == IPPROTO_TCP)
-+		port_ptr = dynamic_tcp_port_list;
-+	else if (protocol == IPPROTO_UDP)
-+		port_ptr = dynamic_udp_port_list;
-+	else
-+		return;
-+
-+	for (i=0; *port_ptr; i++)
-+	{
-+		if (port == *port_ptr)
-+			return;
-+		port_ptr++;
-+	}
-+	port_ptr++;
-+	*port_ptr = port;
-+}
-+
-+/*----------------------------------------------------------------------
-+* sl_nat_remove_port
-+*----------------------------------------------------------------------*/
-+void sl_nat_remove_port(u8 protocol, u16 port)
-+{
-+	int 	i, j;
-+	u16		*port_ptr, *next;
-+
-+	if (protocol == IPPROTO_TCP)
-+		port_ptr = dynamic_tcp_port_list;
-+	else if (protocol == IPPROTO_UDP)
-+		port_ptr = dynamic_udp_port_list;
-+	else
-+		return;
-+
-+	for (i=0; *port_ptr; i++, port_ptr++)
-+	{
-+		if (port == *port_ptr)
-+		{
-+			port_next = port_ptr + 1;
-+			for (j=i+1; *port_next; i++, j++)
-+				*port_ptr++ = *port_next++;
-+			*port_ptr = 0;
-+			return;
-+		}
-+	}
-+}
-+#endif
-+
-+/*----------------------------------------------------------------------
-+* sl351x_nat_ioctl
-+*----------------------------------------------------------------------*/
-+int sl351x_nat_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-+{
-+	GMAC_INFO_T 		*tp = (GMAC_INFO_T *)dev->priv;
-+	int 				i, j, port_id;
-+    NATCMD_HDR_T		nat_hdr;
-+    NAT_REQ_E			ctrl;
-+	unsigned char		*req_datap;
-+	NAT_IP_ENTRY_T		*ipcfg;
-+	NAT_XPORT_ENTRY_T	*xport_entry;
-+	NAT_WRULE_ENTRY_T	*wrule_entry;
-+	unsigned int		qid;
-+
-+	if (copy_from_user((void *)&nat_hdr, rq->ifr_data, sizeof(nat_hdr)))
-+		return -EFAULT;
-+	req_datap = (unsigned char *)rq->ifr_data + sizeof(nat_hdr);
-+	port_id = tp->port_id;
-+	switch (nat_hdr.cmd) {
-+	case NATSSTATUS:
-+		if (!capable(CAP_NET_ADMIN))
-+			return -EPERM;
-+		if (nat_hdr.len != sizeof(NAT_STATUS_T))
-+			return -EPERM;
-+		if (copy_from_user((void *)&ctrl.status, req_datap, sizeof(ctrl.status)))
-+			return -EFAULT;
-+		if (ctrl.status.enable != 0 && ctrl.status.enable != 1)
-+			return -EPERM;
-+		// sl351x_nat_set_enabled_flag(ctrl.status.enable);
-+		if (nat_cfg.enabled && (ctrl.status.enable == 0))
-+		{
-+			for (i=0; i= CONFIG_NAT_MAX_IP_NUM)
-+			return -E2BIG;
-+		if (copy_from_user((void *)&nat_cfg.ipcfg[port_id].entry[i], req_datap, sizeof(NAT_IPCFG_T)))
-+			return -EFAULT;
-+		nat_cfg.ipcfg[port_id].total++;
-+		break;
-+	case NATDELIP:
-+		if (!capable(CAP_NET_ADMIN))
-+			return -EPERM;
-+		if (nat_hdr.len != sizeof(NAT_IPCFG_T))
-+			return -EPERM;
-+		if (copy_from_user((void *)&ctrl.ipcfg, req_datap, sizeof(ctrl.ipcfg)))
-+			return -EFAULT;
-+		ipcfg = (NAT_IP_ENTRY_T *)&nat_cfg.ipcfg[port_id].entry[0];
-+		for (i=0; iipaddr == ctrl.ipcfg.entry.ipaddr)
-+			{
-+				NAT_IP_ENTRY_T *ipcfg_next;
-+				ipcfg_next = ipcfg + 1;
-+				for (j=i+1; j < nat_cfg.ipcfg[port_id].total; i++, j++)
-+				{
-+					memcpy((void *)ipcfg, (void *)ipcfg_next, sizeof(NAT_IP_ENTRY_T));
-+					ipcfg++;
-+					ipcfg_next++;
-+				}
-+				ipcfg->ipaddr = 0;
-+				ipcfg->netmask = 0;
-+				nat_cfg.ipcfg[port_id].total--;
-+				return 0;
-+			}
-+		}
-+		return -ENOENT;
-+	case NATGETIP:
-+		if (nat_hdr.len != sizeof(NAT_IPCFG_ALL_T))
-+			return -EPERM;
-+		if (copy_to_user(req_datap, (void *)&nat_cfg.ipcfg[port_id], sizeof(NAT_IPCFG_ALL_T)))
-+			return -EFAULT;
-+		break;
-+	case NATAXPORT:
-+		if (!capable(CAP_NET_ADMIN))
-+			return -EPERM;
-+		if (nat_hdr.len != sizeof(NAT_XPORT_T))
-+			return -EPERM;
-+		i = nat_cfg.xport.total;
-+		if (i >= CONFIG_NAT_MAX_XPORT)
-+			return -E2BIG;
-+		if (copy_from_user((void *)&nat_cfg.xport.entry[i], req_datap, sizeof(NAT_XPORT_T)))
-+			return -EFAULT;
-+		nat_cfg.xport.total++;
-+		break;
-+	case NATDXPORT:
-+		if (!capable(CAP_NET_ADMIN))
-+			return -EPERM;
-+		if (nat_hdr.len != sizeof(NAT_XPORT_T))
-+			return -EPERM;
-+		if (copy_from_user((void *)&ctrl.xport, req_datap, sizeof(NAT_XPORT_T)))
-+			return -EFAULT;
-+		xport_entry = (NAT_XPORT_ENTRY_T *)&nat_cfg.xport.entry[0];
-+		for (i=0; i CONFIG_NAT_TXQ_NUM)
-+			return -EPERM;
-+		i = nat_cfg.wrule[qid].total;
-+		if (i >= CONFIG_NAT_MAX_WRULE)
-+			return -E2BIG;
-+		if (copy_from_user((void *)&nat_cfg.wrule[qid].entry[i], req_datap+sizeof(qid), sizeof(NAT_WRULE_T)))
-+			return -EFAULT;
-+		nat_cfg.wrule[qid].total++;
-+		break;
-+	case NATDWRULE:
-+		if (!capable(CAP_NET_ADMIN))
-+			return -EPERM;
-+		if (nat_hdr.len != sizeof(NAT_WRULE_T))
-+			return -EPERM;
-+		if (copy_from_user((void *)&ctrl.wrule, req_datap, sizeof(NAT_WRULE_T)))
-+			return -EFAULT;
-+		qid = ctrl.wrule.qid;
-+		if (qid >= CONFIG_NAT_TXQ_NUM)
-+			return -EPERM;
-+		wrule_entry = (NAT_WRULE_ENTRY_T *)&nat_cfg.wrule[qid].entry[0];
-+		for (i=0; i= CONFIG_NAT_TXQ_NUM)
-+			return -EPERM;
-+		if (copy_to_user(req_datap, (void *)&nat_cfg.wrule[qid], sizeof(NAT_WRULE_ALL_T)))
-+			return -EFAULT;
-+		break;
-+	case NATSDEFQ:
-+		if (!capable(CAP_NET_ADMIN))
-+			return -EPERM;
-+		if (nat_hdr.len != sizeof(NAT_QUEUE_T))
-+			return -EPERM;
-+		if (copy_from_user((void *)&nat_cfg.default_hw_txq, req_datap, sizeof(u32)))
-+			return -EFAULT;
-+		break;
-+	case NATGDEFQ:
-+		if (nat_hdr.len != sizeof(NAT_QUEUE_T))
-+			return -EPERM;
-+		if (copy_to_user(req_datap, (void *)&nat_cfg.default_hw_txq, sizeof(u32)))
-+			return -EFAULT;
-+	case NATRMIPCFG:
-+		nat_cfg.ipcfg[port_id].total = 0;
-+		break;
-+	case NATTESTENTRY:
-+		if (!capable(CAP_NET_ADMIN))
-+			return -EPERM;
-+		if (nat_hdr.len != sizeof(NAT_TESTENTRY_T))
-+			return -EPERM;
-+		if (copy_from_user((void *)&ctrl.init_entry, req_datap, sizeof(ctrl.init_entry)))
-+			return -EFAULT;
-+		if (ctrl.init_entry.init_enable != 0 && ctrl.init_entry.init_enable != 1)
-+			return -EPERM;
-+		nat_cfg.init_enabled = ctrl.init_entry.init_enable;
-+		break;
-+
-+	default:
-+		return -EPERM;
-+	}
-+
-+	return 0;
-+}
-+
-+/*----------------------------------------------------------------------
-+* 	nat_init_test_entry
-+*	Initialize NAT test hash entries
-+*
-+*	SmartBits P1  -----> Lepus GMAC 0 --------------+
-+*													|
-+*													|
-+*             P3  <----- Lepus GMAC 1 -- HW TxQ0 <--+
-+*									  -- HW TxQ1 <--+
-+*									  -- HW TxQ2 <--+
-+*									  -- HW TxQ3 <--+
-+*
-+*	SmartBits P1  <----- Lepus GMAC 0 -- HW TxQ0 <--+
-+*									  -- HW TxQ1 <--+
-+*                                     -- HW TxQ2 <--+
-+*									  -- HW TxQ3 <--+
-+*													|
-+*													|
-+*             P3  -----> Lepus GMAC 1 --------------+
-+*
-+*   LAN GMAC0 <--------------------------------------------> GMAC1 WAN
-+*	192.168.[x].[y]:50 --> 168.95.[x].[y]:80 ---TXQ[y-1]---> 192.168.2.254:200[y] --> 168.95.[x].[y]:80
-+*	192.168.[x].[y]:50 <-- 168.95.[x].[y]:80 <--TXQ[y-1]---- 192.168.2.254:200[y] <-- 168.95.[x].[y]:80
-+*   where:
-+*		[x] : Packet Type
-+*		[y] : Tx Queue, 1 for TxQ0, 2 for TxQ1, 3 for TxQ2, 4 for TxQ3,
-+*
-+*
-+* Packet Type:
-+* 1. TCP Frames <---> TCP Frames
-+*   LAN GMAC0 <--------------------------------> GMAC1 WAN
-+*	192.168.1.1:50 --> 168.95.1.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.1.1:80
-+*	192.168.1.1:50 <-- 168.95.1.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.1.1:80
-+*
-+*	192.168.1.2:50 --> 168.95.1.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.1.2:80
-+*	192.168.1.2:50 <-- 168.95.1.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.1.2:80
-+*
-+*	192.168.1.3:50 --> 168.95.1.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.1.3:80
-+*	192.168.1.3:50 <-- 168.95.1.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.1.3:80
-+*
-+*	192.168.1.4:50 --> 168.95.1.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.1.4:80
-+*	192.168.1.4:50 <-- 168.95.1.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.1.4:80
-+*
-+* 2 TCP Frames <----> PPPoE + TCP Frames
-+*   LAN GMAC0 <--------------------------------> GMAC1 WAN
-+*	192.168.2.1:50 --> 168.95.2.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.2.1:80
-+*	192.168.2.1:50 <-- 168.95.2.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.2.1:80
-+*
-+*	192.168.2.2:50 --> 168.95.2.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.2.2:80
-+*	192.168.2.2:50 <-- 168.95.2.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.2.2:80
-+*
-+*	192.168.2.3:50 --> 168.95.2.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.2.3:80
-+*	192.168.2.3:50 <-- 168.95.2.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.2.3:80
-+*
-+*	192.168.2.4:50 --> 168.95.2.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.2.4:80
-+*	192.168.2.4:50 <-- 168.95.2.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.2.4:80
-+*
-+* 3 TCP Frames <----> VLAN + PPPoE + TCP Frames
-+*   LAN GMAC0 <--------------------------------> GMAC1 WAN
-+*	192.168.3.1:50 --> 168.95.3.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.3.1:80
-+*	192.168.3.1:50 <-- 168.95.3.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.3.1:80
-+*
-+*	192.168.3.2:50 --> 168.95.3.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.3.2:80
-+*	192.168.3.2:50 <-- 168.95.3.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.3.2:80
-+*
-+*	192.168.3.3:50 --> 168.95.3.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.3.3:80
-+*	192.168.3.3:50 <-- 168.95.3.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.3.3:80
-+*
-+*	192.168.3.4:50 --> 168.95.3.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.3.4:80
-+*	192.168.3.4:50 <-- 168.95.3.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.3.4:80
-+*
-+* 4 VLAN-A + TCP Frames <----> VLAN-B + PPPoE + TCP Frames
-+*   LAN GMAC0 <--------------------------------> GMAC1 WAN
-+*	192.168.4.1:50 --> 168.95.4.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.4.1:80
-+*	192.168.4.1:50 <-- 168.95.4.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.4.1:80
-+*
-+*	192.168.4.2:50 --> 168.95.4.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.4.2:80
-+*	192.168.4.2:50 <-- 168.95.4.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.4.2:80
-+*
-+*	192.168.4.3:50 --> 168.95.4.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.4.3:80
-+*	192.168.4.3:50 <-- 168.95.4.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.4.3:80
-+*
-+*	192.168.4.4:50 --> 168.95.4.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.4.4:80
-+*	192.168.4.4:50 <-- 168.95.4.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.4.4:80
-+*
-+*
-+*
-+*----------------------------------------------------------------------*/
-+#ifdef SL351x_NAT_TEST_BY_SMARTBITS
-+#define 	NAT_IPIV(a,b,c,d)			((a<<24)+(b<<16)+(c<<8)+d)
-+#define     NAT_TEST_CLIENT_IP 			NAT_IPIV(192,168,1,1)
-+#define     NAT_TEST_SERVER_IP 			NAT_IPIV(168,95,1,1)
-+#define		NAT_TEST_LAN_IP				NAT_IPIV(192,168,1,254)
-+#define		NAT_TEST_WAN_IP				NAT_IPIV(192,168,2,254)
-+#define     NAT_TEST_MAP_PORT_BASE		2001
-+#define     NAT_TEST_SPORT				50
-+#define     NAT_TEST_DPORT				80
-+#define     NAT_TEST_PROTOCOL			6
-+u8			nat_test_lan_target_da[6]={0x00,0x11,0x22,0x33,0x44,0x55};
-+u8			nat_test_wan_target_da[6]={0x00,0xaa,0xbb,0xcc,0xdd,0xee};
-+u8			nat_test_lan_my_da[6]={0x00,0x11,0x11,0x11,0x11,0x11};
-+u8			nat_test_wan_my_da[6]={0x00,0x22,0x22,0x22,0x22,0x22};
-+static void nat_init_test_entry(void)
-+{
-+	int 				i, j ;
-+	NAT_HASH_ENTRY_T	*hash_entry;
-+	u32					sip, dip;
-+	u32					hash_data[HASH_MAX_DWORDS];
-+	NAT_CFG_T			*cfg;
-+	int					hash_index;
-+
-+	cfg = (NAT_CFG_T *)&nat_cfg;
-+	hash_entry = (NAT_HASH_ENTRY_T *)&hash_data;
-+	hash_entry->key.Ethertype 	= 0;
-+	hash_entry->key.rule_id 	= 0;
-+	hash_entry->key.ip_protocol = IPPROTO_TCP;
-+	hash_entry->key.reserved1 	= 0;
-+	hash_entry->key.reserved2 	= 0;
-+	// hash_entry->key.sip 		= NAT_TEST_CLIENT_IP;
-+	// hash_entry->key.dip 		= NAT_TEST_SERVER_IP;
-+	hash_entry->key.sport 		= htons(NAT_TEST_SPORT);
-+	hash_entry->key.dport 		= htons(NAT_TEST_DPORT);
-+	hash_entry->key.rule_id = cfg->tcp_udp_rule_id;
-+	hash_entry->action.dword = NAT_LAN2WAN_ACTIONS;
-+
-+	sip = NAT_TEST_CLIENT_IP;
-+	dip = NAT_TEST_SERVER_IP;
-+
-+	// Init TCP <------> TCP hash entries
-+	// LAN --> WAN
-+	// (1) TCP --> TCP
-+	// (2) TCP --> PPPoE + TCP
-+	// (3) TCP --> VLAN-B + PPPoE + TCP
-+	// (4) TCP + VLAN-A --> VLAN-B + PPPoE + TCP
-+	memcpy(hash_entry->param.da, nat_test_wan_target_da, 6);
-+	memcpy(hash_entry->param.sa, nat_test_wan_my_da, 6);
-+	hash_entry->key.port_id = cfg->lan_port;
-+	for (i=0; iaction.bits.dest_qid = i+2;
-+		}
-+		else
-+		{
-+			hash_entry->action.bits.dest_qid = i;
-+		}
-+		hash_entry->action.bits.dest_qid += (cfg->wan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
-+		hash_entry->param.Sport = NAT_TEST_MAP_PORT_BASE+i;
-+		hash_entry->param.Dport = NAT_TEST_DPORT;
-+		for (j=0; j<4; j++)
-+		{
-+			hash_entry->key.sip = sip + i + j*0x100;
-+			hash_entry->key.dip = dip + i + j*0x100;
-+			hash_entry->param.Dip = hash_entry->key.dip;
-+			hash_entry->param.Sip = NAT_TEST_WAN_IP;
-+			switch (j)
-+			{
-+			case 0:
-+				hash_entry->action.bits.pppoe = 0;
-+				hash_entry->param.pppoe = 0;
-+				hash_entry->action.bits.vlan = 0;
-+				hash_entry->param.vlan = 0;
-+				break;
-+			case 1:
-+				hash_entry->action.bits.pppoe = 1;
-+				hash_entry->param.pppoe = i+1;
-+				hash_entry->action.bits.vlan = 0;
-+				hash_entry->param.vlan = 0;
-+				break;
-+			case 2:
-+				hash_entry->action.bits.pppoe = 1;
-+				hash_entry->param.pppoe = i+1;
-+				hash_entry->action.bits.vlan = 1;
-+				hash_entry->param.vlan = i+10;
-+				break;
-+			case 3:
-+				hash_entry->action.bits.pppoe = 1;
-+				hash_entry->param.pppoe = i+1;
-+				hash_entry->action.bits.vlan = 1;
-+				hash_entry->param.vlan = i+10;
-+				break;
-+			}
-+			hash_entry->tmo.counter = hash_entry->tmo.interval = 0x7fff;
-+			hash_index = nat_build_keys(&hash_entry->key);
-+			nat_write_hash_entry(hash_index, hash_entry);
-+			hash_nat_enable_owner(hash_index);
-+			hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
-+		}
-+	}
-+
-+
-+	// WAN --> LAN
-+	hash_entry->key.port_id 	= cfg->wan_port;
-+	hash_entry->key.sport 		= htons(NAT_TEST_DPORT);
-+	hash_entry->key.dport 		= htons(NAT_TEST_DPORT);
-+	hash_entry->key.rule_id		= cfg->tcp_udp_rule_id;
-+	hash_entry->action.dword	= NAT_WAN2LAN_ACTIONS;
-+	hash_entry->key.sport		= htons(NAT_TEST_DPORT);
-+	memcpy(hash_entry->param.da, nat_test_lan_target_da, 6);
-+	memcpy(hash_entry->param.sa, nat_test_lan_my_da, 6);
-+	for (i=0; ikey.dport = htons(NAT_TEST_MAP_PORT_BASE + i);
-+		if (i < 2)
-+		{
-+			hash_entry->action.bits.dest_qid = i+2;
-+		}
-+		else
-+		{
-+			hash_entry->action.bits.dest_qid = i;
-+		}
-+		hash_entry->action.bits.dest_qid += (cfg->lan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
-+		hash_entry->param.Dport = NAT_TEST_SPORT;
-+		hash_entry->param.Sport = NAT_TEST_DPORT;
-+		hash_entry->param.da[5] = i;
-+		for (j=0; j<4; j++)
-+		{
-+			hash_entry->key.sip = (dip + i + j*0x100);
-+			hash_entry->key.dip = (NAT_TEST_WAN_IP);
-+			hash_entry->param.Sip = hash_entry->key.sip;
-+			hash_entry->param.Dip = sip + i + j*0x100;
-+			switch (j)
-+			{
-+			case 0:
-+				hash_entry->action.bits.pppoe = 0;
-+				hash_entry->param.pppoe = 0;
-+				hash_entry->action.bits.vlan = 0;
-+				hash_entry->param.vlan = 0;
-+				break;
-+			case 1:
-+				hash_entry->action.bits.pppoe = 2;
-+				hash_entry->param.pppoe = i+1;
-+				hash_entry->action.bits.vlan = 0;
-+				hash_entry->param.vlan = 0;
-+				break;
-+			case 2:
-+				hash_entry->action.bits.pppoe = 2;
-+				hash_entry->param.pppoe = i+1;
-+				hash_entry->action.bits.vlan = 2;
-+				hash_entry->param.vlan = i+5;
-+				break;
-+			case 3:
-+				hash_entry->action.bits.pppoe = 1;
-+				hash_entry->param.pppoe = i+1;
-+				hash_entry->action.bits.vlan = 1;
-+				hash_entry->param.vlan = i+5;
-+				break;
-+			}
-+			hash_entry->tmo.counter = hash_entry->tmo.interval = 0x7fff;
-+			hash_index = nat_build_keys(&hash_entry->key);
-+			nat_write_hash_entry(hash_index, hash_entry);
-+			hash_nat_enable_owner(hash_index);
-+			hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
-+		}
-+	}
-+}
-+#endif	// SL351x_NAT_TEST_BY_SMARTBITS
-+
-+#endif // CONFIG_SL351x_NAT
-+
---- /dev/null
-+++ b/drivers/net/sl351x_proc.c
-@@ -0,0 +1,578 @@
-+/****************************************************************************
-+* Copyright 2006 Storlink Corp.  All rights reserved.
-+*----------------------------------------------------------------------------
-+* Name			: sl351x_proc.c
-+* Description	:
-+*		Handle Proc Routines for Storlink SL351x Platform
-+*
-+* History
-+*
-+*	Date		Writer		Description
-+*----------------------------------------------------------------------------
-+*	04/13/2006	Gary Chen	Create and implement
-+*
-+*
-+****************************************************************************/
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#ifdef CONFIG_NETFILTER
-+// #include 
-+#endif
-+#include 
-+#include 
-+#include 
-+#ifdef CONFIG_SYSCTL
-+#include 
-+#endif
-+
-+#define	 MIDWAY
-+#define	 SL_LEPUS
-+
-+// #define PROC_DEBUG_MSG	1
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#ifdef CONFIG_PROC_FS
-+/*----------------------------------------------------------------------
-+* Definition
-+*----------------------------------------------------------------------*/
-+#define	proc_printf					printk
-+#define SL351x_GMAC_PROC_NAME		"sl351x_gmac"
-+#define SL351x_NAT_PROC_NAME		"sl351x_nat"
-+#define SL351x_TOE_PROC_NAME		"sl351x_toe"
-+
-+/*----------------------------------------------------------------------
-+* Function Definition
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL351x_NAT
-+static int nat_ct_open(struct inode *inode, struct file *file);
-+static void *nat_ct_seq_start(struct seq_file *s, loff_t *pos);
-+static void nat_ct_seq_stop(struct seq_file *s, void *v);
-+static void *nat_ct_seq_next(struct seq_file *s, void *v, loff_t *pos);
-+static int nat_ct_seq_show(struct seq_file *s, void *v);
-+#endif
-+
-+#ifdef CONFIG_SL351x_RXTOE
-+static int toe_ct_open(struct inode *inode, struct file *file);
-+static void *toe_ct_seq_start(struct seq_file *s, loff_t *pos);
-+static void toe_ct_seq_stop(struct seq_file *s, void *v);
-+static void *toe_ct_seq_next(struct seq_file *s, void *v, loff_t *pos);
-+static int toe_ct_seq_show(struct seq_file *s, void *v);
-+extern int sl351x_get_toe_conn_flag(int index);
-+extern struct toe_conn * sl351x_get_toe_conn_info(int index);
-+#endif
-+
-+static int gmac_ct_open(struct inode *inode, struct file *file);
-+static void *gmac_ct_seq_start(struct seq_file *s, loff_t *pos);
-+static void gmac_ct_seq_stop(struct seq_file *s, void *v);
-+static void *gmac_ct_seq_next(struct seq_file *s, void *v, loff_t *pos);
-+static int gmac_ct_seq_show(struct seq_file *s, void *v);
-+
-+
-+/*----------------------------------------------------------------------
-+* Data
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SYSCTL
-+// static struct ctl_table_header *nat_ct_sysctl_header;
-+#endif
-+
-+#ifdef CONFIG_SL351x_NAT
-+static struct seq_operations nat_ct_seq_ops = {
-+	.start = nat_ct_seq_start,
-+	.next  = nat_ct_seq_next,
-+	.stop  = nat_ct_seq_stop,
-+	.show  = nat_ct_seq_show
-+};
-+
-+static struct file_operations nat_file_ops= {
-+	.owner   = THIS_MODULE,
-+	.open    = nat_ct_open,
-+	.read    = seq_read,
-+	.llseek  = seq_lseek,
-+	.release = seq_release
-+};
-+#endif // CONFIG_SL351x_NAT
-+
-+#ifdef CONFIG_SL351x_RXTOE
-+static struct seq_operations toe_ct_seq_ops = {
-+	.start = toe_ct_seq_start,
-+	.next  = toe_ct_seq_next,
-+	.stop  = toe_ct_seq_stop,
-+	.show  = toe_ct_seq_show
-+};
-+
-+static struct file_operations toe_file_ops= {
-+	.owner   = THIS_MODULE,
-+	.open    = toe_ct_open,
-+	.read    = seq_read,
-+	.llseek  = seq_lseek,
-+	.release = seq_release
-+};
-+#endif
-+
-+static struct seq_operations gmac_ct_seq_ops = {
-+	.start = gmac_ct_seq_start,
-+	.next  = gmac_ct_seq_next,
-+	.stop  = gmac_ct_seq_stop,
-+	.show  = gmac_ct_seq_show
-+};
-+
-+static struct file_operations gmac_file_ops= {
-+	.owner   = THIS_MODULE,
-+	.open    = gmac_ct_open,
-+	.read    = seq_read,
-+	.llseek  = seq_lseek,
-+	.release = seq_release
-+};
-+
-+#ifdef SL351x_GMAC_WORKAROUND
-+extern u32 gmac_workaround_cnt[4];
-+extern u32 gmac_short_frame_workaround_cnt[2];
-+#ifdef CONFIG_SL351x_NAT
-+	extern u32 sl351x_nat_workaround_cnt;
-+#endif
-+#endif
-+/*----------------------------------------------------------------------
-+* nat_ct_open
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL351x_NAT
-+static int nat_ct_open(struct inode *inode, struct file *file)
-+{
-+	return seq_open(file, &nat_ct_seq_ops);
-+}
-+#endif // CONFIG_SL351x_NAT
-+/*----------------------------------------------------------------------
-+* nat_ct_seq_start
-+* find the first
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL351x_NAT
-+static void *nat_ct_seq_start(struct seq_file *s, loff_t *pos)
-+{
-+	int i;
-+
-+	// proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
-+	for (i=*pos; iHASH_TOTAL_ENTRIES)
-+		return -ENOSPC;
-+
-+	idx--;
-+	nat_entry = (NAT_HASH_ENTRY_T *)&hash_tables[idx];
-+	gre_entry = (GRE_HASH_ENTRY_T *)nat_entry;
-+	if (nat_entry->key.ip_protocol == IPPROTO_GRE)
-+	{
-+		if (seq_printf(s, "%4d: KEY MAC-%d [%d] %u.%u.%u.%u [%u]-->%u.%u.%u.%u\n",
-+					idx, gre_entry->key.port_id, gre_entry->key.ip_protocol,
-+					HIPQUAD(gre_entry->key.sip), ntohs(gre_entry->key.call_id),
-+					HIPQUAD(gre_entry->key.dip)))
-+			return -ENOSPC;
-+		if (seq_printf(s, "      PARAMETER: %u.%u.%u.%u -->%u.%u.%u.%u [%u] Timeout:%ds\n",
-+					HIPQUAD(gre_entry->param.Sip),
-+					HIPQUAD(gre_entry->param.Dip), gre_entry->param.Dport,
-+					gre_entry->tmo.counter))
-+			return -ENOSPC;
-+	}
-+	else
-+	{
-+		if (seq_printf(s, "%4d: KEY MAC-%d [%d] %u.%u.%u.%u [%u]-->%u.%u.%u.%u [%u]\n",
-+					idx, nat_entry->key.port_id, nat_entry->key.ip_protocol,
-+					HIPQUAD(nat_entry->key.sip), ntohs(nat_entry->key.sport),
-+					HIPQUAD(nat_entry->key.dip), ntohs(nat_entry->key.dport)))
-+			return -ENOSPC;
-+		if (seq_printf(s, "      PARAMETER: %u.%u.%u.%u [%u]-->%u.%u.%u.%u [%u] Timeout:%ds\n",
-+					HIPQUAD(nat_entry->param.Sip), nat_entry->param.Sport,
-+					HIPQUAD(nat_entry->param.Dip), nat_entry->param.Dport,
-+					nat_entry->tmo.counter))
-+			return -ENOSPC;
-+	}
-+	return 0;
-+}
-+#endif // CONFIG_SL351x_NAT
-+
-+/*----------------------------------------------------------------------
-+* toe_ct_open
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL351x_RXTOE
-+static int toe_ct_open(struct inode *inode, struct file *file)
-+{
-+	return seq_open(file, &toe_ct_seq_ops);
-+}
-+#endif
-+/*----------------------------------------------------------------------
-+* toe_ct_seq_start
-+* find the first
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_SL351x_RXTOE
-+static void *toe_ct_seq_start(struct seq_file *s, loff_t *pos)
-+{
-+	int i;
-+
-+	// proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
-+	for (i=*pos; iTOE_TOE_QUEUE_NUM)
-+		return -ENOSPC;
-+
-+	idx--;
-+	toe_entry = (struct toe_conn *)sl351x_get_toe_conn_info(idx);
-+	if (!toe_entry)
-+		return -ENOSPC;
-+
-+	if (seq_printf(s, "%4d: Qid %d MAC-%d TCP %u.%u.%u.%u [%u]-->%u.%u.%u.%u [%u]\n",
-+				idx, toe_entry->qid, toe_entry->gmac->port_id,
-+				NIPQUAD(toe_entry->saddr[0]), ntohs(toe_entry->source),
-+				NIPQUAD(toe_entry->daddr[0]), ntohs(toe_entry->dest)))
-+			return -ENOSPC;
-+	return 0;
-+}
-+#endif
-+/*----------------------------------------------------------------------
-+* gmac_ct_open
-+*----------------------------------------------------------------------*/
-+static int gmac_ct_open(struct inode *inode, struct file *file)
-+{
-+	return seq_open(file, &gmac_ct_seq_ops);
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_ct_seq_start
-+* find the first
-+*----------------------------------------------------------------------*/
-+static void *gmac_ct_seq_start(struct seq_file *s, loff_t *pos)
-+{
-+	int i;
-+	i = (int)*pos + 1;;
-+
-+	if (i > 9)
-+		return NULL;
-+	else
-+		return (void *)i;
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_ct_seq_stop
-+*----------------------------------------------------------------------*/
-+static void gmac_ct_seq_stop(struct seq_file *s, void *v)
-+{
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_ct_seq_next
-+*----------------------------------------------------------------------*/
-+static void *gmac_ct_seq_next(struct seq_file *s, void *v, loff_t *pos)
-+{
-+	int i;
-+
-+	// proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
-+
-+	(*pos)++;
-+	i = (int)*pos + 1;;
-+
-+	if (i > 9)
-+		return NULL;
-+	else
-+		return (void *)i;
-+}
-+
-+/*----------------------------------------------------------------------
-+* seq_dm_long
-+*----------------------------------------------------------------------*/
-+static void seq_dm_long(struct seq_file *s, u32 location, int length)
-+{
-+	u32		*start_p, *curr_p, *end_p;
-+	u32		*datap, data;
-+	int		i;
-+
-+	//if (length > 1024)
-+	//	length = 1024;
-+
-+	start_p = (u32 *)location;
-+	end_p = (u32 *)location + length;
-+	curr_p = (u32 *)((u32)location & 0xfffffff0);
-+	datap = (u32 *)location;
-+	while (curr_p < end_p)
-+	{
-+		cond_resched();
-+		seq_printf(s, "0x%08x: ",(u32)curr_p & 0xfffffff0);
-+		for (i=0; i<4; i++)
-+		{
-+			if (curr_p < start_p || curr_p >= end_p)
-+               seq_printf(s, "         ");
-+			else
-+			{
-+				data = *datap;
-+				seq_printf(s, "%08X ", data);
-+			}
-+			if (i==1)
-+              seq_printf(s, "- ");
-+
-+			curr_p++;
-+			datap++;
-+		}
-+        seq_printf(s, "\n");
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* gmac_ct_seq_show
-+*----------------------------------------------------------------------*/
-+static int gmac_ct_seq_show(struct seq_file *s, void *v)
-+{
-+	switch ((int)v)
-+	{
-+		case 1:
-+			seq_printf(s, "\nGMAC Global Registers\n");
-+			seq_dm_long(s, TOE_GLOBAL_BASE, 32);
-+			break;
-+		case 2:
-+			seq_printf(s, "\nGMAC Non-TOE Queue Header\n");
-+			seq_dm_long(s, TOE_NONTOE_QUE_HDR_BASE, 12);
-+			break;
-+		case 3:
-+			seq_printf(s, "\nGMAC TOE Queue Header\n");
-+			seq_dm_long(s, TOE_TOE_QUE_HDR_BASE, 12);
-+			break;
-+		case 4:
-+			seq_printf(s, "\nGMAC-0 DMA Registers\n");
-+			seq_dm_long(s, TOE_GMAC0_DMA_BASE, 52);
-+			break;
-+		case 5:
-+			seq_printf(s, "\nGMAC-0 Registers\n");
-+			seq_dm_long(s, TOE_GMAC0_BASE, 32);
-+			break;
-+		case 6:
-+			seq_printf(s, "\nGMAC-1 DMA Registers\n");
-+			seq_dm_long(s, TOE_GMAC1_DMA_BASE, 52);
-+			break;
-+		case 7:
-+			seq_printf(s, "\nGMAC-1 Registers\n");
-+			seq_dm_long(s, TOE_GMAC1_BASE, 32);
-+			break;
-+		case 8:
-+			seq_printf(s, "\nGLOBAL Registers\n");
-+			seq_dm_long(s, GMAC_GLOBAL_BASE_ADDR, 16);
-+			break;
-+		case 9:
-+#ifdef SL351x_GMAC_WORKAROUND
-+			seq_printf(s, "\nGMAC-0 Rx/Tx/Short Workaround: %u, %u, %u\n", gmac_workaround_cnt[0], gmac_workaround_cnt[1], gmac_short_frame_workaround_cnt[0]);
-+			seq_printf(s, "GMAC-1 Rx/Tx/Short Workaround: %u, %u, %u\n", gmac_workaround_cnt[2], gmac_workaround_cnt[3], gmac_short_frame_workaround_cnt[1]);
-+#ifdef CONFIG_SL351x_NAT
-+			seq_printf(s, "NAT Workaround: %u\n", sl351x_nat_workaround_cnt);
-+#endif
-+#endif
-+			break;
-+		default:
-+			return -ENOSPC;
-+	}
-+	return 0;
-+}
-+
-+/*----------------------------------------------------------------------
-+* init
-+*----------------------------------------------------------------------*/
-+static int __init init(void)
-+{
-+	struct proc_dir_entry *proc_gmac=NULL;
-+
-+#ifdef CONFIG_SL351x_NAT
-+	struct proc_dir_entry *proc_nat=NULL;
-+#endif
-+
-+#ifdef CONFIG_SL351x_RXTOE
-+	struct proc_dir_entry *proc_toe=NULL;
-+#endif
-+
-+#ifdef CONFIG_SYSCTL
-+	// nat_ct_sysctl_header = NULL;
-+#endif
-+	proc_gmac = proc_net_fops_create(SL351x_GMAC_PROC_NAME, 0440, &gmac_file_ops);
-+	if (!proc_gmac) goto init_bad;
-+
-+#ifdef CONFIG_SL351x_NAT
-+	proc_nat = proc_net_fops_create(SL351x_NAT_PROC_NAME, 0440, &nat_file_ops);
-+	if (!proc_nat) goto init_bad;
-+#endif // CONFIG_SL351x_NAT
-+
-+#ifdef CONFIG_SL351x_RXTOE
-+	proc_toe = proc_net_fops_create(SL351x_TOE_PROC_NAME, 0440, &toe_file_ops);
-+	if (!proc_toe) goto init_bad;
-+#endif
-+
-+#ifdef CONFIG_SYSCTL
-+	// nat_ct_sysctl_header = register_sysctl_table(nat_ct_net_table, 0);
-+	// if (!nat_ct_sysctl_header) goto init_bad;
-+#endif
-+
-+	return 0;
-+
-+init_bad:
-+	if (proc_gmac) proc_net_remove(SL351x_GMAC_PROC_NAME);
-+
-+#ifdef CONFIG_SL351x_NAT
-+	if (proc_nat) proc_net_remove(SL351x_NAT_PROC_NAME);
-+#endif
-+
-+#ifdef CONFIG_SL351x_RXTOE
-+	if (proc_toe) proc_net_remove(SL351x_NAT_PROC_NAME);
-+#endif
-+
-+#ifdef CONFIG_SYSCTL
-+	// if (nat_ct_sysctl_header) unregister_sysctl_table(nat_ct_sysctl_header);
-+#endif
-+	proc_printf("SL351x NAT Proc: can't create proc or register sysctl.\n");
-+	return -ENOMEM;
-+}
-+
-+/*----------------------------------------------------------------------
-+* fini
-+*----------------------------------------------------------------------*/
-+static void __exit fini(void)
-+{
-+	proc_net_remove(SL351x_GMAC_PROC_NAME);
-+
-+#ifdef CONFIG_SL351x_NAT
-+	proc_net_remove(SL351x_NAT_PROC_NAME);
-+#endif
-+
-+#ifdef CONFIG_SL351x_RXTOE
-+	proc_net_remove(SL351x_TOE_PROC_NAME);
-+#endif
-+
-+#ifdef CONFIG_SYSCTL
-+	// unregister_sysctl_table(nat_ct_sysctl_header);
-+#endif
-+}
-+
-+/*----------------------------------------------------------------------
-+* module
-+*----------------------------------------------------------------------*/
-+module_init(init);
-+module_exit(fini);
-+
-+#endif	// CONFIG_PROC_FS
---- /dev/null
-+++ b/drivers/net/sl351x_toe.c
-@@ -0,0 +1,1083 @@
-+/**************************************************************************
-+* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
-+*--------------------------------------------------------------------------
-+* Name			: sl351x_toe.c
-+* Description	:
-+*		Provide TOE routines for SL351x
-+*
-+* History
-+*
-+*	Date		Writer		Description
-+*----------------------------------------------------------------------------
-+*				Xiaochong
-+*
-+****************************************************************************/
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+static int in_toe_isr;
-+static int toe_initialized=0;
-+
-+static struct toe_conn	toe_connections[TOE_TOE_QUEUE_NUM];
-+EXPORT_SYMBOL(toe_connections);
-+static __u32 toe_connection_bits[TOE_TOE_QUEUE_NUM/32] __attribute__ ((aligned(16)));
-+struct sk_buff* gen_pure_ack(struct toe_conn* connection, TOE_QHDR_T* toe_qhdr, INTR_QHDR_T *intr_curr_desc);
-+
-+extern struct storlink_sysctl	storlink_ctl;
-+extern TOE_INFO_T toe_private_data;
-+extern spinlock_t gmac_fq_lock;
-+extern void mac_write_dma_reg(int mac, unsigned int offset, u32 data);
-+extern int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2);
-+extern int hash_add_toe_entry(HASH_ENTRY_T *entry);
-+extern void toe_gmac_fill_free_q(void);
-+
-+#define _DEBUG_SKB_		1
-+#ifdef _DEBUG_SKB_
-+/*---------------------------------------------------------------------------
-+ * _debug_skb
-+ *-------------------------------------------------------------------------*/
-+static inline void _debug_skb(struct sk_buff *skb, GMAC_RXDESC_T *toe_curr_desc, u32 data)
-+{
-+	if ((u32)skb < 0x1000)
-+	{
-+		printk("%s skb=%x\n", __func__, (u32)skb);
-+		while(1);
-+	}
-+	REG32(__va(toe_curr_desc->word2.buf_adr)-SKB_RESERVE_BYTES) = data;
-+}
-+#else
-+#define _debug_skb(x, y, z)
-+#endif
-+
-+/*---------------------------------------------------------------------------
-+ * get_connection_seq_num
-+ *-------------------------------------------------------------------------*/
-+u32 get_connection_seq_num(unsigned short qid)
-+{
-+	TOE_QHDR_T	*toe_qhdr;
-+
-+	toe_qhdr = (TOE_QHDR_T*)TOE_TOE_QUE_HDR_BASE;
-+	toe_qhdr += qid;
-+	return (u32)toe_qhdr->word3.seq_num;
-+}
-+EXPORT_SYMBOL(get_connection_seq_num);
-+
-+/*---------------------------------------------------------------------------
-+ * get_connection_ack_num
-+ *-------------------------------------------------------------------------*/
-+u32 get_connection_ack_num(unsigned short qid)
-+{
-+	TOE_QHDR_T	*toe_qhdr;
-+
-+	toe_qhdr = (TOE_QHDR_T*)TOE_TOE_QUE_HDR_BASE;
-+	toe_qhdr += qid;
-+	return (u32)toe_qhdr->word4.ack_num;
-+}
-+EXPORT_SYMBOL(get_connection_ack_num);
-+
-+/*---------------------------------------------------------------------------
-+ * dump_toe_qhdr
-+ *-------------------------------------------------------------------------*/
-+void dump_toe_qhdr(TOE_QHDR_T *toe_qhdr)
-+{
-+	printk("TOE w1 %x, w2 %x, w3 %x\n", toe_qhdr->word1.bits32,
-+		toe_qhdr->word2.bits32, toe_qhdr->word3.bits32);
-+	printk("w4 %x, w5 %x, w6 %x\n", toe_qhdr->word4.bits32,
-+		toe_qhdr->word5.bits32, toe_qhdr->word6.bits32);
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * dump_intrq_desc
-+ *-------------------------------------------------------------------------*/
-+void dump_intrq_desc(INTR_QHDR_T *intr_curr_desc)
-+{
-+	printk("INTR w0 %x, w1 %x, seq %x\n", intr_curr_desc->word0.bits32,
-+		intr_curr_desc->word1.bits32, intr_curr_desc->word2.bits32);
-+	printk("ack %x, w4 %x\n", intr_curr_desc->word3.bits32,
-+		intr_curr_desc->word4.bits32);
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * This routine will initialize a TOE matching rule
-+ * called by SL351x GMAC driver.
-+ *-------------------------------------------------------------------------*/
-+void sl351x_toe_init(void)
-+{
-+	GMAC_MRxCR0_T	mrxcr0;
-+	GMAC_MRxCR1_T	mrxcr1;
-+	GMAC_MRxCR2_T	mrxcr2;
-+	int	rule, rc;
-+
-+	if (toe_initialized)
-+		return;
-+
-+	toe_initialized = 1;
-+
-+#ifndef CONFIG_SL351x_NAT
-+	mrxcr0.bits32 = 0;
-+	mrxcr1.bits32 = 0;
-+	mrxcr2.bits32 = 0;
-+	mrxcr0.bits.l3 = 1;
-+	mrxcr0.bits.l4 = 1;
-+	mrxcr1.bits.sip = 1;
-+	mrxcr1.bits.dip = 1;
-+	mrxcr1.bits.l4_byte0_15 = 0x0f;
-+	mrxcr0.bits.sprx = 1;
-+	rule = 0;
-+	rc = mac_set_rule_reg(0, rule, 1, mrxcr0.bits32, mrxcr1.bits32,
-+						mrxcr2.bits32);
-+	if (rc<0) {
-+		printk("%s::Set MAC 0 rule fail!\n", __func__);
-+	}
-+	rc = mac_set_rule_reg(1, rule, 1, mrxcr0.bits32, mrxcr1.bits32,
-+	     					mrxcr2.bits32);
-+	if (rc<0) {
-+		printk("%s::Set MAC 1 rule fail!\n", __func__);
-+	}
-+#endif // CONFIG_SL351x_NAT
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * dump_intrq_desc
-+ * assign an interrupt queue number to a give tcp queue
-+ *-------------------------------------------------------------------------*/
-+int get_interrupt_queue_id(int tcp_qid)
-+{
-+	return (int)(tcp_qid & 0x0003);
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * reset_connection_index
-+ * reset the connection bit by given index
-+ *-------------------------------------------------------------------------*/
-+void reset_connection_index(__u8 index)
-+{
-+	__u32 mask = ~(0xffffffff & (1<< (index&0x1f)));
-+	toe_connection_bits[index>>5] = toe_connection_bits[index>>5] & mask;
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * update_timer
-+ *-------------------------------------------------------------------------*/
-+void update_timer(struct toe_conn* connection)
-+{
-+//	if (time_before(jiffies, connection->last_rx_jiffies+3))
-+//	if ((jiffies + 0xffffffff - connection->last_rx_jiffies) & 0x3)
-+//	if (connection->last_rx_jiffies > jiffies)
-+//		printk("%s::jif %g, last_rx_jif %g\n", __func__, jiffies, connection->last_rx_jiffies);
-+/*	if ((long)(jiffies + 2)< 3) { // overflow...
-+		printk("%s::jiffies %x\n", __func__, jiffies);
-+	} */
-+//	if ((long)(jiffies - connection->last_rx_jiffies)< 2)
-+//		return;
-+	connection->last_rx_jiffies = jiffies;
-+	// gary chen mod_timer(&connection->rx_timer, jiffies+2);
-+	connection->rx_timer.expires = jiffies + 2;
-+	add_timer(&connection->rx_timer);
-+//	printk("%s::nt %x, lj %x\n", __func__, (jiffies+2), connection->last_rx_jiffies);
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * gen_pure_ack
-+ *-------------------------------------------------------------------------*/
-+struct sk_buff* gen_pure_ack(struct toe_conn* connection, TOE_QHDR_T* toe_qhdr,
-+INTR_QHDR_T *intr_curr_desc)
-+{
-+	struct sk_buff	*skb;
-+	struct iphdr	*ip_hdr;
-+	struct tcphdr	*tcp_hdr;
-+	struct ethhdr	*eth_hdr;
-+
-+	if ((skb= dev_alloc_skb(RX_BUF_SIZE))==NULL) {
-+		printk("%s::alloc pure ack fail!\n", __func__);
-+		return NULL;
-+	}
-+	skb_reserve(skb, RX_INSERT_BYTES);
-+	memset(skb->data, 0, 60);
-+
-+	eth_hdr = (struct ethhdr*)&(skb->data[0]);
-+	memcpy(eth_hdr, &connection->l2_hdr, sizeof(struct ethhdr));
-+
-+	ip_hdr = (struct iphdr*)&(skb->data[14]);
-+	ip_hdr->version = connection->ip_ver;
-+	ip_hdr->ihl = 20>>2;
-+	ip_hdr->tot_len = ntohs(40);
-+	ip_hdr->frag_off = htons(IP_DF);
-+	ip_hdr->ttl = 128;
-+	ip_hdr->protocol = 0x06;
-+	ip_hdr->saddr = connection->saddr[0];
-+	ip_hdr->daddr = connection->daddr[0];
-+//	printk("%s ip sa %x, da %x\n",
-+//		__func__, ntohl(ip_hdr->saddr), ntohl(ip_hdr->daddr));
-+
-+	tcp_hdr = (struct tcphdr*)&(skb->data[34]);
-+	tcp_hdr->source = connection->source;
-+	tcp_hdr->dest = connection->dest;
-+	if (intr_curr_desc) {
-+		tcp_hdr->seq = htonl(intr_curr_desc->word2.seq_num);
-+		tcp_hdr->ack_seq = htonl(intr_curr_desc->word3.ack_num);
-+		tcp_hdr->window = htons(intr_curr_desc->word0.bits.win_size);
-+	} else {
-+		tcp_hdr->seq = htonl(toe_qhdr->word3.seq_num);
-+		tcp_hdr->ack_seq = htonl(toe_qhdr->word4.ack_num);
-+		tcp_hdr->window = htons(toe_qhdr->word6.bits.WinSize);
-+	}
-+	tcp_hdr->ack = 1;
-+	tcp_hdr->doff = 20 >> 2;
-+#if 0
-+	if (!intr_curr_desc) {
-+		unsigned char byte;
-+		for (i=0; i<20; i++) {
-+			byte = skb->data[34+i];
-+			printk("%x ", byte);
-+		}
-+		printk("\n");
-+	}
-+#endif
-+	TCP_SKB_CB(skb)->connection = connection;
-+	return skb;
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * connection_rx_timer
-+ *-------------------------------------------------------------------------*/
-+void connection_rx_timer(unsigned long *data)
-+{
-+	struct toe_conn	*connection = (struct toe_conn*)data;
-+	unsigned int	tcp_qid, toeq_wptr;
-+	unsigned int	pkt_size, desc_count;
-+	struct sk_buff	*skb;
-+	GMAC_RXDESC_T	*toe_curr_desc;
-+	TOE_QHDR_T	*toe_qhdr;
-+	struct net_device	*dev;
-+	unsigned long	conn_flags;
-+	DMA_RWPTR_T		toeq_rwptr;
-+	unsigned short	timeout_descs;
-+
-+	if (in_toe_isr)
-+		printk("%s::in_toe_isr=%d!\n", __func__, in_toe_isr);
-+
-+	if (connection) {
-+		/* should we disable gmac interrupt first? */
-+		if (!connection->gmac)
-+			printk("%s::conn gmac %x!\n", __func__, (u32)connection->gmac);
-+		local_irq_save(conn_flags);
-+		if (!spin_trylock(&connection->conn_lock)) {
-+			local_irq_restore(conn_flags);
-+			// timer should be updated by the toeq isr. So no need to update here.
-+			printk("%s::conn_lock is held by ISR!\n", __func__);
-+			return;
-+		}
-+		disable_irq(connection->gmac->irq);
-+
-+		/* disable hash entry and get toeq desc. */
-+		hash_set_valid_flag(connection->hash_entry_index, 0);
-+		do{} while(0);	/* wait until HW finish */
-+
-+		dev = connection->dev;
-+		if (!dev)
-+			printk("%s::conn dev NULL!\n", __func__);
-+		tcp_qid = connection->qid;
-+		toe_qhdr = (TOE_QHDR_T *)(TOE_TOE_QUE_HDR_BASE +
-+		              tcp_qid * sizeof(TOE_QHDR_T));
-+		toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
-+		toeq_wptr = toe_qhdr->word1.bits.wptr;
-+		timeout_descs = toeq_wptr - toeq_rwptr.bits.rptr;
-+
-+		if (toeq_rwptr.bits.rptr == toeq_wptr) {
-+			if (toe_qhdr->word5.bits32) {
-+				// shall we check toe_qhdr->word2.bits?
-+				skb = gen_pure_ack(connection, toe_qhdr, (INTR_QHDR_T *)NULL);
-+				skb_put(skb, 54);
-+				skb->dev = connection->dev;
-+				skb->ip_summed = CHECKSUM_UNNECESSARY;
-+				skb->protocol = eth_type_trans(skb, connection->dev);
-+				netif_rx(skb);
-+				connection->dev->last_rx = jiffies;
-+			}
-+		} else {
-+			while (toeq_rwptr.bits.rptr != toeq_rwptr.bits.wptr) {
-+				/* we just simply send those packets to tcp? */
-+				toe_curr_desc = (GMAC_RXDESC_T*)(toe_private_data.toe_desc_base[tcp_qid]
-+					+ toeq_rwptr.bits.rptr * sizeof(GMAC_RXDESC_T));
-+				connection->curr_desc = toe_curr_desc;
-+				if (toe_curr_desc->word3.bits.ctrl_flag) {
-+					printk("%s::ctrl flag! %x, conn rptr %d, to %d, jif %x, conn_jif %x\n",
-+						__func__, toe_curr_desc->word3.bits32,
-+						connection->toeq_rwptr.bits.rptr, timeout_descs,
-+						(u32)jiffies, (u32)connection->last_rx_jiffies);
-+				}
-+				desc_count = toe_curr_desc->word0.bits.desc_count;
-+				pkt_size = toe_curr_desc->word1.bits.byte_count;
-+				consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
-+					PCI_DMA_FROMDEVICE);
-+				skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr)-
-+					SKB_RESERVE_BYTES));
-+				_debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x02);
-+				connection->curr_rx_skb = skb;
-+				skb_reserve(skb, RX_INSERT_BYTES);
-+				skb_put(skb, pkt_size);
-+				skb->dev = dev;
-+				skb->protocol = eth_type_trans(skb, dev);
-+				{
-+					struct iphdr* ip_hdr = (struct iphdr*)&(skb->data[0]);
-+					if (toe_curr_desc->word3.bits.ctrl_flag)
-+						printk("%s::ip id %x\n", __func__, ntohs(ip_hdr->id));
-+				}
-+				skb->ip_summed = CHECKSUM_UNNECESSARY;
-+
-+				netif_rx(skb);
-+				dev->last_rx = jiffies;
-+#if 0
-+				if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
-+					printk("%s::alloc buf fail!\n", __func__);
-+				}
-+				*(unsigned int*)(skb->data) = (unsigned int)skb;
-+				connection->curr_rx_skb = skb;
-+				skb_reserve(skb, SKB_RESERVE_BYTES);
-+				spin_lock_irqsave(&connection->gmac->rx_mutex, flags);
-+				fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+				if (toe_private_data.fq_rx_rwptr.bits.wptr != fq_rwptr.bits.wptr) {
-+					mac_stop_txdma((struct net_device*)connection->dev);
-+					spin_unlock_irqrestore(&connection->gmac->rx_mutex, flags);
-+					while(1);
-+				}
-+				fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base + fq_rwptr.bits.wptr;
-+				fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
-+				fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
-+				SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
-+				toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
-+				spin_unlock_irqrestore(&connection->gmac->rx_mutex, flags);
-+#endif
-+//				spin_lock_irqsave(&connection->gmac->rx_mutex, flags);
-+				toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
-+				SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
-+//				spin_unlock_irqrestore(&connection->gmac->rx_mutex, flags);
-+				connection->toeq_rwptr.bits32 = toeq_rwptr.bits32;
-+			}
-+			toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
-+//			toe_gmac_fill_free_q();
-+		}
-+		connection->last_rx_jiffies = jiffies;
-+		if (connection->status != TCP_CONN_CLOSED)
-+			mod_timer(&connection->rx_timer, jiffies+2);
-+		if (connection->status != TCP_CONN_ESTABLISHED)
-+			printk("%s::conn status %x\n", __func__, connection->status);
-+		hash_set_valid_flag(connection->hash_entry_index, 1);
-+		enable_irq(connection->gmac->irq);
-+		// Gary Chen spin_unlock_irqrestore(&connection->conn_lock, conn_flags);
-+	}
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * free_toeq_descs
-+ *-------------------------------------------------------------------------*/
-+void free_toeq_descs(int qid, TOE_INFO_T *toe)
-+{
-+	void	*desc_ptr;
-+
-+	desc_ptr = (void*)toe->toe_desc_base[qid];
-+	pci_free_consistent(NULL, TOE_TOE_DESC_NUM*sizeof(GMAC_RXDESC_T), desc_ptr,
-+	   (dma_addr_t)toe->toe_desc_base_dma[qid]);
-+	toe->toe_desc_base[qid] = 0;
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * set_toeq_hdr
-+ *-------------------------------------------------------------------------*/
-+void set_toeq_hdr(struct toe_conn*	connection, TOE_INFO_T* toe, struct net_device *dev)
-+{
-+	volatile TOE_QHDR_T	*toe_qhdr;
-+	volatile unsigned int	toeq_wptr; // toeq_rptr
-+	volatile GMAC_RXDESC_T	*toe_curr_desc;
-+	struct sk_buff	*skb;
-+	unsigned int	pkt_size;
-+	DMA_RWPTR_T	toeq_rwptr;
-+
-+	if (connection->status == TCP_CONN_CLOSING) {
-+		connection->status = TCP_CONN_CLOSED;
-+		hash_set_valid_flag(connection->hash_entry_index, 0);
-+		// remove timer first.
-+		// del_timer_sync(&(connection->rx_timer));
-+		// check if any queued frames last time.
-+		toe_qhdr = (volatile TOE_QHDR_T*)TOE_TOE_QUE_HDR_BASE;
-+		toe_qhdr += connection->qid;
-+		toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
-+
-+		//toeq_rptr = toe_qhdr->word1.bits.rptr;
-+		toeq_wptr = toe_qhdr->word1.bits.wptr;
-+		while (toeq_rwptr.bits.rptr != toeq_wptr) {
-+			printk("%s::pending frames in TOE Queue before closing!\n", __func__);
-+			toe_curr_desc = (GMAC_RXDESC_T*)(toe->toe_desc_base[connection->qid] +
-+				toe_qhdr->word1.bits.rptr*sizeof(GMAC_RXDESC_T));
-+			connection->curr_desc = (GMAC_RXDESC_T *)toe_curr_desc;
-+			pkt_size = toe_curr_desc->word1.bits.byte_count;
-+			consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
-+				PCI_DMA_FROMDEVICE);
-+			skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr) -
-+				SKB_RESERVE_BYTES));
-+			_debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x03);
-+			connection->curr_rx_skb = skb;
-+			skb_reserve(skb, RX_INSERT_BYTES);
-+			skb_put(skb, pkt_size);
-+			skb->dev = connection->dev;
-+			skb->protocol = eth_type_trans(skb, connection->dev);
-+			skb->ip_summed = CHECKSUM_UNNECESSARY;
-+			netif_rx(skb);
-+			connection->dev->last_rx = jiffies;
-+
-+			toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
-+			SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
-+		}
-+		free_toeq_descs(connection->qid, toe);
-+		// shall we re-fill free queue?
-+
-+		reset_connection_index(connection->qid);
-+		//memset(connection, 0, sizeof(struct toe_conn));
-+		printk(" del timer and close connection %x, qid %d\n", (u32)connection, connection->qid);
-+		return;
-+	}
-+	/* enable or setup toe queue header */
-+	if (connection->status == TCP_CONN_CONNECTING && storlink_ctl.rx_max_pktsize) {
-+		volatile TOE_QHDR_T	*qhdr;
-+		int iq_id;
-+		connection->status = TCP_CONN_ESTABLISHED;
-+		qhdr = (volatile TOE_QHDR_T*)((unsigned int)TOE_TOE_QUE_HDR_BASE +
-+		               connection->qid * sizeof(TOE_QHDR_T));
-+
-+		iq_id = get_interrupt_queue_id(connection->qid);
-+		connection->dev = dev;
-+		connection->gmac = dev->priv;
-+		connection->toeq_rwptr.bits32 = 0;
-+
-+//		qhdr->word6.bits.iq_num = iq_id;
-+		qhdr->word6.bits.MaxPktSize = (connection->max_pktsize)>>2; // in word.
-+		qhdr->word7.bits.AckThreshold = connection->ack_threshold;
-+		qhdr->word7.bits.SeqThreshold = connection->seq_threshold;
-+
-+		// init timer.
-+#if 1
-+		init_timer(&connection->rx_timer);
-+		connection->rx_timer.expires = jiffies + 5;
-+		connection->rx_timer.data = (unsigned long)connection;
-+		connection->rx_timer.function = (void *)&connection_rx_timer;
-+		add_timer(&connection->rx_timer);
-+		connection->last_rx_jiffies = jiffies;
-+		printk("init_timer %x\n", (u32)jiffies);
-+#endif
-+		hash_set_valid_flag(connection->hash_entry_index, 1);
-+		return;
-+	} else {
-+		printk("%s::conn status %x, rx_pktsize %d\n",
-+			__func__, connection->status, storlink_ctl.rx_max_pktsize);
-+	}
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * get_connection_index
-+ * get_connection_index will find an available index for the connection,
-+ * when allocate a new connection is needed.
-+ * we find available Qid from AV bits and write to hash_table, so that when RxTOE
-+ * packet is received, sw_id from ToeQ descriptor is also the Qid of conneciton Q.
-+ *-------------------------------------------------------------------------*/
-+int get_connection_index(void)
-+{
-+	int i=0, j=0, index=-1;
-+	__u32	connection_bits;
-+
-+	for (i = 0; i< TOE_TOE_QUEUE_NUM/32; i++) {
-+		connection_bits = ~(toe_connection_bits[i]);
-+		if (connection_bits == 0)
-+			// all 32 bits are used.
-+			continue;
-+
-+		for (j=0; j<32; j++) {
-+			if (connection_bits & 0x01) {
-+				index = i*32 + j;
-+				return index;
-+			}
-+			connection_bits = connection_bits >> 1;
-+		}
-+	}
-+	return index;
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * set_toe_connection
-+ *-------------------------------------------------------------------------*/
-+void set_toe_connection(int index, int val)
-+{
-+	if (val) {
-+		toe_connection_bits[index/32] |= (1<<(index%32));
-+	} else {
-+		toe_connection_bits[index/32] &= (~(1<<(index%32)));
-+	}
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * sl351x_get_toe_conn_flag
-+ *-------------------------------------------------------------------------*/
-+int sl351x_get_toe_conn_flag(int index)
-+{
-+	if (index < TOE_TOE_QUEUE_NUM)
-+		return (toe_connection_bits[index/32] & (1 << (index %32)));
-+	else
-+		return 0;
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * sl351x_get_toe_conn_info
-+ *-------------------------------------------------------------------------*/
-+struct toe_conn * sl351x_get_toe_conn_info(int index)
-+{
-+	if (index < TOE_TOE_QUEUE_NUM)
-+		return (struct toe_conn *)&toe_connections[index];
-+	else
-+		return NULL;
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * create_sw_toe_connection
-+ *-------------------------------------------------------------------------*/
-+struct toe_conn* create_sw_toe_connection(int qid, int ip_ver, void* ip_hdr,
-+	struct tcphdr* tcp_hdr)
-+{
-+	struct toe_conn*	connection =  &(toe_connections[qid]);
-+
-+	connection->ip_ver = (__u8)ip_ver;
-+	connection->qid = (__u8)qid;
-+	connection->source = (__u16)tcp_hdr->source;
-+	connection->dest = (__u16)tcp_hdr->dest;
-+	if (ip_ver == 4) {
-+		struct iphdr* iph = (struct iphdr*) ip_hdr;
-+		connection->saddr[0] = (__u32)iph->saddr;
-+		connection->daddr[0] = (__u32)iph->daddr;
-+//		printk("%s::saddr %x, daddr %x\n", __func__,
-+//			ntohl(connection->saddr[0]), ntohl(connection->daddr[0]));
-+	} else if (ip_ver == 6) {
-+		struct ipv6hdr *iph = (struct ipv6hdr*)ip_hdr;
-+		int i=0;
-+		for (i=0; i<4; i++) {
-+			connection->saddr[i] = (__u32)iph->saddr.in6_u.u6_addr32[i];
-+			connection->daddr[i] = (__u32)iph->daddr.in6_u.u6_addr32[i];
-+		}
-+	}
-+	connection->status = TCP_CONN_CREATION;
-+	return connection;
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * fill_toeq_buf
-+ *-------------------------------------------------------------------------*/
-+int fill_toeq_buf(int index, TOE_INFO_T* toe)
-+{
-+	volatile TOE_QHDR_T	*qhdr;
-+	//struct toe_conn* connection;
-+	GMAC_RXDESC_T	*desc_ptr;
-+
-+	if (!toe->toe_desc_base[index]) {
-+		// first time. init.
-+		desc_ptr = (GMAC_RXDESC_T*)(pci_alloc_consistent(NULL, TOE_TOE_DESC_NUM
-+		            *sizeof(GMAC_RXDESC_T), (dma_addr_t*)&toe->toe_desc_base_dma[index]));
-+
-+		toe->toe_desc_num = TOE_TOE_DESC_NUM;
-+		toe->toe_desc_base[index] = (unsigned int)desc_ptr;
-+	}
-+	qhdr = (volatile TOE_QHDR_T*)((unsigned int)TOE_TOE_QUE_HDR_BASE +
-+									index*sizeof(TOE_QHDR_T));
-+	//connection = (struct toe_conn*)&(toe_connections[index]);
-+
-+	qhdr->word0.base_size = ((unsigned int)toe->toe_desc_base_dma[index]&TOE_QHDR0_BASE_MASK)
-+					| TOE_TOE_DESC_POWER;
-+	qhdr->word1.bits32 = 0;
-+	qhdr->word2.bits32 = 0;
-+	qhdr->word3.bits32 = 0;
-+	qhdr->word4.bits32 = 0;
-+	qhdr->word5.bits32 = 0;
-+	return 1;
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * create_toe_hash_entry_smb
-+ * add SMB header in hash entry.
-+ *-------------------------------------------------------------------------*/
-+int create_toe_hash_entry_smb(int ip_ver, void* ip_hdr, struct tcphdr* tcp_hdr,
-+	int sw_id)
-+{
-+	HASH_ENTRY_T	hash_entry, *entry;
-+	int	hash_entry_index;
-+	int i;
-+
-+	entry = (HASH_ENTRY_T*)&hash_entry;
-+	memset((void*)entry, 0, sizeof(HASH_ENTRY_T));
-+	entry->rule = 0;
-+
-+	/* enable fields of hash key */
-+	entry->key_present.ip_protocol = 1;
-+	entry->key_present.sip = 1;
-+	entry->key_present.dip = 1;
-+	entry->key_present.l4_bytes_0_3 = 1;	// src port and dest port
-+	entry->key_present.l7_bytes_0_3 = 0;	// do we need to enable NETBIOS? how?
-+	entry->key_present.l7_bytes_4_7 = 1;	// "SMB" header
-+
-+	/* hash key */
-+	entry->key.ip_protocol = IPPROTO_TCP;
-+	if (ip_ver == 4) {
-+		struct iphdr *iph = (struct iphdr*)ip_hdr;
-+		memcpy(entry->key.sip, &iph->saddr, 4);
-+		memcpy(entry->key.dip, &iph->daddr, 4);
-+	} else if (ip_ver == 6) {
-+		struct ipv6hdr *iph = (struct ipv6hdr*)ip_hdr;
-+		for (i=0; i<4; i++) {
-+			memcpy(&(entry->key.sip[i*4]), &(iph->saddr.in6_u.u6_addr32[i]), 4);
-+			memcpy(&(entry->key.dip[i*4]), &(iph->daddr.in6_u.u6_addr32[i]), 4);
-+		}
-+	}
-+	*(__u16*)&entry->key.l4_bytes[0] = tcp_hdr->source;
-+	*(__u16*)&entry->key.l4_bytes[2] = tcp_hdr->dest;
-+
-+	entry->key.l7_bytes[4] = 0xff;
-+	entry->key.l7_bytes[5] = 0x53;
-+	entry->key.l7_bytes[6] = 0x4d;
-+	entry->key.l7_bytes[7] = 0x42;
-+
-+	/* action of hash entry match */
-+	entry->action.sw_id = 1;
-+	entry->action.dest_qid = (__u8)TOE_TOE_QID(sw_id);
-+	entry->action.srce_qid = 0;
-+	hash_entry_index = hash_add_toe_entry(entry);
-+
-+	return hash_entry_index;
-+}
-+
-+// best performance of tcp streaming.
-+/*---------------------------------------------------------------------------
-+ * create_toe_hash_entry_smb
-+ * add SMB header in hash entry.
-+ *-------------------------------------------------------------------------*/
-+int create_toe_hash_entry_ftp(int ip_ver, void* ip_hdr, struct tcphdr* tcphdr)
-+{
-+	return 0;
-+}
-+
-+// is hash entry for nfs needed?
-+
-+/*
-+ * Create a TOE hash entry by given ip addresses and tcp port numbers.
-+ * hash entry index will be saved in sw connection.
-+ */
-+/*---------------------------------------------------------------------------
-+ * create_toe_hash_entry
-+ *-------------------------------------------------------------------------*/
-+int create_toe_hash_entry(int ip_ver, void* ip_hdr, struct tcphdr* tcp_hdr, int sw_id)
-+{
-+	HASH_ENTRY_T	hash_entry, *entry;
-+//	unsigned long	hash_key[HASH_MAX_DWORDS];
-+	int	hash_entry_index;
-+
-+	entry = (HASH_ENTRY_T*) &hash_entry;
-+	memset((void*)entry, 0, sizeof(HASH_ENTRY_T));
-+	entry->rule = 0;
-+	/* enable fields of hash key */
-+	entry->key_present.ip_protocol = 1;
-+	entry->key_present.sip = 1;
-+	entry->key_present.dip = 1;
-+	entry->key_present.l4_bytes_0_3 = 1;	// src port and dest port
-+
-+	/* hash key */
-+	entry->key.ip_protocol = IPPROTO_TCP;
-+	if (ip_ver == 4) {
-+		// key of ipv4
-+		struct iphdr* iph = (struct iphdr*)ip_hdr;
-+		memcpy(entry->key.sip, &iph->saddr, 4);
-+		memcpy(entry->key.dip, &iph->daddr, 4);
-+	} else if (ip_ver == 6) {
-+		// key of ipv6
-+		int i=0;
-+		struct ipv6hdr *iph = (struct ipv6hdr*)ip_hdr;
-+		for (i=0; i<4; i++) {
-+			memcpy(&(entry->key.sip[i*4]), &(iph->saddr.in6_u.u6_addr32[i]), 4);
-+			memcpy(&(entry->key.dip[i*4]), &(iph->daddr.in6_u.u6_addr32[i]), 4);
-+		}
-+	}
-+	*(__u16*)&entry->key.l4_bytes[0] = tcp_hdr->source;
-+	*(__u16*)&entry->key.l4_bytes[2] = tcp_hdr->dest;
-+	// is it necessary to write ip version to hash key?
-+
-+	/* action of hash entry match */
-+	entry->action.sw_id = 1;
-+	entry->action.dest_qid = (__u8)TOE_TOE_QID(sw_id);
-+	entry->action.srce_qid = 0;	// 0 for SW FreeQ. 1 for HW FreeQ.
-+	hash_entry_index = hash_add_toe_entry(entry);
-+//	printk("\n%s. sw_id %d, hash_entry index %x\n",
-+//		__func__, TOE_TOE_QID(sw_id), hash_entry_index);
-+	return hash_entry_index;
-+}
-+
-+/*---------------------------------------------------------------------------
-+ * init_toeq
-+ * 1. Reserve a TOE Queue id first, to get the sw toe_connection.
-+ * 2. Setup the hash entry with given iphdr and tcphdr, save hash entry index
-+ *    in sw toe_connection.
-+ * 3. Prepare sw toe_connection and allocate buffers.
-+ * 4. Validate hash entry.
-+ *-------------------------------------------------------------------------*/
-+struct toe_conn* init_toeq(int ipver, void* iph, struct tcphdr* tcp_hdr,
-+	TOE_INFO_T* toe, unsigned char* l2hdr)
-+{
-+//	printk("\t*** %s, ipver %d\n", __func__, ipver);
-+	int qid=-1;
-+	struct toe_conn* connection;
-+	int hash_entry_index;
-+	// int i=0;
-+	unsigned short	dest_port = ntohs(tcp_hdr->dest);
-+
-+	if (dest_port == 445) {
-+		printk("%s::SMB/CIFS connection\n", __func__);
-+	} else if (dest_port == 20) {
-+		printk("%s::ftp-data connection\n", __func__);
-+	} else if (dest_port == 2049) {
-+		printk("%s::nfs daemon connection\n", __func__);
-+	}
-+	qid = get_connection_index();
-+	if (qid<0)
-+		return 0;	// setup toeq failure
-+	set_toe_connection(qid, 1); // reserve this sw toeq.
-+
-+	//connection = (struct toe_conn*)&(toe_connections[qid]);
-+	hash_entry_index = create_toe_hash_entry(ipver, iph, tcp_hdr, qid);
-+	if (hash_entry_index <0) {
-+		printk("%s::release toe hash entry!\n", __func__);
-+		set_toe_connection(qid, 0); // release this sw toeq.
-+		return 0;
-+	}
-+	connection = create_sw_toe_connection(qid, ipver, iph, tcp_hdr);
-+	connection->hash_entry_index = (__u16) hash_entry_index;
-+
-+	fill_toeq_buf(qid, toe);
-+	memcpy(&connection->l2_hdr, l2hdr, sizeof(struct ethhdr));
-+	spin_lock_init(&connection->conn_lock);
-+
-+	return connection;
-+}
-+
-+#if 0
-+/*----------------------------------------------------------------------
-+*   toe_init_toe_queue
-+*   (1) Initialize the TOE Queue Header
-+*       Register: TOE_TOE_QUE_HDR_BASE (0x60003000)
-+*   (2) Initialize Descriptors of TOE Queues
-+*----------------------------------------------------------------------*/
-+void toe_init_toe_queue(TOE_INFO_T* toe)
-+{
-+}
-+EXPORT_SYMBOL(toe_init_toe_queue);
-+#endif
-+
-+/*---------------------------------------------------------------------------
-+ * dump_jumbo_skb
-+ *-------------------------------------------------------------------------*/
-+void dump_jumbo_skb(struct jumbo_frame *jumbo_skb)
-+{
-+	if (jumbo_skb->skb0) {
-+//		printk("%s. jumbo skb %x, len %d\n",
-+//			__func__, jumbo_skb->skb0->data, jumbo_skb->skb0->len);
-+		netif_rx(jumbo_skb->skb0);
-+	}
-+	jumbo_skb->skb0 = 0;
-+	jumbo_skb->tail = 0;
-+	jumbo_skb->iphdr0 = 0;
-+	jumbo_skb->tcphdr0 = 0;
-+}
-+
-+/* ---------------------------------------------------------------------
-+ * Append skb to skb0. skb0 is the jumbo frame that will be passed to
-+ * kernel tcp.
-+ * --------------------------------------------------------------------*/
-+void rx_append_skb(struct jumbo_frame *jumbo_skb, struct sk_buff* skb, int payload_len)
-+{
-+	struct iphdr* iphdr0 = (struct iphdr*)&(skb->data[0]);
-+	int ip_hdrlen = iphdr0->ihl << 2;
-+	struct tcphdr* tcphdr0 = (struct tcphdr*)&(skb->data[ip_hdrlen]);
-+
-+	if (!jumbo_skb->skb0) {
-+		// head of the jumbo frame.
-+		jumbo_skb->skb0 = skb;
-+		jumbo_skb->tail = 0;
-+		jumbo_skb->iphdr0 = iphdr0;
-+		jumbo_skb->tcphdr0 = tcphdr0;
-+	} else {
-+		if (!jumbo_skb->tail)
-+			skb_shinfo(jumbo_skb->skb0)->frag_list = skb;
-+		else
-+			(jumbo_skb->tail)->next = skb;
-+		jumbo_skb->tail = skb;
-+
-+		// do we need to change truesize as well?
-+		jumbo_skb->skb0->len += payload_len;
-+		jumbo_skb->skb0->data_len += payload_len;
-+
-+		jumbo_skb->iphdr0->tot_len = htons(ntohs(jumbo_skb->iphdr0->tot_len)+payload_len);
-+		jumbo_skb->tcphdr0->ack_seq = tcphdr0->ack_seq;
-+		jumbo_skb->tcphdr0->window = tcphdr0->window;
-+
-+		skb->len += payload_len;
-+		skb->data_len = 0;
-+		skb->data += ntohs(iphdr0->tot_len) - payload_len;
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_gmac_handle_toeq
-+* (1) read interrupt Queue to get TOE Q.
-+* (2) get packet fro TOE Q and send to upper layer handler.
-+* (3) allocate new buffers and put to TOE Q. Intr Q buffer is recycled.
-+*----------------------------------------------------------------------*/
-+void toe_gmac_handle_toeq(struct net_device *dev, GMAC_INFO_T* tp, __u32 status)
-+{
-+	//volatile INTRQ_INFO_T	*intrq_info;
-+	//TOEQ_INFO_T		*toeq_info;
-+	volatile NONTOE_QHDR_T	*intr_qhdr;
-+	volatile TOE_QHDR_T		*toe_qhdr;
-+	volatile INTR_QHDR_T	*intr_curr_desc;
-+	TOE_INFO_T	*toe = &toe_private_data;
-+
-+	volatile GMAC_RXDESC_T	*toe_curr_desc; // , *fq_desc;// *tmp_desc;
-+	volatile DMA_RWPTR_T	intr_rwptr, toeq_rwptr;  // fq_rwptr;
-+
-+	unsigned int 	pkt_size, desc_count, tcp_qid;
-+	volatile unsigned int	toeq_wptr;
-+	struct toe_conn*		connection;
-+	int		i, frag_id = 0;
-+	// unsigned long	toeq_flags;
-+	struct jumbo_frame	jumbo_skb;
-+	struct sk_buff	*skb;
-+	__u32	interrupt_status;
-+
-+	in_toe_isr++;
-+
-+	interrupt_status = status >> 24;
-+	// get interrupt queue header
-+	intr_qhdr = (volatile NONTOE_QHDR_T*)TOE_INTR_Q_HDR_BASE;
-+	memset(&jumbo_skb, 0, sizeof(struct jumbo_frame));
-+
-+	for (i=0; i> 1;
-+			continue;
-+		}
-+		interrupt_status = interrupt_status >> 1;
-+		intr_rwptr.bits32 = readl(&intr_qhdr->word1);
-+
-+		while ( intr_rwptr.bits.rptr != intr_rwptr.bits.wptr) {
-+			int max_pktsize = 1;
-+			// get interrupt queue descriptor.
-+			intr_curr_desc = (INTR_QHDR_T*)toe->intr_desc_base +
-+				i* TOE_INTR_DESC_NUM + intr_rwptr.bits.rptr;
-+//			printk("%s::int %x\n", __func__, intr_curr_desc->word1.bits32);
-+			// get toeq id
-+			tcp_qid = (u8)intr_curr_desc->word1.bits.tcp_qid - (u8)TOE_TOE_QID(0);
-+			// get toeq queue header
-+			toe_qhdr = (volatile TOE_QHDR_T*) TOE_TOE_QUE_HDR_BASE;
-+			toe_qhdr += tcp_qid;
-+			connection = &toe_connections[tcp_qid];
-+			del_timer(&connection->rx_timer);
-+			// Gary Chen spin_lock_irqsave(&connection->conn_lock, toeq_flags);
-+			// handling interrupts of this TOE Q.
-+			if (intr_curr_desc->word1.bits.ctl || intr_curr_desc->word1.bits.osq ||
-+				intr_curr_desc->word1.bits.abn)
-+				max_pktsize = 0;
-+			if (!max_pktsize || intr_curr_desc->word1.bits.TotalPktSize) {
-+				desc_count=0;
-+				// wptr in intl queue is where this TOE interrupt should stop.
-+				toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
-+				toeq_wptr = intr_curr_desc->word0.bits.wptr;
-+				if (connection->toeq_rwptr.bits.rptr != toeq_rwptr.bits.rptr)
-+					printk("conn rptr %d, hw rptr %d\n",
-+						connection->toeq_rwptr.bits.rptr, toeq_rwptr.bits.rptr);
-+
-+				if (intr_curr_desc->word1.bits.ctl &&
-+					(toeq_rwptr.bits.rptr == toeq_wptr)) {
-+					printk("\nctrl frame, but not in TOE queue! conn rptr %d, hw wptr %d\n",
-+						connection->toeq_rwptr.bits.rptr, toeq_wptr);
-+//					dump_toe_qhdr(toe_qhdr);
-+//					dump_intrq_desc(intr_curr_desc);
-+				}
-+				// while (toeq_rwptr.bits.rptr != intr_curr_desc->word0.bits.wptr) {
-+				while (toe_qhdr->word1.bits.rptr != intr_curr_desc->word0.bits.wptr) {
-+					frag_id++;
-+					toe_curr_desc = (volatile GMAC_RXDESC_T *)(toe->toe_desc_base[tcp_qid]
-+						+ toe_qhdr->word1.bits.rptr *sizeof(GMAC_RXDESC_T));
-+					connection->curr_desc = (GMAC_RXDESC_T *)toe_curr_desc;
-+					desc_count = toe_curr_desc->word0.bits.desc_count;
-+					pkt_size = toe_curr_desc->word1.bits.byte_count;
-+					consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
-+						PCI_DMA_FROMDEVICE);
-+					skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr)-
-+						SKB_RESERVE_BYTES));
-+					_debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x01);
-+					connection->curr_rx_skb = skb;
-+					skb_reserve(skb, RX_INSERT_BYTES);
-+					if ((skb->len + pkt_size) > (1514+16))
-+					{
-+						printk("skb->len=%d, pkt_size=%d\n",skb->len, pkt_size);
-+						while(1);
-+					}
-+
-+					skb_put(skb, pkt_size);
-+					skb->dev = dev;
-+					skb->protocol = eth_type_trans(skb, dev);
-+					skb->ip_summed = CHECKSUM_UNNECESSARY;
-+
-+					if (toe_curr_desc->word3.bits32 & 0x1b000000)
-+						dump_jumbo_skb(&jumbo_skb);
-+
-+					rx_append_skb(&jumbo_skb, skb, pkt_size-toe_curr_desc->word3.bits.l7_offset);
-+//					spin_lock_irqsave(&gmac_fq_lock, flags);
-+					toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
-+					SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
-+//					spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+					if (storlink_ctl.fqint_threshold)
-+						continue;
-+#if 0
-+//#if (HANDLE_FREEQ_METHOD == HANDLE_FREEQ_INDIVIDUAL)
-+					if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
-+						printk("%s::toe queue alloc buffer ", __func__);
-+					}
-+					*(unsigned int*)(skb->data) = (unsigned int)skb;
-+					connection->curr_rx_skb = skb;
-+					skb_reserve(skb, SKB_RESERVE_BYTES);
-+
-+					spin_lock_irqsave(&gmac_fq_lock, flags);
-+					fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+					if (toe->fq_rx_rwptr.bits.wptr != fq_rwptr.bits.wptr) {
-+						printk("%s::fq_rx_rwptr %x\n", __func__, toe->fq_rx_rwptr.bits32);
-+						mac_stop_txdma((struct net_device*) tp->dev);
-+						spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+						while(1);
-+					}
-+					fq_desc = (GMAC_RXDESC_T*)toe->swfq_desc_base + fq_rwptr.bits.wptr;
-+					fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
-+
-+					fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
-+					SET_WPTR(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
-+					toe->fq_rx_rwptr.bits32 = fq_rwptr.bits32;
-+					spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+#endif
-+				} // end of this multi-desc.
-+				dump_jumbo_skb(&jumbo_skb);
-+				dev->last_rx = jiffies;
-+				connection->toeq_rwptr.bits32 = toeq_rwptr.bits32;
-+			} else if (intr_curr_desc->word1.bits.sat) {
-+				toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
-+				toeq_wptr = intr_curr_desc->word0.bits.wptr;
-+				if (connection->toeq_rwptr.bits.rptr != toeq_rwptr.bits.rptr)
-+					printk("SAT. conn rptr %d, hw rptr %d\n",
-+						connection->toeq_rwptr.bits.rptr, toeq_rwptr.bits.rptr);
-+/*
-+					printk("%s::SAT int!, ackcnt %x, seqcnt %x, rptr %d, wptr %d, ack %x, qhack %x\n",
-+ 						__func__, intr_curr_desc->word4.bits.AckCnt, intr_curr_desc->word4.bits.SeqCnt,
-+						toeq_rptr, toeq_wptr, intr_curr_desc->word3.ack_num, toe_qhdr->word4.ack_num);*/
-+				/* pure ack */
-+				if (toeq_rwptr.bits.rptr == toeq_wptr) {
-+					if (intr_curr_desc->word4.bits32) {
-+						skb = gen_pure_ack(connection, (TOE_QHDR_T *)toe_qhdr, (INTR_QHDR_T *)intr_curr_desc);
-+						skb_put(skb, 60);
-+						skb->dev = connection->dev;
-+						skb->ip_summed = CHECKSUM_UNNECESSARY;
-+						skb->protocol = eth_type_trans(skb, connection->dev);
-+						netif_rx(skb);
-+					} else
-+						printk("%s::SAT Interrupt!. But cnt is 0!\n", __func__);
-+				} else {
-+					// while (toeq_rwptr.bits.rptr != toeq_wptr) {
-+					while (toe_qhdr->word1.bits.rptr != intr_curr_desc->word0.bits.wptr) {
-+						toe_curr_desc = (volatile GMAC_RXDESC_T*)(toe->toe_desc_base[tcp_qid]
-+							+ toe_qhdr->word1.bits.rptr * sizeof(GMAC_RXDESC_T));
-+						connection->curr_desc = (GMAC_RXDESC_T *)toe_curr_desc;
-+						desc_count = toe_curr_desc->word0.bits.desc_count;
-+						pkt_size = toe_curr_desc->word1.bits.byte_count;
-+						consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
-+							PCI_DMA_FROMDEVICE);
-+						// if ( ((toeq_rwptr.bits.rptr +1)&(TOE_TOE_DESC_NUM-1)) == toeq_wptr) {
-+						if ( RWPTR_ADVANCE_ONE(toe_qhdr->word1.bits.rptr, TOE_TOE_DESC_NUM) == toeq_wptr) {
-+							skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr) -
-+								SKB_RESERVE_BYTES));
-+							_debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x04);
-+							connection->curr_rx_skb = skb;
-+							skb_reserve(skb, RX_INSERT_BYTES);
-+							skb_put(skb, pkt_size);
-+							skb->dev = dev;
-+							skb->protocol = eth_type_trans(skb, dev);
-+							skb->ip_summed = CHECKSUM_UNNECESSARY;
-+							// printk("toeq_rptr %d, wptr %d\n", toeq_rptr, toeq_wptr);
-+							netif_rx(skb);
-+							dev->last_rx = jiffies;
-+/*
-+							if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
-+
-+							}
-+							*(unsigned int*)(skb->data) = (unsigned int) skb;
-+							skb_reserve(skb, SKB_RESERVE_BYTES); */
-+						} else {
-+							// reuse this skb, append to free queue..
-+							skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr)-
-+								SKB_RESERVE_BYTES));
-+							_debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x05);
-+							connection->curr_rx_skb = skb;
-+							dev_kfree_skb_irq(skb);
-+						}
-+#if 0
-+						spin_lock_irqsave(&gmac_fq_lock, flags);
-+						fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+/*						if (toe->fq_rx_rwptr.bits.wptr != fq_rwptr.bits.wptr) {
-+							printk("%s::fq_rx_rwptr %x\n", __func__, toe->fq_rx_rwptr.bits32);
-+							mac_stop_txdma((struct net_device*) tp->dev);
-+							spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+							while(1);
-+						} */
-+						fq_desc = (GMAC_RXDESC_T*)toe->swfq_desc_base + fq_rwptr.bits.wptr;
-+						fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
-+
-+						fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
-+						SET_WPTR(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
-+						toe->fq_rx_rwptr.bits32 = fq_rwptr.bits32;
-+	//					spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+#endif
-+//						spin_lock_irqsave(&gmac_fq_lock, flags);
-+						toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
-+						SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
-+//						spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+					}
-+				} // end of ACK with options.
-+				connection->toeq_rwptr.bits32 = toeq_rwptr.bits32;
-+				// Gary Chen spin_unlock_irqrestore(&connection->conn_lock, toeq_flags);
-+//				}
-+			};
-+			update_timer(connection);
-+			// any protection against interrupt queue header?
-+			intr_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(intr_rwptr.bits.rptr, TOE_INTR_DESC_NUM);
-+			SET_RPTR(&intr_qhdr->word1, intr_rwptr.bits.rptr);
-+			intr_rwptr.bits32 = readl(&intr_qhdr->word1);
-+			toe_gmac_fill_free_q();
-+		} // end of this interrupt Queue processing.
-+	} // end of all interrupt Queues.
-+
-+	in_toe_isr = 0;
-+}
-+
-+
---- /dev/null
-+++ b/drivers/net/sl_lepus_hash.c
-@@ -0,0 +1,553 @@
-+/**************************************************************************
-+* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
-+*--------------------------------------------------------------------------
-+* Name			: sl_lepus_hash.c
-+* Description	:
-+*		Handle Storlink Lepus Hash Functions
-+*
-+* History
-+*
-+*	Date		Writer		Description
-+*----------------------------------------------------------------------------
-+*	03/13/2006	Gary Chen	Create and implement
-+*
-+****************************************************************************/
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#define	 MIDWAY
-+#define	 SL_LEPUS
-+
-+#include 
-+#include 
-+#include 
-+
-+#ifndef RXTOE_DEBUG
-+#define RXTOE_DEBUG
-+#endif
-+#undef RXTOE_DEBUG
-+
-+/*----------------------------------------------------------------------
-+* Definition
-+*----------------------------------------------------------------------*/
-+#define	hash_printf				printk
-+
-+#define HASH_TIMER_PERIOD		(60*HZ)	// seconds
-+#define HASH_ILLEGAL_INDEX		0xffff
-+
-+/*----------------------------------------------------------------------
-+* Variables
-+*----------------------------------------------------------------------*/
-+u32					hash_activate_bits[HASH_TOTAL_ENTRIES/32];
-+u32					hash_nat_owner_bits[HASH_TOTAL_ENTRIES/32];
-+char 				hash_tables[HASH_TOTAL_ENTRIES][HASH_MAX_BYTES] __attribute__ ((aligned(16)));
-+static struct timer_list hash_timer_obj;
-+LIST_HEAD(hash_timeout_list);
-+
-+/*----------------------------------------------------------------------
-+* Functions
-+*----------------------------------------------------------------------*/
-+void dm_long(u32 location, int length);
-+static void hash_timer_func(u32 data);
-+
-+/*----------------------------------------------------------------------
-+* hash_init
-+*----------------------------------------------------------------------*/
-+void hash_init(void)
-+{
-+	int i;
-+	volatile u32 *dp1, *dp2, dword;
-+
-+	dp1 = (volatile u32 *) TOE_V_BIT_BASE;
-+	dp2 = (volatile u32 *) TOE_A_BIT_BASE;
-+
-+	for (i=0; iindex, 1);
-+//	printk("Dump hash key!\n");
-+//	dump_hash_key(entry);
-+	return entry->index;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_set_valid_flag
-+*----------------------------------------------------------------------*/
-+void hash_set_valid_flag(int index, int valid)
-+{
-+	register u32 reg32;
-+
-+	reg32 = TOE_V_BIT_BASE + (index/32) * 4;
-+
-+	if (valid)
-+	{
-+		writel(readl(reg32) | (1 << (index%32)), reg32);
-+	}
-+	else
-+	{
-+		writel(readl(reg32) & ~(1 << (index%32)), reg32);
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_set_nat_owner_flag
-+*----------------------------------------------------------------------*/
-+void hash_set_nat_owner_flag(int index, int valid)
-+{
-+	if (valid)
-+	{
-+		hash_nat_owner_bits[index/32] |= (1 << (index % 32));
-+	}
-+	else
-+	{
-+		hash_nat_owner_bits[index/32] &= ~(1 << (index % 32));
-+	}
-+}
-+
-+
-+/*----------------------------------------------------------------------
-+* hash_build_keys
-+*----------------------------------------------------------------------*/
-+int hash_build_keys(u32 *destp, HASH_ENTRY_T *entry)
-+{
-+	u32 	data;
-+	unsigned char 	*cp;
-+	int				i, j;
-+	unsigned short 	index;
-+	int 			total;
-+
-+	memset((void *)destp, 0, HASH_MAX_BYTES);
-+	cp = (unsigned char *)destp;
-+
-+	if (entry->key_present.port || entry->key_present.Ethertype)
-+	{
-+		HASH_PUSH_WORD(cp, entry->key.Ethertype);		// word 0
-+		HASH_PUSH_BYTE(cp, entry->key.port);			// Byte 2
-+		HASH_PUSH_BYTE(cp, 0);							// Byte 3
-+	}
-+	else
-+	{
-+		HASH_PUSH_DWORD(cp, 0);
-+	}
-+
-+	if (entry->key_present.da || entry->key_present.sa)
-+	{
-+		unsigned char mac[4];
-+		if (entry->key_present.da)
-+		{
-+			for (i=0; i<4; i++)
-+				HASH_PUSH_BYTE(cp, entry->key.da[i]);
-+		}
-+		mac[0] = (entry->key_present.da) ? entry->key.da[4] : 0;
-+		mac[1] = (entry->key_present.da) ? entry->key.da[5] : 0;
-+		mac[2] = (entry->key_present.sa) ? entry->key.sa[0] : 0;
-+		mac[3] = (entry->key_present.sa) ? entry->key.sa[1] : 0;
-+		data = mac[0] + (mac[1]<<8) + (mac[2]<<16) + (mac[3]<<24);
-+		HASH_PUSH_DWORD(cp, data);
-+		if (entry->key_present.sa)
-+		{
-+			for (i=2; i<6; i++)
-+				HASH_PUSH_BYTE(cp, entry->key.sa[i]);
-+		}
-+	}
-+
-+	if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
-+	{
-+		HASH_PUSH_WORD(cp, entry->key.vlan_id);		// low word
-+		HASH_PUSH_WORD(cp, entry->key.pppoe_sid);	// high word
-+	}
-+	if (entry->key_present.ipv4_hdrlen || entry->key_present.ip_tos || entry->key_present.ip_protocol)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.ip_protocol);		// Byte 0
-+		HASH_PUSH_BYTE(cp, entry->key.ip_tos);			// Byte 1
-+		HASH_PUSH_BYTE(cp, entry->key.ipv4_hdrlen);		// Byte 2
-+		HASH_PUSH_BYTE(cp, 0);							// Byte 3
-+	}
-+
-+	if (entry->key_present.ipv6_flow_label)
-+	{
-+		HASH_PUSH_DWORD(cp, entry->key.ipv6_flow_label);	// low word
-+	}
-+	if (entry->key_present.sip)
-+	{
-+		// input (entry->key.sip[i]) is network-oriented
-+		// output (hash key) is host-oriented
-+		for (i=3; i>=0; i--)
-+			HASH_PUSH_BYTE(cp, entry->key.sip[i]);
-+		if (entry->key.ipv6)
-+		{
-+			for (i=4; i<16; i+=4)
-+			{
-+				for (j=i+3; j>=i; j--)
-+					HASH_PUSH_BYTE(cp, entry->key.sip[j]);
-+			}
-+		}
-+	}
-+	if (entry->key_present.dip)
-+	{
-+		// input (entry->key.sip[i]) is network-oriented
-+		// output (hash key) is host-oriented
-+		for (i=3; i>=0; i--)
-+			HASH_PUSH_BYTE(cp, entry->key.dip[i]);
-+		if (entry->key.ipv6)
-+		{
-+			for (i=4; i<16; i+=4)
-+			{
-+				for (j=i+3; j>=i; j--)
-+					HASH_PUSH_BYTE(cp, entry->key.dip[j]);
-+			}
-+		}
-+	}
-+
-+	if (entry->key_present.l4_bytes_0_3)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
-+	}
-+	if (entry->key_present.l4_bytes_4_7)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[4]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[5]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[6]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[7]);
-+	}
-+	if (entry->key_present.l4_bytes_8_11)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[8]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[9]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[10]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[11]);
-+	}
-+	if (entry->key_present.l4_bytes_12_15)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[12]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[13]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[14]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[15]);
-+	}
-+	if (entry->key_present.l4_bytes_16_19)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[16]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[17]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[18]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[19]);
-+	}
-+	if (entry->key_present.l4_bytes_20_23)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[20]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[21]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[22]);
-+		HASH_PUSH_BYTE(cp, entry->key.l4_bytes[23]);
-+	}
-+	if (entry->key_present.l7_bytes_0_3)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[0]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[1]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[2]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[3]);
-+	}
-+	if (entry->key_present.l7_bytes_4_7)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[4]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[5]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[6]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[7]);
-+	}
-+	if (entry->key_present.l7_bytes_8_11)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[8]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[9]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[10]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[11]);
-+	}
-+	if (entry->key_present.l7_bytes_12_15)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[12]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[13]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[14]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[15]);
-+	}
-+	if (entry->key_present.l7_bytes_16_19)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[16]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[17]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[18]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[19]);
-+	}
-+	if (entry->key_present.l7_bytes_20_23)
-+	{
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[20]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[21]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[22]);
-+		HASH_PUSH_BYTE(cp, entry->key.l7_bytes[23]);
-+	}
-+
-+	// get hash index
-+	total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
-+
-+	if (total > HASH_MAX_KEY_DWORD)
-+	{
-+		//hash_printf("Total key words (%d) is too large (> %d)!\n",
-+		//				total, HASH_MAX_KEY_DWORD);
-+		return -1;
-+	}
-+
-+	if (entry->key_present.port || entry->key_present.Ethertype)
-+		index = hash_gen_crc16((unsigned char *)destp, total * 4);
-+	else
-+	{
-+		if (total == 1)
-+		{
-+			hash_printf("No key is assigned!\n");
-+			return -1;
-+		}
-+
-+		index = hash_gen_crc16((unsigned char *)(destp+1), (total-1) * 4);
-+	}
-+
-+	entry->index = index & HASH_BITS_MASK;
-+
-+	//hash_printf("Total key words = %d, Hash Index= %d\n",
-+	//				total, entry->index);
-+
-+	cp = (unsigned char *)destp;
-+	cp+=3;
-+	HASH_PUSH_BYTE(cp, entry->rule);	// rule
-+
-+	entry->total_dwords = total;
-+
-+	return total;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_build_nat_keys
-+*----------------------------------------------------------------------*/
-+void hash_build_nat_keys(u32 *destp, HASH_ENTRY_T *entry)
-+{
-+	unsigned char 	*cp;
-+	int				i;
-+	unsigned short 	index;
-+	int 			total;
-+
-+	memset((void *)destp, 0, HASH_MAX_BYTES);
-+
-+	cp = (unsigned char *)destp + 2;
-+	HASH_PUSH_BYTE(cp, entry->key.port);
-+	cp++;
-+
-+	if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
-+	{
-+		HASH_PUSH_WORD(cp, entry->key.vlan_id);		// low word
-+		HASH_PUSH_WORD(cp, entry->key.pppoe_sid);	// high word
-+	}
-+
-+	HASH_PUSH_BYTE(cp, entry->key.ip_protocol);
-+	cp+=3;
-+
-+	// input (entry->key.sip[i]) is network-oriented
-+	// output (hash key) is host-oriented
-+	for (i=3; i>=0; i--)
-+		HASH_PUSH_BYTE(cp, entry->key.sip[i]);
-+
-+	// input (entry->key.sip[i]) is network-oriented
-+	// output (hash key) is host-oriented
-+	for (i=3; i>=0; i--)
-+		HASH_PUSH_BYTE(cp, entry->key.dip[i]);
-+
-+	HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
-+	HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
-+	HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
-+	HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
-+
-+	// get hash index
-+	total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
-+
-+	index = hash_gen_crc16((unsigned char *)destp, total * 4);
-+	entry->index = index & ((1 << HASH_BITS) - 1);
-+
-+	cp = (unsigned char *)destp;
-+	cp+=3;
-+	HASH_PUSH_BYTE(cp, entry->rule);	// rule
-+
-+	entry->total_dwords = total;
-+}
-+
-+
-+/*----------------------------------------------------------------------
-+* hash_write_entry
-+*----------------------------------------------------------------------*/
-+int hash_write_entry(HASH_ENTRY_T *entry, unsigned char *key)
-+{
-+	int		i;
-+	u32		*srcep, *destp, *destp2;
-+
-+	srcep = (u32 *)key;
-+	destp2 = destp = (u32 *)&hash_tables[entry->index][0];
-+
-+	for (i=0; i<(entry->total_dwords); i++, srcep++, destp++)
-+		*destp = *srcep;
-+
-+	srcep = (u32 *)&entry->action;
-+	*destp++ = *srcep;
-+
-+	srcep = (u32 *)&entry->param;
-+	for (i=0; i<(sizeof(ENTRY_PARAM_T)/sizeof(*destp)); i++, srcep++, destp++)
-+		*destp = *srcep;
-+
-+	memset(destp, 0, (HASH_MAX_DWORDS-entry->total_dwords-HASH_ACTION_DWORDS) * sizeof(u32));
-+
-+	consistent_sync(destp2, (entry->total_dwords+HASH_ACTION_DWORDS) * 4, PCI_DMA_TODEVICE);
-+	return 0;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_timer_func
-+*----------------------------------------------------------------------*/
-+static void hash_timer_func(u32 data)
-+{
-+	int				i, j;
-+	volatile u32	*active_p, *own_p, *valid_p;
-+	u32				a_bits, own_bits;
-+
-+	valid_p = (volatile u32 *)TOE_V_BIT_BASE;
-+	active_p = (volatile u32 *)hash_activate_bits;
-+	own_p = (volatile u32 *)hash_nat_owner_bits;
-+	for (i=0; i<(HASH_TOTAL_ENTRIES/32); i++, own_p++, active_p++, valid_p++)
-+	{
-+		*active_p |= readl(TOE_A_BIT_BASE + (i*4));
-+		a_bits = *active_p;
-+		own_bits = *own_p;
-+		if (own_bits)
-+		{
-+#ifndef DEBUG_NAT_MIXED_HW_SW_TX
-+			a_bits = own_bits & ~a_bits;
-+#else
-+			a_bits = own_bits & a_bits;
-+#endif
-+			for (j=0; a_bits && j<32; j++)
-+			{
-+				if (a_bits & 1)
-+				{
-+					*valid_p &= ~(1 << j);		// invalidate it
-+#if !(defined(NAT_DEBUG_LAN_HASH_TIMEOUT) || defined(NAT_DEBUG_WAN_HASH_TIMEOUT))
-+					*own_p &= ~(1 << j);		// release ownership for NAT
-+#endif
-+// #ifdef DEBUG_NAT_MIXED_HW_SW_TX
-+#if 0
-+					hash_printf("%lu %s: Clear hash index: %d\n", jiffies/HZ, __func__, i*32+j);
-+#endif
-+				}
-+				a_bits >>= 1;
-+			}
-+			*active_p &= ~own_bits;		// deactivate it for next polling
-+		}
-+	}
-+
-+	hash_timer_obj.expires = jiffies + HASH_TIMER_PERIOD;
-+	add_timer((struct timer_list *)data);
-+}
-+
-+/*----------------------------------------------------------------------
-+* dm_long
-+*----------------------------------------------------------------------*/
-+void dm_long(u32 location, int length)
-+{
-+	u32		*start_p, *curr_p, *end_p;
-+	u32		*datap, data;
-+	int		i;
-+
-+	//if (length > 1024)
-+	//	length = 1024;
-+
-+	start_p = (u32 *)location;
-+	end_p = (u32 *)location + length;
-+	curr_p = (u32 *)((u32)location & 0xfffffff0);
-+	datap = (u32 *)location;
-+	while (curr_p < end_p)
-+	{
-+		hash_printf("0x%08x: ",(u32)curr_p & 0xfffffff0);
-+		for (i=0; i<4; i++)
-+		{
-+			if (curr_p < start_p || curr_p >= end_p)
-+               hash_printf("         ");
-+			else
-+			{
-+				data = *datap;
-+				hash_printf("%08X ", data);
-+			}
-+			if (i==1)
-+              hash_printf("- ");
-+
-+			curr_p++;
-+			datap++;
-+		}
-+        hash_printf("\n");
-+	}
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_dump_entry
-+*----------------------------------------------------------------------*/
-+void hash_dump_entry(int index)
-+{
-+	hash_printf("Hash Index %d:\n", index);
-+	dm_long((u32)&hash_tables[index][0], HASH_MAX_DWORDS);
-+}
-+
-+
---- /dev/null
-+++ b/drivers/net/sl_switch.c
-@@ -0,0 +1,650 @@
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#define GMAC_GLOBAL_BASE_ADDR       (IO_ADDRESS(SL2312_GLOBAL_BASE))
-+#define GPIO_BASE_ADDR1  (IO_ADDRESS(SL2312_GPIO_BASE1))
-+enum GPIO_REG
-+{
-+    GPIO_DATA_OUT   = 0x00,
-+    GPIO_DATA_IN    = 0x04,
-+    GPIO_PIN_DIR    = 0x08,
-+    GPIO_BY_PASS    = 0x0c,
-+    GPIO_DATA_SET   = 0x10,
-+    GPIO_DATA_CLEAR = 0x14,
-+};
-+
-+#define GMAC_SPEED_10			0
-+#define GMAC_SPEED_100			1
-+#define GMAC_SPEED_1000			2
-+
-+enum phy_state
-+{
-+    LINK_DOWN   = 0,
-+    LINK_UP     = 1
-+};
-+
-+#ifndef BIT
-+#define BIT(x)						(1 << (x))
-+#endif
-+
-+//int Get_Set_port_status();
-+unsigned int SPI_read_bit(void);
-+void SPI_write_bit(char bit_EEDO);
-+void SPI_write(unsigned char block,unsigned char subblock,unsigned char addr,unsigned int value);
-+unsigned int SPI_read(unsigned char block,unsigned char subblock,unsigned char addr);
-+int SPI_default(void);
-+void SPI_CS_enable(unsigned char enable);
-+unsigned int SPI_get_identifier(void);
-+void phy_write(unsigned char port_no,unsigned char reg,unsigned int val);
-+unsigned int phy_read(unsigned char port_no,unsigned char reg);
-+void phy_write_masked(unsigned char port_no,unsigned char reg,unsigned int val,unsigned int mask);
-+void init_seq_7385(unsigned char port_no) ;
-+void phy_receiver_init (unsigned char port_no);
-+
-+#define PORT_NO		4
-+int switch_pre_speed[PORT_NO]={0,0,0,0};
-+int switch_pre_link[PORT_NO]={0,0,0,0};
-+
-+
-+
-+
-+
-+/*				NOTES
-+ *   The Protocol of the SPI are as follows:
-+ *
-+ *     		   Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
-+ *	byte0     |   Block id  | r/w | sub-block        |
-+ *	byte1     |		Address			 |
-+ *	byte2	  |		Data			 |
-+ *	byte3	  |		Data			 |
-+ *	byte4	  |		Data			 |
-+ *	byte5	  |		Data			 |
-+ */
-+
-+
-+
-+
-+/***************************************/
-+/* define GPIO module base address     */
-+/***************************************/
-+#define GPIO_EECS	     0x80000000		/*   EECS: GPIO[22]   */
-+#define GPIO_MOSI	     0x20000000         /*   EEDO: GPIO[29]   send to 6996*/
-+#define GPIO_MISO	     0x40000000         /*   EEDI: GPIO[30]   receive from 6996*/
-+#define GPIO_EECK	     0x10000000         /*   EECK: GPIO[31]   */
-+
-+/*************************************************************
-+* SPI protocol for ADM6996 control
-+**************************************************************/
-+#define SPI_OP_LEN	     0x08		// the length of start bit and opcode
-+#define SPI_OPWRITE	     0X05		// write
-+#define SPI_OPREAD	     0X06		// read
-+#define SPI_OPERASE	     0X07		// erase
-+#define SPI_OPWTEN	     0X04		// write enable
-+#define SPI_OPWTDIS	     0X04		// write disable
-+#define SPI_OPERSALL	     0X04		// erase all
-+#define SPI_OPWTALL	     0X04		// write all
-+
-+#define SPI_ADD_LEN	     8			// bits of Address
-+#define SPI_DAT_LEN	     32			// bits of Data
-+
-+
-+/****************************************/
-+/*	Function Declare		*/
-+/****************************************/
-+
-+//unsigned int SPI_read_bit(void);
-+//void SPI_write_bit(char bit_EEDO);
-+//unsigned int SPI_read_bit(void);
-+/******************************************
-+* SPI_write
-+* addr -> Write Address
-+* value -> value to be write
-+***************************************** */
-+void phy_receiver_init (unsigned char port_no)
-+{
-+    phy_write(port_no,31,0x2a30);
-+    phy_write_masked(port_no, 12, 0x0200, 0x0300);
-+    phy_write(port_no,31,0);
-+}
-+
-+void phy_write(unsigned char port_no,unsigned char reg,unsigned int val)
-+{
-+	unsigned int cmd;
-+
-+	cmd = (port_no<<21)|(reg<<16)|val;
-+	SPI_write(3,0,1,cmd);
-+}
-+
-+unsigned int phy_read(unsigned char port_no,unsigned char reg)
-+{
-+	unsigned int cmd,reg_val;
-+
-+	cmd = BIT(26)|(port_no<<21)|(reg<<16);
-+	SPI_write(3,0,1,cmd);
-+	msleep(2);
-+	reg_val = SPI_read(3,0,2);
-+	return reg_val;
-+}
-+
-+void phy_write_masked(unsigned char port_no,unsigned char reg,unsigned int val,unsigned int mask)
-+{
-+	unsigned int cmd,reg_val;
-+
-+	cmd = BIT(26)|(port_no<<21)|(reg<<16);	// Read reg_val
-+	SPI_write(3,0,1,cmd);
-+	mdelay(2);
-+	reg_val = SPI_read(3,0,2);
-+	reg_val &= ~mask;			// Clear masked bit
-+	reg_val |= (val&mask) ;			// set masked bit ,if true
-+	cmd = (port_no<<21)|(reg<<16)|reg_val;
-+	SPI_write(3,0,1,cmd);
-+}
-+
-+void init_seq_7385(unsigned char port_no)
-+{
-+	unsigned char rev;
-+
-+	phy_write(port_no, 31, 0x2a30);
-+	phy_write_masked(port_no, 8, 0x0200, 0x0200);
-+	phy_write(port_no, 31, 0x52b5);
-+	phy_write(port_no, 16, 0xb68a);
-+	phy_write_masked(port_no, 18, 0x0003, 0xff07);
-+	phy_write_masked(port_no, 17, 0x00a2, 0x00ff);
-+	phy_write(port_no, 16, 0x968a);
-+	phy_write(port_no, 31, 0x2a30);
-+	phy_write_masked(port_no, 8, 0x0000, 0x0200);
-+	phy_write(port_no, 31, 0x0000); /* Read revision */
-+	rev = phy_read(port_no, 3) & 0x000f;
-+	if (rev == 0)
-+	{
-+		phy_write(port_no, 31, 0x2a30);
-+		phy_write_masked(port_no, 8, 0x0200, 0x0200);
-+		phy_write(port_no, 31, 0x52b5);
-+		phy_write(port_no, 18, 0x0000);
-+		phy_write(port_no, 17, 0x0689);
-+		phy_write(port_no, 16, 0x8f92);
-+		phy_write(port_no, 31, 0x52B5);
-+		phy_write(port_no, 18, 0x0000);
-+		phy_write(port_no, 17, 0x0E35);
-+		phy_write(port_no, 16, 0x9786);
-+		phy_write(port_no, 31, 0x2a30);
-+		phy_write_masked(port_no, 8, 0x0000, 0x0200);
-+		phy_write(port_no, 23, 0xFF80);
-+		phy_write(port_no, 23, 0x0000);
-+	}
-+	phy_write(port_no, 31, 0x0000);
-+	phy_write(port_no, 18, 0x0048);
-+	if (rev == 0)
-+	{
-+		phy_write(port_no, 31, 0x2a30);
-+		phy_write(port_no, 20, 0x6600);
-+		phy_write(port_no, 31, 0x0000);
-+		phy_write(port_no, 24, 0xa24e);
-+	}
-+	else
-+	{
-+		phy_write(port_no, 31, 0x2a30);
-+		phy_write_masked(port_no, 22, 0x0240, 0x0fc0);
-+		phy_write_masked(port_no, 20, 0x4000, 0x6000);
-+		phy_write(port_no, 31, 1);
-+		phy_write_masked(port_no, 20, 0x6000, 0xe000);
-+		phy_write(port_no, 31, 0x0000);
-+	}
-+}
-+
-+int Get_Set_port_status()
-+{
-+	unsigned int    reg_val,ability,rcv_mask,mac_config;
-+	int is_link=0;
-+	int i;
-+
-+ 	rcv_mask = SPI_read(2,0,0x10);			// Receive mask
-+
-+	for(i=0;i<4;i++){
-+		reg_val = phy_read(i,1);
-+		if ((reg_val & 0x0024) == 0x0024) /* link is established and auto_negotiate process completed */
-+		{
-+			is_link=1;
-+			if(switch_pre_link[i]==LINK_DOWN){		// Link Down ==> Link up
-+
-+				rcv_mask |= BIT(i);			// Enable receive
-+
-+				reg_val = phy_read(i,10);
-+				if(reg_val & 0x0c00){
-+					printk("Port%d:Giga mode\n",i);
-+//					SPI_write(1,i,0x00,0x300701B1);
-+					mac_config = 0x00060004|(6<<6);
-+
-+					SPI_write(1,i,0x00,((mac_config & 0xfffffff8) | 1) | 0x20000030);	// reset port
-+					mac_config |= (( BIT(i) << 19) | 0x08000000);
-+					SPI_write(1,i,0x00,mac_config);
-+					SPI_write(1,i,0x04,0x000300ff);		// flow control
-+
-+					reg_val = SPI_read(5,0,0x12);
-+					reg_val &= ~BIT(i);
-+					SPI_write(5,0,0x12,reg_val);
-+
-+					reg_val = SPI_read(1,i,0x00);
-+					reg_val |= 0x10010000;
-+					SPI_write(1,i,0x00,reg_val);
-+//					SPI_write(1,i,0x00,0x10070181);
-+					switch_pre_link[i]=LINK_UP;
-+					switch_pre_speed[i]=GMAC_SPEED_1000;
-+				}
-+				else{
-+					reg_val = phy_read(i,5);
-+					ability = (reg_val&0x5e0) >>5;
-+					if ((ability & 0x0C)) /* 100M */
-+					{
-+//						SPI_write(1,i,0x00,0x30050472);
-+						if((ability&0x08)==0) 		// Half
-+							mac_config = 0x00040004 |(17<<6);
-+						else				// Full
-+							mac_config = 0x00040004 |(17<<6);
-+
-+						SPI_write(1,i,0x00,((mac_config & 0xfffffff8) | 1) | 0x20000030);	// reset port
-+						mac_config |= (( BIT(i) << 19) | 0x08000000);
-+						SPI_write(1,i,0x00,mac_config);
-+						SPI_write(1,i,0x04,0x000300ff);		// flow control
-+
-+						reg_val = SPI_read(5,0,0x12);
-+						reg_val &= ~BIT(i);
-+						SPI_write(5,0,0x12,reg_val);
-+
-+						reg_val = SPI_read(1,i,0x00);
-+						reg_val &= ~0x08000000;
-+						reg_val |= 0x10010000;
-+						SPI_write(1,i,0x00,reg_val);
-+//						SPI_write(1,i,0x00,0x10050442);
-+						printk("Port%d:100M\n",i);
-+						switch_pre_link[i]=LINK_UP;
-+						switch_pre_speed[i]=GMAC_SPEED_100;
-+					}
-+					else if((ability & 0x03)) /* 10M */
-+					{
-+//						SPI_write(1,i,0x00,0x30050473);
-+						if((ability&0x2)==0)		// Half
-+							mac_config = 0x00040004 |(17<<6);
-+						else				// Full
-+							mac_config = 0x00040004 |(17<<6);
-+
-+						SPI_write(1,i,0x00,((mac_config & 0xfffffff8) | 1) | 0x20000030);	// reset port
-+						mac_config |= (( BIT(i) << 19) | 0x08000000);
-+						SPI_write(1,i,0x00,mac_config);
-+						SPI_write(1,i,0x04,0x000300ff);		// flow control
-+
-+						reg_val = SPI_read(5,0,0x12);
-+						reg_val &= ~BIT(i);
-+						SPI_write(5,0,0x12,reg_val);
-+
-+						reg_val = SPI_read(1,i,0x00);
-+						reg_val &= ~0x08000000;
-+						reg_val |= 0x10010000;
-+						SPI_write(1,i,0x00,reg_val);
-+//						SPI_write(1,i,0x00,0x10050443);
-+						printk("Port%d:10M\n",i);
-+						switch_pre_link[i]=LINK_UP;
-+						switch_pre_speed[i]=GMAC_SPEED_10;
-+					}
-+					else{
-+						SPI_write(1,i,0x00,0x20000030);
-+						printk("Port%d:Unknown mode\n",i);
-+						switch_pre_link[i]=LINK_DOWN;
-+						switch_pre_speed[i]=GMAC_SPEED_10;
-+					}
-+				}
-+			}
-+			else{						// Link up ==> Link UP
-+
-+			}
-+		}
-+		else{							// Link Down
-+			if(switch_pre_link[i]==LINK_UP){
-+				printk("Port%d:Link Down\n",i);
-+				//phy_receiver_init(i);
-+				reg_val = SPI_read(1,i,0);
-+				reg_val &= ~BIT(16);
-+				SPI_write(1,i,0x00,reg_val);			// disable RX
-+				SPI_write(5,0,0x0E,BIT(i));			// dicard packet
-+				while((SPI_read(5,0,0x0C)&BIT(i))==0)		// wait to be empty
-+					msleep(1);
-+				SPI_write(1,i,0x00,0x20000030);			// PORT_RST
-+				SPI_write(5,0,0x0E,SPI_read(5,0,0x0E) & ~BIT(i));// accept packet
-+
-+				reg_val = SPI_read(5,0,0x12);
-+				reg_val |= BIT(i);
-+				SPI_write(5,0,0x12,reg_val);
-+			}
-+			switch_pre_link[i]=LINK_DOWN;
-+			rcv_mask &= ~BIT(i);			// disable receive
-+		}
-+	}
-+
-+	SPI_write(2,0,0x10,rcv_mask);			// Receive mask
-+	return is_link;
-+
-+}
-+EXPORT_SYMBOL(Get_Set_port_status);
-+
-+void SPI_write(unsigned char block,unsigned char subblock,unsigned char addr,unsigned int value)
-+{
-+	int     i;
-+	char    bit;
-+	unsigned int data;
-+
-+	SPI_CS_enable(1);
-+
-+	data = (block<<5) | 0x10 | subblock;
-+
-+	//send write command
-+	for(i=SPI_OP_LEN-1;i>=0;i--)
-+	{
-+		bit = (data>>i)& 0x01;
-+		SPI_write_bit(bit);
-+	}
-+
-+	// send 8 bits address (MSB first, LSB last)
-+	for(i=SPI_ADD_LEN-1;i>=0;i--)
-+	{
-+		bit = (addr>>i)& 0x01;
-+		SPI_write_bit(bit);
-+	}
-+	// send 32 bits data (MSB first, LSB last)
-+	for(i=SPI_DAT_LEN-1;i>=0;i--)
-+	{
-+		bit = (value>>i)& 0x01;
-+		SPI_write_bit(bit);
-+	}
-+
-+	SPI_CS_enable(0);	// CS low
-+
-+}
-+
-+
-+/************************************
-+* SPI_write_bit
-+* bit_EEDO -> 1 or 0 to be written
-+************************************/
-+void SPI_write_bit(char bit_EEDO)
-+{
-+	unsigned int addr;
-+	unsigned int value;
-+
-+	addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
-+	value = readl(addr) |GPIO_EECK |GPIO_MOSI ;   /* set EECK/MISO Pin to output */
-+	writel(value,addr);
-+	if(bit_EEDO)
-+	{
-+		addr = (GPIO_BASE_ADDR1 + GPIO_DATA_SET);
-+		writel(GPIO_MOSI,addr); /* set MISO to 1 */
-+
-+	}
-+	else
-+	{
-+		addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
-+		writel(GPIO_MOSI,addr); /* set MISO to 0 */
-+	}
-+	addr = (GPIO_BASE_ADDR1 + GPIO_DATA_SET);
-+	writel(GPIO_EECK,addr); /* set EECK to 1 */
-+	addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
-+	writel(GPIO_EECK,addr); /* set EECK to 0 */
-+
-+	//return ;
-+}
-+
-+/**********************************************************************
-+* read a bit from ADM6996 register
-+***********************************************************************/
-+unsigned int SPI_read_bit(void) // read data from
-+{
-+	unsigned int addr;
-+	unsigned int value;
-+
-+	addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
-+	value = readl(addr) & (~GPIO_MISO);   // set EECK to output and MISO to input
-+	writel(value,addr);
-+
-+	addr =(GPIO_BASE_ADDR1 + GPIO_DATA_SET);
-+	writel(GPIO_EECK,addr); // set EECK to 1
-+
-+
-+	addr = (GPIO_BASE_ADDR1 + GPIO_DATA_IN);
-+	value = readl(addr) ;
-+
-+	addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
-+	writel(GPIO_EECK,addr); // set EECK to 0
-+
-+
-+	value = value >> 30;
-+	return value ;
-+}
-+
-+/******************************************
-+* SPI_default
-+* EEPROM content default value
-+*******************************************/
-+int SPI_default(void)
-+{
-+	int i;
-+	unsigned reg_val,cmd;
-+
-+#if 0
-+	SPI_write(7,0,0x1C,0x01);				// map code space to 0
-+
-+	reg_val = SPI_read(7,0,0x10);
-+	reg_val |= 0x0146;
-+	reg_val &= ~0x0001;
-+	SPI_write(7,0,0x10,reg_val);				// reset iCPU and enable ext_access
-+	SPI_write(7,0,0x11,0x0000);				// start address
-+	for(i=0;i which table to be read: 1/count  0/EEPROM
-+* addr  -> Address to be read
-+* return : Value of the register
-+*************************************************/
-+unsigned int SPI_read(unsigned char block,unsigned char subblock,unsigned char addr)
-+{
-+	int     i;
-+	char    bit;
-+	unsigned int data,value=0;
-+
-+	SPI_CS_enable(1);
-+
-+	data = (block<<5) | subblock;
-+
-+	//send write command
-+	for(i=SPI_OP_LEN-1;i>=0;i--)
-+	{
-+		bit = (data>>i)& 0x01;
-+		SPI_write_bit(bit);
-+	}
-+
-+	// send 8 bits address (MSB first, LSB last)
-+	for(i=SPI_ADD_LEN-1;i>=0;i--)
-+	{
-+		bit = (addr>>i)& 0x01;
-+		SPI_write_bit(bit);
-+	}
-+
-+	// dummy read for chip ready
-+	for(i=0;i<8;i++)
-+		SPI_read_bit();
-+
-+
-+	// read 32 bits data (MSB first, LSB last)
-+	for(i=SPI_DAT_LEN-1;i>=0;i--)
-+	{
-+		bit = SPI_read_bit();
-+		value |= bit<
-+
-+#define SL351x_GMAC_WORKAROUND		1
-+
-+#undef BIG_ENDIAN
-+#define BIG_ENDIAN  				0
-+#define GMAC_DEBUG      			1
-+#define GMAC_NUM					2
-+//#define	L2_jumbo_frame				1
-+
-+#define _PACKED_					__attribute__ ((aligned(1), packed))
-+
-+#ifndef BIT
-+#define BIT(x)						(1 << (x))
-+#endif
-+
-+#define REG32(addr)     			(*(volatile unsigned long  * const)(addr))
-+
-+#define DMA_MALLOC(size,handle)		pci_alloc_consistent(NULL,size,handle)
-+#define DMA_MFREE(mem,size,handle)	pci_free_consistent(NULL,size,mem,handle)
-+
-+// Define frame size
-+#define ETHER_ADDR_LEN				6
-+#define GMAC_MAX_ETH_FRAME_SIZE		1514
-+#define GMAC_TX_BUF_SIZE			((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
-+#define MAX_ISR_WORK        		20
-+
-+#ifdef	L2_jumbo_frame
-+#define SW_RX_BUF_SIZE				9234	// 2048 ,9234
-+#else
-+#define SW_RX_BUF_SIZE				1536	// 2048
-+#endif
-+
-+#define HW_RX_BUF_SIZE				1536	// 2048
-+
-+#define GMAC_DEV_TX_TIMEOUT  		(10*HZ)			//add by CH
-+#define	SKB_RESERVE_BYTES			16
-+
-+/**********************************************************************
-+ * Base Register
-+ **********************************************************************/
-+#define TOE_BASE					(IO_ADDRESS(SL2312_TOE_BASE))
-+#define GMAC_GLOBAL_BASE_ADDR       (IO_ADDRESS(SL2312_GLOBAL_BASE))
-+
-+#define TOE_GLOBAL_BASE				(TOE_BASE + 0x0000)
-+#define TOE_NONTOE_QUE_HDR_BASE		(TOE_BASE + 0x2000)
-+#define TOE_TOE_QUE_HDR_BASE		(TOE_BASE + 0x3000)
-+#define TOE_V_BIT_BASE				(TOE_BASE + 0x4000)
-+#define TOE_A_BIT_BASE				(TOE_BASE + 0x6000)
-+#define TOE_GMAC0_DMA_BASE			(TOE_BASE + 0x8000)
-+#define TOE_GMAC0_BASE				(TOE_BASE + 0xA000)
-+#define TOE_GMAC1_DMA_BASE			(TOE_BASE + 0xC000)
-+#define TOE_GMAC1_BASE				(TOE_BASE + 0xE000)
-+
-+/**********************************************************************
-+ * Queue ID
-+ **********************************************************************/
-+#define TOE_SW_FREE_QID				0x00
-+#define TOE_HW_FREE_QID				0x01
-+#define TOE_GMAC0_SW_TXQ0_QID		0x02
-+#define TOE_GMAC0_SW_TXQ1_QID		0x03
-+#define TOE_GMAC0_SW_TXQ2_QID		0x04
-+#define TOE_GMAC0_SW_TXQ3_QID		0x05
-+#define TOE_GMAC0_SW_TXQ4_QID		0x06
-+#define TOE_GMAC0_SW_TXQ5_QID		0x07
-+#define TOE_GMAC0_HW_TXQ0_QID		0x08
-+#define TOE_GMAC0_HW_TXQ1_QID		0x09
-+#define TOE_GMAC0_HW_TXQ2_QID		0x0A
-+#define TOE_GMAC0_HW_TXQ3_QID		0x0B
-+#define TOE_GMAC1_SW_TXQ0_QID		0x12
-+#define TOE_GMAC1_SW_TXQ1_QID		0x13
-+#define TOE_GMAC1_SW_TXQ2_QID		0x14
-+#define TOE_GMAC1_SW_TXQ3_QID		0x15
-+#define TOE_GMAC1_SW_TXQ4_QID		0x16
-+#define TOE_GMAC1_SW_TXQ5_QID		0x17
-+#define TOE_GMAC1_HW_TXQ0_QID		0x18
-+#define TOE_GMAC1_HW_TXQ1_QID		0x19
-+#define TOE_GMAC1_HW_TXQ2_QID		0x1A
-+#define TOE_GMAC1_HW_TXQ3_QID		0x1B
-+#define TOE_GMAC0_DEFAULT_QID		0x20
-+#define TOE_GMAC1_DEFAULT_QID		0x21
-+#define TOE_CLASSIFICATION_QID(x)	(0x22 + x)	// 0x22 ~ 0x2F
-+#define TOE_TOE_QID(x)				(0x40 + x)	// 0x40 ~ 0x7F
-+
-+/**********************************************************************
-+ * TOE DMA Queue Number should be 2^n, n = 6...12
-+ * TOE DMA Queues are the following queue types:
-+ *		SW Free Queue, HW Free Queue,
-+ *		GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
-+ * They have same descriptor numbers.
-+ * The base address and descriptor number are configured at
-+ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
-+ **********************************************************************/
-+#define TOE_SW_FREEQ_DESC_POWER		10
-+#define TOE_SW_FREEQ_DESC_NUM		(1<y) ? x :y)
-+#define TX_DESC_NUM					_max(TOE_GMAC0_SWTXQ_DESC_NUM, TOE_GMAC1_SWTXQ_DESC_NUM)
-+
-+#define RWPTR_ADVANCE_ONE(x, max)	((x == (max -1)) ? 0 : x+1)
-+#define RWPTR_RECEDE_ONE(x, max)	((x == 0) ? (max -1) : x-1)
-+#define SET_WPTR(addr, data)		(*(volatile u16 * const)((u32)(addr)+2) = (u16)data)
-+#define SET_RPTR(addr, data)		(*(volatile u16 * const)((u32)(addr)) = (u16)data)
-+
-+/**********************************************************************
-+ * Global registers
-+ * #define TOE_GLOBAL_BASE			(TOE_BASE + 0x0000)
-+ * Base 0x60000000
-+ **********************************************************************/
-+#define GLOBAL_TOE_VERSION_REG			0x0000
-+#define GLOBAL_SW_FREEQ_BASE_SIZE_REG	0x0004
-+#define GLOBAL_HW_FREEQ_BASE_SIZE_REG	0x0008
-+#define GLOBAL_DMA_SKB_SIZE_REG			0x0010
-+#define GLOBAL_SWFQ_RWPTR_REG			0x0014
-+#define GLOBAL_HWFQ_RWPTR_REG			0x0018
-+#define GLOBAL_INTERRUPT_STATUS_0_REG	0x0020
-+#define GLOBAL_INTERRUPT_ENABLE_0_REG	0x0024
-+#define GLOBAL_INTERRUPT_SELECT_0_REG	0x0028
-+#define GLOBAL_INTERRUPT_STATUS_1_REG	0x0030
-+#define GLOBAL_INTERRUPT_ENABLE_1_REG	0x0034
-+#define GLOBAL_INTERRUPT_SELECT_1_REG	0x0038
-+#define GLOBAL_INTERRUPT_STATUS_2_REG	0x0040
-+#define GLOBAL_INTERRUPT_ENABLE_2_REG	0x0044
-+#define GLOBAL_INTERRUPT_SELECT_2_REG	0x0048
-+#define GLOBAL_INTERRUPT_STATUS_3_REG	0x0050
-+#define GLOBAL_INTERRUPT_ENABLE_3_REG	0x0054
-+#define GLOBAL_INTERRUPT_SELECT_3_REG	0x0058
-+#define GLOBAL_INTERRUPT_STATUS_4_REG	0x0060
-+#define GLOBAL_INTERRUPT_ENABLE_4_REG	0x0064
-+#define GLOBAL_INTERRUPT_SELECT_4_REG	0x0068
-+#define GLOBAL_HASH_TABLE_BASE_REG		0x006C
-+#define GLOBAL_QUEUE_THRESHOLD_REG		0x0070
-+
-+/**********************************************************************
-+ * GMAC 0/1 DMA/TOE register
-+ * #define TOE_GMAC0_DMA_BASE		(TOE_BASE + 0x8000)
-+ * #define TOE_GMAC1_DMA_BASE		(TOE_BASE + 0xC000)
-+ * Base 0x60008000 or 0x6000C000
-+ **********************************************************************/
-+#define GMAC_DMA_CTRL_REG				0x0000
-+#define GMAC_TX_WEIGHTING_CTRL_0_REG	0x0004
-+#define GMAC_TX_WEIGHTING_CTRL_1_REG	0x0008
-+#define GMAC_SW_TX_QUEUE0_PTR_REG		0x000C
-+#define GMAC_SW_TX_QUEUE1_PTR_REG		0x0010
-+#define GMAC_SW_TX_QUEUE2_PTR_REG		0x0014
-+#define GMAC_SW_TX_QUEUE3_PTR_REG		0x0018
-+#define GMAC_SW_TX_QUEUE4_PTR_REG		0x001C
-+#define GMAC_SW_TX_QUEUE5_PTR_REG		0x0020
-+#define GMAC_HW_TX_QUEUE0_PTR_REG		0x0024
-+#define GMAC_HW_TX_QUEUE1_PTR_REG		0x0028
-+#define GMAC_HW_TX_QUEUE2_PTR_REG		0x002C
-+#define GMAC_HW_TX_QUEUE3_PTR_REG		0x0030
-+#define GMAC_DMA_TX_FIRST_DESC_REG		0x0038
-+#define GMAC_DMA_TX_CURR_DESC_REG		0x003C
-+#define GMAC_DMA_TX_DESC_WORD0_REG		0x0040
-+#define GMAC_DMA_TX_DESC_WORD1_REG		0x0044
-+#define GMAC_DMA_TX_DESC_WORD2_REG		0x0048
-+#define GMAC_DMA_TX_DESC_WORD3_REG		0x004C
-+#define GMAC_SW_TX_QUEUE_BASE_REG		0x0050
-+#define GMAC_HW_TX_QUEUE_BASE_REG		0x0054
-+#define GMAC_DMA_RX_FIRST_DESC_REG		0x0058
-+#define GMAC_DMA_RX_CURR_DESC_REG		0x005C
-+#define GMAC_DMA_RX_DESC_WORD0_REG		0x0060
-+#define GMAC_DMA_RX_DESC_WORD1_REG		0x0064
-+#define GMAC_DMA_RX_DESC_WORD2_REG		0x0068
-+#define GMAC_DMA_RX_DESC_WORD3_REG		0x006C
-+#define GMAC_HASH_ENGINE_REG0			0x0070
-+#define GMAC_HASH_ENGINE_REG1			0x0074
-+#define GMAC_MR0CR0						0x0078 	// matching rule 0 Control register 0
-+#define GMAC_MR0CR1						0x007C	// matching rule 0 Control register 1
-+#define GMAC_MR0CR2						0x0080	// matching rule 0 Control register 2
-+#define GMAC_MR1CR0						0x0084	// matching rule 1 Control register 0
-+#define GMAC_MR1CR1						0x0088	// matching rule 1 Control register 1
-+#define GMAC_MR1CR2						0x008C	// matching rule 1 Control register 2
-+#define GMAC_MR2CR0						0x0090	// matching rule 2 Control register 0
-+#define GMAC_MR2CR1						0x0094	// matching rule 2 Control register 1
-+#define GMAC_MR2CR2						0x0098	// matching rule 2 Control register 2
-+#define GMAC_MR3CR0						0x009C	// matching rule 3 Control register 0
-+#define GMAC_MR3CR1						0x00A0	// matching rule 3 Control register 1
-+#define GMAC_MR3CR2						0x00A4	// matching rule 3 Control register 2
-+#define GMAC_SPR0						0x00A8	// Support Protocol Regsister 0
-+#define GMAC_SPR1						0x00AC	// Support Protocol Regsister 1
-+#define GMAC_SPR2						0x00B0	// Support Protocol Regsister 2
-+#define GMAC_SPR3						0x00B4	// Support Protocol Regsister 3
-+#define GMAC_SPR4						0x00B8	// Support Protocol Regsister 4
-+#define GMAC_SPR5						0x00BC	// Support Protocol Regsister 5
-+#define GMAC_SPR6						0x00C0	// Support Protocol Regsister 6
-+#define GMAC_SPR7						0x00C4	// Support Protocol Regsister 7
-+#define GMAC_AHB_WEIGHT_REG				0x00C8	// GMAC Hash/Rx/Tx AHB Weighting register
-+
-+/**********************************************************************
-+ * TOE GMAC 0/1 register
-+ * #define TOE_GMAC0_BASE				(TOE_BASE + 0xA000)
-+ * #define TOE_GMAC1_BASE				(TOE_BASE + 0xE000)
-+ * Base 0x6000A000 or 0x6000E000
-+ **********************************************************************/
-+enum GMAC_REGISTER {
-+	GMAC_STA_ADD0 	= 0x0000,
-+	GMAC_STA_ADD1	= 0x0004,
-+	GMAC_STA_ADD2	= 0x0008,
-+	GMAC_RX_FLTR	= 0x000c,
-+	GMAC_MCAST_FIL0 = 0x0010,
-+	GMAC_MCAST_FIL1 = 0x0014,
-+	GMAC_CONFIG0	= 0x0018,
-+	GMAC_CONFIG1	= 0x001c,
-+	GMAC_CONFIG2	= 0x0020,
-+	GMAC_CONFIG3	= 0x0024,
-+	GMAC_RESERVED	= 0x0028,
-+	GMAC_STATUS		= 0x002c,
-+	GMAC_IN_DISCARDS= 0x0030,
-+	GMAC_IN_ERRORS  = 0x0034,
-+	GMAC_IN_MCAST   = 0x0038,
-+	GMAC_IN_BCAST   = 0x003c,
-+	GMAC_IN_MAC1    = 0x0040,	// for STA 1 MAC Address
-+	GMAC_IN_MAC2    = 0x0044	// for STA 2 MAC Address
-+};
-+/**********************************************************************
-+ * TOE version Register (offset 0x0000)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int reserved		: 15;	// bit 31:17
-+		unsigned int v_bit_mode		: 1;	// bit 16		1: 128-entry
-+		unsigned int device_id		: 12;	// bit 15:4 	Device ID
-+		unsigned int revision_id	: 4;	// bit  3:0 	Revision ID
-+#else
-+		unsigned int revision_id	: 4;	// bit  3:0 	Revision ID
-+		unsigned int device_id		: 12;	// bit 15:4 	Device ID
-+		unsigned int v_bit_mode		: 1;	// bit 16		1: 128-entry
-+		unsigned int reserved		: 15;	// bit 31:17
-+#endif
-+	} bits;
-+} TOE_VERSION_T;
-+
-+
-+/**********************************************************************
-+ * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	unsigned int base_size;
-+} DMA_Q_BASE_SIZE_T;
-+#define DMA_Q_BASE_MASK 	(~0x0f)
-+
-+/**********************************************************************
-+ * DMA SKB Buffer register (offset 0x0008)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_0008
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int hw_skb_size	: 16;	// bit 31:16	HW Free poll SKB Size
-+		unsigned int sw_skb_size	: 16;	// bit 15:0 	SW Free poll SKB Size
-+#else
-+		unsigned int sw_skb_size	: 16;	// bit 15:0 	SW Free poll SKB Size
-+		unsigned int hw_skb_size	: 16;	// bit 31:16	HW Free poll SKB Size
-+#endif
-+	} bits;
-+} DMA_SKB_SIZE_T;
-+
-+/**********************************************************************
-+ * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_000c
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int wptr			: 16;	// bit 31:16 	Write Ptr, RW
-+		unsigned int rptr			: 16;	// bit 15:0		Read Ptr, RO
-+#else
-+		unsigned int rptr			: 16;	// bit 15:0		Read Ptr, RO
-+		unsigned int wptr			: 16;	// bit 31:16 	Write Ptr, RW
-+#endif
-+	} bits;
-+} DMA_RWPTR_T;
-+
-+/**********************************************************************
-+ * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
-+ **********************************************************************/
-+// see DMA_RWPTR_T structure
-+
-+/**********************************************************************
-+ * Interrupt Status Register 0 	(offset 0x0020)
-+ * Interrupt Mask Register 0 	(offset 0x0024)
-+ * Interrupt Select Register 0 	(offset 0x0028)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_0020
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int txDerr1		: 1;	// bit 31	GMAC1 AHB Bus Error while Tx
-+		unsigned int txPerr1		: 1;	// bit 30	GMAC1 Tx Descriptor Protocol Error
-+		unsigned int txDerr0		: 1;	// bit 29	GMAC0 AHB Bus Error while Tx
-+		unsigned int txPerr0		: 1;	// bit 28	GMAC0 Tx Descriptor Protocol Error
-+		unsigned int rxDerr1		: 1;	// bit 27	GMAC1 AHB Bus Error while Rx
-+		unsigned int rxPerr1		: 1;	// bit 26	GMAC1 Rx Descriptor Protocol Error
-+		unsigned int rxDerr0		: 1;	// bit 25	GMAC0 AHB Bus Error while Rx
-+		unsigned int rxPerr0		: 1;	// bit 24	GMAC0 Rx Descriptor Protocol Error
-+		unsigned int swtq15_fin		: 1;	// bit 23	GMAC1 SW Tx Queue 5 Finish Interrupt
-+		unsigned int swtq14_fin		: 1;	// bit 22	GMAC1 SW Tx Queue 4 Finish Interrupt
-+		unsigned int swtq13_fin		: 1;	// bit 21	GMAC1 SW Tx Queue 3 Finish Interrupt
-+		unsigned int swtq12_fin		: 1;	// bit 20	GMAC1 SW Tx Queue 2 Finish Interrupt
-+		unsigned int swtq11_fin		: 1;	// bit 19	GMAC1 SW Tx Queue 1 Finish Interrupt
-+		unsigned int swtq10_fin		: 1;	// bit 18	GMAC1 SW Tx Queue 0 Finish Interrupt
-+		unsigned int swtq05_fin		: 1;	// bit 17	GMAC0 SW Tx Queue 5 Finish Interrupt
-+		unsigned int swtq04_fin		: 1;	// bit 16	GMAC0 SW Tx Queue 4 Finish Interrupt
-+		unsigned int swtq03_fin		: 1;	// bit 15	GMAC0 SW Tx Queue 3 Finish Interrupt
-+		unsigned int swtq02_fin		: 1;	// bit 14	GMAC0 SW Tx Queue 2 Finish Interrupt
-+		unsigned int swtq01_fin		: 1;	// bit 13	GMAC0 SW Tx Queue 1 Finish Interrupt
-+		unsigned int swtq00_fin		: 1;	// bit 12	GMAC0 SW Tx Queue 0 Finish Interrupt
-+		unsigned int swtq15_eof		: 1;	// bit 11	GMAC1 SW Tx Queue 5 EOF Interrupt
-+		unsigned int swtq14_eof		: 1;	// bit 10	GMAC1 SW Tx Queue 4 EOF Interrupt
-+		unsigned int swtq13_eof		: 1;	// bit 9	GMAC1 SW Tx Queue 3 EOF Interrupt
-+		unsigned int swtq12_eof		: 1;	// bit 8	GMAC1 SW Tx Queue 2 EOF Interrupt
-+		unsigned int swtq11_eof		: 1;	// bit 7	GMAC1 SW Tx Queue 1 EOF Interrupt
-+		unsigned int swtq10_eof		: 1;	// bit 6	GMAC1 SW Tx Queue 0 EOF Interrupt
-+		unsigned int swtq05_eof		: 1;	// bit 5	GMAC0 SW Tx Queue 5 EOF Interrupt
-+		unsigned int swtq04_eof		: 1;	// bit 4	GMAC0 SW Tx Queue 4 EOF Interrupt
-+		unsigned int swtq03_eof		: 1;	// bit 3	GMAC0 SW Tx Queue 3 EOF Interrupt
-+		unsigned int swtq02_eof		: 1;	// bit 2	GMAC0 SW Tx Queue 2 EOF Interrupt
-+		unsigned int swtq01_eof		: 1;	// bit 1	GMAC0 SW Tx Queue 1 EOF Interrupt
-+		unsigned int swtq00_eof		: 1;	// bit 0	GMAC0 SW Tx Queue 0 EOF Interrupt
-+#else
-+		unsigned int swtq00_eof		: 1;	// bit 0	GMAC0 SW Tx Queue 0 EOF Interrupt
-+		unsigned int swtq01_eof		: 1;	// bit 1	GMAC0 SW Tx Queue 1 EOF Interrupt
-+		unsigned int swtq02_eof		: 1;	// bit 2	GMAC0 SW Tx Queue 2 EOF Interrupt
-+		unsigned int swtq03_eof		: 1;	// bit 3	GMAC0 SW Tx Queue 3 EOF Interrupt
-+		unsigned int swtq04_eof		: 1;	// bit 4	GMAC0 SW Tx Queue 4 EOF Interrupt
-+		unsigned int swtq05_eof		: 1;	// bit 5	GMAC0 SW Tx Queue 5 EOF Interrupt
-+		unsigned int swtq10_eof		: 1;	// bit 6	GMAC1 SW Tx Queue 0 EOF Interrupt
-+		unsigned int swtq11_eof		: 1;	// bit 7	GMAC1 SW Tx Queue 1 EOF Interrupt
-+		unsigned int swtq12_eof		: 1;	// bit 8	GMAC1 SW Tx Queue 2 EOF Interrupt
-+		unsigned int swtq13_eof		: 1;	// bit 9	GMAC1 SW Tx Queue 3 EOF Interrupt
-+		unsigned int swtq14_eof		: 1;	// bit 10	GMAC1 SW Tx Queue 4 EOF Interrupt
-+		unsigned int swtq15_eof		: 1;	// bit 11	GMAC1 SW Tx Queue 5 EOF Interrupt
-+		unsigned int swtq00_fin		: 1;	// bit 12	GMAC0 SW Tx Queue 0 Finish Interrupt
-+		unsigned int swtq01_fin		: 1;	// bit 13	GMAC0 SW Tx Queue 1 Finish Interrupt
-+		unsigned int swtq02_fin		: 1;	// bit 14	GMAC0 SW Tx Queue 2 Finish Interrupt
-+		unsigned int swtq03_fin		: 1;	// bit 15	GMAC0 SW Tx Queue 3 Finish Interrupt
-+		unsigned int swtq04_fin		: 1;	// bit 16	GMAC0 SW Tx Queue 4 Finish Interrupt
-+		unsigned int swtq05_fin		: 1;	// bit 17	GMAC0 SW Tx Queue 5 Finish Interrupt
-+		unsigned int swtq10_fin		: 1;	// bit 18	GMAC1 SW Tx Queue 0 Finish Interrupt
-+		unsigned int swtq11_fin		: 1;	// bit 19	GMAC1 SW Tx Queue 1 Finish Interrupt
-+		unsigned int swtq12_fin		: 1;	// bit 20	GMAC1 SW Tx Queue 2 Finish Interrupt
-+		unsigned int swtq13_fin		: 1;	// bit 21	GMAC1 SW Tx Queue 3 Finish Interrupt
-+		unsigned int swtq14_fin		: 1;	// bit 22	GMAC1 SW Tx Queue 4 Finish Interrupt
-+		unsigned int swtq15_fin		: 1;	// bit 23	GMAC1 SW Tx Queue 5 Finish Interrupt
-+		unsigned int rxPerr0		: 1;	// bit 24	GMAC0 Rx Descriptor Protocol Error
-+		unsigned int rxDerr0		: 1;	// bit 25	GMAC0 AHB Bus Error while Rx
-+		unsigned int rxPerr1		: 1;	// bit 26	GMAC1 Rx Descriptor Protocol Error
-+		unsigned int rxDerr1		: 1;	// bit 27	GMAC1 AHB Bus Error while Rx
-+		unsigned int txPerr0		: 1;	// bit 28	GMAC0 Tx Descriptor Protocol Error
-+		unsigned int txDerr0		: 1;	// bit 29	GMAC0 AHB Bus Error while Tx
-+		unsigned int txPerr1		: 1;	// bit 30	GMAC1 Tx Descriptor Protocol Error
-+		unsigned int txDerr1		: 1;	// bit 31	GMAC1 AHB Bus Error while Tx
-+#endif
-+	} bits;
-+} INTR_REG0_T;
-+
-+#define GMAC1_TXDERR_INT_BIT		BIT(31)
-+#define GMAC1_TXPERR_INT_BIT		BIT(30)
-+#define GMAC0_TXDERR_INT_BIT		BIT(29)
-+#define GMAC0_TXPERR_INT_BIT		BIT(28)
-+#define GMAC1_RXDERR_INT_BIT		BIT(27)
-+#define GMAC1_RXPERR_INT_BIT		BIT(26)
-+#define GMAC0_RXDERR_INT_BIT		BIT(25)
-+#define GMAC0_RXPERR_INT_BIT		BIT(24)
-+#define GMAC1_SWTQ15_FIN_INT_BIT	BIT(23)
-+#define GMAC1_SWTQ14_FIN_INT_BIT	BIT(22)
-+#define GMAC1_SWTQ13_FIN_INT_BIT	BIT(21)
-+#define GMAC1_SWTQ12_FIN_INT_BIT	BIT(20)
-+#define GMAC1_SWTQ11_FIN_INT_BIT	BIT(19)
-+#define GMAC1_SWTQ10_FIN_INT_BIT	BIT(18)
-+#define GMAC0_SWTQ05_FIN_INT_BIT	BIT(17)
-+#define GMAC0_SWTQ04_FIN_INT_BIT	BIT(16)
-+#define GMAC0_SWTQ03_FIN_INT_BIT	BIT(15)
-+#define GMAC0_SWTQ02_FIN_INT_BIT	BIT(14)
-+#define GMAC0_SWTQ01_FIN_INT_BIT	BIT(13)
-+#define GMAC0_SWTQ00_FIN_INT_BIT	BIT(12)
-+#define GMAC1_SWTQ15_EOF_INT_BIT	BIT(11)
-+#define GMAC1_SWTQ14_EOF_INT_BIT	BIT(10)
-+#define GMAC1_SWTQ13_EOF_INT_BIT	BIT(9)
-+#define GMAC1_SWTQ12_EOF_INT_BIT	BIT(8)
-+#define GMAC1_SWTQ11_EOF_INT_BIT	BIT(7)
-+#define GMAC1_SWTQ10_EOF_INT_BIT	BIT(6)
-+#define GMAC0_SWTQ05_EOF_INT_BIT	BIT(5)
-+#define GMAC0_SWTQ04_EOF_INT_BIT	BIT(4)
-+#define GMAC0_SWTQ03_EOF_INT_BIT	BIT(3)
-+#define GMAC0_SWTQ02_EOF_INT_BIT	BIT(2)
-+#define GMAC0_SWTQ01_EOF_INT_BIT	BIT(1)
-+#define GMAC0_SWTQ00_EOF_INT_BIT	BIT(0)
-+
-+
-+/**********************************************************************
-+ * Interrupt Status Register 1 	(offset 0x0030)
-+ * Interrupt Mask Register 1 	(offset 0x0034)
-+ * Interrupt Select Register 1 	(offset 0x0038)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_0030
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int toe_iq3_full	: 1;	// bit 31	TOE Interrupt Queue 3 Full Interrupt
-+		unsigned int toe_iq2_full	: 1;	// bit 30	TOE Interrupt Queue 2 Full Interrupt
-+		unsigned int toe_iq1_full	: 1;	// bit 29	TOE Interrupt Queue 1 Full Interrupt
-+		unsigned int toe_iq0_full	: 1;	// bit 28	TOE Interrupt Queue 0 Full Interrupt
-+		unsigned int toe_iq3_intr	: 1;	// bit 27	TOE Interrupt Queue 3 with Interrupts
-+		unsigned int toe_iq2_intr	: 1;	// bit 26	TOE Interrupt Queue 2 with Interrupts
-+		unsigned int toe_iq1_intr	: 1;	// bit 25	TOE Interrupt Queue 1 with Interrupts
-+		unsigned int toe_iq0_intr	: 1;	// bit 24	TOE Interrupt Queue 0 with Interrupts
-+		unsigned int hwtq13_eof		: 1;	// bit 23	GMAC1 HW Tx Queue3 EOF Interrupt
-+		unsigned int hwtq12_eof		: 1;	// bit 22	GMAC1 HW Tx Queue2 EOF Interrupt
-+		unsigned int hwtq11_eof		: 1;	// bit 21	GMAC1 HW Tx Queue1 EOF Interrupt
-+		unsigned int hwtq10_eof		: 1;	// bit 20	GMAC1 HW Tx Queue0 EOF Interrupt
-+		unsigned int hwtq03_eof		: 1;	// bit 19	GMAC0 HW Tx Queue3 EOF Interrupt
-+		unsigned int hwtq02_eof		: 1;	// bit 18	GMAC0 HW Tx Queue2 EOF Interrupt
-+		unsigned int hwtq01_eof		: 1;	// bit 17	GMAC0 HW Tx Queue1 EOF Interrupt
-+		unsigned int hwtq00_eof		: 1;	// bit 16	GMAC0 HW Tx Queue0 EOF Interrupt
-+		unsigned int class_rx		: 14;	// bit 15:2	Classification Queue Rx Interrupt
-+		unsigned int default_q1_eof	: 1;	// bit 1	Default Queue 1 EOF Interrupt
-+		unsigned int default_q0_eof	: 1;	// bit 0	Default Queue 0 EOF Interrupt
-+#else
-+		unsigned int default_q0_eof	: 1;	// bit 0	Default Queue 0 EOF Interrupt
-+		unsigned int default_q1_eof	: 1;	// bit 1	Default Queue 1 EOF Interrupt
-+		unsigned int class_rx		: 14;	// bit 15:2	Classification Queue Rx Interrupt
-+		unsigned int hwtq00_eof		: 1;	// bit 16	GMAC0 HW Tx Queue0 EOF Interrupt
-+		unsigned int hwtq01_eof		: 1;	// bit 17	GMAC0 HW Tx Queue1 EOF Interrupt
-+		unsigned int hwtq02_eof		: 1;	// bit 18	GMAC0 HW Tx Queue2 EOF Interrupt
-+		unsigned int hwtq03_eof		: 1;	// bit 19	GMAC0 HW Tx Queue3 EOF Interrupt
-+		unsigned int hwtq10_eof		: 1;	// bit 20	GMAC1 HW Tx Queue0 EOF Interrupt
-+		unsigned int hwtq11_eof		: 1;	// bit 21	GMAC1 HW Tx Queue1 EOF Interrupt
-+		unsigned int hwtq12_eof		: 1;	// bit 22	GMAC1 HW Tx Queue2 EOF Interrupt
-+		unsigned int hwtq13_eof		: 1;	// bit 23	GMAC1 HW Tx Queue3 EOF Interrupt
-+		unsigned int toe_iq0_intr	: 1;	// bit 24	TOE Interrupt Queue 0 with Interrupts
-+		unsigned int toe_iq1_intr	: 1;	// bit 25	TOE Interrupt Queue 1 with Interrupts
-+		unsigned int toe_iq2_intr	: 1;	// bit 26	TOE Interrupt Queue 2 with Interrupts
-+		unsigned int toe_iq3_intr	: 1;	// bit 27	TOE Interrupt Queue 3 with Interrupts
-+		unsigned int toe_iq0_full	: 1;	// bit 28	TOE Interrupt Queue 0 Full Interrupt
-+		unsigned int toe_iq1_full	: 1;	// bit 29	TOE Interrupt Queue 1 Full Interrupt
-+		unsigned int toe_iq2_full	: 1;	// bit 30	TOE Interrupt Queue 2 Full Interrupt
-+		unsigned int toe_iq3_full	: 1;	// bit 31	TOE Interrupt Queue 3 Full Interrupt
-+#endif
-+	} bits;
-+} INTR_REG1_T;
-+
-+#define TOE_IQ3_FULL_INT_BIT		BIT(31)
-+#define TOE_IQ2_FULL_INT_BIT		BIT(30)
-+#define TOE_IQ1_FULL_INT_BIT		BIT(29)
-+#define TOE_IQ0_FULL_INT_BIT		BIT(28)
-+#define TOE_IQ3_INT_BIT				BIT(27)
-+#define TOE_IQ2_INT_BIT				BIT(26)
-+#define TOE_IQ1_INT_BIT				BIT(25)
-+#define TOE_IQ0_INT_BIT				BIT(24)
-+#define GMAC1_HWTQ13_EOF_INT_BIT	BIT(23)
-+#define GMAC1_HWTQ12_EOF_INT_BIT	BIT(22)
-+#define GMAC1_HWTQ11_EOF_INT_BIT	BIT(21)
-+#define GMAC1_HWTQ10_EOF_INT_BIT	BIT(20)
-+#define GMAC0_HWTQ03_EOF_INT_BIT	BIT(19)
-+#define GMAC0_HWTQ02_EOF_INT_BIT	BIT(18)
-+#define GMAC0_HWTQ01_EOF_INT_BIT	BIT(17)
-+#define GMAC0_HWTQ00_EOF_INT_BIT	BIT(16)
-+#define CLASS_RX_INT_BIT(x)			BIT((x+2))
-+#define DEFAULT_Q1_INT_BIT			BIT(1)
-+#define DEFAULT_Q0_INT_BIT			BIT(0)
-+
-+#define TOE_IQ_INT_BITS				(TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
-+		               	 			TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
-+#define	TOE_IQ_FULL_BITS			(TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
-+		                	 		TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
-+#define	TOE_IQ_ALL_BITS				(TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
-+#define TOE_CLASS_RX_INT_BITS		0xfffc
-+
-+/**********************************************************************
-+ * Interrupt Status Register 2 	(offset 0x0040)
-+ * Interrupt Mask Register 2 	(offset 0x0044)
-+ * Interrupt Select Register 2 	(offset 0x0048)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_0040
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int toe_q31_full	: 1;	// bit 31	TOE Queue 31 Full Interrupt
-+		unsigned int toe_q30_full	: 1;	// bit 30	TOE Queue 30 Full Interrupt
-+		unsigned int toe_q29_full	: 1;	// bit 29	TOE Queue 29 Full Interrupt
-+		unsigned int toe_q28_full	: 1;	// bit 28	TOE Queue 28 Full Interrupt
-+		unsigned int toe_q27_full	: 1;	// bit 27	TOE Queue 27 Full Interrupt
-+		unsigned int toe_q26_full	: 1;	// bit 26	TOE Queue 26 Full Interrupt
-+		unsigned int toe_q25_full	: 1;	// bit 25	TOE Queue 25 Full Interrupt
-+		unsigned int toe_q24_full	: 1;	// bit 24	TOE Queue 24 Full Interrupt
-+		unsigned int toe_q23_full	: 1;	// bit 23	TOE Queue 23 Full Interrupt
-+		unsigned int toe_q22_full	: 1;	// bit 22	TOE Queue 22 Full Interrupt
-+		unsigned int toe_q21_full	: 1;	// bit 21	TOE Queue 21 Full Interrupt
-+		unsigned int toe_q20_full	: 1;	// bit 20	TOE Queue 20 Full Interrupt
-+		unsigned int toe_q19_full	: 1;	// bit 19	TOE Queue 19 Full Interrupt
-+		unsigned int toe_q18_full	: 1;	// bit 18	TOE Queue 18 Full Interrupt
-+		unsigned int toe_q17_full	: 1;	// bit 17	TOE Queue 17 Full Interrupt
-+		unsigned int toe_q16_full	: 1;	// bit 16	TOE Queue 16 Full Interrupt
-+		unsigned int toe_q15_full	: 1;	// bit 15	TOE Queue 15 Full Interrupt
-+		unsigned int toe_q14_full	: 1;	// bit 14	TOE Queue 14 Full Interrupt
-+		unsigned int toe_q13_full	: 1;	// bit 13	TOE Queue 13 Full Interrupt
-+		unsigned int toe_q12_full	: 1;	// bit 12	TOE Queue 12 Full Interrupt
-+		unsigned int toe_q11_full	: 1;	// bit 11	TOE Queue 11 Full Interrupt
-+		unsigned int toe_q10_full	: 1;	// bit 10	TOE Queue 10 Full Interrupt
-+		unsigned int toe_q9_full	: 1;	// bit 9	TOE Queue 9 Full Interrupt
-+		unsigned int toe_q8_full	: 1;	// bit 8	TOE Queue 8 Full Interrupt
-+		unsigned int toe_q7_full	: 1;	// bit 7	TOE Queue 7 Full Interrupt
-+		unsigned int toe_q6_full	: 1;	// bit 6	TOE Queue 6 Full Interrupt
-+		unsigned int toe_q5_full	: 1;	// bit 5	TOE Queue 5 Full Interrupt
-+		unsigned int toe_q4_full	: 1;	// bit 4	TOE Queue 4 Full Interrupt
-+		unsigned int toe_q3_full	: 1;	// bit 3	TOE Queue 3 Full Interrupt
-+		unsigned int toe_q2_full	: 1;	// bit 2	TOE Queue 2 Full Interrupt
-+		unsigned int toe_q1_full	: 1;	// bit 1	TOE Queue 1 Full Interrupt
-+		unsigned int toe_q0_full	: 1;	// bit 0	TOE Queue 0 Full Interrupt
-+#else
-+		unsigned int toe_q0_full	: 1;	// bit 0	TOE Queue 0 Full Interrupt
-+		unsigned int toe_q1_full	: 1;	// bit 1	TOE Queue 1 Full Interrupt
-+		unsigned int toe_q2_full	: 1;	// bit 2	TOE Queue 2 Full Interrupt
-+		unsigned int toe_q3_full	: 1;	// bit 3	TOE Queue 3 Full Interrupt
-+		unsigned int toe_q4_full	: 1;	// bit 4	TOE Queue 4 Full Interrupt
-+		unsigned int toe_q5_full	: 1;	// bit 5	TOE Queue 5 Full Interrupt
-+		unsigned int toe_q6_full	: 1;	// bit 6	TOE Queue 6 Full Interrupt
-+		unsigned int toe_q7_full	: 1;	// bit 7	TOE Queue 7 Full Interrupt
-+		unsigned int toe_q8_full	: 1;	// bit 8	TOE Queue 8 Full Interrupt
-+		unsigned int toe_q9_full	: 1;	// bit 9	TOE Queue 9 Full Interrupt
-+		unsigned int toe_q10_full	: 1;	// bit 10	TOE Queue 10 Full Interrupt
-+		unsigned int toe_q11_full	: 1;	// bit 11	TOE Queue 11 Full Interrupt
-+		unsigned int toe_q12_full	: 1;	// bit 12	TOE Queue 12 Full Interrupt
-+		unsigned int toe_q13_full	: 1;	// bit 13	TOE Queue 13 Full Interrupt
-+		unsigned int toe_q14_full	: 1;	// bit 14	TOE Queue 14 Full Interrupt
-+		unsigned int toe_q15_full	: 1;	// bit 15	TOE Queue 15 Full Interrupt
-+		unsigned int toe_q16_full	: 1;	// bit 16	TOE Queue 16 Full Interrupt
-+		unsigned int toe_q17_full	: 1;	// bit 17	TOE Queue 17 Full Interrupt
-+		unsigned int toe_q18_full	: 1;	// bit 18	TOE Queue 18 Full Interrupt
-+		unsigned int toe_q19_full	: 1;	// bit 19	TOE Queue 19 Full Interrupt
-+		unsigned int toe_q20_full	: 1;	// bit 20	TOE Queue 20 Full Interrupt
-+		unsigned int toe_q21_full	: 1;	// bit 21	TOE Queue 21 Full Interrupt
-+		unsigned int toe_q22_full	: 1;	// bit 22	TOE Queue 22 Full Interrupt
-+		unsigned int toe_q23_full	: 1;	// bit 23	TOE Queue 23 Full Interrupt
-+		unsigned int toe_q24_full	: 1;	// bit 24	TOE Queue 24 Full Interrupt
-+		unsigned int toe_q25_full	: 1;	// bit 25	TOE Queue 25 Full Interrupt
-+		unsigned int toe_q26_full	: 1;	// bit 26	TOE Queue 26 Full Interrupt
-+		unsigned int toe_q27_full	: 1;	// bit 27	TOE Queue 27 Full Interrupt
-+		unsigned int toe_q28_full	: 1;	// bit 28	TOE Queue 28 Full Interrupt
-+		unsigned int toe_q29_full	: 1;	// bit 29	TOE Queue 29 Full Interrupt
-+		unsigned int toe_q30_full	: 1;	// bit 30	TOE Queue 30 Full Interrupt
-+		unsigned int toe_q31_full	: 1;	// bit 31	TOE Queue 31 Full Interrupt
-+#endif
-+	} bits;
-+} INTR_REG2_T;
-+
-+#define TOE_QL_FULL_INT_BIT(x)		BIT(x)
-+
-+/**********************************************************************
-+ * Interrupt Status Register 3 	(offset 0x0050)
-+ * Interrupt Mask Register 3 	(offset 0x0054)
-+ * Interrupt Select Register 3 	(offset 0x0058)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_0050
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int toe_q63_full	: 1;	// bit 63	TOE Queue 63 Full Interrupt
-+		unsigned int toe_q62_full	: 1;	// bit 62	TOE Queue 62 Full Interrupt
-+		unsigned int toe_q61_full	: 1;	// bit 61	TOE Queue 61 Full Interrupt
-+		unsigned int toe_q60_full	: 1;	// bit 60	TOE Queue 60 Full Interrupt
-+		unsigned int toe_q59_full	: 1;	// bit 59	TOE Queue 59 Full Interrupt
-+		unsigned int toe_q58_full	: 1;	// bit 58	TOE Queue 58 Full Interrupt
-+		unsigned int toe_q57_full	: 1;	// bit 57	TOE Queue 57 Full Interrupt
-+		unsigned int toe_q56_full	: 1;	// bit 56	TOE Queue 56 Full Interrupt
-+		unsigned int toe_q55_full	: 1;	// bit 55	TOE Queue 55 Full Interrupt
-+		unsigned int toe_q54_full	: 1;	// bit 54	TOE Queue 54 Full Interrupt
-+		unsigned int toe_q53_full	: 1;	// bit 53	TOE Queue 53 Full Interrupt
-+		unsigned int toe_q52_full	: 1;	// bit 52	TOE Queue 52 Full Interrupt
-+		unsigned int toe_q51_full	: 1;	// bit 51	TOE Queue 51 Full Interrupt
-+		unsigned int toe_q50_full	: 1;	// bit 50	TOE Queue 50 Full Interrupt
-+		unsigned int toe_q49_full	: 1;	// bit 49	TOE Queue 49 Full Interrupt
-+		unsigned int toe_q48_full	: 1;	// bit 48	TOE Queue 48 Full Interrupt
-+		unsigned int toe_q47_full	: 1;	// bit 47	TOE Queue 47 Full Interrupt
-+		unsigned int toe_q46_full	: 1;	// bit 46	TOE Queue 46 Full Interrupt
-+		unsigned int toe_q45_full	: 1;	// bit 45	TOE Queue 45 Full Interrupt
-+		unsigned int toe_q44_full	: 1;	// bit 44	TOE Queue 44 Full Interrupt
-+		unsigned int toe_q43_full	: 1;	// bit 43	TOE Queue 43 Full Interrupt
-+		unsigned int toe_q42_full	: 1;	// bit 42	TOE Queue 42 Full Interrupt
-+		unsigned int toe_q41_full	: 1;	// bit 41	TOE Queue 41 Full Interrupt
-+		unsigned int toe_q40_full	: 1;	// bit 40	TOE Queue 40 Full Interrupt
-+		unsigned int toe_q39_full	: 1;	// bit 39 	TOE Queue 39 Full Interrupt
-+		unsigned int toe_q38_full	: 1;	// bit 38	TOE Queue 38 Full Interrupt
-+		unsigned int toe_q37_full	: 1;	// bit 37	TOE Queue 37 Full Interrupt
-+		unsigned int toe_q36_full	: 1;	// bit 36	TOE Queue 36 Full Interrupt
-+		unsigned int toe_q35_full	: 1;	// bit 35	TOE Queue 35 Full Interrupt
-+		unsigned int toe_q34_full	: 1;	// bit 34	TOE Queue 34 Full Interrupt
-+		unsigned int toe_q33_full	: 1;	// bit 33	TOE Queue 33 Full Interrupt
-+		unsigned int toe_q32_full	: 1;	// bit 32	TOE Queue 32 Full Interrupt
-+#else
-+		unsigned int toe_q32_full	: 1;	// bit 32	TOE Queue 32 Full Interrupt
-+		unsigned int toe_q33_full	: 1;	// bit 33	TOE Queue 33 Full Interrupt
-+		unsigned int toe_q34_full	: 1;	// bit 34	TOE Queue 34 Full Interrupt
-+		unsigned int toe_q35_full	: 1;	// bit 35	TOE Queue 35 Full Interrupt
-+		unsigned int toe_q36_full	: 1;	// bit 36	TOE Queue 36 Full Interrupt
-+		unsigned int toe_q37_full	: 1;	// bit 37	TOE Queue 37 Full Interrupt
-+		unsigned int toe_q38_full	: 1;	// bit 38	TOE Queue 38 Full Interrupt
-+		unsigned int toe_q39_full	: 1;	// bit 39	TOE Queue 39 Full Interrupt
-+		unsigned int toe_q40_full	: 1;	// bit 40	TOE Queue 40 Full Interrupt
-+		unsigned int toe_q41_full	: 1;	// bit 41	TOE Queue 41 Full Interrupt
-+		unsigned int toe_q42_full	: 1;	// bit 42	TOE Queue 42 Full Interrupt
-+		unsigned int toe_q43_full	: 1;	// bit 43	TOE Queue 43 Full Interrupt
-+		unsigned int toe_q44_full	: 1;	// bit 44	TOE Queue 44 Full Interrupt
-+		unsigned int toe_q45_full	: 1;	// bit 45	TOE Queue 45 Full Interrupt
-+		unsigned int toe_q46_full	: 1;	// bit 46	TOE Queue 46 Full Interrupt
-+		unsigned int toe_q47_full	: 1;	// bit 47	TOE Queue 47 Full Interrupt
-+		unsigned int toe_q48_full	: 1;	// bit 48	TOE Queue 48 Full Interrupt
-+		unsigned int toe_q49_full	: 1;	// bit 49	TOE Queue 49 Full Interrupt
-+		unsigned int toe_q50_full	: 1;	// bit 50	TOE Queue 50 Full Interrupt
-+		unsigned int toe_q51_full	: 1;	// bit 51	TOE Queue 51 Full Interrupt
-+		unsigned int toe_q52_full	: 1;	// bit 52	TOE Queue 52 Full Interrupt
-+		unsigned int toe_q53_full	: 1;	// bit 53	TOE Queue 53 Full Interrupt
-+		unsigned int toe_q54_full	: 1;	// bit 54	TOE Queue 54 Full Interrupt
-+		unsigned int toe_q55_full	: 1;	// bit 55	TOE Queue 55 Full Interrupt
-+		unsigned int toe_q56_full	: 1;	// bit 56	TOE Queue 56 Full Interrupt
-+		unsigned int toe_q57_full	: 1;	// bit 57	TOE Queue 57 Full Interrupt
-+		unsigned int toe_q58_full	: 1;	// bit 58	TOE Queue 58 Full Interrupt
-+		unsigned int toe_q59_full	: 1;	// bit 59	TOE Queue 59 Full Interrupt
-+		unsigned int toe_q60_full	: 1;	// bit 60	TOE Queue 60 Full Interrupt
-+		unsigned int toe_q61_full	: 1;	// bit 61	TOE Queue 61 Full Interrupt
-+		unsigned int toe_q62_full	: 1;	// bit 62	TOE Queue 62 Full Interrupt
-+		unsigned int toe_q63_full	: 1;	// bit 63	TOE Queue 63 Full Interrupt
-+#endif
-+	} bits;
-+} INTR_REG3_T;
-+
-+#define TOE_QH_FULL_INT_BIT(x)		BIT(x-32)
-+
-+/**********************************************************************
-+ * Interrupt Status Register 4 	(offset 0x0060)
-+ * Interrupt Mask Register 4 	(offset 0x0064)
-+ * Interrupt Select Register 4 	(offset 0x0068)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned char byte;
-+	struct bit_0060
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned char reserved		: 1;	//
-+		unsigned char cnt_full 		: 1;	// MIB counters half full interrupt
-+		unsigned char rx_pause_on	: 1;	// received pause on frame interrupt
-+		unsigned char tx_pause_on	: 1;	// transmit pause on frame interrupt
-+		unsigned char rx_pause_off  : 1;	// received pause off frame interrupt
-+		unsigned char tx_pause_off	: 1;	// received pause off frame interrupt
-+		unsigned char rx_overrun	: 1;    // GMAC Rx FIFO overrun interrupt
-+		unsigned char status_changed: 1;	// Status Changed Intr for RGMII Mode
-+#else
-+		unsigned char status_changed: 1;	// Status Changed Intr for RGMII Mode
-+		unsigned char rx_overrun	: 1;   // GMAC Rx FIFO overrun interrupt
-+		unsigned char tx_pause_off	: 1;	// received pause off frame interrupt
-+		unsigned char rx_pause_off  : 1;	// received pause off frame interrupt
-+		unsigned char tx_pause_on	: 1;	// transmit pause on frame interrupt
-+		unsigned char rx_pause_on	: 1;	// received pause on frame interrupt
-+		unsigned char cnt_full 		: 1;	// MIB counters half full interrupt
-+		unsigned char reserved		: 1;	//
-+#endif
-+	} _PACKED_ bits;
-+} _PACKED_ GMAC_INTR_T;
-+
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_0060_2
-+	{
-+#if (BIG_ENDIAN==1)
-+		GMAC_INTR_T		gmac1;
-+		GMAC_INTR_T		gmac0;
-+		unsigned int	class_qf_int: 14;	// bit 15:2 Classification Rx Queue13-0 Full Intr.
-+		unsigned int    hwfq_empty	: 1;	// bit 1	Hardware Free Queue Empty Intr.
-+		unsigned int    swfq_empty	: 1;	// bit 0	Software Free Queue Empty Intr.
-+#else
-+#endif
-+		unsigned int    swfq_empty	: 1;	// bit 0	Software Free Queue Empty Intr.
-+		unsigned int    hwfq_empty	: 1;	// bit 1	Hardware Free Queue Empty Intr.
-+		unsigned int	class_qf_int: 14;	// bit 15:2 Classification Rx Queue13-0 Full Intr.
-+		GMAC_INTR_T		gmac0;
-+		GMAC_INTR_T		gmac1;
-+	} bits;
-+} INTR_REG4_T;
-+
-+#define GMAC1_RESERVED_INT_BIT		BIT(31)
-+#define GMAC1_MIB_INT_BIT			BIT(30)
-+#define GMAC1_RX_PAUSE_ON_INT_BIT	BIT(29)
-+#define GMAC1_TX_PAUSE_ON_INT_BIT	BIT(28)
-+#define GMAC1_RX_PAUSE_OFF_INT_BIT	BIT(27)
-+#define GMAC1_TX_PAUSE_OFF_INT_BIT	BIT(26)
-+#define GMAC1_RX_OVERRUN_INT_BIT	BIT(25)
-+#define GMAC1_STATUS_CHANGE_INT_BIT	BIT(24)
-+#define GMAC0_RESERVED_INT_BIT		BIT(23)
-+#define GMAC0_MIB_INT_BIT			BIT(22)
-+#define GMAC0_RX_PAUSE_ON_INT_BIT	BIT(21)
-+#define GMAC0_TX_PAUSE_ON_INT_BIT	BIT(20)
-+#define GMAC0_RX_PAUSE_OFF_INT_BIT	BIT(19)
-+#define GMAC0_TX_PAUSE_OFF_INT_BIT	BIT(18)
-+#define GMAC0_RX_OVERRUN_INT_BIT	BIT(17)
-+#define GMAC0_STATUS_CHANGE_INT_BIT	BIT(16)
-+#define CLASS_RX_FULL_INT_BIT(x)	BIT((x+2))
-+#define HWFQ_EMPTY_INT_BIT			BIT(1)
-+#define SWFQ_EMPTY_INT_BIT			BIT(0)
-+
-+#if 1
-+#define GMAC0_INT_BITS				(GMAC0_MIB_INT_BIT)
-+#define GMAC1_INT_BITS				(GMAC1_MIB_INT_BIT)
-+#else
-+#define GMAC0_INT_BITS				(GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
-+									 GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT |	\
-+									 GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | 	\
-+									 GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
-+#define GMAC1_INT_BITS				(GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
-+									 GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT |	\
-+									 GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | 	\
-+									 GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
-+#endif
-+
-+#define CLASS_RX_FULL_INT_BITS		0xfffc
-+
-+/**********************************************************************
-+ * GLOBAL_QUEUE_THRESHOLD_REG 	(offset 0x0070)
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_0070_2
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int	toe_class	: 8;	// 31:24
-+		unsigned int	intrq		: 8;	// 23:16
-+		unsigned int    hwfq_empty	: 8;	// 15:8		Hardware Free Queue Empty Threshold
-+		unsigned int    swfq_empty	: 8;	//  7:0  	Software Free Queue Empty Threshold
-+#else
-+#endif
-+		unsigned int    swfq_empty	: 8;	//  7:0  	Software Free Queue Empty Threshold
-+		unsigned int    hwfq_empty	: 8;	// 15:8		Hardware Free Queue Empty Threshold
-+		unsigned int	intrq		: 8;	// 23:16
-+		unsigned int	toe_class	: 8;	// 31:24
-+	} bits;
-+} QUEUE_THRESHOLD_T;
-+
-+
-+/**********************************************************************
-+ * GMAC DMA Control Register
-+ * GMAC0 offset 0x8000
-+ * GMAC1 offset 0xC000
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8000
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int    rd_enable		: 1;	// bit 31	Rx DMA Enable
-+		unsigned int    td_enable		: 1;	// bit 30	Tx DMA Enable
-+		unsigned int    loopback		: 1;	// bit 29	Loopback TxDMA to RxDMA
-+		unsigned int    drop_small_ack	: 1;	// bit 28	1: Drop, 0: Accept
-+		unsigned int	reserved		: 10;	// bit 27:18
-+		unsigned int	rd_insert_bytes	: 2;	// bit 17:16
-+		unsigned int	rd_prot			: 4;	// bit 15:12 DMA Protection Control
-+		unsigned int	rd_burst_size	: 2;	// bit 11:10 DMA max burst size for every AHB request
-+		unsigned int	rd_bus		    : 2;	// bit 9:8 	Peripheral Bus Width
-+		unsigned int	td_prot			: 4;	// bit 7:4  TxDMA protection control
-+		unsigned int	td_burst_size	: 2;	// bit 3:2	TxDMA max burst size for every AHB request
-+		unsigned int	td_bus		    : 2;	// bit 1:0  Peripheral Bus Width
-+#else
-+		unsigned int	td_bus		    : 2;	// bit 1:0  Peripheral Bus Width
-+		unsigned int	td_burst_size	: 2;	// bit 3:2	TxDMA max burst size for every AHB request
-+		unsigned int	td_prot			: 4;	// bit 7:4  TxDMA protection control
-+		unsigned int	rd_bus		    : 2;	// bit 9:8 	Peripheral Bus Width
-+		unsigned int	rd_burst_size	: 2;	// bit 11:10 DMA max burst size for every AHB request
-+		unsigned int	rd_prot			: 4;	// bit 15:12 DMA Protection Control
-+		unsigned int	rd_insert_bytes	: 2;	// bit 17:16
-+		unsigned int	reserved		: 10;	// bit 27:18
-+		unsigned int    drop_small_ack	: 1;	// bit 28	1: Drop, 0: Accept
-+		unsigned int    loopback		: 1;	// bit 29	Loopback TxDMA to RxDMA
-+		unsigned int    td_enable		: 1;	// bit 30	Tx DMA Enable
-+		unsigned int    rd_enable		: 1;	// bit 31	Rx DMA Enable
-+#endif
-+	} bits;
-+} GMAC_DMA_CTRL_T;
-+
-+/**********************************************************************
-+ * GMAC Tx Weighting Control Register 0
-+ * GMAC0 offset 0x8004
-+ * GMAC1 offset 0xC004
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8004
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int    reserved		: 8;	// bit 31:24
-+		unsigned int    hw_tq3			: 6;	// bit 23:18	HW TX Queue 0
-+		unsigned int    hw_tq2			: 6;	// bit 17:12	HW TX Queue 1
-+		unsigned int    hw_tq1			: 6;	// bit 11:6		HW TX Queue 2
-+		unsigned int    hw_tq0			: 6;	// bit 5:0		HW TX Queue 3
-+#else
-+		unsigned int    hw_tq0			: 6;	// bit 5:0		HW TX Queue 3
-+		unsigned int    hw_tq1			: 6;	// bit 11:6		HW TX Queue 2
-+		unsigned int    hw_tq2			: 6;	// bit 17:12	HW TX Queue 1
-+		unsigned int    hw_tq3			: 6;	// bit 23:18	HW TX Queue 0
-+		unsigned int    reserved		: 8;	// bit 31:24
-+#endif
-+	} bits;
-+} GMAC_TX_WCR0_T;	// Weighting Control Register 0
-+
-+/**********************************************************************
-+ * GMAC Tx Weighting Control Register 1
-+ * GMAC0 offset 0x8008
-+ * GMAC1 offset 0xC008
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8008
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int    reserved		: 2;	// bit 31:30
-+		unsigned int    sw_tq5			: 5;	// bit 29:25	SW TX Queue 5
-+		unsigned int    sw_tq4			: 5;	// bit 24:20	SW TX Queue 4
-+		unsigned int    sw_tq3			: 5;	// bit 19:15	SW TX Queue 3
-+		unsigned int    sw_tq2			: 5;	// bit 14:10	SW TX Queue 2
-+		unsigned int    sw_tq1			: 5;	// bit 9:5		SW TX Queue 1
-+		unsigned int    sw_tq0			: 5;	// bit 4:0		SW TX Queue 0
-+#else
-+		unsigned int    sw_tq0			: 5;	// bit 4:0		SW TX Queue 0
-+		unsigned int    sw_tq1			: 5;	// bit 9:5		SW TX Queue 1
-+		unsigned int    sw_tq2			: 5;	// bit 14:10	SW TX Queue 2
-+		unsigned int    sw_tq3			: 5;	// bit 19:15	SW TX Queue 3
-+		unsigned int    sw_tq4			: 5;	// bit 24:20	SW TX Queue 4
-+		unsigned int    sw_tq5			: 5;	// bit 29:25	SW TX Queue 5
-+		unsigned int    reserved		: 2;	// bit 31:30
-+#endif
-+	} bits;
-+} GMAC_TX_WCR1_T;	// Weighting Control Register 1
-+
-+/**********************************************************************
-+ * Queue Read/Write Pointer
-+ * GMAC SW TX Queue 0~5 Read/Write Pointer register
-+ * GMAC0 offset 0x800C ~ 0x8020
-+ * GMAC1 offset 0xC00C ~ 0xC020
-+ * GMAC HW TX Queue 0~3 Read/Write Pointer register
-+ * GMAC0 offset 0x8024 ~ 0x8030
-+ * GMAC1 offset 0xC024 ~ 0xC030
-+ **********************************************************************/
-+// see DMA_RWPTR_T structure
-+
-+/**********************************************************************
-+ * GMAC DMA Tx First Description Address Register
-+ * GMAC0 offset 0x8038
-+ * GMAC1 offset 0xC038
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8038
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int td_first_des_ptr	: 28;	// bit 31:4	first descriptor address
-+		unsigned int td_busy			:  1;	// bit 3	1: TxDMA busy; 0: TxDMA idle
-+		unsigned int reserved			:  3;
-+#else
-+		unsigned int reserved			:  3;
-+		unsigned int td_busy			:  1;	// bit 3	1: TxDMA busy; 0: TxDMA idle
-+		unsigned int td_first_des_ptr	: 28;	// bit 31:4	first descriptor address
-+#endif
-+	} bits;
-+} GMAC_TXDMA_FIRST_DESC_T;
-+
-+/**********************************************************************
-+ * GMAC DMA Tx Current Description Address Register
-+ * GMAC0 offset 0x803C
-+ * GMAC1 offset 0xC03C
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_803C
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int td_curr_desc_ptr	: 28;	// bit 31:4	current descriptor address
-+		unsigned int reserved			:  4;
-+#else
-+		unsigned int reserved			:  4;
-+		unsigned int td_curr_desc_ptr	: 28;	// bit 31:4	current descriptor address
-+#endif
-+	} bits;
-+} GMAC_TXDMA_CURR_DESC_T;
-+
-+/**********************************************************************
-+ * GMAC DMA Tx Description Word 0 Register
-+ * GMAC0 offset 0x8040
-+ * GMAC1 offset 0xC040
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8040
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int reserved		: 1;	// bit 31
-+		unsigned int derr			: 1;	// bit 30	 data error during processing this descriptor
-+		unsigned int perr			: 1;	// bit 29	 protocol error during processing this descriptor
-+		unsigned int status_rvd		: 6;	// bit 28:23 Tx Status, Reserved bits
-+		unsigned int status_tx_ok	: 1;	// bit 22    Tx Status, 1: Successful 0: Failed
-+		unsigned int desc_count 	: 6;	// bit 21:16 number of descriptors used for the current frame
-+		unsigned int buffer_size 	: 16;	// bit 15:0  Transfer size
-+#else
-+		unsigned int buffer_size 	: 16;	// bit 15:0  Transfer size
-+		unsigned int desc_count 	: 6;	// bit 21:16 number of descriptors used for the current frame
-+		unsigned int status_tx_ok	: 1;	// bit 22    Tx Status, 1: Successful 0: Failed
-+		unsigned int status_rvd		: 6;	// bit 28:23 Tx Status, Reserved bits
-+		unsigned int perr			: 1;	// bit 29	 protocol error during processing this descriptor
-+		unsigned int derr			: 1;	// bit 30	 data error during processing this descriptor
-+		unsigned int reserved		: 1;	// bit 31
-+#endif
-+	} bits;
-+} GMAC_TXDESC_0_T;
-+
-+/**********************************************************************
-+ * GMAC DMA Tx Description Word 1 Register
-+ * GMAC0 offset 0x8044
-+ * GMAC1 offset 0xC044
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct txdesc_word1
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int	reserved	: 9;	// bit 31:23 	Tx Flag, Reserved
-+		unsigned int	ip_fixed_len: 1;	// bit 22
-+		unsigned int	bypass_tss	: 1;	// bit 21
-+		unsigned int	udp_chksum	: 1;	// bit 20		UDP Checksum Enable
-+		unsigned int	tcp_chksum	: 1;	// bit 19		TCP Checksum Enable
-+		unsigned int	ipv6_enable	: 1;	// bit 18		IPV6 Tx Enable
-+		unsigned int	ip_chksum	: 1;	// bit 17		IPV4 Header Checksum Enable
-+		unsigned int	mtu_enable	: 1;	// bit 16		TSS segmentation use MTU setting
-+		unsigned int	byte_count	: 16;	// bit 15: 0	Tx Frame Byte Count
-+#else
-+		unsigned int	byte_count	: 16;	// bit 15: 0	Tx Frame Byte Count
-+		unsigned int	mtu_enable	: 1;	// bit 16		TSS segmentation use MTU setting
-+		unsigned int	ip_chksum	: 1;	// bit 17		IPV4 Header Checksum Enable
-+		unsigned int	ipv6_enable	: 1;	// bit 18		IPV6 Tx Enable
-+		unsigned int	tcp_chksum	: 1;	// bit 19		TCP Checksum Enable
-+		unsigned int	udp_chksum	: 1;	// bit 20		UDP Checksum Enable
-+		unsigned int	bypass_tss	: 1;	// bit 21
-+		unsigned int	ip_fixed_len: 1;	// bit 22
-+		unsigned int	reserved	: 9;	// bit 31:23 	Tx Flag, Reserved
-+#endif
-+	} bits;
-+} GMAC_TXDESC_1_T;
-+
-+#define TSS_IP_FIXED_LEN_BIT	BIT(22)
-+#define TSS_UDP_CHKSUM_BIT		BIT(20)
-+#define TSS_TCP_CHKSUM_BIT		BIT(19)
-+#define TSS_IPV6_ENABLE_BIT		BIT(18)
-+#define TSS_IP_CHKSUM_BIT		BIT(17)
-+#define TSS_MTU_ENABLE_BIT		BIT(16)
-+
-+/**********************************************************************
-+ * GMAC DMA Tx Description Word 2 Register
-+ * GMAC0 offset 0x8048
-+ * GMAC1 offset 0xC048
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int	bits32;
-+	unsigned int 	buf_adr;
-+} GMAC_TXDESC_2_T;
-+
-+/**********************************************************************
-+ * GMAC DMA Tx Description Word 3 Register
-+ * GMAC0 offset 0x804C
-+ * GMAC1 offset 0xC04C
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct txdesc_word3
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int	sof_eof		: 2;	// bit 31:30 	11: only one, 10: first, 01: last, 00: linking
-+		unsigned int	eofie		: 1;	// bit 29		End of frame interrupt enable
-+		unsigned int	reserved	: 18;	// bit 28:11
-+		unsigned int	mtu_size	: 11;	// bit 10: 0	Tx Frame Byte Count
-+#else
-+		unsigned int	mtu_size	: 11;	// bit 10: 0	Tx Frame Byte Count
-+		unsigned int	reserved	: 18;	// bit 28:11
-+		unsigned int	eofie		: 1;	// bit 29		End of frame interrupt enable
-+		unsigned int	sof_eof		: 2;	// bit 31:30 	11: only one, 10: first, 01: last, 00: linking
-+#endif
-+	} bits;
-+} GMAC_TXDESC_3_T;
-+#define SOF_EOF_BIT_MASK	0x3fffffff
-+#define SOF_BIT				0x80000000
-+#define EOF_BIT				0x40000000
-+#define EOFIE_BIT			BIT(29)
-+#define MTU_SIZE_BIT_MASK	0x7ff
-+
-+/**********************************************************************
-+ * GMAC Tx Descriptor
-+ **********************************************************************/
-+typedef struct
-+{
-+	GMAC_TXDESC_0_T	word0;
-+	GMAC_TXDESC_1_T	word1;
-+	GMAC_TXDESC_2_T	word2;
-+	GMAC_TXDESC_3_T	word3;
-+} GMAC_TXDESC_T;
-+
-+
-+/**********************************************************************
-+ * GMAC DMA Rx First Description Address Register
-+ * GMAC0 offset 0x8058
-+ * GMAC1 offset 0xC058
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8058
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int rd_first_des_ptr	: 28;	// bit 31:4 first descriptor address
-+		unsigned int rd_busy			:  1;	// bit 3	1-RxDMA busy; 0-RxDMA idle
-+		unsigned int reserved			:  3;	// bit 2:0
-+#else
-+		unsigned int reserved			:  3;	// bit 2:0
-+		unsigned int rd_busy			:  1;	// bit 3	1-RxDMA busy; 0-RxDMA idle
-+		unsigned int rd_first_des_ptr	: 28;	// bit 31:4 first descriptor address
-+#endif
-+	} bits;
-+} GMAC_RXDMA_FIRST_DESC_T;
-+
-+/**********************************************************************
-+ * GMAC DMA Rx Current Description Address Register
-+ * GMAC0 offset 0x805C
-+ * GMAC1 offset 0xC05C
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_805C
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int rd_curr_des_ptr	: 28;	// bit 31:4 current descriptor address
-+		unsigned int reserved			:  4;	// bit 3:0
-+#else
-+		unsigned int reserved			:  4;	// bit 3:0
-+		unsigned int rd_curr_des_ptr	: 28;	// bit 31:4 current descriptor address
-+#endif
-+	} bits;
-+} GMAC_RXDMA_CURR_DESC_T;
-+
-+/**********************************************************************
-+ * GMAC DMA Rx Description Word 0 Register
-+ * GMAC0 offset 0x8060
-+ * GMAC1 offset 0xC060
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8060
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int drop			: 1;	// bit 31	 TOE/CIS Queue Full dropped packet to default queue
-+		unsigned int derr			: 1;	// bit 30	 data error during processing this descriptor
-+		unsigned int perr			: 1;	// bit 29	 protocol error during processing this descriptor
-+		unsigned int chksum_status	: 3;	// bit 28:26 Check Sum Status
-+		unsigned int status			: 4;	// bit 24:22 Status of rx frame
-+		unsigned int desc_count 	: 6;	// bit 21:16 number of descriptors used for the current frame
-+		unsigned int buffer_size 	: 16;	// bit 15:0  number of descriptors used for the current frame
-+#else
-+		unsigned int buffer_size 	: 16;	// bit 15:0  number of descriptors used for the current frame
-+		unsigned int desc_count 	: 6;	// bit 21:16 number of descriptors used for the current frame
-+		unsigned int status			: 4;	// bit 24:22 Status of rx frame
-+		unsigned int chksum_status	: 3;	// bit 28:26 Check Sum Status
-+		unsigned int perr			: 1;	// bit 29	 protocol error during processing this descriptor
-+		unsigned int derr			: 1;	// bit 30	 data error during processing this descriptor
-+		unsigned int drop			: 1;	// bit 31	 TOE/CIS Queue Full dropped packet to default queue
-+#endif
-+	} bits;
-+} GMAC_RXDESC_0_T;
-+
-+#define		GMAC_RXDESC_0_T_derr				BIT(30)
-+#define		GMAC_RXDESC_0_T_perr				BIT(29)
-+#define		GMAC_RXDESC_0_T_chksum_status(x)	BIT((x+26))
-+#define		GMAC_RXDESC_0_T_status(x)			BIT((x+22))
-+#define		GMAC_RXDESC_0_T_desc_count(x)		BIT((x+16))
-+
-+#define	RX_CHKSUM_IP_UDP_TCP_OK			0
-+#define	RX_CHKSUM_IP_OK_ONLY			1
-+#define	RX_CHKSUM_NONE					2
-+#define	RX_CHKSUM_IP_ERR_UNKNOWN		4
-+#define	RX_CHKSUM_IP_ERR				5
-+#define	RX_CHKSUM_TCP_UDP_ERR			6
-+#define RX_CHKSUM_NUM					8
-+
-+#define RX_STATUS_GOOD_FRAME			0
-+#define RX_STATUS_TOO_LONG_GOOD_CRC		1
-+#define RX_STATUS_RUNT_FRAME			2
-+#define RX_STATUS_SFD_NOT_FOUND			3
-+#define RX_STATUS_CRC_ERROR				4
-+#define RX_STATUS_TOO_LONG_BAD_CRC		5
-+#define RX_STATUS_ALIGNMENT_ERROR		6
-+#define RX_STATUS_TOO_LONG_BAD_ALIGN	7
-+#define RX_STATUS_RX_ERR				8
-+#define RX_STATUS_DA_FILTERED			9
-+#define RX_STATUS_BUFFER_FULL			10
-+#define RX_STATUS_NUM					16
-+
-+
-+/**********************************************************************
-+ * GMAC DMA Rx Description Word 1 Register
-+ * GMAC0 offset 0x8064
-+ * GMAC1 offset 0xC064
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct rxdesc_word1
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int	sw_id		: 16;	// bit 31:16	Software ID
-+		unsigned int	byte_count	: 16;	// bit 15: 0	Rx Frame Byte Count
-+#else
-+		unsigned int	byte_count	: 16;	// bit 15: 0	Rx Frame Byte Count
-+		unsigned int	sw_id		: 16;	// bit 31:16	Software ID
-+#endif
-+	} bits;
-+} GMAC_RXDESC_1_T;
-+
-+/**********************************************************************
-+ * GMAC DMA Rx Description Word 2 Register
-+ * GMAC0 offset 0x8068
-+ * GMAC1 offset 0xC068
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int	bits32;
-+	unsigned int	buf_adr;
-+} GMAC_RXDESC_2_T;
-+
-+#define RX_INSERT_NONE		0
-+#define RX_INSERT_1_BYTE	1
-+#define RX_INSERT_2_BYTE	2
-+#define RX_INSERT_3_BYTE	3
-+
-+#define RX_INSERT_BYTES		RX_INSERT_2_BYTE
-+/**********************************************************************
-+ * GMAC DMA Rx Description Word 3 Register
-+ * GMAC0 offset 0x806C
-+ * GMAC1 offset 0xC06C
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct rxdesc_word3
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int	sof_eof		: 2;	// bit 31:30 	11: only one, 10: first, 01: last, 00: linking
-+		unsigned int	eofie		: 1;	// bit 29		End of frame interrupt enable
-+		unsigned int	ctrl_flag	: 1;	// bit 28 		Control Flag is present
-+		unsigned int	out_of_seq	: 1;	// bit 27		Out of Sequence packet
-+		unsigned int	option		: 1;	// bit 26		IPV4 option or IPV6 extension header
-+		unsigned int	abnormal	: 1;	// bit 25		abnormal case found
-+		unsigned int	dup_ack		: 1;	// bit 24		Duplicated ACK detected
-+		unsigned int	l7_offset	: 8;	// bit 23: 16	L7 data offset
-+		unsigned int	l4_offset	: 8;	// bit 15: 8	L4 data offset
-+		unsigned int	l3_offset	: 8;	// bit 7: 0		L3 data offset
-+#else
-+		unsigned int	l3_offset	: 8;	// bit 7: 0		L3 data offset
-+		unsigned int	l4_offset	: 8;	// bit 15: 8	L4 data offset
-+		unsigned int	l7_offset	: 8;	// bit 23: 16	L7 data offset
-+		unsigned int	dup_ack		: 1;	// bit 24		Duplicated ACK detected
-+		unsigned int	abnormal	: 1;	// bit 25		abnormal case found
-+		unsigned int	option		: 1;	// bit 26		IPV4 option or IPV6 extension header
-+		unsigned int	out_of_seq	: 1;	// bit 27		Out of Sequence packet
-+		unsigned int	ctrl_flag	: 1;	// bit 28 		Control Flag is present
-+		unsigned int	eofie		: 1;	// bit 29		End of frame interrupt enable
-+		unsigned int	sof_eof		: 2;	// bit 31:30 	11: only one, 10: first, 01: last, 00: linking
-+#endif
-+	} bits;
-+} GMAC_RXDESC_3_T;
-+
-+/**********************************************************************
-+ * GMAC Rx Descriptor
-+ **********************************************************************/
-+typedef struct
-+{
-+	GMAC_RXDESC_0_T	word0;
-+	GMAC_RXDESC_1_T	word1;
-+	GMAC_RXDESC_2_T	word2;
-+	GMAC_RXDESC_3_T	word3;
-+} GMAC_RXDESC_T;
-+
-+/**********************************************************************
-+ * GMAC Hash Engine Enable/Action Register 0 Offset Register
-+ * GMAC0 offset 0x8070
-+ * GMAC1 offset 0xC070
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8070
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int	mr1en		: 1;	// bit 31		Enable Matching Rule 1
-+		unsigned int	reserved1	: 1;	// bit 30
-+		unsigned int	timing		: 3;	// bit 29:27
-+		unsigned int	mr1_action	: 5;	// bit 26:22	Matching Rule 1 action offset
-+		unsigned int	mr1hel		: 6;	// bit 21:16	match rule 1 hash entry size
-+		unsigned int	mr0en		: 1;	// bit 15		Enable Matching Rule 0
-+		unsigned int	reserved0	: 4;	// bit 14:11
-+		unsigned int	mr0_action	: 5;	// bit 10:6		Matching Rule 0 action offset
-+		unsigned int	mr0hel		: 6;	// bit 5:0		match rule 0 hash entry size
-+#else
-+		unsigned int	mr0hel		: 6;	// bit 5:0		match rule 0 hash entry size
-+		unsigned int	mr0_action	: 5;	// bit 10:6		Matching Rule 0 action offset
-+		unsigned int	reserved0	: 4;	// bit 14:11
-+		unsigned int	mr0en		: 1;	// bit 15		Enable Matching Rule 0
-+		unsigned int	mr1hel		: 6;	// bit 21:16	match rule 1 hash entry size
-+		unsigned int	mr1_action	: 5;	// bit 26:22	Matching Rule 1 action offset
-+		unsigned int	timing		: 3;	// bit 29:27
-+		unsigned int	reserved1	: 1;	// bit 30
-+		unsigned int	mr1en		: 1;	// bit 31		Enable Matching Rule 1
-+#endif
-+	} bits;
-+} GMAC_HASH_ENABLE_REG0_T;
-+
-+/**********************************************************************
-+ * GMAC Hash Engine Enable/Action Register 1 Offset Register
-+ * GMAC0 offset 0x8074
-+ * GMAC1 offset 0xC074
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8074
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int	mr3en		: 1;	// bit 31		Enable Matching Rule 3
-+		unsigned int	reserved3	: 4;	// bit 30:27
-+		unsigned int	mr3_action	: 5;	// bit 26:22	Matching Rule 3 action offset
-+		unsigned int	mr3hel		: 6;	// bit 21:16	match rule 3 hash entry size
-+		unsigned int	mr2en		: 1;	// bit 15		Enable Matching Rule 2
-+		unsigned int	reserved2	: 4;	// bit 14:11
-+		unsigned int	mr2_action	: 5;	// bit 10:6		Matching Rule 2 action offset
-+		unsigned int	mr2hel		: 6;	// bit 5:0		match rule 2 hash entry size
-+#else
-+		unsigned int	mr2hel		: 6;	// bit 5:0		match rule 2 hash entry size
-+		unsigned int	mr2_action	: 5;	// bit 10:6		Matching Rule 2 action offset
-+		unsigned int	reserved2	: 4;	// bit 14:11
-+		unsigned int	mr2en		: 1;	// bit 15		Enable Matching Rule 2
-+		unsigned int	mr3hel		: 6;	// bit 21:16	match rule 3 hash entry size
-+		unsigned int	mr3_action	: 5;	// bit 26:22	Matching Rule 3 action offset
-+		unsigned int	reserved1	: 4;	// bit 30:27
-+		unsigned int	mr3en		: 1;	// bit 31		Enable Matching Rule 3
-+#endif
-+	} bits;
-+} GMAC_HASH_ENABLE_REG1_T;
-+
-+
-+/**********************************************************************
-+ * GMAC Matching Rule Control Register 0
-+ * GMAC0 offset 0x8078
-+ * GMAC1 offset 0xC078
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8078
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int	l2			: 1;	// bit 31		L2 matching enable
-+		unsigned int	l3			: 1;	// bit 30		L3 matching enable
-+		unsigned int	l4			: 1;	// bit 29		L4 matching enable
-+		unsigned int	l7			: 1;	// bit 28		L7 matching enable
-+		unsigned int	port		: 1;	// bit 27		PORT ID matching enable
-+		unsigned int	priority	: 3;	// bit 26:24	priority if multi-rules matched
-+		unsigned int	da			: 1;	// bit 23		MAC DA enable
-+		unsigned int	sa			: 1;	// bit 22		MAC SA enable
-+		unsigned int	ether_type	: 1;	// bit 21		Ethernet type enable
-+		unsigned int	vlan		: 1;	// bit 20		VLAN ID enable
-+		unsigned int	pppoe		: 1;	// bit 19		PPPoE Session ID enable
-+		unsigned int	reserved1	: 3;	// bit 18:16
-+		unsigned int	ip_version	: 1;	// bit 15		0: IPV4, 1: IPV6
-+		unsigned int	ip_hdr_len	: 1;	// bit 14		IPV4 Header length
-+		unsigned int	flow_lable	: 1;	// bit 13		IPV6 Flow label
-+		unsigned int	tos_traffic	: 1;	// bit 12		IPV4 TOS or IPV6 Traffice Class
-+		unsigned int	reserved2	: 4;	// bit 11:8
-+		unsigned int	sprx		: 8;	// bit 7:0		Support Protocol Register 7:0
-+#else
-+		unsigned int	sprx		: 8;	// bit 7:0		Support Protocol Register 7:0
-+		unsigned int	reserved2	: 4;	// bit 11:8
-+		unsigned int	tos_traffic	: 1;	// bit 12		IPV4 TOS or IPV6 Traffice Class
-+		unsigned int	flow_lable	: 1;	// bit 13		IPV6 Flow label
-+		unsigned int	ip_hdr_len	: 1;	// bit 14		IPV4 Header length
-+		unsigned int	ip_version	: 1;	// bit 15		0: IPV4, 1: IPV6
-+		unsigned int	reserved1	: 3;	// bit 18:16
-+		unsigned int	pppoe		: 1;	// bit 19		PPPoE Session ID enable
-+		unsigned int	vlan		: 1;	// bit 20		VLAN ID enable
-+		unsigned int	ether_type	: 1;	// bit 21		Ethernet type enable
-+		unsigned int	sa			: 1;	// bit 22		MAC SA enable
-+		unsigned int	da			: 1;	// bit 23		MAC DA enable
-+		unsigned int	priority	: 3;	// bit 26:24	priority if multi-rules matched
-+		unsigned int	port		: 1;	// bit 27		PORT ID matching enable
-+		unsigned int	l7			: 1;	// bit 28		L7 matching enable
-+		unsigned int	l4			: 1;	// bit 29		L4 matching enable
-+		unsigned int	l3			: 1;	// bit 30		L3 matching enable
-+		unsigned int	l2			: 1;	// bit 31		L2 matching enable
-+#endif
-+	} bits;
-+} GMAC_MRxCR0_T;
-+
-+#define MR_L2_BIT			BIT(31)
-+#define MR_L3_BIT			BIT(30)
-+#define MR_L4_BIT			BIT(29)
-+#define MR_L7_BIT			BIT(28)
-+#define MR_PORT_BIT			BIT(27)
-+#define MR_PRIORITY_BIT		BIT(26)
-+#define MR_DA_BIT			BIT(23)
-+#define MR_SA_BIT			BIT(22)
-+#define MR_ETHER_TYPE_BIT	BIT(21)
-+#define MR_VLAN_BIT			BIT(20)
-+#define MR_PPPOE_BIT		BIT(19)
-+#define MR_IP_VER_BIT		BIT(15)
-+#define MR_IP_HDR_LEN_BIT	BIT(14)
-+#define MR_FLOW_LABLE_BIT	BIT(13)
-+#define MR_TOS_TRAFFIC_BIT	BIT(12)
-+#define MR_SPR_BIT(x)		BIT(x)
-+#define MR_SPR_BITS		0xff
-+
-+/**********************************************************************
-+ * GMAC Matching Rule Control Register 1
-+ * GMAC0 offset 0x807C
-+ * GMAC1 offset 0xC07C
-+ **********************************************************************/
-+ typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_807C
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int	sip			: 1;	// bit 31		Srce IP
-+		unsigned int	sip_netmask	: 7;	// bit 30:24	Srce IP net mask, number of mask bits
-+		unsigned int	dip			: 1;	// bit 23		Dest IP
-+		unsigned int	dip_netmask	: 7;	// bit 22:16	Dest IP net mask, number of mask bits
-+		unsigned int    l4_byte0_15	: 16;	// bit 15: 0
-+#else
-+		unsigned int    l4_byte0_15	: 16;	// bit 15: 0
-+		unsigned int	dip_netmask	: 7;	// bit 22:16	Dest IP net mask, number of mask bits
-+		unsigned int	dip			: 1;	// bit 23		Dest IP
-+		unsigned int	sip_netmask	: 7;	// bit 30:24	Srce IP net mask, number of mask bits
-+		unsigned int	sip			: 1;	// bit 31		Srce IP
-+#endif
-+	} bits;
-+} GMAC_MRxCR1_T;
-+
-+/**********************************************************************
-+ * GMAC Matching Rule Control Register 2
-+ * GMAC0 offset 0x8080
-+ * GMAC1 offset 0xC080
-+ **********************************************************************/
-+ typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_8080
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int    l4_byte16_24: 8;	// bit 31: 24
-+		unsigned int    l7_byte0_23	: 24;	// bit 23:0
-+#else
-+		unsigned int    l7_byte0_23	: 24;	// bit 23:0
-+		unsigned int    l4_byte16_24: 8;	// bit 31: 24
-+#endif
-+	} bits;
-+} GMAC_MRxCR2_T;
-+
-+
-+/**********************************************************************
-+ * GMAC Support registers
-+ * GMAC0 offset 0x80A8
-+ * GMAC1 offset 0xC0A8
-+ **********************************************************************/
-+ typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_80A8
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int    reserved: 21;	// bit 31:11
-+		unsigned int    swap	: 3;	// bit 10:8		Swap
-+		unsigned int    protocol: 8;	// bit 7:0		Supported protocol
-+#else
-+		unsigned int    protocol: 8;	// bit 7:0		Supported protocol
-+		unsigned int    swap	: 3;	// bit 10:8		Swap
-+		unsigned int    reserved: 21;	// bit 31:11
-+#endif
-+	} bits;
-+} GMAC_SPR_T;
-+
-+/**********************************************************************
-+ * GMAC_AHB_WEIGHT registers
-+ * GMAC0 offset 0x80C8
-+ * GMAC1 offset 0xC0C8
-+ **********************************************************************/
-+ typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_80C8
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int    reserved		: 7;	// 31:25
-+		unsigned int    tqDV_threshold	: 5;	// 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
-+		unsigned int    pre_req			: 5;	// 19:15 Rx Data Pre Request FIFO Threshold
-+		unsigned int    tx_weight		: 5;	// 14:10
-+		unsigned int    rx_weight		: 5;	// 9:5
-+		unsigned int    hash_weight		: 5;	// 4:0
-+#else
-+		unsigned int    hash_weight		: 5;	// 4:0
-+		unsigned int    rx_weight		: 5;	// 9:5
-+		unsigned int    tx_weight		: 5;	// 14:10
-+		unsigned int    pre_req			: 5;	// 19:15 Rx Data Pre Request FIFO Threshold
-+		unsigned int    tqDV_threshold	: 5;	// 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
-+		unsigned int    reserved		: 7;	// 31:25
-+#endif
-+	} bits;
-+} GMAC_AHB_WEIGHT_T;
-+/**********************************************************************
-+ * the register structure of GMAC
-+ **********************************************************************/
-+
-+/**********************************************************************
-+ * GMAC RX FLTR
-+ * GMAC0 Offset 0xA00C
-+ * GMAC1 Offset 0xE00C
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit1_000c
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int 				: 27;
-+		unsigned int error			:  1;	/* enable receive of all error frames */
-+		unsigned int promiscuous	:  1;   /* enable receive of all frames */
-+		unsigned int broadcast		:  1;	/* enable receive of broadcast frames */
-+		unsigned int multicast		:  1;	/* enable receive of multicast frames that pass multicast filter */
-+		unsigned int unicast		:  1;	/* enable receive of unicast frames that are sent to STA address */
-+#else
-+		unsigned int unicast		:  1;	/* enable receive of unicast frames that are sent to STA address */
-+		unsigned int multicast		:  1;	/* enable receive of multicast frames that pass multicast filter */
-+		unsigned int broadcast		:  1;	/* enable receive of broadcast frames */
-+		unsigned int promiscuous	:  1;   /* enable receive of all frames */
-+		unsigned int error			:  1;	/* enable receive of all error frames */
-+		unsigned int 				: 27;
-+#endif
-+	} bits;
-+} GMAC_RX_FLTR_T;
-+
-+/**********************************************************************
-+ * GMAC Configuration 0
-+ * GMAC0 Offset 0xA018
-+ * GMAC1 Offset 0xE018
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit1_0018
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int reserved		:  2;	// 31
-+		unsigned int port1_chk_classq :  1;	// 29
-+		unsigned int port0_chk_classq :  1;	// 28
-+		unsigned int port1_chk_toeq	:  1;	// 27
-+		unsigned int port0_chk_toeq	:  1;	// 26
-+		unsigned int port1_chk_hwq	:  1;	// 25
-+		unsigned int port0_chk_hwq	:  1;	// 24
-+		unsigned int rx_err_detect  :  1;	// 23
-+		unsigned int ipv6_exthdr_order: 1;	// 22
-+		unsigned int rxc_inv		:  1;	// 21
-+		unsigned int rgmm_edge		:  1;	// 20
-+        unsigned int rx_tag_remove  :  1;   /* 19: Remove Rx VLAN tag */
-+        unsigned int ipv6_rx_chksum :  1;   /* 18: IPv6 RX Checksum enable */
-+        unsigned int ipv4_rx_chksum :  1;   /* 17: IPv4 RX Checksum enable */
-+        unsigned int rgmii_en       :  1;   /* 16: RGMII in-band status enable */
-+		unsigned int tx_fc_en		:  1;	/* 15: TX flow control enable */
-+		unsigned int rx_fc_en		:  1;	/* 14: RX flow control enable */
-+		unsigned int sim_test		:  1;	/* 13: speed up timers in simulation */
-+		unsigned int dis_col		:  1;	/* 12: disable 16 collisions abort function */
-+		unsigned int dis_bkoff		:  1;	/* 11: disable back-off function */
-+		unsigned int max_len		:  3;	/* 8-10 maximum receive frame length allowed */
-+		unsigned int adj_ifg		:  4;	/* 4-7: adjust IFG from 96+/-56 */
-+        unsigned int flow_ctrl      :  1;   /* 3: flow control also trigged by Rx queues */
-+		unsigned int loop_back		:  1;	/* 2: transmit data loopback enable */
-+		unsigned int dis_rx			:  1;	/* 1: disable receive */
-+		unsigned int dis_tx			:  1;	/* 0: disable transmit */
-+#else
-+		unsigned int dis_tx			:  1;	/* 0: disable transmit */
-+		unsigned int dis_rx			:  1;	/* 1: disable receive */
-+		unsigned int loop_back		:  1;	/* 2: transmit data loopback enable */
-+        unsigned int flow_ctrl      :  1;   /* 3: flow control also trigged by Rx queues */
-+		unsigned int adj_ifg		:  4;	/* 4-7: adjust IFG from 96+/-56 */
-+		unsigned int max_len		:  3;	/* 8-10 maximum receive frame length allowed */
-+		unsigned int dis_bkoff		:  1;	/* 11: disable back-off function */
-+		unsigned int dis_col		:  1;	/* 12: disable 16 collisions abort function */
-+		unsigned int sim_test		:  1;	/* 13: speed up timers in simulation */
-+		unsigned int rx_fc_en		:  1;	/* 14: RX flow control enable */
-+		unsigned int tx_fc_en		:  1;	/* 15: TX flow control enable */
-+        unsigned int rgmii_en       :  1;   /* 16: RGMII in-band status enable */
-+        unsigned int ipv4_rx_chksum :  1;   /* 17: IPv4 RX Checksum enable */
-+        unsigned int ipv6_rx_chksum :  1;   /* 18: IPv6 RX Checksum enable */
-+        unsigned int rx_tag_remove  :  1;   /* 19: Remove Rx VLAN tag */
-+		unsigned int rgmm_edge		:  1;	// 20
-+		unsigned int rxc_inv		:  1;	// 21
-+		unsigned int ipv6_exthdr_order: 1;	// 22
-+		unsigned int rx_err_detect  :  1;	// 23
-+		unsigned int port0_chk_hwq	:  1;	// 24
-+		unsigned int port1_chk_hwq	:  1;	// 25
-+		unsigned int port0_chk_toeq	:  1;	// 26
-+		unsigned int port1_chk_toeq	:  1;	// 27
-+		unsigned int port0_chk_classq :  1;	// 28
-+		unsigned int port1_chk_classq :  1;	// 29
-+		unsigned int reserved		:  2;	// 31
-+#endif
-+	} bits;
-+} GMAC_CONFIG0_T;
-+
-+/**********************************************************************
-+ * GMAC Configuration 1
-+ * GMAC0 Offset 0xA01C
-+ * GMAC1 Offset 0xE01C
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit1_001c
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int reserved		: 16;
-+		unsigned int rel_threshold	: 8;	/* flow control release threshold */
-+		unsigned int set_threshold	: 8; 	/* flow control set threshold */
-+#else
-+		unsigned int set_threshold	: 8; 	/* flow control set threshold */
-+		unsigned int rel_threshold	: 8;	/* flow control release threshold */
-+		unsigned int reserved		: 16;
-+#endif
-+	} bits;
-+} GMAC_CONFIG1_T;
-+
-+#define GMAC_FLOWCTRL_SET_MAX		32
-+#define GMAC_FLOWCTRL_SET_MIN		0
-+#define GMAC_FLOWCTRL_RELEASE_MAX	32
-+#define GMAC_FLOWCTRL_RELEASE_MIN	0
-+
-+/**********************************************************************
-+ * GMAC Configuration 2
-+ * GMAC0 Offset 0xA020
-+ * GMAC1 Offset 0xE020
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit1_0020
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int rel_threshold	: 16;	/* flow control release threshold */
-+		unsigned int set_threshold	: 16; 	/* flow control set threshold */
-+#else
-+		unsigned int set_threshold	: 16; 	/* flow control set threshold */
-+		unsigned int rel_threshold	: 16;	/* flow control release threshold */
-+#endif
-+	} bits;
-+} GMAC_CONFIG2_T;
-+
-+/**********************************************************************
-+ * GMAC Configuration 3
-+ * GMAC0 Offset 0xA024
-+ * GMAC1 Offset 0xE024
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit1_0024
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int rel_threshold	: 16;	/* flow control release threshold */
-+		unsigned int set_threshold	: 16; 	/* flow control set threshold */
-+#else
-+		unsigned int set_threshold	: 16; 	/* flow control set threshold */
-+		unsigned int rel_threshold	: 16;	/* flow control release threshold */
-+#endif
-+	} bits;
-+} GMAC_CONFIG3_T;
-+
-+
-+/**********************************************************************
-+ * GMAC STATUS
-+ * GMAC0 Offset 0xA02C
-+ * GMAC1 Offset 0xE02C
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit1_002c
-+	{
-+#if (BIG_ENDIAN==1)
-+		unsigned int 				: 25;
-+		unsigned int mii_rmii		:  2;   /* PHY interface type */
-+		unsigned int reserved		:  1;
-+		unsigned int duplex			:  1;	/* duplex mode */
-+		unsigned int speed			:  2;	/* link speed(00->2.5M 01->25M 10->125M) */
-+		unsigned int link			:  1;	/* link status */
-+#else
-+		unsigned int link			:  1;	/* link status */
-+		unsigned int speed			:  2;	/* link speed(00->2.5M 01->25M 10->125M) */
-+		unsigned int duplex			:  1;	/* duplex mode */
-+		unsigned int reserved		:  1;
-+		unsigned int mii_rmii		:  2;   /* PHY interface type */
-+		unsigned int 				: 25;
-+#endif
-+	} bits;
-+} GMAC_STATUS_T;
-+
-+#define GMAC_SPEED_10			0
-+#define GMAC_SPEED_100			1
-+#define GMAC_SPEED_1000			2
-+
-+#define GMAC_PHY_MII			0
-+#define GMAC_PHY_GMII			1
-+#define GMAC_PHY_RGMII_100		2
-+#define GMAC_PHY_RGMII_1000		3
-+
-+/**********************************************************************
-+ * Queue Header
-+ *	(1) TOE Queue Header
-+ *	(2) Non-TOE Queue Header
-+ *	(3) Interrupt Queue Header
-+ *
-+ * memory Layout
-+ *	TOE Queue Header
-+ *	 0x60003000 +---------------------------+ 0x0000
-+ *				|     TOE Queue 0 Header	|
-+ *				|         8 * 4 Bytes	    |
-+ *				+---------------------------+ 0x0020
-+ *				|     TOE Queue 1 Header  	|
-+ *				|         8 * 4 Bytes		|
-+ *				+---------------------------+ 0x0040
-+ *				|   	......  			|
-+ *				|      						|
-+ *				+---------------------------+
-+ *
-+ *	Non TOE Queue Header
-+ *	 0x60002000 +---------------------------+ 0x0000
-+ *				|   Default Queue 0 Header  |
-+ *				|         2 * 4 Bytes		|
-+ *				+---------------------------+ 0x0008
-+ *				|   Default Queue 1 Header	|
-+ *				|         2 * 4 Bytes		|
-+ *				+---------------------------+ 0x0010
-+ *				|   Classification Queue 0	|
-+ *				|      	  2 * 4 Bytes		|
-+ *				+---------------------------+
-+ *				|   Classification Queue 1	|
-+ *				|      	  2 * 4 Bytes		|
-+ *				+---------------------------+ (n * 8 + 0x10)
-+ *				|   		...				|
-+ *				|      	  2 * 4 Bytes		|
-+ *				+---------------------------+ (13 * 8 + 0x10)
-+ *				|   Classification Queue 13	|
-+ *				|      	  2 * 4 Bytes		|
-+ *				+---------------------------+ 0x80
-+ * 				|      Interrupt Queue 0	|
-+ *				|      	  2 * 4 Bytes		|
-+ *				+---------------------------+
-+ * 				|      Interrupt Queue 1	|
-+ *				|      	  2 * 4 Bytes		|
-+ *				+---------------------------+
-+ * 				|      Interrupt Queue 2	|
-+ *				|      	  2 * 4 Bytes		|
-+ *				+---------------------------+
-+ * 				|      Interrupt Queue 3	|
-+ *				|      	  2 * 4 Bytes		|
-+ *				+---------------------------+
-+ *
-+ **********************************************************************/
-+#define TOE_QUEUE_HDR_ADDR(n)		(TOE_TOE_QUE_HDR_BASE + n * 32)
-+#define TOE_Q_HDR_AREA_END			(TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX+1))
-+#define TOE_DEFAULT_Q0_HDR_BASE		(TOE_NONTOE_QUE_HDR_BASE + 0x00)
-+#define TOE_DEFAULT_Q1_HDR_BASE		(TOE_NONTOE_QUE_HDR_BASE + 0x08)
-+#define TOE_CLASS_Q_HDR_BASE		(TOE_NONTOE_QUE_HDR_BASE + 0x10)
-+#define TOE_INTR_Q_HDR_BASE			(TOE_NONTOE_QUE_HDR_BASE + 0x80)
-+#define INTERRUPT_QUEUE_HDR_ADDR(n)	(TOE_INTR_Q_HDR_BASE + n * 8)
-+#define NONTOE_Q_HDR_AREA_END		(INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX+1))
-+/**********************************************************************
-+ * TOE Queue Header Word 0
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	unsigned int base_size;
-+} TOE_QHDR0_T;
-+
-+#define TOE_QHDR0_BASE_MASK 	(~0x0f)
-+
-+/**********************************************************************
-+ * TOE Queue Header Word 1
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_qhdr1
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int wptr			: 16;	// bit 31:16
-+		unsigned int rptr			: 16;	// bit 15:0
-+#else
-+		unsigned int rptr			: 16;	// bit 15:0
-+		unsigned int wptr			: 16;	// bit 31:16
-+#endif
-+	} bits;
-+} TOE_QHDR1_T;
-+
-+/**********************************************************************
-+ * TOE Queue Header Word 2
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_qhdr2
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int usd			: 1;	// bit 31		0: if no data assembled yet
-+		unsigned int ctl			: 1;	// bit 30		1: have control flag bits (except ack)
-+		unsigned int osq			: 1;	// bit 29		1: out of sequence
-+		unsigned int sat			: 1;	// bit 28		1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
-+		unsigned int ip_opt			: 1;	// bit 27		1: have IPV4 option or IPV6 Extension header
-+		unsigned int tcp_opt		: 1;	// bit 26		1: Have TCP option
-+		unsigned int abn			: 1;	// bit 25		1: Abnormal case Found
-+		unsigned int dack			: 1;	// bit 24		1: Duplicated ACK
-+		unsigned int reserved		: 7;	// bit 23:17
-+		unsigned int TotalPktSize	: 17;	// bit 16: 0	Total packet size
-+#else
-+		unsigned int TotalPktSize	: 17;	// bit 16: 0	Total packet size
-+		unsigned int reserved		: 7;	// bit 23:17
-+		unsigned int dack			: 1;	// bit 24		1: Duplicated ACK
-+		unsigned int abn			: 1;	// bit 25		1: Abnormal case Found
-+		unsigned int tcp_opt		: 1;	// bit 26		1: Have TCP option
-+		unsigned int ip_opt			: 1;	// bit 27		1: have IPV4 option or IPV6 Extension header
-+		unsigned int sat			: 1;	// bit 28		1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
-+		unsigned int osq			: 1;	// bit 29		1: out of sequence
-+		unsigned int ctl			: 1;	// bit 30		1: have control flag bits (except ack)
-+		unsigned int usd			: 1;	// bit 31		0: if no data assembled yet
-+#endif
-+	} bits;
-+} TOE_QHDR2_T;
-+
-+/**********************************************************************
-+ * TOE Queue Header Word 3
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	unsigned int seq_num;
-+} TOE_QHDR3_T;
-+
-+/**********************************************************************
-+ * TOE Queue Header Word 4
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	unsigned int ack_num;
-+} TOE_QHDR4_T;
-+
-+/**********************************************************************
-+ * TOE Queue Header Word 5
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_qhdr5
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int SeqCnt		: 16;	// bit 31:16
-+		unsigned int AckCnt		: 16;	// bit 15:0
-+#else
-+		unsigned int AckCnt		: 16;	// bit 15:0
-+		unsigned int SeqCnt		: 16;	// bit 31:16
-+#endif
-+	} bits;
-+} TOE_QHDR5_T;
-+
-+/**********************************************************************
-+ * TOE Queue Header Word 6
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_qhdr6
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int MaxPktSize	: 14;	// bit 31:18
-+		unsigned int iq_num		: 2;	// bit 17:16
-+		unsigned int WinSize	: 16;	// bit 15:0
-+#else
-+		unsigned int WinSize	: 16;	// bit 15:0
-+		unsigned int iq_num		: 2;	// bit 17:16
-+		unsigned int MaxPktSize	: 14;	// bit 31:18
-+#endif
-+	} bits;
-+} TOE_QHDR6_T;
-+
-+/**********************************************************************
-+ * TOE Queue Header Word 7
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_qhdr7
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int SeqThreshold	: 16;	// bit 31:16
-+		unsigned int AckThreshold	: 16;	// bit 15:0
-+#else
-+		unsigned int AckThreshold	: 16;	// bit 15:0
-+		unsigned int SeqThreshold	: 16;	// bit 31:16
-+#endif
-+	} bits;
-+} TOE_QHDR7_T;
-+
-+/**********************************************************************
-+ * TOE Queue Header
-+ **********************************************************************/
-+typedef struct
-+{
-+	TOE_QHDR0_T		word0;
-+	TOE_QHDR1_T		word1;
-+	TOE_QHDR2_T		word2;
-+	TOE_QHDR3_T		word3;
-+	TOE_QHDR4_T		word4;
-+	TOE_QHDR5_T		word5;
-+	TOE_QHDR6_T		word6;
-+	TOE_QHDR7_T		word7;
-+} TOE_QHDR_T;
-+
-+/**********************************************************************
-+ * NONTOE Queue Header Word 0
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	unsigned int base_size;
-+} NONTOE_QHDR0_T;
-+
-+#define NONTOE_QHDR0_BASE_MASK 	(~0x0f)
-+
-+/**********************************************************************
-+ * NONTOE Queue Header Word 1
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_nonqhdr1
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int wptr			: 16;	// bit 31:16
-+		unsigned int rptr			: 16;	// bit 15:0
-+#else
-+		unsigned int rptr			: 16;	// bit 15:0
-+		unsigned int wptr			: 16;	// bit 31:16
-+#endif
-+	} bits;
-+} NONTOE_QHDR1_T;
-+
-+/**********************************************************************
-+ * Non-TOE Queue Header
-+ **********************************************************************/
-+typedef struct
-+{
-+	NONTOE_QHDR0_T		word0;
-+	NONTOE_QHDR1_T		word1;
-+} NONTOE_QHDR_T;
-+
-+/**********************************************************************
-+ * Interrupt Queue Header Word 0
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_intrqhdr0
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int wptr		: 16;	// bit 31:16	Write Pointer where hw stopped
-+		unsigned int win_size	: 16;	// bit 15:0 	Descriptor Ring Size
-+#else
-+		unsigned int win_size	: 16;	// bit 15:0 	Descriptor Ring Size
-+		unsigned int wptr		: 16;	// bit 31:16	Write Pointer where hw stopped
-+#endif
-+	} bits;
-+} INTR_QHDR0_T;
-+
-+/**********************************************************************
-+ * Interrupt Queue Header Word 1
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_intrqhdr1
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int ctl			: 1;	// bit 31		1: have control flag bits (except ack)
-+		unsigned int osq			: 1;	// bit 30		1: out of sequence
-+		unsigned int sat			: 1;	// bit 29		1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
-+		unsigned int ip_opt			: 1;	// bit 28		1: have IPV4 option or IPV6 Extension header
-+		unsigned int tcp_opt		: 1;	// bit 27		1: Have TCP option
-+		unsigned int abn			: 1;	// bit 26		1: Abnormal case Found
-+		unsigned int dack			: 1;	// bit 25		1: Duplicated ACK
-+		unsigned int tcp_qid		: 8;	// bit 24:17	TCP Queue ID
-+		unsigned int TotalPktSize	: 17;	// bit 16: 0	Total packet size
-+#else
-+		unsigned int TotalPktSize	: 17;	// bit 16: 0	Total packet size
-+		unsigned int tcp_qid		: 8;	// bit 24:17	TCP Queue ID
-+		unsigned int dack			: 1;	// bit 25		1: Duplicated ACK
-+		unsigned int abn			: 1;	// bit 26		1: Abnormal case Found
-+		unsigned int tcp_opt		: 1;	// bit 27		1: Have TCP option
-+		unsigned int ip_opt			: 1;	// bit 28		1: have IPV4 option or IPV6 Extension header
-+		unsigned int sat			: 1;	// bit 29		1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
-+		unsigned int osq			: 1;	// bit 30		1: out of sequence
-+		unsigned int ctl			: 1;	// bit 31		1: have control flag bits (except ack)
-+#endif
-+	} bits;
-+} INTR_QHDR1_T;
-+
-+/**********************************************************************
-+ * Interrupt Queue Header Word 2
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	unsigned int seq_num;
-+} INTR_QHDR2_T;
-+
-+/**********************************************************************
-+ * Interrupt Queue Header Word 3
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	unsigned int ack_num;
-+} INTR_QHDR3_T;
-+
-+/**********************************************************************
-+ * Interrupt Queue Header Word 4
-+ **********************************************************************/
-+typedef union
-+{
-+	unsigned int bits32;
-+	struct bit_intrqhdr4
-+	{
-+#if (BIG_ENDIAN==1)
-+
-+		unsigned int SeqCnt		: 16;	// bit 31:16	Seq# change since last seq# intr.
-+		unsigned int AckCnt		: 16;	// bit 15:0     Ack# change since last ack# intr.
-+#else
-+		unsigned int AckCnt		: 16;	// bit 15:0		Ack# change since last ack# intr.
-+		unsigned int SeqCnt		: 16;	// bit 31:16	Seq# change since last seq# intr.
-+#endif
-+	} bits;
-+} INTR_QHDR4_T;
-+
-+/**********************************************************************
-+ * Interrupt Queue Header
-+ **********************************************************************/
-+typedef struct
-+{
-+	INTR_QHDR0_T		word0;
-+	INTR_QHDR1_T		word1;
-+	INTR_QHDR2_T		word2;
-+	INTR_QHDR3_T		word3;
-+	INTR_QHDR4_T		word4;
-+	unsigned int		word5;
-+	unsigned int		word6;
-+	unsigned int		word7;
-+} INTR_QHDR_T;
-+
-+/**********************************************************************
-+ * GMAC Conf
-+ **********************************************************************/
-+typedef struct gmac_conf {
-+	struct net_device *dev;
-+	int portmap;
-+	int vid;
-+	int flag;     /* 1: active  0: non-active */
-+} sys_gmac_conf;
-+
-+/**********************************************************************
-+ * GMAC private data
-+ **********************************************************************/
-+typedef struct {
-+	unsigned int		rwptr_reg;
-+	unsigned int		desc_base;
-+	unsigned int		total_desc_num;
-+	unsigned short		finished_idx;
-+	GMAC_TXDESC_T		*curr_tx_desc;
-+	GMAC_TXDESC_T		*curr_finished_desc;
-+	struct sk_buff		*tx_skb[TX_DESC_NUM];
-+	unsigned long		total_sent;
-+	unsigned long		total_finished;
-+	unsigned long		intr_cnt;
-+} GMAC_SWTXQ_T;
-+
-+typedef struct {
-+	unsigned int		desc_base;
-+	unsigned long 		eof_cnt;
-+} GMAC_HWTXQ_T;
-+
-+typedef struct gmac_private{
-+	struct net_device	*dev;
-+	unsigned int		existed;
-+	unsigned int		port_id;	// 0 or 1
-+	unsigned int		base_addr;
-+	unsigned int		dma_base_addr;
-+	unsigned char		*mac_addr1;
-+	unsigned char		*mac_addr2;
-+	unsigned int		swtxq_desc_base;
-+	unsigned int		hwtxq_desc_base;
-+	GMAC_SWTXQ_T		swtxq[TOE_SW_TXQ_NUM];
-+	GMAC_HWTXQ_T		hwtxq[TOE_HW_TXQ_NUM];
-+	NONTOE_QHDR_T		*default_qhdr;
-+	unsigned int		default_desc_base;
-+	unsigned int		default_desc_num;
-+	unsigned int		rx_curr_desc;
-+	DMA_RWPTR_T			rx_rwptr;
-+	struct sk_buff		*curr_rx_skb;
-+	dma_addr_t			default_desc_base_dma;
-+	dma_addr_t			swtxq_desc_base_dma;
-+	dma_addr_t			hwtxq_desc_base_dma;
-+	unsigned int		irq;
-+	unsigned int		flow_control_enable	;
-+	unsigned int		pre_phy_status;
-+	unsigned int		full_duplex_cfg;
-+	unsigned int		speed_cfg;
-+	unsigned int		auto_nego_cfg;
-+	unsigned int		full_duplex_status;
-+	unsigned int		speed_status;
-+	unsigned int		phy_mode;	/* 0->MII 1->GMII 2->RGMII(10/100) 3->RGMII(1000) */
-+	unsigned int		phy_addr;
-+	unsigned int		intr0_enabled;	// 1: enabled
-+	unsigned int		intr1_enabled;	// 1: enabled
-+	unsigned int		intr2_enabled;	// 1: enabled
-+	unsigned int		intr3_enabled;	// 1: enabled
-+	unsigned int		intr4_enabled;	// 1: enabled
-+//	unsigned int		intr4_enabled_1;	// 1: enabled
-+	unsigned int		intr0_selected;	// 1: selected
-+	unsigned int		intr1_selected;	// 1: selected
-+	unsigned int		intr2_selected;	// 1: selected
-+	unsigned int		intr3_selected;	// 1: selected
-+	unsigned int		intr4_selected;	// 1: selected
-+	// void 				(*gmac_rcv_handler)(struct sk_buff *, int);
-+	struct net_device_stats ifStatics;
-+	unsigned long		txDerr_cnt[GMAC_NUM];
-+	unsigned long		txPerr_cnt[GMAC_NUM];
-+	unsigned long		RxDerr_cnt[GMAC_NUM];
-+	unsigned long		RxPerr_cnt[GMAC_NUM];
-+	unsigned int		isr_rx_cnt;
-+	unsigned int		isr_tx_cnt;
-+	unsigned long		rx_discard;
-+	unsigned long		rx_error;
-+	unsigned long		rx_mcast;
-+	unsigned long		rx_bcast;
-+	unsigned long		rx_status_cnt[8];
-+	unsigned long		rx_chksum_cnt[8];
-+	unsigned long		rx_sta1_ucast;	// for STA 1 MAC Address
-+	unsigned long		rx_sta2_ucast;	// for STA 2 MAC Address
-+	unsigned long		mib_full_cnt;
-+	unsigned long		rx_pause_on_cnt;
-+	unsigned long		tx_pause_on_cnt;
-+	unsigned long		rx_pause_off_cnt;
-+	unsigned long		tx_pause_off_cnt;
-+	unsigned long		rx_overrun_cnt;
-+	unsigned long		status_changed_cnt;
-+	unsigned long		default_q_cnt;
-+	unsigned long		hw_fq_empty_cnt;
-+	unsigned long		sw_fq_empty_cnt;
-+	unsigned long		default_q_intr_cnt;
-+	pid_t               thr_pid;
-+	wait_queue_head_t   thr_wait;
-+	struct completion   thr_exited;
-+    spinlock_t          lock;
-+    int                 time_to_die;
-+    int					operation;
-+#ifdef SL351x_GMAC_WORKAROUND
-+    unsigned long		short_frames_cnt;
-+#endif
-+}GMAC_INFO_T ;
-+
-+typedef struct toe_private {
-+	unsigned int	swfq_desc_base;
-+	unsigned int	hwfq_desc_base;
-+	unsigned int	hwfq_buf_base;
-+//	unsigned int	toe_desc_base[TOE_TOE_QUEUE_NUM];
-+//	unsigned int	toe_desc_num;
-+//	unsigned int	class_desc_base;
-+//	unsigned int	class_desc_num;
-+//	unsigned int	intr_desc_base;
-+//	unsigned int	intr_desc_num;
-+//	unsigned int	intr_buf_base;
-+	DMA_RWPTR_T		fq_rx_rwptr;
-+	GMAC_INFO_T		gmac[GMAC_NUM];
-+	dma_addr_t		sw_freeq_desc_base_dma;
-+	dma_addr_t		hw_freeq_desc_base_dma;
-+	dma_addr_t		hwfq_buf_base_dma;
-+	dma_addr_t		hwfq_buf_end_dma;
-+//	dma_addr_t		toe_desc_base_dma[TOE_TOE_QUEUE_NUM];
-+//	dma_addr_t		class_desc_base_dma;
-+//	dma_addr_t		intr_desc_base_dma;
-+//	dma_addr_t		intr_buf_base_dma;
-+//	unsigned long	toe_iq_intr_full_cnt[TOE_INTR_QUEUE_NUM];
-+//	unsigned long	toe_iq_intr_cnt[TOE_INTR_QUEUE_NUM];
-+//	unsigned long	toe_q_intr_full_cnt[TOE_TOE_QUEUE_NUM];
-+//	unsigned long	class_q_intr_full_cnt[TOE_CLASS_QUEUE_NUM];
-+//	unsigned long	class_q_intr_cnt[TOE_CLASS_QUEUE_NUM];
-+} TOE_INFO_T;
-+
-+extern TOE_INFO_T toe_private_data;
-+
-+#define GMAC_PORT0	0
-+#define GMAC_PORT1	1
-+/**********************************************************************
-+ * PHY Definition
-+ **********************************************************************/
-+#define HPHY_ADDR   			0x01
-+#define GPHY_ADDR   			0x02
-+
-+enum phy_state
-+{
-+    LINK_DOWN   = 0,
-+    LINK_UP     = 1
-+};
-+
-+/* transmit timeout value */
-+
-+#endif //_GMAC_SL351x_H
---- /dev/null
-+++ b/include/asm-arm/arch-sl2312/sl351x_hash_cfg.h
-@@ -0,0 +1,365 @@
-+/*-----------------------------------------------------------------------------------
-+*	sl351x_hash_cfg.h
-+*
-+*	Description:
-+*	
-+*	History:
-+*
-+*	9/14/2005	Gary Chen	Create
-+*
-+*-------------------------------------------------------------------------------------*/
-+#ifndef _SL351x_HASH_CFG_H_
-+#define _SL351x_HASH_CFG_H_	1
-+
-+// #define NAT_DEBUG_MSG	1
-+// #define DEBUG_NAT_MIXED_HW_SW_TX	1
-+#ifdef DEBUG_NAT_MIXED_HW_SW_TX
-+	// #define NAT_DEBUG_LAN_HASH_TIMEOUT	1
-+	// #define NAT_DEBUG_WAN_HASH_TIMEOUT	1
-+#endif
-+
-+#define IPIV(a,b,c,d)		((a<<24)+(b<<16)+(c<<8)+d)
-+#define	IPIV1(a)			((a>>24)&0xff)
-+#define	IPIV2(a)			((a>>16)&0xff)
-+#define IPIV3(a)			((a>>8)&0xff)
-+#define IPIV4(a)			((a)&0xff)
-+
-+#define HASH_MAX_BYTES			64	// 128
-+#define HASH_ACTION_DWORDS		9
-+#define HASH_MAX_DWORDS			(HASH_MAX_BYTES / sizeof(u32))
-+#define HASH_MAX_KEY_DWORD		(HASH_MAX_DWORDS - HASH_ACTION_DWORDS)
-+#define HASH_INIT_KEY			0x534C4F52
-+#define HASH_BITS				12	// 12 : Normal, 7: Simulation
-+#define HASH_TOTAL_ENTRIES		(1 << HASH_BITS)
-+#define HASH_MAX_ENTRIES		(1 << 12)
-+#define HASH_TOE_ENTRIES		(HASH_TOTAL_ENTRIES >> 5)
-+#define HASH_BITS_MASK			((1 << HASH_BITS) - 1)
-+
-+#define hash_lock(lock)			// spin_lock_bh(lock)
-+#define hash_unlock(lock)		// spin_unlock_bh(lock)
-+
-+/*----------------------------------------------------------------------
-+ *  special macro
-+ ----------------------------------------------------------------------*/
-+#define HASH_PUSH_WORD(cp, data)	{*cp++ = (((u16)(data))     ) & 0xff; 	\
-+							 		*cp++ = (((u16)(data)) >> 8) & 0xff;} 
-+#define HASH_PUSH_DWORD(cp, data)	{*cp++ = (u8)(((u32)(data))      ) & 0xff;	\
-+							  		*cp++ = (u8)(((u32)(data)) >>  8) & 0xff;	\
-+							  		*cp++ = (u8)(((u32)(data)) >> 16) & 0xff;	\
-+							  		*cp++ = (u8)(((u32)(data)) >> 24) & 0xff;}
-+#define HASH_PUSH_BYTE(cp, data)	{*cp++ = ((u8)(data)) & 0xff;}
-+
-+/*----------------------------------------------------------------------
-+ *  key
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	u8		port;
-+	u16		Ethertype;
-+	u8		da[6];
-+	u8		sa[6];
-+	u16		pppoe_sid;	
-+	u16		vlan_id;	
-+	u8		ipv4_hdrlen;	
-+	u8		ip_tos;	
-+	u8		ip_protocol;	
-+	u32		ipv6_flow_label;
-+	u8		sip[16];
-+	u8		dip[16];
-+	//__u32			sip[4];
-+	//__u32			dip[4];
-+	u8		l4_bytes[24];
-+	u8		l7_bytes[24];
-+	u8		ipv6;	// 1: IPv6, 0: IPV4
-+} ENTRY_KEY_T;
-+
-+/*----------------------------------------------------------------------
-+ *  key for NAT
-+ *	Note: packed
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	u16		Ethertype;		// not used
-+	u8		port_id;
-+	u8		rule_id;
-+	u8		ip_protocol;
-+	u8		reserved1;		// ip_tos, not used
-+	u16		reserved2;		// not used
-+	u32		sip;
-+	u32		dip;
-+	u16		sport;
-+	u16		dport;
-+} NAT_KEY_T;
-+
-+#define NAT_KEY_DWORD_SIZE	(sizeof(NAT_KEY_T)/sizeof(u32))
-+#define NAT_KEY_SIZE		(sizeof(NAT_KEY_T))
-+
-+/*----------------------------------------------------------------------
-+ *  key for NAT
-+ *	Note: packed
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	u16		Ethertype;		// not used
-+	u8		port_id;
-+	u8		rule_id;
-+	u8		ip_protocol;
-+	u8		reserved1;		// ip_tos, not used
-+	u16		reserved2;		// not used
-+	u32		sip;
-+	u32		dip;
-+	u16		reserved3;
-+	u16		protocol;
-+	u16		reserved4;
-+	u16		call_id;
-+} GRE_KEY_T;
-+
-+#define GRE_KEY_DWORD_SIZE	(sizeof(GRE_KEY_T)/sizeof(u32))
-+#define GRE_KEY_SIZE		(sizeof(GRE_KEY_T))
-+/*----------------------------------------------------------------------
-+ *  key present or not
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	u32		port			: 1;
-+	u32		Ethertype		: 1;
-+	u32		da				: 1;
-+	u32		sa				: 1;
-+	u32		pppoe_sid		: 1;	
-+	u32		vlan_id			: 1;	
-+	u32		ipv4_hdrlen		: 1;	
-+	u32		ip_tos			: 1;
-+	u32		ip_protocol		: 1;	
-+	u32		ipv6_flow_label	: 1;
-+	u32		sip				: 1;
-+	u32		dip				: 1;
-+	u32		l4_bytes_0_3	: 1;
-+	u32		l4_bytes_4_7	: 1;
-+	u32		l4_bytes_8_11	: 1;
-+	u32		l4_bytes_12_15	: 1;
-+	u32		l4_bytes_16_19	: 1;
-+	u32		l4_bytes_20_23	: 1;
-+	u32		l7_bytes_0_3	: 1;
-+	u32		l7_bytes_4_7	: 1;
-+	u32		l7_bytes_8_11	: 1;
-+	u32		l7_bytes_12_15	: 1;
-+	u32		l7_bytes_16_19	: 1;
-+	u32		l7_bytes_20_23	: 1;
-+	u32		reserved		: 8;
-+} KEY_FIELD_T;
-+
-+/*----------------------------------------------------------------------
-+ *  action
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	u32		reserved0	: 5;	// bit 0:4
-+	u32		pppoe		: 2;	// bit 5:6
-+	u32		vlan		: 2;	// bit 7:8
-+	u32		sa			: 1;	// bit 9
-+	u32		da			: 1;	// bit 10
-+	u32		Dport		: 1;	// bit 11
-+	u32		Sport		: 1;	// bit 12
-+	u32		Dip			: 1;	// bit 13
-+	u32		Sip			: 1;	// bit 14
-+	u32		sw_id		: 1;	// bit 15
-+	u32		frag		: 1;	// bit 16
-+	u32		option		: 1;	// bit 17
-+	u32		ttl_0		: 1;	// bit 18
-+	u32		ttl_1		: 1;	// bit 19
-+	u32		mtu			: 1;	// bit 20
-+	u32		exception	: 1;	// bit 21
-+	u32		srce_qid	: 1;	// bit 22
-+	u32		discard		: 1;	// bit 23
-+	u32		dest_qid	: 8;	// bit 24:31
-+} ENTRY_ACTION_T;
-+
-+#define ACTION_DISCARD_BIT		BIT(23)
-+#define ACTION_SRCE_QID_BIT		BIT(22)
-+#define ACTION_EXCEPTION_BIT	BIT(21)
-+#define ACTION_MTU_BIT			BIT(20)
-+#define ACTION_TTL_1_BIT		BIT(19)
-+#define ACTION_TTL_0_BIT		BIT(18)
-+#define ACTION_IP_OPTION		BIT(17)
-+#define ACTION_FRAG_BIT			BIT(16)
-+#define ACTION_SWID_BIT			BIT(15)
-+#define ACTION_SIP_BIT			BIT(14)
-+#define ACTION_DIP_BIT			BIT(13)
-+#define ACTION_SPORT_BIT		BIT(12)
-+#define ACTION_DPORT_BIT		BIT(11)
-+#define ACTION_DA_BIT			BIT(10)
-+#define ACTION_SA_BIT			BIT(9)
-+#define ACTION_VLAN_DEL_BIT		BIT(8)
-+#define ACTION_VLAN_INS_BIT		BIT(7)
-+#define ACTION_PPPOE_DEL_BIT	BIT(6)
-+#define ACTION_PPPOE_INS_BIT	BIT(5)
-+#define ACTION_L4_THIRD_BIT		BIT(4)
-+#define ACTION_L4_FOURTH_BIT	BIT(3)
-+
-+#define NAT_ACTION_BITS			(ACTION_SRCE_QID_BIT  | ACTION_EXCEPTION_BIT |	\
-+								ACTION_TTL_1_BIT | ACTION_TTL_0_BIT | 			\
-+								ACTION_IP_OPTION | ACTION_FRAG_BIT |			\
-+								ACTION_DA_BIT | ACTION_SA_BIT)
-+#define NAT_LAN2WAN_ACTIONS		(NAT_ACTION_BITS | ACTION_SIP_BIT | ACTION_SPORT_BIT)
-+#define NAT_WAN2LAN_ACTIONS		(NAT_ACTION_BITS | ACTION_DIP_BIT | ACTION_DPORT_BIT)
-+#define NAT_PPPOE_LAN2WAN_ACTIONS	(NAT_LAN2WAN_ACTIONS | ACTION_PPPOE_INS_BIT)
-+#define NAT_PPPOE_WAN2LAN_ACTIONS	(NAT_WAN2LAN_ACTIONS | ACTION_PPPOE_DEL_BIT)
-+#define NAT_PPTP_LAN2WAN_ACTIONS	(NAT_ACTION_BITS | ACTION_SIP_BIT | ACTION_L4_FOURTH_BIT)
-+#define NAT_PPTP_WAN2LAN_ACTIONS	(NAT_ACTION_BITS | ACTION_DIP_BIT | ACTION_L4_FOURTH_BIT)
-+#define NAT_PPPOE_PPTP_LAN2WAN_ACTIONS	(NAT_PPTP_LAN2WAN_ACTIONS | ACTION_PPPOE_INS_BIT)
-+#define NAT_PPPOE_PPTP_WAN2LAN_ACTIONS	(NAT_PPTP_WAN2LAN_ACTIONS | ACTION_PPPOE_DEL_BIT)
-+								
-+/*----------------------------------------------------------------------
-+ *  parameter
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	u8		da[6];
-+	u8		sa[6];
-+	u16		vlan;	
-+	u16  	pppoe;	
-+	u32		Sip;
-+	u32		Dip;
-+	u16  	Sport;	
-+	u16  	Dport;	
-+	u16  	sw_id;	
-+	u16  	mtu;	
-+} ENTRY_PARAM_T;
-+
-+/*----------------------------------------------------------------------
-+ *  Hash Entry
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	char			rule;
-+	ENTRY_KEY_T		key;
-+	KEY_FIELD_T		key_present;
-+	ENTRY_ACTION_T	action;
-+	ENTRY_PARAM_T	param;
-+	int				index;
-+	int				total_dwords;
-+} HASH_ENTRY_T;
-+
-+/*----------------------------------------------------------------------
-+ *  NAT Hash Entry
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	short	counter;
-+	short	interval;
-+} HASH_TIMEOUT_T;
-+
-+/*----------------------------------------------------------------------
-+ *  NAT Hash Entry for TCP/UDP protocol
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	NAT_KEY_T			key;
-+	union {
-+		u32				dword;
-+		ENTRY_ACTION_T	bits;
-+	} action;
-+	ENTRY_PARAM_T		param;
-+	HASH_TIMEOUT_T		tmo;	// used by software only, to use memory space efficiently
-+} NAT_HASH_ENTRY_T;
-+
-+#define NAT_HASH_ENTRY_SIZE		(sizeof(NAT_HASH_ENTRY_T))
-+
-+/*----------------------------------------------------------------------
-+ *  GRE Hash Entry for PPTP/GRE protocol
-+ ----------------------------------------------------------------------*/
-+typedef struct {
-+	GRE_KEY_T			key;
-+	union {
-+		u32				dword;
-+		ENTRY_ACTION_T	bits;
-+	} action;
-+	ENTRY_PARAM_T		param;
-+	HASH_TIMEOUT_T		tmo;	// used by software only, to use memory space efficiently
-+} GRE_HASH_ENTRY_T;
-+
-+#define GRE_HASH_ENTRY_SIZE		(sizeof(GRE_HASH_ENTRY_T))
-+
-+/*----------------------------------------------------------------------
-+ *  External Variables
-+ ----------------------------------------------------------------------*/
-+extern char				hash_tables[HASH_TOTAL_ENTRIES][HASH_MAX_BYTES] __attribute__ ((aligned(16)));
-+extern u32				hash_nat_owner_bits[HASH_TOTAL_ENTRIES/32];
-+/*----------------------------------------------------------------------
-+* hash_get_valid_flag
-+*----------------------------------------------------------------------*/
-+static inline int hash_get_valid_flag(int index)
-+{
-+	volatile u32 *hash_valid_bits_ptr = (volatile u32 *)TOE_V_BIT_BASE;
-+
-+#ifdef SL351x_GMAC_WORKAROUND
-+	if (index >= (0x80 * 8) && index < (0x8c * 8))
-+		return 1;
-+#endif	
-+	return (hash_valid_bits_ptr[index/32] & (1 << (index %32)));
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_get_nat_owner_flag
-+*----------------------------------------------------------------------*/
-+static inline int hash_get_nat_owner_flag(int index)
-+{
-+	return (hash_nat_owner_bits[index/32] & (1 << (index %32)));
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_validate_entry
-+*----------------------------------------------------------------------*/
-+static inline void hash_validate_entry(int index)
-+{
-+	volatile u32	*hash_valid_bits_ptr = (volatile u32 *)TOE_V_BIT_BASE;
-+	register int	ptr = index/32, bits = 1 << (index %32);
-+	
-+	hash_valid_bits_ptr[ptr] |= bits;
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_invalidate_entry
-+*----------------------------------------------------------------------*/
-+static inline void hash_invalidate_entry(int index)
-+{
-+	volatile u32 *hash_valid_bits_ptr = (volatile u32 *)TOE_V_BIT_BASE;
-+	register int	ptr = index/32, bits = 1 << (index %32);
-+	
-+	hash_valid_bits_ptr[ptr] &= ~(bits);
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_nat_enable_owner
-+*----------------------------------------------------------------------*/
-+static inline void hash_nat_enable_owner(int index)
-+{
-+	hash_nat_owner_bits[index/32] |= (1 << (index % 32));
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_nat_disable_owner
-+*----------------------------------------------------------------------*/
-+static inline void hash_nat_disable_owner(int index)
-+{
-+	hash_nat_owner_bits[index/32] &= ~(1 << (index % 32));
-+}
-+
-+/*----------------------------------------------------------------------
-+* hash_get_entry
-+*----------------------------------------------------------------------*/
-+static inline void *hash_get_entry(int index)
-+{
-+	return (void*) &hash_tables[index][0];
-+}
-+
-+/*----------------------------------------------------------------------
-+* Functions
-+*----------------------------------------------------------------------*/
-+extern int hash_add_entry(HASH_ENTRY_T *entry);
-+extern void sl351x_hash_init(void);
-+extern void hash_set_valid_flag(int index, int valid);
-+extern void hash_set_nat_owner_flag(int index, int valid);
-+extern void *hash_get_entry(int index);
-+extern int hash_build_keys(u32 *destp, HASH_ENTRY_T *entry);
-+extern void hash_build_nat_keys(u32 *destp, HASH_ENTRY_T *entry);
-+extern int hash_write_entry(HASH_ENTRY_T *entry, u8 *key);
-+extern int hash_add_entry(HASH_ENTRY_T *entry);
-+extern	u16 hash_crc16(u16 crc, u8 *datap, u32 len);
-+extern	u16 hash_gen_crc16(u8 *datap, u32 len);
-+
-+#endif // _SL351x_HASH_CFG_H_
-+
-+
-+
---- /dev/null
-+++ b/include/asm-arm/arch-sl2312/sl351x_nat_cfg.h
-@@ -0,0 +1,211 @@
-+/**************************************************************************
-+* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.                
-+*--------------------------------------------------------------------------
-+*	sl_nat_cfg.h
-+*
-+*	Description:
-+*		- Define the Device Control Commands for NAT Configuration
-+*	
-+*	History:
-+*
-+*	4/28/2006	Gary Chen	Create
-+*
-+*-----------------------------------------------------------------------------*/
-+#ifndef _SL351x_NAT_CFG_H_
-+#define _SL351x_NAT_CFG_H_	1
-+
-+/*----------------------------------------------------------------------
-+* Confiuration
-+*----------------------------------------------------------------------*/
-+#ifdef CONFIG_NETFILTER
-+#define CONFIG_SL351x_NAT			1
-+#undef CONFIG_SL351x_NAT
-+#undef CONFIG_SL351x_SYSCTL
-+#endif
-+#define CONFIG_NAT_MAX_IP_NUM		4	// per device (eth0 or eth1)
-+#define CONFIG_NAT_MAX_XPORT		64
-+#define CONFIG_NAT_MAX_WRULE		16	// per Queue
-+#define CONFIG_NAT_TXQ_NUM			4
-+/*----------------------------------------------------------------------
-+* Command set
-+*----------------------------------------------------------------------*/
-+#define SIOCDEVSL351x	SIOCDEVPRIVATE	// 0x89F0
-+#define NATSSTATUS		0
-+#define NATGSTATUS		1
-+#define NATSETPORT		2
-+#define NATGETPORT		3
-+#define NATADDIP		4
-+#define NATDELIP		5
-+#define NATGETIP		6
-+#define NATAXPORT		7
-+#define NATDXPORT		8
-+#define NATGXPORT		9
-+#define NATSWEIGHT		10
-+#define NATGWEIGHT		11
-+#define NATAWRULE		12
-+#define NATDWRULE		13
-+#define NATGWRULE		14
-+#define NATSDEFQ		15
-+#define NATGDEFQ		16
-+#define NATRMIPCFG		17		// remove IP config
-+#define NATTESTENTRY	18
-+#define NATSETMEM		19
-+#define NATSHOWMEM		20
-+/*----------------------------------------------------------------------
-+* Command Structure
-+*----------------------------------------------------------------------*/
-+// Common Header
-+typedef struct {
-+	unsigned short		cmd;	// command ID
-+	unsigned short		len;	// data length, excluding this header
-+} NATCMD_HDR_T;
-+
-+// NATSSTATUS & NATGSTATUS commands
-+typedef struct {
-+	unsigned char		enable;
-+} NAT_STATUS_T;	
-+
-+// NATSETPORT & NATGETPORT commands
-+typedef struct {
-+	unsigned char		portmap;
-+} NAT_PORTCFG_T;
-+
-+typedef struct {
-+	unsigned int		ipaddr;
-+	unsigned int		netmask;
-+} NAT_IP_ENTRY_T;
-+
-+// NATADDIP & NATDELIP commands
-+typedef struct {
-+	NAT_IP_ENTRY_T	entry;
-+} NAT_IPCFG_T;
-+
-+// NATGETIP command
-+typedef struct {
-+	unsigned int	total;
-+	NAT_IP_ENTRY_T	entry[CONFIG_NAT_MAX_IP_NUM];
-+} NAT_IPCFG_ALL_T;
-+
-+typedef struct {
-+	unsigned int		protocol;
-+	unsigned short		sport_start;
-+	unsigned short		sport_end;
-+	unsigned short		dport_start;
-+	unsigned short		dport_end;
-+} NAT_XPORT_ENTRY_T;
-+
-+// NATAXPORT & NATDXPORT Commands
-+typedef struct {
-+	NAT_XPORT_ENTRY_T	entry;
-+} NAT_XPORT_T;
-+
-+// NATGXPORT Command
-+typedef struct {
-+	unsigned int		total;
-+	NAT_XPORT_ENTRY_T	entry[CONFIG_NAT_MAX_XPORT];
-+} NAT_XPORT_ALL_T;
-+
-+// NATSWEIGHT & NATGWEIGHT Commands
-+typedef struct {
-+	unsigned char		weight[CONFIG_NAT_TXQ_NUM];
-+} NAT_WEIGHT_T;
-+
-+typedef struct {
-+	unsigned int		protocol;
-+	unsigned int		sip_start;
-+	unsigned int		sip_end;
-+	unsigned int		dip_start;
-+	unsigned int		dip_end;
-+	unsigned short		sport_start;
-+	unsigned short		sport_end;
-+	unsigned short		dport_start;
-+	unsigned short		dport_end;
-+} NAT_WRULE_ENTRY_T;	
-+
-+// NATAWRULE & NATDWRULE Commands
-+typedef struct {
-+	unsigned int		qid;
-+	NAT_WRULE_ENTRY_T	entry;
-+} NAT_WRULE_T;
-+
-+// NATGWRULE Command
-+typedef struct {
-+	unsigned int		total;
-+	NAT_WRULE_ENTRY_T	entry[CONFIG_NAT_MAX_WRULE];
-+} NAT_WRULE_ALL_T;
-+
-+// NATSDEFQ & NATGDEFQ commands
-+typedef struct {
-+	unsigned int		qid;
-+} NAT_QUEUE_T;	
-+
-+// NATTESTENTRY 
-+typedef struct {
-+	u_int16_t		cmd;	// command ID
-+	u_int16_t		len;	// data length, excluding this header
-+	u_int8_t		init_enable;
-+} NAT_TESTENTRY_T;	
-+	
-+typedef union
-+{
-+	NAT_STATUS_T		status;
-+	NAT_PORTCFG_T		portcfg;
-+	NAT_IPCFG_T			ipcfg;
-+	NAT_XPORT_T			xport;
-+	NAT_WEIGHT_T		weight;
-+	NAT_WRULE_T			wrule;
-+	NAT_QUEUE_T			queue;
-+	NAT_TESTENTRY_T init_entry;
-+} NAT_REQ_E;
-+	
-+/*----------------------------------------------------------------------
-+* NAT Configuration
-+*	- Used by driver only
-+*----------------------------------------------------------------------*/
-+typedef struct {
-+	unsigned int		enabled;
-+	unsigned int		init_enabled;
-+	unsigned int		tcp_udp_rule_id;
-+	unsigned int		gre_rule_id;
-+	unsigned int		lan_port;
-+	unsigned int		wan_port;
-+	unsigned int		default_hw_txq;
-+	short				tcp_tmo_interval;
-+	short				udp_tmo_interval;
-+	short				gre_tmo_interval;
-+	NAT_IPCFG_ALL_T		ipcfg[2];	// LAN/WAN port
-+	NAT_XPORT_ALL_T		xport;
-+	NAT_WEIGHT_T		weight;
-+	NAT_WRULE_ALL_T		wrule[CONFIG_NAT_TXQ_NUM];
-+} NAT_CFG_T;
-+
-+/*----------------------------------------------------------------------
-+* NAT Control Block
-+*	- Used by driver only
-+*	- Stores LAN-IN or WAN-IN information
-+*	- WAN-OUT and LAN-OUT driver use them to build up a hash entry
-+*	- NOTES: To update this data structure, MUST take care of alignment issue
-+*   -		 MUST make sure that the size of skbuff structure must 
-+*            be larger than (40 + sizof(NAT_CB_T))
-+*----------------------------------------------------------------------*/
-+typedef struct {
-+	unsigned short		tag;
-+	unsigned char		sa[6];
-+	unsigned int		sip;
-+	unsigned int		dip;
-+	unsigned short		sport;
-+	unsigned short		dport;
-+	unsigned char		pppoe_frame;
-+	unsigned char		state;			// same to enum tcp_conntrack
-+	unsigned char		reserved[2];
-+} NAT_CB_T;
-+
-+#define NAT_CB_TAG		0x4C53	// "SL"
-+#define NAT_CB_SIZE		sizeof(NAT_CB_T)
-+// #define NAT_SKB_CB(skb)	(NAT_CB_T *)(((unsigned int)&((skb)->cb[40]) + 3) & ~3)  // for align 4
-+#define NAT_SKB_CB(skb)	(NAT_CB_T *)&((skb)->cb[40])  // for align 4
-+
-+#endif // _SL351x_NAT_CFG_H_
-+
-+
-+
---- /dev/null
-+++ b/include/asm-arm/arch-sl2312/sl351x_toe.h
-@@ -0,0 +1,88 @@
-+/**************************************************************************
-+* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
-+*--------------------------------------------------------------------------
-+* Name			: sl351x_toe.h
-+* Description	:
-+*		Define for TOE driver of Storlink SL351x
-+*
-+* History
-+*
-+*	Date		Writer		Description
-+*----------------------------------------------------------------------------
-+*				Xiaochong	Create
-+*
-+****************************************************************************/
-+#ifndef __SL351x_TOE_H
-+#define __SL351x_TOE_H	1
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+/*
-+ * TOE_CONN_T is data structure of tcp connection info, used at both
-+ * device layer and kernel tcp layer
-+ * skb is the jumbo frame
-+ */
-+
-+struct toe_conn{
-+	__u8	qid;		// connection qid 0~63.
-+	__u8	ip_ver;		// 0: not used; 4: ipv4; 6: ipv6.
-+	/* hash key of the connection */
-+	__u16	source;
-+	__u16	dest;
-+	__u32	saddr[4];
-+	__u32	daddr[4];
-+
-+	__u32	seq;
-+	__u32	ack_seq;
-+
-+	/* these fields are used to set TOE QHDR */
-+	__u32	ack_threshold;
-+	__u32	seq_threshold;
-+	__u16	max_pktsize;
-+
-+	/* used by sw toe, accumulated ack_seq of ack frames */
-+	__u16	ack_cnt;
-+	/* used by sw toe, accumulated data frames held at driver */
-+	__u16	cur_pktsize;
-+
-+	__u8	status;
-+#define	TCP_CONN_UNDEFINE		0X00
-+#define	TCP_CONN_CREATION		0X01
-+#define	TCP_CONN_CONNECTING		0X02
-+#define	TCP_CONN_ESTABLISHED	0X04
-+#define	TCP_CONN_RESET			0X08	// this is used for out-of-order
-+                      			    	// or congestion window is small
-+#define	TCP_CONN_CLOSING		0X10
-+#define	TCP_CONN_CLOSED			0x11
-+
-+	__u16	hash_entry_index;	/* associated hash entry */
-+
-+	// one timer per connection. Otherwise all connections should be scanned
-+	// in a timeout interrupt, and timeout interrupt is triggered no matter
-+	// a connection is actually timeout or not.
-+	struct timer_list	rx_timer;
-+	unsigned long		last_rx_jiffies;
-+	GMAC_INFO_T			*gmac;
-+	struct net_device	*dev;
-+
-+	//	for generating pure ack frame.
-+	struct ethhdr		l2_hdr;
-+	struct iphdr		l3_hdr;
-+
-+	spinlock_t			conn_lock;
-+	DMA_RWPTR_T			toeq_rwptr;
-+	GMAC_RXDESC_T		*curr_desc;
-+	struct sk_buff		*curr_rx_skb;
-+};
-+
-+struct jumbo_frame {
-+	struct sk_buff	*skb0;		// the head of jumbo frame
-+	struct sk_buff	*tail;		// the tail of jumbo frame
-+	struct iphdr	*iphdr0;	// the ip hdr of skb0.
-+	struct tcphdr	*tcphdr0;	// the tcp hdr of skb0.
-+};
-+
-+#endif // __SL351x_TOE_H
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -2131,6 +2131,42 @@
- 
- 	  The safe and default value for this is N.
- 
-+config NET_GMAC
-+	tristate "Storlink Gigabit Ethernet support"
-+	depends on ARCH_SL2312
-+	help
-+	  This driver supports Storlink dual Gigabit Ethernet.
-+
-+config NET_SL2312
-+	tristate "Storlink Gigabit Ethernet support"
-+	depends on NET_GMAC
-+	help
-+	  This driver supports Storlink dual Gigabit Ethernet.
-+
-+config NET_SL351X
-+	tristate "Storlink Lepus Gigabit Ethernet support"
-+	depends on NET_GMAC
-+	help
-+	  This driver supports Storlink TOE and NAT dual Gigabit Ethernet.
-+
-+config SL2312_TSO
-+	bool "Tx Segmentation Enable"
-+	depends on NET_GMAC
-+	help
-+	  TBD
-+
-+config SL2312_MPAGE
-+	bool "Tx Multipage Enable"
-+	depends on NET_GMAC
-+	help
-+	  TBD
-+
-+config SL2312_RECVFILE
-+	bool "Rx Multipage Enable"
-+	depends on NET_GMAC
-+	help
-+	  TBD
-+
- config DL2K
- 	tristate "D-Link DL2000-based Gigabit Ethernet support"
- 	depends on PCI
---- a/drivers/net/Makefile
-+++ b/drivers/net/Makefile
-@@ -236,4 +236,8 @@
- 
- obj-$(CONFIG_FS_ENET) += fs_enet/
- 
--obj-$(CONFIG_NETXEN_NIC) += netxen/
-+
-+obj-$(CONFIG_NET_SL351X)+= sl351x_gmac.o sl351x_nat.o sl351x_hash.o sl351x_crc16.o sl351x_proc.o sl_switch.o
-+obj-$(CONFIG_NET_SL2312)+= sl2312_emac.o
-+
-+
diff --git a/target/linux/storm/patches/003-gmac_one_phy.patch b/target/linux/storm/patches/003-gmac_one_phy.patch
deleted file mode 100644
index 15a69c905e..0000000000
--- a/target/linux/storm/patches/003-gmac_one_phy.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/include/asm-arm/arch-sl2312/sl351x_gmac.h
-+++ b/include/asm-arm/arch-sl2312/sl351x_gmac.h
-@@ -21,7 +21,7 @@
- #undef BIG_ENDIAN
- #define BIG_ENDIAN  				0
- #define GMAC_DEBUG      			1
--#define GMAC_NUM					2
-+#define GMAC_NUM					1
- //#define	L2_jumbo_frame				1
- 
- #define _PACKED_					__attribute__ ((aligned(1), packed))
diff --git a/target/linux/storm/patches/004-gmac_enable_napi.patch b/target/linux/storm/patches/004-gmac_enable_napi.patch
deleted file mode 100644
index ea374c41c9..0000000000
--- a/target/linux/storm/patches/004-gmac_enable_napi.patch
+++ /dev/null
@@ -1,81 +0,0 @@
---- a/drivers/net/sl351x_gmac.c
-+++ b/drivers/net/sl351x_gmac.c
-@@ -68,9 +68,11 @@
- #include 
- #endif
- 
-+/* Enables NAPI unconditionally */
-+#define CONFIG_SL_NAPI					1
-+
- // #define SL351x_TEST_WORKAROUND
- #ifdef CONFIG_SL351x_NAT
--#define CONFIG_SL_NAPI					1
- #endif
- #define GMAX_TX_INTR_DISABLED			1
- #define DO_HW_CHKSUM					1
-@@ -124,12 +126,17 @@
-  *************************************************************/
- static int	gmac_initialized = 0;
- TOE_INFO_T toe_private_data;
--//static int		do_again = 0;
-+static int		do_again = 0;
- spinlock_t gmac_fq_lock;
- unsigned int FLAG_SWITCH;
- 
- static unsigned int     	next_tick = 3 * HZ;
--static unsigned char    	eth_mac[CONFIG_MAC_NUM][6]= {{0x00,0x11,0x11,0x87,0x87,0x87}, {0x00,0x22,0x22,0xab,0xab,0xab}};
-+static unsigned char    	eth_mac[CONFIG_MAC_NUM][6]= {
-+		{0x00,0x11,0x11,0x87,0x87,0x87},
-+#if GMAC_NUM != 1
-+		{0x00,0x22,0x22,0xab,0xab,0xab}
-+#endif
-+};
- 
- #undef CONFIG_SL351x_RXTOE
- extern NAT_CFG_T nat_cfg;
-@@ -2443,7 +2450,8 @@
- 	toe = (TOE_INFO_T *)&toe_private_data;
- //	handle NAPI
- #ifdef CONFIG_SL_NAPI
--if (storlink_ctl.pauseoff == 1)
-+	/* XXX: check this, changed from 'storlink_ctl.pauseoff == 1' to if (1) */
-+if (1)
- {
- /* disable GMAC interrupt */
-     //toe_gmac_disable_interrupt(tp->irq);
-@@ -2530,7 +2538,7 @@
- 				{
- 					if (likely(netif_rx_schedule_prep(dev)))
-         			{
--        				unsigned int data32;
-+        				// unsigned int data32;
-         				// disable GMAC-0 rx interrupt
-         				// class-Q & TOE-Q are implemented in future
-         				//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-@@ -2563,7 +2571,7 @@
- 			{
- 				if (likely(netif_rx_schedule_prep(dev)))
-         		{
--        			unsigned int data32;
-+        			// unsigned int data32;
-          			// disable GMAC-0 rx interrupt
-         			// class-Q & TOE-Q are implemented in future
-         			//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-@@ -4217,7 +4225,7 @@
- 	GMAC_INFO_T			*tp = (GMAC_INFO_T *)dev->priv;
- 	unsigned int		status4;
- 	volatile DMA_RWPTR_T	fq_rwptr;
--	int					max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
-+	// int					max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
- 	//unsigned long		rx_old_bytes;
- 	struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
- 	//unsigned long long	rx_time;
-@@ -4479,7 +4487,7 @@
- 
- 	if (rwptr.bits.rptr == rwptr.bits.wptr)
- 	{
--		unsigned int data32;
-+		// unsigned int data32;
- 			//printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr]   rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
- 
- 	    /* Receive descriptor is empty now */
diff --git a/target/linux/storm/patches/005-gmac_napi_mask_intrs.patch b/target/linux/storm/patches/005-gmac_napi_mask_intrs.patch
deleted file mode 100644
index f0b6375432..0000000000
--- a/target/linux/storm/patches/005-gmac_napi_mask_intrs.patch
+++ /dev/null
@@ -1,248 +0,0 @@
---- a/drivers/net/sl351x_gmac.c
-+++ b/drivers/net/sl351x_gmac.c
-@@ -127,6 +127,7 @@
- static int	gmac_initialized = 0;
- TOE_INFO_T toe_private_data;
- static int		do_again = 0;
-+static int rx_poll_enabled;
- spinlock_t gmac_fq_lock;
- unsigned int FLAG_SWITCH;
- 
-@@ -1065,7 +1066,8 @@
- 	    tp->intr3_enabled = 	0xffffffff;
- 	    tp->intr4_selected = 	GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
- 	    						HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
--	    tp->intr4_enabled = 	GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
-+	    tp->intr4_enabled = 	GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT| GMAC0_RX_OVERRUN_INT_BIT;
-+	    // GMAC0_TX_PAUSE_OFF_INT_BIT| GMAC0_MIB_INT_BIT;
- 
- 	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
- 	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
-@@ -1115,7 +1117,7 @@
- 	    	tp->intr3_enabled	|= 	0xffffffff;
- 	    	tp->intr4_selected 	|= 	CLASS_RX_FULL_INT_BITS |
- 	    							HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
--	    	tp->intr4_enabled	|= 	SWFQ_EMPTY_INT_BIT;
-+	    	tp->intr4_enabled	|= 	SWFQ_EMPTY_INT_BIT | GMAC1_RX_OVERRUN_INT_BIT;
- 		}
- 	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) | tp->intr0_selected;
- 	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
-@@ -2408,7 +2410,7 @@
- 	// unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
- 
- 	fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--	spin_lock_irqsave(&gmac_fq_lock, flags);
-+	// spin_lock_irqsave(&gmac_fq_lock, flags);
- 	//while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
- 	//				TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
- 	while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
-@@ -2428,10 +2430,47 @@
- 		SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
- 		toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
- 	}
--	spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+	// spin_unlock_irqrestore(&gmac_fq_lock, flags);
- }
- // EXPORT_SYMBOL(toe_gmac_fill_free_q);
- 
-+static void gmac_registers(const char *message)
-+{
-+	unsigned int		status0;
-+	unsigned int		status1;
-+	unsigned int		status2;
-+	unsigned int		status3;
-+	unsigned int		status4;
-+
-+	printk("%s\n", message);
-+
-+	status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
-+	status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
-+	status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
-+	status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
-+	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+	printk("status: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
-+		   status0, status1, status2, status3, status4);
-+
-+	status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_0_REG);
-+	status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+	status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_2_REG);
-+	status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_3_REG);
-+	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+
-+	printk("mask  : s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
-+		   status0, status1, status2, status3, status4);
-+
-+	status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
-+	status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
-+	status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
-+	status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
-+	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+
-+	printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
-+		   status0, status1, status2, status3, status4);
-+}
- /*----------------------------------------------------------------------
- * toe_gmac_interrupt
- *----------------------------------------------------------------------*/
-@@ -2492,6 +2531,7 @@
- 		writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
- 	if (status4)
- 		writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
-+
- #if 0
- 	/* handle freeq interrupt first */
- 	if (status4 & tp->intr4_enabled) {
-@@ -2536,10 +2576,31 @@
- 			}
- 				if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
- 				{
--					if (likely(netif_rx_schedule_prep(dev)))
-+					if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
-         			{
--        				// unsigned int data32;
--        				// disable GMAC-0 rx interrupt
-+        				unsigned int data32;
-+
-+						if (rx_poll_enabled)
-+								gmac_registers("check #1");
-+
-+						BUG_ON(rx_poll_enabled == 1);
-+
-+#if 0
-+        				/* Masks GMAC-0 rx interrupt */
-+						data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+						data32 &= ~(DEFAULT_Q0_INT_BIT);
-+						writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+
-+        				/* Masks GMAC-0 queue empty interrupt */
-+						data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+						data32 &= ~DEFAULT_Q0_INT_BIT;
-+						writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+
-+						data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+						data32 &= ~DEFAULT_Q0_INT_BIT;
-+						writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+#endif
-+
-         				// class-Q & TOE-Q are implemented in future
-         				//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-         				//data32 &= ~DEFAULT_Q0_INT_BIT;
-@@ -2549,7 +2610,8 @@
- 						//tp->total_q_cnt_napi=0;
- 						//rx_time = jiffies;
- 						//rx_old_bytes = isPtr->rx_bytes;
--            			__netif_rx_schedule(dev);
-+						__netif_rx_schedule(dev);
-+						rx_poll_enabled = 1;
-         			}
- 			}
- 		}
-@@ -2569,9 +2631,31 @@
- 
- 			if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
- 			{
--				if (likely(netif_rx_schedule_prep(dev)))
-+				if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
-         		{
--        			// unsigned int data32;
-+        			unsigned int data32;
-+
-+					if (rx_poll_enabled)
-+							gmac_registers("check #2");
-+
-+					BUG_ON(rx_poll_enabled == 1);
-+
-+#if 0
-+					/* Masks GMAC-1 rx interrupt */
-+					data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+					data32 &= ~(DEFAULT_Q1_INT_BIT);
-+					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+
-+        			/* Masks GMAC-1 queue empty interrupt */
-+					data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+					data32 &= ~DEFAULT_Q1_INT_BIT;
-+					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+
-+					data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+					data32 &= ~DEFAULT_Q1_INT_BIT;
-+					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+#endif
-+
-          			// disable GMAC-0 rx interrupt
-         			// class-Q & TOE-Q are implemented in future
-         			//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-@@ -2583,9 +2667,13 @@
- 					//rx_time = jiffies;
- 					//rx_old_bytes = isPtr->rx_bytes;
-            			__netif_rx_schedule(dev);
-+				rx_poll_enabled = 1;
-         		}
- 			}
- 		}
-+	} else {
-+
-+		gmac_registers("check #3");
- 	}
- 
- 	// Interrupt Status 0
-@@ -3306,8 +3394,10 @@
- 		SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
-      	tp->rx_rwptr.bits32 = rwptr.bits32;
- 
--		toe_gmac_fill_free_q();
- 	}
-+
-+	/* Handles first available packets only then refill the queue. */
-+	toe_gmac_fill_free_q();
- }
- 
- /*----------------------------------------------------------------------
-@@ -4217,6 +4307,7 @@
-     GMAC_RXDESC_T   	*curr_desc;
- 	struct sk_buff 		*skb;
-     DMA_RWPTR_T			rwptr;
-+    unsigned int data32;
- 	unsigned int 		pkt_size;
- 	unsigned int        desc_count;
- 	unsigned int        good_frame, chksum_status, rx_status;
-@@ -4231,7 +4322,7 @@
- 	//unsigned long long	rx_time;
- 
- 
--
-+	BUG_ON(rx_poll_enabled == 0);
- #if 1
- 	if (do_again)
- 	{
-@@ -4516,6 +4607,30 @@
- #endif
-         //toe_gmac_fill_free_q();
-         netif_rx_complete(dev);
-+
-+		rx_poll_enabled = 0;
-+
-+		data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+		if (tp->port_id == 0)
-+				data32 |= DEFAULT_Q0_INT_BIT;
-+		else
-+				data32 |= DEFAULT_Q1_INT_BIT;
-+		writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+
-+		data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+		if (tp->port_id == 0)
-+				data32 |= DEFAULT_Q0_INT_BIT;
-+		else
-+				data32 |= DEFAULT_Q1_INT_BIT;
-+		writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+
-+		data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+		if (tp->port_id == 0)
-+				data32 |= DEFAULT_Q0_INT_BIT;
-+		else
-+				data32 |= DEFAULT_Q1_INT_BIT;
-+		writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+
-         // enable GMAC-0 rx interrupt
-         // class-Q & TOE-Q are implemented in future
-         //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
diff --git a/target/linux/storm/patches/006-gmac_napi_tx.patch b/target/linux/storm/patches/006-gmac_napi_tx.patch
deleted file mode 100644
index 5861a6553d..0000000000
--- a/target/linux/storm/patches/006-gmac_napi_tx.patch
+++ /dev/null
@@ -1,2094 +0,0 @@
---- a/drivers/net/sl351x_gmac.c
-+++ b/drivers/net/sl351x_gmac.c
-@@ -43,9 +43,13 @@
- 
- #include 
- 
-+#define GET_RPTR(x) ((x) & 0xFFFF)
-+#define GET_WPTR(x) ((x) >> 16)
-+
- #define	 MIDWAY
- #define	 SL_LEPUS
--#define VITESSE_G5SWITCH	1
-+// #define VITESSE_G5SWITCH	1
-+#undef VITESSE_G5SWITCH
- 
- #ifndef CONFIG_SL351x_RXTOE
- //#define CONFIG_SL351x_RXTOE	1
-@@ -126,7 +130,6 @@
-  *************************************************************/
- static int	gmac_initialized = 0;
- TOE_INFO_T toe_private_data;
--static int		do_again = 0;
- static int rx_poll_enabled;
- spinlock_t gmac_fq_lock;
- unsigned int FLAG_SWITCH;
-@@ -190,7 +193,7 @@
- void mac_set_sw_tx_weight(struct net_device *dev, char *weight);
- void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
- void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
--static inline void toe_gmac_fill_free_q(void);
-+static inline void toe_gmac_fill_free_q(int count);
- 
- #ifdef VITESSE_G5SWITCH
- extern int Get_Set_port_status(void);
-@@ -295,12 +298,14 @@
- 	for(j = 0; idev = NULL;
-@@ -459,7 +464,7 @@
- 		toe->gmac[1].dma_base_addr = TOE_GMAC1_DMA_BASE;
-         toe->gmac[0].auto_nego_cfg = 1;
-         toe->gmac[1].auto_nego_cfg = 1;
--#ifdef CONFIG_SL3516_ASIC
-+#ifndef CONFIG_SL3516_ASIC
-         toe->gmac[0].speed_cfg = GMAC_SPEED_1000;
-         toe->gmac[1].speed_cfg = GMAC_SPEED_1000;
- #else
-@@ -508,7 +513,7 @@
- 		// Write GLOBAL_QUEUE_THRESHOLD_REG
- 		threshold.bits32 = 0;
- 		threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
--		                                        TOE_SW_FREEQ_DESC_NUM/2;
-+		                                        TOE_SW_FREEQ_DESC_NUM/16;
- 		threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256/4 :
- 		                                        TOE_HW_FREEQ_DESC_NUM/4;
- 		threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256/4 :
-@@ -613,18 +618,25 @@
- 	rwptr_reg.bits.rptr = 0;
- 	toe->fq_rx_rwptr.bits32 = rwptr_reg.bits32;
- 	writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+	printk("SWFQ: %08X\n", readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG));
- 
- 	// SW Free Queue Descriptors
- 	for (i=0; iword0.bits.buffer_size = SW_RX_BUF_SIZE;
--		sw_desc_ptr->word1.bits.sw_id = i;	// used to locate skb
-+		sw_desc_ptr->word1.bits.sw_id = 0;	// used to locate skb
- 		if ( (skb = dev_alloc_skb(SW_RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
- 		{
- 			printk("%s::skb buffer allocation fail !\n",__func__); while(1);
- 		}
--		REG32(skb->data) = (unsigned int)skb;
-+
-+		data = skb->data;
- 		skb_reserve(skb, SKB_RESERVE_BYTES);
-+
-+		REG32(data + 0) = (unsigned int)skb;
-+		REG32(data + 4) = (unsigned short)i;
-+
- 		// toe->rx_skb[i] = skb;
- 		sw_desc_ptr->word2.buf_adr = (unsigned int)__pa(skb->data);
- //   		consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
-@@ -851,14 +863,14 @@
- *----------------------------------------------------------------------*/
- static void toe_init_default_queue(void)
- {
--	TOE_INFO_T				*toe;
-+	TOE_INFO_T		*toe;
- 	volatile NONTOE_QHDR_T	*qhdr;
--	GMAC_RXDESC_T			*desc_ptr;
--	DMA_SKB_SIZE_T			skb_size;
-+	GMAC_RXDESC_T		*desc_ptr;
-+	DMA_SKB_SIZE_T		skb_size;
- 
- 	toe = (TOE_INFO_T *)&toe_private_data;
- 	desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T)),
--											(dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
-+					       (dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
- 	if (!desc_ptr)
- 	{
- 		printk("%s::DMA_MALLOC fail !\n",__func__);
-@@ -866,14 +878,17 @@
- 	}
- 	memset((void *)desc_ptr, 0, TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T));
- 	toe->gmac[0].default_desc_base = (unsigned int)desc_ptr;
-+	printk("toe->gmac[0].default_desc_base_dma: %08X\n", toe->gmac[0].default_desc_base_dma);
-+
- 	toe->gmac[0].default_desc_num = TOE_DEFAULT_Q0_DESC_NUM;
- 	qhdr = (volatile NONTOE_QHDR_T *)TOE_DEFAULT_Q0_HDR_BASE;
- 	qhdr->word0.base_size = ((unsigned int)toe->gmac[0].default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q0_DESC_POWER;
- 	qhdr->word1.bits32 = 0;
- 	toe->gmac[0].rx_rwptr.bits32 = 0;
- 	toe->gmac[0].default_qhdr = (NONTOE_QHDR_T *)qhdr;
-+
- 	desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q1_DESC_NUM * sizeof(GMAC_RXDESC_T)),
--											(dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
-+					       (dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
- 	if (!desc_ptr)
- 	{
- 		printk("%s::DMA_MALLOC fail !\n",__func__);
-@@ -1071,12 +1086,16 @@
- 
- 	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
- 	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
-+
- 	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG) & ~tp->intr1_selected;
- 	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
-+
- 	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG) & ~tp->intr2_selected;
- 	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
-+
- 	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG) & ~tp->intr3_selected;
- 	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
-+
- 	    data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) & ~tp->intr4_selected;
- 	    writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
- 	}
-@@ -1176,11 +1195,11 @@
- 	GMAC_CONFIG2_T	config2_val;
- 	GMAC_CONFIG0_T	config0,config0_mask;
- 	GMAC_CONFIG1_T	config1;
--	#ifdef CONFIG_SL351x_NAT
- 	GMAC_CONFIG3_T	config3_val;
--	#endif
- 	GMAC_TX_WCR0_T	hw_weigh;
- 	GMAC_TX_WCR1_T	sw_weigh;
-+
-+	uint32_t weight = 0;
- //	GMAC_HASH_ENABLE_REG0_T hash_ctrl;
- //
- #if 0 /* mac address will be set in late_initcall */
-@@ -1202,24 +1221,23 @@
- 	//	config1.bits32 = 0x002004;	//next version
- 	/* set flow control threshold */
- 	config1.bits32 = 0;
--	config1.bits.set_threshold = 32 / 2;
--	config1.bits.rel_threshold = 32 / 4 * 3;
-+	config1.bits.set_threshold = (32 / 2);
-+	config1.bits.rel_threshold = (32 / 4) * 3;
- 	gmac_write_reg(tp->base_addr, GMAC_CONFIG1, config1.bits32, 0xffffffff);
- 
--	/* set flow control threshold */
-+	/* TODO: set flow control threshold */
- 	config2_val.bits32 = 0;
--	config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM/2;
--	config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM*3/4;
-+	config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM/4;
-+	config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM/2;
- 	gmac_write_reg(tp->base_addr, GMAC_CONFIG2, config2_val.bits32,0xffffffff);
- 
--	#ifdef CONFIG_SL351x_NAT
--	/* set HW free queue flow control threshold */
-+	/* TODO: set HW free queue flow control threshold */
- 	config3_val.bits32 = 0;
- 	config3_val.bits.set_threshold = PAUSE_SET_HW_FREEQ;
- 	config3_val.bits.rel_threshold = PAUSE_REL_HW_FREEQ;
- 	gmac_write_reg(tp->base_addr, GMAC_CONFIG3, config3_val.bits32,0xffffffff);
--	#endif
--	/* set_mcast_filter mask*/
-+
-+	/* TODO: set_mcast_filter mask*/
- 	//	gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,0x0,0xffffffff);
- 	//  gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,0x0,0xffffffff);
- 
-@@ -1249,7 +1267,7 @@
- 	config0.bits.dis_rx = 1;  /* disable rx */
- 	config0.bits.dis_tx = 1;  /* disable tx */
- 	config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
--	config0.bits.rx_err_detect = 1;
-+	config0.bits.rx_err_detect = 1;	/* TODO: was 1, means disabled, 0 enabled ! */
- 	config0.bits.rgmii_en = 0;
- 	config0.bits.rgmm_edge = 1;
- 	config0.bits.rxc_inv = 0;
-@@ -1342,6 +1360,9 @@
- 	gmac_write_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG, ahb_weight.bits32, ahb_weight_mask.bits32);
- 	#endif
- 
-+	weight = gmac_read_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG);
-+	printk("====> %08X\n", weight);
-+
- 	#if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
- 	gmac_write_reg(tp->dma_base_addr, GMAC_SPR0, IPPROTO_TCP, 0xffffffff);
- 	#endif
-@@ -1552,7 +1573,7 @@
- 		rwptr.bits32 = readl(swtxq->rwptr_reg);
- 		if (rwptr.bits.rptr == swtxq->finished_idx)
- 			break;
--    	curr_desc = (volatile GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
-+		curr_desc = (volatile GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
- //   		consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
- 		word0.bits32 = curr_desc->word0.bits32;
- 		word1.bits32 = curr_desc->word1.bits32;
-@@ -1573,6 +1594,7 @@
- 				swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
- 				curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
- 				word0.bits32 = curr_desc->word0.bits32;
-+
- #ifdef _DUMP_TX_TCP_CONTENT
- 				if (curr_desc->word0.bits.buffer_size < 16)
- 				{
-@@ -1592,12 +1614,12 @@
- 			word0.bits.status_tx_ok = 0;
- 			if (swtxq->tx_skb[swtxq->finished_idx])
- 			{
--				if (interrupt)
--					dev_kfree_skb_irq(swtxq->tx_skb[swtxq->finished_idx]);
--				else
--					dev_kfree_skb(swtxq->tx_skb[swtxq->finished_idx]);
-+				dev_kfree_skb(swtxq->tx_skb[swtxq->finished_idx]);
- 				swtxq->tx_skb[swtxq->finished_idx] = NULL;
-+			} else {
-+				BUG();
- 			}
-+
- 			curr_desc->word0.bits32 = word0.bits32;
-   			swtxq->curr_finished_desc = (GMAC_TXDESC_T *)curr_desc;
-  			swtxq->total_finished++;
-@@ -1624,31 +1646,29 @@
- *----------------------------------------------------------------------*/
- static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
- {
--	GMAC_INFO_T 			*tp= dev->priv;
--//	static unsigned int     pcount = 0;
--//	unsigned int			tx_qid;
--    DMA_RWPTR_T				rwptr;
--	volatile GMAC_TXDESC_T	*curr_desc;
--	int 					snd_pages = skb_shinfo(skb)->nr_frags + 1;  /* get number of descriptor */
--	int 					frag_id = 0;
--	int 					len, total_len = skb->len;
-+	GMAC_INFO_T *tp= dev->priv;
-+	DMA_RWPTR_T rwptr;
-+	GMAC_TXDESC_T *curr_desc;
-+	int snd_pages = skb_shinfo(skb)->nr_frags + 1;  /* get number of descriptor */
-+	int frag_id = 0;
-+	int len, total_len = skb->len;
- 	struct net_device_stats *isPtr;
--	unsigned int			free_desc;
--	GMAC_SWTXQ_T			*swtxq;
-+	unsigned int free_desc;
-+	GMAC_SWTXQ_T *swtxq;
- 	register unsigned long	word0, word1, word2, word3;
- 	unsigned short			wptr, rptr;
- #ifdef	L2_jumbo_frame
- 	int header_len = skb->len;
- 	struct iphdr	*ip_hdr;
--    struct tcphdr	*tcp_hdr;
--    int             tcp_hdr_len;
--    unsigned char 	*ptr;
--    int             data_len,a;
--    unsigned int    val;
-+	struct tcphdr	*tcp_hdr;
-+	int             tcp_hdr_len;
-+	unsigned char 	*ptr;
-+	int             data_len,a;
-+	unsigned int    val;
- #endif
- 
- #ifdef GMAC_LEN_1_2_ISSUE
--	int						total_pages;
-+	int total_pages;
- 	total_pages = snd_pages;
- #endif
- 
-@@ -1664,13 +1684,6 @@
-     }
- #endif
- 
--#if 0
--	if (storlink_ctl.recvfile==2)
--	{
--	    printk("snd_pages=%d skb->len=%d\n",snd_pages,skb->len);
--	}
--#endif
--
- #ifdef GMAC_USE_TXQ0
- 	#define tx_qid 	0
- #endif
-@@ -1703,9 +1716,9 @@
- 	toe_gmac_tx_complete(tp, tx_qid, dev, 0);
- 
- 	if (wptr >= swtxq->finished_idx)
--		free_desc = swtxq->total_desc_num - wptr - 1 + swtxq->finished_idx;
-+		free_desc = swtxq->total_desc_num - wptr + swtxq->finished_idx;
- 	else
--		free_desc = swtxq->finished_idx - wptr - 1;
-+		free_desc = swtxq->finished_idx - wptr;
- 	if (free_desc < snd_pages)
- 	{
- //		spin_unlock(&tp->tx_mutex);
-@@ -2063,9 +2076,10 @@
- struct net_device_stats * gmac_get_stats(struct net_device *dev)
- {
-     GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
-+#if 0	/* don't read stats from hardware, scary numbers. */
-     // unsigned int        flags;
--    unsigned int        pkt_drop;
--    unsigned int        pkt_error;
-+    unsigned int        pkt_drop = 0;
-+    unsigned int        pkt_error = 0;
- 
-     if (netif_running(dev))
-     {
-@@ -2073,10 +2087,14 @@
-         // spin_lock_irqsave(&tp->lock,flags);
-         pkt_drop = gmac_read_reg(tp->base_addr,GMAC_IN_DISCARDS);
-         pkt_error = gmac_read_reg(tp->base_addr,GMAC_IN_ERRORS);
-+	printk("**** stack: %lu, hw: %lu\n", tp->ifStatics.rx_dropped, pkt_drop);
-+
-         tp->ifStatics.rx_dropped = tp->ifStatics.rx_dropped + pkt_drop;
-         tp->ifStatics.rx_errors = tp->ifStatics.rx_errors + pkt_error;
-         // spin_unlock_irqrestore(&tp->lock,flags);
-     }
-+#endif
-+
-     return &tp->ifStatics;
- }
- 
-@@ -2401,36 +2419,63 @@
- * toe_gmac_fill_free_q
- * allocate buffers for free queue.
- *----------------------------------------------------------------------*/
--static inline void toe_gmac_fill_free_q(void)
-+static inline void toe_gmac_fill_free_q(int count)
- {
- 	struct sk_buff	*skb;
- 	volatile DMA_RWPTR_T	fq_rwptr;
- 	volatile GMAC_RXDESC_T	*fq_desc;
--	unsigned long	flags;
-+	unsigned long flags;
-+	unsigned short index;
-+	int filled = 0;
-+	static int entered;
- 	// unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
- 
-+	BUG_ON(entered == 1);
-+
-+	entered = 1;
-+
-+
- 	fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
- 	// spin_lock_irqsave(&gmac_fq_lock, flags);
- 	//while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
- 	//				TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
--	while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
--					TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
-+	index = fq_rwptr.bits.wptr;
-+#if 0
-+	printk("wptr: %hu, rptr: %hu, refill idx: %hu\n",
-+	       GET_RPTR(fq_rwptr.bits32),
-+	       GET_WPTR(fq_rwptr.bits32),
-+	       index);
-+#endif
-+
-+	index = RWPTR_ADVANCE_ONE(index, TOE_SW_FREEQ_DESC_NUM);
-+	fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base + index;
-+	while (fq_desc->word2.buf_adr == 0) {
-+		void *data = NULL;
-+
- 		if ((skb = dev_alloc_skb(SW_RX_BUF_SIZE)) == NULL) {
- 			printk("%s::skb allocation fail!\n", __func__);
--			//while(1);
--			break;
-+			goto out;
- 		}
--		REG32(skb->data) = (unsigned int)skb;
-+		++ filled;
-+		data = skb->data;
- 		skb_reserve(skb, SKB_RESERVE_BYTES);
--		// fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--		fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
--			TOE_SW_FREEQ_DESC_NUM);
--		fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base+fq_rwptr.bits.wptr;
-+
-+		REG32(data + 0) = (unsigned int)skb;
-+		REG32(data + 4) = (unsigned short)index;
-+
-+		// printk("refill skb: %p, idx: %hu\n", skb, index);
- 		fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
--		SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
--		toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
-+	writel(0x07960202, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+		SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, index);
-+	writel(0x07960200, TOE_GMAC0_BASE+GMAC_CONFIG0);
-+
-+		index = RWPTR_ADVANCE_ONE(index, TOE_SW_FREEQ_DESC_NUM);
-+		fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base+index;
- 	}
-+out:
- 	// spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+
-+	entered = 0;
- }
- // EXPORT_SYMBOL(toe_gmac_fill_free_q);
- 
-@@ -2442,14 +2487,14 @@
- 	unsigned int		status3;
- 	unsigned int		status4;
- 
--	printk("%s\n", message);
--
- 	status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
- 	status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
- 	status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
- 	status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
- 	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
- 
-+	printk("%s\n", message);
-+
- 	printk("status: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
- 		   status0, status1, status2, status3, status4);
- 
-@@ -2468,8 +2513,9 @@
- 	status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
- 	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
- 
--	printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
--		   status0, status1, status2, status3, status4);
-+	if (status0 || status1 || status2 || status3 || status4)
-+			printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
-+				   status0, status1, status2, status3, status4);
- }
- /*----------------------------------------------------------------------
- * toe_gmac_interrupt
-@@ -2485,75 +2531,44 @@
- 	unsigned int		status3;
- 	unsigned int		status4;
- 
--//	struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
- 	toe = (TOE_INFO_T *)&toe_private_data;
--//	handle NAPI
--#ifdef CONFIG_SL_NAPI
--	/* XXX: check this, changed from 'storlink_ctl.pauseoff == 1' to if (1) */
--if (1)
--{
--/* disable GMAC interrupt */
--    //toe_gmac_disable_interrupt(tp->irq);
- 
--//	isPtr->interrupts++;
-+	if (0 && rx_poll_enabled) {
-+		gmac_registers("interrupt handler");
-+	}
-+
- 	/* read Interrupt status */
- 	status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
- 	status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
- 	status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
- 	status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
- 	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
--	// prompt warning if status bit ON but not enabled
-+
- #if 0
--	if (status0 & ~tp->intr0_enabled)
--		printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
--				status0, tp->intr0_enabled);
--	if (status1 & ~tp->intr1_enabled)
--		printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
--				status1, tp->intr1_enabled);
--	if (status2 & ~tp->intr2_enabled)
--		printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
--				status2, tp->intr2_enabled);
--	if (status3 & ~tp->intr3_enabled)
--		printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
--				status3, tp->intr3_enabled);
--	if (status4 & ~tp->intr4_enabled)
--		printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
--				status4, tp->intr4_enabled);
-+	/* handle freeq interrupt first */
-+	if (status4 & SWFQ_EMPTY_INT_BIT)
-+	{
-+		toe_gmac_fill_free_q();
-+		writel(status4 & SWFQ_EMPTY_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
-+		tp->sw_fq_empty_cnt++;
-+	}
- #endif
- 
-+	if (status4 & GMAC0_MIB_INT_BIT)
-+		writel(GMAC0_MIB_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+	if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
-+		writel(GMAC0_RX_OVERRUN_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
-+
- 	if (status0)
- 		writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
--	if (status1)
--		writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
- 	if (status2)
- 		writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
- 	if (status3)
- 		writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
--	if (status4)
--		writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
--
--#if 0
--	/* handle freeq interrupt first */
--	if (status4 & tp->intr4_enabled) {
--		if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
--		{
--			// unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--			//gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
--			//	tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
--
--			if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
--				toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
--			if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
--				toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
--			printk("\nfreeq int\n");
--			toe_gmac_fill_free_q();
--			tp->sw_fq_empty_cnt++;
- 
--		}
--	}
--#endif
- 	// Interrupt Status 1
--	if (status1 & tp->intr1_enabled)
-+	if ((status1 & 3) || (status4 & 1))
- 	{
- 		#define G1_INTR0_BITS	(GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
- 		#define G0_INTR0_BITS	(GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
-@@ -2563,7 +2578,7 @@
- 		// because they should pass packets to upper layer
- 		if (tp->port_id == 0)
- 		{
--			if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
-+			if (((status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS)) || (status4 & 1))
- 			{
- 				if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
- 					tp->hwtxq[3].eof_cnt++;
-@@ -2574,50 +2589,51 @@
- 				if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
- 					tp->hwtxq[0].eof_cnt++;
- 			}
--				if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
-+			if (status1 & DEFAULT_Q0_INT_BIT || status4 & 1)
-+			{
-+				if (likely(netif_rx_schedule_prep(dev)))
- 				{
--					if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
--        			{
--        				unsigned int data32;
-+					unsigned int data32;
-+
-+					BUG_ON(rx_poll_enabled == 1);
- 
--						if (rx_poll_enabled)
--								gmac_registers("check #1");
-+					/* Masks GMAC-0 rx interrupt */
-+					data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+					data32 &= ~(DEFAULT_Q0_INT_BIT);
-+					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
- 
--						BUG_ON(rx_poll_enabled == 1);
-+					/* Masks GMAC-0 queue empty interrupt */
-+					data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+					data32 &= ~DEFAULT_Q0_INT_BIT;
-+					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
- 
-+					__netif_rx_schedule(dev);
-+					rx_poll_enabled = 1;
-+				} else {
- #if 0
--        				/* Masks GMAC-0 rx interrupt */
--						data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
--						data32 &= ~(DEFAULT_Q0_INT_BIT);
--						writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
--
--        				/* Masks GMAC-0 queue empty interrupt */
--						data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
--						data32 &= ~DEFAULT_Q0_INT_BIT;
--						writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
--
--						data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
--						data32 &= ~DEFAULT_Q0_INT_BIT;
--						writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
--#endif
--
--        				// class-Q & TOE-Q are implemented in future
--        				//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
--        				//data32 &= ~DEFAULT_Q0_INT_BIT;
--						//writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
--						//printk("\%s: DEFAULT_Q0_INT_BIT===================>>>>>>>>>>>>\n",__func__);
--						writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
--						//tp->total_q_cnt_napi=0;
--						//rx_time = jiffies;
--						//rx_old_bytes = isPtr->rx_bytes;
--						__netif_rx_schedule(dev);
--						rx_poll_enabled = 1;
--        			}
-+					unsigned int data32;
-+
-+					if (rx_poll_enabled)
-+						gmac_registers("->poll() running.");
-+					/* Masks GMAC-0 rx interrupt */
-+					data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+					data32 &= ~(DEFAULT_Q0_INT_BIT);
-+					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+
-+					/* Masks GMAC-0 queue empty interrupt */
-+					data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+					data32 &= ~DEFAULT_Q0_INT_BIT;
-+					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+#endif
-+				}
-+			} else {
-+				if (0)
-+					gmac_registers("status1 & DEFAULT_Q0_INT_BIT || status4 & 1");
- 			}
- 		}
--		else if (tp->port_id == 1)
-+		else if (tp->port_id == 1 && netif_running(dev))
- 		{
--			if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
-+			if ((status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
- 			{
- 				if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
- 					tp->hwtxq[3].eof_cnt++;
-@@ -2629,14 +2645,14 @@
- 					tp->hwtxq[0].eof_cnt++;
- 			}
- 
--			if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
-+			if ((status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
- 			{
- 				if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
--        		{
--        			unsigned int data32;
-+				{
-+					unsigned int data32;
- 
- 					if (rx_poll_enabled)
--							gmac_registers("check #2");
-+						gmac_registers("check #2");
- 
- 					BUG_ON(rx_poll_enabled == 1);
- 
-@@ -2646,7 +2662,7 @@
- 					data32 &= ~(DEFAULT_Q1_INT_BIT);
- 					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
- 
--        			/* Masks GMAC-1 queue empty interrupt */
-+					/* Masks GMAC-1 queue empty interrupt */
- 					data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
- 					data32 &= ~DEFAULT_Q1_INT_BIT;
- 					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
-@@ -2656,24 +2672,21 @@
- 					writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
- #endif
- 
--         			// disable GMAC-0 rx interrupt
--        			// class-Q & TOE-Q are implemented in future
--        			//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
--        			//data32 &= ~DEFAULT_Q1_INT_BIT;
-+					// disable GMAC-0 rx interrupt
-+					// class-Q & TOE-Q are implemented in future
-+					//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+					//data32 &= ~DEFAULT_Q1_INT_BIT;
- 					//writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
- 					//printk("\%s: 1111111111--->DEFAULT_Q1_INT_BIT===================>>>>>>>>>>>>\n",__func__);
- 					writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
- 					//tp->total_q_cnt_napi=0;
- 					//rx_time = jiffies;
- 					//rx_old_bytes = isPtr->rx_bytes;
--           			__netif_rx_schedule(dev);
--				rx_poll_enabled = 1;
--        		}
-+					__netif_rx_schedule(dev);
-+					rx_poll_enabled = 1;
-+				}
- 			}
- 		}
--	} else {
--
--		gmac_registers("check #3");
- 	}
- 
- 	// Interrupt Status 0
-@@ -2814,676 +2827,93 @@
- 		}
- 	}
- 
--	//toe_gmac_enable_interrupt(tp->irq);
--#ifdef IxscriptMate_1518
--	if (storlink_ctl.pauseoff == 1)
--	{
--		GMAC_CONFIG0_T config0;
--		config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
--		config0.bits.dis_rx = 0;
--		writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
--		config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
--		config0.bits.dis_rx = 0;
--		writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
--	}
--#endif
--//	 enable_irq(gmac_irq[dev_index]);
--	//printk("gmac_interrupt complete!\n\n");
--//	return IRQ_RETVAL(handled);
- 	return	IRQ_RETVAL(1);
- }
--else
--{
--#endif	//endif NAPI
- 
-+/*----------------------------------------------------------------------
-+* gmac_get_phy_vendor
-+*----------------------------------------------------------------------*/
-+static unsigned int gmac_get_phy_vendor(int phy_addr)
-+{
-+    unsigned int	reg_val;
-+    reg_val=(mii_read(phy_addr,0x02) << 16) + mii_read(phy_addr,0x03);
-+    return reg_val;
-+}
- 
--	/* disable GMAC interrupt */
--    toe_gmac_disable_interrupt(tp->irq);
-+/*----------------------------------------------------------------------
-+* gmac_set_phy_status
-+*----------------------------------------------------------------------*/
-+void gmac_set_phy_status(struct net_device *dev)
-+{
-+	GMAC_INFO_T *tp = dev->priv;
-+	GMAC_STATUS_T   status;
-+	unsigned int    reg_val, ability,wan_port_id;
-+	unsigned int    i = 0;
- 
--//	isPtr->interrupts++;
--	/* read Interrupt status */
--	status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
--	status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
--	status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
--	status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
--	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
--	// prompt warning if status bit ON but not enabled
-+#ifdef VITESSE_G5SWITCH
-+	if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1)){
- #if 0
--	if (status0 & ~tp->intr0_enabled)
--		printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
--				status0, tp->intr0_enabled);
--	if (status1 & ~tp->intr1_enabled)
--		printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
--				status1, tp->intr1_enabled);
--	if (status2 & ~tp->intr2_enabled)
--		printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
--				status2, tp->intr2_enabled);
--	if (status3 & ~tp->intr3_enabled)
--		printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
--				status3, tp->intr3_enabled);
--	if (status4 & ~tp->intr4_enabled)
--		printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
--				status4, tp->intr4_enabled);
--#endif
--#define	INTERRUPT_SELECT			1
--	if (status0)
--		writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
--	if (status1)
--		writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
--	if (status2)
--		writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
--	if (status3)
--		writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
--	if (status4)
--		writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
--
--	/* handle freeq interrupt first */
--	if (status4 & tp->intr4_enabled) {
--		if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
--		{
--			// unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--			//gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
--			//	tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
--
--			//gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
--			//	SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
--			if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
--				toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
--			if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
--				toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
--			printk("\nfreeq int\n");
--			toe_gmac_fill_free_q();
--			tp->sw_fq_empty_cnt++;
--
--			gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
--				SWFQ_EMPTY_INT_BIT);
--		}
--	}
--
--	// Interrupt Status 1
--	if (status1 & tp->intr1_enabled)
--	{
--		#define G1_INTR0_BITS	(GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
--		#define G0_INTR0_BITS	(GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
--		// Handle GMAC 0/1 HW Tx queue 0-3 EOF events
--		// Only count
--		// TOE, Classification, and default queues interrupts are handled by ISR
--		// because they should pass packets to upper layer
--		if (tp->port_id == 0)
--		{
--#ifndef	INTERRUPT_SELECT
--			if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
--			{
--				if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
--					tp->hwtxq[3].eof_cnt++;
--				if (status1 & GMAC0_HWTQ02_EOF_INT_BIT)
--					tp->hwtxq[2].eof_cnt++;
--				if (status1 & GMAC0_HWTQ01_EOF_INT_BIT)
--					tp->hwtxq[1].eof_cnt++;
--				if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
--					tp->hwtxq[0].eof_cnt++;
--#endif	//INTERRUPT_SELECT
--#ifndef	INTERRUPT_SELECT
--			}
--#endif	//INTERRUPT_SELECT
--			if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
--			{
--				tp->default_q_intr_cnt++;
--				toe_gmac_handle_default_rxq(dev, tp);
-+		rcv_mask = SPI_read(2,0,0x10);			// Receive mask
-+		rcv_mask |= 0x4F;
-+		for(i=0;i<4;i++){
-+			reg_val = BIT(26)|(i<<21)|(10<<16);
-+			SPI_write(3,0,1,reg_val);
-+			msleep(10);
-+			reg_val = SPI_read(3,0,2);
-+			if(reg_val & 0x0c00){
-+				printk("Port%d:Giga mode\n",i);
-+				SPI_write(1,i,0x00,0x300701B1);
-+				SPI_write(1,i,0x00,0x10070181);
-+				switch_pre_link[i]=LINK_UP;
-+				switch_pre_speed[i]=GMAC_SPEED_1000;
- 			}
--#ifdef CONFIG_SL351x_RXTOE
--			if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
--			    (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
--				//printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
--				toe_gmac_handle_toeq(dev, tp, status1);
--				//toe_gmac_handle_toeq(dev, toe, tp, status1);
-+			else{
-+				reg_val = BIT(26)|(i<<21)|(5<<16);
-+				SPI_write(3,0,1,reg_val);
-+				msleep(10);
-+				ability = (reg_val = SPI_read(3,0,2)&0x5e0) >>5;
-+				if ((ability & 0x0C)) /* 100M full duplex */
-+				{
-+					SPI_write(1,i,0x00,0x30050472);
-+					SPI_write(1,i,0x00,0x10050442);
-+					printk("Port%d:100M\n",i);
-+					switch_pre_link[i]=LINK_UP;
-+				switch_pre_speed[i]=GMAC_SPEED_100;
-+				}
-+				else if((ability & 0x03)) /* 10M full duplex */
-+				{
-+					SPI_write(1,i,0x00,0x30050473);
-+					SPI_write(1,i,0x00,0x10050443);
-+					printk("Port%d:10M\n",i);
-+					switch_pre_link[i]=LINK_UP;
-+					switch_pre_speed[i]=GMAC_SPEED_10;
-+				}
-+				else{
-+					SPI_write(1,i,0x00,BIT(16));			// disable RX
-+					SPI_write(5,0,0x0E,BIT(i));			// dicard packet
-+					while((SPI_read(5,0,0x0C)&BIT(i))==0)		// wait to be empty
-+						msleep(1);
-+
-+					SPI_write(1,i,0x00,0x20000030);			// PORT_RST
-+					switch_pre_link[i]=LINK_DOWN;
-+					switch_pre_speed[i]=GMAC_SPEED_10;
-+					rcv_mask &= ~BIT(i);
-+					SPI_write(2,0,0x10,rcv_mask);			// Disable Receive
-+				}
- 			}
--#endif
- 		}
--		else if (tp->port_id == 1)
--		{
--#ifndef	INTERRUPT_SELECT
--			if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
--			{
--				if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
--					tp->hwtxq[3].eof_cnt++;
--				if (status1 & GMAC1_HWTQ12_EOF_INT_BIT)
--					tp->hwtxq[2].eof_cnt++;
--				if (status1 & GMAC1_HWTQ11_EOF_INT_BIT)
--					tp->hwtxq[1].eof_cnt++;
--				if (status1 & GMAC1_HWTQ10_EOF_INT_BIT)
--					tp->hwtxq[0].eof_cnt++;
--#endif	//INTERRUPT_SELECT
--#ifndef	INTERRUPT_SELECT
--			}
--#endif	//INTERRUPT_SELECT
--			if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
--			{
--				tp->default_q_intr_cnt++;
--				toe_gmac_handle_default_rxq(dev, tp);
--			}
--#ifdef CONFIG_SL351x_RXTOE
--			if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
--			    (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
--				//printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
--				toe_gmac_handle_toeq(dev, tp, status1);
--				//toe_gmac_handle_toeq(dev, toe, tp, status1);
--			}
- #endif
--		}
-+		gmac_get_switch_status(dev);
-+		gmac_write_reg(tp->base_addr, GMAC_STATUS, 0x7d, 0x0000007f);
-+//		SPI_write(2,0,0x10,rcv_mask);			// Enable Receive
-+		return ;
- 	}
-+#endif
- 
-+	reg_val = gmac_get_phy_vendor(tp->phy_addr);
-+	printk("GMAC-%d Addr %d Vendor ID: 0x%08x\n", tp->port_id, tp->phy_addr, reg_val);
- 
--	// Interrupt Status 0
--	if (status0 & tp->intr0_enabled)
--	{
--
--		#define ERR_INTR_BITS	(GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |	\
--								 GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |	\
--								 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |	\
--								 GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT)
--#ifndef	INTERRUPT_SELECT
--		if (status0 &  ERR_INTR_BITS)
--		{
--			if ((status0 & GMAC0_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXDERR_INT_BIT))
--			{
--				tp->txDerr_cnt[0]++;
--				printk("GMAC0 TX AHB Bus Error!\n");
--			}
--			if ((status0 & GMAC0_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXPERR_INT_BIT))
--			{
--				tp->txPerr_cnt[0]++;
--				printk("GMAC0 Tx Descriptor Protocol Error!\n");
--			}
--			if ((status0 & GMAC1_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXDERR_INT_BIT))
--			{
--				tp->txDerr_cnt[1]++;
--				printk("GMAC1 Tx AHB Bus Error!\n");
--			}
--			if ((status0 & GMAC1_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXPERR_INT_BIT))
--			{
--				tp->txPerr_cnt[1]++;
--				printk("GMAC1 Tx Descriptor Protocol Error!\n");
--			}
--
--			if ((status0 & GMAC0_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXDERR_INT_BIT))
--			{
--				tp->RxDerr_cnt[0]++;
--				printk("GMAC0 Rx AHB Bus Error!\n");
--			}
--			if ((status0 & GMAC0_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXPERR_INT_BIT))
--			{
--				tp->RxPerr_cnt[0]++;
--				printk("GMAC0 Rx Descriptor Protocol Error!\n");
--			}
--			if ((status0 & GMAC1_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXDERR_INT_BIT))
--			{
--				tp->RxDerr_cnt[1]++;
--				printk("GMAC1 Rx AHB Bus Error!\n");
--			}
--			if ((status0 & GMAC1_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXPERR_INT_BIT))
--			{
--				tp->RxPerr_cnt[1]++;
--				printk("GMAC1 Rx Descriptor Protocol Error!\n");
--			}
--		}
--#endif	//INTERRUPT_SELECT
--#ifndef	GMAX_TX_INTR_DISABLED
--		if (tp->port_id == 1 &&	netif_running(dev) &&
--			(((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
--			||
--			((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT))))
--		{
--			toe_gmac_tx_complete(&toe_private_data.gmac[1], 0, dev, 1);
--		}
--
--		if (tp->port_id == 0 &&	netif_running(dev) &&
--			(((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
--			||
--			((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT))))
--		{
--			toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
--		}
--#endif
--		// clear enabled status bits
--	}
--	// Interrupt Status 4
--#ifndef	INTERRUPT_SELECT
--	if (status4 & tp->intr4_enabled)
--	{
--		#define G1_INTR4_BITS		(0xff000000)
--		#define G0_INTR4_BITS		(0x00ff0000)
--
--		if (tp->port_id == 0)
--		{
--			if ((status4 & G0_INTR4_BITS) && (tp->intr4_enabled & G0_INTR4_BITS))
--			{
--				if (status4 & GMAC0_RESERVED_INT_BIT)
--					printk("GMAC0_RESERVED_INT_BIT is ON\n");
--				if (status4 & GMAC0_MIB_INT_BIT)
--					tp->mib_full_cnt++;
--				if (status4 & GMAC0_RX_PAUSE_ON_INT_BIT)
--					tp->rx_pause_on_cnt++;
--				if (status4 & GMAC0_TX_PAUSE_ON_INT_BIT)
--					tp->tx_pause_on_cnt++;
--				if (status4 & GMAC0_RX_PAUSE_OFF_INT_BIT)
--					tp->rx_pause_off_cnt++;
--				if (status4 & GMAC0_TX_PAUSE_OFF_INT_BIT)
--					tp->rx_pause_off_cnt++;
--				if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
--					tp->rx_overrun_cnt++;
--				if (status4 & GMAC0_STATUS_CHANGE_INT_BIT)
--					tp->status_changed_cnt++;
--			}
--		}
--		else if (tp->port_id == 1)
--		{
--			if ((status4 & G1_INTR4_BITS) && (tp->intr4_enabled & G1_INTR4_BITS))
--			{
--				if (status4 & GMAC1_RESERVED_INT_BIT)
--					printk("GMAC1_RESERVED_INT_BIT is ON\n");
--				if (status4 & GMAC1_MIB_INT_BIT)
--					tp->mib_full_cnt++;
--				if (status4 & GMAC1_RX_PAUSE_ON_INT_BIT)
--				{
--					//printk("Gmac pause on\n");
--					tp->rx_pause_on_cnt++;
--				}
--				if (status4 & GMAC1_TX_PAUSE_ON_INT_BIT)
--				{
--					//printk("Gmac pause on\n");
--					tp->tx_pause_on_cnt++;
--				}
--				if (status4 & GMAC1_RX_PAUSE_OFF_INT_BIT)
--				{
--					//printk("Gmac pause off\n");
--					tp->rx_pause_off_cnt++;
--				}
--				if (status4 & GMAC1_TX_PAUSE_OFF_INT_BIT)
--				{
--					//printk("Gmac pause off\n");
--					tp->rx_pause_off_cnt++;
--				}
--				if (status4 & GMAC1_RX_OVERRUN_INT_BIT)
--				{
--					//printk("Gmac Rx Overrun \n");
--					tp->rx_overrun_cnt++;
--				}
--				if (status4 & GMAC1_STATUS_CHANGE_INT_BIT)
--					tp->status_changed_cnt++;
--			}
--		}
--#if 0
--		if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
--		{
--			// unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--//			mac_stop_rxdma(tp->sc);
--			gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
--				tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
--
--			gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
--				SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
--			toe_gmac_fill_free_q();
--			tp->sw_fq_empty_cnt++;
--
--			gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
--				SWFQ_EMPTY_INT_BIT);
--//#if 0
--/*			if (netif_running(dev))
--				toe_gmac_handle_default_rxq(dev, tp);
--			printk("SWFQ_EMPTY_INT_BIT is ON!\n");	// should not be happened */
--//#endif
--		}
--#endif
--	}
--#endif	//INTERRUPT_SELECT
--	toe_gmac_enable_interrupt(tp->irq);
--//enable gmac rx function when do RFC 2544
--#ifdef IxscriptMate_1518
--	if (storlink_ctl.pauseoff == 1)
--	{
--		GMAC_CONFIG0_T config0;
--		config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
--		config0.bits.dis_rx = 0;
--		writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
--		config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
--		config0.bits.dis_rx = 0;
--		writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
--	}
--#endif
--	//printk("gmac_interrupt complete!\n\n");
--//	return IRQ_RETVAL(handled);
--	return	IRQ_RETVAL(1);
--#ifdef CONFIG_SL_NAPI
--}
--#endif
--}
--
--/*----------------------------------------------------------------------
--*	toe_gmac_handle_default_rxq
--*	(1) Get rx Buffer for default Rx queue
--*	(2) notify or call upper-routine to handle it
--*	(3) get a new buffer and insert it into SW free queue
--*	(4) Note: The SW free queue Read-Write Pointer should be locked when accessing
--*----------------------------------------------------------------------*/
--//static inline void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
--static void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
--{
--	TOE_INFO_T			*toe;
--    GMAC_RXDESC_T   	*curr_desc;
--	struct sk_buff 		*skb;
--    DMA_RWPTR_T			rwptr;
--	unsigned int 		pkt_size;
--	int					max_cnt;
--	unsigned int        desc_count;
--	unsigned int        good_frame, chksum_status, rx_status;
--	struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
--
--//when do ixia RFC 2544 test and packet size is select 1518 bytes,disable gmace rx function immediately after one interrupt come in.
--#ifdef IxscriptMate_1518
--	if (storlink_ctl.pauseoff == 1)
--	{
--		GMAC_CONFIG0_T config0;
--		config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
--		config0.bits.dis_rx = 1;
--		writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
--		config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
--		config0.bits.dis_rx = 1;
--		writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
--	}
--#endif
--	rwptr.bits32 = readl(&tp->default_qhdr->word1);
--#if 0
--	if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
--	{
--		mac_stop_txdma((struct net_device *)tp->dev);
--		printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
--				rwptr.bits32, tp->rx_rwptr.bits.rptr);
--		while(1);
--	}
--#endif
--	toe = (TOE_INFO_T *)&toe_private_data;
--	max_cnt = DEFAULT_RXQ_MAX_CNT;
--	while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr)
--//	while (rwptr.bits.rptr != rwptr.bits.wptr)
--	{
--//if packet size is not 1518 for RFC 2544,enable gmac rx function.The other packet size have RX workaround.
--#ifdef IxscriptMate_1518
--    	if (storlink_ctl.pauseoff == 1)
--		{
--			if (pkt_size != 1514)
--			{
--						GMAC_CONFIG0_T config0;
--						config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
--						config0.bits.dis_rx = 0;
--						writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
--						config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
--						config0.bits.dis_rx = 0;
--						writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
--			}
--		}
--#endif
--    	curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
--//		consistent_sync(curr_desc, sizeof(GMAC_RXDESC_T), PCI_DMA_FROMDEVICE);
--		tp->default_q_cnt++;
--    	tp->rx_curr_desc = (unsigned int)curr_desc;
--    	rx_status = curr_desc->word0.bits.status;
--    	chksum_status = curr_desc->word0.bits.chksum_status;
--    	tp->rx_status_cnt[rx_status]++;
--    	tp->rx_chksum_cnt[chksum_status]++;
--        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
--		desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
--		good_frame=1;
--		if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
--			|| (pkt_size < 60)
--		    || (chksum_status & 0x4)
--			|| rx_status)
--		{
--			good_frame = 0;
--			if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
--				printk("%s::derr (GMAC-%d)!!!\n", __func__, tp->port_id);
--			if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
--				printk("%s::perr (GMAC-%d)!!!\n", __func__, tp->port_id);
--			if (rx_status)
--			{
--				if (rx_status == 4 || rx_status == 7)
--					isPtr->rx_crc_errors++;
--//				printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
--			}
--#ifdef SL351x_GMAC_WORKAROUND
--			else if (pkt_size < 60)
--			{
--				if (tp->short_frames_cnt < GMAC_SHORT_FRAME_THRESHOLD)
--					tp->short_frames_cnt++;
--				if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
--				{
--					GMAC_CONFIG0_T config0;
--					config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
--					config0.bits.dis_rx = 1;
--					writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
--					config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
--					config0.bits.dis_rx = 1;
--					writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
--				}
--			}
--#endif
--//			if (chksum_status)
--//				printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
--			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
--			dev_kfree_skb_irq(skb);
--		}
--		if (good_frame)
--		{
--			if (curr_desc->word0.bits.drop)
--				printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
--//			if (chksum_status)
--//				printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
--
--	    	/* get frame information from the first descriptor of the frame */
--#ifdef SL351x_GMAC_WORKAROUND
--			if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
--			{
--				GMAC_CONFIG0_T config0;
--				config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
--				config0.bits.dis_rx = 0;
--				writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
--				config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
--				config0.bits.dis_rx = 0;
--				writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
--			}
--			tp->short_frames_cnt = 0;
--#endif
--			isPtr->rx_packets++;
--			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr - SKB_RESERVE_BYTES)));
--			if (!skb)
--			{
--				printk("Fatal Error!!skb==NULL\n");
--				goto next_rx;
--			}
--			tp->curr_rx_skb = skb;
--			// consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
--
--	//		curr_desc->word2.buf_adr = 0;
--
--			skb_reserve (skb, RX_INSERT_BYTES);	/* 16 byte align the IP fields. */
--			skb_put(skb, pkt_size);
--			skb->dev = dev;
--			if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
--			{
--				skb->ip_summed = CHECKSUM_UNNECESSARY;
--#ifdef CONFIG_SL351x_NAT
--				if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
--				{
--					struct iphdr	*ip_hdr;
--					ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
--					sl351x_nat_input(skb,
--									tp->port_id,
--									(void *)curr_desc->word3.bits.l3_offset,
--								  	(void *)curr_desc->word3.bits.l4_offset);
--				}
--#endif
--				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
--#if 0
--#ifdef CONFIG_SL351x_RXTOE
--				if (storlink_ctl.rx_max_pktsize) {
--					struct iphdr	*ip_hdr;
--					struct tcphdr	*tcp_hdr;
--					int ip_hdrlen;
--
-- 					ip_hdr = (struct iphdr*)&(skb->data[0]);
--					if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
--					   ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
--						ip_hdrlen = ip_hdr->ihl << 2;
--						tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
--						if (tcp_hdr->syn) {
--							struct toe_conn* connection = init_toeq(ip_hdr->version,
--									ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
--							TCP_SKB_CB(skb)->connection = connection;
--							//	hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
--							//		printk("%s::skb data %x, conn %x, mode %x\n",
--							//			__func__, skb->data, connection, connection->mode);
--						}
--					}
--				}
--#endif
--#endif
--			}
--			else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
--			{
--				skb->ip_summed = CHECKSUM_UNNECESSARY;
--#ifdef CONFIG_SL351x_NAT
--				if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
--				{
--					struct iphdr		*ip_hdr;
--					//struct tcphdr		*tcp_hdr;
--					ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
--					//tcp_hdr = (struct tcphdr *)&(skb->data[curr_desc->word3.bits.l4_offset]);
--					if (ip_hdr->protocol == IPPROTO_UDP)
--					{
--						sl351x_nat_input(skb,
--										tp->port_id,
--										(void *)curr_desc->word3.bits.l3_offset,
--								  		(void *)curr_desc->word3.bits.l4_offset);
--					}
--					else if (ip_hdr->protocol == IPPROTO_GRE)
--					{
--						sl351x_nat_input(skb,
--									tp->port_id,
--									(void *)curr_desc->word3.bits.l3_offset,
--								  	(void *)curr_desc->word3.bits.l4_offset);
--					}
--				}
--#endif
--				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
--			}
--			else
--			{
--				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
--			}
--
--			netif_rx(skb);  /* socket rx */
--			dev->last_rx = jiffies;
--
--			isPtr->rx_bytes += pkt_size;
--
--        }
--
--next_rx:
--		// advance one for Rx default Q 0/1
--		rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
--		SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
--     	tp->rx_rwptr.bits32 = rwptr.bits32;
--
--	}
--
--	/* Handles first available packets only then refill the queue. */
--	toe_gmac_fill_free_q();
--}
--
--/*----------------------------------------------------------------------
--* gmac_get_phy_vendor
--*----------------------------------------------------------------------*/
--static unsigned int gmac_get_phy_vendor(int phy_addr)
--{
--    unsigned int	reg_val;
--    reg_val=(mii_read(phy_addr,0x02) << 16) + mii_read(phy_addr,0x03);
--    return reg_val;
--}
--
--/*----------------------------------------------------------------------
--* gmac_set_phy_status
--*----------------------------------------------------------------------*/
--void gmac_set_phy_status(struct net_device *dev)
--{
--	GMAC_INFO_T *tp = dev->priv;
--	GMAC_STATUS_T   status;
--	unsigned int    reg_val, ability,wan_port_id;
--	unsigned int    i = 0;
--
--#ifdef VITESSE_G5SWITCH
--	if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1)){
--#if 0
--		rcv_mask = SPI_read(2,0,0x10);			// Receive mask
--		rcv_mask |= 0x4F;
--		for(i=0;i<4;i++){
--			reg_val = BIT(26)|(i<<21)|(10<<16);
--			SPI_write(3,0,1,reg_val);
--			msleep(10);
--			reg_val = SPI_read(3,0,2);
--			if(reg_val & 0x0c00){
--				printk("Port%d:Giga mode\n",i);
--				SPI_write(1,i,0x00,0x300701B1);
--				SPI_write(1,i,0x00,0x10070181);
--				switch_pre_link[i]=LINK_UP;
--				switch_pre_speed[i]=GMAC_SPEED_1000;
--			}
--			else{
--				reg_val = BIT(26)|(i<<21)|(5<<16);
--				SPI_write(3,0,1,reg_val);
--				msleep(10);
--				ability = (reg_val = SPI_read(3,0,2)&0x5e0) >>5;
--				if ((ability & 0x0C)) /* 100M full duplex */
--				{
--					SPI_write(1,i,0x00,0x30050472);
--					SPI_write(1,i,0x00,0x10050442);
--					printk("Port%d:100M\n",i);
--					switch_pre_link[i]=LINK_UP;
--				switch_pre_speed[i]=GMAC_SPEED_100;
--				}
--				else if((ability & 0x03)) /* 10M full duplex */
--				{
--					SPI_write(1,i,0x00,0x30050473);
--					SPI_write(1,i,0x00,0x10050443);
--					printk("Port%d:10M\n",i);
--					switch_pre_link[i]=LINK_UP;
--					switch_pre_speed[i]=GMAC_SPEED_10;
--				}
--				else{
--					SPI_write(1,i,0x00,BIT(16));			// disable RX
--					SPI_write(5,0,0x0E,BIT(i));			// dicard packet
--					while((SPI_read(5,0,0x0C)&BIT(i))==0)		// wait to be empty
--						msleep(1);
--
--					SPI_write(1,i,0x00,0x20000030);			// PORT_RST
--					switch_pre_link[i]=LINK_DOWN;
--					switch_pre_speed[i]=GMAC_SPEED_10;
--					rcv_mask &= ~BIT(i);
--					SPI_write(2,0,0x10,rcv_mask);			// Disable Receive
--				}
--			}
--		}
--#endif
--		gmac_get_switch_status(dev);
--		gmac_write_reg(tp->base_addr, GMAC_STATUS, 0x7d, 0x0000007f);
--//		SPI_write(2,0,0x10,rcv_mask);			// Enable Receive
--		return ;
--	}
--#endif
--
--	reg_val = gmac_get_phy_vendor(tp->phy_addr);
--	printk("GMAC-%d Addr %d Vendor ID: 0x%08x\n", tp->port_id, tp->phy_addr, reg_val);
--
--	switch (tp->phy_mode)
-+	switch (tp->phy_mode)
- 	{
- 		case GMAC_PHY_GMII:
- 		mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
-@@ -3552,6 +2982,7 @@
- 		status.bits.link = LINK_DOWN;
- 		//		clear_bit(__LINK_STATE_START, &dev->state);
- 		printk("Link Down (0x%04x) ", reg_val);
-+#ifdef VITESSE_G5SWITCH
- 		if(Giga_switch == 1)
- 		{
- 				wan_port_id = 1;
-@@ -3565,6 +2996,7 @@
- 				storlink_ctl.link[ tp->port_id] = 0;
- #endif
- 		}
-+#endif
- 	}
- 	else
- 	{
-@@ -3572,6 +3004,7 @@
- 		status.bits.link = LINK_UP;
- 		//		set_bit(__LINK_STATE_START, &dev->state);
- 		printk("Link Up (0x%04x) ",reg_val);
-+#ifdef VITESSE_G5SWITCH
- 		if(Giga_switch == 1)
- 		{
- 				wan_port_id = 1;
-@@ -3585,6 +3018,7 @@
- 				storlink_ctl.link[ tp->port_id] = 1;
- #endif
- 		}
-+#endif
- 	}
- 	//    value = mii_read(PHY_ADDR,0x05);
- 
-@@ -3863,6 +3297,7 @@
- 			}
- 		}
- 		status.bits.link = LINK_UP; /* link up */
-+#ifdef VITESSE_G5SWITCH
- 		if(Giga_switch==1)
- 		{
- 				wan_port_id = 1;
-@@ -3874,6 +3309,7 @@
- 				storlink_ctl.link[ tp->port_id] = 1;
- #endif
- 		}
-+#endif
- 		if ((ability & 0x20)==0x20)
- 		{
- 			if (tp->flow_control_enable == 0)
-@@ -3914,6 +3350,7 @@
- 	else
- 	{
- 		status.bits.link = LINK_DOWN; /* link down */
-+#ifdef VITESSE_G5SWITCH
- 		if(Giga_switch == 1)
- 		{
- 				wan_port_id = 1;
-@@ -3925,6 +3362,7 @@
- 				storlink_ctl.link[ tp->port_id] = 0;
- #endif
- 		}
-+#endif
- 		if (tp->pre_phy_status == LINK_UP)
- 		{
- 			printk("GMAC-%d LINK_Down......\n",tp->port_id);
-@@ -4298,86 +3736,102 @@
- }
- 
- #ifdef CONFIG_SL_NAPI
-+
-+static int gmax_rx(struct net_device *dev, int *budget)
-+{
-+	return 0;
-+}
-+
-+static int gmac_tx(struct net_device *dev, int *budget)
-+{
-+	return 0;
-+}
-+
- /*----------------------------------------------------------------------
- * gmac_rx_poll
- *----------------------------------------------------------------------*/
- static int gmac_rx_poll(struct net_device *dev, int *budget)
- {
--	TOE_INFO_T			*toe;
--    GMAC_RXDESC_T   	*curr_desc;
--	struct sk_buff 		*skb;
--    DMA_RWPTR_T			rwptr;
--    unsigned int data32;
--	unsigned int 		pkt_size;
--	unsigned int        desc_count;
--	unsigned int        good_frame, chksum_status, rx_status;
--	int                 rx_pkts_num = 0;
--	int                 quota = min(dev->quota, *budget);
--	GMAC_INFO_T			*tp = (GMAC_INFO_T *)dev->priv;
--	unsigned int		status4;
--	volatile DMA_RWPTR_T	fq_rwptr;
--	// int					max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
--	//unsigned long		rx_old_bytes;
-+	TOE_INFO_T	*toe;
-+	GMAC_RXDESC_T	*curr_desc;
-+	struct sk_buff	*skb;
-+	DMA_RWPTR_T	rwptr;
-+	unsigned int	data32;
-+	unsigned int	pkt_size;
-+	unsigned int	desc_count;
-+	unsigned int	good_frame, chksum_status, rx_status;
-+	int		rx_pkts_num = 0;
-+	int		quota = min(dev->quota, *budget);
-+	GMAC_INFO_T	*tp = (GMAC_INFO_T *)dev->priv;
-+	unsigned int	status1;
-+	unsigned int	status4;
- 	struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
--	//unsigned long long	rx_time;
--
- 
- 	BUG_ON(rx_poll_enabled == 0);
--#if 1
--	if (do_again)
--	{
--			toe_gmac_fill_free_q();
--			status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
--			fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--			//printk("\n%s:: do_again toe_gmac_fill_free_q =======>status4=0x%x =====fq_rwptr =0x%8x======>JKJKJKJKJKJKJKJKJ \n", __func__,status4,fq_rwptr.bits32);
--			if (fq_rwptr.bits.wptr != fq_rwptr.bits.rptr)
--			{
--						//status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
--						do_again =0;
--						//netif_rx_complete(dev);
--						gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,	0x1);
--						fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--						rwptr.bits32 = readl(&tp->default_qhdr->word1);
--			}
--			else
--				return 1;
--	}
--#endif
--	rwptr.bits32 = readl(&tp->default_qhdr->word1);
--#if 0
--	if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
--	{
--		mac_stop_txdma((struct net_device *)tp->dev);
--		printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
--				rwptr.bits32, tp->rx_rwptr.bits.rptr);
--		while(1);
--	}
--#endif
-+
- 	toe = (TOE_INFO_T *)&toe_private_data;
- 
--	fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--	//printk("%s:---Before-------------->Default Queue HW RW ptr (0x%8x),   fq_rwptr =0x%8x \n",__func__,rwptr.bits32,fq_rwptr.bits32 );
--	//printk("%s:---Before while   rx_pkts_num=%d------rx_finished_idx=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rx_finished_idx,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
--//	while ((--max_cnt) && (rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
-+rx_poll_retry:
-+	status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
-+	if (status1 & 1) {
-+		writel(1, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
-+	}
- 
-+	rwptr.bits32 = readl(&tp->default_qhdr->word1);
- 	while ((rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
- 	{
--
--    	curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
-+		curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
- 		tp->default_q_cnt++;
--    	tp->rx_curr_desc = (unsigned int)curr_desc;
--    	rx_status = curr_desc->word0.bits.status;
--    	chksum_status = curr_desc->word0.bits.chksum_status;
--    	tp->rx_status_cnt[rx_status]++;
--    	tp->rx_chksum_cnt[chksum_status]++;
--        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
-+		tp->rx_curr_desc = (unsigned int)curr_desc;
-+		rx_status = curr_desc->word0.bits.status;
-+		chksum_status = curr_desc->word0.bits.chksum_status;
-+		tp->rx_status_cnt[rx_status]++;
-+		tp->rx_chksum_cnt[chksum_status]++;
-+		pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
- 		desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
- 		good_frame=1;
-+
-+		if (0) {
-+
-+				int free, busy;
-+				uint32_t rwptr1;
-+				uint32_t rwptr2;
-+
-+				rwptr1 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+				free = (GET_WPTR(rwptr1) - GET_RPTR(rwptr1)) & 0xFF;
-+
-+				rwptr2 = readl(&tp->default_qhdr->word1);
-+				busy = (GET_RPTR(rwptr2) - GET_WPTR(rwptr2)) & 0xFF;
-+
-+				if (GET_WPTR(rwptr1) == GET_RPTR(rwptr1)) {
-+					printk("frame  status: %d\n"
-+					       "SWFQ: wptr: %hu, rptr: %hu, free: %d\n"
-+					       "GMAC: wptr: %hu, rptr: %hu, free: %d\n",
-+					       rx_status,
-+					       GET_WPTR(rwptr1), GET_RPTR(rwptr1), free,
-+					       GET_WPTR(rwptr2), GET_RPTR(rwptr2), busy);
-+				}
-+		}
-+
-+		{
-+			GMAC_RXDESC_T	*fq_desc;
-+			void *data;
-+			struct sk_buff *skb;
-+			unsigned short idx;
-+
-+			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
-+			idx = (unsigned short)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES + 4));
-+
-+			BUG_ON(idx > TOE_SW_FREEQ_DESC_NUM);
-+			BUG_ON(skb == NULL);
-+			fq_desc = (GMAC_RXDESC_T*)toe->swfq_desc_base + idx;
-+			fq_desc->word2.buf_adr = 0;
-+		}
-+
- 		if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
--			|| (pkt_size < 60)
-+		    || (pkt_size < 60)
- 		    || (chksum_status & 0x4)
- 		    || rx_status )
--//			|| rx_status || (rwptr.bits.rptr > rwptr.bits.wptr ))
- 		{
- 			good_frame = 0;
- 			if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
-@@ -4388,7 +3842,6 @@
- 			{
- 				if (rx_status == 4 || rx_status == 7)
- 					isPtr->rx_crc_errors++;
--//				printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
- 			}
- #ifdef SL351x_GMAC_WORKAROUND
- 			else if (pkt_size < 60)
-@@ -4407,17 +3860,32 @@
- 				}
- 			}
- #endif
--//			if (chksum_status)
--//				printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
- 			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
--			dev_kfree_skb_irq(skb);
-+			dev_kfree_skb(skb);
-+
-+			if (0) {
-+				int free, busy;
-+				uint32_t rwptr1;
-+				uint32_t rwptr2;
-+
-+				rwptr1 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
-+				free = (GET_WPTR(rwptr1) - GET_RPTR(rwptr1)) & 0xFF;
-+
-+				rwptr2 = readl(&tp->default_qhdr->word1);
-+				busy = (GET_RPTR(rwptr2) - GET_WPTR(rwptr2)) & 0xFF;
-+
-+				printk("frame  status: %d\n"
-+				       "SWFQ: wptr: %hu, rptr: %hu, free: %d\n"
-+				       "GMAC: wptr: %hu, rptr: %hu, free: %d\n",
-+				       rx_status,
-+				       GET_WPTR(rwptr1), GET_RPTR(rwptr1), free,
-+				       GET_WPTR(rwptr2), GET_RPTR(rwptr2), busy);
-+			}
- 		}
- 		if (good_frame)
- 		{
- 			if (curr_desc->word0.bits.drop)
- 				printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
--//			if (chksum_status)
--//				printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
- 
- #ifdef SL351x_GMAC_WORKAROUND
- 			if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
-@@ -4432,225 +3900,118 @@
- 			}
- 			tp->short_frames_cnt = 0;
- #endif
--	    	/* get frame information from the first descriptor of the frame */
-+			/* get frame information from the first descriptor of the frame */
- 			isPtr->rx_packets++;
--			//consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
-+			consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
- 			skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
- 			tp->curr_rx_skb = skb;
--	//		curr_desc->word2.buf_adr = 0;
- 
--		    //skb_reserve (skb, SKB_RESERVE_BYTES);
- 			skb_reserve (skb, RX_INSERT_BYTES);	/* 2 byte align the IP fields. */
--			//if ((skb->tail+pkt_size) > skb->end )
--			//printk("%s::------------->Here skb->len=%d,pkt_size= %d,skb->head=0x%x,skb->tail= 0x%x, skb->end= 0x%x\n", __func__, skb->len, pkt_size,skb->head,skb->tail,skb->end);
- 			skb_put(skb, pkt_size);
- 
--
- 			skb->dev = dev;
- 			if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
- 			{
- 				skb->ip_summed = CHECKSUM_UNNECESSARY;
--#ifdef CONFIG_SL351x_NAT
--				if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
--				{
--					struct iphdr	*ip_hdr;
--					ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
--					sl351x_nat_input(skb,
--									tp->port_id,
--									(void *)curr_desc->word3.bits.l3_offset,
--								  	(void *)curr_desc->word3.bits.l4_offset);
--				}
--#endif
- 				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
--#if 0
--#ifdef CONFIG_SL351x_RXTOE
--				if (storlink_ctl.rx_max_pktsize) {
--					struct iphdr	*ip_hdr;
--					struct tcphdr	*tcp_hdr;
--					int ip_hdrlen;
--
-- 					ip_hdr = (struct iphdr*)&(skb->data[0]);
--					if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
--					   ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
--						ip_hdrlen = ip_hdr->ihl << 2;
--						tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
--						if (tcp_hdr->syn) {
--							struct toe_conn* connection = init_toeq(ip_hdr->version,
--									ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
--							TCP_SKB_CB(skb)->connection = connection;
--							//	hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
--							//		printk("%s::skb data %x, conn %x, mode %x\n",
--							//			__func__, skb->data, connection, connection->mode);
--						}
--					}
--				}
--#endif
--#endif
- 			}
- 			else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
- 			{
- 				skb->ip_summed = CHECKSUM_UNNECESSARY;
--#ifdef CONFIG_SL351x_NAT
--				if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
--				{
--					struct iphdr	*ip_hdr;
--					ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
--					if (ip_hdr->protocol == IPPROTO_UDP)
--					{
--						sl351x_nat_input(skb,
--										tp->port_id,
--										(void *)curr_desc->word3.bits.l3_offset,
--								  		(void *)curr_desc->word3.bits.l4_offset);
--					}
--					else if (ip_hdr->protocol == IPPROTO_GRE)
--					{
--						sl351x_nat_input(skb,
--									tp->port_id,
--									(void *)curr_desc->word3.bits.l3_offset,
--								  	(void *)curr_desc->word3.bits.l4_offset);
--					}
--				}
--#endif
- 				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
- 			}
- 			else
- 			{
- 				skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
- 			}
--			//netif_rx(skb);  /* socket rx */
-+
- 			netif_receive_skb(skb); //For NAPI
- 			dev->last_rx = jiffies;
- 
- 			isPtr->rx_bytes += pkt_size;
--			//printk("------------------->isPtr->rx_bytes = %d\n",isPtr->rx_bytes);
--
-+		}
- 
--        }
- 		// advance one for Rx default Q 0/1
- 		rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
- 		SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
--     	tp->rx_rwptr.bits32 = rwptr.bits32;
-+		tp->rx_rwptr.bits32 = rwptr.bits32;
- 		rx_pkts_num++;
--		//rwptr.bits32 = readl(&tp->default_qhdr->word1);//try read default_qhdr again
--		//fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--		//printk("%s:---Loop  -------->rx_pkts_num=%d------------>Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits32,fq_rwptr.bits32 );
--#if 0
--		if ((status4 & 0x1) == 0)
--		{
--			//if (!((dev->last_rx <= (rx_time + 2)) &&  (isPtr->rx_bytes > (rx_old_bytes + 1000000 ))))
--			if (tp->total_q_cnt_napi < 1024)
--			{
--				tp->total_q_cnt_napi++;
--				toe_gmac_fill_free_q();  //for iperf test disable
--			}
--			//else
--				//printk("%s:---isPtr->rx_bytes =%u , rx_old_bytes =%u\n",__func__,isPtr->rx_bytes,rx_old_bytes );
-+		// rwptr.bits32 = readl(&tp->default_qhdr->word1);
- 
-+		status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+		if (status4 & 1) {
-+			writel(status4 & SWFQ_EMPTY_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
- 		}
-+
-+		toe_gmac_fill_free_q(5);
-+	}
-+
-+#if 0
-+	/* avoid races with hard_start_xmit() */
-+
-+	spin_lock(&gmac_fq_lock);
-+	toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
-+	spin_unlock(&gmac_fq_lock);
- #endif
--		//rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
--		//printk("%s:---Loop  -------->rx_pkts_num=%d----rwptr.bits.rptr=0x%x-------->Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits32,fq_rwptr.bits32 );
--		//printk("%s:---Loop  rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
-+
-+	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+	if (status4 & 1)
-+	{
-+		writel(status4 & SWFQ_EMPTY_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
-+		status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
-+		toe_gmac_fill_free_q(rx_pkts_num);
- 	}
--	// advance one for Rx default Q 0/1
- 
--		//rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
--		//SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
--     	//tp->rx_rwptr.bits32 = rwptr.bits32;
--     	//rwptr.bits.rptr = rwptr.bits.rptr;
-+	rwptr.bits32 = readl(&tp->default_qhdr->word1);
-+	if (rwptr.bits.rptr != rwptr.bits.wptr &&
-+	    quota > rx_pkts_num)
-+		goto rx_poll_retry;
- 
- 	dev->quota -= rx_pkts_num;
- 	*budget -= rx_pkts_num;
- 
--	status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);//try read SWFQ empty again
--	//fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
--	rwptr.bits32 = readl(&tp->default_qhdr->word1); //try read default_qhdr again
--	//printk("%s:---After    rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
--//	if (rwptr.bits.rptr > rwptr.bits.wptr )
--//			{
--				//toe_gmac_disable_rx(dev);
--				//wait_event_interruptible_timeout(freeq_wait,
--					//(rx_pkts_num == 100), CMTP_INTEROP_TIMEOUT);
--				//printk("\n%s:: return 22222=======> rx_pkts_num =%d,   rwptr.bits.rptr=%d,   rwptr.bits.wptr = %d ====---------=======>JKJKJKJKJK\n",
--					//__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
--//				return 1;
--//			}
--
--	if (rwptr.bits.rptr == rwptr.bits.wptr)
-+	/* Receive queue is empty now */
-+	if (quota >= rx_pkts_num)
- 	{
--		// unsigned int data32;
--			//printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr]   rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
--
--	    /* Receive descriptor is empty now */
--#if 1
--     if (status4 & 0x1)
--   			{
--   				do_again =1;
--   				//writel(0x40400000, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_4_REG); //disable SWFQ empty interrupt
--   				//toe_gmac_disable_interrupt(tp->irq);
--   				tp->sw_fq_empty_cnt++;
--   				//toe_gmac_disable_rx(dev);
--   				writel(0x07960202, TOE_GMAC0_BASE+GMAC_CONFIG0);
--				writel(0x07960202, TOE_GMAC1_BASE+GMAC_CONFIG0);
--   				//printk("\n%s ::  freeq int-----tp->sw_fq_empty_cnt  =%d---------====================----------------->\n",__func__,tp->sw_fq_empty_cnt);
--   				//while ((fq_rwptr.bits.wptr >= (fq_rwptr.bits.rptr+256)) || (fq_rwptr.bits.wptr <= (fq_rwptr.bits.rptr+256)))
--   				//{
--   					//gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
--					//0x1);
--				//printk("\n%s::fq_rwptr.wrptr = %x =======> ===========>here \n", __func__,fq_rwptr.bits32);
--				//if ((status4 & 0x1) == 0)
--					//break;
--				 return 1;
--				//}
-+		unsigned long flags;
- 
-+		netif_rx_complete(dev);
-+		rx_poll_enabled = 0;
-+#if 0
-+		status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
-+		if (status1 & 1) {
-+			if (netif_rx_reschedule(dev, rx_pkts_num)) {
-+				rx_poll_enabled = 1;
-+				return 1;
- 			}
-+		}
- #endif
--        //toe_gmac_fill_free_q();
--        netif_rx_complete(dev);
--
--		rx_poll_enabled = 0;
- 
--		data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
--		if (tp->port_id == 0)
--				data32 |= DEFAULT_Q0_INT_BIT;
--		else
--				data32 |= DEFAULT_Q1_INT_BIT;
--		writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+		spin_lock_irqsave(&gmac_fq_lock, flags);
- 
- 		data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
- 		if (tp->port_id == 0)
--				data32 |= DEFAULT_Q0_INT_BIT;
-+			data32 |= DEFAULT_Q0_INT_BIT;
- 		else
--				data32 |= DEFAULT_Q1_INT_BIT;
-+			data32 |= DEFAULT_Q1_INT_BIT;
- 		writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
- 
--		data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+		data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
- 		if (tp->port_id == 0)
--				data32 |= DEFAULT_Q0_INT_BIT;
-+			data32 |= DEFAULT_Q0_INT_BIT;
- 		else
--				data32 |= DEFAULT_Q1_INT_BIT;
--		writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
-+			data32 |= DEFAULT_Q1_INT_BIT;
-+		writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
- 
--        // enable GMAC-0 rx interrupt
--        // class-Q & TOE-Q are implemented in future
--        //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
--        //if (tp->port_id == 0)
--        	//data32 |= DEFAULT_Q0_INT_BIT;
--        //else
--        	//data32 |= DEFAULT_Q1_INT_BIT;
--        //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
--		writel(0x3, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
--		//printk("\n%s::netif_rx_complete-->  rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x ====---------=======>JKJKJKJKJK\n",
--		//__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
--        writel(0x07960200, TOE_GMAC0_BASE+GMAC_CONFIG0);
--		writel(0x07960200, TOE_GMAC1_BASE+GMAC_CONFIG0);
--        return 0;
--    }
--    else
--    {
--        //printk("\n%s:: return 1 -->status4= 0x%x,rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x  ======> \n", __func__,status4,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
--        return 1;
--    }
-+		spin_unlock_irqrestore(&gmac_fq_lock, flags);
-+
-+		return 0;
-+	}
-+	else
-+	{
-+		/* not done, will call ->poll() later. */
-+		return 1;
-+	}
- }
- #endif
- 
-@@ -5114,6 +4475,7 @@
- 			{
- 				sl351x_nat_workaround_cnt++;
- 				sl351x_nat_workaround_handler();
-+				printk("%():%d - workaround\n", __func__, __LINE__);
- 			}
- #endif
- #endif
-@@ -5124,6 +4486,7 @@
- 	}
- 
- do_workaround:
-+	printk("doing workaround ?!\n");
- 
- 	gmac_initialized = 0;
- 	if (hanged_state)
-@@ -5290,6 +4653,7 @@
- 	GMAC_SWTXQ_T	*swtxq;
- 	DMA_RWPTR_T		rwptr;
- 
-+	printk("**** %s():%d\n", __func__, __LINE__);
- 	toe = (TOE_INFO_T *)&toe_private_data;
- 	tp = (GMAC_INFO_T *)&toe->gmac[0];
- 	for (i=0; igmac[0];
- 	for (i=0; iclassq[0];
- 	for (i=0; i
- #include 
- 
-+//****** Storlink SoC ******
- #define AMD_BOOTLOC_BUG
--#define FORCE_WORD_WRITE 0
--
--#define MAX_WORD_RETRIES 3
-+//#define FORCE_WORD_WRITE 0
-+#define FORCE_WORD_WRITE 1
-+#define FORCE_FAST_PROG 0
-+
-+//#define MAX_WORD_RETRIES 3
-+#define MAX_WORD_RETRIES 3 // CONFIG_MTD_CFI_AMDSTD_RETRY
-+//**************************
- 
- #define MANUFACTURER_AMD	0x0001
- #define MANUFACTURER_ATMEL	0x001F
-@@ -322,6 +327,13 @@
- #endif
- 
- 		bootloc = extp->TopBottom;
-+//****** Storlink SoC ******
-+		if(bootloc == 5)
-+		{
-+			bootloc = 3;
-+			extp->TopBottom = 3;
-+		}
-+//**************************
- 		if ((bootloc != 2) && (bootloc != 3)) {
- 			printk(KERN_WARNING "%s: CFI does not contain boot "
- 			       "bank location. Assuming top.\n", map->name);
-@@ -340,6 +352,9 @@
- 				cfi->cfiq->EraseRegionInfo[j] = swap;
- 			}
- 		}
-+#ifdef CONFIG_MTD_MAP_BANK_WIDTH_1
-+		cfi->device_type = CFI_DEVICETYPE_X8;
-+#endif
- 		/* Set the default CFI lock/unlock addresses */
- 		cfi->addr_unlock1 = 0x555;
- 		cfi->addr_unlock2 = 0x2aa;
-@@ -461,6 +476,7 @@
- 	map_word d, t;
- 
- 	d = map_read(map, addr);
-+	udelay(20);	//Storlink SoC
- 	t = map_read(map, addr);
- 
- 	return map_word_equal(map, d, t);
-@@ -626,7 +642,9 @@
- 	default:
- 		printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
- 	}
-+//****** Storlink SoC ******
- 	wake_up(&chip->wq);
-+//**************************
- }
- 
- #ifdef CONFIG_MTD_XIP
-@@ -940,7 +958,9 @@
- 	cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
- 	cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
- 
-+//****** Storlink SoC ******
- 	wake_up(&chip->wq);
-+//**************************
- 	spin_unlock(chip->mutex);
- 
- 	return 0;
-@@ -1005,7 +1025,10 @@
- 	 */
- 	unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
- 	int ret = 0;
--	map_word oldd;
-+//****** Storlink SoC ******
-+//	map_word oldd;
-+	map_word oldd, tmp;
-+//**************************
- 	int retry_cnt = 0;
- 
- 	adr += chip->start;
-@@ -1037,9 +1060,15 @@
- 	ENABLE_VPP(map);
- 	xip_disable(map, chip, adr);
-  retry:
-+//****** Storlink SoC ******
-+#if FORCE_FAST_PROG  /* Unlock bypass */
-+	cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
-+#else
- 	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
- 	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
- 	cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
-+#endif
-+//**************************
- 	map_write(map, datum, adr);
- 	chip->state = FL_WRITING;
- 
-@@ -1072,7 +1101,13 @@
- 		}
- 
- 		if (chip_ready(map, adr))
--			break;
-+		{
-+			tmp = map_read(map, adr);
-+			if(map_word_equal(map, tmp, datum))
-+//				goto op_done;
-+                break;
-+
-+		}
- 
- 		/* Latency issues. Drop the lock, wait a while and retry */
- 		UDELAY(map, chip, adr, 1);
-@@ -1084,8 +1119,17 @@
- 		/* FIXME - should have reset delay before continuing */
- 
- 		if (++retry_cnt <= MAX_WORD_RETRIES)
-+		{
-+//****** Storlink SoC ******
-+#if FORCE_FAST_PROG
-+			cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
-+			cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
-+			cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
-+		//udelay(1);
-+#endif
-+			udelay(1);
- 			goto retry;
--
-+		}
- 		ret = -EIO;
- 	}
- 	xip_enable(map, chip, adr);
-@@ -1171,7 +1215,14 @@
- 				return 0;
- 		}
- 	}
--
-+//****** Storlink SoC ******
-+	map_write( map, CMD(0xF0), chipstart );
-+#if FORCE_FAST_PROG
-+		cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
-+		cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
-+		cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
-+#endif
-+//**************************
- 	/* We are now aligned, write as much as possible */
- 	while(len >= map_bankwidth(map)) {
- 		map_word datum;
-@@ -1181,7 +1232,15 @@
- 		ret = do_write_oneword(map, &cfi->chips[chipnum],
- 				       ofs, datum);
- 		if (ret)
-+		{
-+//****** Storlink SoC ******
-+#if FORCE_FAST_PROG
-+			/* Get out of unlock bypass mode */
-+			cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+			cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+#endif
- 			return ret;
-+		}
- 
- 		ofs += map_bankwidth(map);
- 		buf += map_bankwidth(map);
-@@ -1189,19 +1248,38 @@
- 		len -= map_bankwidth(map);
- 
- 		if (ofs >> cfi->chipshift) {
-+//****** Storlink SoC ******
-+#if FORCE_FAST_PROG
-+			/* Get out of unlock bypass mode */
-+			cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+			cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+#endif
- 			chipnum ++;
- 			ofs = 0;
- 			if (chipnum == cfi->numchips)
- 				return 0;
- 			chipstart = cfi->chips[chipnum].start;
-+#if FORCE_FAST_PROG
-+			/* Go into unlock bypass mode for next set of chips */
-+			cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
-+			cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
-+			cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
-+#endif
- 		}
- 	}
- 
-+#if FORCE_FAST_PROG
-+	/* Get out of unlock bypass mode */
-+	cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+	cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+#endif
-+
- 	/* Write the trailing bytes if any */
- 	if (len & (map_bankwidth(map)-1)) {
- 		map_word tmp_buf;
- 
-  retry1:
-+
- 		spin_lock(cfi->chips[chipnum].mutex);
- 
- 		if (cfi->chips[chipnum].state != FL_READY) {
-@@ -1221,7 +1299,11 @@
- #endif
- 			goto retry1;
- 		}
--
-+#if FORCE_FAST_PROG
-+		cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
-+		cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
-+		cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
-+#endif
- 		tmp_buf = map_read(map, ofs + chipstart);
- 
- 		spin_unlock(cfi->chips[chipnum].mutex);
-@@ -1231,11 +1313,23 @@
- 		ret = do_write_oneword(map, &cfi->chips[chipnum],
- 				ofs, tmp_buf);
- 		if (ret)
-+		{
-+#if FORCE_FAST_PROG
-+	/* Get out of unlock bypass mode */
-+	cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+	cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+#endif
- 			return ret;
--
-+		}
-+#if FORCE_FAST_PROG
-+	/* Get out of unlock bypass mode */
-+	cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+	cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
-+#endif
- 		(*retlen) += len;
- 	}
- 
-+	map_write( map, CMD(0xF0), chipstart );
- 	return 0;
- }
- 
-@@ -1275,6 +1369,7 @@
- 	ENABLE_VPP(map);
- 	xip_disable(map, chip, cmd_adr);
- 
-+	map_write( map, CMD(0xF0), chip->start );	//Storlink
- 	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
- 	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
- 	//cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
-@@ -1535,6 +1630,9 @@
- 	DECLARE_WAITQUEUE(wait, current);
- 	int ret = 0;
- 
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_lock();				// sl2312 share pin lock
-+#endif
- 	adr += chip->start;
- 
- 	spin_lock(chip->mutex);
-@@ -1613,6 +1711,9 @@
- 	chip->state = FL_READY;
- 	put_chip(map, chip, adr);
- 	spin_unlock(chip->mutex);
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_unlock();				// sl2312 share pin lock
-+#endif
- 	return ret;
- }
- 
---- /dev/null
-+++ b/drivers/mtd/chips/map_serial.c
-@@ -0,0 +1,188 @@
-+/*
-+ * Common code to handle map devices which are simple ROM
-+ * (C) 2000 Red Hat. GPL'd.
-+ * $Id: map_serial.c,v 1.3 2006/06/05 02:34:54 middle Exp $
-+ */
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+#include  //add
-+#include 
-+#include 
-+
-+static int mapserial_erase(struct mtd_info *mtd, struct erase_info *instr);
-+static int mapserial_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
-+static int mapserial_write (struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
-+static void mapserial_nop (struct mtd_info *);
-+struct mtd_info *map_serial_probe(struct map_info *map);
-+
-+extern int m25p80_sector_erase(__u32 address, __u32 schip_en);
-+
-+static struct mtd_chip_driver mapserial_chipdrv = {
-+	probe: map_serial_probe,
-+	name: "map_serial",
-+	module: THIS_MODULE
-+};
-+
-+struct mtd_info *map_serial_probe(struct map_info *map)
-+{
-+	struct mtd_info *mtd;
-+
-+	mtd = kmalloc(sizeof(*mtd), GFP_KERNEL);
-+	if (!mtd)
-+		return NULL;
-+
-+	memset(mtd, 0, sizeof(*mtd));
-+
-+	map->fldrv = &mapserial_chipdrv;
-+	mtd->priv = map;
-+	mtd->name = map->name;
-+	mtd->type = MTD_OTHER;
-+	mtd->erase = mapserial_erase;
-+	mtd->size = map->size;
-+	mtd->read = mapserial_read;
-+	mtd->write = mapserial_write;
-+	mtd->sync = mapserial_nop;
-+	mtd->flags = (MTD_WRITEABLE|MTD_ERASEABLE);
-+//	mtd->erasesize = 512; // page size;
-+#ifdef CONFIG_MTD_SL2312_SERIAL_ST
-+	mtd->erasesize = M25P80_SECTOR_SIZE; // block size;
-+#else
-+	mtd->erasesize = 0x1000; // block size;
-+#endif
-+
-+	__module_get(THIS_MODULE);
-+	//MOD_INC_USE_COUNT;
-+	return mtd;
-+}
-+
-+#define	FLASH_ACCESS_OFFSET	        		0x00000010
-+#define	FLASH_ADDRESS_OFFSET            		0x00000014
-+#define	FLASH_WRITE_DATA_OFFSET         		0x00000018
-+#define	FLASH_READ_DATA_OFFSET          		0x00000018
-+
-+static __u32 readflash_ctrl_reg(__u32 ofs)
-+{
-+    __u32 *base;
-+
-+    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
-+    return __raw_readl(base);
-+}
-+
-+static void writeflash_ctrl_reg(__u32 data, __u32 ofs)
-+{
-+    __u32 *base;
-+
-+    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
-+    __raw_writel(data, base);
-+}
-+
-+static int mapserial_erase_block(struct map_info *map,unsigned int block)
-+{
-+
-+	__u32 address;
-+#ifdef CONFIG_MTD_SL2312_SERIAL_ST
-+
-+	if(!m25p80_sector_erase(block, 0))
-+		return (MTD_ERASE_DONE);
-+#else
-+      __u32 opcode;
-+      __u32 count=0;
-+//      __u8  status;
-+
-+ //     printk("mapserial_erase_block : erase block %d \n",block);
-+//      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd;
-+      opcode = 0x80000000 | 0x0200 | 0x50;
-+      address = (block << 13);
-+      writeflash_ctrl_reg(address,FLASH_ADDRESS_OFFSET);
-+      writeflash_ctrl_reg(opcode,FLASH_ACCESS_OFFSET);
-+      opcode=readflash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      while(opcode&0x80000000)
-+      {
-+          opcode = readflash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+          count++;
-+          if (count > 10000)
-+          {
-+            return (MTD_ERASE_FAILED);
-+          }
-+      }
-+      return (MTD_ERASE_DONE);
-+#endif
-+}
-+
-+static int mapserial_erase(struct mtd_info *mtd, struct erase_info *instr)
-+{
-+	struct map_info *map = (struct map_info *)mtd->priv;
-+    unsigned int    addr;
-+    int             len;
-+    unsigned int    block;
-+    unsigned int    ret=0;
-+
-+	addr = instr->addr;
-+	len = instr->len;
-+    while (len > 0)
-+    {
-+        block = addr / mtd->erasesize;
-+#ifdef CONFIG_MTD_SL2312_SERIAL_ST
-+        ret = mapserial_erase_block(map,addr);
-+#else
-+		ret = mapserial_erase_block(map,block);
-+#endif
-+        addr = addr + mtd->erasesize;
-+        len = len - mtd->erasesize;
-+    }
-+    return (ret);
-+}
-+
-+static int mapserial_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
-+{
-+	struct map_info *map = (struct map_info *)mtd->priv;
-+//        printk("mapserial_read : \n");
-+	map->copy_from(map, buf, from, len);
-+	*retlen = len;
-+	return 0;
-+}
-+
-+static void mapserial_nop(struct mtd_info *mtd)
-+{
-+	/* Nothing to see here */
-+}
-+
-+static int mapserial_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
-+{
-+	struct map_info *map = (struct map_info *)mtd->priv;
-+//	printk("mapserial_write : buf %x to %x len %x \n",(int)buf, (int)to, (int)len);
-+	//map->copy_to(map, buf, to, len);
-+	map->copy_to(map, to, buf, len);
-+	*retlen = len;
-+	return 0;
-+}
-+
-+int __init map_serial_init(void)
-+{
-+	register_mtd_chip_driver(&mapserial_chipdrv);
-+	return 0;
-+}
-+
-+static void __exit map_serial_exit(void)
-+{
-+	unregister_mtd_chip_driver(&mapserial_chipdrv);
-+}
-+
-+module_init(map_serial_init);
-+module_exit(map_serial_exit);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("David Woodhouse ");
-+MODULE_DESCRIPTION("MTD chip driver for ROM chips");
---- a/drivers/mtd/maps/Kconfig
-+++ b/drivers/mtd/maps/Kconfig
-@@ -614,5 +614,30 @@
- 
- 	  This selection automatically selects the map_ram driver.
- 
-+#***************************************************************************************
-+# Storlink parallel/Serial Flash configuration
-+#***************************************************************************************
-+config MTD_SL2312_CFI
-+        tristate "CFI Flash device mapped on SL2312"
-+        depends on MTD_CFI
-+        help
-+          Map driver for SL2312 demo board.
-+
-+config MTD_SL2312_SERIAL_ATMEL
-+        tristate "ATMEL Serial Flash device mapped on SL2312"
-+        depends on MTD_PARTITIONS && ARCH_SL2312
-+        help
-+          Map driver for SL2312 demo board.
-+
-+config MTD_SL2312_SERIAL_ST
-+        tristate "ST Serial Flash device mapped on SL2312"
-+        depends on MTD_PARTITIONS && ARCH_SL2312
-+        help
-+          Map driver for SL2312 demo board.
-+
-+config SL2312_SHARE_PIN
-+        tristate "Parallel Flash share pin on SL2312 ASIC"
-+        depends on SL3516_ASIC
-+
- endmenu
- 
---- /dev/null
-+++ b/drivers/mtd/maps/sl2312-flash-atmel.c
-@@ -0,0 +1,554 @@
-+/*
-+ * $Id: sl2312-flash-atmel.c,v 1.2 2006/06/05 02:35:57 middle Exp $
-+ *
-+ * Flash and EPROM on Hitachi Solution Engine and similar boards.
-+ *
-+ * (C) 2001 Red Hat, Inc.
-+ *
-+ * GPL'd
-+ */
-+
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include  //add
-+
-+
-+#define  g_page_addr  AT45DB321_PAGE_SHIFT    //321 : shift 10  ; 642 : shift 11
-+#define  g_chipen     SERIAL_FLASH_CHIP0_EN   //atmel
-+
-+extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
-+
-+void address_to_page(__u32 address, __u16 *page, __u16 *offset)
-+{
-+    *page = address / SPAGE_SIZE;
-+    *offset = address % SPAGE_SIZE;
-+}
-+
-+static __u32 read_flash_ctrl_reg(__u32 ofs)
-+{
-+    __u32 *base;
-+
-+    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
-+    return __raw_readl(base);
-+}
-+
-+static void write_flash_ctrl_reg(__u32 ofs,__u32 data)
-+{
-+    __u32 *base;
-+
-+    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
-+    __raw_writel(data, base);
-+}
-+
-+void atmel_read_status(__u8 cmd, __u8 *data)
-+{
-+      __u32 opcode;
-+      __u32 value;
-+
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | cmd | g_chipen;
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      while(opcode&0x80000000)
-+      {
-+          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+          flash_delay();
-+          schedule();
-+      }
-+
-+      value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      *data = value & 0xff;
-+}
-+
-+void main_memory_page_read(__u8 cmd, __u16 page, __u16 offset, __u8 *data)
-+{
-+      __u32 opcode;
-+      __u32 address;
-+      __u32 value;
-+
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA | cmd | g_chipen;
-+      address = (page << g_page_addr) + offset;
-+      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      while(opcode&0x80000000)
-+      {
-+          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+          flash_delay();
-+          schedule();
-+      }
-+
-+      value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      *data = value & 0xff;
-+}
-+
-+void buffer_to_main_memory(__u8 cmd, __u16 page)
-+{
-+      __u32 opcode;
-+      __u32 address;
-+      __u8  status;
-+
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
-+      address = (page << g_page_addr);
-+      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      while(opcode&0x80000000)
-+      {
-+          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+          flash_delay();
-+          schedule();
-+      }
-+      atmel_read_status(READ_STATUS_SPI, &status);
-+      while(!(status&0x80))
-+      {
-+          atmel_read_status(READ_STATUS_SPI, &status);
-+          flash_delay();
-+          schedule();
-+      }
-+
-+}
-+
-+
-+void atmel_flash_read_page(__u32 address, __u8 *buffer, __u32 len)
-+{
-+    __u8  byte;
-+    __u16 page, offset;
-+    __u16 i;
-+
-+    address_to_page(address, &page, &offset);
-+
-+     for(i=0; i> 8;
-+//printk("sl2312_write32:: address = %08x  data = %c \n",ofs,byte);
-+    }
-+#else
-+      write_flash_ctrl_reg(ofs, d);
-+#endif
-+}
-+
-+void sl2312_write8(struct map_info *map, __u8 d, unsigned long ofs)
-+{
-+     __u16 page, offset;
-+
-+     address_to_page(ofs, &page, &offset);
-+     main_memory_page_program(MAIN_MEMORY_PROGRAM_BUFFER1, page, offset, d);
-+//printk("sl2312_write8:: address = %08x  data = %c \n",ofs,d);
-+
-+}
-+
-+void sl2312_copy_from(struct map_info *map, void *buf, unsigned long ofs, ssize_t len)
-+{
-+     __u32 size;
-+     __u8  *buffer;
-+     __u32 length;//i, j,
-+
-+     //printk("sl2312_copy_from:: address = %08x  datalen = %d \n",ofs,len);
-+
-+     length = len;
-+     buffer = (__u8 *)buf;
-+     while(len)
-+     {
-+        size = SPAGE_SIZE - (ofs%SPAGE_SIZE);
-+        if(size > len)
-+            size = len;
-+        atmel_flash_read_page(ofs, buffer, size);
-+        buffer+=size;
-+        ofs+=size;
-+        len -= size;
-+     }
-+
-+#if 0
-+        buffer = (__u8 *)buf;
-+        for(i=0; i len)
-+            size = len;
-+        atmel_flash_program_page(ofs, buffer, size);
-+        buffer+=size;
-+        ofs+=size;
-+	len-=size;
-+    }
-+
-+
-+}
-+
-+
-+static struct mtd_info *serial_mtd;
-+
-+static struct mtd_partition *parsed_parts;
-+
-+static struct map_info sl2312_serial_map = {
-+//	name: "SL2312 serial flash",
-+//	size: 4194304, //0x400000,
-+//		//buswidth: 4,
-+//	bankwidth: 4,
-+//	phys:		 SL2312_FLASH_BASE,
-+//#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
-+//	//read32: sl2312_read32,
-+//	//read8: sl2312_read8,
-+//	copy_from: sl2312_copy_from,
-+//	//write8: sl2312_write8,
-+//	//write32: sl2312_write32,
-+//	read: sl2312_read32,
-+//	write: sl2312_write32,
-+//	copy_to: sl2312_copy_to
-+//#endif
-+	.name = "SL2312 serial flash",
-+	.size = 4194304, //0x400000,
-+		//buswidth: 4,
-+	.bankwidth = 4,
-+	.phys =		 SL2312_FLASH_BASE,
-+#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
-+	//read32: sl2312_read32,
-+	//read8: sl2312_read8,
-+	.copy_from = sl2312_copy_from,
-+	//write8: sl2312_write8,
-+	//write32: sl2312_write32,
-+	.read = sl2312_read32,
-+	.write = sl2312_write32,
-+	.copy_to = sl2312_copy_to
-+#endif
-+};
-+
-+
-+
-+static struct mtd_partition sl2312_partitions[] = {
-+
-+
-+	///* boot code */
-+	//{ name: "bootloader", offset: 0x00000000, size: 0x20000, },
-+	///* kernel image */
-+	//{ name: "kerel image", offset: 0x000020000, size: 0x2E0000 },
-+	///* All else is writable (e.g. JFFS) */
-+	//{ name: "user data", offset: 0x00300000, size: 0x00100000, },
-+	/* boot code */
-+	{ .name = "bootloader", .offset = 0x00000000, .size = 0x20000, },
-+	/* kernel image */
-+	{ .name = "kerel image", .offset = 0x000020000, .size = 0xE0000 },
-+	/* All else is writable (e.g. JFFS) */
-+	{ .name = "user data", .offset = 0x00100000, .size = 0x00300000, },
-+
-+
-+};
-+
-+
-+
-+static int __init init_sl2312_maps(void)
-+{
-+	int nr_parts = 0;
-+	struct mtd_partition *parts;
-+
-+	serial_mtd = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
-+	if (!serial_mtd)
-+		return NULL;
-+
-+	memset(serial_mtd, 0, sizeof(struct mtd_info));
-+	//sl2312flash_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
-+    //sl2312_serial_map.map_priv_1 = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)FLASH_VBASE;
-+    sl2312_serial_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)ioremap(FLASH_START, SFLASH_SIZE);
-+    if (!sl2312_serial_map.virt) {
-+		printk(" failed to ioremap \n");
-+		return -EIO;
-+	}
-+	serial_mtd = do_map_probe("map_serial", &sl2312_serial_map);
-+	if (serial_mtd) {
-+		//serial_mtd->module = THIS_MODULE;
-+		serial_mtd->owner = THIS_MODULE;
-+
-+	}
-+
-+#ifdef CONFIG_MTD_REDBOOT_PARTS
-+	nr_parts = parse_redboot_partitions(serial_mtd, &parsed_parts);
-+	if (nr_parts > 0)
-+		printk(KERN_NOTICE "Found RedBoot partition table.\n");
-+	else if (nr_parts < 0)
-+		printk(KERN_NOTICE "Error looking for RedBoot partitions.\n");
-+#else
-+	parsed_parts = sl2312_partitions;
-+	parts = sl2312_partitions;
-+	nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
-+	nr_parts = sizeof(sl2312_partitions)/sizeof(*parsed_parts);
-+#endif /* CONFIG_MTD_REDBOOT_PARTS */
-+
-+	if (nr_parts > 0)
-+	    add_mtd_partitions(serial_mtd, parsed_parts, nr_parts);
-+	else
-+	    add_mtd_device(serial_mtd);
-+
-+	return 0;
-+}
-+
-+static void __exit cleanup_sl2312_maps(void)
-+{
-+	if (parsed_parts)
-+	    del_mtd_partitions(serial_mtd);
-+	else
-+	    del_mtd_device(serial_mtd);
-+
-+	map_destroy(serial_mtd);
-+
-+
-+}
-+
-+module_init(init_sl2312_maps);
-+module_exit(cleanup_sl2312_maps);
-+
-+
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Plus Chen ");
-+MODULE_DESCRIPTION("MTD map driver for Storlink Sword boards");
-+
---- /dev/null
-+++ b/drivers/mtd/maps/sl2312-flash-cfi.c
-@@ -0,0 +1,370 @@
-+/*======================================================================
-+
-+   This program is free software; you can redistribute it and/or modify
-+   it under the terms of the GNU General Public License as published by
-+   the Free Software Foundation; either version 2 of the License, or
-+   (at your option) any later version.
-+
-+   This program is distributed in the hope that it will be useful,
-+   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+   GNU General Public License for more details.
-+
-+   You should have received a copy of the GNU General Public License
-+   along with this program; if not, write to the Free Software
-+   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+======================================================================*/
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include "sl2312_flashmap.h"
-+
-+
-+//extern int parse_afs_partitions(struct mtd_info *, struct mtd_partition **);
-+
-+/* the base address of FLASH control register */
-+#define FLASH_CONTROL_BASE_ADDR	    (IO_ADDRESS(SL2312_FLASH_CTRL_BASE))
-+#define SL2312_GLOBAL_BASE_ADDR     (IO_ADDRESS(SL2312_GLOBAL_BASE))
-+
-+/* define read/write register utility */
-+#define FLASH_READ_REG(offset)			(__raw_readl(offset+FLASH_CONTROL_BASE_ADDR))
-+#define FLASH_WRITE_REG(offset,val) 	(__raw_writel(val,offset+FLASH_CONTROL_BASE_ADDR))
-+
-+/* the offset of FLASH control register */
-+enum EMAC_REGISTER {
-+	FLASH_ID     	= 0x0000,
-+	FLASH_STATUS 	= 0x0008,
-+	FLASH_TYPE   	= 0x000c,
-+	FLASH_ACCESS	= 0x0020,
-+	FLASH_ADDRESS   = 0x0024,
-+	FLASH_DATA		= 0x0028,
-+	FLASH_TIMING    = 0x002c,
-+};
-+
-+//#define FLASH_BASE	FLASH_CONTROL_BASE_ADDR
-+//#define FLASH_SIZE	0x00800000 //INTEGRATOR_FLASH_SIZE
-+
-+//#define FLASH_PART_SIZE 8388608
-+
-+static unsigned int flash_indirect_access = 0;
-+
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+static unsigned int chip_en = 0x00000000;
-+
-+void sl2312flash_enable_parallel_flash(void)
-+{
-+    unsigned int    reg_val;
-+
-+    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
-+    reg_val = reg_val & 0xfffffffd;
-+    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
-+    return;
-+}
-+
-+void sl2312flash_disable_parallel_flash(void)
-+{
-+    unsigned int    reg_val;
-+
-+    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
-+    reg_val = reg_val | 0x00000002;
-+    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
-+    return;
-+}
-+#endif
-+
-+
-+static struct map_info sl2312flash_map =
-+{
-+	name:		"SL2312 CFI Flash",
-+	size:       FLASH_SIZE,
-+	bankwidth:   2,
-+	//bankwidth:   1, //for 8 bits width
-+    phys:       SL2312_FLASH_BASE,
-+};
-+
-+static struct mtd_info *mtd;
-+#if 0
-+static struct mtd_partition sl2312_partitions[] = {
-+	/* boot code */
-+	{
-+		name: "bootloader",
-+		offset: 0x00000000,
-+		size: 0x20000,
-+//		mask_flags: MTD_WRITEABLE,
-+	},
-+	/* kernel image */
-+	{
-+		name: "kerel image",
-+		offset: 0x00020000,
-+		size: 0x2E0000
-+	},
-+	/* All else is writable (e.g. JFFS) */
-+	{
-+		name: "user data",
-+		offset: 0x00300000,
-+		size: 0x00100000,
-+	}
-+};
-+#endif
-+
-+
-+
-+static int __init sl2312flash_init(void)
-+{
-+	struct mtd_partition *parts;
-+	int nr_parts = 0;
-+	int ret;
-+#ifndef CONFIG_SL2312_SHARE_PIN
-+    unsigned int    reg_val;
-+#endif
-+
-+    printk("SL2312 MTD Driver Init.......\n");
-+
-+#ifndef CONFIG_SL2312_SHARE_PIN
-+	/* enable flash */
-+    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
-+    reg_val = reg_val & 0xfffffffd;
-+    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
-+#else
-+    sl2312flash_enable_parallel_flash();      /* enable Parallel FLASH */
-+#endif
-+    FLASH_WRITE_REG(FLASH_ACCESS,0x00004000); /* parallel flash direct access mode */
-+    ret = FLASH_READ_REG(FLASH_ACCESS);
-+    if (ret == 0x00004000)
-+    {
-+        flash_indirect_access = 0;  /* parallel flash direct access */
-+    }
-+    else
-+    {
-+        flash_indirect_access = 1;  /* parallel flash indirect access */
-+    }
-+
-+	/*
-+	 * Also, the CFI layer automatically works out what size
-+	 * of chips we have, and does the necessary identification
-+	 * for us automatically.
-+	 */
-+#ifdef CONFIG_GEMINI_IPI
-+	sl2312flash_map.virt = FLASH_VBASE;//(unsigned int *)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
-+#else
-+	sl2312flash_map.virt = (unsigned int *)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
-+#endif
-+	//printk("sl2312flash_map.virt  = %08x\n",(unsigned int)sl2312flash_map.virt);
-+
-+//	simple_map_init(&sl2312flash_map);
-+
-+	mtd = do_map_probe("cfi_probe", &sl2312flash_map);
-+	if (!mtd)
-+	{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+        sl2312flash_disable_parallel_flash();      /* disable Parallel FLASH */
-+#endif
-+		return -ENXIO;
-+	}
-+	mtd->owner = THIS_MODULE;
-+//    mtd->erase = flash_erase;
-+//    mtd->read = flash_read;
-+//    mtd->write = flash_write;
-+
-+    parts = sl2312_partitions;
-+	nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
-+	ret = add_mtd_partitions(mtd, parts, nr_parts);
-+	/*If we got an error, free all resources.*/
-+	if (ret < 0) {
-+		del_mtd_partitions(mtd);
-+		map_destroy(mtd);
-+	}
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+    sl2312flash_disable_parallel_flash();      /* disable Parallel FLASH */
-+#endif
-+    printk("SL2312 MTD Driver Init Success ......\n");
-+	return ret;
-+}
-+
-+static void __exit sl2312flash_exit(void)
-+{
-+	if (mtd) {
-+		del_mtd_partitions(mtd);
-+		map_destroy(mtd);
-+	}
-+
-+	if (sl2312flash_map.virt) {
-+	    iounmap((void *)sl2312flash_map.virt);
-+	    sl2312flash_map.virt = 0;
-+	}
-+}
-+
-+char chrtohex(char c)
-+{
-+  char val;
-+  if ((c >= '0') && (c <= '9'))
-+  {
-+    val = c - '0';
-+    return val;
-+  }
-+  else if ((c >= 'a') && (c <= 'f'))
-+  {
-+    val = 10 + (c - 'a');
-+    return val;
-+  }
-+  else if ((c >= 'A') && (c <= 'F'))
-+  {
-+    val = 10 + (c - 'A');
-+    return val;
-+  }
-+  printk("<1>Error number\n");
-+  return 0;
-+}
-+
-+
-+int get_vlaninfo(vlaninfo* vlan)
-+{
-+	vctl_mheader head;
-+	vctl_entry entry;
-+	struct mtd_info *mymtd=NULL;
-+	int i, j, loc = 0;
-+	char *payload=0, *tmp1, *tmp2, tmp3[9];
-+	size_t retlen;
-+
-+	#ifdef CONFIG_SL2312_SHARE_PIN
-+	sl2312flash_enable_parallel_flash();
-+	#endif
-+	for(i=0;iname: %s\n", mymtd->name);
-+		if(mymtd && !strcmp(mymtd->name,"VCTL"))
-+		{
-+			//      printk("%s\n", mymtd->name);
-+			break;
-+		}
-+	}
-+	if( i >= MAX_MTD_DEVICES)
-+	{
-+		printk("Can't find version control\n");
-+		#ifdef CONFIG_SL2312_SHARE_PIN
-+		sl2312flash_disable_parallel_flash();
-+		#endif
-+		return 0;
-+	}
-+
-+	if (!mymtd | !mymtd->read)
-+	{
-+		printk("<1>Can't read Version Configuration\n");
-+		#ifdef CONFIG_SL2312_SHARE_PIN
-+		sl2312flash_disable_parallel_flash();
-+		#endif
-+		return 0;
-+	}
-+
-+	mymtd->read(mymtd, 0, VCTL_HEAD_SIZE, &retlen, (u_char*)&head);
-+	//  printk("entry header: %c%c%c%c\n", head.header[0], head.header[1], head.header[2], head.header[3]);
-+	//  printk("entry number: %x\n", head.entry_num);
-+	if ( strncmp(head.header, "FLFM", 4) )
-+	{
-+		printk("VCTL is a erase block\n");
-+		#ifdef CONFIG_SL2312_SHARE_PIN
-+		sl2312flash_disable_parallel_flash();
-+		#endif
-+		return 0;
-+	}
-+	loc += retlen;
-+	for (i = 0; i < head.entry_num; i++)
-+	{
-+		mymtd->read(mymtd, loc, VCTL_ENTRY_LEN, &retlen, (u_char*)&entry);
-+		//    printk("type: %x\n", entry.type);
-+		//    printk("size: %x\n", entry.size);
-+		strncpy(tmp3, entry.header, 4);
-+		if (entry.type == VCT_VLAN)
-+		{
-+			for (j = 0; j < 6 ; j++)
-+			{
-+				vlan[0].mac[j] = 0;
-+				vlan[1].mac[j] = 0;
-+			}
-+			vlan[0].vlanid = 1;
-+			vlan[1].vlanid = 2;
-+			vlan[0].vlanmap = 0x7F;
-+			vlan[1].vlanmap = 0x80;
-+
-+			payload = (char *)kmalloc(entry.size - VCTL_ENTRY_LEN, GFP_KERNEL);
-+			loc += VCTL_ENTRY_LEN;
-+			mymtd->read(mymtd, loc, entry.size - VCTL_ENTRY_LEN, &retlen, payload);
-+			//      printk("%s\n", payload);
-+			tmp1 = strstr(payload, "MAC1:");
-+			tmp2 = strstr(payload, "MAC2:");
-+			if(!tmp1||!tmp2){
-+				kfree(payload);
-+				#ifdef CONFIG_SL2312_SHARE_PIN
-+				sl2312flash_disable_parallel_flash();
-+				#endif
-+				printk("Error VCTL format!!\n");
-+				return 0;
-+			}
-+			tmp1 += 7;
-+			tmp2 += 7;
-+
-+
-+			for (j = 0; j < 6; j++)
-+			{
-+				vlan[0].mac[j] = chrtohex(tmp1[2*j])*16 + chrtohex(tmp1[(2*j)+1]);
-+				vlan[1].mac[j] = chrtohex(tmp2[2*j])*16 + chrtohex(tmp2[(2*j)+1]);
-+			}
-+			tmp1 = strstr(payload, "ID1:");
-+			tmp2 = strstr(payload, "ID2:");
-+			tmp1 += 4;
-+			tmp2 += 4;
-+			vlan[0].vlanid = tmp1[0] - '0';
-+			vlan[1].vlanid = tmp2[0] - '0';
-+			tmp1 = strstr(payload, "MAP1:");
-+			tmp2 = strstr(payload, "MAP2:");
-+			tmp1 += 7;
-+			tmp2 += 7;
-+			vlan[0].vlanmap = chrtohex(tmp1[0]) * 16 + chrtohex(tmp1[1]);
-+			vlan[1].vlanmap = chrtohex(tmp2[0]) * 16 + chrtohex(tmp2[1]);
-+			//  printk("Vlan1 id:%x map:%02x mac:%x%x%x%x%x%x\n", vlan[0].vlanid, vlan[0].vlanmap, vlan[0].mac[0], vlan[0].mac[1], vlan[0].mac[2], vlan[0].mac[3], vlan[0].mac[4], vlan[0].mac[5]);
-+			//  printk("Vlan2 id:%x map:%02x mac:%x%x%x%x%x%x\n", vlan[1].vlanid, vlan[1].vlanmap, vlan[1].mac[0], vlan[1].mac[1], vlan[1].mac[2], vlan[1].mac[3], vlan[1].mac[4], vlan[1].mac[5]);
-+			break;
-+		}
-+		loc += entry.size;
-+	}
-+	if ( entry.type == VCT_VLAN )
-+	{
-+		#ifdef CONFIG_SL2312_SHARE_PIN
-+		sl2312flash_disable_parallel_flash();
-+		#endif
-+		kfree(payload);
-+		return 1;
-+	}
-+	if (i >= head.entry_num)
-+	printk("Can't find vlan information\n");
-+	#ifdef CONFIG_SL2312_SHARE_PIN
-+	sl2312flash_disable_parallel_flash();
-+	#endif
-+	return 0;
-+}
-+
-+EXPORT_SYMBOL(get_vlaninfo);
-+
-+
-+module_init(sl2312flash_init);
-+module_exit(sl2312flash_exit);
-+
-+MODULE_AUTHOR("Storlink Ltd");
-+MODULE_DESCRIPTION("CFI map driver");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/mtd/maps/sl2312-flash-m25p80.c
-@@ -0,0 +1,498 @@
-+/*
-+ * $Id: sl2312-flash-m25p80.c,v 1.2 2006/06/02 08:46:02 middle Exp $
-+ *
-+ * Flash and EPROM on Hitachi Solution Engine and similar boards.
-+ *
-+ * (C) 2001 Red Hat, Inc.
-+ *
-+ * GPL'd
-+ */
-+
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include  //add
-+#define  g_chipen     SERIAL_FLASH_CHIP0_EN   //ST
-+
-+//static int m25p80_page_program(__u32 address, __u8 data, __u32 schip_en);
-+static void m25p80_write_cmd(__u8 cmd, __u32 schip_en);
-+extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
-+
-+
-+static __u32 read_flash_ctrl_reg(__u32 ofs)
-+{
-+    __u32 *base;
-+
-+    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
-+    return __raw_readl(base);
-+}
-+
-+static void write_flash_ctrl_reg(__u32 ofs,__u32 data)
-+{
-+    __u32 *base;
-+
-+    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
-+    __raw_writel(data, base);
-+}
-+
-+static void m25p80_read(__u32 address, __u8 *data, __u32 schip_en)
-+{
-+      __u32 opcode,status;
-+      __u32 value;
-+
-+      //opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ;
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | M25P80_READ;
-+      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
-+
-+      	opcode|=g_chipen;
-+
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      status=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      while(status&0x80000000)
-+      {
-+          status=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+          flash_delay();
-+          schedule();
-+      }
-+
-+      value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      *data = value & 0xff;
-+}
-+
-+static int m25p80_page_program(__u32 address, __u8 *data, __u32 schip_en)
-+{
-+      __u32 opcode;
-+      __u32  status;
-+	  __u32 tmp;
-+	  int res = FLASH_ERR_OK;
-+	  //volatile FLASH_DATA_T* data_ptr = (volatile FLASH_DATA_T*) data;
-+	  opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
-+
-+      	      opcode|=g_chipen;
-+
-+          write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+          tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			while(tmp&0x80000000)
-+      			{
-+      			    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			    flash_delay();
-+      			    schedule();
-+      			}
-+          //middle delay_ms(130);
-+          status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+          if((status&0x02)==0x02)
-+      	  {
-+      	       //middle delay_ms(100);
-+               m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
-+          }
-+
-+
-+      m25p80_write_cmd(M25P80_WRITE_ENABLE, schip_en);
-+      ////middle delay_ms(10);
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | M25P80_PAGE_PROGRAM;
-+      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
-+      write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, *data);
-+
-+      //status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      //while(status!=data)
-+      //{
-+      //    status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      //    //middle delay_ms(10);
-+      //}
-+
-+      	opcode|=g_chipen;
-+
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			while(tmp&0x80000000)
-+      			{
-+      			    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			    flash_delay();
-+      			    schedule();
-+      			}
-+      //opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
-+
-+      	opcode|=g_chipen;
-+
-+
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			while(tmp&0x80000000)
-+      			{
-+      			    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			    flash_delay();
-+      			    schedule();
-+      			}
-+      status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      //while(status&0xfd)
-+      while(status&0x01)
-+      {
-+      	  //if((status&0x9c)!=0)
-+      	  //	printf("  m25p80_page_program	Protect Status = %x\n",status);
-+      	  write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      	  tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			while(tmp&0x80000000)
-+      			{
-+      			    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			    flash_delay();
-+      			    schedule();
-+      			}
-+          status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+          flash_delay();
-+          schedule();
-+          //middle delay_ms(50);
-+      }
-+      //printf("status = %x, data = %x\n",status,data);
-+      if((status&0x02)==0x02)
-+      {
-+	  //middle delay_ms(100);
-+          m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
-+      }
-+    //};//while (len > 0)
-+    return res;
-+}
-+
-+void m25p80_copy_from(struct map_info *map, void *buf, unsigned long ofs, ssize_t len)
-+{
-+//     __u32 size;
-+     __u8  *buffer;
-+     __u32 length;//i, j,
-+
-+	length = len;
-+     buffer = (__u8 *)buf;
-+     while(len)
-+     {
-+        m25p80_read(ofs, buffer, g_chipen);
-+        buffer++;
-+        ofs++;
-+        len --;
-+     }	;
-+
-+}
-+
-+__u32 m25p80_read32(struct map_info *map, unsigned long ofs)
-+{
-+
-+      return read_flash_ctrl_reg(ofs);
-+
-+
-+}
-+
-+void m25p80_write32(struct map_info *map, __u32 d, unsigned long ofs)
-+{
-+
-+      write_flash_ctrl_reg(ofs, d);
-+
-+}
-+
-+void m25p80_copy_to(struct map_info *map, unsigned long ofs, void *buf, ssize_t len)
-+{
-+     __u32 size, i, ret;
-+
-+     while(len > 0)
-+     {
-+        if(len >= M25P80_PAGE_SIZE)
-+			size = M25P80_PAGE_SIZE;
-+		else
-+			size = len;
-+
-+        for(i=0;im25p80_sector_erase");
-+	if(address >= FLASH_START)
-+		address-=FLASH_START;
-+
-+      m25p80_write_cmd(M25P80_WRITE_ENABLE, schip_en);
-+      //printf("\n     m25p80_sector_erase : after we-en");
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | M25P80_SECTOR_ERASE;
-+      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
-+      #ifdef MIDWAY_DIAG
-+      	opcode|=schip_en;
-+      #endif
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			while(tmp&0x80000000)
-+      			{
-+      			    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			    flash_delay();
-+      			    schedule();
-+      			}
-+
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
-+      #ifdef MIDWAY_DIAG
-+      	opcode|=schip_en;
-+      #endif
-+
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			while(tmp&0x80000000)
-+      			{
-+      			    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			    flash_delay();
-+      			    schedule();
-+      			}
-+      status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      //while(status&0xfd)
-+      while(status&0x01)
-+      {
-+      	  //if((status&0x9c)!=0)
-+      	  //	printf("  m25p80_sector_erase	Protect Status = %x\n",status);
-+      	  write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      	  tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			while(tmp&0x80000000)
-+      			{
-+      			    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			    flash_delay();
-+      			    schedule();
-+      			}
-+          status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+          flash_delay();
-+          schedule();
-+          //middle delay_ms(50);
-+      }
-+      if((status&0x02)==0x02)
-+      {
-+      	  //middle delay_ms(100);
-+          m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
-+      }
-+      //printf("\n<--m25p80_sector_erase");
-+      return res;
-+}
-+
-+static void m25p80_write_cmd(__u8 cmd, __u32 schip_en)
-+{
-+      __u32 opcode,tmp;
-+      __u32  status;
-+
-+
-+
-+
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE | cmd;
-+
-+      	opcode|=g_chipen;
-+
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      while(tmp&0x80000000)
-+      {
-+          tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+          flash_delay();
-+          schedule();
-+      }
-+      //////
-+      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
-+
-+      	opcode|=g_chipen;
-+
-+      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      while(tmp&0x80000000)
-+      {
-+          tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+          flash_delay();
-+          schedule();
-+      }
-+      //middle delay_ms(130);
-+      status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      //printf("\ncmd =%x  status = %x",cmd,status);
-+      if(cmd==M25P80_WRITE_ENABLE)
-+      {
-+      	//printf("\n**-->enable**  status = %x",status);
-+      	//middle delay_ms(100);
-+      	   while((status&0x03) != 2)
-+      	   {
-+      	   	//if((status&0x9c)!=0)
-+      	  	//    printf("	M25P80_WRITE_ENABLE   Protect Status = %x\n",status);
-+
-+      	   	  write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      	   	  tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			while(tmp&0x80000000)
-+      			{
-+      			    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			    //flash_delay();
-+      			}
-+      	       status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      	       //printf("\n**enable**  status = %x",status);
-+      	       flash_delay();
-+      	       schedule();
-+      	       //middle delay_ms(100);
-+      	   }
-+      }
-+      else if(cmd==M25P80_WRITE_DISABLE)
-+      {
-+      	   //while((status&0x03) == 2)
-+      	   //   printf("\n**disable**  status = %x",status);
-+      	   //middle delay_ms(100);
-+      	   while((status&0x03) != 0)
-+      	   {
-+	       //m25p80_write_status((status&0xfd),schip_en);
-+      	       write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      	       tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      		while(tmp&0x80000000)
-+      		{
-+      		    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      		    flash_delay();
-+      		    schedule();
-+      		}
-+      	       status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      	       //printf("\n**disable**  status = %x",status);
-+      	       flash_delay();
-+      	       schedule();
-+      	       //middle delay_ms(50);
-+      	   }
-+      }
-+      else
-+      {
-+      	   //while((status&0x01) !=0)
-+      	   while((status&0x01) !=0)
-+      	   {
-+      	   	  write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
-+      	   	  tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			while(tmp&0x80000000)
-+      			{
-+      			    tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
-+      			    flash_delay();
-+      			    schedule();
-+      			}
-+      	       status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
-+      	       flash_delay();
-+      	       schedule();
-+      	       //middle delay_ms(50);
-+      	   }
-+      }
-+      //////
-+
-+      //printf("\n<--  status = %x",status);
-+}
-+
-+static int __init init_sl2312_m25p80(void)
-+{
-+	int nr_parts = 0;
-+	struct mtd_partition *parts;
-+
-+	serial_mtd = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
-+	if (!serial_mtd)
-+		return NULL;
-+
-+	memset(serial_mtd, 0, sizeof(struct mtd_info));
-+	m25p80_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)ioremap(FLASH_START, SFLASH_SIZE);
-+    if (!m25p80_map.virt) {
-+		printk(" failed to ioremap \n");
-+		return -EIO;
-+	}
-+	serial_mtd = do_map_probe("map_serial", &m25p80_map);
-+	if (serial_mtd) {
-+		serial_mtd->owner = THIS_MODULE;
-+
-+	}
-+
-+#ifdef CONFIG_MTD_REDBOOT_PARTS
-+	nr_parts = parse_redboot_partitions(serial_mtd, &parsed_parts);
-+	if (nr_parts > 0)
-+		printk(KERN_NOTICE "Found RedBoot partition table.\n");
-+	else if (nr_parts < 0)
-+		printk(KERN_NOTICE "Error looking for RedBoot partitions.\n");
-+#else
-+	parsed_parts = m25p80_partitions;
-+	parts = m25p80_partitions;
-+	nr_parts = sizeof(m25p80_partitions)/sizeof(*parts);
-+	nr_parts = sizeof(m25p80_partitions)/sizeof(*parsed_parts);
-+#endif /* CONFIG_MTD_REDBOOT_PARTS */
-+
-+	if (nr_parts > 0)
-+	    add_mtd_partitions(serial_mtd, parsed_parts, nr_parts);
-+	else
-+	    add_mtd_device(serial_mtd);
-+
-+	return 0;
-+}
-+
-+static void __exit cleanup_sl2312_m25p80(void)
-+{
-+	if (parsed_parts)
-+	    del_mtd_partitions(serial_mtd);
-+	else
-+	    del_mtd_device(serial_mtd);
-+
-+	map_destroy(serial_mtd);
-+
-+
-+}
-+
-+module_init(init_sl2312_m25p80);
-+module_exit(cleanup_sl2312_m25p80);
-+
-+
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Plus Chen ");
-+MODULE_DESCRIPTION("MTD map driver for Storlink Sword boards");
-+
---- /dev/null
-+++ b/drivers/mtd/maps/sl2312_flashmap.h
-@@ -0,0 +1,21 @@
-+/*
-+ * Please note that the name are used in mkflash script. Therefore
-+ * don't change them.  If you want to add different partitions, you
-+ * will need to modify mkflash script as well so that the end image
-+ * is what you include here!
-+ *
-+ * Also, the 7th item is always the size, so please don't add extra
-+ * spaces in the name or other items.
-+ *
-+ *  - Alan
-+ */
-+
-+static struct mtd_partition sl2312_partitions[] = {
-+	{ name: "RedBoot", 	 offset: 0x00000000, size: 0x00020000, },
-+	{ name: "kernel", 	 offset: 0x00020000, size: 0x00100000, },
-+	{ name: "rootfs", 	 offset: 0x00120000, size: 0x00500000, },
-+	{ name: "rootfs_data", 	 offset: 0x00620000, size: 0x001A0000, },
-+	{ name: "VCTL", 	 offset: 0x007C0000, size: 0x00010000, },
-+	{ name: "cfg", 	 	 offset: 0x007D0000, size: 0x00020000, },
-+	{ name: "FIS directory", offset: 0x007F0000, size: 0x00010000, }
-+};
---- /dev/null
-+++ b/drivers/mtd/maps/sl2312_flashmap.h.16MB
-@@ -0,0 +1,21 @@
-+/*
-+ * Please note that the name are used in mkflash script. Therefore
-+ * don't change them.  If you want to add different partitions, you
-+ * will need to modify mkflash script as well so that the end image
-+ * is what you include here!
-+ *
-+ * Also, the 7th item is always the size, so please don't add extra
-+ * spaces in the name or other items.
-+ *
-+ *  - Alan
-+ */
-+
-+static struct mtd_partition sl2312_partitions[] = {
-+	{ name: "RedBoot",     	 offset: 0x00000000, size: 0x00020000, },
-+	{ name: "Kernel",      	 offset: 0x00020000, size: 0x00300000, },
-+	{ name: "Ramdisk",     	 offset: 0x00320000, size: 0x00600000, },
-+	{ name: "Application", 	 offset: 0x00920000, size: 0x00600000, },
-+	{ name: "VCTL", 	 offset: 0x00F20000, size: 0x00020000, },
-+	{ name: "CurConf", 	 offset: 0x00F40000, size: 0x000A0000, },
-+	{ name: "FIS directory", offset: 0x00FE0000, size: 0x00020000, }
-+};
---- /dev/null
-+++ b/drivers/mtd/maps/sl2312_flashmap.h.8MB
-@@ -0,0 +1,21 @@
-+/*
-+ * Please note that the name are used in mkflash script. Therefore
-+ * don't change them.  If you want to add different partitions, you
-+ * will need to modify mkflash script as well so that the end image
-+ * is what you include here!
-+ *
-+ * Also, the 7th item is always the size, so please don't add extra
-+ * spaces in the name or other items.
-+ *
-+ *  - Alan
-+ */
-+
-+static struct mtd_partition sl2312_partitions[] = {
-+	{ name: "RedBoot", 	 offset: 0x00000000, size: 0x00020000, },
-+	{ name: "Kernel", 	 offset: 0x00020000, size: 0x00200000, },
-+	{ name: "Ramdisk", 	 offset: 0x00220000, size: 0x00280000, },
-+	{ name: "Application", 	 offset: 0x004A0000, size: 0x00300000, },
-+	{ name: "VCTL", 	 offset: 0x007A0000, size: 0x00020000, },
-+	{ name: "CurConf", 	 offset: 0x007C0000, size: 0x00020000, },
-+	{ name: "FIS directory", offset: 0x007E0000, size: 0x00020000, }
-+};
---- a/drivers/mtd/mtdchar.c
-+++ b/drivers/mtd/mtdchar.c
-@@ -59,6 +59,77 @@
- 	enum mtd_file_modes mode;
- };
- 
-+/***********************************************************************
-+/*             Storlink SoC -- flash
-+/***********************************************************************/
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+unsigned int share_pin_flag=0;		// bit0:FLASH, bit1:UART, bit2:EMAC, bit3-4:IDE
-+unsigned int check_sleep_flag=0;	// bit0:FLASH, bit1:IDE
-+static spinlock_t sl2312_flash_lock = SPIN_LOCK_UNLOCKED;
-+EXPORT_SYMBOL(share_pin_flag);
-+int dbg=0;
-+DECLARE_WAIT_QUEUE_HEAD(wq);
-+extern struct wait_queue_head_t *flash_wait;
-+unsigned int flash_req=0;
-+void mtd_lock()
-+{
-+	struct task_struct *tsk = current;
-+	unsigned int value ;
-+	unsigned long flags;
-+	flash_req = 1;
-+	DECLARE_WAITQUEUE(wait, tsk);
-+	add_wait_queue(&wq, &wait);
-+	for(;;)
-+	{
-+		set_task_state(tsk, TASK_INTERRUPTIBLE);
-+		spin_lock_irqsave(&sl2312_flash_lock,flags);
-+		if((share_pin_flag&0x1E)){//||(check_sleep_flag&0x00000002)) {
-+			spin_unlock_irqrestore(&sl2312_flash_lock, flags);
-+			check_sleep_flag |= 0x00000001;
-+			if(dbg)
-+				printk("mtd yield %x %x\n",share_pin_flag,check_sleep_flag);
-+			wake_up_interruptible(&flash_wait);
-+			schedule();
-+		}
-+		else {
-+			check_sleep_flag &= ~0x01;
-+			share_pin_flag |= 0x00000001 ;			// set share pin flag
-+			spin_unlock_irqrestore(&sl2312_flash_lock, flags);
-+			value = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
-+			value = value & (~PFLASH_SHARE_BIT) ;
-+			writel(value,IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
-+			if(dbg)
-+				printk("mtd Go %x %x\n",share_pin_flag,check_sleep_flag);
-+			tsk->state = TASK_RUNNING;
-+			remove_wait_queue(&wq, &wait);
-+			return ;
-+		}
-+	}
-+}
-+
-+void mtd_unlock()
-+{
-+	unsigned int value ;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&sl2312_flash_lock,flags);		// Disable IRQ
-+	value = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
-+	value = value | PFLASH_SHARE_BIT ;				// Disable Flash PADs
-+	writel(value,IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
-+	share_pin_flag &= ~(0x00000001);			// clear share pin flag
-+	check_sleep_flag &= ~0x00000001;
-+	spin_unlock_irqrestore(&sl2312_flash_lock, flags);	// Restore IRQ
-+	if (check_sleep_flag & 0x00000002)
-+	{
-+		check_sleep_flag &= ~(0x00000002);
-+		wake_up_interruptible(&flash_wait);
-+	}
-+	DEBUG(MTD_DEBUG_LEVEL0, "Flash Unlock...\n");
-+	flash_req = 0;
-+}
-+#endif
-+/***********************************************************************/
-+
- static loff_t mtd_lseek (struct file *file, loff_t offset, int orig)
- {
- 	struct mtd_file_info *mfi = file->private_data;
-@@ -162,13 +233,21 @@
- 	int len;
- 	char *kbuf;
- 
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_lock();				// sl2312 share pin lock
-+#endif
-+
- 	DEBUG(MTD_DEBUG_LEVEL0,"MTD_read\n");
- 
- 	if (*ppos + count > mtd->size)
- 		count = mtd->size - *ppos;
- 
--	if (!count)
-+	if (!count){
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_unlock();				// sl2312 share pin lock
-+#endif
- 		return 0;
-+	}
- 
- 	/* FIXME: Use kiovec in 2.5 to lock down the user's buffers
- 	   and pass them directly to the MTD functions */
-@@ -178,8 +257,12 @@
- 	else
- 		kbuf=kmalloc(count, GFP_KERNEL);
- 
--	if (!kbuf)
-+	if (!kbuf) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_unlock();				// sl2312 share pin lock
-+#endif
- 		return -ENOMEM;
-+	}
- 
- 	while (count) {
- 
-@@ -224,6 +307,9 @@
- 			*ppos += retlen;
- 			if (copy_to_user(buf, kbuf, retlen)) {
- 				kfree(kbuf);
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+				mtd_unlock();				// sl2312 share pin lock
-+#endif
- 				return -EFAULT;
- 			}
- 			else
-@@ -235,13 +321,19 @@
- 				count = 0;
- 		}
- 		else {
--			kfree(kbuf);
-+	 		kfree(kbuf);
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return ret;
- 		}
- 
- 	}
- 
- 	kfree(kbuf);
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_unlock();				// sl2312 share pin lock
-+#endif
- 	return total_retlen;
- } /* mtd_read */
- 
-@@ -255,24 +347,40 @@
- 	int ret=0;
- 	int len;
- 
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_lock();				// sl2312 share pin lock
-+#endif
-+
- 	DEBUG(MTD_DEBUG_LEVEL0,"MTD_write\n");
- 
--	if (*ppos == mtd->size)
-+	if (*ppos == mtd->size){
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_unlock();				// sl2312 share pin lock
-+#endif
- 		return -ENOSPC;
-+	}
- 
- 	if (*ppos + count > mtd->size)
- 		count = mtd->size - *ppos;
- 
--	if (!count)
-+	if (!count){
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_unlock();				// sl2312 share pin lock
-+#endif
- 		return 0;
-+	}
- 
- 	if (count > MAX_KMALLOC_SIZE)
- 		kbuf=kmalloc(MAX_KMALLOC_SIZE, GFP_KERNEL);
- 	else
- 		kbuf=kmalloc(count, GFP_KERNEL);
- 
--	if (!kbuf)
-+	if (!kbuf) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+		mtd_unlock();				// sl2312 share pin lock
-+#endif
- 		return -ENOMEM;
-+	}
- 
- 	while (count) {
- 
-@@ -283,6 +391,9 @@
- 
- 		if (copy_from_user(kbuf, buf, len)) {
- 			kfree(kbuf);
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
- 		}
- 
-@@ -323,11 +434,17 @@
- 		}
- 		else {
- 			kfree(kbuf);
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return ret;
- 		}
- 	}
- 
- 	kfree(kbuf);
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_unlock();				// sl2312 share pin lock
-+#endif
- 	return total_retlen;
- } /* mtd_write */
- 
-@@ -381,36 +498,67 @@
- 	u_long size;
- 	struct mtd_info_user info;
- 
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_lock();				// sl2312 share pin lock
-+#endif
-+
- 	DEBUG(MTD_DEBUG_LEVEL0, "MTD_ioctl\n");
- 
- 	size = (cmd & IOCSIZE_MASK) >> IOCSIZE_SHIFT;
- 	if (cmd & IOC_IN) {
- 		if (!access_ok(VERIFY_READ, argp, size))
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 	}
- 	if (cmd & IOC_OUT) {
- 		if (!access_ok(VERIFY_WRITE, argp, size))
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 	}
- 
- 	switch (cmd) {
- 	case MEMGETREGIONCOUNT:
- 		if (copy_to_user(argp, &(mtd->numeraseregions), sizeof(int)))
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 		break;
- 
- 	case MEMGETREGIONINFO:
- 	{
- 		struct region_info_user ur;
- 
--		if (copy_from_user(&ur, argp, sizeof(struct region_info_user)))
-+		if (copy_from_user(&ur, argp, sizeof(struct region_info_user))) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 
--		if (ur.regionindex >= mtd->numeraseregions)
-+		if (ur.regionindex >= mtd->numeraseregions) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EINVAL;
-+		}
- 		if (copy_to_user(argp, &(mtd->eraseregions[ur.regionindex]),
--				sizeof(struct mtd_erase_region_info)))
-+				sizeof(struct mtd_erase_region_info))) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 		break;
- 	}
- 
-@@ -433,7 +581,12 @@
- 		struct erase_info *erase;
- 
- 		if(!(file->f_mode & 2))
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EPERM;
-+		}
- 
- 		erase=kzalloc(sizeof(struct erase_info),GFP_KERNEL);
- 		if (!erase)
-@@ -447,6 +600,9 @@
- 			if (copy_from_user(&erase->addr, argp,
- 				    sizeof(struct erase_info_user))) {
- 				kfree(erase);
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+				mtd_unlock();				// sl2312 share pin lock
-+#endif
- 				return -EFAULT;
- 			}
- 			erase->mtd = mtd;
-@@ -484,14 +640,26 @@
- 		struct mtd_oob_buf buf;
- 		struct mtd_oob_ops ops;
- 
--		if(!(file->f_mode & 2))
-+		if(!(file->f_mode & 2)) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EPERM;
-+		}
- 
--		if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf)))
-+		if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf))) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 
--		if (buf.length > 4096)
-+		if (buf.length > 4096) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EINVAL;
-+		}
- 
- 		if (!mtd->write_oob)
- 			ret = -EOPNOTSUPP;
-@@ -499,8 +667,12 @@
- 			ret = access_ok(VERIFY_READ, buf.ptr,
- 					buf.length) ? 0 : EFAULT;
- 
--		if (ret)
-+		if (ret) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return ret;
-+		}
- 
- 		ops.ooblen = buf.length;
- 		ops.ooboffs = buf.start & (mtd->oobsize - 1);
-@@ -536,19 +708,35 @@
- 		struct mtd_oob_buf buf;
- 		struct mtd_oob_ops ops;
- 
--		if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf)))
-+		if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf))) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 
--		if (buf.length > 4096)
-+		if (buf.length > 4096) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EINVAL;
-+		}
- 
--		if (!mtd->read_oob)
-+		if (!mtd->read_oob) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			ret = -EOPNOTSUPP;
-+		}
- 		else
- 			ret = access_ok(VERIFY_WRITE, buf.ptr,
- 					buf.length) ? 0 : -EFAULT;
--		if (ret)
-+		if (ret) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return ret;
-+		}
- 
- 		ops.ooblen = buf.length;
- 		ops.ooboffs = buf.start & (mtd->oobsize - 1);
-@@ -580,7 +768,12 @@
- 		struct erase_info_user info;
- 
- 		if (copy_from_user(&info, argp, sizeof(info)))
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 
- 		if (!mtd->lock)
- 			ret = -EOPNOTSUPP;
-@@ -594,7 +787,12 @@
- 		struct erase_info_user info;
- 
- 		if (copy_from_user(&info, argp, sizeof(info)))
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 
- 		if (!mtd->unlock)
- 			ret = -EOPNOTSUPP;
-@@ -629,11 +827,21 @@
- 		loff_t offs;
- 
- 		if (copy_from_user(&offs, argp, sizeof(loff_t)))
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 		if (!mtd->block_isbad)
- 			ret = -EOPNOTSUPP;
- 		else
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return mtd->block_isbad(mtd, offs);
-+		}
- 		break;
- 	}
- 
-@@ -642,11 +850,21 @@
- 		loff_t offs;
- 
- 		if (copy_from_user(&offs, argp, sizeof(loff_t)))
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 		if (!mtd->block_markbad)
- 			ret = -EOPNOTSUPP;
- 		else
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return mtd->block_markbad(mtd, offs);
-+		}
- 		break;
- 	}
- 
-@@ -654,8 +872,12 @@
- 	case OTPSELECT:
- 	{
- 		int mode;
--		if (copy_from_user(&mode, argp, sizeof(int)))
-+		if (copy_from_user(&mode, argp, sizeof(int))) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
-+		}
- 
- 		mfi->mode = MTD_MODE_NORMAL;
- 
-@@ -670,7 +892,12 @@
- 	{
- 		struct otp_info *buf = kmalloc(4096, GFP_KERNEL);
- 		if (!buf)
-+		{
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -ENOMEM;
-+		}
- 		ret = -EOPNOTSUPP;
- 		switch (mfi->mode) {
- 		case MTD_MODE_OTP_FACTORY:
-@@ -701,12 +928,24 @@
- 	{
- 		struct otp_info info;
- 
--		if (mfi->mode != MTD_MODE_OTP_USER)
-+		if (mfi->mode != MTD_MODE_OTP_USER) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EINVAL;
--		if (copy_from_user(&info, argp, sizeof(info)))
-+		}
-+		if (copy_from_user(&info, argp, sizeof(info))) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EFAULT;
--		if (!mtd->lock_user_prot_reg)
-+		}
-+		if (!mtd->lock_user_prot_reg) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+			mtd_unlock();				// sl2312 share pin lock
-+#endif
- 			return -EOPNOTSUPP;
-+		}
- 		ret = mtd->lock_user_prot_reg(mtd, info.start, info.length);
- 		break;
- 	}
-@@ -742,8 +981,12 @@
- 			break;
- 
- 		case MTD_MODE_RAW:
--			if (!mtd->read_oob || !mtd->write_oob)
-+			if (!mtd->read_oob || !mtd->write_oob) {
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+				mtd_unlock();				// sl2312 share pin lock
-+#endif
- 				return -EOPNOTSUPP;
-+			}
- 			mfi->mode = arg;
- 
- 		case MTD_MODE_NORMAL:
-@@ -766,6 +1009,10 @@
- 		ret = -ENOTTY;
- 	}
- 
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+	mtd_unlock();				// sl2312 share pin lock
-+#endif
-+
- 	return ret;
- } /* memory_ioctl */
- 
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -44,6 +44,13 @@
- 	  This enables the driver for the autronix autcpu12 board to
- 	  access the SmartMediaCard.
- 
-+config MTD_NAND_SL2312
-+	tristate "NAND Flash device on Storlink board"
-+	depends on ARM && MTD_NAND && ARCH_SL2312
-+	help
-+	  This enables the driver for the Storlink board to
-+	  access the nand device.
-+
- config MTD_NAND_EDB7312
- 	tristate "Support for Cirrus Logic EBD7312 evaluation board"
- 	depends on ARCH_EDB7312
---- /dev/null
-+++ b/drivers/mtd/nand/sl2312-flash-nand.c
-@@ -0,0 +1,2287 @@
-+/*
-+ *  drivers/mtd/sl2312.c
-+ *
-+ * $Id: sl2312-flash-nand.c,v 1.5 2006/06/15 07:02:29 middle Exp $
-+ *
-+ * Copyright (C) 2001 Toshiba Corporation
-+ *
-+ * 2003 (c) MontaVista Software, Inc. This file is licensed under
-+ * the terms of the GNU General Public License version 2. This program
-+ * is licensed "as is" without any warranty of any kind, whether express
-+ * or implied.
-+ *
-+ */
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include "sl2312-flash-nand.h"
-+
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+
-+/*
-+ * NAND low-level MTD interface functions
-+ */
-+static void sl2312_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
-+static void sl2312_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
-+static int sl2312_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
-+
-+static int sl2312_nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
-+static int sl2312_nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
-+static int sl2312_nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
-+static int sl2312_nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf);
-+static int sl2312_nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
-+			   size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
-+static int sl2312_nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf);
-+static int sl2312_nand_writev (struct mtd_info *mtd, const struct kvec *vecs,
-+			unsigned long count, loff_t to, size_t * retlen);
-+static int sl2312_nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs,
-+			unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
-+static int sl2312_nand_erase (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
-+static void sl2312_nand_sync (struct mtd_info *mtd);
-+static int sl2312_nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf,  struct nand_oobinfo *oobsel);
-+static int sl2312_nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt);
-+static int sl2312_nand_erase_block(struct mtd_info *mtd, int page);
-+
-+/*
-+ * MTD structure for sl2312 NDFMC
-+ */
-+static struct mtd_info *sl2312_mtd = NULL;
-+static int nand_page=0,nand_col=0;
-+
-+/* Define default oob placement schemes for large and small page devices */
-+static struct nand_oobinfo nand_oob_8 = {
-+	.useecc = MTD_NANDECC_AUTOPLACE,
-+	.eccbytes = 3,
-+	.eccpos = {0, 1, 2},
-+	.oobfree = { {3, 2}, {6, 2} }
-+};
-+
-+static struct nand_oobinfo nand_oob_16 = {
-+	.useecc = MTD_NANDECC_AUTOPLACE,
-+	.eccbytes = 6,
-+	.eccpos = {0, 1, 2, 3, 6, 7},
-+	.oobfree = { {8, 8} }
-+};
-+
-+static struct nand_oobinfo nand_oob_64 = {
-+	.useecc = MTD_NANDECC_AUTOPLACE,
-+	.eccbytes = 24,
-+	.eccpos = {
-+		40, 41, 42, 43, 44, 45, 46, 47,
-+		48, 49, 50, 51, 52, 53, 54, 55,
-+		56, 57, 58, 59, 60, 61, 62, 63},
-+	.oobfree = { {2, 38} }
-+};
-+
-+
-+/*
-+ * Define partitions for flash device
-+ */
-+/* the base address of FLASH control register */
-+#define FLASH_CONTROL_BASE_ADDR	    (IO_ADDRESS(SL2312_FLASH_CTRL_BASE))
-+#define SL2312_GLOBAL_BASE_ADDR     (IO_ADDRESS(SL2312_GLOBAL_BASE))
-+//#define SL2312_FLASH_BASE_ADDR      (IO_ADDRESS(SL2312_FLASH_BASE))
-+#define SL2312_FLASH_BASE_ADDR       FLASH_VADDR(SL2312_FLASH_BASE)
-+static unsigned int CHIP_EN;
-+/* define read/write register utility */
-+//#define FLASH_READ_REG(offset)			(__raw_readl(offset+FLASH_CONTROL_BASE_ADDR))
-+//#define FLASH_WRITE_REG(offset,val) 	(__raw_writel(val,offset+FLASH_CONTROL_BASE_ADDR))
-+//#define FLASH_READ_DATA(offset)			(__raw_readb(offset+SL2312_FLASH_BASE_ADDR))
-+//#define FLASH_WRITE_DATA(offset,val) 	(__raw_writeb(val,offset+SL2312_FLASH_BASE_ADDR))
-+
-+unsigned int FLASH_READ_REG(unsigned int addr)
-+{
-+    unsigned int *base;
-+    unsigned int data;
-+
-+    base = (unsigned int *)(FLASH_CONTROL_BASE_ADDR + addr);
-+    data = *base;
-+    return (data);
-+}
-+
-+void FLASH_WRITE_REG(unsigned int addr,unsigned int data)
-+{
-+    unsigned int *base;
-+
-+    base = (unsigned int *)(FLASH_CONTROL_BASE_ADDR + addr);
-+    *base = data;
-+    return;
-+}
-+
-+unsigned int FLASH_READ_DATA(unsigned int addr)
-+{
-+    unsigned char *base;
-+    unsigned int data;
-+
-+    base = (unsigned char *)(SL2312_FLASH_BASE_ADDR + addr);
-+    data = *base;
-+    return (data);
-+}
-+
-+void FLASH_WRITE_DATA(unsigned int addr,unsigned int data)
-+{
-+    unsigned char *base;
-+
-+    base = (unsigned char *)(SL2312_FLASH_BASE_ADDR + addr);
-+    *base = data;
-+    return;
-+}
-+
-+/* the offset of FLASH control register */
-+enum NFLASH_REGISTER {
-+	NFLASH_ID     			= 0x0000,
-+	NFLASH_STATUS 			= 0x0008,
-+	NFLASH_TYPE   			= 0x000c,
-+	NFLASH_ACCESS			= 0x0030,
-+	NFLASH_COUNT			= 0x0034,
-+	NFLASH_CMD_ADDR 		= 0x0038,
-+	NFLASH_ADDRESS			= 0x003C,
-+	NFLASH_DATA				= 0x0040,
-+	NFLASH_TIMING   		= 0x004C,
-+	NFLASH_ECC_STATUS		= 0x0050,
-+	NFLASH_ECC_CONTROL		= 0x0054,
-+	NFLASH_ECC_OOB			= 0x005c,
-+	NFLASH_ECC_CODE_GEN0	= 0x0060,
-+	NFLASH_ECC_CODE_GEN1	= 0x0064,
-+	NFLASH_ECC_CODE_GEN2	= 0x0068,
-+	NFLASH_ECC_CODE_GEN3	= 0x006C,
-+	NFLASH_FIFO_CONTROL		= 0x0070,
-+	NFLASH_FIFO_STATUS		= 0x0074,
-+	NFLASH_FIFO_ADDRESS		= 0x0078,
-+	NFLASH_FIFO_DATA		= 0x007c,
-+};
-+
-+
-+
-+//#define FLASH_BASE	FLASH_CONTROL_BASE_ADDR
-+//#define FLASH_SIZE	0x00800000 //INTEGRATOR_FLASH_SIZE
-+
-+//#define FLASH_PART_SIZE 8388608
-+
-+//static unsigned int flash_indirect_access = 0;
-+
-+
-+#ifdef CONFIG_SL2312_SHARE_PIN
-+void sl2312flash_enable_nand_flash(void)
-+{
-+    unsigned int    reg_val;
-+
-+    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
-+    reg_val = reg_val & 0xfffffffb;
-+    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
-+    return;
-+}
-+
-+void sl2312flash_disable_nand_flash(void)
-+{
-+    unsigned int    reg_val;
-+
-+    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
-+    reg_val = reg_val | 0x00000004;
-+    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
-+    return;
-+}
-+#endif
-+
-+extern struct nand_oobinfo jffs2_oobinfo;
-+/*
-+ * Define partitions for flash devices
-+ */
-+
-+static struct mtd_partition sl2312_partitions[] = {
-+	{ name: "RedBoot", offset: 0x00000000, size: 0x0020000, },
-+	{ name: "Kernel", offset: 0x00020000, size: 0x00200000, },
-+	{ name: "Ramdisk", offset: 0x00220000, size: 0x00280000, },
-+	{ name: "Application", offset: 0x004A0000, size: 0x00320000, },
-+	{ name: "VCTL", offset: 0x007C0000, size: 0x20000, },
-+	{ name: "CurConf", offset: 0x007E0000, size: 0x20000, },
-+	{ name: "FIS directory", offset: 0x007e0000, size: 0x00020000, }
-+
-+};
-+
-+
-+/*
-+ *	hardware specific access to control-lines
-+*/
-+static void sl2312_hwcontrol(struct mtd_info *mtd, int cmd)
-+{
-+
-+	return ;
-+}
-+
-+static int sl2312_nand_scan_bbt(struct mtd_info *mtd)
-+{
-+	return 0;
-+}
-+
-+/**
-+ * nand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
-+ * @mtd:	MTD device structure
-+ * @ofs:	offset relative to mtd start
-+ */
-+static int sl2312_nand_block_isbad (struct mtd_info *mtd, loff_t ofs)
-+{
-+	/* Check for invalid offset */
-+	if (ofs > mtd->size)
-+		return -EINVAL;
-+
-+	return sl2312_nand_block_checkbad (mtd, ofs, 1, 0);
-+}
-+
-+/**
-+ * nand_block_checkbad - [GENERIC] Check if a block is marked bad
-+ * @mtd:	MTD device structure
-+ * @ofs:	offset from device start
-+ * @getchip:	0, if the chip is already selected
-+ * @allowbbt:	1, if its allowed to access the bbt area
-+ *
-+ * Check, if the block is bad. Either by reading the bad block table or
-+ * calling of the scan function.
-+ */
-+
-+static int sl2312_nand_erase_block(struct mtd_info *mtd, int page)
-+{
-+	int opcode;
-+	/* Send commands to erase a page */
-+		FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
-+
-+		if(mtd->oobblock > 528)
-+		    FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff21);  // 3 address & 2 command
-+		else
-+		    FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff11);  // 2 address & 2 command
-+
-+		FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x0000d060); // write read id command
-+		FLASH_WRITE_REG(NFLASH_ADDRESS, page); //write address 0x00
-+
-+
-+
-+		/* read maker code */
-+		opcode = 0x80003000|DWIDTH|CHIP_EN; //set start bit & 8bits write command
-+		FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
-+
-+		while(opcode&0x80000000) //polling flash access 31b
-+      	{
-+           opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+           //sl2312_flash_delay();
-+           schedule();
-+           //cond_resched();
-+      	}
-+}
-+
-+void sl2312_flash_delay(void)
-+{
-+      int i;
-+
-+      for(i=0; i<50; i++)
-+           i=i;
-+}
-+
-+static int sl2312_nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt)
-+{
-+	struct nand_chip *this = mtd->priv;
-+
-+	if (!this->bbt)
-+		return this->block_bad(mtd, ofs, getchip);
-+
-+	/* Return info from the table */
-+	return nand_isbad_bbt (mtd, ofs, allowbbt);
-+}
-+
-+/**
-+ * nand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
-+ * @mtd:	MTD device structure
-+ * @ofs:	offset relative to mtd start
-+ */
-+static int sl2312_nand_block_markbad (struct mtd_info *mtd, loff_t ofs)
-+{
-+	struct nand_chip *this = mtd->priv;
-+	int ret;
-+
-+        if ((ret = sl2312_nand_block_isbad(mtd, ofs))) {
-+        	/* If it was bad already, return success and do nothing. */
-+		if (ret > 0)
-+			return 0;
-+        	return ret;
-+        }
-+
-+	return this->block_markbad(mtd, ofs);
-+}
-+
-+/*
-+ *	Get chip for selected access
-+ */
-+static inline void sl2312_nand_get_chip (struct nand_chip *this, struct mtd_info *mtd, int new_state, int *erase_state)
-+{
-+
-+	DECLARE_WAITQUEUE (wait, current);
-+
-+	/*
-+	 * Grab the lock and see if the device is available
-+	 * For erasing, we keep the spinlock until the
-+	 * erase command is written.
-+	*/
-+retry:
-+	spin_lock_bh (&this->chip_lock);
-+
-+	if (this->state == FL_READY) {
-+		this->state = new_state;
-+		if (new_state != FL_ERASING)
-+			spin_unlock_bh (&this->chip_lock);
-+		return;
-+	}
-+
-+	if (this->state == FL_ERASING) {
-+		if (new_state != FL_ERASING) {
-+			this->state = new_state;
-+			spin_unlock_bh (&this->chip_lock);
-+			this->select_chip(mtd, 0);	/* select in any case */
-+			this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
-+			return;
-+		}
-+	}
-+
-+	set_current_state (TASK_UNINTERRUPTIBLE);
-+	add_wait_queue (&this->wq, &wait);
-+	spin_unlock_bh (&this->chip_lock);
-+	schedule ();
-+	remove_wait_queue (&this->wq, &wait);
-+	goto retry;
-+}
-+
-+/*
-+*	read device ready pin
-+*/
-+static int sl2312_device_ready(struct mtd_info *mtd)
-+{
-+	int ready;
-+
-+	FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
-+	FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000070); //set only command no address and two data
-+
-+	FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000070); //write read status command
-+
-+
-+	ready = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
-+	FLASH_WRITE_REG(NFLASH_ACCESS, ready);
-+
-+	while(ready&0x80000000) //polling flash access 31b
-+    {
-+        ready=FLASH_READ_REG(NFLASH_ACCESS);
-+        //sl2312_flash_delay();
-+		schedule();
-+    }
-+    FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
-+      	ready=FLASH_READ_REG(NFLASH_DATA)&0xff;
-+	return ready;
-+}
-+void sl2312_enable_hwecc(struct mtd_info *mtd, int mode)
-+{
-+	/* reset first */
-+	FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
-+
-+}
-+
-+
-+void sl2312_device_setup(void)
-+{
-+
-+}
-+static u_char sl2312_nand_read_byte(struct mtd_info *mtd)
-+{
-+
-+        unsigned int    data=0, page=0, col=0, tmp, i;
-+
-+        printk ("**************************sl2312_nand_read_byte !! \n");
-+        //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
-+        //col  = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
-+        page = nand_page;
-+        col  = nand_col;
-+        for(i=0;i<(mtd->oobblock+mtd->oobsize);i++)
-+        {
-+        	if(i==col)
-+				data = FLASH_READ_DATA(page*mtd->oobblock +i);
-+			else
-+				tmp = FLASH_READ_DATA(page*mtd->oobblock +i);
-+        }
-+        return data&0xff;
-+}
-+
-+static void sl2312_nand_write_byte(struct mtd_info *mtd, u_char byte)
-+{
-+        //struct nand_chip *this = mtd->priv;
-+        unsigned int    page=0, col=0, i;
-+        u_char *databuf,oobbuf[mtd->oobsize];
-+        size_t  retlen;
-+        retlen=0;
-+		printk ("********************sl2312_nand_write_byte !! \n");
-+		page = nand_page;
-+        col  = nand_col;
-+		databuf = kmalloc (mtd->oobsize+mtd->oobblock,GFP_KERNEL);
-+
-+		if (!databuf) {
-+			printk ("sl2312_nand_write_byte : Unable to allocate SL2312 NAND MTD device structure.\n");
-+
-+		}
-+
-+		 for(i=0;i<(mtd->oobblock+mtd->oobsize);i++)
-+           	databuf[i] = FLASH_READ_DATA(page*mtd->oobblock +i);
-+
-+        databuf[col] = byte;
-+        sl2312_nand_write_ecc (mtd, page, mtd->oobblock, &retlen, databuf, oobbuf, NULL);
-+
-+}
-+
-+static void sl2312_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-+{
-+	int i, page=0,col=0;
-+	struct nand_chip *this = mtd->priv;
-+	u_char *databuf, *oobbuf;
-+        size_t  retlen;
-+        retlen=0;
-+
-+
-+		printk ("***********************sl2312_nand_write_buf !! \n");
-+		databuf = &(this->data_buf[0]);
-+		oobbuf = &(this->data_buf[mtd->oobblock]);
-+		for (i = 0; i < mtd->oobsize; i++)
-+			oobbuf[i] = 0xff;
-+
-+	if(len < mtd->oobblock)
-+	{
-+		//addr = FLASH_READ_REG(NFLASH_ADDRESS);
-+		//page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
-+		//col  = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
-+		page = nand_page;
-+        col  = nand_col;
-+
-+		sl2312_nand_read_ecc (mtd, page, mtd->oobblock , &retlen, databuf, oobbuf, NULL);
-+
-+        for(i=col;ioobblock, &retlen, databuf, oobbuf, NULL);
-+
-+	}
-+
-+}
-+
-+static void sl2312_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-+{
-+	int i, page=0,col=0,addr=0,tmp=0;
-+	//struct nand_chip *this = mtd->priv;
-+	printk ("********************sl2312_nand_read_buf !! \n");
-+	if(len < mtd->oobblock)
-+	{
-+		//addr = FLASH_READ_REG(NFLASH_ADDRESS);
-+		//page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
-+		//col  = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
-+		page = nand_page;
-+        col  = nand_col;
-+		for (i=col; i<((mtd->oobblock+mtd->oobsize)-col); i++)
-+		{
-+			if(ipriv;
-+	u_char *datatmp, *oobtmp;
-+	size_t  retlen;
-+	retlen=0;
-+
-+	datatmp = kmalloc (mtd->oobblock,GFP_KERNEL);
-+	oobtmp = kmalloc (mtd->oobsize,GFP_KERNEL);
-+
-+	if ((!datatmp)||(!oobtmp)) {
-+		printk ("sl2312_nand_verify_buf : Unable to allocate SL2312 NAND MTD device structure.\n");
-+
-+	}
-+	//page = nand_page;
-+	for(i=0;ioobblock;i++)
-+		datatmp[i] = FLASH_READ_DATA(nand_page*mtd->oobblock +i);
-+	/* read oobdata */
-+	for (i = 0; i <  mtd->oobsize; i++)
-+		oobtmp[i] = FLASH_READ_DATA(nand_page*mtd->oobblock + mtd->oobblock + i);
-+
-+	if(len==mtd->oobblock)
-+	{
-+		for (i=0; i page: %x, byte: %x \n",nand_page,i);
-+				return i;
-+			}
-+		}
-+	}
-+	else if(len == mtd->oobsize)
-+	{
-+		for (i=0; i page: %x, byte: %x \n",nand_page,i);
-+				return i;
-+			}
-+		}
-+	}
-+	else
-+	{
-+		printk (KERN_WARNING "sl2312_nand_verify_buf : verify length not match 0x%08x\n", len);
-+		kfree(datatmp);
-+		kfree(oobtmp);
-+		return -1;
-+	}
-+
-+	kfree(datatmp);
-+	kfree(oobtmp);
-+	return 0;
-+}
-+
-+/*
-+ * Send command to NAND device
-+ */
-+static void sl2312_nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
-+{
-+	register struct nand_chip *this = mtd->priv;
-+	int opcode;
-+
-+
-+	/*
-+	 * program and erase have their own busy handlers
-+	 * status and sequential in needs no delay
-+	*/
-+	switch (command) {
-+
-+	case NAND_CMD_PAGEPROG:
-+	case NAND_CMD_ERASE1:
-+	case NAND_CMD_ERASE2:
-+	case NAND_CMD_SEQIN:
-+	case NAND_CMD_STATUS:
-+	case NAND_CMD_READ0:
-+
-+		/*
-+		 * Write out the command to the device.
-+		 */
-+		if (column != -1 || page_addr != -1) {
-+
-+			/* Serially input address */
-+			if (column != -1)
-+				//FLASH_WRITE_REG(NFLASH_ADDRESS,column);
-+				nand_col=column;
-+
-+			opcode = FLASH_READ_REG(NFLASH_ADDRESS);
-+
-+			if (page_addr != -1)
-+				//FLASH_WRITE_REG(NFLASH_ADDRESS,opcode|(page_addr<<8));
-+				nand_page = page_addr;
-+
-+		}
-+		return;
-+
-+	case NAND_CMD_RESET:
-+		if (this->dev_ready)
-+			break;
-+		FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
-+		FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff70); //set only command and no other data
-+		FLASH_WRITE_REG(NFLASH_CMD_ADDR, NAND_CMD_RESET); //write reset command
-+
-+		opcode = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
-+		FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
-+
-+		while(opcode&0x80000000) //polling flash access 31b
-+      	{
-+           opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+           //sl2312_flash_delay();
-+           schedule();
-+      	}
-+		while ( !(sl2312_device_ready(mtd) & 0x40));
-+		{
-+			FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
-+			//sl2312_flash_delay();
-+			schedule();
-+			return;
-+		}
-+	/* This applies to read commands */
-+	default:
-+		/*
-+		 * If we don't have access to the busy pin, we apply the given
-+		 * command delay
-+		*/
-+		if (!this->dev_ready) {
-+			udelay (this->chip_delay);
-+			FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
-+			return;
-+		}
-+	}
-+
-+	/* wait until command is processed */
-+	while (!this->dev_ready(mtd));
-+
-+}
-+/*Add function*/
-+static void nand_read_id(int chip_no, unsigned char *id)
-+{
-+	unsigned int opcode, i;
-+
-+	if(chip_no==0)
-+		CHIP_EN = NFLASH_CHIP0_EN;
-+	else
-+		CHIP_EN = NFLASH_CHIP1_EN;
-+
-+	opcode = FLASH_READ_REG(NFLASH_TYPE);
-+
-+	FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
-+	if((opcode&0x00000300)<=0x00000100)
-+	    FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000100); //set only command & address and two data
-+	else
-+	    FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000300); //set only command & address and 4 data
-+
-+	FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000090); //write read id command
-+	FLASH_WRITE_REG(NFLASH_ADDRESS, 0x00000000); //write address 0x00
-+
-+	/* read maker code */
-+	opcode = 0x80002000|DWIDTH|CHIP_EN;//|chip0_en; //set start bit & 8bits read command
-+	FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
-+	opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+		while(opcode&0x80000000) //polling flash access 31b
-+      	{
-+           opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+           //sl2312_flash_delay();
-+           schedule();
-+      	}
-+
-+    opcode = FLASH_READ_REG(NFLASH_DATA);
-+    if(DWIDTH==NFLASH_WiDTH16)
-+    {
-+      		id[0] = opcode&0xff;
-+      		id[1] = (opcode&0xff00)>>8;
-+    }
-+    else
-+    {
-+    	    id[0] = opcode&0xff;
-+    	    opcode = 0x80002000|DWIDTH|CHIP_EN;//|chip0_en; //set start bit & 8bits read command
-+			FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
-+			opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+			while(opcode&0x80000000) //polling flash access 31b
-+    	  	{
-+    	       opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+    	       //sl2312_flash_delay();
-+    	       schedule();
-+    	  	}
-+    		opcode = FLASH_READ_REG(NFLASH_DATA);
-+      		id[1] = (opcode&0xff00)>>8;
-+
-+      		opcode=FLASH_READ_REG(NFLASH_TYPE);
-+      		if((opcode&0x300)>0x100)
-+      		{
-+      		    for(i=0;i<2;i++)
-+      		    {
-+      				//data cycle 3 & 4 ->not use
-+      				opcode = 0x80002000|DWIDTH|CHIP_EN;//set start bit & 8bits read command
-+					FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
-+					opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+      				while(opcode&0x80000000) //polling flash access 31b
-+      				{
-+        			   opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+        			   //sl2312_flash_delay();
-+        			   schedule();
-+      				}
-+
-+      				opcode=FLASH_READ_REG(NFLASH_DATA);
-+      				id[2+i] = (opcode&(0xff0000<>(8*(2+i));
-+      		    }
-+      		}
-+    }
-+    FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
-+}
-+
-+/*
-+ * NAND erase a block
-+ */
-+static int sl2312_nand_erase (struct mtd_info *mtd, struct erase_info *instr, int allowbbt)
-+{
-+	int page, len, status, pages_per_block, ret, chipnr;
-+	struct nand_chip *this = mtd->priv;
-+
-+	DEBUG (MTD_DEBUG_LEVEL3,
-+	       "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
-+
-+	/* Start address must align on block boundary */
-+	if (instr->addr & ((1 << this->phys_erase_shift) - 1)) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
-+		return -EINVAL;
-+	}
-+
-+	/* Length must align on block boundary */
-+	if (instr->len & ((1 << this->phys_erase_shift) - 1)) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n");
-+		return -EINVAL;
-+	}
-+
-+	/* Do not allow erase past end of device */
-+	if ((instr->len + instr->addr) > mtd->size) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n");
-+		return -EINVAL;
-+	}
-+
-+	instr->fail_addr = 0xffffffff;
-+
-+	/* Grab the lock and see if the device is available */
-+	sl2312_nand_get_chip (this, mtd, FL_ERASING, NULL);
-+
-+	/* Shift to get first page */
-+	page = (int) (instr->addr >> this->page_shift);
-+	chipnr = (int) (instr->addr >> this->chip_shift);
-+
-+	/* Calculate pages in each block */
-+	pages_per_block = 1 << (this->phys_erase_shift - this->page_shift);
-+
-+	/* Select the NAND device */
-+	//this->select_chip(mtd, chipnr);
-+	this->select_chip(mtd, 0);
-+
-+	/* Check the WP bit */
-+	/* Check, if it is write protected */
-+	status = sl2312_device_ready(mtd);
-+	if (!(status & 0x80)) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n");
-+		instr->state = MTD_ERASE_FAILED;
-+		goto erase_exit;
-+	}
-+
-+	/* Loop through the pages */
-+	len = instr->len;
-+
-+	instr->state = MTD_ERASING;
-+
-+	while (len) {
-+		/* Check if we have a bad block, we do not erase bad blocks ! */
-+		if (this->block_bad(mtd, ((loff_t) page) << this->page_shift, 0)) {
-+			printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page);
-+			//instr->state = MTD_ERASE_FAILED;
-+			//goto erase_exit;
-+		}
-+
-+		/* Invalidate the page cache, if we erase the block which contains
-+		   the current cached page */
-+		if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block))
-+			this->pagebuf = -1;
-+		/////////
-+
-+		///* Send commands to erase a page */
-+		//FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
-+	    //
-+		//if(mtd->oobblock > 528)
-+		//    FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff21);  // 3 address & 2 command
-+		//else
-+		//    FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff11);  // 2 address & 2 command
-+		//
-+		//FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x0000d060); // write read id command
-+		//FLASH_WRITE_REG(NFLASH_ADDRESS, page); //write address 0x00
-+		//
-+		//
-+		//
-+		///* read maker code */
-+		//opcode = 0x80003000|DWIDTH|CHIP_EN; //set start bit & 8bits write command
-+		//FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
-+		//
-+		//while(opcode&0x80000000) //polling flash access 31b
-+      	//{
-+        //   opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+        //   //sl2312_flash_delay();
-+        //   schedule();
-+        //   //cond_resched();
-+      	//}
-+      	sl2312_nand_erase_block(mtd, page);
-+      	//////////////
-+		status = this->waitfunc (mtd, this, FL_ERASING);
-+		/* See if block erase succeeded */
-+		if (status & 0x01) {
-+			DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page);
-+			instr->state = MTD_ERASE_FAILED;
-+			instr->fail_addr = (page << this->page_shift);
-+			goto erase_exit;
-+		}
-+
-+		/* Increment page address and decrement length */
-+		len -= (1 << this->phys_erase_shift);
-+		page += pages_per_block;
-+
-+		/* Check, if we cross a chip boundary */
-+		if (len && !(page & this->pagemask)) {
-+			chipnr++;
-+			this->select_chip(mtd, 0);
-+			this->select_chip(mtd, 0);
-+		}
-+		//sl2312_flash_delay();
-+           schedule();
-+           //cond_resched();
-+	}
-+	instr->state = MTD_ERASE_DONE;
-+
-+erase_exit:
-+	/* De-select the NAND device */
-+	this->select_chip(mtd, 0);
-+	spin_unlock_bh (&this->chip_lock);
-+
-+	ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;;
-+	/* Do call back function */
-+	if (!ret && instr->callback)
-+		instr->callback (instr);
-+
-+	/* The device is ready */
-+	spin_lock_bh (&this->chip_lock);
-+	this->state = FL_READY;
-+	spin_unlock_bh (&this->chip_lock);
-+	FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
-+	/* Return more or less happy */
-+	return ret;
-+}
-+
-+static void sl2312_nand_select_chip(struct mtd_info *mtd, int chip)
-+{
-+	//struct nand_chip *this = mtd->priv;
-+
-+	switch(chip) {
-+	case -1:
-+		CHIP_EN = NFLASH_CHIP0_EN;
-+		break;
-+	case 0:
-+		CHIP_EN = NFLASH_CHIP0_EN;
-+		break;
-+	case 1:
-+		CHIP_EN = NFLASH_CHIP1_EN;
-+		break;
-+	default:
-+			CHIP_EN = NFLASH_CHIP0_EN;
-+			break;
-+	}
-+}
-+
-+/**
-+ * nand_default_block_markbad - [DEFAULT] mark a block bad
-+ * @mtd:	MTD device structure
-+ * @ofs:	offset from device start
-+ *
-+ * This is the default implementation, which can be overridden by
-+ * a hardware specific driver.
-+*/
-+static int sl2312_nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
-+{
-+	struct nand_chip *this = mtd->priv;
-+	u_char buf[2] = {0, 0};
-+	size_t	retlen;
-+	int block;
-+
-+	/* Get block number */
-+	block = ((int) ofs) >> this->bbt_erase_shift;
-+	this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
-+
-+	/* Do we have a flash based bad block table ? */
-+	if (this->options & NAND_USE_FLASH_BBT)
-+		return nand_update_bbt (mtd, ofs);
-+
-+	/* We write two bytes, so we dont have to mess with 16 bit access */
-+	ofs += mtd->oobsize + (this->badblockpos & ~0x01);
-+	return sl2312_nand_write_oob (mtd, ofs , 2, &retlen, buf);
-+}
-+
-+/* Appropriate chip should already be selected */
-+static int sl2312_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)//(struct mtd_info *mtd, unsigned long page, )
-+{
-+	u_char *buf, *oobbuf;
-+	size_t  retlen;
-+	unsigned long page, chipnr;
-+	struct nand_chip *this = mtd->priv;
-+
-+	if (getchip) {
-+		page = (int)(ofs >> this->page_shift);
-+		chipnr = (int)(ofs >> this->chip_shift);
-+
-+		/* Grab the lock and see if the device is available */
-+		sl2312_nand_get_chip (this, mtd, FL_READING, NULL);
-+		/* Select the NAND device */
-+		this->select_chip(mtd, chipnr);
-+	} else
-+		page = (int) ofs;
-+
-+	buf = kmalloc (mtd->oobblock,GFP_KERNEL);
-+	oobbuf = kmalloc (mtd->oobsize,GFP_KERNEL);
-+
-+	if ((!buf)||(!oobbuf)) {
-+		printk ("sl2312_nand_block_bad : Unable to allocate SL2312 NAND MTD device structure.\n");
-+
-+	}
-+
-+	sl2312_nand_read_ecc (mtd, page, mtd->oobblock , &retlen, buf, oobbuf, NULL);
-+
-+
-+	if(((mtd->oobblock < 528)&&(oobbuf[5] != 0xff))||((mtd->oobblock > 528)&&(oobbuf[0] != 0xff)))
-+	{
-+		kfree(buf);
-+		kfree(oobbuf);
-+		return 1;
-+	}
-+
-+	kfree(buf);
-+	kfree(oobbuf);
-+	return 0;
-+}
-+
-+/*
-+*	Use NAND read ECC
-+*/
-+static int sl2312_nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
-+{
-+	return sl2312_nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL);
-+}
-+
-+/*
-+ * NAND read with ECC
-+ */
-+static int sl2312_nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
-+			  size_t * retlen, u_char * buf, u_char * oob_buf, struct nand_oobinfo *oobsel)
-+{
-+	int j, col, page, opcode, i;
-+	int end=0;//, ecc=0;//, end_page=0;
-+	int erase_state = 0;
-+	int read = 0, oob = 0, ecc_failed = 0;//, ecc_status = 0
-+	struct nand_chip *this = mtd->priv;
-+	u_char *data_poi, *oob_data = oob_buf;
-+	//u_char ecc_calc[6];
-+	//u_char ecc_code[6];
-+	int 	eccmode;
-+	int	*oob_config;
-+
-+
-+
-+	// use chip default if zero
-+	if (oobsel == NULL)
-+		oobsel = &mtd->oobinfo;
-+
-+	eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
-+	oob_config = oobsel->eccpos;
-+
-+	DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
-+
-+	/* Do not allow reads past end of device */
-+	if ((from + len) > mtd->size) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n");
-+		*retlen = 0;
-+		return -EINVAL;
-+	}
-+
-+	/* Grab the lock and see if the device is available */
-+	sl2312_nand_get_chip (this, mtd ,FL_READING, &erase_state);
-+
-+	/* Select the NAND device */
-+	this->select_chip(mtd, 0);
-+
-+	/* First we calculate the starting page */
-+	page = from >> this->page_shift;
-+
-+	//end_page = mtd->oobblock + mtd->oobsize;
-+	end = mtd->oobblock;
-+	//ecc = mtd->eccsize;
-+	/* Get raw starting column */
-+	col = (from & (mtd->oobblock - 1));
-+
-+
-+	/* Send the read command */
-+	//this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page);
-+
-+	/* Loop until all data read */
-+	FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
-+	while (read < len) {
-+
-+		//udelay(1200);
-+		/* If we have consequent page reads, apply delay or wait for ready/busy pin */
-+		if (read) {
-+			if (!this->dev_ready)
-+				udelay (this->chip_delay);
-+			else
-+				while (!this->dev_ready(mtd));
-+		}
-+
-+		/*
-+		 * If the read is not page aligned, we have to read into data buffer
-+		 * due to ecc, else we read into return buffer direct
-+		 */
-+		if (!col && (len - read) >= end)
-+			data_poi = &buf[read];
-+		else
-+			data_poi = this->data_buf;
-+
-+		/* get oob area, if we have no oob buffer from fs-driver */
-+		if (!oob_buf) {
-+			oob_data = &this->data_buf[end];
-+			oob = 0;
-+		}
-+
-+		j = 0;
-+		switch (eccmode) {
-+			case NAND_ECC_NONE: {	/* No ECC, Read in a page */
-+				FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
-+				break;
-+			}
-+
-+			case NAND_ECC_SOFT:	/* Software ECC 3/256: Read in a page + oob data */
-+				break;
-+
-+			case NAND_ECC_HW3_256: /* Hardware ECC 3 byte /256 byte data: Read in first 256 byte, get ecc, */
-+				break;
-+
-+			case NAND_ECC_HW3_512:
-+			case NAND_ECC_HW6_512: /* Hardware ECC 3/6 byte / 512 byte data : Read in a page  */
-+				FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
-+				break;
-+
-+			default:
-+				printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
-+				FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0);
-+				//BUG();
-+		}//end switch
-+
-+			for(i=0;ioobblock +i);
-+			}
-+			/* read oobdata */
-+			for (i = 0; i <  mtd->oobsize; i++)
-+			{
-+				//udelay(7);
-+				oob_data[oob + i] = FLASH_READ_DATA(page*mtd->oobblock +end+i);
-+			}
-+
-+		/* Skip ECC, if not active */
-+			if (eccmode == NAND_ECC_NONE)
-+				goto readdata;
-+
-+			// compare ecc and correct data
-+
-+				opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
-+				while(!(opcode&0x80000000)) //polling flash access 31b
-+      			{
-+        			   opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
-+        			   //sl2312_flash_delay();
-+        			   schedule();
-+      			}
-+      			for(j=0;j<(end/512);j++)
-+      			{//for 2k page
-+
-+					opcode = 0x00000000|oob_data[mtd->oobsize-3-4*j]<<16|oob_data[mtd->oobsize-2-4*j]<<8|oob_data[mtd->oobsize-1-4*j];
-+
-+					//opcode=FLASH_READ_REG(NFLASH_ECC_CODE_GEN0+(j*4));
-+
-+					FLASH_WRITE_REG(NFLASH_ECC_OOB, opcode);
-+					opcode = 0x00000000|(j<<8); //select ECC code generation 0
-+					FLASH_WRITE_REG(NFLASH_ECC_CONTROL, opcode); //???
-+
-+					opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
-+					if((opcode&0x00000003)==0x03)
-+					{
-+						printk (KERN_WARNING "\nPageRead Uncorrectable error !!\n");
-+						ecc_failed++;
-+					}
-+					else if((opcode&0x00000003)==0x01)
-+					{
-+						printk (KERN_WARNING "\nPageRead One bit data error !!");
-+						// correct data
-+						if((data_poi[(opcode&0xff80)>>7]>>((opcode&0x38)>>3))%1)
-+							data_poi[(opcode&0xff80)>>7] &= ~(1<<((opcode&0x38)>>3));
-+						else
-+							data_poi[(opcode&0xff80)>>7] |= (1<<((opcode&0x38)>>3));
-+
-+					}
-+					else if((opcode&0x00000003)==0x02)
-+					{
-+						printk (KERN_WARNING "\nPageRead One bit ECC error !!\n");
-+					}
-+					else if((opcode&0x00000003)==0x00)
-+					{
-+
-+					}
-+
-+				}//for 2k page
-+readdata:
-+		if (col || (len - read) < end) {
-+			for (j = col; j < end && read < len; j++)
-+				buf[read++] = data_poi[j];
-+		} else
-+			read += mtd->oobblock;
-+		/* For subsequent reads align to page boundary. */
-+		col = 0;
-+		/* Increment page address */
-+		page++;
-+		schedule();
-+	}
-+	/* De-select the NAND device */
-+	//this->select_chip(mtd, -1);
-+	FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
-+	FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_INDIRECT);
-+	/* Wake up anyone waiting on the device */
-+	spin_lock_bh (&this->chip_lock);
-+	this->state = FL_READY;
-+	wake_up (&this->wq);
-+	spin_unlock_bh (&this->chip_lock);
-+
-+	/*
-+	 * Return success, if no ECC failures, else -EIO
-+	 * fs driver will take care of that, because
-+	 * retlen == desired len and result == -EIO
-+	 */
-+	*retlen = read;
-+	return ecc_failed ? -EIO : 0;
-+}
-+
-+/*
-+ * Wait for command done. This applies to erase and program only
-+ * Erase can take up to 400ms and program up to 20ms according to
-+ * general NAND and SmartMedia specs
-+ *
-+*/
-+static int sl2312_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
-+{
-+	unsigned long	timeo = jiffies;
-+	int	status, opcode;
-+
-+	if (state == FL_ERASING)
-+		 timeo += (HZ * 400) / 1000;
-+	else
-+		 timeo += (HZ * 20) / 1000;
-+
-+	spin_lock_bh (&this->chip_lock);
-+	FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
-+	FLASH_WRITE_REG(NFLASH_COUNT, 0x007f000070); //set only command no address and two data
-+
-+	FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000070); //write read status command
-+
-+
-+	opcode = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
-+	FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
-+
-+	while(opcode&0x80000000) //polling flash access 31b
-+    {
-+        opcode=FLASH_READ_REG(NFLASH_ACCESS);
-+        //sl2312_flash_delay();
-+        schedule();
-+    }
-+
-+	while (time_before(jiffies, timeo)) {
-+		/* Check, if we were interrupted */
-+		if (this->state != state) {
-+			spin_unlock_bh (&this->chip_lock);
-+			FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
-+			return 0;
-+		}
-+		if (this->dev_ready) {
-+			if (this->dev_ready(mtd))
-+				break;
-+		}
-+		if (FLASH_READ_REG(NFLASH_DATA) & 0x40)
-+			break;
-+
-+		spin_unlock_bh (&this->chip_lock);
-+		yield ();
-+		spin_lock_bh (&this->chip_lock);
-+	}
-+	status = FLASH_READ_REG(NFLASH_DATA)&0xff;
-+	spin_unlock_bh (&this->chip_lock);
-+	FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
-+	return status;
-+}
-+
-+static int sl2312_nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
-+{
-+	int i, col, page, j=0;
-+	//int erase_state = 0;
-+	struct nand_chip *this = mtd->priv;
-+	u_char *databuf, *oobbuf;
-+
-+	databuf = &this->data_buf[0];
-+	oobbuf = &this->data_buf[mtd->oobblock];
-+		for (i = 0; i < mtd->oobsize; i++)
-+			oobbuf[i] = 0xff;
-+
-+	DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
-+
-+	/* Shift to get page */
-+	page = ((int) from) >> this->page_shift;
-+
-+	/* Mask to get column */
-+	col = from & (mtd->oobsize-1);  //0x0f;
-+
-+	/* Initialize return length value */
-+	*retlen = 0;
-+	sl2312_nand_read_ecc (mtd, page, mtd->oobblock , retlen, databuf, oobbuf, NULL);
-+	for(i=col,j=0;ioobsize||i<(col+len);i++,j++)
-+		buf[j] = oobbuf[i];
-+
-+	*retlen = j ;
-+	return 0;
-+}
-+
-+#define NOTALIGNED(x) (x & (mtd->oobblock-1)) != 0
-+/*
-+*	Use NAND write ECC
-+*/
-+static int sl2312_nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
-+{
-+	return (sl2312_nand_write_ecc (mtd, to, len, retlen, buf, NULL, NULL));
-+}
-+
-+/*
-+ * NAND write with ECC
-+ */
-+static int sl2312_nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
-+			   size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel)
-+{
-+	int page, ret = 0, oob = 0, written = 0;
-+	struct nand_chip *this = mtd->priv;
-+
-+	DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
-+
-+
-+	/* Do not allow write past end of device */
-+	if ((to + len) > mtd->size) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n");
-+		return -EINVAL;
-+	}
-+
-+	/* reject writes, which are not page aligned */
-+	if (NOTALIGNED (to) || NOTALIGNED(len)) {
-+		printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
-+		return -EINVAL;
-+	}
-+
-+	// if oobsel is NULL, use chip defaults
-+	if (oobsel == NULL)
-+		oobsel = &mtd->oobinfo;
-+
-+	/* Shift to get page */
-+	page = ((int) to) >> this->page_shift;
-+
-+	/* Grab the lock and see if the device is available */
-+	sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
-+
-+	/* Select the NAND device */
-+	this->select_chip(mtd, 0);
-+
-+	/* Check the WP bit */
-+	if (!(sl2312_device_ready(mtd) & 0x80)) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Device is write protected!!!\n");
-+		ret = -EIO;
-+		goto out;
-+	}
-+
-+	/* Loop until all data is written */
-+	while (written < len) {
-+		//udelay(100);
-+		int cnt = mtd->oobblock;
-+		this->data_poi = (u_char*) &buf[written];
-+		/* We use the same function for write and writev */
-+		if (eccbuf) {
-+			ret = sl2312_nand_write_page (mtd, this, page, &eccbuf[oob], oobsel);
-+			oob += mtd->oobsize;
-+		} else
-+			ret = sl2312_nand_write_page (mtd, this, page, NULL, oobsel);
-+
-+		if (ret)
-+			goto out;
-+
-+		/* Update written bytes count */
-+		written += cnt;
-+		/* Increment page address */
-+		page++;
-+	}
-+
-+out:
-+	/* De-select the NAND device */
-+	//this->select_chip(mtd, -1);
-+
-+	/* Wake up anyone waiting on the device */
-+	spin_lock_bh (&this->chip_lock);
-+	this->state = FL_READY;
-+	wake_up (&this->wq);
-+	spin_unlock_bh (&this->chip_lock);
-+
-+	*retlen = written;
-+	return ret;
-+}
-+
-+/*
-+ *	Nand_page_program function is used for write and writev !
-+ *	This function will always program a full page of data
-+ *	If you call it with a non page aligned buffer, you're lost :)
-+ */
-+static int sl2312_nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf,  struct nand_oobinfo *oobsel)
-+{
-+	int 	i, j, status, opcode;
-+	u_char	ecc_code[16], *oob_data;
-+	int	eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
-+	//int  	*oob_config = oobsel->eccpos;
-+
-+	/* pad oob area, if we have no oob buffer from fs-driver */
-+	if (!oob_buf) {
-+		oob_data = &this->data_buf[mtd->oobblock];
-+		for (i = 0; i < mtd->oobsize; i++)
-+			oob_data[i] = 0xff;
-+	} else
-+		oob_data = oob_buf;
-+
-+	/* Send command to begin auto page programming */
-+
-+	memset(oob_data,0xff,mtd->oobsize);
-+	/* Write out complete page of data, take care of eccmode */
-+	switch (eccmode) {
-+	/* No ecc and software ecc 3/256, write all */
-+	case NAND_ECC_NONE:
-+		printk (KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n");
-+		FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
-+		break;
-+	case NAND_ECC_SOFT:
-+		break;
-+
-+	/* Hardware ecc 3 byte / 256 data, write first half, get ecc, then second, if 512 byte pagesize */
-+	case NAND_ECC_HW3_256:
-+		break;
-+
-+	/* Hardware ecc 3 byte / 512 byte data, write full page */
-+	case NAND_ECC_HW3_512:
-+		FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
-+
-+	/* Hardware ecc 6 byte / 512 byte data, write full page */
-+	case NAND_ECC_HW6_512:
-+		break;
-+
-+	default:
-+		printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
-+		FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
-+		//BUG();
-+	}
-+
-+	FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
-+
-+	for(i=0;ioobblock;i++)
-+	{
-+		//udelay(5);
-+		FLASH_WRITE_DATA((page*mtd->oobblock)+i,this->data_poi[i]);
-+	}
-+	///////////////
-+	if(eccmode!=NAND_ECC_NONE)
-+	{
-+		opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
-+		while(!(opcode&0x80000000)) //polling flash access 31b
-+    	{
-+    	 	   opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
-+    	 	   //sl2312_flash_delay();
-+    	 	   schedule();
-+    	}
-+
-+
-+    	for(i=0;i<(mtd->oobblock/512);i++)
-+    	{
-+    		opcode=FLASH_READ_REG(NFLASH_ECC_CODE_GEN0+(i*4));
-+
-+    		for(j=3;j>0;j--)
-+    		      oob_data[(mtd->oobsize-j-(i*4))] = (opcode<<((4-j)*8)) >>24;
-+
-+    		for(j=0;j<4;j++)
-+    		{
-+    			ecc_code[15-i*4] = opcode;
-+    			ecc_code[15-i*4-1] = opcode>>8;
-+    			ecc_code[15-i*4-2] = opcode>>16;
-+    		}
-+    	}
-+
-+    	//disable ecc
-+    	FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000);
-+
-+    	/* Write out OOB data */
-+    	for(i=0;ioobsize;i++)
-+    	{
-+    		//udelay(5);
-+			FLASH_WRITE_DATA((page*mtd->oobblock)+mtd->oobblock+i,oob_data[i]);
-+		}
-+    }
-+    else
-+    {
-+    	for(i=0;ioobsize;i++)
-+    	{
-+    		//udelay(5);
-+			FLASH_WRITE_DATA((page*mtd->oobblock)+mtd->oobblock+i,0xff);
-+		}
-+    }
-+
-+
-+	/* call wait ready function */
-+	status = this->waitfunc (mtd, this, FL_WRITING);
-+	FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
-+	/* See if device thinks it succeeded */
-+	if (status & 0x01) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page);
-+		FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
-+		return -EIO;
-+	}
-+
-+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
-+	/*
-+	 * The NAND device assumes that it is always writing to
-+	 * a cleanly erased page. Hence, it performs its internal
-+	 * write verification only on bits that transitioned from
-+	 * 1 to 0. The device does NOT verify the whole page on a
-+	 * byte by byte basis. It is possible that the page was
-+	 * not completely erased or the page is becoming unusable
-+	 * due to wear. The read with ECC would catch the error
-+	 * later when the ECC page check fails, but we would rather
-+	 * catch it early in the page write stage. Better to write
-+	 * no data than invalid data.
-+	 */
-+
-+	/* Send command to read back the page */
-+	this->cmdfunc (mtd, NAND_CMD_READ0, 0, page);
-+	/* Loop through and verify the data */
-+	if (this->verify_buf(mtd, this->data_poi, mtd->oobblock)) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
-+		return -EIO;
-+	}
-+
-+	/* check, if we have a fs-supplied oob-buffer */
-+	if (oob_buf) {
-+		if (this->verify_buf(mtd, oob_data, mtd->oobsize)) {
-+			DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
-+			return -EIO;
-+		}
-+	} else {
-+		if (eccmode != NAND_ECC_NONE) {
-+			int ecc_bytes = 0;
-+
-+			switch (this->eccmode) {
-+			case NAND_ECC_SOFT:
-+			case NAND_ECC_HW3_256: ecc_bytes = (mtd->oobblock == 512) ? 6 : 3; break;
-+			case NAND_ECC_HW3_512: ecc_bytes = 3; break;
-+			case NAND_ECC_HW6_512: ecc_bytes = 6; break;
-+			}
-+
-+
-+
-+			for(i=0;i < (mtd->oobblock+mtd->oobsize);i++)
-+			{
-+				if(i>=mtd->oobblock)
-+					oob_data[i-mtd->oobblock] = FLASH_READ_DATA((page*mtd->oobblock) +i);
-+				else
-+					oob_data[0] = FLASH_READ_DATA((page*mtd->oobblock) +i);
-+			}
-+
-+			if(this->eccmode == NAND_ECC_HW3_512)
-+			{
-+				for(i=0;i<(mtd->oobblock/512);i++)
-+    			{
-+    				for(j=0;j<3;j++)
-+    				{
-+    				    if (oob_data[mtd->oobsize-1-j-4*i] != ecc_code[15-j-4*i]) {
-+							DEBUG (MTD_DEBUG_LEVEL0,
-+							       "%s: Failed ECC write "
-+						       "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
-+							return -EIO;
-+						}
-+    				}
-+    			}
-+			}
-+		}//eccmode != NAND_ECC_NONE
-+	}
-+	/*
-+	 * Terminate the read command. This is faster than sending a reset command or
-+	 * applying a 20us delay before issuing the next programm sequence.
-+	 * This is not a problem for all chips, but I have found a bunch of them.
-+	 */
-+	//this->select_chip(mtd, -1);
-+	//this->select_chip(mtd, 0);
-+#endif
-+
-+	return 0;
-+}
-+
-+/*
-+ * NAND write with iovec
-+ */
-+static int sl2312_nand_writev (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
-+		loff_t to, size_t * retlen)
-+{
-+	return (sl2312_nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, 0));
-+}
-+
-+static int sl2312_nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
-+		loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel)
-+{
-+	int i, page, len, total_len, ret = 0, written = 0;
-+	struct nand_chip *this = mtd->priv;
-+
-+	/* Calculate total length of data */
-+	total_len = 0;
-+	for (i = 0; i < count; i++)
-+		total_len += (int) vecs[i].iov_len;
-+
-+	DEBUG (MTD_DEBUG_LEVEL3,
-+	       "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
-+
-+	/* Do not allow write past end of page */
-+	if ((to + total_len) > mtd->size) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n");
-+		return -EINVAL;
-+	}
-+
-+	/* reject writes, which are not page aligned */
-+	if (NOTALIGNED (to) || NOTALIGNED(total_len)) {
-+		printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
-+		return -EINVAL;
-+	}
-+
-+	// if oobsel is NULL, use chip defaults
-+	if (oobsel == NULL)
-+		oobsel = &mtd->oobinfo;
-+
-+	/* Shift to get page */
-+	page = ((int) to) >> this->page_shift;
-+
-+	/* Grab the lock and see if the device is available */
-+	sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
-+
-+	/* Select the NAND device */
-+	this->select_chip(mtd, 0);
-+
-+	/* Check the WP bit */
-+	if (!(sl2312_device_ready(mtd) & 0x80)) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "sl2312_nand_writev_ecc: Device is write protected!!!\n");
-+		ret = -EIO;
-+		goto out;
-+	}
-+
-+	/* Loop until all iovecs' data has been written */
-+	len = 0;
-+	while (count) {
-+		/*
-+		 *  Check, if the tuple gives us not enough data for a
-+		 *  full page write. Then we can use the iov direct,
-+		 *  else we have to copy into data_buf.
-+		 */
-+		if ((vecs->iov_len - len) >= mtd->oobblock) {
-+			this->data_poi = (u_char *) vecs->iov_base;
-+			this->data_poi += len;
-+			len += mtd->oobblock;
-+			/* Check, if we have to switch to the next tuple */
-+			if (len >= (int) vecs->iov_len) {
-+				vecs++;
-+				len = 0;
-+				count--;
-+			}
-+		} else {
-+			/*
-+			 * Read data out of each tuple until we have a full page
-+			 * to write or we've read all the tuples.
-+		 	*/
-+			int cnt = 0;
-+			while ((cnt < mtd->oobblock) && count) {
-+				if (vecs->iov_base != NULL && vecs->iov_len) {
-+					this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++];
-+				}
-+				/* Check, if we have to switch to the next tuple */
-+				if (len >= (int) vecs->iov_len) {
-+					vecs++;
-+					len = 0;
-+					count--;
-+				}
-+			}
-+			this->data_poi = this->data_buf;
-+		}
-+
-+		/* We use the same function for write and writev !) */
-+		ret = sl2312_nand_write_page (mtd, this, page, NULL, oobsel);
-+		if (ret)
-+			goto out;
-+
-+		/* Update written bytes count */
-+		written += mtd->oobblock;;
-+
-+		/* Increment page address */
-+		page++;
-+	}
-+
-+out:
-+	/* De-select the NAND device */
-+	//this->select_chip(mtd, -1);
-+
-+	/* Wake up anyone waiting on the device */
-+	spin_lock_bh (&this->chip_lock);
-+	this->state = FL_READY;
-+	wake_up (&this->wq);
-+	spin_unlock_bh (&this->chip_lock);
-+
-+	*retlen = written;
-+	return ret;
-+}
-+
-+/*
-+static u_char ffchars[] = {
-+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-+};
-+*/
-+/*
-+ * NAND write out-of-band
-+ */
-+static int sl2312_nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
-+{
-+	int column, page, status, ret = 0, j=0;
-+	struct nand_chip *this = mtd->priv;
-+	u_char *databuf, *oobbuf;
-+
-+
-+		databuf = &this->data_buf[0];
-+		oobbuf = &this->data_buf[mtd->oobblock];
-+		for (j = 0; j < mtd->oobsize; j++)
-+			oobbuf[j] = 0xff;
-+//#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
-+//	int 	i;
-+//#endif
-+
-+	DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
-+
-+	/* Shift to get page */
-+	page = ((int) to) >> this->page_shift;
-+
-+	/* Mask to get column */
-+	column = to & 0x1f;
-+
-+	/* Initialize return length value */
-+	*retlen = 0;
-+
-+	/* Do not allow write past end of page */
-+	if ((column + len) > mtd->oobsize) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n");
-+		return -EINVAL;
-+	}
-+
-+	/* Grab the lock and see if the device is available */
-+	sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
-+
-+	/* Select the NAND device */
-+	this->select_chip(mtd, 0);
-+
-+	/* Reset the chip. Some chips (like the Toshiba TC5832DC found
-+	   in one of my DiskOnChip 2000 test units) will clear the whole
-+	   data page too if we don't do this. I have no clue why, but
-+	   I seem to have 'fixed' it in the doc2000 driver in
-+	   August 1999.  dwmw2. */
-+	this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
-+
-+	/* Check the WP bit */
-+	if (!(sl2312_device_ready(mtd) & 0x80)) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Device is write protected!!!\n");
-+		ret = -EIO;
-+		goto out;
-+	}
-+	/* Write out desired data */
-+	this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page);
-+
-+	sl2312_nand_read_ecc (mtd, page, mtd->oobblock , retlen, databuf, oobbuf, NULL);
-+
-+    for(j=column;j<(column+len);j++)
-+    	oobbuf[j] = buf[j-column];
-+    sl2312_nand_write_ecc (mtd, page, mtd->oobblock, retlen, databuf, oobbuf, NULL);
-+
-+	status = this->waitfunc (mtd, this, FL_WRITING);
-+
-+	/* See if device thinks it succeeded */
-+	if (status & 0x01) {
-+		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page);
-+		ret = -EIO;
-+		goto out;
-+	}
-+	/* Return happy */
-+	*retlen = len;
-+
-+
-+out:
-+	/* De-select the NAND device */
-+	//this->select_chip(mtd, -1);
-+
-+	/* Wake up anyone waiting on the device */
-+	spin_lock_bh (&this->chip_lock);
-+	this->state = FL_READY;
-+	wake_up (&this->wq);
-+	spin_unlock_bh (&this->chip_lock);
-+
-+	return ret;
-+}
-+
-+/*
-+ * NAND sync
-+ */
-+static void sl2312_nand_sync (struct mtd_info *mtd)
-+{
-+	struct nand_chip *this = mtd->priv;
-+	DECLARE_WAITQUEUE (wait, current);
-+
-+	DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
-+
-+retry:
-+	/* Grab the spinlock */
-+	spin_lock_bh (&this->chip_lock);
-+
-+	/* See what's going on */
-+	switch (this->state) {
-+	case FL_READY:
-+	case FL_SYNCING:
-+		this->state = FL_SYNCING;
-+		spin_unlock_bh (&this->chip_lock);
-+		break;
-+
-+	default:
-+		/* Not an idle state */
-+		add_wait_queue (&this->wq, &wait);
-+		spin_unlock_bh (&this->chip_lock);
-+		schedule ();
-+
-+		remove_wait_queue (&this->wq, &wait);
-+		goto retry;
-+	}
-+
-+	/* Lock the device */
-+	spin_lock_bh (&this->chip_lock);
-+
-+	/* Set the device to be ready again */
-+	if (this->state == FL_SYNCING) {
-+		this->state = FL_READY;
-+		wake_up (&this->wq);
-+	}
-+
-+	/* Unlock the device */
-+	spin_unlock_bh (&this->chip_lock);
-+}
-+
-+
-+/*
-+ * Scan for the NAND device
-+ */
-+int sl2312_nand_scan (struct mtd_info *mtd, int maxchips)
-+{
-+	int i, j, nand_maf_id, nand_dev_id, busw;
-+	struct nand_chip *this = mtd->priv;
-+	unsigned char id[4];
-+
-+	/* Get buswidth to select the correct functions*/
-+	busw = this->options & NAND_BUSWIDTH_16;
-+
-+	/* check for proper chip_delay setup, set 20us if not */
-+	if (!this->chip_delay)
-+		this->chip_delay = 20;
-+
-+	/* check, if a user supplied command function given */
-+	if (this->cmdfunc == NULL)
-+		this->cmdfunc = sl2312_nand_command;
-+
-+	/* check, if a user supplied wait function given */
-+	if (this->waitfunc == NULL)
-+		this->waitfunc = sl2312_nand_waitfunc;
-+
-+	if (!this->select_chip)
-+		this->select_chip = sl2312_nand_select_chip;
-+	if (!this->write_byte)
-+		this->write_byte = sl2312_nand_write_byte; //busw ? nand_write_byte16 : nand_write_byte;
-+	if (!this->read_byte)
-+		this->read_byte = sl2312_nand_read_byte; //busw ? nand_read_byte16 : nand_read_byte;
-+//	if (!this->write_word)
-+//		this->write_word = nand_write_word;
-+//	if (!this->read_word)
-+//		this->read_word = nand_read_word;
-+//	if (!this->block_bad)
-+		this->block_bad = sl2312_nand_block_bad; //nand_block_bad;
-+	if (!this->block_markbad)
-+		this->block_markbad = sl2312_nand_default_block_markbad;
-+	if (!this->write_buf)
-+		this->write_buf = sl2312_nand_write_buf; //busw ? nand_write_buf16 : nand_write_buf;
-+	if (!this->read_buf)
-+		this->read_buf = sl2312_nand_read_buf; //busw ? nand_read_buf16 : nand_read_buf;
-+	if (!this->verify_buf)
-+		this->verify_buf = sl2312_nand_verify_buf; //busw ? nand_verify_buf16 : nand_verify_buf;
-+	if (!this->scan_bbt)
-+		this->scan_bbt = sl2312_nand_scan_bbt;
-+
-+	/* Select the device */
-+	this->select_chip(mtd, 0);
-+
-+	/* Read manufacturer and device IDs */
-+	nand_read_id(0,id);
-+
-+	nand_maf_id = id[0];
-+	nand_dev_id = id[1];
-+
-+	/* Print and store flash device information */
-+	for (i = 0; nand_flash_ids[i].name != NULL; i++) {
-+
-+		if (nand_dev_id != nand_flash_ids[i].id)
-+			continue;
-+
-+		if (!mtd->name) mtd->name = nand_flash_ids[i].name;
-+		this->chipsize = nand_flash_ids[i].chipsize << 20;
-+
-+		/* New devices have all the information in additional id bytes */
-+		if (!nand_flash_ids[i].pagesize) {
-+			int extid;
-+
-+			/* The 4th id byte is the important one */
-+			extid = id[3];
-+			/* Calc pagesize */
-+			mtd->oobblock = 1024 << (extid & 0x3);
-+			extid >>= 2;
-+			/* Calc oobsize */
-+			mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512);
-+			extid >>= 2;
-+			/* Calc blocksize. Blocksize is multiples of 64KiB */
-+			mtd->erasesize = (64 * 1024)  << (extid & 0x03);
-+			extid >>= 2;
-+			/* Get buswidth information */
-+			busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
-+
-+		} else {
-+			/* Old devices have this data hardcoded in the
-+			 * device id table */
-+			mtd->erasesize = nand_flash_ids[i].erasesize;
-+			mtd->oobblock = nand_flash_ids[i].pagesize;
-+			mtd->oobsize = mtd->oobblock / 32;
-+			busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
-+		}
-+
-+		/* Check, if buswidth is correct. Hardware drivers should set
-+		 * this correct ! */
-+		if (busw != (this->options & NAND_BUSWIDTH_16)) {
-+			printk (KERN_INFO "NAND device: Manufacturer ID:"
-+				" 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
-+				nand_manuf_ids[i].name , mtd->name);
-+			printk (KERN_WARNING
-+				"NAND bus width %d instead %d bit\n",
-+					(this->options & NAND_BUSWIDTH_16) ? 16 : 8,
-+					busw ? 16 : 8);
-+			this->select_chip(mtd, -1);
-+			return 1;
-+		}
-+
-+		/* Calculate the address shift from the page size */
-+		this->page_shift = ffs(mtd->oobblock) - 1;
-+		this->bbt_erase_shift = this->phys_erase_shift = ffs(mtd->erasesize) - 1;
-+		this->chip_shift = ffs(this->chipsize) - 1;
-+
-+		/* Set the bad block position */
-+		this->badblockpos = mtd->oobblock > 512 ?
-+			NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
-+
-+		/* Get chip options, preserve non chip based options */
-+		this->options &= ~NAND_CHIPOPTIONS_MSK;
-+		this->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
-+		/* Set this as a default. Board drivers can override it, if neccecary */
-+		this->options |= NAND_NO_AUTOINCR;
-+		/* Check if this is a not a samsung device. Do not clear the options
-+		 * for chips which are not having an extended id.
-+		 */
-+		if (nand_maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
-+			this->options &= ~NAND_SAMSUNG_LP_OPTIONS;
-+
-+		/* Check for AND chips with 4 page planes */
-+	//	if (this->options & NAND_4PAGE_ARRAY)
-+	//		this->erase_cmd = multi_erase_cmd;
-+	//	else
-+	//		this->erase_cmd = single_erase_cmd;
-+
-+		/* Do not replace user supplied command function ! */
-+	//	if (mtd->oobblock > 512 && this->cmdfunc == nand_command)
-+	//		this->cmdfunc = nand_command_lp;
-+
-+		/* Try to identify manufacturer */
-+		for (j = 0; nand_manuf_ids[j].id != 0x0; j++) {
-+			if (nand_manuf_ids[j].id == nand_maf_id)
-+				break;
-+		}
-+		printk (KERN_INFO "NAND device: Manufacturer ID:"
-+			" 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
-+			nand_manuf_ids[j].name , nand_flash_ids[i].name);
-+		break;
-+	}
-+	/////////////////////////////
-+
-+	for (i=1; i < maxchips; i++) {
-+		this->select_chip(mtd, i);
-+
-+		/* Send the command for reading device ID */
-+		nand_read_id(1,id);
-+
-+		/* Read manufacturer and device IDs */
-+		if (nand_maf_id != id[0] ||
-+		    nand_dev_id != id[1])
-+			break;
-+	}
-+	if (i > 1)
-+		printk(KERN_INFO "%d NAND chips detected\n", i);
-+
-+	/* Allocate buffers, if neccecary */
-+	if (!this->oob_buf) {
-+		size_t len;
-+		len = mtd->oobsize << (this->phys_erase_shift - this->page_shift);
-+		this->oob_buf = kmalloc (len, GFP_KERNEL);
-+		if (!this->oob_buf) {
-+			printk (KERN_ERR "nand_scan(): Cannot allocate oob_buf\n");
-+			return -ENOMEM;
-+		}
-+		this->options |= NAND_OOBBUF_ALLOC;
-+	}
-+
-+	if (!this->data_buf) {
-+		size_t len;
-+		len = mtd->oobblock + mtd->oobsize;
-+		this->data_buf = kmalloc (len, GFP_KERNEL);
-+		if (!this->data_buf) {
-+			if (this->options & NAND_OOBBUF_ALLOC)
-+				kfree (this->oob_buf);
-+			printk (KERN_ERR "nand_scan(): Cannot allocate data_buf\n");
-+			return -ENOMEM;
-+		}
-+		this->options |= NAND_DATABUF_ALLOC;
-+	}
-+
-+	/* Store the number of chips and calc total size for mtd */
-+	this->numchips = i;
-+	mtd->size = i * this->chipsize;
-+	/* Convert chipsize to number of pages per chip -1. */
-+	this->pagemask = (this->chipsize >> this->page_shift) - 1;
-+	/* Preset the internal oob buffer */
-+	memset(this->oob_buf, 0xff, mtd->oobsize << (this->phys_erase_shift - this->page_shift));
-+
-+	/* If no default placement scheme is given, select an
-+	 * appropriate one */
-+	if (!this->autooob) {
-+		/* Select the appropriate default oob placement scheme for
-+		 * placement agnostic filesystems */
-+		switch (mtd->oobsize) {
-+		case 8:
-+			this->autooob = &nand_oob_8;
-+			break;
-+		case 16:
-+			this->autooob = &nand_oob_16;
-+			break;
-+		case 64:
-+			this->autooob = &nand_oob_64;
-+			break;
-+		default:
-+			printk (KERN_WARNING "No oob scheme defined for oobsize %d\n",
-+				mtd->oobsize);
-+			BUG();
-+		}
-+	}
-+
-+	/* The number of bytes available for the filesystem to place fs dependend
-+	 * oob data */
-+	if (this->options & NAND_BUSWIDTH_16) {
-+		mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2);
-+		if (this->autooob->eccbytes & 0x01)
-+			mtd->oobavail--;
-+	} else
-+		mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1);
-+
-+
-+	/*
-+	 * check ECC mode, default to software
-+	 * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize
-+	 * fallback to software ECC
-+	*/
-+	this->eccsize = 256;	/* set default eccsize */
-+	this->eccbytes = 3;
-+
-+	switch (this->eccmode) {
-+	case NAND_ECC_HW12_2048:
-+		if (mtd->oobblock < 2048) {
-+			printk(KERN_WARNING "2048 byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
-+			       mtd->oobblock);
-+			this->eccmode = NAND_ECC_SOFT;
-+			this->calculate_ecc = nand_calculate_ecc;
-+			this->correct_data = nand_correct_data;
-+		} else
-+			this->eccsize = 2048;
-+		break;
-+
-+	case NAND_ECC_HW3_512:
-+	case NAND_ECC_HW6_512:
-+	case NAND_ECC_HW8_512:
-+		if (mtd->oobblock == 256) {
-+			printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n");
-+			this->eccmode = NAND_ECC_SOFT;
-+			this->calculate_ecc = nand_calculate_ecc;
-+			this->correct_data = nand_correct_data;
-+		} else
-+			this->eccsize = 512; /* set eccsize to 512 */
-+		break;
-+
-+	case NAND_ECC_HW3_256:
-+		break;
-+
-+	case NAND_ECC_NONE:
-+		printk (KERN_WARNING "NAND_ECC_NONE selected by board driver. This is not recommended !!\n");
-+		this->eccmode = NAND_ECC_NONE;
-+		break;
-+
-+	case NAND_ECC_SOFT:
-+		this->calculate_ecc = nand_calculate_ecc;
-+		this->correct_data = nand_correct_data;
-+		break;
-+
-+	default:
-+		printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
-+		BUG();
-+	}
-+
-+	/* Check hardware ecc function availability and adjust number of ecc bytes per
-+	 * calculation step
-+	*/
-+	switch (this->eccmode) {
-+	case NAND_ECC_HW12_2048:
-+		this->eccbytes += 4;
-+	case NAND_ECC_HW8_512:
-+		this->eccbytes += 2;
-+	case NAND_ECC_HW6_512:
-+		this->eccbytes += 3;
-+//	case NAND_ECC_HW3_512:
-+	case NAND_ECC_HW3_256:
-+		if (this->calculate_ecc && this->correct_data && this->enable_hwecc)
-+			break;
-+		printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n");
-+		BUG();
-+	}
-+
-+	mtd->eccsize = this->eccsize;
-+
-+	/* Set the number of read / write steps for one page to ensure ECC generation */
-+	switch (this->eccmode) {
-+	case NAND_ECC_HW12_2048:
-+		this->eccsteps = mtd->oobblock / 2048;
-+		break;
-+	case NAND_ECC_HW3_512:
-+	case NAND_ECC_HW6_512:
-+	case NAND_ECC_HW8_512:
-+		this->eccsteps = mtd->oobblock / 512;
-+		break;
-+	case NAND_ECC_HW3_256:
-+	case NAND_ECC_SOFT:
-+		this->eccsteps = mtd->oobblock / 256;
-+		break;
-+
-+	case NAND_ECC_NONE:
-+		this->eccsteps = 1;
-+		break;
-+	}
-+
-+	/* Initialize state, waitqueue and spinlock */
-+	this->state = FL_READY;
-+	init_waitqueue_head (&this->wq);
-+	spin_lock_init (&this->chip_lock);
-+
-+	/* De-select the device */
-+	this->select_chip(mtd, 0);
-+
-+	/* Print warning message for no device */
-+	if (!mtd->size) {
-+		printk (KERN_WARNING "No NAND device found!!!\n");
-+		return 1;
-+	}
-+
-+	/* Fill in remaining MTD driver data */
-+	mtd->type = MTD_NANDFLASH;
-+	mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
-+	mtd->ecctype = MTD_ECC_SW;
-+	mtd->erase = sl2312_nand_erase;
-+	mtd->point = NULL;
-+	mtd->unpoint = NULL;
-+	mtd->read = sl2312_nand_read;
-+	mtd->write = sl2312_nand_write;
-+	mtd->read_ecc = sl2312_nand_read_ecc;
-+	mtd->write_ecc = sl2312_nand_write_ecc;
-+	mtd->read_oob = sl2312_nand_read_oob;
-+	mtd->write_oob = sl2312_nand_write_oob;
-+	mtd->readv = NULL;
-+	mtd->writev = sl2312_nand_writev;
-+	mtd->writev_ecc = sl2312_nand_writev_ecc;
-+	mtd->sync = sl2312_nand_sync;
-+	mtd->lock = NULL;
-+	mtd->unlock = NULL;
-+	mtd->suspend = NULL;
-+	mtd->resume = NULL;
-+	mtd->block_isbad = sl2312_nand_block_isbad;
-+	mtd->block_markbad = sl2312_nand_block_markbad;
-+
-+	/* and make the autooob the default one */
-+	memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
-+
-+	mtd->owner = THIS_MODULE;
-+
-+	/* Build bad block table */
-+	return this->scan_bbt (mtd);
-+}
-+
-+/*End Add function*/
-+
-+/*
-+ * Main initialization routine
-+ */
-+extern int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
-+
-+int __init sl2312_mtd_init (void)
-+{
-+	struct nand_chip *this;
-+	int err = 0;
-+	struct mtd_partition *parts;
-+	int nr_parts = 0;
-+	int ret, data, *base;
-+
-+	printk("NAND MTD Driver Start Init ......\n");
-+
-+    	base = (unsigned int *)(IO_ADDRESS(SL2312_GLOBAL_BASE) + 0x30);
-+    	data = *base;
-+    	data&=0xffffffeb;
-+    	data|=0x3; //disable p & s flash
-+        *base = data;
-+
-+	/* Allocate memory for MTD device structure and private data */
-+	sl2312_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
-+	if (!sl2312_mtd) {
-+		printk ("Unable to allocate SL2312 NAND MTD device structure.\n");
-+		err = -ENOMEM;
-+		goto out;
-+	}
-+
-+      //  sl2312_device_setup();
-+
-+	/* io is indirect via a register so don't need to ioremap address */
-+
-+	/* Get pointer to private data */
-+	this = (struct nand_chip *) (&sl2312_mtd[1]);
-+
-+	/* Initialize structures */
-+	memset((char *) sl2312_mtd, 0, sizeof(struct mtd_info));
-+	memset((char *) this, 0, sizeof(struct nand_chip));
-+
-+	/* Link the private data with the MTD structure */
-+	sl2312_mtd->priv = this;
-+	sl2312_mtd->name = "sl2312-nand";
-+
-+	/* Set address of NAND IO lines */
-+	this->IO_ADDR_R = (void __iomem *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE+NFLASH_DATA)); //(unsigned long)&(sl2312_ndfmcptr->dtr);
-+	this->IO_ADDR_W = (void __iomem *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE+NFLASH_DATA)); //(unsigned long)&(sl2312_ndfmcptr->dtr);
-+	this->read_byte = sl2312_nand_read_byte;
-+    this->write_byte = sl2312_nand_write_byte;
-+    this->write_buf = sl2312_nand_write_buf;
-+	this->read_buf = sl2312_nand_read_buf;
-+	this->verify_buf = sl2312_nand_verify_buf;
-+	this->select_chip = sl2312_nand_select_chip;
-+	this->block_bad = sl2312_nand_block_bad;
-+	this->hwcontrol = sl2312_hwcontrol;
-+	this->dev_ready = sl2312_device_ready;
-+	this->cmdfunc = sl2312_nand_command;
-+	this->waitfunc = sl2312_nand_waitfunc;
-+	//this->calculate_ecc = sl2312_readecc;
-+	this->enable_hwecc = sl2312_enable_hwecc;
-+	this->eccmode = NAND_ECC_HW3_512;
-+	/*this->eccsize = 512;	*/
-+	/* 20 us command delay time */
-+	this->chip_delay = 20;
-+
-+	this->correct_data = nand_correct_data;
-+//	this->scan_bbt = sl2312_nand_scan_bbt;
-+
-+	/* Allocate memory for internal data buffer */
-+	this->data_buf = kmalloc (sizeof(u_char) * (sl2312_mtd->oobblock + sl2312_mtd->oobsize), GFP_KERNEL);
-+	if (!this->data_buf) {
-+		printk ("Unable to allocate NAND data buffer.\n");
-+		err = -ENOMEM;
-+		goto out_ior;
-+	}
-+
-+	/* Scan to find existance of the device */
-+	if (sl2312_nand_scan(sl2312_mtd, 1)) {
-+		err = -ENXIO;
-+		goto out_ior;
-+	}
-+
-+	/* Register the partitions */
-+	parts = sl2312_partitions;
-+	nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
-+
-+	ret = add_mtd_partitions(sl2312_mtd, sl2312_partitions, nr_parts);
-+	/*If we got an error, free all resources.*/
-+	if (ret < 0) {
-+		del_mtd_partitions(sl2312_mtd);
-+		map_destroy(sl2312_mtd);
-+	}
-+	goto out;
-+
-+//out_buf:
-+//	kfree (this->data_buf);
-+out_ior:
-+out:
-+	printk("NAND MTD Driver Init Success ......\n");
-+	return err;
-+}
-+
-+module_init(sl2312_mtd_init);
-+
-+/*
-+ * Clean up routine
-+ */
-+#ifdef MODULE
-+static void __exit sl2312_cleanup (void)
-+{
-+	struct nand_chip *this = (struct nand_chip *) &sl2312_mtd[1];
-+
-+	/* Unregister partitions */
-+	del_mtd_partitions(sl2312_mtd);
-+
-+	/* Unregister the device */
-+	del_mtd_device (sl2312_mtd);
-+
-+	/* Free internal data buffers */
-+	kfree (this->data_buf);
-+
-+	/* Free the MTD device structure */
-+	kfree (sl2312_mtd);
-+}
-+module_exit(sl2312_cleanup);
-+#endif
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Alice Hennessy ");
-+MODULE_DESCRIPTION("Glue layer for SmartMediaCard on Toshiba RBsl2312");
---- /dev/null
-+++ b/drivers/mtd/nand/sl2312-flash-nand.h
-@@ -0,0 +1,24 @@
-+#ifndef SL2312_FLASH_NAND_H
-+#define SL2312_FLASH_NAND_H
-+
-+#include 
-+#include 
-+
-+/*Add function*/
-+static void nand_read_id(int chip_no,unsigned char *id);
-+
-+
-+
-+#define	NFLASH_WiDTH8              0x00000000
-+#define	NFLASH_WiDTH16             0x00000400
-+#define	NFLASH_WiDTH32             0x00000800
-+#define NFLASH_CHIP0_EN            0x00000000  // 16th bit = 0
-+#define NFLASH_CHIP1_EN            0x00010000  // 16th bit = 1
-+#define	NFLASH_DIRECT              0x00004000
-+#define	NFLASH_INDIRECT            0x00000000
-+
-+
-+#define	DWIDTH             NFLASH_WiDTH8
-+
-+
-+#endif /* SL2312_FLASH_NAND_H */
---- /dev/null
-+++ b/include/linux/mtd/kvctl.h
-@@ -0,0 +1,40 @@
-+#ifndef KVCTL_H
-+#define KVCTL_H
-+
-+#define VCTL_HEAD_SIZE	8
-+#define VCTL_ENTRY_LEN	20
-+
-+typedef struct
-+{
-+  char header[4];
-+  unsigned int entry_num;
-+} vctl_mheader;
-+
-+typedef struct
-+{
-+  char header[4];
-+  unsigned int size;
-+  unsigned int type;
-+  char majorver[4];
-+  char minorver[4];
-+  unsigned char *payload;
-+} vctl_entry;
-+
-+typedef struct
-+{
-+  unsigned char mac[6];
-+  unsigned char vlanid;
-+  unsigned char vlanmap;
-+} vlaninfo;
-+
-+#define VCT_VENDORSPEC		0
-+#define VCT_BOOTLOADER		1
-+#define VCT_KERNEL		2
-+#define VCT_VERCTL		3
-+#define VCT_CURRCONF		4
-+#define VCT_DEFAULTCONF		5
-+#define VCT_ROOTFS		6
-+#define VCT_APP			7
-+#define VCT_VLAN		8
-+
-+#endif
---- a/drivers/mtd/maps/Makefile
-+++ b/drivers/mtd/maps/Makefile
-@@ -71,3 +71,7 @@
- obj-$(CONFIG_MTD_OMAP_NOR)	+= omap_nor.o
- obj-$(CONFIG_MTD_MTX1)		+= mtx-1_flash.o
- obj-$(CONFIG_MTD_TQM834x)	+= tqm834x.o
-+###### for Storlink Soc #######
-+obj-$(CONFIG_MTD_SL2312_CFI) += sl2312-flash-cfi.o
-+obj-$(CONFIG_MTD_SL2312_SERIAL_ATMEL) += sl2312-flash-atmel.o
-+obj-$(CONFIG_MTD_SL2312_SERIAL_ST) += sl2312-flash-m25p80.o
diff --git a/target/linux/storm/patches/008-serial.patch b/target/linux/storm/patches/008-serial.patch
deleted file mode 100644
index b7009af251..0000000000
--- a/target/linux/storm/patches/008-serial.patch
+++ /dev/null
@@ -1,2809 +0,0 @@
---- /dev/null
-+++ b/drivers/serial/it8712.c
-@@ -0,0 +1,858 @@
-+/*
-+ *  linux/drivers/char/serial_uart00.c
-+ *
-+ *  Driver for UART00 serial ports
-+ *
-+ *  Based on drivers/char/serial_amba.c, by ARM Limited &
-+ *                                          Deep Blue Solutions Ltd.
-+ *  Copyright 2001 Altera Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ *
-+ *  $Id: it8712.c,v 1.2 2006/06/06 06:36:04 middle Exp $
-+ *
-+ */
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#if defined(CONFIG_SERIAL_IT8712_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-+#define SUPPORT_SYSRQ
-+#endif
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include "it8712.h"
-+
-+//#define DEBUG           1
-+#define UART_NR		1
-+
-+#define SERIAL_IT8712_NAME	"ttySI"
-+#define SERIAL_IT8712_MAJOR	204
-+#define SERIAL_IT8712_MINOR	41      /* Temporary - will change in future */
-+#define SERIAL_IT8712_NR	UART_NR
-+#define UART_PORT_SIZE 0x50
-+#define LPC_HOST_CONTINUE_MODE	0x00000040
-+
-+#define IT8712_NO_PORTS         UART_NR
-+#define IT8712_ISR_PASS_LIMIT	256
-+
-+#define LPC_BUS_CTRL	*(unsigned int*)(IO_ADDRESS(SL2312_LPC_HOST_BASE + 4))
-+#define LPC_BUS_STATUS	*(unsigned int*)(IO_ADDRESS(SL2312_LPC_HOST_BASE + 4))
-+#define LPC_SERIAL_IRQ_CTRL	*(unsigned int*)(IO_ADDRESS(SL2312_LPC_HOST_BASE + 8))
-+#define LPC_SERIAL_IRQ_STATUS	*(unsigned int*)(IO_ADDRESS(SL2312_LPC_HOST_BASE + 0x0c))
-+#define LPC_SERIAL_IRQ_TRITYPE *(unsigned int*)(IO_ADDRESS(SL2312_LPC_HOST_BASE + 0x10))
-+#define LPC_SERIAL_IRQ_POLARITY	*(unsigned int*)(IO_ADDRESS(SL2312_LPC_HOST_BASE + 0x14))
-+#define LPC_SERIAL_IRQ_ENABLE	*(unsigned int*)(IO_ADDRESS(SL2312_LPC_HOST_BASE + 0x18))
-+
-+
-+
-+
-+/*
-+ * Access macros for the SL2312 UARTs
-+ */
-+#define UART_GET_INT_STATUS(p)	(inb(((p)->membase+UART_IIR)) & 0x0F)  // interrupt identification
-+#define UART_PUT_IER(p, c)      outb(c,((p)->membase+UART_IER))         // interrupt enable
-+#define UART_GET_IER(p)         inb(((p)->membase+UART_IER))
-+#define UART_PUT_CHAR(p, c)     outb(c,((p)->membase+UART_TX))         // transmitter holding
-+#define UART_GET_CHAR(p)        inb(((p)->membase+UART_RX))            // receive buffer
-+#define UART_GET_LSR(p)         inb(((p)->membase+UART_LSR))            // line status
-+#define UART_GET_MSR(p)         inb(((p)->membase+UART_MSR))            // modem status
-+#define UART_GET_MCR(p)         inb(((p)->membase+UART_MCR))            // modem control
-+#define UART_PUT_MCR(p, c)      outb(c,((p)->membase+UART_MCR))
-+#define UART_GET_LCR(p)         inb(((p)->membase+UART_LCR))       // mode control
-+#define UART_PUT_LCR(p, c)      outb(c,((p)->membase+UART_LCR))
-+#define UART_PUT_FCR(p, c)      outb(c,((p)->membase+UART_FCR))       // fifo control
-+#define UART_GET_DIV_HI(p)	inb(((p)->membase+UART_DLM))
-+#define UART_PUT_DIV_HI(p, c)	outb(c,((p)->membase+UART_DLM))
-+#define UART_GET_DIV_LO(p)	inb(((p)->membase+UART_DLL))
-+#define UART_PUT_DIV_LO(p, c)	outb(c,((p)->membase+UART_DLL))
-+#define UART_PUT_MDR(p, c)      outb(c,UART_MDR((p)->membase))
-+#define UART_RX_DATA(s)		((s) & UART_LSR_DR)
-+#define UART_TX_READY(s)	((s) & UART_LSR_THRE)
-+
-+static void it8712_stop_tx(struct uart_port *port, u_int from_tty)
-+{
-+        unsigned int reg;
-+
-+        //printk("it8712 stop tx : \n");
-+        reg = UART_GET_IER(port);
-+        reg &= ~(UART_IER_THRI);
-+	UART_PUT_IER(port, reg);
-+}
-+
-+static void it8712_stop_rx(struct uart_port *port)
-+{
-+        unsigned int reg;
-+
-+        //printk("it8712 stop rx : \n");
-+        reg = UART_GET_IER(port);
-+        reg &= ~(UART_IER_RDI);
-+	UART_PUT_IER(port, reg);
-+
-+}
-+
-+static void it8712_enable_ms(struct uart_port *port)
-+{
-+        unsigned int reg;
-+
-+        //printk("it8712 enable ms : \n");
-+
-+        reg = UART_GET_IER(port);
-+        reg |= (UART_IER_MSI);
-+	UART_PUT_IER(port, reg);
-+
-+}
-+
-+static void it8712_rx_chars(struct uart_port *port, struct pt_regs *regs)
-+{
-+	struct tty_struct *tty = port->info->tty;
-+	unsigned int status, mask, ch, flg, ignored = 0;
-+
-+ //       printk("it8712_rx_chars : \n");
-+	status = UART_GET_LSR(port);
-+	while (UART_RX_DATA(status)) {
-+
-+		/*
-+		 * We need to read rds before reading the
-+		 * character from the fifo
-+		 */
-+		ch = UART_GET_CHAR(port);
-+		port->icount.rx++;
-+
-+		if (tty->flip.count >= TTY_FLIPBUF_SIZE)
-+			goto ignore_char;
-+
-+		flg = TTY_NORMAL;
-+
-+		/*
-+		 * Note that the error handling code is
-+		 * out of the main execution path
-+		 */
-+
-+		if (status & (UART_LSR_OE|UART_LSR_PE|UART_LSR_FE|UART_LSR_BI|UART_LSR_DE))
-+			goto handle_error;
-+		if (uart_handle_sysrq_char(port, ch, regs))
-+			goto ignore_char;
-+
-+	error_return:
-+		*tty->flip.flag_buf_ptr++ = flg;
-+		*tty->flip.char_buf_ptr++ = ch;
-+		tty->flip.count++;
-+	ignore_char:
-+		status = UART_GET_LSR(port);
-+	} // end of while
-+out:
-+	tty_flip_buffer_push(tty);
-+	return;
-+
-+handle_error:
-+	if (status & UART_LSR_BI) {
-+		status &= ~(UART_LSR_FE);
-+		port->icount.brk++;
-+
-+#ifdef SUPPORT_SYSRQ
-+		if (uart_handle_break(port))
-+			goto ignore_char;
-+#endif
-+	} else if (status & UART_LSR_PE)
-+		port->icount.parity++;
-+	else if (status & UART_LSR_FE)
-+		port->icount.frame++;
-+
-+	if (status & UART_LSR_OE)
-+		port->icount.overrun++;
-+
-+	if (status & port->ignore_status_mask) {
-+		if (++ignored > 100)
-+			goto out;
-+		goto ignore_char;
-+	}
-+
-+	mask = status & port->read_status_mask;
-+
-+	if (mask & UART_LSR_BI)
-+		flg = TTY_BREAK;
-+	else if (mask & UART_LSR_PE)
-+		flg = TTY_PARITY;
-+	else if (mask & UART_LSR_FE)
-+		flg = TTY_FRAME;
-+
-+	if (status & UART_LSR_OE) {
-+		/*
-+		 * CHECK: does overrun affect the current character?
-+		 * ASSUMPTION: it does not.
-+		 */
-+		*tty->flip.flag_buf_ptr++ = flg;
-+		*tty->flip.char_buf_ptr++ = ch;
-+		tty->flip.count++;
-+		if (tty->flip.count >= TTY_FLIPBUF_SIZE)
-+			goto ignore_char;
-+		ch = 0;
-+		flg = TTY_OVERRUN;
-+	}
-+#ifdef SUPPORT_SYSRQ
-+	port->sysrq = 0;
-+#endif
-+	goto error_return;
-+}
-+
-+static void it8712_tx_chars(struct uart_port *port)
-+{
-+        struct circ_buf *xmit = &port->info->xmit;
-+	int count;
-+
-+	if (port->x_char) {
-+		while(!(UART_GET_LSR(port)&UART_LSR_THRE));
-+		UART_PUT_CHAR(port, port->x_char);
-+		port->icount.tx++;
-+		port->x_char = 0;
-+
-+		return;
-+	}
-+	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
-+		it8712_stop_tx(port, 0);
-+		return;
-+	}
-+
-+	count = port->fifosize >> 1;
-+	do {
-+		while(!(UART_GET_LSR(port)&UART_LSR_THRE));
-+		UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
-+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-+		port->icount.tx++;
-+		if (uart_circ_empty(xmit))
-+			break;
-+	} while (--count > 0);
-+
-+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-+		uart_write_wakeup(port);
-+
-+	if (uart_circ_empty(xmit))
-+		it8712_stop_tx(port, 0);
-+}
-+
-+static void it8712_start_tx(struct uart_port *port, unsigned int tty_start)
-+{
-+        unsigned int reg;
-+
-+        //printk("it8712 start tx : \n");
-+        reg = UART_GET_IER(port);
-+        reg |= (UART_IER_THRI);
-+	UART_PUT_IER(port, reg);
-+	it8712_tx_chars(port);
-+}
-+
-+static void it8712_modem_status(struct uart_port *port)
-+{
-+	unsigned int status;
-+
-+//        printk("it8712 modem status : \n");
-+
-+	status = UART_GET_MSR(port);
-+
-+	if (!(status & (UART_MSR_DCTS | UART_MSR_DDSR |
-+		       UART_MSR_TERI | UART_MSR_DDCD)))
-+		return;
-+
-+        if (status & UART_MSR_DDCD)
-+                uart_handle_dcd_change(port, status & UART_MSR_DCD);
-+
-+        if (status & UART_MSR_DDSR)
-+                port->icount.dsr++;
-+
-+        if (status & UART_MSR_DCTS)
-+                uart_handle_cts_change(port, status & UART_MSR_CTS);
-+
-+	wake_up_interruptible(&port->info->delta_msr_wait);
-+
-+}
-+
-+static irqreturn_t  it8712_int(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+	struct uart_port *port = dev_id;
-+	unsigned int status, pass_counter = 0, data;
-+
-+
-+		data = LPC_SERIAL_IRQ_STATUS;
-+	if((data&0x10)==0x10)
-+	{
-+		status = UART_GET_INT_STATUS(port);
-+		do {
-+//			     printk("it8712_int: status %x \n", status);
-+			switch(status)
-+			{
-+			   case UART_IIR_RDI:
-+			   case UART_IIR_RLSI:
-+			   case UART_IIR_RCTO:
-+				it8712_rx_chars(port, regs);
-+			   break;
-+			   case UART_IIR_THRI:
-+				it8712_tx_chars(port);
-+			   break;
-+			   case UART_IIR_MSI:
-+				it8712_modem_status(port);
-+			   break;
-+			   default:
-+			   break;
-+			}
-+			if (pass_counter++ > IT8712_ISR_PASS_LIMIT)
-+				break;
-+
-+			status = UART_GET_INT_STATUS(port);
-+		} while (status);
-+	}
-+
-+		status = 0;
-+        status |= (IRQ_LPC_MASK);
-+        *((volatile unsigned int *)IRQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE))) = status;
-+
-+	//cnt=0;
-+	//do{
-+	//	data = LPC_SERIAL_IRQ_STATUS;
-+		LPC_SERIAL_IRQ_STATUS = data;
-+	//	cnt++;
-+	//}while(data);
-+	//if(cnt>2)
-+	//	printf("it8712_uart_Isr clear LPC_SERIAL_IRQ_STATUS %x \n", cnt);
-+        return IRQ_HANDLED;
-+}
-+
-+static u_int it8712_tx_empty(struct uart_port *port)
-+{
-+//        printk("it8712 tx empty : \n");
-+
-+	return ((UART_GET_LSR(port) & UART_LSR_THRE)? TIOCSER_TEMT : 0);
-+}
-+
-+static u_int it8712_get_mctrl(struct uart_port *port)
-+{
-+	unsigned int result = 0;
-+	unsigned int status;
-+
-+//        printk("it8712 get mctrl : \n");
-+
-+	status = UART_GET_MSR(port);
-+	if (status & UART_MSR_DCD)
-+		result |= TIOCM_CAR;
-+	if (status & UART_MSR_DSR)
-+		result |= TIOCM_DSR;
-+	if (status & UART_MSR_CTS)
-+		result |= TIOCM_CTS;
-+	if (status & UART_MSR_RI)
-+		result |= TIOCM_RI;
-+
-+	return result;
-+}
-+
-+static void it8712_set_mctrl_null(struct uart_port *port, u_int mctrl)
-+{
-+}
-+
-+static void it8712_break_ctl(struct uart_port *port, int break_state)
-+{
-+	unsigned int lcr;
-+
-+//        printk("it8712 break ctl : \n");
-+
-+	lcr = UART_GET_LCR(port);
-+	if (break_state == -1)
-+		lcr |= UART_LCR_SBC;
-+	else
-+		lcr &= ~UART_LCR_SBC;
-+	UART_PUT_LCR(port, lcr);
-+}
-+
-+static inline u_int uart_calculate_quot(struct uart_port *port, u_int baud)
-+{
-+	u_int quot;
-+
-+	/* Special case: B0 rate */
-+	if (!baud)
-+		baud = 9600;
-+
-+	quot = (port->uartclk/(16 * baud)) ;
-+
-+	return quot;
-+}
-+static void it8712_set_termios(struct uart_port *port, struct termios *termios,
-+                               struct termios *old)
-+{
-+	unsigned int  uart_mc, old_ier, baud, quot;
-+	unsigned long flags;
-+
-+        termios->c_cflag |= CREAD;
-+        termios->c_cflag |= CLOCAL;
-+#ifdef DEBUG
-+	printk("it8712_set_cflag(0x%x) called\n", cflag);
-+#endif
-+        baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
-+        quot = uart_get_divisor(port, baud);
-+
-+	/* byte size and parity */
-+	switch (termios->c_cflag & CSIZE) {
-+	case CS5:
-+              uart_mc = UART_LCR_WLEN5;
-+              break;
-+	case CS6:
-+              uart_mc = UART_LCR_WLEN6;
-+              break;
-+	case CS7:
-+              uart_mc = UART_LCR_WLEN7;
-+              break;
-+	default: // CS8
-+              uart_mc = UART_LCR_WLEN8;
-+              break;
-+	}
-+
-+	if (termios->c_cflag & CSTOPB)
-+		uart_mc|= UART_LCR_STOP;
-+	if (termios->c_cflag & PARENB) {
-+		uart_mc |= UART_LCR_EVEN;
-+		if (!(termios->c_cflag & PARODD))
-+			uart_mc |= UART_LCR_ODD;
-+	}
-+
-+        spin_lock_irqsave(&port->lock, flags);
-+        /*
-+         * Update the per-port timeout
-+         */
-+        uart_update_timeout(port, termios->c_cflag, baud);
-+	port->read_status_mask = UART_LSR_OE;
-+	if (termios->c_iflag & INPCK)
-+		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
-+	if (termios->c_iflag & (BRKINT | PARMRK))
-+		port->read_status_mask |= UART_LSR_BI;
-+
-+	/*
-+	 * Characters to ignore
-+	 */
-+	port->ignore_status_mask = 0;
-+	if (termios->c_iflag & IGNPAR)
-+		port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE;
-+	if (termios->c_iflag & IGNBRK) {
-+		port->ignore_status_mask |= UART_LSR_BI;
-+		/*
-+		 * If we're ignoring parity and break indicators,
-+		 * ignore overruns to (for real raw support).
-+		 */
-+		if (termios->c_iflag & IGNPAR)
-+			port->ignore_status_mask |= UART_LSR_OE;
-+	}
-+
-+	old_ier = UART_GET_IER(port);
-+
-+        if(UART_ENABLE_MS(port, termios->c_cflag))
-+             old_ier |= UART_IER_MSI;
-+
-+	/* Set baud rate */
-+	quot = quot / 13;
-+	UART_PUT_LCR(port, UART_LCR_DLAB);
-+	UART_PUT_DIV_LO(port, (quot & 0xff));
-+	UART_PUT_DIV_HI(port, ((quot & 0xf00) >> 8));
-+
-+	UART_PUT_LCR(port, uart_mc);
-+//	UART_PUT_LCR(port, 0x07); // ???? it is wired
-+        UART_PUT_MCR(port, 0x08);
-+        UART_PUT_FCR(port, 0x01);
-+	UART_PUT_IER(port, 0x07);
-+
-+	spin_unlock_irqrestore(&port->lock, flags);
-+}
-+
-+static int it8712_startup(struct uart_port *port)
-+{
-+	int retval, i;
-+	unsigned int regs;
-+
-+        //printk("it8712 startup : \n");
-+
-+	/*
-+	 * Use iobase to store a pointer to info. We need this to start a
-+	 * transmission as the tranmittr interrupt is only generated on
-+	 * the transition to the idle state
-+	 */
-+
-+	//	regs = 0;
-+    //    regs |= (IRQ_LPC_MASK);
-+    //    *((volatile unsigned int *)IRQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE))) = regs;
-+
-+	/*
-+	 * Allocate the IRQ
-+	 */
-+	retval = request_irq(port->irq, it8712_int, SA_INTERRUPT, "it8712", port);
-+	if (retval)
-+		return retval;
-+
-+	//printk("Init LPC int...........\n");
-+        /* setup interrupt controller  */
-+        regs = *((volatile unsigned int *)IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
-+        regs &= ~(IRQ_LPC_MASK);
-+        *((volatile unsigned int *)IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))) = regs;
-+        regs = *((volatile unsigned int *)IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
-+        regs &= ~(IRQ_LPC_MASK);
-+        *((volatile unsigned int *)IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))) = regs;
-+        *((volatile unsigned int *)IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_LPC_MASK);
-+
-+	LPC_SERIAL_IRQ_POLARITY = 0x10; //0x10; //0x02;
-+	LPC_SERIAL_IRQ_TRITYPE = 0x10; //0x10;//
-+	LPC_SERIAL_IRQ_ENABLE = 0x10;
-+
-+	LPC_BUS_CTRL = 0xc0;
-+	LPC_SERIAL_IRQ_CTRL = 0xc0;
-+	for(i=0;i<1000;i++) ;
-+	LPC_SERIAL_IRQ_CTRL = 0x80;
-+	/*
-+	 * Finally, enable interrupts. Use the TII interrupt to minimise
-+	 * the number of interrupts generated. If higher performance is
-+	 * needed, consider using the TI interrupt with a suitable FIFO
-+	 * threshold
-+	 */
-+	//UART_PUT_IER(port, (UART_IER_RDI|UART_IER_THRI));
-+	UART_PUT_IER(port, (UART_IER_RDI|UART_IER_THRI|UART_IER_RLSI));//middle
-+
-+	return 0;
-+}
-+
-+static void it8712_shutdown(struct uart_port *port)
-+{
-+        //printk("it8712 shutdown : \n");
-+
-+	/*
-+	 * disable all interrupts, disable the port
-+	 */
-+	UART_PUT_IER(port, 0x0);
-+
-+	/* disable break condition and fifos */
-+//	UART_PUT_MCR(port, (UART_GET_MCR(port)&UART_MCR_MASK));
-+
-+	/*
-+	 * Free the interrupt
-+	 */
-+	free_irq(port->irq, port);
-+}
-+
-+static const char *it8712_type(struct uart_port *port)
-+{
-+	return port->type == PORT_IT8712 ? "IT8712" : NULL;
-+}
-+
-+/*
-+ * Release the memory region(s) being used by 'port'
-+ */
-+static void it8712_release_port(struct uart_port *port)
-+{
-+//        printk("it8712 release port : \n");
-+
-+	release_mem_region(port->mapbase, UART_PORT_SIZE);
-+}
-+
-+/*
-+ * Request the memory region(s) being used by 'port'
-+ */
-+static int it8712_request_port(struct uart_port *port)
-+{
-+	return request_mem_region(port->mapbase, UART_PORT_SIZE,
-+				    "serial_it8712") != NULL ? 0 : -EBUSY;
-+}
-+
-+/*
-+ * Configure/autoconfigure the port.
-+ */
-+static void it8712_config_port(struct uart_port *port, int flags)
-+{
-+
-+	if (flags & UART_CONFIG_TYPE) {
-+		if (it8712_request_port(port) == 0)
-+			port->type = PORT_IT8712;
-+	}
-+}
-+
-+/*
-+ * verify the new serial_struct (for TIOCSSERIAL).
-+ */
-+static int it8712_verify_port(struct uart_port *port, struct serial_struct *ser)
-+{
-+	int ret = 0;
-+
-+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_UART00)
-+		ret = -EINVAL;
-+	if (ser->irq < 0 || ser->irq >= NR_IRQS)
-+		ret = -EINVAL;
-+	if (ser->baud_base < 9600)
-+		ret = -EINVAL;
-+	return ret;
-+}
-+
-+static struct uart_ops it8712_pops = {
-+	.tx_empty	= it8712_tx_empty,
-+	.set_mctrl	= it8712_set_mctrl_null,
-+	.get_mctrl	= it8712_get_mctrl,
-+	.stop_tx	= it8712_stop_tx,
-+	.start_tx	= it8712_start_tx,
-+	.stop_rx	= it8712_stop_rx,
-+	.enable_ms	= it8712_enable_ms,
-+	.break_ctl	= it8712_break_ctl,
-+	.startup	= it8712_startup,
-+	.shutdown	= it8712_shutdown,
-+	.set_termios	= it8712_set_termios,
-+	.type		= it8712_type,
-+	.release_port	= it8712_release_port,
-+	.request_port	= it8712_request_port,
-+	.config_port	= it8712_config_port,
-+	.verify_port	= it8712_verify_port,
-+};
-+
-+#ifdef CONFIG_ARCH_SL2312
-+
-+static struct uart_port it8712_ports[UART_NR] = {
-+	{
-+		membase:	(void *)0,
-+		mapbase:	0,
-+		iotype:		SERIAL_IO_MEM,
-+		irq:		0,
-+		uartclk:	UART_CLK/2,
-+		fifosize:	16,
-+		ops:		&it8712_pops,
-+		flags:		ASYNC_BOOT_AUTOCONF,
-+	}
-+};
-+
-+#endif
-+
-+#ifdef CONFIG_SERIAL_IT8712_CONSOLE
-+#ifdef used_and_not_const_char_pointer
-+static int it8712_console_read(struct uart_port *port, char *s, u_int count)
-+{
-+	unsigned int status;
-+	int c;
-+#ifdef DEBUG
-+	printk("it8712_console_read() called\n");
-+#endif
-+
-+	c = 0;
-+	while (c < count) {
-+		status = UART_GET_LSR(port);
-+ 		if (UART_RX_DATA(status)) {
-+			*s++ = UART_GET_CHAR(port);
-+			c++;
-+		} else {
-+			// nothing more to get, return
-+			return c;
-+		}
-+	}
-+	// return the count
-+	return c;
-+}
-+#endif
-+static void it8712_console_write(struct console *co, const char *s, unsigned count)
-+{
-+#ifdef CONFIG_ARCH_SL2312
-+	struct uart_port *port = it8712_ports + co->index;
-+	unsigned int status, old_ies;
-+	int i;
-+
-+	/*
-+	 *	First save the CR then disable the interrupts
-+	 */
-+	old_ies = UART_GET_IER(port);
-+	//if(old_ies!=7)
-+	//{
-+	//
-+	//	printk("old_ies = %x\n",old_ies);
-+	//	old_ies = 7;
-+	//}
-+	UART_PUT_IER(port,0x0);
-+
-+	/*
-+	 *	Now, do each character
-+	 */
-+	for (i = 0; i < count; i++) {
-+		do {
-+			status = UART_GET_LSR(port);
-+		} while (!UART_TX_READY(status));
-+		UART_PUT_CHAR(port, s[i]);
-+		if (s[i] == '\n') {
-+			do {
-+				status = UART_GET_LSR(port);
-+			} while (!UART_TX_READY(status));
-+			UART_PUT_CHAR(port, '\r');
-+		}
-+	}
-+
-+	/*
-+	 *	Finally, wait for transmitter to become empty
-+	 *	and restore the IES
-+	 */
-+	do {
-+		status = UART_GET_LSR(port);
-+	} while (!(status&UART_LSR_THRE));
-+	UART_PUT_IER(port, old_ies);
-+#endif
-+}
-+
-+static void /*__init*/ it8712_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
-+{
-+	//printk("it8712 console get options : \n");
-+
-+	u_int uart_mc, quot;
-+	uart_mc= UART_GET_MCR(port);
-+
-+	*parity = 'n';
-+	if (uart_mc & UART_LCR_PARITY) {
-+		if (uart_mc & UART_LCR_EVEN)
-+			*parity = 'e';
-+		else
-+			*parity = 'o';
-+	}
-+
-+	switch (uart_mc & UART_LCR_MSK){
-+
-+	case UART_LCR_WLEN5:
-+		*bits = 5;
-+		break;
-+	case UART_LCR_WLEN6:
-+		*bits = 6;
-+		break;
-+	case UART_LCR_WLEN7:
-+		*bits = 7;
-+		break;
-+	case UART_LCR_WLEN8:
-+		*bits = 8;
-+		break;
-+	}
-+	UART_PUT_MCR(port,UART_LCR_DLAB);
-+	quot = UART_GET_DIV_LO(port) | (UART_GET_DIV_HI(port) << 8);
-+	UART_PUT_MCR(port,uart_mc);
-+	*baud = (port->uartclk / (16 *quot));
-+}
-+
-+static int __init it8712_console_setup(struct console *co, char *options)
-+{
-+	struct uart_port *port;
-+	int baud = 38400;
-+	int bits = 8;
-+	int parity = 'n';
-+	int flow= 'n';
-+	int base;//, irq;
-+	int i ;
-+
-+	printk("it8712 console setup : \n");
-+
-+	LPCSetConfig(0, 0x02, 0x01);
-+        LPCSetConfig(LDN_SERIAL1, 0x30, 0x1);
-+        LPCSetConfig(LDN_SERIAL1, 0x23, 0x0);
-+	base = IT8712_IO_BASE;
-+	base += ((LPCGetConfig(LDN_SERIAL1, 0x60) << 8) + LPCGetConfig(LDN_SERIAL1, 0x61));
-+	it8712_ports[0].mapbase = base;
-+	it8712_ports[0].membase = (void *)IO_ADDRESS(base);
-+	it8712_ports[0].irq = IRQ_LPC_OFFSET;
-+    //   	irq = LPCGetConfig(LDN_SERIAL1, 0x70);
-+	//it8712_ports[0].irq += irq;
-+
-+	//printk("it8712 irq is %x \n", it8712_ports[0].irq);
-+
-+	// setup LPC Host 'quiet mode'
-+	//*((volatile unsigned int *)IO_ADDRESS((SL2312_LPC_HOST_BASE+0x04))) |= LPC_HOST_CONTINUE_MODE ;
-+	//for(i=0;i<1000;i++) ;						// delay
-+	//*((volatile unsigned int *)IO_ADDRESS((SL2312_LPC_HOST_BASE+0x04))) &= ~(LPC_HOST_CONTINUE_MODE) ;
-+	LPC_BUS_CTRL = 0xc0;
-+	LPC_SERIAL_IRQ_CTRL = 0xc0;
-+	for(i=0;i<1000;i++) ;
-+	LPC_SERIAL_IRQ_CTRL = 0x80;
-+
-+#ifdef CONFIG_ARCH_SL2312
-+	/*
-+	 * Check whether an invalid uart number has been specified, and
-+	 * if so, search for the first available port that does have
-+	 * console support.
-+	 */
-+	port = uart_get_console(it8712_ports,IT8712_NO_PORTS,co);
-+#else
-+	return -ENODEV;
-+#endif
-+
-+	if (options)
-+		uart_parse_options(options, &baud, &parity, &bits, &flow);
-+	else
-+		it8712_console_get_options(port, &baud, &parity, &bits);
-+
-+	return uart_set_options(port, co, baud, parity, bits, flow);
-+}
-+
-+extern struct uart_driver it8712_reg;
-+static struct console it8712_console = {
-+	.name           = SERIAL_IT8712_NAME,
-+	.write		= it8712_console_write,
-+	.device		= uart_console_device,
-+        .setup          = it8712_console_setup,
-+	.flags		= CON_PRINTBUFFER,
-+	.index		= 0,
-+        .data           = &it8712_reg,
-+};
-+
-+static int __init it8712_console_init(void)
-+{
-+	register_console(&it8712_console);
-+        return 0;
-+}
-+
-+console_initcall(it8712_console_init);
-+
-+#define IT8712_CONSOLE	&it8712_console
-+#else
-+#define IT8712_CONSOLE	NULL
-+#endif
-+
-+static struct uart_driver it8712_reg = {
-+	.owner                  = NULL,
-+	.driver_name		= SERIAL_IT8712_NAME,
-+	.dev_name		= SERIAL_IT8712_NAME,
-+        .major                  = SERIAL_IT8712_MAJOR,
-+	.minor			= SERIAL_IT8712_MINOR,
-+	.nr			= UART_NR,
-+	.cons			= IT8712_CONSOLE,
-+};
-+
-+static int __init it8712_init(void)
-+{
-+        int result;
-+	//printk("serial_it8712: it871212_init \n");
-+
-+
-+        result = uart_register_driver(&it8712_reg);
-+        if(result)
-+             return result;
-+	result = uart_add_one_port(&it8712_reg, &it8712_ports[0]);
-+
-+        return result;
-+
-+}
-+
-+
-+__initcall(it8712_init);
---- /dev/null
-+++ b/drivers/serial/it8712.h
-@@ -0,0 +1,135 @@
-+#define UART_RX		0	/* In:  Receive buffer (DLAB=0) */
-+#define UART_TX		0	/* Out: Transmit buffer (DLAB=0) */
-+#define UART_DLL	0	/* Out: Divisor Latch Low (DLAB=1) */
-+#define UART_TRG	0	/* (LCR=BF) FCTR bit 7 selects Rx or Tx
-+				 * In: Fifo count
-+				 * Out: Fifo custom trigger levels
-+				 * XR16C85x only */
-+
-+#define UART_DLM	1	/* Out: Divisor Latch High (DLAB=1) */
-+#define UART_IER	1	/* Out: Interrupt Enable Register */
-+#define UART_FCTR	1	/* (LCR=BF) Feature Control Register
-+				 * XR16C85x only */
-+
-+#define UART_IIR	2	/* In:  Interrupt ID Register */
-+#define UART_FCR	2	/* Out: FIFO Control Register */
-+#define UART_EFR	2	/* I/O: Extended Features Register */
-+				/* (DLAB=1, 16C660 only) */
-+
-+#define UART_LCR	3	/* Out: Line Control Register */
-+#define UART_MCR	4	/* Out: Modem Control Register */
-+#define UART_LSR	5	/* In:  Line Status Register */
-+#define UART_MSR	6	/* In:  Modem Status Register */
-+#define UART_SCR	7	/* I/O: Scratch Register */
-+#define UART_EMSR	7	/* (LCR=BF) Extended Mode Select Register
-+				 * FCTR bit 6 selects SCR or EMSR
-+				 * XR16c85x only */
-+
-+/*
-+ * These are the definitions for the FIFO Control Register
-+ * (16650 only)
-+ */
-+#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
-+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
-+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
-+#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
-+#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
-+#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
-+#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
-+#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
-+/* 16650 redefinitions */
-+#define UART_FCR6_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 1 */
-+#define UART_FCR6_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 4 */
-+#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
-+#define UART_FCR6_R_TRIGGER_28	0xC0 /* Mask for receive trigger set at 14 */
-+#define UART_FCR6_T_TRIGGER_16	0x00 /* Mask for transmit trigger set at 16 */
-+#define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
-+#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
-+#define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
-+/* TI 16750 definitions */
-+#define UART_FCR7_64BYTE	0x20 /* Go into 64 byte mode */
-+
-+/*
-+ * These are the definitions for the Line Control Register
-+ *
-+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
-+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
-+ */
-+#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */
-+#define UART_LCR_SBC	0x40	/* Set break control */
-+#define UART_LCR_SPAR	0x20	/* Stick parity (?) */
-+#define UART_LCR_EPAR	0x10	/* Even parity select */
-+#define UART_LCR_PARITY	0x08	/* Parity Enable */
-+#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-+#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */
-+#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */
-+#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */
-+#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits */
-+#define UART_LCR_EVEN   0x18    /* Even parity */
-+#define UART_LCR_ODD    0x08    /* Odd parity */
-+#define UART_LCR_MSK    0x03
-+/*
-+ * These are the definitions for the Line Status Register
-+ */
-+#define UART_LSR_DE     0x80    /* FIFO Data Error */
-+#define UART_LSR_TEMT	0x40	/* Transmitter empty */
-+#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
-+#define UART_LSR_BI	0x10	/* Break interrupt indicator */
-+#define UART_LSR_FE	0x08	/* Frame error indicator */
-+#define UART_LSR_PE	0x04	/* Parity error indicator */
-+#define UART_LSR_OE	0x02	/* Overrun error indicator */
-+#define UART_LSR_DR	0x01	/* Receiver data ready */
-+
-+/*
-+ * These are the definitions for the Interrupt Identification Register
-+ */
-+#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
-+#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
-+
-+#define UART_IIR_MSI	0x00	/* Modem status interrupt */
-+#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
-+#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
-+#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
-+#define UART_IIR_RCTO	0x0c	/* Receiver character timeout interrupt */
-+/*
-+ * These are the definitions for the Interrupt Enable Register
-+ */
-+#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
-+#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
-+#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
-+#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
-+/*
-+ * Sleep mode for ST16650 and TI16750.
-+ * Note that for 16650, EFR-bit 4 must be selected as well.
-+ */
-+#define UART_IERX_SLEEP  0x10	/* Enable sleep mode */
-+
-+/*
-+ * These are the definitions for the Modem Control Register
-+ */
-+#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
-+#define UART_MCR_OUT2	0x08	/* Out2 complement */
-+#define UART_MCR_OUT1	0x04	/* Out1 complement */
-+#define UART_MCR_RTS	0x02	/* RTS complement */
-+#define UART_MCR_DTR	0x01	/* DTR complement */
-+
-+/*
-+ * These are the definitions for the Modem Status Register
-+ */
-+#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
-+#define UART_MSR_RI	0x40	/* Ring Indicator */
-+#define UART_MSR_DSR	0x20	/* Data Set Ready */
-+#define UART_MSR_CTS	0x10	/* Clear to Send */
-+#define UART_MSR_DDCD	0x08	/* Delta DCD */
-+#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
-+#define UART_MSR_DDSR	0x02	/* Delta DSR */
-+#define UART_MSR_DCTS	0x01	/* Delta CTS */
-+#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */
-+
-+#define UART_PARITY_NONE	0x00
-+#define UART_PARITY_ODD		0x01
-+#define UART_PARITY_EVEN	0x02
-+
-+
-+
---- /dev/null
-+++ b/drivers/serial/serial_it8712.c
-@@ -0,0 +1,876 @@
-+/*
-+ *  linux/drivers/char/serial_uart00.c
-+ *
-+ *  Driver for UART00 serial ports
-+ *
-+ *  Based on drivers/char/serial_amba.c, by ARM Limited &
-+ *                                          Deep Blue Solutions Ltd.
-+ *  Copyright 2001 Altera Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ *
-+ *  $Id: serial_it8712.c,v 1.1.1.1 2006/04/03 08:41:00 amos_lee Exp $
-+ *
-+ */
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#if defined(CONFIG_SERIAL_IT8712_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-+#define SUPPORT_SYSRQ
-+#endif
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include "serial_it8712.h"
-+
-+//#define DEBUG           1
-+#define UART_NR		1
-+
-+#define SERIAL_IT8712_NAME	"ttySI"
-+#define SERIAL_IT8712_MAJOR	204
-+#define SERIAL_IT8712_MINOR	41      /* Temporary - will change in future */
-+#define SERIAL_IT8712_NR	UART_NR
-+#define UART_PORT_SIZE 0x50
-+
-+#define CALLOUT_IT8712_NAME	"cuaslI"
-+#define CALLOUT_IT8712_MAJOR	205
-+#define CALLOUT_IT8712_MINOR	41      /* Temporary - will change in future */
-+#define CALLOUT_IT8712_NR	UART_NR
-+#define LPC_HOST_CONTINUE_MODE	0x00000040
-+
-+#define IT8712_NO_PORTS         UART_NR
-+
-+static struct tty_driver normal, callout;
-+static struct tty_struct *it8712_table[UART_NR];
-+static struct termios *it8712_termios[UART_NR], *it8712_termios_locked[UART_NR];
-+static struct console it8712_console;
-+
-+#define IT8712_ISR_PASS_LIMIT	256
-+
-+/*
-+ * Access macros for the SL2312 UARTs
-+ */
-+#define UART_GET_INT_STATUS(p)	(inb(((p)->membase+UART_IIR)) & 0x0F)  // interrupt identification
-+#define UART_PUT_IER(p, c)      outb(c,((p)->membase+UART_IER))         // interrupt enable
-+#define UART_GET_IER(p)         inb(((p)->membase+UART_IER))
-+#define UART_PUT_CHAR(p, c)     outb(c,((p)->membase+UART_TX))         // transmitter holding
-+#define UART_GET_CHAR(p)        inb(((p)->membase+UART_RX))            // receive buffer
-+#define UART_GET_LSR(p)         inb(((p)->membase+UART_LSR))            // line status
-+#define UART_GET_MSR(p)         inb(((p)->membase+UART_MSR))            // modem status
-+#define UART_GET_MCR(p)         inb(((p)->membase+UART_MCR))            // modem control
-+#define UART_PUT_MCR(p, c)      outb(c,((p)->membase+UART_MCR))
-+#define UART_GET_LCR(p)         inb(((p)->membase+UART_LCR))       // mode control
-+#define UART_PUT_LCR(p, c)      outb(c,((p)->membase+UART_LCR))
-+#define UART_PUT_FCR(p, c)      outb(c,((p)->membase+UART_FCR))       // fifo control
-+#define UART_GET_DIV_HI(p)	inb(((p)->membase+UART_DLM))
-+#define UART_PUT_DIV_HI(p, c)	outb(c,((p)->membase+UART_DLM))
-+#define UART_GET_DIV_LO(p)	inb(((p)->membase+UART_DLL))
-+#define UART_PUT_DIV_LO(p, c)	outb(c,((p)->membase+UART_DLL))
-+#define UART_PUT_MDR(p, c)      outb(c,UART_MDR((p)->membase))
-+#define UART_RX_DATA(s)		((s) & UART_LSR_DR)
-+#define UART_TX_READY(s)	((s) & UART_LSR_THRE)
-+
-+static void it8712_stop_tx(struct uart_port *port, u_int from_tty)
-+{
-+        unsigned int reg;
-+
-+//        printk("it8712 stop tx : \n");
-+        reg = UART_GET_IER(port);
-+        reg &= ~(UART_IER_THRI);
-+	UART_PUT_IER(port, reg);
-+}
-+
-+static void it8712_stop_rx(struct uart_port *port)
-+{
-+        unsigned int reg;
-+
-+//        printk("it8712 stop rx : \n");
-+        reg = UART_GET_IER(port);
-+        reg &= ~(UART_IER_RDI);
-+	UART_PUT_IER(port, reg);
-+
-+}
-+
-+static void it8712_enable_ms(struct uart_port *port)
-+{
-+        unsigned int reg;
-+
-+//        printk("it8712 enable ms : \n");
-+
-+        reg = UART_GET_IER(port);
-+        reg |= (UART_IER_MSI);
-+	UART_PUT_IER(port, reg);
-+
-+}
-+
-+static void
-+it8712_rx_chars(struct uart_info *info, struct pt_regs *regs)
-+{
-+	struct tty_struct *tty = info->tty;
-+	unsigned int status, mask, ch, flg, ignored = 0;
-+	struct uart_port *port = info->port;
-+
-+ //       printk("it8712_rx_chars : \n");
-+	status = UART_GET_LSR(port);
-+	while (UART_RX_DATA(status)) {
-+
-+		/*
-+		 * We need to read rds before reading the
-+		 * character from the fifo
-+		 */
-+		ch = UART_GET_CHAR(port);
-+		port->icount.rx++;
-+
-+		if (tty->flip.count >= TTY_FLIPBUF_SIZE)
-+			goto ignore_char;
-+
-+		flg = TTY_NORMAL;
-+
-+		/*
-+		 * Note that the error handling code is
-+		 * out of the main execution path
-+		 */
-+
-+		if (status & (UART_LSR_OE|UART_LSR_PE|UART_LSR_FE|UART_LSR_BI|UART_LSR_DE))
-+			goto handle_error;
-+		if (uart_handle_sysrq_char(info, ch, regs))
-+			goto ignore_char;
-+
-+	error_return:
-+		*tty->flip.flag_buf_ptr++ = flg;
-+		*tty->flip.char_buf_ptr++ = ch;
-+		tty->flip.count++;
-+	ignore_char:
-+		status = UART_GET_LSR(port);
-+	} // end of while
-+out:
-+	tty_flip_buffer_push(tty);
-+	return;
-+
-+handle_error:
-+	if (status & UART_LSR_BI) {
-+		status &= ~(UART_LSR_FE);
-+		port->icount.brk++;
-+
-+#ifdef SUPPORT_SYSRQ
-+		if (uart_handle_break(info, &it8712_console))
-+			goto ignore_char;
-+#endif
-+	} else if (status & UART_LSR_PE)
-+		port->icount.parity++;
-+	else if (status & UART_LSR_FE)
-+		port->icount.frame++;
-+
-+	if (status & UART_LSR_OE)
-+		port->icount.overrun++;
-+
-+	if (status & port->ignore_status_mask) {
-+		if (++ignored > 100)
-+			goto out;
-+		goto ignore_char;
-+	}
-+
-+	mask = status & port->read_status_mask;
-+
-+	if (mask & UART_LSR_BI)
-+		flg = TTY_BREAK;
-+	else if (mask & UART_LSR_PE)
-+		flg = TTY_PARITY;
-+	else if (mask & UART_LSR_FE)
-+		flg = TTY_FRAME;
-+
-+	if (status & UART_LSR_OE) {
-+		/*
-+		 * CHECK: does overrun affect the current character?
-+		 * ASSUMPTION: it does not.
-+		 */
-+		*tty->flip.flag_buf_ptr++ = flg;
-+		*tty->flip.char_buf_ptr++ = ch;
-+		tty->flip.count++;
-+		if (tty->flip.count >= TTY_FLIPBUF_SIZE)
-+			goto ignore_char;
-+		ch = 0;
-+		flg = TTY_OVERRUN;
-+	}
-+#ifdef SUPPORT_SYSRQ
-+	info->sysrq = 0;
-+#endif
-+	goto error_return;
-+}
-+
-+static void it8712_tx_chars(struct uart_info *info)
-+{
-+	int count;
-+	struct uart_port *port=info->port;
-+
-+	if (port->x_char) {
-+		while(!(UART_GET_LSR(port)&UART_LSR_THRE));
-+		UART_PUT_CHAR(port, port->x_char);
-+		port->icount.tx++;
-+		port->x_char = 0;
-+
-+		return;
-+	}
-+	if (info->xmit.head == info->xmit.tail
-+	    || info->tty->stopped
-+	    || info->tty->hw_stopped) {
-+		it8712_stop_tx(info->port, 0);
-+		return;
-+	}
-+
-+	count = port->fifosize >> 1;
-+	do {
-+		while(!(UART_GET_LSR(port)&UART_LSR_THRE));
-+		UART_PUT_CHAR(port, info->xmit.buf[info->xmit.tail]);
-+		info->xmit.tail = (info->xmit.tail + 1) & (UART_XMIT_SIZE - 1);
-+		port->icount.tx++;
-+		if (info->xmit.head == info->xmit.tail)
-+			break;
-+	} while (--count > 0);
-+
-+	if (CIRC_CNT(info->xmit.head,
-+		     info->xmit.tail,
-+		     UART_XMIT_SIZE) < WAKEUP_CHARS)
-+		uart_event(info, EVT_WRITE_WAKEUP);
-+
-+	if (info->xmit.head == info->xmit.tail)
-+		it8712_stop_tx(info->port, 0);
-+}
-+
-+static void it8712_start_tx(struct uart_port *port, u_int nonempty, u_int from_tty)
-+{
-+        unsigned int reg;
-+	struct uart_info *info=(struct uart_info*)(port->iobase);
-+
-+//        printk("it8712 start tx : \n");
-+        reg = UART_GET_IER(port);
-+        reg |= (UART_IER_THRI);
-+	UART_PUT_IER(port, reg);
-+	it8712_tx_chars(info);
-+}
-+
-+static void it8712_modem_status(struct uart_info *info)
-+{
-+	unsigned int status;
-+	struct uart_icount *icount = &info->port->icount;
-+
-+//        printk("it8712 modem status : \n");
-+
-+	status = UART_GET_MSR(info->port);
-+
-+	if (!(status & (UART_MSR_DCTS | UART_MSR_DDSR |
-+		       UART_MSR_TERI | UART_MSR_DDCD)))
-+		return;
-+
-+	if (status & UART_MSR_DCD) {
-+		icount->dcd++;
-+#ifdef CONFIG_HARD_PPS
-+		if ((info->flags & ASYNC_HARDPPS_CD) &&
-+		    (status & UART_MSR_DCD_MSK))
-+			hardpps();
-+#endif
-+		if (info->flags & ASYNC_CHECK_CD) {
-+			if (status & UART_MSR_DCD)
-+				wake_up_interruptible(&info->open_wait);
-+			else if (!((info->flags & ASYNC_CALLOUT_ACTIVE) &&
-+				   (info->flags & ASYNC_CALLOUT_NOHUP))) {
-+				if (info->tty)
-+					tty_hangup(info->tty);
-+			}
-+		}
-+	}
-+
-+	if (status & UART_MSR_DDSR)
-+		icount->dsr++;
-+
-+	if (status & UART_MSR_DCTS) {
-+		icount->cts++;
-+
-+		if (info->flags & ASYNC_CTS_FLOW) {
-+			status &= UART_MSR_CTS;
-+
-+			if (info->tty->hw_stopped) {
-+				if (status) {
-+					info->tty->hw_stopped = 0;
-+					info->ops->start_tx(info->port, 1, 0);
-+					uart_event(info, EVT_WRITE_WAKEUP);
-+				}
-+			} else {
-+				if (!status) {
-+					info->tty->hw_stopped = 1;
-+					info->ops->stop_tx(info->port, 0);
-+				}
-+			}
-+		}
-+	}
-+	wake_up_interruptible(&info->delta_msr_wait);
-+
-+}
-+
-+static void it8712_int(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+	struct uart_info *info = dev_id;
-+	unsigned int status, pass_counter = 0;
-+
-+	status = UART_GET_INT_STATUS(info->port);
-+	do {
-+//		     printk("it8712_int: status %x \n", status);
-+		switch(status)
-+		{
-+		   case UART_IIR_RDI:
-+		   case UART_IIR_RLSI:
-+		   case UART_IIR_RCTO:
-+			it8712_rx_chars(info, regs);
-+		   break;
-+		   case UART_IIR_THRI:
-+			it8712_tx_chars(info);
-+		   break;
-+		   case UART_IIR_MSI:
-+			it8712_modem_status(info);
-+		   break;
-+		   default:
-+		   break;
-+		}
-+		if (pass_counter++ > IT8712_ISR_PASS_LIMIT)
-+			break;
-+
-+		status = UART_GET_INT_STATUS(info->port);
-+	} while (status);
-+}
-+
-+static u_int it8712_tx_empty(struct uart_port *port)
-+{
-+//        printk("it8712 tx empty : \n");
-+
-+	return ((UART_GET_LSR(port) & UART_LSR_THRE)? TIOCSER_TEMT : 0);
-+}
-+
-+static u_int it8712_get_mctrl(struct uart_port *port)
-+{
-+	unsigned int result = 0;
-+	unsigned int status;
-+
-+//        printk("it8712 get mctrl : \n");
-+
-+	status = UART_GET_MSR(port);
-+	if (status & UART_MSR_DCD)
-+		result |= TIOCM_CAR;
-+	if (status & UART_MSR_DSR)
-+		result |= TIOCM_DSR;
-+	if (status & UART_MSR_CTS)
-+		result |= TIOCM_CTS;
-+	if (status & UART_MSR_RI)
-+		result |= TIOCM_RI;
-+
-+	return result;
-+}
-+
-+static void it8712_set_mctrl_null(struct uart_port *port, u_int mctrl)
-+{
-+}
-+
-+static void it8712_break_ctl(struct uart_port *port, int break_state)
-+{
-+	unsigned int lcr;
-+
-+//        printk("it8712 break ctl : \n");
-+
-+	lcr = UART_GET_LCR(port);
-+	if (break_state == -1)
-+		lcr |= UART_LCR_SBC;
-+	else
-+		lcr &= ~UART_LCR_SBC;
-+	UART_PUT_LCR(port, lcr);
-+}
-+
-+static inline u_int uart_calculate_quot(struct uart_info *info, u_int baud)
-+{
-+	u_int quot;
-+
-+	/* Special case: B0 rate */
-+	if (!baud)
-+		baud = 9600;
-+
-+	quot = (info->port->uartclk/(16 * baud)) ;
-+
-+	return quot;
-+}
-+static void it8712_change_speed(struct uart_port *port, u_int cflag, u_int iflag, u_int quot)
-+{
-+	u_int uart_mc=0, old_ier;
-+	unsigned long flags;
-+
-+#ifdef DEBUG
-+	printk("it8712_set_cflag(0x%x) called\n", cflag);
-+#endif
-+
-+
-+	/* byte size and parity */
-+	switch (cflag & CSIZE) {
-+	case CS5: uart_mc = UART_LCR_WLEN5; break;
-+	case CS6: uart_mc = UART_LCR_WLEN6; break;
-+	case CS7: uart_mc = UART_LCR_WLEN7; break;
-+	default:  uart_mc = UART_LCR_WLEN8; break; // CS8
-+	}
-+	if (cflag & CSTOPB)
-+		uart_mc|= UART_LCR_STOP;
-+	if (cflag & PARENB) {
-+		uart_mc |= UART_LCR_EVEN;
-+		if (!(cflag & PARODD))
-+			uart_mc |= UART_LCR_ODD;
-+	}
-+
-+	port->read_status_mask = UART_LSR_OE;
-+	if (iflag & INPCK)
-+		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
-+	if (iflag & (BRKINT | PARMRK))
-+		port->read_status_mask |= UART_LSR_BI;
-+
-+	/*
-+	 * Characters to ignore
-+	 */
-+	port->ignore_status_mask = 0;
-+	if (iflag & IGNPAR)
-+		port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE;
-+	if (iflag & IGNBRK) {
-+		port->ignore_status_mask |= UART_LSR_BI;
-+		/*
-+		 * If we're ignoring parity and break indicators,
-+		 * ignore overruns to (for real raw support).
-+		 */
-+		if (iflag & IGNPAR)
-+			port->ignore_status_mask |= UART_LSR_OE;
-+	}
-+
-+	/* first, disable everything */
-+	save_flags(flags); cli();
-+	old_ier = UART_GET_IER(port);
-+
-+	if ((port->flags & ASYNC_HARDPPS_CD) ||
-+	    (cflag & CRTSCTS) || !(cflag & CLOCAL))
-+		old_ier |= UART_IER_MSI;
-+
-+	/* Set baud rate */
-+	quot = quot / 13;
-+	UART_PUT_LCR(port, UART_LCR_DLAB);
-+	UART_PUT_DIV_LO(port, (quot & 0xff));
-+	UART_PUT_DIV_HI(port, ((quot & 0xf00) >> 8));
-+
-+	UART_PUT_LCR(port, uart_mc);
-+//	UART_PUT_LCR(port, 0x07); // ???? it is wired
-+        UART_PUT_MCR(port, 0x08);
-+        UART_PUT_FCR(port, 0x01);
-+	UART_PUT_IER(port, 0x05);
-+
-+	restore_flags(flags);
-+}
-+
-+static int it8712_startup(struct uart_port *port, struct uart_info *info)
-+{
-+	int retval;
-+	unsigned int regs;
-+
-+//        printk("it8712 startup : \n");
-+
-+	/*
-+	 * Use iobase to store a pointer to info. We need this to start a
-+	 * transmission as the tranmittr interrupt is only generated on
-+	 * the transition to the idle state
-+	 */
-+
-+	port->iobase=(u_int)info;
-+
-+	/*
-+	 * Allocate the IRQ
-+	 */
-+	retval = request_irq(port->irq, it8712_int, SA_INTERRUPT, "it8712", info);
-+	if (retval)
-+		return retval;
-+
-+        /* setup interrupt controller  */
-+        regs = *((volatile unsigned int *)IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
-+        regs |= (IRQ_SERIRQ0_MASK);
-+        *((volatile unsigned int *)IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))) = regs;
-+        regs = *((volatile unsigned int *)IRQ_LEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
-+        regs &= ~(IRQ_SERIRQ0_MASK);
-+        *((volatile unsigned int *)IRQ_LEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))) = regs;
-+        *((volatile unsigned int *)IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_SERIRQ0_MASK);
-+
-+	/*
-+	 * Finally, enable interrupts. Use the TII interrupt to minimise
-+	 * the number of interrupts generated. If higher performance is
-+	 * needed, consider using the TI interrupt with a suitable FIFO
-+	 * threshold
-+	 */
-+	UART_PUT_IER(port, (UART_IER_RDI|UART_IER_THRI));
-+
-+	return 0;
-+}
-+
-+static void it8712_shutdown(struct uart_port *port, struct uart_info *info)
-+{
-+//        printk("it8712 shutdown : \n");
-+
-+	/*
-+	 * disable all interrupts, disable the port
-+	 */
-+	UART_PUT_IER(port, 0x0);
-+
-+	/* disable break condition and fifos */
-+//	UART_PUT_MCR(port, (UART_GET_MCR(port)&UART_MCR_MASK));
-+
-+	/*
-+	 * Free the interrupt
-+	 */
-+	free_irq(port->irq, info);
-+}
-+
-+static const char *it8712_type(struct uart_port *port)
-+{
-+	return port->type == PORT_IT8712 ? "IT8712" : NULL;
-+}
-+
-+/*
-+ * Release the memory region(s) being used by 'port'
-+ */
-+static void it8712_release_port(struct uart_port *port)
-+{
-+//        printk("it8712 release port : \n");
-+
-+	release_mem_region(port->mapbase, UART_PORT_SIZE);
-+}
-+
-+/*
-+ * Request the memory region(s) being used by 'port'
-+ */
-+static int it8712_request_port(struct uart_port *port)
-+{
-+	return request_mem_region(port->mapbase, UART_PORT_SIZE,
-+				    "serial_it8712") != NULL ? 0 : -EBUSY;
-+}
-+
-+/*
-+ * Configure/autoconfigure the port.
-+ */
-+static void it8712_config_port(struct uart_port *port, int flags)
-+{
-+
-+	if (flags & UART_CONFIG_TYPE) {
-+		if (it8712_request_port(port) == 0)
-+			port->type = PORT_IT8712;
-+	}
-+}
-+
-+/*
-+ * verify the new serial_struct (for TIOCSSERIAL).
-+ */
-+static int it8712_verify_port(struct uart_port *port, struct serial_struct *ser)
-+{
-+	int ret = 0;
-+
-+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_UART00)
-+		ret = -EINVAL;
-+	if (ser->irq < 0 || ser->irq >= NR_IRQS)
-+		ret = -EINVAL;
-+	if (ser->baud_base < 9600)
-+		ret = -EINVAL;
-+	return ret;
-+}
-+
-+static struct uart_ops it8712_pops = {
-+	tx_empty:	it8712_tx_empty,
-+	set_mctrl:	it8712_set_mctrl_null,
-+	get_mctrl:	it8712_get_mctrl,
-+	stop_tx:	it8712_stop_tx,
-+	start_tx:	it8712_start_tx,
-+	stop_rx:	it8712_stop_rx,
-+	enable_ms:	it8712_enable_ms,
-+	break_ctl:	it8712_break_ctl,
-+	startup:	it8712_startup,
-+	shutdown:	it8712_shutdown,
-+	change_speed:	it8712_change_speed,
-+	type:		it8712_type,
-+	release_port:	it8712_release_port,
-+	request_port:	it8712_request_port,
-+	config_port:	it8712_config_port,
-+	verify_port:	it8712_verify_port,
-+};
-+
-+#ifdef CONFIG_ARCH_SL2312
-+
-+static struct uart_port it8712_ports[UART_NR] = {
-+	{
-+		membase:	(void *)0,
-+		mapbase:	0,
-+		iotype:		SERIAL_IO_MEM,
-+		irq:		0,
-+		uartclk:	UART_CLK/2,
-+		fifosize:	16,
-+		ops:		&it8712_pops,
-+		flags:		ASYNC_BOOT_AUTOCONF,
-+	}
-+};
-+
-+#endif
-+
-+#ifdef CONFIG_SERIAL_IT8712_CONSOLE
-+#ifdef used_and_not_const_char_pointer
-+static int it8712_console_read(struct uart_port *port, char *s, u_int count)
-+{
-+	unsigned int status;
-+	int c;
-+#ifdef DEBUG
-+	printk("it8712_console_read() called\n");
-+#endif
-+
-+	c = 0;
-+	while (c < count) {
-+		status = UART_GET_LSR(port);
-+ 		if (UART_RX_DATA(status)) {
-+			*s++ = UART_GET_CHAR(port);
-+			c++;
-+		} else {
-+			// nothing more to get, return
-+			return c;
-+		}
-+	}
-+	// return the count
-+	return c;
-+}
-+#endif
-+static void it8712_console_write(struct console *co, const char *s, unsigned count)
-+{
-+#ifdef CONFIG_ARCH_SL2312
-+	struct uart_port *port = it8712_ports + co->index;
-+	unsigned int status, old_ies;
-+	int i;
-+
-+	/*
-+	 *	First save the CR then disable the interrupts
-+	 */
-+	old_ies = UART_GET_IER(port);
-+	UART_PUT_IER(port,0x0);
-+
-+	/*
-+	 *	Now, do each character
-+	 */
-+	for (i = 0; i < count; i++) {
-+		do {
-+			status = UART_GET_LSR(port);
-+		} while (!UART_TX_READY(status));
-+		UART_PUT_CHAR(port, s[i]);
-+		if (s[i] == '\n') {
-+			do {
-+				status = UART_GET_LSR(port);
-+			} while (!UART_TX_READY(status));
-+			UART_PUT_CHAR(port, '\r');
-+		}
-+	}
-+
-+	/*
-+	 *	Finally, wait for transmitter to become empty
-+	 *	and restore the IES
-+	 */
-+	do {
-+		status = UART_GET_LSR(port);
-+	} while (!(status&UART_LSR_THRE));
-+	UART_PUT_IER(port, old_ies);
-+#endif
-+}
-+
-+static kdev_t it8712_console_device(struct console *co)
-+{
-+	return MKDEV(SERIAL_IT8712_MAJOR, SERIAL_IT8712_MINOR + co->index);
-+}
-+
-+static int it8712_console_wait_key(struct console *co)
-+{
-+#ifdef CONFIG_ARCH_SL2312
-+	struct uart_port *port = (it8712_ports + co->index);
-+	unsigned int status;
-+
-+	do {
-+		status = UART_GET_LSR(port);
-+	} while (!UART_RX_DATA(status));
-+	return UART_GET_CHAR(port);
-+#else
-+	return 0;
-+#endif
-+}
-+
-+static void /*__init*/ it8712_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
-+{
-+	printk("it8712 console get options : \n");
-+
-+	u_int uart_mc, quot;
-+	uart_mc= UART_GET_MCR(port);
-+
-+	*parity = 'n';
-+	if (uart_mc & UART_LCR_PARITY) {
-+		if (uart_mc & UART_LCR_EVEN)
-+			*parity = 'e';
-+		else
-+			*parity = 'o';
-+	}
-+
-+	switch (uart_mc & UART_LCR_MSK){
-+
-+	case UART_LCR_WLEN5:
-+		*bits = 5;
-+		break;
-+	case UART_LCR_WLEN6:
-+		*bits = 6;
-+		break;
-+	case UART_LCR_WLEN7:
-+		*bits = 7;
-+		break;
-+	case UART_LCR_WLEN8:
-+		*bits = 8;
-+		break;
-+	}
-+	UART_PUT_MCR(port,UART_LCR_DLAB);
-+	quot = UART_GET_DIV_LO(port) | (UART_GET_DIV_HI(port) << 8);
-+	UART_PUT_MCR(port,uart_mc);
-+	*baud = (port->uartclk / (16 *quot));
-+}
-+
-+static int __init it8712_console_setup(struct console *co, char *options)
-+{
-+	struct uart_port *port;
-+	int baud = 38400;
-+	int bits = 8;
-+	int parity = 'n';
-+	int flow= 'n';
-+	int base, irq;
-+	int i ;
-+
-+//	printk("it8712 console setup : \n");
-+
-+	LPCSetConfig(0, 0x02, 0x01);
-+        LPCSetConfig(LDN_SERIAL1, 0x30, 0x1);
-+        LPCSetConfig(LDN_SERIAL1, 0x23, 0x0);
-+	base = IT8712_IO_BASE;
-+	base += ((LPCGetConfig(LDN_SERIAL1, 0x60) << 8) + LPCGetConfig(LDN_SERIAL1, 0x61));
-+	it8712_ports[0].mapbase = base;
-+	it8712_ports[0].membase = IO_ADDRESS(base);
-+	it8712_ports[0].irq = IRQ_SERIRQ0_OFFSET;
-+       	irq = LPCGetConfig(LDN_SERIAL1, 0x70);
-+	it8712_ports[0].irq += irq;
-+
-+	printk("it8712 irq is %x %x \n", it8712_ports[0].irq, irq);
-+
-+	// setup LPC Host 'quiet mode'
-+	*((volatile unsigned int *)IO_ADDRESS((SL2312_LPC_HOST_BASE+0x04))) |= LPC_HOST_CONTINUE_MODE ;
-+	for(i=0;i<1000;i++) ;						// delay
-+	*((volatile unsigned int *)IO_ADDRESS((SL2312_LPC_HOST_BASE+0x04))) &= ~(LPC_HOST_CONTINUE_MODE) ;
-+
-+#ifdef CONFIG_ARCH_SL2312
-+	/*
-+	 * Check whether an invalid uart number has been specified, and
-+	 * if so, search for the first available port that does have
-+	 * console support.
-+	 */
-+	port = uart_get_console(it8712_ports,IT8712_NO_PORTS,co);
-+#else
-+	return -ENODEV;
-+#endif
-+
-+	if (options)
-+		uart_parse_options(options, &baud, &parity, &bits, &flow);
-+	else
-+		it8712_console_get_options(port, &baud, &parity, &bits);
-+
-+	return uart_set_options(port, co, baud, parity, bits, flow);
-+}
-+
-+static struct console it8712_console = {
-+	name:           SERIAL_IT8712_NAME,
-+	write:		it8712_console_write,
-+#ifdef used_and_not_const_char_pointer
-+	read:		it8712_console_read,
-+#endif
-+	device:		it8712_console_device,
-+//	wait_key:	it8712_console_wait_key,
-+	setup:		it8712_console_setup,
-+	flags:		(CON_PRINTBUFFER|CON_ENABLED),
-+	index:		-1,
-+};
-+
-+void __init it8712_console_init(void)
-+{
-+	register_console(&it8712_console);
-+}
-+
-+#define IT8712_CONSOLE	&it8712_console
-+#else
-+#define IT8712_CONSOLE	NULL
-+#endif
-+
-+static struct uart_driver it8712_reg = {
-+	owner:                  NULL,
-+	normal_major:		SERIAL_IT8712_MAJOR,
-+	normal_name:		SERIAL_IT8712_NAME,
-+	normal_driver:		&normal,
-+	callout_major:		CALLOUT_IT8712_MAJOR,
-+	callout_name:		CALLOUT_IT8712_NAME,
-+	callout_driver:		&callout,
-+	table:			it8712_table,
-+	termios:		it8712_termios,
-+	termios_locked:		it8712_termios_locked,
-+	minor:			SERIAL_IT8712_MINOR,
-+	nr:			UART_NR,
-+#ifdef CONFIG_ARCH_SL2312
-+	port:			it8712_ports,
-+#endif
-+	state:			NULL,
-+	cons:			IT8712_CONSOLE,
-+};
-+
-+static int __init it8712_init(void)
-+{
-+//	printk("serial_it8712: it871212_init \n");
-+
-+	return uart_register_driver(&it8712_reg);
-+}
-+
-+
-+__initcall(it8712_init);
---- /dev/null
-+++ b/drivers/serial/serial_sl2312.c
-@@ -0,0 +1,827 @@
-+/*
-+ *  linux/drivers/char/serial_uart00.c
-+ *
-+ *  Driver for UART00 serial ports
-+ *
-+ *  Based on drivers/char/serial_amba.c, by ARM Limited &
-+ *                                          Deep Blue Solutions Ltd.
-+ *  Copyright 2001 Altera Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ *
-+ *  $Id: serial_sl2312.c,v 1.1.1.1 2006/04/03 08:41:00 amos_lee Exp $
-+ *
-+ */
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+
-+#if defined(CONFIG_SERIAL_SL2312_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-+#define SUPPORT_SYSRQ
-+#endif
-+
-+#include 
-+#define UART_TYPE (volatile unsigned int*)
-+#include 
-+#include 
-+
-+// #define DEBUG           1
-+#define UART_NR		1
-+
-+
-+#define SERIAL_SL2312_NAME	"ttyS"
-+#define SERIAL_SL2312_MAJOR	204
-+#define SERIAL_SL2312_MINOR	40      /* Temporary - will change in future */
-+#define SERIAL_SL2312_NR	UART_NR
-+#define UART_PORT_SIZE 0x50
-+
-+#define SL2312_NO_PORTS         UART_NR
-+#define SL2312_ISR_PASS_LIMIT	256
-+
-+/*
-+ * Access macros for the SL2312 UARTs
-+ */
-+#define UART_GET_INT_STATUS(p)	(inl(UART_IIR((p)->membase)) & 0x0F)      // interrupt identification
-+#define UART_PUT_IER(p, c)      outl(c,UART_IER((p)->membase))    // interrupt enable
-+#define UART_GET_IER(p)         inl(UART_IER((p)->membase))
-+#define UART_PUT_CHAR(p, c)     outl(c,UART_THR((p)->membase))    // transmitter holding
-+#define UART_GET_CHAR(p)        inl(UART_RBR((p)->membase))       // receive buffer
-+#define UART_GET_LSR(p)         inl(UART_LSR((p)->membase))       // line status
-+#define UART_GET_MSR(p)         inl(UART_MSR((p)->membase))       // modem status
-+#define UART_GET_MCR(p)         inl(UART_MCR((p)->membase))       // modem control
-+#define UART_PUT_MCR(p, c)      outl(c,UART_MCR((p)->membase))
-+#define UART_GET_LCR(p)         inl(UART_LCR((p)->membase))       // mode control
-+#define UART_PUT_LCR(p, c)      outl(c,UART_LCR((p)->membase))
-+#define UART_GET_DIV_HI(p)	inl(UART_DIV_HI((p)->membase))
-+#define UART_PUT_DIV_HI(p, c)	outl(c,UART_DIV_HI((p)->membase))
-+#define UART_GET_DIV_LO(p)	inl(UART_DIV_LO((p)->membase))
-+#define UART_PUT_DIV_LO(p, c)	outl(c,UART_DIV_LO((p)->membase))
-+#define UART_PUT_MDR(p, c)      outl(c,UART_MDR((p)->membase))
-+#define UART_RX_DATA(s)		((s) & UART_LSR_DR)
-+#define UART_TX_READY(s)	((s) & UART_LSR_THRE)
-+
-+
-+static void sl2312_stop_tx(struct uart_port *port)
-+{
-+        unsigned int reg;
-+
-+//        printk("sl2312 stop tx : \n");
-+        reg = UART_GET_IER(port);
-+        reg &= ~(UART_IER_TE);
-+	UART_PUT_IER(port, reg);
-+}
-+
-+static void sl2312_stop_rx(struct uart_port *port)
-+{
-+        unsigned int reg;
-+
-+//        printk("sl2312 stop rx : \n");
-+        reg = UART_GET_IER(port);
-+        reg &= ~(UART_IER_DR);
-+	UART_PUT_IER(port, reg);
-+
-+}
-+
-+static void sl2312_enable_ms(struct uart_port *port)
-+{
-+        unsigned int reg;
-+
-+//        printk("sl2312 enable ms : \n");
-+
-+        reg = UART_GET_IER(port);
-+        reg |= (UART_IER_MS);
-+	UART_PUT_IER(port, reg);
-+
-+}
-+
-+static void
-+sl2312_rx_chars(struct uart_port *port)
-+{
-+	struct tty_struct *tty = port->info->tty;
-+	unsigned int status, mask, ch, flg, ignored = 0;
-+
-+
-+ //       printk("sl2312_rx_chars : \n");
-+	status = UART_GET_LSR(port);
-+	while (UART_RX_DATA(status)) {
-+
-+		/*
-+		 * We need to read rds before reading the
-+		 * character from the fifo
-+		 */
-+		ch = UART_GET_CHAR(port);
-+		port->icount.rx++;
-+
-+		//if (tty->flip.count >= TTY_FLIPBUF_SIZE)
-+		if (tty && !tty_buffer_request_room(tty, 1))
-+			goto ignore_char;
-+
-+		flg = TTY_NORMAL;
-+
-+		/*
-+		 * Note that the error handling code is
-+		 * out of the main execution path
-+		 */
-+
-+		if (status & (UART_LSR_OE|UART_LSR_PE|UART_LSR_FE|UART_LSR_BI|UART_LSR_DE))
-+			goto handle_error;
-+		if (uart_handle_sysrq_char(port, ch))
-+			goto ignore_char;
-+
-+	error_return:
-+		//*tty->flip.flag_buf_ptr++ = flg;
-+		//*tty->flip.char_buf_ptr++ = ch;
-+		//tty->flip.count++;
-+		tty_insert_flip_char(tty, ch, flg);
-+	ignore_char:
-+		status = UART_GET_LSR(port);
-+	} // end of while
-+out:
-+	tty_flip_buffer_push(tty);
-+	return;
-+
-+handle_error:
-+	if (status & UART_LSR_BI) {
-+		status &= ~(UART_LSR_FE);
-+		port->icount.brk++;
-+
-+#ifdef SUPPORT_SYSRQ
-+		if (uart_handle_break(port))
-+			goto ignore_char;
-+#endif
-+	} else if (status & UART_LSR_PE)
-+		port->icount.parity++;
-+	else if (status & UART_LSR_FE)
-+		port->icount.frame++;
-+
-+	if (status & UART_LSR_OE)
-+		port->icount.overrun++;
-+
-+	if (status & port->ignore_status_mask) {
-+		if (++ignored > 100)
-+			goto out;
-+		goto ignore_char;
-+	}
-+
-+	mask = status & port->read_status_mask;
-+
-+	if (mask & UART_LSR_BI)
-+		flg = TTY_BREAK;
-+	else if (mask & UART_LSR_PE)
-+		flg = TTY_PARITY;
-+	else if (mask & UART_LSR_FE)
-+		flg = TTY_FRAME;
-+
-+	if (status & UART_LSR_OE) {
-+		/*
-+		 * CHECK: does overrun affect the current character?
-+		 * ASSUMPTION: it does not.
-+		 */
-+		//*tty->flip.flag_buf_ptr++ = flg;
-+		//*tty->flip.char_buf_ptr++ = ch;
-+		//tty->flip.count++;
-+
-+		tty_insert_flip_char(tty, 0, TTY_BREAK);
-+
-+		// if (tty->flip.count >= TTY_FLIPBUF_SIZE)
-+		if (tty_buffer_request_room(tty, 1))
-+			goto ignore_char;
-+		ch = 0;
-+		flg = TTY_OVERRUN;
-+	}
-+#ifdef SUPPORT_SYSRQ
-+	port->sysrq = 0;
-+#endif
-+	goto error_return;
-+}
-+
-+static void sl2312_tx_chars(struct uart_port *port)
-+{
-+	struct circ_buf *xmit = &port->info->xmit;
-+	int count;
-+
-+
-+	if (port->x_char) {
-+		while(!(UART_GET_LSR(port)&UART_LSR_THRE));
-+		UART_PUT_CHAR(port, port->x_char);
-+		port->icount.tx++;
-+		port->x_char = 0;
-+
-+		return;
-+	}
-+	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
-+		sl2312_stop_tx(port);
-+
-+		return;
-+	}
-+
-+	count = port->fifosize >> 1;
-+	do {
-+		while(!(UART_GET_LSR(port)&UART_LSR_THRE));
-+		UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
-+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-+		port->icount.tx++;
-+		if (uart_circ_empty(xmit))
-+			break;
-+	} while (--count > 0);
-+
-+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-+		uart_write_wakeup(port);
-+
-+	if (uart_circ_empty(xmit))
-+		sl2312_stop_tx(port);
-+
-+}
-+
-+static void sl2312_start_tx(struct uart_port *port)
-+{
-+        unsigned int reg;
-+
-+//        printk("sl2312 start tx : \n");
-+        reg = UART_GET_IER(port);
-+        reg |= (UART_IER_TE);
-+	UART_PUT_IER(port, reg);
-+
-+	sl2312_tx_chars(port);
-+}
-+
-+static void sl2312_modem_status(struct uart_port *port)
-+{
-+	unsigned int status;
-+
-+//        printk("it8712 modem status : \n");
-+
-+	status = UART_GET_MSR(port);
-+
-+	if (!(status & (UART_MSR_DCTS | UART_MSR_DDSR |
-+		       UART_MSR_TERI | UART_MSR_DDCD)))
-+		return;
-+
-+        if (status & UART_MSR_DDCD)
-+                uart_handle_dcd_change(port, status & UART_MSR_DCD);
-+
-+        if (status & UART_MSR_DDSR)
-+                port->icount.dsr++;
-+
-+        if (status & UART_MSR_DCTS)
-+                uart_handle_cts_change(port, status & UART_MSR_CTS);
-+
-+	wake_up_interruptible(&port->info->delta_msr_wait);
-+
-+}
-+
-+static irqreturn_t sl2312_int(int irq, void *dev_id)
-+{
-+	struct uart_port *port = dev_id;
-+	unsigned int status, pass_counter = 0;
-+
-+	status = UART_GET_INT_STATUS(port);
-+	do {
-+		switch(status)
-+		{
-+		   case UART_IIR_DR:
-+		   case UART_IIR_RLS:
-+			sl2312_rx_chars(port);
-+		   break;
-+		   case UART_IIR_TE:
-+			sl2312_tx_chars(port);
-+		   break;
-+		   case UART_IIR_MODEM:
-+			sl2312_modem_status(port);
-+		   break;
-+		   default:
-+		   break;
-+		}
-+		if (pass_counter++ > SL2312_ISR_PASS_LIMIT)
-+			break;
-+
-+		status = UART_GET_INT_STATUS(port);
-+	} while (status);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static u_int sl2312_tx_empty(struct uart_port *port)
-+{
-+//        printk("sl2312 tx empty : \n");
-+
-+	return ((UART_GET_LSR(port) & UART_LSR_TE)? TIOCSER_TEMT : 0);
-+}
-+
-+static u_int sl2312_get_mctrl(struct uart_port *port)
-+{
-+	unsigned int result = 0;
-+	unsigned int status;
-+
-+//        printk("sl2312 get mctrl : \n");
-+
-+	status = UART_GET_MSR(port);
-+	if (status & UART_MSR_DCD)
-+		result |= TIOCM_CAR;
-+	if (status & UART_MSR_DSR)
-+		result |= TIOCM_DSR;
-+	if (status & UART_MSR_CTS)
-+		result |= TIOCM_CTS;
-+	if (status & UART_MSR_RI)
-+		result |= TIOCM_RI;
-+
-+	return result;
-+}
-+
-+static void sl2312_set_mctrl_null(struct uart_port *port, u_int mctrl)
-+{
-+}
-+
-+static void sl2312_break_ctl(struct uart_port *port, int break_state)
-+{
-+	unsigned int lcr;
-+
-+//        printk("sl2312 break ctl : \n");
-+
-+	lcr = UART_GET_LCR(port);
-+	if (break_state == -1)
-+		lcr |= UART_LCR_SETBREAK;
-+	else
-+		lcr &= ~UART_LCR_SETBREAK;
-+	UART_PUT_LCR(port, lcr);
-+}
-+
-+static inline u_int uart_calculate_quot(struct uart_port *port, u_int baud)
-+{
-+	u_int quot;
-+
-+	/* Special case: B0 rate */
-+	if (!baud)
-+		baud = 9600;
-+
-+	quot = (port->uartclk / (16 * baud)-1)  ;
-+
-+	return quot;
-+}
-+
-+static void sl2312_set_termios(struct uart_port *port, struct ktermios *termios,
-+                               struct ktermios *old)
-+{
-+	unsigned int  uart_mc, old_ier, baud, quot;
-+	unsigned long flags;
-+
-+        termios->c_cflag |= CREAD;
-+#ifdef DEBUG
-+	printk("it8712_set_cflag(0x%x) called\n", cflag);
-+#endif
-+        baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
-+        quot = (port->uartclk / (16 * baud))  ;
-+        //uart_get_divisor(port, baud);
-+
-+	/* byte size and parity */
-+	switch (termios->c_cflag & CSIZE) {
-+	case CS5:
-+              uart_mc = UART_LCR_LEN5;
-+              break;
-+	case CS6:
-+              uart_mc = UART_LCR_LEN6;
-+              break;
-+	case CS7:
-+              uart_mc = UART_LCR_LEN7;
-+              break;
-+	default: // CS8
-+              uart_mc = UART_LCR_LEN8;
-+              break;
-+	}
-+
-+	if (termios->c_cflag & CSTOPB)
-+		uart_mc|= UART_LCR_STOP;
-+	if (termios->c_cflag & PARENB) {
-+		uart_mc |= UART_LCR_EVEN;
-+		if (!(termios->c_cflag & PARODD))
-+			uart_mc |= UART_LCR_ODD;
-+	}
-+
-+    spin_lock_irqsave(&port->lock, flags);
-+        /*
-+         * Update the per-port timeout
-+         */
-+        uart_update_timeout(port, termios->c_cflag, baud);
-+	port->read_status_mask = UART_LSR_OE;
-+	if (termios->c_iflag & INPCK)
-+		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
-+	if (termios->c_iflag & (BRKINT | PARMRK))
-+		port->read_status_mask |= UART_LSR_BI;
-+
-+	/*
-+	 * Characters to ignore
-+	 */
-+	port->ignore_status_mask = 0;
-+	if (termios->c_iflag & IGNPAR)
-+		port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE;
-+	if (termios->c_iflag & IGNBRK) {
-+		port->ignore_status_mask |= UART_LSR_BI;
-+		/*
-+		 * If we're ignoring parity and break indicators,
-+		 * ignore overruns to (for real raw support).
-+		 */
-+		if (termios->c_iflag & IGNPAR)
-+			port->ignore_status_mask |= UART_LSR_OE;
-+	}
-+
-+	//save_flags(flags); cli();
-+	old_ier = UART_GET_IER(port);
-+
-+        if(UART_ENABLE_MS(port, termios->c_cflag))
-+             old_ier |= UART_IER_MS;
-+
-+	/* Set baud rate */
-+	UART_PUT_LCR(port, UART_LCR_DLAB);
-+	UART_PUT_DIV_LO(port, (quot & 0xff));
-+	UART_PUT_DIV_HI(port, ((quot & 0xf00) >> 8));
-+
-+	UART_PUT_LCR(port, uart_mc);
-+	UART_PUT_IER(port, old_ier);
-+
-+	//restore_flags(flags);
-+	spin_unlock_irqrestore(&port->lock, flags);
-+}
-+
-+
-+
-+static int sl2312_startup(struct uart_port *port)
-+{
-+	int retval;
-+	unsigned int regs;
-+
-+//        printk("sl2312 startup : \n");
-+
-+	/*
-+	 * Use iobase to store a pointer to info. We need this to start a
-+	 * transmission as the tranmittr interrupt is only generated on
-+	 * the transition to the idle state
-+	 */
-+
-+	/*
-+	 * Allocate the IRQ
-+	 */
-+	retval = request_irq(port->irq, sl2312_int, IRQF_DISABLED, "sl2312", port);
-+	if (retval)
-+		return retval;
-+
-+        /* setup interrupt controller  */
-+        regs = *((volatile unsigned int *)IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
-+        regs &= ~(IRQ_UART_MASK);
-+        *((volatile unsigned int *)IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))) = regs;
-+        regs = *((volatile unsigned int *)IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
-+        regs &= ~(IRQ_UART_MASK);
-+        *((volatile unsigned int *)IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))) = regs;
-+        *((volatile unsigned int *)IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_UART_MASK);
-+
-+	/*
-+	 * Finally, enable interrupts. Use the TII interrupt to minimise
-+	 * the number of interrupts generated. If higher performance is
-+	 * needed, consider using the TI interrupt with a suitable FIFO
-+	 * threshold
-+	 */
-+	UART_PUT_IER(port, (UART_IER_DR|UART_IER_TE));
-+
-+	return 0;
-+}
-+
-+static void sl2312_shutdown(struct uart_port *port)
-+{
-+//        printk("sl2312 shutdown : \n");
-+
-+	/*
-+	 * disable all interrupts, disable the port
-+	 */
-+	UART_PUT_IER(port, 0x0);
-+
-+	/* disable break condition and fifos */
-+//	UART_PUT_MCR(port, (UART_GET_MCR(port)&UART_MCR_MASK));
-+
-+	/*
-+	 * Free the interrupt
-+	 */
-+	free_irq(port->irq, port);
-+}
-+
-+static const char *sl2312_type(struct uart_port *port)
-+{
-+	return port->type == PORT_SL2312 ? "SL2312" : NULL;
-+}
-+
-+/*
-+ * Release the memory region(s) being used by 'port'
-+ */
-+static void sl2312_release_port(struct uart_port *port)
-+{
-+//        printk("sl2312 release port : \n");
-+
-+	release_mem_region(port->mapbase, UART_PORT_SIZE);
-+}
-+
-+/*
-+ * Request the memory region(s) being used by 'port'
-+ */
-+static int sl2312_request_port(struct uart_port *port)
-+{
-+	return request_mem_region(port->mapbase, UART_PORT_SIZE,
-+				    "serial_sl2312") != NULL ? 0 : -EBUSY;
-+}
-+
-+/*
-+ * Configure/autoconfigure the port.
-+ */
-+static void sl2312_config_port(struct uart_port *port, int flags)
-+{
-+
-+	if (flags & UART_CONFIG_TYPE) {
-+		if (sl2312_request_port(port) == 0)
-+			port->type = PORT_SL2312;
-+	}
-+}
-+
-+/*
-+ * verify the new serial_struct (for TIOCSSERIAL).
-+ */
-+static int sl2312_verify_port(struct uart_port *port, struct serial_struct *ser)
-+{
-+	int ret = 0;
-+
-+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_UART00)
-+		ret = -EINVAL;
-+	if (ser->irq < 0 || ser->irq >= NR_IRQS)
-+		ret = -EINVAL;
-+	if (ser->baud_base < 9600)
-+		ret = -EINVAL;
-+	return ret;
-+}
-+
-+static struct uart_ops sl2312_pops = {
-+	.tx_empty		=sl2312_tx_empty,
-+	.set_mctrl		=sl2312_set_mctrl_null,
-+	.get_mctrl		=sl2312_get_mctrl,
-+	.stop_tx		=sl2312_stop_tx,
-+	.start_tx		=sl2312_start_tx,
-+	.stop_rx		=sl2312_stop_rx,
-+	.enable_ms		=sl2312_enable_ms,
-+	.break_ctl		=sl2312_break_ctl,
-+	.startup		=sl2312_startup,
-+	.shutdown		=sl2312_shutdown,
-+	.set_termios	=sl2312_set_termios,
-+	.type			=sl2312_type,
-+	.release_port	=sl2312_release_port,
-+	.request_port	=sl2312_request_port,
-+	.config_port	=sl2312_config_port,
-+	.verify_port	=sl2312_verify_port,
-+};
-+
-+#ifdef CONFIG_ARCH_SL2312
-+
-+static struct uart_port sl2312_ports[UART_NR] = {
-+	{
-+		membase:	(void *)IO_ADDRESS(SL2312_UART_BASE),
-+		mapbase:	SL2312_UART_BASE,
-+		iotype:		SERIAL_IO_MEM,
-+		irq:		IRQ_UART,
-+		uartclk:	UART_CLK,
-+		fifosize:	16,
-+		ops:		&sl2312_pops,
-+		flags:		ASYNC_BOOT_AUTOCONF,
-+	}
-+};
-+
-+#endif
-+
-+#ifdef CONFIG_SERIAL_SL2312_CONSOLE
-+#ifdef used_and_not_const_char_pointer
-+static int sl2312_console_read(struct uart_port *port, char *s, u_int count)
-+{
-+	unsigned int status;
-+	int c;
-+#ifdef DEBUG
-+	printk("sl2312_console_read() called\n");
-+#endif
-+
-+	c = 0;
-+	while (c < count) {
-+		status = UART_GET_LSR(port);
-+ 		if (UART_RX_DATA(status)) {
-+			*s++ = UART_GET_CHAR(port);
-+			c++;
-+		} else {
-+			// nothing more to get, return
-+			return c;
-+		}
-+	}
-+	// return the count
-+	return c;
-+}
-+#endif
-+static void sl2312_console_write(struct console *co, const char *s, unsigned count)
-+{
-+#ifdef CONFIG_ARCH_SL2312
-+	struct uart_port *port = sl2312_ports + co->index;
-+	unsigned int status, old_ies;
-+	int i;
-+
-+	/*
-+	 *	First save the CR then disable the interrupts
-+	 */
-+	old_ies = UART_GET_IER(port);
-+	UART_PUT_IER(port,0x0);
-+
-+	/*
-+	 *	Now, do each character
-+	 */
-+	for (i = 0; i < count; i++) {
-+		do {
-+			status = UART_GET_LSR(port);
-+		} while (!UART_TX_READY(status));
-+		UART_PUT_CHAR(port, s[i]);
-+		if (s[i] == '\n') {
-+			do {
-+				status = UART_GET_LSR(port);
-+			} while (!UART_TX_READY(status));
-+			UART_PUT_CHAR(port, '\r');
-+		}
-+	}
-+
-+	/*
-+	 *	Finally, wait for transmitter to become empty
-+	 *	and restore the IES
-+	 */
-+	do {
-+		status = UART_GET_LSR(port);
-+	} while (!(status&UART_LSR_TE));
-+	UART_PUT_IER(port, old_ies);
-+#endif
-+}
-+
-+#if 0
-+static void sl2312_console_device(struct console *co,int *index)
-+{
-+
-+	struct uart_driver *p = co->data;
-+    *index = co->index;
-+    return p->tty_driver;
-+
-+}
-+#endif
-+
-+static void /*__init*/ sl2312_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
-+{
-+//	printk("sl2312 console get options : \n");
-+
-+	u_int uart_mc, quot;
-+	uart_mc= UART_GET_MCR(port);
-+
-+	*parity = 'n';
-+	if (uart_mc & UART_LCR_PE) {
-+		if (uart_mc & UART_LCR_EVEN)
-+			*parity = 'e';
-+		else
-+			*parity = 'o';
-+	}
-+
-+	switch (uart_mc & UART_LCR_MSK){
-+
-+	case UART_LCR_LEN5:
-+		*bits = 5;
-+		break;
-+	case UART_LCR_LEN6:
-+		*bits = 6;
-+		break;
-+	case UART_LCR_LEN7:
-+		*bits = 7;
-+		break;
-+	case UART_LCR_LEN8:
-+		*bits = 8;
-+		break;
-+	}
-+	UART_PUT_MCR(port,UART_LCR_DLAB);
-+	quot = UART_GET_DIV_LO(port) | (UART_GET_DIV_HI(port) << 8);
-+	UART_PUT_MCR(port,uart_mc);
-+	*baud = port->uartclk / (16 *quot );
-+}
-+
-+static int __init sl2312_console_setup(struct console *co, char *options)
-+{
-+	struct uart_port *port;
-+	int baud = 19200;
-+	int bits = 8;
-+	int parity = 'n';
-+	int flow= 'n';
-+
-+	printk("sl2312 console setup : \n");
-+
-+#ifdef CONFIG_ARCH_SL2312
-+	/*
-+	 * Check whether an invalid uart number has been specified, and
-+	 * if so, search for the first available port that does have
-+	 * console support.
-+	 */
-+	port = uart_get_console(sl2312_ports,SL2312_NO_PORTS,co);
-+#else
-+	return -ENODEV;
-+#endif
-+
-+	if (options)
-+		uart_parse_options(options, &baud, &parity, &bits, &flow);
-+	else
-+		sl2312_console_get_options(port, &baud, &parity, &bits);
-+
-+	return uart_set_options(port, co, baud, parity, bits, flow);
-+}
-+
-+extern struct uart_driver sl2312_reg;
-+static struct console sl2312_console = {
-+	.name      = SERIAL_SL2312_NAME,
-+	.write		= sl2312_console_write,
-+	.device		= uart_console_device,
-+//	.device		= sl2312_console_device,
-+	.setup		= sl2312_console_setup,
-+//	.flags		= (CON_PRINTBUFFER|CON_ENABLED),
-+	.flags		= CON_PRINTBUFFER,
-+	.index		= -1,
-+	.data       = &sl2312_reg,
-+};
-+
-+static int __init sl2312_console_init(void)
-+{
-+	register_console(&sl2312_console);
-+	return 0;
-+
-+}
-+
-+console_initcall(sl2312_console_init);
-+
-+#define SL2312_CONSOLE	&sl2312_console
-+#else
-+#define SL2312_CONSOLE	NULL
-+#endif
-+
-+// static
-+struct uart_driver sl2312_reg = {
-+	.owner         = NULL,
-+	.driver_name	= SERIAL_SL2312_NAME,
-+	.dev_name		= SERIAL_SL2312_NAME,
-+	.major          = SERIAL_SL2312_MAJOR,
-+	.minor			= SERIAL_SL2312_MINOR,
-+	.nr				= UART_NR,
-+	.cons			= SL2312_CONSOLE,
-+};
-+
-+static int __init sl2312_init(void)
-+{
-+       int result;
-+	//printk("serial_it8712: it871212_init \n");
-+
-+        result = uart_register_driver(&sl2312_reg);
-+        if(result)
-+             return result;
-+	result = uart_add_one_port(&sl2312_reg, &sl2312_ports[0]);
-+
-+        return result;
-+}
-+
-+
-+__initcall(sl2312_init);
---- a/include/linux/serial_core.h
-+++ b/include/linux/serial_core.h
-@@ -147,6 +147,10 @@
- #define PORT_SB1250_DUART	77
- 
- 
-+/* Storlink Soc */
-+#define PORT_SL2312     72
-+#define PORT_IT8712     73
-+
- #ifdef __KERNEL__
- 
- #include 
---- a/drivers/char/Makefile
-+++ b/drivers/char/Makefile
-@@ -70,6 +70,16 @@
- obj-$(CONFIG_APPLICOM)		+= applicom.o
- obj-$(CONFIG_SONYPI)		+= sonypi.o
- obj-$(CONFIG_RTC)		+= rtc.o
-+
-+###  for Storlink SoC ###
-+obj-$(CONFIG_SL2312_RTC) += sl2312_rtc.o
-+obj-$(CONFIG_IT8712_GPIO)   += it8712_gpio.o
-+obj-$(CONFIG_GEMINI_GPIO)   += gemini_gpio.o
-+obj-$(CONFIG_GEMINI_PWC) += gemini_pwr.o
-+obj-$(CONFIG_GEMINI_CIR)    += gemini_cir.o
-+obj-$(CONFIG_GEMINI_I2S)    += gemini_i2s.o
-+obj-$(CONFIG_SL2312_WATCHDOG) += sl2312_wd.o
-+
- obj-$(CONFIG_HPET)		+= hpet.o
- obj-$(CONFIG_GEN_RTC)		+= genrtc.o
- obj-$(CONFIG_EFI_RTC)		+= efirtc.o
---- a/drivers/serial/Kconfig
-+++ b/drivers/serial/Kconfig
-@@ -280,6 +280,56 @@
- 
- comment "Non-8250 serial port support"
- 
-+config SERIAL_SL2312
-+	bool "SL2312  serial port (sl2312) support"
-+	depends on ARCH_SL2312
-+	select SERIAL_CORE
-+	select SERIAL_SL2312_CONSOLE
-+	help
-+         Say Y here if you want to use the hard logic uart on SWORD. This
-+         driver also supports soft logic implentations of this uart core.
-+
-+config SERIAL_SL2312_CONSOLE
-+	bool "Support for console on SL2312 serial port"
-+	depends on SERIAL_SL2312
-+	select SERIAL_CORE_CONSOLE
-+	help
-+        Say Y here if you want to support a serial console on an SWORD
-+        hard logic uart or uart00 IP core.
-+
-+        Even if you say Y here, the currently visible virtual console
-+        (/dev/tty0) will still be used as the system console by default, but
-+        you can alter that using a kernel command line option such as
-+        "console=ttyS0". (Try "man bootparam" or see the documentation of
-+        your boot loader (lilo or loadlin) about how to pass options to the
-+        kernel at boot time.)
-+
-+
-+config SERIAL_IT8712
-+	bool "Sl2312 serial port(IT8712) support"
-+	depends on ARM && ARCH_SL2312 && SL2312_LPC
-+	select SERIAL_CORE
-+	select SERIAL_IT8712_CONSOLE
-+	help
-+	  Say Y here if you want to use the hard logic uart on Excalibur. This
-+	  driver also supports soft logic implentations of this uart core.
-+
-+config SERIAL_IT8712_CONSOLE
-+	bool "Support for console on Sword serial port(IT8712)"
-+	depends on SERIAL_IT8712
-+	select SERIAL_CORE_CONSOLE
-+	help
-+	  Say Y here if you want to support a serial console on an Excalibur
-+	  hard logic uart or uart00 IP core.
-+
-+	  Even if you say Y here, the currently visible virtual console
-+	  (/dev/tty0) will still be used as the system console by default, but
-+	  you can alter that using a kernel command line option such as
-+	  "console=ttySI0". (Try "man bootparam" or see the documentation of
-+	  your boot loader (lilo or loadlin) about how to pass options to the
-+	  kernel at boot time.)
-+
-+
- config SERIAL_AMBA_PL010
- 	tristate "ARM AMBA PL010 serial port support"
- 	depends on ARM_AMBA && (BROKEN || !ARCH_VERSATILE)
---- a/drivers/serial/Makefile
-+++ b/drivers/serial/Makefile
-@@ -62,5 +62,7 @@
- obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
- obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
- obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
-+obj-$(CONFIG_SERIAL_IT8712) += it8712.o
-+obj-$(CONFIG_SERIAL_SL2312) += serial_sl2312.o
- obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
- obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
diff --git a/target/linux/storm/patches/009-watchdog.patch b/target/linux/storm/patches/009-watchdog.patch
deleted file mode 100644
index 3055a94822..0000000000
--- a/target/linux/storm/patches/009-watchdog.patch
+++ /dev/null
@@ -1,398 +0,0 @@
---- a/arch/arm/mach-sl2312/sl3516_device.c
-+++ b/arch/arm/mach-sl2312/sl3516_device.c
-@@ -76,9 +76,30 @@
- 	.resource       = sl3516_sata0_resources,
- };
- 
-+static struct resource sl351x_wdt_resources[] = {
-+	[0] = {
-+		.start  = SL2312_WAQTCHDOG_BASE + 0x00,
-+		.end    = SL2312_WAQTCHDOG_BASE + 0x1C,
-+		.flags  = IORESOURCE_MEM,
-+	},
-+	[1] = {
-+		.start  = IRQ_WATCHDOG,
-+		.end    = IRQ_WATCHDOG,
-+		.flags  = IORESOURCE_IRQ,
-+	},
-+};
-+
-+static struct platform_device sl351x_wdt = {
-+	.name		= "sl351x-wdt",
-+	.id		= -1,
-+	.resource	= sl351x_wdt_resources,
-+	.num_resources	= ARRAY_SIZE(sl351x_wdt_resources),
-+};
-+
- static struct platform_device *sata_devices[] __initdata = {
- 	&sata_device,
- 	&sata0_device,
-+	&sl351x_wdt,
- };
- 
- static int __init sl3516_init(void)
---- a/drivers/char/watchdog/Kconfig
-+++ b/drivers/char/watchdog/Kconfig
-@@ -171,6 +171,17 @@
- 	  To compile this driver as a module, choose M here: the
- 	  module will be called ep93xx_wdt.
- 
-+config WATCHDOG_SL351X
-+	tristate "SL351x Watchdog"
-+	depends on WATCHDOG && ARCH_SL2312
-+	help
-+	  This driver adds watchdog support for the integrated watchdog in the
-+	  SL351x processors (Farraday core). If you have one of these processors
-+	  and wish to have watchdog support enabled, say Y, otherwise say N.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called sl351x_wdt.
-+
- config OMAP_WATCHDOG
- 	tristate "OMAP Watchdog"
- 	depends on ARCH_OMAP16XX || ARCH_OMAP24XX
---- a/drivers/char/watchdog/Makefile
-+++ b/drivers/char/watchdog/Makefile
-@@ -36,6 +36,7 @@
- obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
- obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
- obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
-+obj-$(CONFIG_WATCHDOG_SL351X) += sl351x_wdt.o
- obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
- obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
- obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
---- /dev/null
-+++ b/drivers/char/watchdog/sl351x_wdt.c
-@@ -0,0 +1,332 @@
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#define WATCHDOG_TEST 1
-+#define PFX "sl351x-wdt: "
-+
-+#define _WATCHDOG_COUNTER  0x00
-+#define _WATCHDOG_LOAD     0x04
-+#define _WATCHDOG_RESTART  0x08
-+#define _WATCHDOG_CR       0x0C
-+#define _WATCHDOG_STATUS   0x10
-+#define _WATCHDOG_CLEAR    0x14
-+#define _WATCHDOG_INTRLEN  0x18
-+
-+static struct resource  *wdt_mem;
-+static struct resource  *wdt_irq;
-+static void __iomem     *wdt_base;
-+static int 		wdt_margin = WATCHDOG_TIMEOUT_MARGIN;	/* in range of 0 .. 60s */
-+
-+static int open_state = WATCHDOG_DRIVER_CLOSE;
-+static int wd_expire = 0;
-+
-+static void watchdog_enable(void)
-+{
-+	unsigned long wdcr;
-+
-+	wdcr = readl(wdt_base + _WATCHDOG_CR);
-+	wdcr |= (WATCHDOG_WDENABLE_MSK|WATCHDOG_WDRST_MSK);
-+#ifdef WATCHDOG_TEST
-+	wdcr |= WATCHDOG_WDINTR_MSK;
-+//	wdcr &= ~WATCHDOG_WDRST_MSK;
-+#endif
-+	wdcr &= ~WATCHDOG_WDCLOCK_MSK;
-+	writel(wdcr, wdt_base + _WATCHDOG_CR);
-+}
-+
-+static void watchdog_set_timeout(unsigned long timeout)
-+{
-+	timeout = WATCHDOG_TIMEOUT_SCALE * timeout;
-+	writel(timeout, wdt_base + _WATCHDOG_LOAD);
-+	writel(WATCHDOG_RESTART_VALUE, wdt_base + _WATCHDOG_RESTART);
-+}
-+
-+static void watchdog_keepalive(void)
-+{
-+	writel(WATCHDOG_RESTART_VALUE, wdt_base + _WATCHDOG_RESTART);
-+}
-+
-+static void watchdog_disable(void)
-+{
-+	unsigned long wdcr;
-+
-+	wdcr = readl(wdt_base + _WATCHDOG_CR);
-+	wdcr &= ~WATCHDOG_WDENABLE_MSK;
-+	writel(wdcr, wdt_base + _WATCHDOG_CR);
-+}
-+
-+
-+#ifdef WATCHDOG_TEST
-+static irqreturn_t watchdog_irq(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+	unsigned int clear;
-+
-+	writel(WATCHDOG_CLEAR_STATUS, wdt_base + _WATCHDOG_CLEAR);
-+	printk(KERN_INFO PFX "Watchdog timeout, resetting system...\n");
-+
-+	clear = __raw_readl(IO_ADDRESS(SL2312_INTERRUPT_BASE)+0x0C);
-+	clear &= 0x01;
-+	__raw_writel(clear,IO_ADDRESS(SL2312_INTERRUPT_BASE)+0x08);
-+	wd_expire = 1;
-+	return IRQ_HANDLED;
-+}
-+
-+#endif
-+
-+#define OPTIONS WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE
-+static struct watchdog_info sl351x_wdt_ident = {
-+	.options          =     OPTIONS,
-+	.firmware_version =     0,
-+	.identity         =     "sl351x Watchdog",
-+};
-+
-+struct file_operations watchdog_fops = {
-+	.write		= watchdog_write,
-+	.read		= watchdog_read,
-+	.open		= watchdog_open,
-+	.release	= watchdog_release,
-+	.ioctl		= watchdog_ioctl,
-+};
-+
-+static int watchdog_open(struct inode *inode, struct file *filp)
-+{
-+	if (open_state == WATCHDOG_DRIVER_OPEN)
-+		return -EBUSY;
-+
-+	wd_expire = 0;
-+
-+	watchdog_disable();
-+	watchdog_set_timeout(wdt_margin);
-+	watchdog_enable();
-+
-+	printk(KERN_INFO PFX "watchog timer enabled, margin: %ds.\n", wdt_margin);
-+	open_state = WATCHDOG_DRIVER_OPEN;
-+
-+	return nonseekable_open(inode, filp);
-+}
-+
-+static int watchdog_release(struct inode *inode, struct file *filp)
-+{
-+	watchdog_disable();
-+
-+	open_state = WATCHDOG_DRIVER_CLOSE;
-+	wd_expire = 0;
-+	printk(KERN_INFO PFX "watchog timer disabled, margin: %ds.\n", wdt_margin);
-+
-+	return 0;
-+}
-+
-+static ssize_t watchdog_read(struct file *filp, char *buf, size_t count, loff_t *off)
-+{
-+	int i;
-+	unsigned long val;
-+
-+
-+	for(i=0;i< count;i++)
-+	{
-+		if ((i%4)==0)
-+			val = *((unsigned long *)WATCHDOG_COUNTER);
-+		buf[i] = (val & 0xFF);
-+		val >>= 8;
-+	}
-+	return count;
-+}
-+
-+static ssize_t watchdog_write(struct file *filp, const char *buf, size_t len, loff_t *off)
-+{
-+	/*  Refresh the timer. */
-+	if (len) {
-+		watchdog_keepalive();
-+	}
-+	return len;
-+
-+}
-+
-+static int watchdog_ioctl(struct inode *inode, struct file *filp,
-+			  unsigned int cmd, unsigned long arg)
-+{
-+	void __user *argp = (void __user *)arg;
-+	int margin;
-+
-+	switch(cmd)
-+	{
-+	case WDIOC_GETSUPPORT:
-+		return copy_to_user(argp, &sl351x_wdt_ident,
-+				    sizeof(sl351x_wdt_ident)) ? -EFAULT : 0;
-+
-+	case WDIOC_GETSTATUS:
-+	case WDIOC_GETBOOTSTATUS:
-+		return put_user(0, (int __user*)argp);
-+
-+	case WDIOC_KEEPALIVE:
-+		watchdog_keepalive();
-+		return 0;
-+
-+	case WDIOC_SETTIMEOUT:
-+		if (get_user(margin, (int __user*)argp))
-+			return -EFAULT;
-+
-+		/* Arbitrary, can't find the card's limits */
-+		if ((margin < 0) || (margin > 60))
-+			return -EINVAL;
-+
-+		// watchdog_disable();
-+		wdt_margin = margin;
-+		watchdog_set_timeout(margin);
-+		watchdog_keepalive();
-+		// watchdog_enable();
-+
-+		/* Fall through */
-+
-+	case WDIOC_GETTIMEOUT:
-+		return put_user(wdt_margin, (int *)arg);
-+
-+	default:
-+		return -ENOIOCTLCMD;
-+	}
-+}
-+
-+static struct miscdevice wd_dev= {
-+	WATCHDOG_MINOR,
-+	"watchdog",
-+	&watchdog_fops
-+};
-+
-+static char banner[] __initdata = KERN_INFO "SL351x Watchdog Timer, (c) 2007 WILIBOX\n";
-+
-+static int sl351x_wdt_probe(struct platform_device *pdev)
-+{
-+	struct resource *res;
-+	int ret, size;
-+	unsigned long wdcr;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (res == NULL) {
-+		printk(KERN_INFO PFX "failed to get memory region resouce\n");
-+		return -ENOMEM;
-+	}
-+
-+	size = (res->end-res->start)+1;
-+
-+	wdt_mem = request_mem_region(res->start, size, pdev->name);
-+	if (wdt_mem == NULL) {
-+		printk(KERN_INFO PFX "failed to get memory region\n");
-+		return -ENOENT;
-+	}
-+
-+	wdt_base = ioremap(res->start, size);
-+	if (wdt_base == NULL) {
-+		printk(KERN_INFO PFX "failed to ioremap() region\n");
-+		return -EINVAL;
-+	}
-+
-+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+	if (res == NULL) {
-+		 printk(KERN_INFO PFX "failed to get irq resource\n");
-+		 return -ENOENT;
-+	}
-+
-+	wdt_irq = res;
-+
-+	ret = request_irq(res->start, watchdog_irq, 0, pdev->name, pdev);
-+	if (ret != 0) {
-+		printk(KERN_INFO PFX "failed to install irq (%d)\n", ret);
-+		return ret;
-+	}
-+
-+	wdcr = readl(wdt_base + _WATCHDOG_CR);
-+	if (wdcr & WATCHDOG_WDENABLE_MSK) {
-+		printk(KERN_INFO PFX "Found watchdog in enabled state, reseting ...\n");
-+		wdcr &= ~WATCHDOG_WDENABLE_MSK;
-+		writel(wdcr, wdt_base + _WATCHDOG_CR);
-+	}
-+
-+	ret = misc_register(&wd_dev);
-+
-+	return ret;
-+}
-+
-+static int sl351x_wdt_remove(struct platform_device *pdev)
-+{
-+	if (wdt_base != NULL) {
-+		iounmap(wdt_base);
-+		wdt_base = NULL;
-+	}
-+
-+	if (wdt_irq != NULL) {
-+		free_irq(wdt_irq->start, pdev);
-+		release_resource(wdt_irq);
-+		wdt_irq = NULL;
-+	}
-+
-+	if (wdt_mem != NULL) {
-+		release_resource(wdt_mem);
-+		wdt_mem = NULL;
-+	}
-+
-+	misc_deregister(&wd_dev);
-+
-+	return 0;
-+}
-+
-+static void sl351x_wdt_shutdown(struct platform_device *dev)
-+{
-+	watchdog_disable();
-+}
-+
-+#ifdef CONFIG_PM
-+static int sl351x_wdt_suspend(struct platform_device *dev, pm_message_t state)
-+{
-+	watchdog_disable();
-+}
-+
-+static int sl351x_wdt_resume(struct platform_device *dev)
-+{
-+	watchdog_set_timeout(wdt_margin);
-+	watchdog_enable();
-+}
-+
-+#else
-+#define sl351x_wdt_suspend	NULL
-+#define sl351x_wdt_resume	NULL
-+#endif
-+
-+static struct platform_driver sl351x_wdt_driver = {
-+	.probe          = sl351x_wdt_probe,
-+	.remove         = sl351x_wdt_remove,
-+	.shutdown       = sl351x_wdt_shutdown,
-+	.suspend        = sl351x_wdt_suspend,
-+	.resume         = sl351x_wdt_resume,
-+	.driver         = {
-+		.owner  = THIS_MODULE,
-+		.name   = "sl351x-wdt",
-+	},
-+};
-+
-+static int __init watchdog_init(void)
-+{
-+	printk(banner);
-+	return platform_driver_register(&sl351x_wdt_driver);
-+}
-+
-+static void __exit watchdog_exit(void)
-+{
-+	platform_driver_unregister(&sl351x_wdt_driver);
-+}
-+
-+module_init(watchdog_init);
-+module_exit(watchdog_exit);
diff --git a/target/linux/storm/patches/1100-gpio.patch b/target/linux/storm/patches/1100-gpio.patch
deleted file mode 100644
index de9c4da375..0000000000
--- a/target/linux/storm/patches/1100-gpio.patch
+++ /dev/null
@@ -1,384 +0,0 @@
---- /dev/null
-+++ b/drivers/char/gemini_gpio_dev.c
-@@ -0,0 +1,356 @@
-+/*
-+ * 	GPIO driver for Gemini board
-+ * 	Provides /dev/gpio
-+ */
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 	/* copy_to_user, copy_from_user */
-+
-+#include 
-+#include 
-+#include 
-+#include 
-+#include 
-+
-+#define GEMINI_GPIO_BASE1		IO_ADDRESS(SL2312_GPIO_BASE)
-+#define GEMINI_GPIO_BASE2		IO_ADDRESS(SL2312_GPIO_BASE1)
-+
-+#define GPIO_SET	2
-+#define MAX_GPIO_LINE	32*GPIO_SET
-+
-+wait_queue_head_t gemini_gpio_wait[MAX_GPIO_LINE];
-+
-+enum GPIO_REG
-+{
-+    GPIO_DATA_OUT   		= 0x00,
-+    GPIO_DATA_IN    		= 0x04,
-+    GPIO_PIN_DIR    		= 0x08,
-+    GPIO_BY_PASS    		= 0x0C,
-+    GPIO_DATA_SET   		= 0x10,
-+    GPIO_DATA_CLEAR 		= 0x14,
-+    GPIO_PULL_ENABLE 		= 0x18,
-+    GPIO_PULL_TYPE 			= 0x1C,
-+    GPIO_INT_ENABLE 		= 0x20,
-+    GPIO_INT_RAW_STATUS 	= 0x24,
-+    GPIO_INT_MASK_STATUS 	= 0x28,
-+    GPIO_INT_MASK 			= 0x2C,
-+    GPIO_INT_CLEAR 			= 0x30,
-+    GPIO_INT_TRIG 			= 0x34,
-+    GPIO_INT_BOTH 			= 0x38,
-+    GPIO_INT_POLAR 			= 0x3C
-+};
-+
-+unsigned int regist_gpio_int0=0,regist_gpio_int1=0;
-+
-+/* defines a specific GPIO bit number and state */
-+struct gpio_bit {
-+	unsigned char bit;
-+	unsigned char state;
-+};
-+
-+#define GPIO_MAJOR    10
-+#define GPIO_MINOR    127
-+
-+/*
-+ * ioctl calls that are permitted to the /dev/gpio interface
-+ */
-+#define GPIO_GET_BIT	0x0000001
-+#define GPIO_SET_BIT	0x0000002
-+#define GPIO_GET_CONFIG	0x0000003
-+#define GPIO_SET_CONFIG 0x0000004
-+
-+//#define GPIO_CONFIG_OUT  1
-+//#define GPIO_CONFIG_IN   2
-+
-+
-+
-+#define DEVICE_NAME "gpio"
-+
-+//#define DEBUG
-+
-+/*
-+ * GPIO interface
-+ */
-+
-+/* /dev/gpio */
-+static int gpio_ioctl(struct inode *inode, struct file *file,
-+                     unsigned int cmd, unsigned long arg);
-+
-+/* /proc/driver/gpio */
-+static int gpio_read_proc(char *page, char **start, off_t off,
-+                         int count, int *eof, void *data);
-+
-+static unsigned char gpio_status;        /* bitmapped status byte.       */
-+
-+/* functions for set/get gpio lines on storlink cpu */
-+
-+void gpio_line_get(unsigned char pin, u32 * data)
-+{
-+	unsigned int set = pin >>5;		// each GPIO set has 32 pins
-+	unsigned int status,addr;
-+
-+	addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1) + GPIO_DATA_IN;
-+	status = readl(addr);
-+#ifdef DEBUG
-+	printk("status = %08X, pin = %d, set = %d\n", status, pin, set);
-+#endif
-+	if (set)
-+			*data = (status&(1<<(pin-32)))?1:0;
-+	else
-+			*data = (status&(1<>5;		// each GPIO set has 32 pins
-+	unsigned int status=0,addr;
-+
-+	addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1)+(high?GPIO_DATA_SET:GPIO_DATA_CLEAR);
-+
-+	status &= ~(1 << (pin %32));
-+	status |= (1 << (pin % 32));
-+	writel(status,addr);
-+}
-+
-+/*
-+ * pin = [0..63]
-+ * mode =
-+ * 			1 -- OUT
-+ * 			2 -- IN
-+ */
-+void gpio_line_config(unsigned char pin, unsigned char mode)
-+{
-+	unsigned char set = pin >>5;		// each GPIO set has 32 pins
-+	unsigned int status,addr;
-+
-+	addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1)+GPIO_PIN_DIR;
-+	status = readl(addr);
-+
-+	status &= ~(1 << (pin %32));
-+	if (mode == 1)
-+			status |= (1 << (pin % 32)); /* PinDir: 0 - input, 1 - output */
-+
-+	writel(status,addr);
-+#if 0
-+	/* enable pullup-high if mode is input */
-+
-+	addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1)+GPIO_PULL_ENABLE;
-+	status = readl(addr);
-+
-+	status &= ~(1 << (pin %32));
-+	if (mode == 2) /* input */
-+			status |= (1 << (pin % 32)); /* PullEnable: 0 - disable, 1 - enable */
-+
-+	writel(status,addr);
-+
-+	addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1)+GPIO_PULL_TYPE;
-+	status = readl(addr);
-+
-+	status &= ~(1 << (pin %32));
-+	if (mode == 2) /* input */
-+			status |= (1 << (pin % 32)); /* PullType: 0 - low, 1 - high */
-+
-+	writel(status,addr);
-+#endif
-+}
-+
-+#define GPIO_IS_OPEN             0x01    /* means /dev/gpio is in use     */
-+
-+/*
-+ *      Now all the various file operations that we export.
-+ */
-+static int gpio_ioctl(struct inode *inode, struct file *file,
-+                         unsigned int cmd, unsigned long arg)
-+{
-+		struct gpio_bit bit;
-+		u32 val;
-+
-+		if (copy_from_user(&bit, (struct gpio_bit *)arg,
-+								sizeof(bit)))
-+				return -EFAULT;
-+
-+		switch (cmd) {
-+
-+				case GPIO_GET_BIT:
-+						gpio_line_get(bit.bit, &val);
-+						bit.state = val;
-+						return copy_to_user((void *)arg, &bit, sizeof(bit)) ? -EFAULT : 0;
-+				case GPIO_SET_BIT:
-+						val = bit.state;
-+						gpio_line_set(bit.bit, val);
-+						return 0;
-+				case GPIO_GET_CONFIG:
-+						// gpio_line_config(bit.bit, bit.state);
-+						return copy_to_user((void *)arg, &bit, sizeof(bit)) ? -EFAULT : 0;
-+				case GPIO_SET_CONFIG:
-+						val = bit.state;
-+						gpio_line_config(bit.bit, bit.state);
-+						return 0;
-+		}
-+		return -EINVAL;
-+}
-+
-+
-+static int gpio_open(struct inode *inode, struct file *file)
-+{
-+        if (gpio_status & GPIO_IS_OPEN)
-+                return -EBUSY;
-+
-+        gpio_status |= GPIO_IS_OPEN;
-+        return 0;
-+}
-+
-+
-+static int gpio_release(struct inode *inode, struct file *file)
-+{
-+        /*
-+         * Turn off all interrupts once the device is no longer
-+         * in use and clear the data.
-+         */
-+
-+        gpio_status &= ~GPIO_IS_OPEN;
-+        return 0;
-+}
-+
-+
-+/*
-+ *      The various file operations we support.
-+ */
-+
-+static struct file_operations gpio_fops = {
-+        .owner          = THIS_MODULE,
-+        .ioctl          = gpio_ioctl,
-+        .open           = gpio_open,
-+        .release        = gpio_release,
-+};
-+
-+static struct miscdevice gpio_dev =
-+{
-+        .minor          = GPIO_MINOR,
-+        .name           = "gpio",
-+        .fops           = &gpio_fops,
-+};
-+
-+
-+
-+
-+#ifdef CONFIG_PROC_FS
-+static struct proc_dir_entry *dir;
-+
-+/*
-+ *      Info exported via "/proc/driver/gpio".
-+ */
-+static int gpio_get_status(char *buf)
-+{
-+    char *p = buf;
-+	u32 val = 0;
-+	int i;
-+	int bit;
-+#ifdef DEBUG
-+	u32 addr;
-+
-+	for (i = 0; i < 0x20; i+=4 ) {
-+			addr = IO_ADDRESS(SL2312_GPIO_BASE) + i;
-+			val = readl(addr);
-+			p+=sprintf(p, "GPIO0: 0x%02X: %08X\n", i, val );
-+	}
-+	for (i = 0; i < 0x20; i+=4 ) {
-+			addr = IO_ADDRESS(SL2312_GPIO_BASE1) + i;
-+			val = readl(addr);
-+			p+=sprintf(p, "GPIO1: 0x%02X: %08X\n", i, val );
-+	}
-+#endif
-+
-+	for (i = 0; i < 32; i++) {
-+			gpio_line_get(i, &bit);
-+			if (bit)
-+					val |= (1 << i);
-+	}
-+	p += sprintf(p, "gpio0\t: 0x%08x\n", val);
-+
-+	val = 0;
-+	for (i = 32; i < 64; i++) {
-+			gpio_line_get(i, &bit);
-+			if (bit)
-+					val |= (1 << i);
-+	}
-+	p += sprintf(p, "gpio1\t: 0x%08x\n", val);
-+
-+	return p - buf;
-+}
-+
-+
-+/* /proc/driver/gpio read op
-+ */
-+static int gpio_read_proc(char *page, char **start, off_t off,
-+                             int count, int *eof, void *data)
-+{
-+        int len = gpio_get_status (page);
-+
-+        if (len <= off+count)
-+			*eof = 1;
-+        *start = page + off;
-+        len -= off;
-+        if ( len > count )
-+			len = count;
-+        if ( len < 0 )
-+			len = 0;
-+        return len;
-+}
-+#endif /* CONFIG_PROC_FS */
-+
-+
-+static int __init gpio_init_module(void)
-+{
-+        int retval;
-+#ifdef CONFIG_PROC_FS
-+	struct proc_dir_entry *res;
-+#endif
-+
-+        /* register /dev/gpio file ops */
-+	//retval = register_chrdev(GPIO_MAJOR, DEVICE_NAME, &gpio_fops);
-+	retval = misc_register(&gpio_dev);
-+        if(retval < 0)
-+                return retval;
-+
-+#ifdef CONFIG_PROC_FS
-+	dir = proc_mkdir("driver/gpio", NULL);
-+	if (!dir) {
-+		misc_deregister(&gpio_dev);
-+		return -ENOMEM;
-+	}
-+        /* register /proc/driver/gpio */
-+	res = create_proc_entry("info", 0644, dir);
-+	if (res) {
-+		res->read_proc= gpio_read_proc;
-+	} else {
-+		misc_deregister(&gpio_dev);
-+		return -ENOMEM;
-+	}
-+#endif
-+
-+	printk("%s: GPIO driver loaded\n", __FILE__);
-+
-+	return 0;
-+}
-+
-+static void __exit gpio_cleanup_module(void)
-+{
-+	remove_proc_entry ("info", dir);
-+        misc_deregister(&gpio_dev);
-+
-+	printk("%s: GPIO driver unloaded\n", __FILE__);
-+}
-+
-+module_init(gpio_init_module);
-+module_exit(gpio_cleanup_module);
-+
-+MODULE_AUTHOR("Jonas Majauskas");
-+MODULE_LICENSE("GPL");
-+
---- a/drivers/char/Kconfig
-+++ b/drivers/char/Kconfig
-@@ -1064,5 +1064,12 @@
- 
- source "drivers/s390/char/Kconfig"
- 
-+config GEMINI_GPIO_DEV
-+	tristate "GPIO driver for Gemini board (provides /dev/gpio)"
-+	depends on ARCH_SL2312
-+	default n
-+	help
-+	  GPIO driver for Gemini boards - SL3512, SL3516.
-+
- endmenu
- 
---- a/drivers/char/Makefile
-+++ b/drivers/char/Makefile
-@@ -115,6 +115,7 @@
- 
- obj-$(CONFIG_HANGCHECK_TIMER)	+= hangcheck-timer.o
- obj-$(CONFIG_TCG_TPM)		+= tpm/
-+obj-$(CONFIG_GEMINI_GPIO_DEV)		+= gemini_gpio_dev.o
- 
- obj-$(CONFIG_PS3_FLASH)		+= ps3flash.o
-