From: Tianling Shen Date: Sat, 11 Oct 2025 09:04:07 +0000 (+0800) Subject: rockchip: backport driver updates for rk3528 X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=c7a26da60d894e1bb6acc4298ee1b54652e66230;p=openwrt%2Fopenwrt.git rockchip: backport driver updates for rk3528 Backport clk/mac/phy driver updates for rk3528. Signed-off-by: Tianling Shen Link: https://github.com/openwrt/openwrt/pull/20375 Signed-off-by: Hauke Mehrtens --- diff --git a/target/linux/rockchip/armv8/config-6.12 b/target/linux/rockchip/armv8/config-6.12 index 1200605efe..c67493cab2 100644 --- a/target/linux/rockchip/armv8/config-6.12 +++ b/target/linux/rockchip/armv8/config-6.12 @@ -128,6 +128,7 @@ CONFIG_CLK_RK3308=y CONFIG_CLK_RK3328=y CONFIG_CLK_RK3368=y CONFIG_CLK_RK3399=y +CONFIG_CLK_RK3528=y CONFIG_CLK_RK3568=y CONFIG_CLK_RK3576=y CONFIG_CLK_RK3588=y diff --git a/target/linux/rockchip/patches-6.12/032-18-v6.15-dt-bindings-clock-Document-clock-and-reset-unit-of-RK3528.patch b/target/linux/rockchip/patches-6.12/032-18-v6.15-dt-bindings-clock-Document-clock-and-reset-unit-of-RK3528.patch new file mode 100644 index 0000000000..af7ffc916c --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-18-v6.15-dt-bindings-clock-Document-clock-and-reset-unit-of-RK3528.patch @@ -0,0 +1,792 @@ +From e0c0a97bc308f71b0934e3637ac545ce65195df0 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Mon, 17 Feb 2025 06:11:42 +0000 +Subject: [PATCH] dt-bindings: clock: Document clock and reset unit of RK3528 + +There are two types of clocks in RK3528 SoC, CRU-managed and +SCMI-managed. Independent IDs are assigned to them. + +For the reset part, differing from previous Rockchip SoCs and +downstream bindings which embeds register offsets into the IDs, gapless +numbers starting from zero are used. + +Signed-off-by: Yao Zi +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org +Signed-off-by: Heiko Stuebner +--- + .../bindings/clock/rockchip,rk3528-cru.yaml | 64 +++ + .../dt-bindings/clock/rockchip,rk3528-cru.h | 453 ++++++++++++++++++ + .../dt-bindings/reset/rockchip,rk3528-cru.h | 241 ++++++++++ + 3 files changed, 758 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml + create mode 100644 include/dt-bindings/clock/rockchip,rk3528-cru.h + create mode 100644 include/dt-bindings/reset/rockchip,rk3528-cru.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml +@@ -0,0 +1,64 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip RK3528 Clock and Reset Controller ++ ++maintainers: ++ - Yao Zi ++ ++description: | ++ The RK3528 clock controller generates the clock and also implements a reset ++ controller for SoC peripherals. For example, it provides SCLK_UART0 and ++ PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART ++ module. ++ Each clock is assigned an identifier, consumer nodes can use it to specify ++ the clock. All available clock and reset IDs are defined in dt-binding ++ headers. ++ ++properties: ++ compatible: ++ const: rockchip,rk3528-cru ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: External 24MHz oscillator clock ++ - description: > ++ 50MHz clock generated by PHY module, for generating GMAC0 clocks only. ++ ++ clock-names: ++ items: ++ - const: xin24m ++ - const: gmac0 ++ ++ "#clock-cells": ++ const: 1 ++ ++ "#reset-cells": ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - "#clock-cells" ++ - "#reset-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ clock-controller@ff4a0000 { ++ compatible = "rockchip,rk3528-cru"; ++ reg = <0xff4a0000 0x30000>; ++ clocks = <&xin24m>, <&gmac0_clk>; ++ clock-names = "xin24m", "gmac0"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; +--- /dev/null ++++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h +@@ -0,0 +1,453 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ ++/* ++ * Copyright (c) 2022 Rockchip Electronics Co. Ltd. ++ * Copyright (c) 2024 Yao Zi ++ * Author: Joseph Chen ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H ++#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H ++ ++/* cru-clocks indices */ ++#define PLL_APLL 0 ++#define PLL_CPLL 1 ++#define PLL_GPLL 2 ++#define PLL_PPLL 3 ++#define PLL_DPLL 4 ++#define ARMCLK 5 ++#define XIN_OSC0_HALF 6 ++#define CLK_MATRIX_50M_SRC 7 ++#define CLK_MATRIX_100M_SRC 8 ++#define CLK_MATRIX_150M_SRC 9 ++#define CLK_MATRIX_200M_SRC 10 ++#define CLK_MATRIX_250M_SRC 11 ++#define CLK_MATRIX_300M_SRC 12 ++#define CLK_MATRIX_339M_SRC 13 ++#define CLK_MATRIX_400M_SRC 14 ++#define CLK_MATRIX_500M_SRC 15 ++#define CLK_MATRIX_600M_SRC 16 ++#define CLK_UART0_SRC 17 ++#define CLK_UART0_FRAC 18 ++#define SCLK_UART0 19 ++#define CLK_UART1_SRC 20 ++#define CLK_UART1_FRAC 21 ++#define SCLK_UART1 22 ++#define CLK_UART2_SRC 23 ++#define CLK_UART2_FRAC 24 ++#define SCLK_UART2 25 ++#define CLK_UART3_SRC 26 ++#define CLK_UART3_FRAC 27 ++#define SCLK_UART3 28 ++#define CLK_UART4_SRC 29 ++#define CLK_UART4_FRAC 30 ++#define SCLK_UART4 31 ++#define CLK_UART5_SRC 32 ++#define CLK_UART5_FRAC 33 ++#define SCLK_UART5 34 ++#define CLK_UART6_SRC 35 ++#define CLK_UART6_FRAC 36 ++#define SCLK_UART6 37 ++#define CLK_UART7_SRC 38 ++#define CLK_UART7_FRAC 39 ++#define SCLK_UART7 40 ++#define CLK_I2S0_2CH_SRC 41 ++#define CLK_I2S0_2CH_FRAC 42 ++#define MCLK_I2S0_2CH_SAI_SRC 43 ++#define CLK_I2S3_8CH_SRC 44 ++#define CLK_I2S3_8CH_FRAC 45 ++#define MCLK_I2S3_8CH_SAI_SRC 46 ++#define CLK_I2S1_8CH_SRC 47 ++#define CLK_I2S1_8CH_FRAC 48 ++#define MCLK_I2S1_8CH_SAI_SRC 49 ++#define CLK_I2S2_2CH_SRC 50 ++#define CLK_I2S2_2CH_FRAC 51 ++#define MCLK_I2S2_2CH_SAI_SRC 52 ++#define CLK_SPDIF_SRC 53 ++#define CLK_SPDIF_FRAC 54 ++#define MCLK_SPDIF_SRC 55 ++#define DCLK_VOP_SRC0 56 ++#define DCLK_VOP_SRC1 57 ++#define CLK_HSM 58 ++#define CLK_CORE_SRC_ACS 59 ++#define CLK_CORE_SRC_PVTMUX 60 ++#define CLK_CORE_SRC 61 ++#define CLK_CORE 62 ++#define ACLK_M_CORE_BIU 63 ++#define CLK_CORE_PVTPLL_SRC 64 ++#define PCLK_DBG 65 ++#define SWCLKTCK 66 ++#define CLK_SCANHS_CORE 67 ++#define CLK_SCANHS_ACLKM_CORE 68 ++#define CLK_SCANHS_PCLK_DBG 69 ++#define CLK_SCANHS_PCLK_CPU_BIU 70 ++#define PCLK_CPU_ROOT 71 ++#define PCLK_CORE_GRF 72 ++#define PCLK_DAPLITE_BIU 73 ++#define PCLK_CPU_BIU 74 ++#define CLK_REF_PVTPLL_CORE 75 ++#define ACLK_BUS_VOPGL_ROOT 76 ++#define ACLK_BUS_VOPGL_BIU 77 ++#define ACLK_BUS_H_ROOT 78 ++#define ACLK_BUS_H_BIU 79 ++#define ACLK_BUS_ROOT 80 ++#define HCLK_BUS_ROOT 81 ++#define PCLK_BUS_ROOT 82 ++#define ACLK_BUS_M_ROOT 83 ++#define ACLK_SYSMEM_BIU 84 ++#define CLK_TIMER_ROOT 85 ++#define ACLK_BUS_BIU 86 ++#define HCLK_BUS_BIU 87 ++#define PCLK_BUS_BIU 88 ++#define PCLK_DFT2APB 89 ++#define PCLK_BUS_GRF 90 ++#define ACLK_BUS_M_BIU 91 ++#define ACLK_GIC 92 ++#define ACLK_SPINLOCK 93 ++#define ACLK_DMAC 94 ++#define PCLK_TIMER 95 ++#define CLK_TIMER0 96 ++#define CLK_TIMER1 97 ++#define CLK_TIMER2 98 ++#define CLK_TIMER3 99 ++#define CLK_TIMER4 100 ++#define CLK_TIMER5 101 ++#define PCLK_JDBCK_DAP 102 ++#define CLK_JDBCK_DAP 103 ++#define PCLK_WDT_NS 104 ++#define TCLK_WDT_NS 105 ++#define HCLK_TRNG_NS 106 ++#define PCLK_UART0 107 ++#define PCLK_DMA2DDR 108 ++#define ACLK_DMA2DDR 109 ++#define PCLK_PWM0 110 ++#define CLK_PWM0 111 ++#define CLK_CAPTURE_PWM0 112 ++#define PCLK_PWM1 113 ++#define CLK_PWM1 114 ++#define CLK_CAPTURE_PWM1 115 ++#define PCLK_SCR 116 ++#define ACLK_DCF 117 ++#define PCLK_INTMUX 118 ++#define CLK_PPLL_I 119 ++#define CLK_PPLL_MUX 120 ++#define CLK_PPLL_100M_MATRIX 121 ++#define CLK_PPLL_50M_MATRIX 122 ++#define CLK_REF_PCIE_INNER_PHY 123 ++#define CLK_REF_PCIE_100M_PHY 124 ++#define ACLK_VPU_L_ROOT 125 ++#define CLK_GMAC1_VPU_25M 126 ++#define CLK_PPLL_125M_MATRIX 127 ++#define ACLK_VPU_ROOT 128 ++#define HCLK_VPU_ROOT 129 ++#define PCLK_VPU_ROOT 130 ++#define ACLK_VPU_BIU 131 ++#define HCLK_VPU_BIU 132 ++#define PCLK_VPU_BIU 133 ++#define ACLK_VPU 134 ++#define HCLK_VPU 135 ++#define PCLK_CRU_PCIE 136 ++#define PCLK_VPU_GRF 137 ++#define HCLK_SFC 138 ++#define SCLK_SFC 139 ++#define CCLK_SRC_EMMC 140 ++#define HCLK_EMMC 141 ++#define ACLK_EMMC 142 ++#define BCLK_EMMC 143 ++#define TCLK_EMMC 144 ++#define PCLK_GPIO1 145 ++#define DBCLK_GPIO1 146 ++#define ACLK_VPU_L_BIU 147 ++#define PCLK_VPU_IOC 148 ++#define HCLK_SAI_I2S0 149 ++#define MCLK_SAI_I2S0 150 ++#define HCLK_SAI_I2S2 151 ++#define MCLK_SAI_I2S2 152 ++#define PCLK_ACODEC 153 ++#define MCLK_ACODEC_TX 154 ++#define PCLK_GPIO3 155 ++#define DBCLK_GPIO3 156 ++#define PCLK_SPI1 157 ++#define CLK_SPI1 158 ++#define SCLK_IN_SPI1 159 ++#define PCLK_UART2 160 ++#define PCLK_UART5 161 ++#define PCLK_UART6 162 ++#define PCLK_UART7 163 ++#define PCLK_I2C3 164 ++#define CLK_I2C3 165 ++#define PCLK_I2C5 166 ++#define CLK_I2C5 167 ++#define PCLK_I2C6 168 ++#define CLK_I2C6 169 ++#define ACLK_MAC_VPU 170 ++#define PCLK_MAC_VPU 171 ++#define CLK_GMAC1_RMII_VPU 172 ++#define CLK_GMAC1_SRC_VPU 173 ++#define PCLK_PCIE 174 ++#define CLK_PCIE_AUX 175 ++#define ACLK_PCIE 176 ++#define HCLK_PCIE_SLV 177 ++#define HCLK_PCIE_DBI 178 ++#define PCLK_PCIE_PHY 179 ++#define PCLK_PIPE_GRF 180 ++#define CLK_PIPE_USB3OTG_COMBO 181 ++#define CLK_UTMI_USB3OTG 182 ++#define CLK_PCIE_PIPE_PHY 183 ++#define CCLK_SRC_SDIO0 184 ++#define HCLK_SDIO0 185 ++#define CCLK_SRC_SDIO1 186 ++#define HCLK_SDIO1 187 ++#define CLK_TS_0 188 ++#define CLK_TS_1 189 ++#define PCLK_CAN2 190 ++#define CLK_CAN2 191 ++#define PCLK_CAN3 192 ++#define CLK_CAN3 193 ++#define PCLK_SARADC 194 ++#define CLK_SARADC 195 ++#define PCLK_TSADC 196 ++#define CLK_TSADC 197 ++#define CLK_TSADC_TSEN 198 ++#define ACLK_USB3OTG 199 ++#define CLK_REF_USB3OTG 200 ++#define CLK_SUSPEND_USB3OTG 201 ++#define ACLK_GPU_ROOT 202 ++#define PCLK_GPU_ROOT 203 ++#define ACLK_GPU_BIU 204 ++#define PCLK_GPU_BIU 205 ++#define ACLK_GPU 206 ++#define CLK_GPU_PVTPLL_SRC 207 ++#define ACLK_GPU_MALI 208 ++#define HCLK_RKVENC_ROOT 209 ++#define ACLK_RKVENC_ROOT 210 ++#define PCLK_RKVENC_ROOT 211 ++#define HCLK_RKVENC_BIU 212 ++#define ACLK_RKVENC_BIU 213 ++#define PCLK_RKVENC_BIU 214 ++#define HCLK_RKVENC 215 ++#define ACLK_RKVENC 216 ++#define CLK_CORE_RKVENC 217 ++#define HCLK_SAI_I2S1 218 ++#define MCLK_SAI_I2S1 219 ++#define PCLK_I2C1 220 ++#define CLK_I2C1 221 ++#define PCLK_I2C0 222 ++#define CLK_I2C0 223 ++#define CLK_UART_JTAG 224 ++#define PCLK_SPI0 225 ++#define CLK_SPI0 226 ++#define SCLK_IN_SPI0 227 ++#define PCLK_GPIO4 228 ++#define DBCLK_GPIO4 229 ++#define PCLK_RKVENC_IOC 230 ++#define HCLK_SPDIF 231 ++#define MCLK_SPDIF 232 ++#define HCLK_PDM 233 ++#define MCLK_PDM 234 ++#define PCLK_UART1 235 ++#define PCLK_UART3 236 ++#define PCLK_RKVENC_GRF 237 ++#define PCLK_CAN0 238 ++#define CLK_CAN0 239 ++#define PCLK_CAN1 240 ++#define CLK_CAN1 241 ++#define ACLK_VO_ROOT 242 ++#define HCLK_VO_ROOT 243 ++#define PCLK_VO_ROOT 244 ++#define ACLK_VO_BIU 245 ++#define HCLK_VO_BIU 246 ++#define PCLK_VO_BIU 247 ++#define HCLK_RGA2E 248 ++#define ACLK_RGA2E 249 ++#define CLK_CORE_RGA2E 250 ++#define HCLK_VDPP 251 ++#define ACLK_VDPP 252 ++#define CLK_CORE_VDPP 253 ++#define PCLK_VO_GRF 254 ++#define PCLK_CRU 255 ++#define ACLK_VOP_ROOT 256 ++#define ACLK_VOP_BIU 257 ++#define HCLK_VOP 258 ++#define DCLK_VOP0 259 ++#define DCLK_VOP1 260 ++#define ACLK_VOP 261 ++#define PCLK_HDMI 262 ++#define CLK_SFR_HDMI 263 ++#define CLK_CEC_HDMI 264 ++#define CLK_SPDIF_HDMI 265 ++#define CLK_HDMIPHY_TMDSSRC 266 ++#define CLK_HDMIPHY_PREP 267 ++#define PCLK_HDMIPHY 268 ++#define HCLK_HDCP_KEY 269 ++#define ACLK_HDCP 270 ++#define HCLK_HDCP 271 ++#define PCLK_HDCP 272 ++#define HCLK_CVBS 273 ++#define DCLK_CVBS 274 ++#define DCLK_4X_CVBS 275 ++#define ACLK_JPEG_DECODER 276 ++#define HCLK_JPEG_DECODER 277 ++#define ACLK_VO_L_ROOT 278 ++#define ACLK_VO_L_BIU 279 ++#define ACLK_MAC_VO 280 ++#define PCLK_MAC_VO 281 ++#define CLK_GMAC0_SRC 282 ++#define CLK_GMAC0_RMII_50M 283 ++#define CLK_GMAC0_TX 284 ++#define CLK_GMAC0_RX 285 ++#define ACLK_JPEG_ROOT 286 ++#define ACLK_JPEG_BIU 287 ++#define HCLK_SAI_I2S3 288 ++#define MCLK_SAI_I2S3 289 ++#define CLK_MACPHY 290 ++#define PCLK_VCDCPHY 291 ++#define PCLK_GPIO2 292 ++#define DBCLK_GPIO2 293 ++#define PCLK_VO_IOC 294 ++#define CCLK_SRC_SDMMC0 295 ++#define HCLK_SDMMC0 296 ++#define PCLK_OTPC_NS 297 ++#define CLK_SBPI_OTPC_NS 298 ++#define CLK_USER_OTPC_NS 299 ++#define CLK_HDMIHDP0 300 ++#define HCLK_USBHOST 301 ++#define HCLK_USBHOST_ARB 302 ++#define CLK_USBHOST_OHCI 303 ++#define CLK_USBHOST_UTMI 304 ++#define PCLK_UART4 305 ++#define PCLK_I2C4 306 ++#define CLK_I2C4 307 ++#define PCLK_I2C7 308 ++#define CLK_I2C7 309 ++#define PCLK_USBPHY 310 ++#define CLK_REF_USBPHY 311 ++#define HCLK_RKVDEC_ROOT 312 ++#define ACLK_RKVDEC_ROOT_NDFT 313 ++#define PCLK_DDRPHY_CRU 314 ++#define HCLK_RKVDEC_BIU 315 ++#define ACLK_RKVDEC_BIU 316 ++#define ACLK_RKVDEC 317 ++#define HCLK_RKVDEC 318 ++#define CLK_HEVC_CA_RKVDEC 319 ++#define ACLK_RKVDEC_PVTMUX_ROOT 320 ++#define CLK_RKVDEC_PVTPLL_SRC 321 ++#define PCLK_DDR_ROOT 322 ++#define PCLK_DDR_BIU 323 ++#define PCLK_DDRC 324 ++#define PCLK_DDRMON 325 ++#define CLK_TIMER_DDRMON 326 ++#define PCLK_MSCH_BIU 327 ++#define PCLK_DDR_GRF 328 ++#define PCLK_DDR_HWLP 329 ++#define PCLK_DDRPHY 330 ++#define CLK_MSCH_BIU 331 ++#define ACLK_DDR_UPCTL 332 ++#define CLK_DDR_UPCTL 333 ++#define CLK_DDRMON 334 ++#define ACLK_DDR_SCRAMBLE 335 ++#define ACLK_SPLIT 336 ++#define CLK_DDRC_SRC 337 ++#define CLK_DDR_PHY 338 ++#define PCLK_OTPC_S 339 ++#define CLK_SBPI_OTPC_S 340 ++#define CLK_USER_OTPC_S 341 ++#define PCLK_KEYREADER 342 ++#define PCLK_BUS_SGRF 343 ++#define PCLK_STIMER 344 ++#define CLK_STIMER0 345 ++#define CLK_STIMER1 346 ++#define PCLK_WDT_S 347 ++#define TCLK_WDT_S 348 ++#define HCLK_TRNG_S 349 ++#define HCLK_BOOTROM 350 ++#define PCLK_DCF 351 ++#define ACLK_SYSMEM 352 ++#define HCLK_TSP 353 ++#define ACLK_TSP 354 ++#define CLK_CORE_TSP 355 ++#define CLK_OTPC_ARB 356 ++#define PCLK_OTP_MASK 357 ++#define CLK_PMC_OTP 358 ++#define PCLK_PMU_ROOT 359 ++#define HCLK_PMU_ROOT 360 ++#define PCLK_I2C2 361 ++#define CLK_I2C2 362 ++#define HCLK_PMU_BIU 363 ++#define PCLK_PMU_BIU 364 ++#define FCLK_MCU 365 ++#define RTC_CLK_MCU 366 ++#define PCLK_OSCCHK 367 ++#define CLK_PMU_MCU_JTAG 368 ++#define PCLK_PMU 369 ++#define PCLK_GPIO0 370 ++#define DBCLK_GPIO0 371 ++#define XIN_OSC0_DIV 372 ++#define CLK_DEEPSLOW 373 ++#define CLK_DDR_FAIL_SAFE 374 ++#define PCLK_PMU_HP_TIMER 375 ++#define CLK_PMU_HP_TIMER 376 ++#define CLK_PMU_32K_HP_TIMER 377 ++#define PCLK_PMU_IOC 378 ++#define PCLK_PMU_CRU 379 ++#define PCLK_PMU_GRF 380 ++#define PCLK_PMU_WDT 381 ++#define TCLK_PMU_WDT 382 ++#define PCLK_PMU_MAILBOX 383 ++#define PCLK_SCRKEYGEN 384 ++#define CLK_SCRKEYGEN 385 ++#define CLK_PVTM_OSCCHK 386 ++#define CLK_REFOUT 387 ++#define CLK_PVTM_PMU 388 ++#define PCLK_PVTM_PMU 389 ++#define PCLK_PMU_SGRF 390 ++#define HCLK_PMU_SRAM 391 ++#define CLK_UART0 392 ++#define CLK_UART1 393 ++#define CLK_UART2 394 ++#define CLK_UART3 395 ++#define CLK_UART4 396 ++#define CLK_UART5 397 ++#define CLK_UART6 398 ++#define CLK_UART7 399 ++#define MCLK_I2S0_2CH_SAI_SRC_PRE 400 ++#define MCLK_I2S1_8CH_SAI_SRC_PRE 401 ++#define MCLK_I2S2_2CH_SAI_SRC_PRE 402 ++#define MCLK_I2S3_8CH_SAI_SRC_PRE 403 ++#define MCLK_SDPDIF_SRC_PRE 404 ++ ++/* scmi-clocks indices */ ++#define SCMI_PCLK_KEYREADER 0 ++#define SCMI_HCLK_KLAD 1 ++#define SCMI_PCLK_KLAD 2 ++#define SCMI_HCLK_TRNG_S 3 ++#define SCMI_HCLK_CRYPTO_S 4 ++#define SCMI_PCLK_WDT_S 5 ++#define SCMI_TCLK_WDT_S 6 ++#define SCMI_PCLK_STIMER 7 ++#define SCMI_CLK_STIMER0 8 ++#define SCMI_CLK_STIMER1 9 ++#define SCMI_PCLK_OTP_MASK 10 ++#define SCMI_PCLK_OTPC_S 11 ++#define SCMI_CLK_SBPI_OTPC_S 12 ++#define SCMI_CLK_USER_OTPC_S 13 ++#define SCMI_CLK_PMC_OTP 14 ++#define SCMI_CLK_OTPC_ARB 15 ++#define SCMI_CLK_CORE_TSP 16 ++#define SCMI_ACLK_TSP 17 ++#define SCMI_HCLK_TSP 18 ++#define SCMI_PCLK_DCF 19 ++#define SCMI_CLK_DDR 20 ++#define SCMI_CLK_CPU 21 ++#define SCMI_CLK_GPU 22 ++#define SCMI_CORE_CRYPTO 23 ++#define SCMI_ACLK_CRYPTO 24 ++#define SCMI_PKA_CRYPTO 25 ++#define SCMI_HCLK_CRYPTO 26 ++#define SCMI_CORE_CRYPTO_S 27 ++#define SCMI_ACLK_CRYPTO_S 28 ++#define SCMI_PKA_CRYPTO_S 29 ++#define SCMI_CORE_KLAD 30 ++#define SCMI_ACLK_KLAD 31 ++#define SCMI_HCLK_TRNG 32 ++ ++#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H +--- /dev/null ++++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h +@@ -0,0 +1,241 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ ++/* ++ * Copyright (c) 2022 Rockchip Electronics Co. Ltd. ++ * Copyright (c) 2024 Yao Zi ++ * Author: Joseph Chen ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H ++#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H ++ ++#define SRST_CORE0_PO 0 ++#define SRST_CORE1_PO 1 ++#define SRST_CORE2_PO 2 ++#define SRST_CORE3_PO 3 ++#define SRST_CORE0 4 ++#define SRST_CORE1 5 ++#define SRST_CORE2 6 ++#define SRST_CORE3 7 ++#define SRST_NL2 8 ++#define SRST_CORE_BIU 9 ++#define SRST_CORE_CRYPTO 10 ++#define SRST_P_DBG 11 ++#define SRST_POT_DBG 12 ++#define SRST_NT_DBG 13 ++#define SRST_P_CORE_GRF 14 ++#define SRST_P_DAPLITE_BIU 15 ++#define SRST_P_CPU_BIU 16 ++#define SRST_REF_PVTPLL_CORE 17 ++#define SRST_A_BUS_VOPGL_BIU 18 ++#define SRST_A_BUS_H_BIU 19 ++#define SRST_A_SYSMEM_BIU 20 ++#define SRST_A_BUS_BIU 21 ++#define SRST_H_BUS_BIU 22 ++#define SRST_P_BUS_BIU 23 ++#define SRST_P_DFT2APB 24 ++#define SRST_P_BUS_GRF 25 ++#define SRST_A_BUS_M_BIU 26 ++#define SRST_A_GIC 27 ++#define SRST_A_SPINLOCK 28 ++#define SRST_A_DMAC 29 ++#define SRST_P_TIMER 30 ++#define SRST_TIMER0 31 ++#define SRST_TIMER1 32 ++#define SRST_TIMER2 33 ++#define SRST_TIMER3 34 ++#define SRST_TIMER4 35 ++#define SRST_TIMER5 36 ++#define SRST_P_JDBCK_DAP 37 ++#define SRST_JDBCK_DAP 38 ++#define SRST_P_WDT_NS 39 ++#define SRST_T_WDT_NS 40 ++#define SRST_H_TRNG_NS 41 ++#define SRST_P_UART0 42 ++#define SRST_S_UART0 43 ++#define SRST_PKA_CRYPTO 44 ++#define SRST_A_CRYPTO 45 ++#define SRST_H_CRYPTO 46 ++#define SRST_P_DMA2DDR 47 ++#define SRST_A_DMA2DDR 48 ++#define SRST_P_PWM0 49 ++#define SRST_PWM0 50 ++#define SRST_P_PWM1 51 ++#define SRST_PWM1 52 ++#define SRST_P_SCR 53 ++#define SRST_A_DCF 54 ++#define SRST_P_INTMUX 55 ++#define SRST_A_VPU_BIU 56 ++#define SRST_H_VPU_BIU 57 ++#define SRST_P_VPU_BIU 58 ++#define SRST_A_VPU 59 ++#define SRST_H_VPU 60 ++#define SRST_P_CRU_PCIE 61 ++#define SRST_P_VPU_GRF 62 ++#define SRST_H_SFC 63 ++#define SRST_S_SFC 64 ++#define SRST_C_EMMC 65 ++#define SRST_H_EMMC 66 ++#define SRST_A_EMMC 67 ++#define SRST_B_EMMC 68 ++#define SRST_T_EMMC 69 ++#define SRST_P_GPIO1 70 ++#define SRST_DB_GPIO1 71 ++#define SRST_A_VPU_L_BIU 72 ++#define SRST_P_VPU_IOC 73 ++#define SRST_H_SAI_I2S0 74 ++#define SRST_M_SAI_I2S0 75 ++#define SRST_H_SAI_I2S2 76 ++#define SRST_M_SAI_I2S2 77 ++#define SRST_P_ACODEC 78 ++#define SRST_P_GPIO3 79 ++#define SRST_DB_GPIO3 80 ++#define SRST_P_SPI1 81 ++#define SRST_SPI1 82 ++#define SRST_P_UART2 83 ++#define SRST_S_UART2 84 ++#define SRST_P_UART5 85 ++#define SRST_S_UART5 86 ++#define SRST_P_UART6 87 ++#define SRST_S_UART6 88 ++#define SRST_P_UART7 89 ++#define SRST_S_UART7 90 ++#define SRST_P_I2C3 91 ++#define SRST_I2C3 92 ++#define SRST_P_I2C5 93 ++#define SRST_I2C5 94 ++#define SRST_P_I2C6 95 ++#define SRST_I2C6 96 ++#define SRST_A_MAC 97 ++#define SRST_P_PCIE 98 ++#define SRST_PCIE_PIPE_PHY 99 ++#define SRST_PCIE_POWER_UP 100 ++#define SRST_P_PCIE_PHY 101 ++#define SRST_P_PIPE_GRF 102 ++#define SRST_H_SDIO0 103 ++#define SRST_H_SDIO1 104 ++#define SRST_TS_0 105 ++#define SRST_TS_1 106 ++#define SRST_P_CAN2 107 ++#define SRST_CAN2 108 ++#define SRST_P_CAN3 109 ++#define SRST_CAN3 110 ++#define SRST_P_SARADC 111 ++#define SRST_SARADC 112 ++#define SRST_SARADC_PHY 113 ++#define SRST_P_TSADC 114 ++#define SRST_TSADC 115 ++#define SRST_A_USB3OTG 116 ++#define SRST_A_GPU_BIU 117 ++#define SRST_P_GPU_BIU 118 ++#define SRST_A_GPU 119 ++#define SRST_REF_PVTPLL_GPU 120 ++#define SRST_H_RKVENC_BIU 121 ++#define SRST_A_RKVENC_BIU 122 ++#define SRST_P_RKVENC_BIU 123 ++#define SRST_H_RKVENC 124 ++#define SRST_A_RKVENC 125 ++#define SRST_CORE_RKVENC 126 ++#define SRST_H_SAI_I2S1 127 ++#define SRST_M_SAI_I2S1 128 ++#define SRST_P_I2C1 129 ++#define SRST_I2C1 130 ++#define SRST_P_I2C0 131 ++#define SRST_I2C0 132 ++#define SRST_P_SPI0 133 ++#define SRST_SPI0 134 ++#define SRST_P_GPIO4 135 ++#define SRST_DB_GPIO4 136 ++#define SRST_P_RKVENC_IOC 137 ++#define SRST_H_SPDIF 138 ++#define SRST_M_SPDIF 139 ++#define SRST_H_PDM 140 ++#define SRST_M_PDM 141 ++#define SRST_P_UART1 142 ++#define SRST_S_UART1 143 ++#define SRST_P_UART3 144 ++#define SRST_S_UART3 145 ++#define SRST_P_RKVENC_GRF 146 ++#define SRST_P_CAN0 147 ++#define SRST_CAN0 148 ++#define SRST_P_CAN1 149 ++#define SRST_CAN1 150 ++#define SRST_A_VO_BIU 151 ++#define SRST_H_VO_BIU 152 ++#define SRST_P_VO_BIU 153 ++#define SRST_H_RGA2E 154 ++#define SRST_A_RGA2E 155 ++#define SRST_CORE_RGA2E 156 ++#define SRST_H_VDPP 157 ++#define SRST_A_VDPP 158 ++#define SRST_CORE_VDPP 159 ++#define SRST_P_VO_GRF 160 ++#define SRST_P_CRU 161 ++#define SRST_A_VOP_BIU 162 ++#define SRST_H_VOP 163 ++#define SRST_D_VOP0 164 ++#define SRST_D_VOP1 165 ++#define SRST_A_VOP 166 ++#define SRST_P_HDMI 167 ++#define SRST_HDMI 168 ++#define SRST_P_HDMIPHY 169 ++#define SRST_H_HDCP_KEY 170 ++#define SRST_A_HDCP 171 ++#define SRST_H_HDCP 172 ++#define SRST_P_HDCP 173 ++#define SRST_H_CVBS 174 ++#define SRST_D_CVBS_VOP 175 ++#define SRST_D_4X_CVBS_VOP 176 ++#define SRST_A_JPEG_DECODER 177 ++#define SRST_H_JPEG_DECODER 178 ++#define SRST_A_VO_L_BIU 179 ++#define SRST_A_MAC_VO 180 ++#define SRST_A_JPEG_BIU 181 ++#define SRST_H_SAI_I2S3 182 ++#define SRST_M_SAI_I2S3 183 ++#define SRST_MACPHY 184 ++#define SRST_P_VCDCPHY 185 ++#define SRST_P_GPIO2 186 ++#define SRST_DB_GPIO2 187 ++#define SRST_P_VO_IOC 188 ++#define SRST_H_SDMMC0 189 ++#define SRST_P_OTPC_NS 190 ++#define SRST_SBPI_OTPC_NS 191 ++#define SRST_USER_OTPC_NS 192 ++#define SRST_HDMIHDP0 193 ++#define SRST_H_USBHOST 194 ++#define SRST_H_USBHOST_ARB 195 ++#define SRST_HOST_UTMI 196 ++#define SRST_P_UART4 197 ++#define SRST_S_UART4 198 ++#define SRST_P_I2C4 199 ++#define SRST_I2C4 200 ++#define SRST_P_I2C7 201 ++#define SRST_I2C7 202 ++#define SRST_P_USBPHY 203 ++#define SRST_USBPHY_POR 204 ++#define SRST_USBPHY_OTG 205 ++#define SRST_USBPHY_HOST 206 ++#define SRST_P_DDRPHY_CRU 207 ++#define SRST_H_RKVDEC_BIU 208 ++#define SRST_A_RKVDEC_BIU 209 ++#define SRST_A_RKVDEC 210 ++#define SRST_H_RKVDEC 211 ++#define SRST_HEVC_CA_RKVDEC 212 ++#define SRST_REF_PVTPLL_RKVDEC 213 ++#define SRST_P_DDR_BIU 214 ++#define SRST_P_DDRC 215 ++#define SRST_P_DDRMON 216 ++#define SRST_TIMER_DDRMON 217 ++#define SRST_P_MSCH_BIU 218 ++#define SRST_P_DDR_GRF 219 ++#define SRST_P_DDR_HWLP 220 ++#define SRST_P_DDRPHY 221 ++#define SRST_MSCH_BIU 222 ++#define SRST_A_DDR_UPCTL 223 ++#define SRST_DDR_UPCTL 224 ++#define SRST_DDRMON 225 ++#define SRST_A_DDR_SCRAMBLE 226 ++#define SRST_A_SPLIT 227 ++#define SRST_DDR_PHY 228 ++ ++#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H diff --git a/target/linux/rockchip/patches-6.12/032-19-v6.15-clk-rockchip-Add-PLL-flag-ROCKCHIP_PLL_FIXED_MODE.patch b/target/linux/rockchip/patches-6.12/032-19-v6.15-clk-rockchip-Add-PLL-flag-ROCKCHIP_PLL_FIXED_MODE.patch new file mode 100644 index 0000000000..59e08aa1d6 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-19-v6.15-clk-rockchip-Add-PLL-flag-ROCKCHIP_PLL_FIXED_MODE.patch @@ -0,0 +1,54 @@ +From 651aabc9fb0f354ad2ba5fd06a6011e652447489 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Mon, 17 Feb 2025 06:11:43 +0000 +Subject: [PATCH] clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE + +RK3528 comes with a new PLL variant: its "PPLL", which mainly generates +clocks for the PCIe controller, operates in normal mode only. Let's +describe it with flag ROCKCHIP_PLL_FIXED_MODE and handle it in code. + +Signed-off-by: Yao Zi +Link: https://lore.kernel.org/r/20250217061142.38480-7-ziyao@disroot.org +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-pll.c | 10 ++++++---- + drivers/clk/rockchip/clk.h | 2 ++ + 2 files changed, 8 insertions(+), 4 deletions(-) + +--- a/drivers/clk/rockchip/clk-pll.c ++++ b/drivers/clk/rockchip/clk-pll.c +@@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_param + rockchip_rk3036_pll_get_params(pll, &cur); + cur.rate = 0; + +- cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); +- if (cur_parent == PLL_MODE_NORM) { +- pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); +- rate_change_remuxed = 1; ++ if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { ++ cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); ++ if (cur_parent == PLL_MODE_NORM) { ++ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); ++ rate_change_remuxed = 1; ++ } + } + + /* update pll values */ +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -469,6 +469,7 @@ struct rockchip_pll_rate_table { + * Flags: + * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the + * rate_table parameters and ajust them if necessary. ++ * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only + */ + struct rockchip_pll_clock { + unsigned int id; +@@ -486,6 +487,7 @@ struct rockchip_pll_clock { + }; + + #define ROCKCHIP_PLL_SYNC_RATE BIT(0) ++#define ROCKCHIP_PLL_FIXED_MODE BIT(1) + + #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ + _lshift, _pflags, _rtable) \ diff --git a/target/linux/rockchip/patches-6.12/032-20-v6.15-clk-rockchip-Add-clock-controller-driver-for-RK3528-SoC.patch b/target/linux/rockchip/patches-6.12/032-20-v6.15-clk-rockchip-Add-clock-controller-driver-for-RK3528-SoC.patch new file mode 100644 index 0000000000..b69acb76f6 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-20-v6.15-clk-rockchip-Add-clock-controller-driver-for-RK3528-SoC.patch @@ -0,0 +1,1193 @@ +From 5d0eb375e6857d270f6376d161ef02a1b7183fa2 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Mon, 17 Feb 2025 06:11:44 +0000 +Subject: [PATCH] clk: rockchip: Add clock controller driver for RK3528 SoC + +Add clock tree definition for RK3528. Similar to previous Rockchip +SoCs, clock controller of RK3528 is combined with the reset controller. +We omit the reset part for now since it's hard to test it without +support for other basic peripherals. + +Signed-off-by: Yao Zi +Link: https://lore.kernel.org/r/20250217061142.38480-8-ziyao@disroot.org +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/Kconfig | 7 + + drivers/clk/rockchip/Makefile | 1 + + drivers/clk/rockchip/clk-rk3528.c | 1114 +++++++++++++++++++++++++++++ + drivers/clk/rockchip/clk.h | 20 + + 4 files changed, 1142 insertions(+) + create mode 100644 drivers/clk/rockchip/clk-rk3528.c + +--- a/drivers/clk/rockchip/Kconfig ++++ b/drivers/clk/rockchip/Kconfig +@@ -93,6 +93,13 @@ config CLK_RK3399 + help + Build the driver for RK3399 Clock Driver. + ++config CLK_RK3528 ++ bool "Rockchip RK3528 clock controller support" ++ depends on ARM64 || COMPILE_TEST ++ default y ++ help ++ Build the driver for RK3528 Clock Controller. ++ + config CLK_RK3568 + bool "Rockchip RK3568 clock controller support" + depends on ARM64 || COMPILE_TEST +--- a/drivers/clk/rockchip/Makefile ++++ b/drivers/clk/rockchip/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-r + obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o + obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o + obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o ++obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o + obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o + obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o + obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o +--- /dev/null ++++ b/drivers/clk/rockchip/clk-rk3528.c +@@ -0,0 +1,1114 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 Rockchip Electronics Co. Ltd. ++ * Copyright (c) 2024 Yao Zi ++ * Author: Joseph Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clk.h" ++ ++#define RK3528_GRF_SOC_STATUS0 0x1a0 ++ ++enum rk3528_plls { ++ apll, cpll, gpll, ppll, dpll, ++}; ++ ++static struct rockchip_pll_rate_table rk3528_pll_rates[] = { ++ RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */ ++ RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0), ++ RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */ ++ RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */ ++ RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0), ++ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), ++ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), ++ RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), ++ RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), ++ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), ++ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), ++ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), ++ RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0), ++ { /* sentinel */ }, ++}; ++ ++#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f ++#define RK3528_DIV_ACLK_M_CORE_SHIFT 11 ++#define RK3528_DIV_PCLK_DBG_MASK 0x1f ++#define RK3528_DIV_PCLK_DBG_SHIFT 1 ++ ++#define RK3528_CLKSEL39(_aclk_m_core) \ ++{ \ ++ .reg = RK3528_CLKSEL_CON(39), \ ++ .val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \ ++ RK3528_DIV_ACLK_M_CORE_SHIFT), \ ++} ++ ++#define RK3528_CLKSEL40(_pclk_dbg) \ ++{ \ ++ .reg = RK3528_CLKSEL_CON(40), \ ++ .val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \ ++ RK3528_DIV_PCLK_DBG_SHIFT), \ ++} ++ ++#define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg) \ ++{ \ ++ .prate = _prate, \ ++ .divs = { \ ++ RK3528_CLKSEL39(_aclk_m_core), \ ++ RK3528_CLKSEL40(_pclk_dbg), \ ++ }, \ ++} ++ ++static struct rockchip_cpuclk_rate_table rk3528_cpuclk_rates[] __initdata = { ++ RK3528_CPUCLK_RATE(1896000000, 1, 13), ++ RK3528_CPUCLK_RATE(1800000000, 1, 12), ++ RK3528_CPUCLK_RATE(1704000000, 1, 11), ++ RK3528_CPUCLK_RATE(1608000000, 1, 11), ++ RK3528_CPUCLK_RATE(1512000000, 1, 11), ++ RK3528_CPUCLK_RATE(1416000000, 1, 9), ++ RK3528_CPUCLK_RATE(1296000000, 1, 8), ++ RK3528_CPUCLK_RATE(1200000000, 1, 8), ++ RK3528_CPUCLK_RATE(1188000000, 1, 8), ++ RK3528_CPUCLK_RATE(1092000000, 1, 7), ++ RK3528_CPUCLK_RATE(1008000000, 1, 6), ++ RK3528_CPUCLK_RATE(1000000000, 1, 6), ++ RK3528_CPUCLK_RATE(996000000, 1, 6), ++ RK3528_CPUCLK_RATE(960000000, 1, 6), ++ RK3528_CPUCLK_RATE(912000000, 1, 6), ++ RK3528_CPUCLK_RATE(816000000, 1, 5), ++ RK3528_CPUCLK_RATE(600000000, 1, 3), ++ RK3528_CPUCLK_RATE(594000000, 1, 3), ++ RK3528_CPUCLK_RATE(408000000, 1, 2), ++ RK3528_CPUCLK_RATE(312000000, 1, 2), ++ RK3528_CPUCLK_RATE(216000000, 1, 1), ++ RK3528_CPUCLK_RATE(96000000, 1, 0), ++}; ++ ++static const struct rockchip_cpuclk_reg_data rk3528_cpuclk_data = { ++ .core_reg[0] = RK3528_CLKSEL_CON(39), ++ .div_core_shift[0] = 5, ++ .div_core_mask[0] = 0x1f, ++ .num_cores = 1, ++ .mux_core_alt = 1, ++ .mux_core_main = 0, ++ .mux_core_shift = 10, ++ .mux_core_mask = 0x1, ++}; ++ ++PNAME(mux_pll_p) = { "xin24m" }; ++PNAME(mux_armclk) = { "apll", "gpll" }; ++PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" }; ++PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" }; ++PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; ++PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", ++ "xin24m" }; ++PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", ++ "xin24m" }; ++PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src", ++ "xin24m" }; ++PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", ++ "clk_50m_src", "xin24m" }; ++PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", ++ "clk_100m_src", "xin24m" }; ++PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", ++ "clk_100m_src", "xin24m" }; ++PNAME(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src", ++ "clk_100m_src", "xin24m" }; ++PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", ++ "clk_100m_src", "xin24m" }; ++PNAME(mux_600m_300m_200m_24m_p) = { "clk_600m_src", "clk_300m_src", ++ "clk_200m_src", "xin24m" }; ++PNAME(aclk_gpu_p) = { "aclk_gpu_root", ++ "clk_gpu_pvtpll_src" }; ++PNAME(aclk_rkvdec_pvtmux_root_p) = { "aclk_rkvdec_root", ++ "clk_rkvdec_pvtpll_src" }; ++PNAME(clk_i2c2_p) = { "clk_200m_src", "clk_100m_src", ++ "xin24m", "clk_32k" }; ++PNAME(clk_ref_pcie_inner_phy_p) = { "clk_ppll_100m_src", "xin24m" }; ++PNAME(dclk_vop0_p) = { "dclk_vop_src0", ++ "clk_hdmiphy_pixel_io" }; ++PNAME(mclk_i2s0_2ch_sai_src_p) = { "clk_i2s0_2ch_src", ++ "clk_i2s0_2ch_frac", "xin12m" }; ++PNAME(mclk_i2s1_8ch_sai_src_p) = { "clk_i2s1_8ch_src", ++ "clk_i2s1_8ch_frac", "xin12m" }; ++PNAME(mclk_i2s2_2ch_sai_src_p) = { "clk_i2s2_2ch_src", ++ "clk_i2s2_2ch_frac", "xin12m" }; ++PNAME(mclk_i2s3_8ch_sai_src_p) = { "clk_i2s3_8ch_src", ++ "clk_i2s3_8ch_frac", "xin12m" }; ++PNAME(mclk_sai_i2s0_p) = { "mclk_i2s0_2ch_sai_src", ++ "i2s0_mclkin" }; ++PNAME(mclk_sai_i2s1_p) = { "mclk_i2s1_8ch_sai_src", ++ "i2s1_mclkin" }; ++PNAME(mclk_spdif_src_p) = { "clk_spdif_src", "clk_spdif_frac", ++ "xin12m" }; ++PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", ++ "xin24m" }; ++PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", ++ "xin24m" }; ++PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", ++ "xin24m" }; ++PNAME(sclk_uart3_src_p) = { "clk_uart3_src", "clk_uart3_frac", ++ "xin24m" }; ++PNAME(sclk_uart4_src_p) = { "clk_uart4_src", "clk_uart4_frac", ++ "xin24m" }; ++PNAME(sclk_uart5_src_p) = { "clk_uart5_src", "clk_uart5_frac", ++ "xin24m" }; ++PNAME(sclk_uart6_src_p) = { "clk_uart6_src", "clk_uart6_frac", ++ "xin24m" }; ++PNAME(sclk_uart7_src_p) = { "clk_uart7_src", "clk_uart7_frac", ++ "xin24m" }; ++PNAME(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" }; ++ ++static struct rockchip_pll_clock rk3528_pll_clks[] __initdata = { ++ [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, ++ CLK_IS_CRITICAL, RK3528_PLL_CON(0), ++ RK3528_MODE_CON, 0, 0, 0, rk3528_pll_rates), ++ ++ [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, ++ CLK_IS_CRITICAL, RK3528_PLL_CON(8), ++ RK3528_MODE_CON, 2, 0, 0, rk3528_pll_rates), ++ ++ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, ++ CLK_IS_CRITICAL, RK3528_PLL_CON(24), ++ RK3528_MODE_CON, 4, 0, 0, rk3528_pll_rates), ++ ++ [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, ++ CLK_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), ++ RK3528_MODE_CON, 6, 0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates), ++ ++ [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), ++ RK3528_DDRPHY_MODE_CON, 0, 0, 0, rk3528_pll_rates), ++}; ++ ++#define MFLAGS CLK_MUX_HIWORD_MASK ++#define DFLAGS CLK_DIVIDER_HIWORD_MASK ++#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) ++ ++static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata = ++ MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(6), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3528_uart1_fracmux __initdata = ++ MUX(CLK_UART1, "clk_uart1", sclk_uart1_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(8), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3528_uart2_fracmux __initdata = ++ MUX(CLK_UART2, "clk_uart2", sclk_uart2_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(10), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3528_uart3_fracmux __initdata = ++ MUX(CLK_UART3, "clk_uart3", sclk_uart3_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(12), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3528_uart4_fracmux __initdata = ++ MUX(CLK_UART4, "clk_uart4", sclk_uart4_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(14), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3528_uart5_fracmux __initdata = ++ MUX(CLK_UART5, "clk_uart5", sclk_uart5_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(16), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3528_uart6_fracmux __initdata = ++ MUX(CLK_UART6, "clk_uart6", sclk_uart6_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(18), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3528_uart7_fracmux __initdata = ++ MUX(CLK_UART7, "clk_uart7", sclk_uart7_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(20), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch mclk_i2s0_2ch_sai_src_fracmux __initdata = ++ MUX(MCLK_I2S0_2CH_SAI_SRC_PRE, "mclk_i2s0_2ch_sai_src_pre", mclk_i2s0_2ch_sai_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(22), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch mclk_i2s1_8ch_sai_src_fracmux __initdata = ++ MUX(MCLK_I2S1_8CH_SAI_SRC_PRE, "mclk_i2s1_8ch_sai_src_pre", mclk_i2s1_8ch_sai_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(26), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch mclk_i2s2_2ch_sai_src_fracmux __initdata = ++ MUX(MCLK_I2S2_2CH_SAI_SRC_PRE, "mclk_i2s2_2ch_sai_src_pre", mclk_i2s2_2ch_sai_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(28), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch mclk_i2s3_8ch_sai_src_fracmux __initdata = ++ MUX(MCLK_I2S3_8CH_SAI_SRC_PRE, "mclk_i2s3_8ch_sai_src_pre", mclk_i2s3_8ch_sai_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(24), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch mclk_spdif_src_fracmux __initdata = ++ MUX(MCLK_SDPDIF_SRC_PRE, "mclk_spdif_src_pre", mclk_spdif_src_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(32), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = { ++ /* top */ ++ FACTOR(0, "xin12m", "xin24m", 0, 1, 2), ++ ++ COMPOSITE(CLK_MATRIX_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(1), 15, 1, MFLAGS, 10, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 5, GFLAGS), ++ COMPOSITE(CLK_MATRIX_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 10, GFLAGS), ++ COMPOSITE_NOMUX(CLK_MATRIX_50M_SRC, "clk_50m_src", "cpll", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(0), 2, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 1, GFLAGS), ++ COMPOSITE_NOMUX(CLK_MATRIX_100M_SRC, "clk_100m_src", "cpll", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(0), 7, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 2, GFLAGS), ++ COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(1), 0, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 3, GFLAGS), ++ COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(1), 5, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 4, GFLAGS), ++ COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(2), 0, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 6, GFLAGS), ++ COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(2), 5, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 7, GFLAGS), ++ COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(2), 10, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 8, GFLAGS), ++ COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(4), 0, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 11, GFLAGS), ++ COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0, ++ RK3528_CLKSEL_CON(32), 10, 1, MFLAGS, 2, 8, DFLAGS, ++ RK3528_CLKGATE_CON(3), 7, GFLAGS), ++ COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0, ++ RK3528_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 8, DFLAGS, ++ RK3528_CLKGATE_CON(3), 8, GFLAGS), ++ COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0, ++ RK3528_CLKSEL_CON(36), 5, 5, DFLAGS, ++ RK3528_CLKGATE_CON(3), 13, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0, ++ RK3528_CLKSEL_CON(4), 5, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 12, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(5), 0, ++ RK3528_CLKGATE_CON(0), 13, GFLAGS, ++ &rk3528_uart0_fracmux), ++ GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, ++ RK3528_CLKGATE_CON(0), 14, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0, ++ RK3528_CLKSEL_CON(6), 2, 5, DFLAGS, ++ RK3528_CLKGATE_CON(0), 15, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(7), 0, ++ RK3528_CLKGATE_CON(1), 0, GFLAGS, ++ &rk3528_uart1_fracmux), ++ GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, ++ RK3528_CLKGATE_CON(1), 1, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0, ++ RK3528_CLKSEL_CON(8), 2, 5, DFLAGS, ++ RK3528_CLKGATE_CON(1), 2, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(9), 0, ++ RK3528_CLKGATE_CON(1), 3, GFLAGS, ++ &rk3528_uart2_fracmux), ++ GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, ++ RK3528_CLKGATE_CON(1), 4, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_UART3_SRC, "clk_uart3_src", "gpll", 0, ++ RK3528_CLKSEL_CON(10), 2, 5, DFLAGS, ++ RK3528_CLKGATE_CON(1), 5, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(11), 0, ++ RK3528_CLKGATE_CON(1), 6, GFLAGS, ++ &rk3528_uart3_fracmux), ++ GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, ++ RK3528_CLKGATE_CON(1), 7, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_UART4_SRC, "clk_uart4_src", "gpll", 0, ++ RK3528_CLKSEL_CON(12), 2, 5, DFLAGS, ++ RK3528_CLKGATE_CON(1), 8, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(13), 0, ++ RK3528_CLKGATE_CON(1), 9, GFLAGS, ++ &rk3528_uart4_fracmux), ++ GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, ++ RK3528_CLKGATE_CON(1), 10, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_UART5_SRC, "clk_uart5_src", "gpll", 0, ++ RK3528_CLKSEL_CON(14), 2, 5, DFLAGS, ++ RK3528_CLKGATE_CON(1), 11, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(15), 0, ++ RK3528_CLKGATE_CON(1), 12, GFLAGS, ++ &rk3528_uart5_fracmux), ++ GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, ++ RK3528_CLKGATE_CON(1), 13, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_UART6_SRC, "clk_uart6_src", "gpll", 0, ++ RK3528_CLKSEL_CON(16), 2, 5, DFLAGS, ++ RK3528_CLKGATE_CON(1), 14, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(17), 0, ++ RK3528_CLKGATE_CON(1), 15, GFLAGS, ++ &rk3528_uart6_fracmux), ++ GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, ++ RK3528_CLKGATE_CON(2), 0, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_UART7_SRC, "clk_uart7_src", "gpll", 0, ++ RK3528_CLKSEL_CON(18), 2, 5, DFLAGS, ++ RK3528_CLKGATE_CON(2), 1, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(19), 0, ++ RK3528_CLKGATE_CON(2), 2, GFLAGS, ++ &rk3528_uart7_fracmux), ++ GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, ++ RK3528_CLKGATE_CON(2), 3, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", "gpll", 0, ++ RK3528_CLKSEL_CON(20), 8, 5, DFLAGS, ++ RK3528_CLKGATE_CON(2), 5, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(21), 0, ++ RK3528_CLKGATE_CON(2), 6, GFLAGS, ++ &mclk_i2s0_2ch_sai_src_fracmux), ++ GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0, ++ RK3528_CLKGATE_CON(2), 7, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_I2S1_8CH_SRC, "clk_i2s1_8ch_src", "gpll", 0, ++ RK3528_CLKSEL_CON(24), 3, 5, DFLAGS, ++ RK3528_CLKGATE_CON(2), 11, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(25), 0, ++ RK3528_CLKGATE_CON(2), 12, GFLAGS, ++ &mclk_i2s1_8ch_sai_src_fracmux), ++ GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0, ++ RK3528_CLKGATE_CON(2), 13, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "gpll", 0, ++ RK3528_CLKSEL_CON(26), 3, 5, DFLAGS, ++ RK3528_CLKGATE_CON(2), 14, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(27), 0, ++ RK3528_CLKGATE_CON(2), 15, GFLAGS, ++ &mclk_i2s2_2ch_sai_src_fracmux), ++ GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0, ++ RK3528_CLKGATE_CON(3), 0, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_I2S3_8CH_SRC, "clk_i2s3_8ch_src", "gpll", 0, ++ RK3528_CLKSEL_CON(22), 3, 5, DFLAGS, ++ RK3528_CLKGATE_CON(2), 8, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(23), 0, ++ RK3528_CLKGATE_CON(2), 9, GFLAGS, ++ &mclk_i2s3_8ch_sai_src_fracmux), ++ GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0, ++ RK3528_CLKGATE_CON(2), 10, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_SPDIF_SRC, "clk_spdif_src", "gpll", 0, ++ RK3528_CLKSEL_CON(30), 2, 5, DFLAGS, ++ RK3528_CLKGATE_CON(3), 4, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(31), 0, ++ RK3528_CLKGATE_CON(3), 5, GFLAGS, ++ &mclk_spdif_src_fracmux), ++ GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0, ++ RK3528_CLKGATE_CON(3), 6, GFLAGS), ++ ++ /* bus */ ++ COMPOSITE_NODIV(ACLK_BUS_M_ROOT, "aclk_bus_m_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(43), 12, 2, MFLAGS, ++ RK3528_CLKGATE_CON(8), 7, GFLAGS), ++ GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(9), 1, GFLAGS), ++ ++ COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(43), 6, 2, MFLAGS, ++ RK3528_CLKGATE_CON(8), 4, GFLAGS), ++ GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0, ++ RK3528_CLKGATE_CON(9), 2, GFLAGS), ++ GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0, ++ RK3528_CLKGATE_CON(9), 4, GFLAGS), ++ GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0, ++ RK3528_CLKGATE_CON(11), 11, GFLAGS), ++ COMPOSITE(ACLK_BUS_VOPGL_ROOT, "aclk_bus_vopgl_root", mux_gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(43), 3, 1, MFLAGS, 0, 3, DFLAGS, ++ RK3528_CLKGATE_CON(8), 0, GFLAGS), ++ COMPOSITE_NODIV(ACLK_BUS_H_ROOT, "aclk_bus_h_root", mux_500m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(43), 4, 2, MFLAGS, ++ RK3528_CLKGATE_CON(8), 2, GFLAGS), ++ GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0, ++ RK3528_CLKGATE_CON(10), 14, GFLAGS), ++ ++ COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(43), 8, 2, MFLAGS, ++ RK3528_CLKGATE_CON(8), 5, GFLAGS), ++ ++ COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(43), 10, 2, MFLAGS, ++ RK3528_CLKGATE_CON(8), 6, GFLAGS), ++ GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0, ++ RK3528_CLKGATE_CON(8), 13, GFLAGS), ++ GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(8), 15, GFLAGS), ++ GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0, ++ RK3528_CLKGATE_CON(9), 5, GFLAGS), ++ GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0, ++ RK3528_CLKGATE_CON(9), 12, GFLAGS), ++ GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0, ++ RK3528_CLKGATE_CON(9), 15, GFLAGS), ++ GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0, ++ RK3528_CLKGATE_CON(10), 7, GFLAGS), ++ GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0, ++ RK3528_CLKGATE_CON(11), 4, GFLAGS), ++ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0, ++ RK3528_CLKGATE_CON(11), 7, GFLAGS), ++ GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0, ++ RK3528_CLKGATE_CON(10), 13, GFLAGS), ++ GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0, ++ RK3528_CLKGATE_CON(11), 10, GFLAGS), ++ GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED, ++ RK3528_CLKGATE_CON(11), 12, GFLAGS), ++ ++ COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(44), 6, 2, MFLAGS, ++ RK3528_CLKGATE_CON(11), 5, GFLAGS), ++ COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(44), 8, 2, MFLAGS, ++ RK3528_CLKGATE_CON(11), 8, GFLAGS), ++ ++ GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0, ++ RK3528_CLKGATE_CON(11), 9, GFLAGS), ++ GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0, ++ RK3528_CLKGATE_CON(11), 6, GFLAGS), ++ GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0, ++ RK3528_CLKGATE_CON(9), 13, GFLAGS), ++ GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, ++ RK3528_CLKGATE_CON(10), 0, GFLAGS), ++ ++ GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0, ++ RK3528_CLKGATE_CON(8), 9, GFLAGS), ++ GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0, ++ RK3528_CLKGATE_CON(9), 6, GFLAGS), ++ GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0, ++ RK3528_CLKGATE_CON(9), 7, GFLAGS), ++ GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0, ++ RK3528_CLKGATE_CON(9), 8, GFLAGS), ++ GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0, ++ RK3528_CLKGATE_CON(9), 9, GFLAGS), ++ GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0, ++ RK3528_CLKGATE_CON(9), 10, GFLAGS), ++ GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0, ++ RK3528_CLKGATE_CON(9), 11, GFLAGS), ++ ++ /* pmu */ ++ GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED, ++ RK3528_PMU_CLKGATE_CON(0), 1, GFLAGS), ++ GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED, ++ RK3528_PMU_CLKGATE_CON(0), 0, GFLAGS), ++ ++ GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0, ++ RK3528_PMU_CLKGATE_CON(0), 7, GFLAGS), ++ GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IS_CRITICAL, ++ RK3528_PMU_CLKGATE_CON(5), 4, GFLAGS), ++ ++ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0, ++ RK3528_PMU_CLKGATE_CON(0), 2, GFLAGS), ++ GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0, ++ RK3528_PMU_CLKGATE_CON(1), 2, GFLAGS), ++ GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", CLK_IS_CRITICAL, ++ RK3528_PMU_CLKGATE_CON(1), 5, GFLAGS), ++ GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IS_CRITICAL, ++ RK3528_PMU_CLKGATE_CON(1), 6, GFLAGS), ++ GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IS_CRITICAL, ++ RK3528_PMU_CLKGATE_CON(1), 7, GFLAGS), ++ GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0, ++ RK3528_PMU_CLKGATE_CON(1), 10, GFLAGS), ++ GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL, ++ RK3528_PMU_CLKGATE_CON(0), 13, GFLAGS), ++ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0, ++ RK3528_PMU_CLKGATE_CON(0), 14, GFLAGS), ++ GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0, ++ RK3528_PMU_CLKGATE_CON(0), 9, GFLAGS), ++ GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0, ++ RK3528_PMU_CLKGATE_CON(1), 12, GFLAGS), ++ GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0, ++ RK3528_PMU_CLKGATE_CON(1), 15, GFLAGS), ++ GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0, ++ RK3528_PMU_CLKGATE_CON(5), 1, GFLAGS), ++ ++ COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", clk_i2c2_p, 0, ++ RK3528_PMU_CLKSEL_CON(0), 0, 2, MFLAGS, ++ RK3528_PMU_CLKGATE_CON(0), 3, GFLAGS), ++ ++ GATE(CLK_REFOUT, "clk_refout", "xin24m", 0, ++ RK3528_PMU_CLKGATE_CON(2), 4, GFLAGS), ++ COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, ++ RK3528_PMU_CLKSEL_CON(5), 0, 5, DFLAGS, ++ RK3528_PMU_CLKGATE_CON(5), 0, GFLAGS), ++ ++ COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0, ++ RK3528_PMU_CLKSEL_CON(1), 0, ++ RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS), ++ /* clk_32k: internal! No path from external osc 32k */ ++ MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL, ++ RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS), ++ GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0, ++ RK3528_PMU_CLKGATE_CON(0), 8, GFLAGS), ++ GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED, ++ RK3528_PMU_CLKGATE_CON(1), 1, GFLAGS), ++ ++ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, ++ RK3528_PMU_CLKSEL_CON(0), 2, 1, MFLAGS, ++ RK3528_PMU_CLKGATE_CON(0), 15, GFLAGS), ++ COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0, ++ RK3528_PMU_CLKSEL_CON(2), 1, 1, MFLAGS, ++ RK3528_PMU_CLKGATE_CON(1), 11, GFLAGS), ++ ++ /* core */ ++ COMPOSITE_NOMUX(ACLK_M_CORE_BIU, "aclk_m_core", "armclk", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(39), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3528_CLKGATE_CON(5), 12, GFLAGS), ++ COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(40), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3528_CLKGATE_CON(5), 13, GFLAGS), ++ GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(6), 1, GFLAGS), ++ GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(6), 2, GFLAGS), ++ ++ /* ddr */ ++ GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", CLK_IS_CRITICAL, ++ RK3528_DDRPHY_CLKGATE_CON(0), 0, GFLAGS), ++ GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", CLK_IS_CRITICAL, ++ RK3528_DDRPHY_CLKGATE_CON(0), 1, GFLAGS), ++ ++ COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(90), 0, 2, MFLAGS, ++ RK3528_CLKGATE_CON(45), 0, GFLAGS), ++ GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IGNORE_UNUSED, ++ RK3528_CLKGATE_CON(45), 3, GFLAGS), ++ GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED, ++ RK3528_CLKGATE_CON(45), 8, GFLAGS), ++ GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED, ++ RK3528_CLKGATE_CON(45), 4, GFLAGS), ++ ++ GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(45), 2, GFLAGS), ++ GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(45), 6, GFLAGS), ++ GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(45), 9, GFLAGS), ++ ++ GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(45), 11, GFLAGS), ++ GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(45), 12, GFLAGS), ++ GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(45), 13, GFLAGS), ++ GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(45), 14, GFLAGS), ++ GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(45), 15, GFLAGS), ++ ++ /* gpu */ ++ COMPOSITE_NODIV(ACLK_GPU_ROOT, "aclk_gpu_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(76), 0, 2, MFLAGS, ++ RK3528_CLKGATE_CON(34), 0, GFLAGS), ++ COMPOSITE_NODIV(ACLK_GPU, "aclk_gpu", aclk_gpu_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(76), 6, 1, MFLAGS, ++ RK3528_CLKGATE_CON(34), 7, GFLAGS), ++ GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0, ++ RK3528_CLKGATE_CON(34), 8, GFLAGS), ++ COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(76), 4, 2, MFLAGS, ++ RK3528_CLKGATE_CON(34), 2, GFLAGS), ++ ++ /* rkvdec */ ++ COMPOSITE_NODIV(ACLK_RKVDEC_ROOT_NDFT, "aclk_rkvdec_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(88), 6, 2, MFLAGS, ++ RK3528_CLKGATE_CON(44), 3, GFLAGS), ++ COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(88), 4, 2, MFLAGS, ++ RK3528_CLKGATE_CON(44), 2, GFLAGS), ++ GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(44), 4, GFLAGS), ++ GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0, ++ RK3528_CLKGATE_CON(44), 9, GFLAGS), ++ COMPOSITE_NODIV(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", mux_600m_300m_200m_24m_p, 0, ++ RK3528_CLKSEL_CON(88), 11, 2, MFLAGS, ++ RK3528_CLKGATE_CON(44), 11, GFLAGS), ++ MUX(ACLK_RKVDEC_PVTMUX_ROOT, "aclk_rkvdec_pvtmux_root", aclk_rkvdec_pvtmux_root_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(88), 13, 1, MFLAGS), ++ GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0, ++ RK3528_CLKGATE_CON(44), 8, GFLAGS), ++ ++ /* rkvenc */ ++ COMPOSITE_NODIV(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(79), 2, 2, MFLAGS, ++ RK3528_CLKGATE_CON(36), 1, GFLAGS), ++ GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(36), 7, GFLAGS), ++ ++ COMPOSITE_NODIV(PCLK_RKVENC_ROOT, "pclk_rkvenc_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(79), 4, 2, MFLAGS, ++ RK3528_CLKGATE_CON(36), 2, GFLAGS), ++ GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(37), 10, GFLAGS), ++ GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(38), 6, GFLAGS), ++ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(36), 11, GFLAGS), ++ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(36), 13, GFLAGS), ++ GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(37), 2, GFLAGS), ++ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(37), 8, GFLAGS), ++ GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(38), 2, GFLAGS), ++ GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(38), 4, GFLAGS), ++ GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(38), 7, GFLAGS), ++ GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(38), 9, GFLAGS), ++ ++ COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mux_150m_100m_24m_p, 0, ++ RK3528_CLKSEL_CON(80), 12, 2, MFLAGS, ++ RK3528_CLKGATE_CON(38), 1, GFLAGS), ++ COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0, ++ RK3528_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, ++ RK3528_CLKGATE_CON(38), 8, GFLAGS), ++ COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0, ++ RK3528_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, ++ RK3528_CLKGATE_CON(38), 10, GFLAGS), ++ ++ COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(79), 0, 2, MFLAGS, ++ RK3528_CLKGATE_CON(36), 0, GFLAGS), ++ GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(36), 9, GFLAGS), ++ GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(37), 14, GFLAGS), ++ GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(38), 0, GFLAGS), ++ GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0, ++ RK3528_CLKGATE_CON(36), 6, GFLAGS), ++ ++ COMPOSITE_NODIV(CLK_CORE_RKVENC, "clk_core_rkvenc", mux_300m_200m_100m_24m_p, 0, ++ RK3528_CLKSEL_CON(79), 6, 2, MFLAGS, ++ RK3528_CLKGATE_CON(36), 8, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(79), 11, 2, MFLAGS, ++ RK3528_CLKGATE_CON(36), 14, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(79), 9, 2, MFLAGS, ++ RK3528_CLKGATE_CON(36), 12, GFLAGS), ++ ++ COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(79), 13, 2, MFLAGS, ++ RK3528_CLKGATE_CON(37), 3, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI_I2S1, "mclk_sai_i2s1", mclk_sai_i2s1_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(79), 8, 1, MFLAGS, ++ RK3528_CLKGATE_CON(36), 10, GFLAGS), ++ GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, ++ RK3528_CLKGATE_CON(37), 9, GFLAGS), ++ ++ /* vo */ ++ COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(83), 2, 2, MFLAGS, ++ RK3528_CLKGATE_CON(39), 1, GFLAGS), ++ GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(40), 2, GFLAGS), ++ GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(43), 3, GFLAGS), ++ GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(41), 7, GFLAGS), ++ GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(39), 10, GFLAGS), ++ GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(41), 3, GFLAGS), ++ GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(43), 4, GFLAGS), ++ GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(42), 1, GFLAGS), ++ GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(41), 1, GFLAGS), ++ GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(39), 7, GFLAGS), ++ GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(42), 9, GFLAGS), ++ GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0, ++ RK3528_CLKGATE_CON(40), 15, GFLAGS), ++ ++ COMPOSITE_NODIV(ACLK_VO_L_ROOT, "aclk_vo_l_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(84), 1, 2, MFLAGS, ++ RK3528_CLKGATE_CON(41), 8, GFLAGS), ++ GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0, ++ RK3528_CLKGATE_CON(41), 10, GFLAGS), ++ ++ COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(83), 4, 2, MFLAGS, ++ RK3528_CLKGATE_CON(39), 2, GFLAGS), ++ GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(41), 11, GFLAGS), ++ GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(42), 4, GFLAGS), ++ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(42), 5, GFLAGS), ++ GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(42), 7, GFLAGS), ++ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(42), 11, GFLAGS), ++ GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(43), 7, GFLAGS), ++ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(43), 9, GFLAGS), ++ GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(43), 11, GFLAGS), ++ ++ GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(43), 13, GFLAGS), ++ ++ GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(39), 13, GFLAGS), ++ GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(39), 15, GFLAGS), ++ GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(40), 6, GFLAGS), ++ GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(40), 14, GFLAGS), ++ GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0, ++ RK3528_CLKGATE_CON(41), 2, GFLAGS), ++ ++ COMPOSITE_NODIV(CLK_CORE_VDPP, "clk_core_vdpp", mux_339m_200m_100m_24m_p, 0, ++ RK3528_CLKSEL_CON(83), 10, 2, MFLAGS, ++ RK3528_CLKGATE_CON(39), 12, GFLAGS), ++ COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_339m_200m_100m_24m_p, 0, ++ RK3528_CLKSEL_CON(83), 8, 2, MFLAGS, ++ RK3528_CLKGATE_CON(39), 9, GFLAGS), ++ COMPOSITE_NODIV(ACLK_JPEG_ROOT, "aclk_jpeg_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(84), 9, 2, MFLAGS, ++ RK3528_CLKGATE_CON(41), 15, GFLAGS), ++ GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0, ++ RK3528_CLKGATE_CON(41), 6, GFLAGS), ++ ++ COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(83), 0, 2, MFLAGS, ++ RK3528_CLKGATE_CON(39), 0, GFLAGS), ++ GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0, ++ RK3528_CLKGATE_CON(39), 8, GFLAGS), ++ GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0, ++ RK3528_CLKGATE_CON(39), 11, GFLAGS), ++ GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0, ++ RK3528_CLKGATE_CON(41), 0, GFLAGS), ++ ++ COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0, ++ RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS, ++ RK3528_CLKGATE_CON(42), 8, GFLAGS), ++ ++ COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", mux_gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(83), 15, 1, MFLAGS, 12, 3, DFLAGS, ++ RK3528_CLKGATE_CON(40), 0, GFLAGS), ++ GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0, ++ RK3528_CLKGATE_CON(40), 5, GFLAGS), ++ ++ COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(85), 13, 2, MFLAGS, ++ RK3528_CLKGATE_CON(43), 10, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(86), 0, 2, MFLAGS, ++ RK3528_CLKGATE_CON(43), 12, GFLAGS), ++ GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, ++ RK3528_CLKGATE_CON(42), 6, GFLAGS), ++ ++ GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, ++ RK3528_CLKGATE_CON(43), 2, GFLAGS), ++ GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0, ++ RK3528_CLKGATE_CON(42), 3, GFLAGS), ++ GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0, ++ RK3528_CLKGATE_CON(43), 14, GFLAGS), ++ GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, ++ RK3528_CLKGATE_CON(42), 12, GFLAGS), ++ FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", ++ 0, 1, 2), ++ ++ GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0, ++ RK3528_CLKGATE_CON(42), 2, GFLAGS), ++ COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3528_CLKSEL_CON(84), 0, 1, MFLAGS, ++ RK3528_CLKGATE_CON(40), 3, GFLAGS), ++ GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT, ++ RK3528_CLKGATE_CON(40), 4, GFLAGS), ++ FACTOR_GATE(DCLK_CVBS, "dclk_cvbs", "dclk_vop1", 0, 1, 4, ++ RK3528_CLKGATE_CON(41), 4, GFLAGS), ++ GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0, ++ RK3528_CLKGATE_CON(41), 5, GFLAGS), ++ ++ FACTOR_GATE(CLK_SFR_HDMI, "clk_sfr_hdmi", "dclk_vop_src1", 0, 1, 4, ++ RK3528_CLKGATE_CON(40), 7, GFLAGS), ++ ++ GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0, ++ RK3528_CLKGATE_CON(40), 10, GFLAGS), ++ GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0, ++ RK3528_CLKGATE_CON(37), 15, GFLAGS), ++ GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0, ++ RK3528_CLKGATE_CON(40), 8, GFLAGS), ++ ++ /* vpu */ ++ GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, ++ RK3528_CLKGATE_CON(26), 5, GFLAGS), ++ GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, ++ RK3528_CLKGATE_CON(27), 1, GFLAGS), ++ GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0, ++ RK3528_CLKGATE_CON(33), 4, GFLAGS), ++ GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0, ++ RK3528_CLKGATE_CON(30), 2, GFLAGS), ++ GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, ++ RK3528_CLKGATE_CON(26), 3, GFLAGS), ++ GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0, ++ RK3528_CLKGATE_CON(33), 2, GFLAGS), ++ COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0, ++ RK3528_CLKSEL_CON(72), 6, 2, MFLAGS, 0, 6, DFLAGS, ++ RK3528_CLKGATE_CON(32), 1, GFLAGS), ++ ++ COMPOSITE_NODIV(PCLK_VPU_ROOT, "pclk_vpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(61), 4, 2, MFLAGS, ++ RK3528_CLKGATE_CON(25), 5, GFLAGS), ++ GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(25), 12, GFLAGS), ++ GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(25), 11, GFLAGS), ++ GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(27), 11, GFLAGS), ++ GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(32), 7, GFLAGS), ++ GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(27), 4, GFLAGS), ++ GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(32), 9, GFLAGS), ++ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(27), 0, GFLAGS), ++ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(26), 4, GFLAGS), ++ GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(32), 11, GFLAGS), ++ GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(26), 13, GFLAGS), ++ GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(27), 13, GFLAGS), ++ GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(27), 9, GFLAGS), ++ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(32), 14, GFLAGS), ++ GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(30), 1, GFLAGS), ++ GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(27), 7, GFLAGS), ++ GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(26), 8, GFLAGS), ++ GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(30), 7, GFLAGS), ++ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(28), 1, GFLAGS), ++ GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(30), 6, GFLAGS), ++ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(27), 15, GFLAGS), ++ GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", CLK_IS_CRITICAL, ++ RK3528_CLKGATE_CON(28), 6, GFLAGS), ++ GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(28), 3, GFLAGS), ++ ++ COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(60), 0, 2, MFLAGS, ++ RK3528_CLKGATE_CON(25), 0, GFLAGS), ++ GATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0, ++ RK3528_CLKGATE_CON(26), 1, GFLAGS), ++ GATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0, ++ RK3528_CLKGATE_CON(28), 5, GFLAGS), ++ GATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0, ++ RK3528_CLKGATE_CON(30), 3, GFLAGS), ++ ++ GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0, ++ RK3528_CLKGATE_CON(33), 1, GFLAGS), ++ ++ COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(61), 2, 2, MFLAGS, ++ RK3528_CLKGATE_CON(25), 4, GFLAGS), ++ GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(25), 10, GFLAGS), ++ GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(25), 13, GFLAGS), ++ GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(26), 0, GFLAGS), ++ GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(26), 9, GFLAGS), ++ GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(26), 11, GFLAGS), ++ ++ GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(30), 4, GFLAGS), ++ GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(30), 5, GFLAGS), ++ GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(32), 2, GFLAGS), ++ GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(32), 4, GFLAGS), ++ ++ COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0, ++ RK3528_CLKSEL_CON(60), 2, 8, DFLAGS, ++ RK3528_CLKGATE_CON(25), 1, GFLAGS), ++ COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0, ++ RK3528_CLKSEL_CON(60), 10, 5, DFLAGS, ++ RK3528_CLKGATE_CON(25), 2, GFLAGS), ++ ++ COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0, ++ RK3528_CLKSEL_CON(73), 13, 1, MFLAGS, 7, 6, DFLAGS, ++ RK3528_CLKGATE_CON(32), 10, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(64), 0, 2, MFLAGS, ++ RK3528_CLKGATE_CON(28), 4, GFLAGS), ++ ++ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0, ++ RK3528_CLKSEL_CON(61), 12, 2, MFLAGS, 6, 6, DFLAGS, ++ RK3528_CLKGATE_CON(25), 14, GFLAGS), ++ COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0, ++ RK3528_CLKSEL_CON(62), 6, 2, MFLAGS, 0, 6, DFLAGS, ++ RK3528_CLKGATE_CON(25), 15, GFLAGS), ++ ++ COMPOSITE_NODIV(ACLK_VPU_ROOT, "aclk_vpu_root", ++ mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3528_CLKSEL_CON(61), 0, 2, MFLAGS, ++ RK3528_CLKGATE_CON(25), 3, GFLAGS), ++ GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0, ++ RK3528_CLKGATE_CON(25), 9, GFLAGS), ++ ++ COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(63), 10, 2, MFLAGS, ++ RK3528_CLKGATE_CON(27), 5, GFLAGS), ++ COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0, ++ RK3528_CLKSEL_CON(72), 14, 2, MFLAGS, 8, 6, DFLAGS, ++ RK3528_CLKGATE_CON(32), 3, GFLAGS), ++ COMPOSITE(CLK_CAN2, "clk_can2", mux_gpll_cpll_p, 0, ++ RK3528_CLKSEL_CON(73), 6, 1, MFLAGS, 0, 6, DFLAGS, ++ RK3528_CLKGATE_CON(32), 8, GFLAGS), ++ COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, ++ RK3528_CLKSEL_CON(74), 3, 5, DFLAGS, ++ RK3528_CLKGATE_CON(32), 15, GFLAGS), ++ COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0, ++ RK3528_CLKSEL_CON(74), 0, 3, DFLAGS, ++ RK3528_CLKGATE_CON(32), 12, GFLAGS), ++ COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0, ++ RK3528_CLKSEL_CON(74), 8, 5, DFLAGS, ++ RK3528_CLKGATE_CON(33), 0, GFLAGS), ++ COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(62), 8, 2, MFLAGS, ++ RK3528_CLKGATE_CON(26), 2, GFLAGS), ++ COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s2_2ch_sai_src", 0, ++ RK3528_CLKSEL_CON(63), 0, 8, DFLAGS, ++ RK3528_CLKGATE_CON(26), 14, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(63), 12, 2, MFLAGS, ++ RK3528_CLKGATE_CON(28), 0, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0, ++ RK3528_CLKSEL_CON(63), 14, 2, MFLAGS, ++ RK3528_CLKGATE_CON(28), 2, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI_I2S0, "mclk_sai_i2s0", mclk_sai_i2s0_p, CLK_SET_RATE_PARENT, ++ RK3528_CLKSEL_CON(62), 10, 1, MFLAGS, ++ RK3528_CLKGATE_CON(26), 10, GFLAGS), ++ GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0, ++ RK3528_CLKGATE_CON(26), 12, GFLAGS), ++ ++ /* pcie */ ++ COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", "ppll", CLK_IS_CRITICAL, ++ RK3528_PCIE_CLKSEL_CON(1), 2, 5, DFLAGS, ++ RK3528_PCIE_CLKGATE_CON(0), 1, GFLAGS), ++ COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", "ppll", CLK_IS_CRITICAL, ++ RK3528_PCIE_CLKSEL_CON(1), 7, 5, DFLAGS, ++ RK3528_PCIE_CLKGATE_CON(0), 2, GFLAGS), ++ MUX(CLK_REF_PCIE_INNER_PHY, "clk_ref_pcie_inner_phy", clk_ref_pcie_inner_phy_p, 0, ++ RK3528_PCIE_CLKSEL_CON(1), 13, 1, MFLAGS), ++ FACTOR(CLK_REF_PCIE_100M_PHY, "clk_ref_pcie_100m_phy", "clk_ppll_100m_src", ++ 0, 1, 1), ++ ++ /* gmac */ ++ DIV(CLK_GMAC0_SRC, "clk_gmac0_src", "gmac0", 0, ++ RK3528_CLKSEL_CON(84), 3, 6, DFLAGS), ++ GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0, ++ RK3528_CLKGATE_CON(41), 13, GFLAGS), ++ GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0, ++ RK3528_CLKGATE_CON(41), 14, GFLAGS), ++ GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "gmac0", 0, ++ RK3528_CLKGATE_CON(41), 12, GFLAGS), ++ ++ FACTOR(CLK_GMAC1_RMII_VPU, "clk_gmac1_50m", "clk_ppll_50m_src", ++ 0, 1, 1), ++ FACTOR(CLK_GMAC1_SRC_VPU, "clk_gmac1_125m", "clk_ppll_125m_src", ++ 0, 1, 1), ++}; ++ ++static int __init clk_rk3528_probe(struct platform_device *pdev) ++{ ++ struct rockchip_clk_provider *ctx; ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches); ++ unsigned long nr_clks; ++ void __iomem *reg_base; ++ ++ nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches, ++ nr_branches) + 1; ++ ++ reg_base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(reg_base)) ++ return dev_err_probe(dev, PTR_ERR(reg_base), ++ "could not map cru region"); ++ ++ ctx = rockchip_clk_init(np, reg_base, nr_clks); ++ if (IS_ERR(ctx)) ++ return dev_err_probe(dev, PTR_ERR(ctx), ++ "rockchip clk init failed"); ++ ++ rockchip_clk_register_plls(ctx, rk3528_pll_clks, ++ ARRAY_SIZE(rk3528_pll_clks), ++ RK3528_GRF_SOC_STATUS0); ++ rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", ++ mux_armclk, ARRAY_SIZE(mux_armclk), ++ &rk3528_cpuclk_data, rk3528_cpuclk_rates, ++ ARRAY_SIZE(rk3528_cpuclk_rates)); ++ rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches); ++ ++ rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL); ++ ++ rockchip_clk_of_add_provider(np, ctx); ++ ++ return 0; ++} ++ ++static const struct of_device_id clk_rk3528_match_table[] = { ++ { .compatible = "rockchip,rk3528-cru" }, ++ { /* end */ } ++}; ++ ++static struct platform_driver clk_rk3528_driver = { ++ .driver = { ++ .name = "clk-rk3528", ++ .of_match_table = clk_rk3528_match_table, ++ .suppress_bind_attrs = true, ++ }, ++}; ++builtin_platform_driver_probe(clk_rk3528_driver, clk_rk3528_probe); +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -208,6 +208,26 @@ struct clk; + #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) + #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) + ++#define RK3528_PMU_CRU_BASE 0x10000 ++#define RK3528_PCIE_CRU_BASE 0x20000 ++#define RK3528_DDRPHY_CRU_BASE 0x28000 ++#define RK3528_PLL_CON(x) RK2928_PLL_CON(x) ++#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) ++#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) ++#define RK3528_MODE_CON 0x280 ++#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) ++#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) ++#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) ++#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) ++#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) ++#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) ++#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE) ++#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE) ++#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) ++#define RK3528_GLB_CNT_TH 0xc00 ++#define RK3528_GLB_SRST_FST 0xc08 ++#define RK3528_GLB_SRST_SND 0xc0c ++ + #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) + #define RK3568_MODE_CON0 0xc0 + #define RK3568_MISC_CON0 0xc4 diff --git a/target/linux/rockchip/patches-6.12/032-21-v6.15-clk-rockchip-rk3528-Add-reset-lookup-table.patch b/target/linux/rockchip/patches-6.12/032-21-v6.15-clk-rockchip-rk3528-Add-reset-lookup-table.patch new file mode 100644 index 0000000000..cebf6270c8 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-21-v6.15-clk-rockchip-rk3528-Add-reset-lookup-table.patch @@ -0,0 +1,364 @@ +From 5738362a5ee7e3417312e7fc03bcb0ffb12ba4f3 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Thu, 27 Feb 2025 17:52:57 +0000 +Subject: [PATCH] clk: rockchip: rk3528: Add reset lookup table + +In the commit 5d0eb375e685 ("clk: rockchip: Add clock controller driver +for RK3528 SoC") only the dt-binding header was added for the reset +controller for the RK3528 SoC. + +Add a reset lookup table generated from the SRST symbols used by vendor +linux-6.1-stan-rkr5 kernel to complete support for the reset controller. + +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20250227175302.2950788-1-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/Makefile | 2 +- + drivers/clk/rockchip/clk-rk3528.c | 2 + + drivers/clk/rockchip/clk.h | 1 + + drivers/clk/rockchip/rst-rk3528.c | 306 ++++++++++++++++++++++++++++++ + 4 files changed, 310 insertions(+), 1 deletion(-) + create mode 100644 drivers/clk/rockchip/rst-rk3528.c + +--- a/drivers/clk/rockchip/Makefile ++++ b/drivers/clk/rockchip/Makefile +@@ -29,7 +29,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-r + obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o + obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o + obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o +-obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o ++obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o rst-rk3528.o + obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o + obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o + obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o +--- a/drivers/clk/rockchip/clk-rk3528.c ++++ b/drivers/clk/rockchip/clk-rk3528.c +@@ -1092,6 +1092,8 @@ static int __init clk_rk3528_probe(struc + ARRAY_SIZE(rk3528_cpuclk_rates)); + rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches); + ++ rk3528_rst_init(np, reg_base); ++ + rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -1187,6 +1187,7 @@ static inline void rockchip_register_sof + return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); + } + ++void rk3528_rst_init(struct device_node *np, void __iomem *reg_base); + void rk3576_rst_init(struct device_node *np, void __iomem *reg_base); + void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); + +--- /dev/null ++++ b/drivers/clk/rockchip/rst-rk3528.c +@@ -0,0 +1,306 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd. ++ * Based on Sebastian Reichel's implementation for RK3588 ++ */ ++ ++#include ++#include ++#include ++#include "clk.h" ++ ++/* 0xFF4A0000 + 0x0A00 */ ++#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) ++ ++/* mapping table for reset ID to register offset */ ++static const int rk3528_register_offset[] = { ++ /* CRU_SOFTRST_CON03 */ ++ RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10), ++ ++ /* CRU_SOFTRST_CON05 */ ++ RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14), ++ RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15), ++ ++ /* CRU_SOFTRST_CON06 */ ++ RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7), ++ ++ /* CRU_SOFTRST_CON08 */ ++ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15), ++ ++ /* CRU_SOFTRST_CON09 */ ++ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15), ++ ++ /* CRU_SOFTRST_CON10 */ ++ RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14), ++ ++ /* CRU_SOFTRST_CON11 */ ++ RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12), ++ ++ /* CRU_SOFTRST_CON25 */ ++ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14), ++ RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15), ++ ++ /* CRU_SOFTRST_CON26 */ ++ RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13), ++ ++ /* CRU_SOFTRST_CON27 */ ++ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14), ++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15), ++ ++ /* CRU_SOFTRST_CON28 */ ++ RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5), ++ ++ /* CRU_SOFTRST_CON30 */ ++ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7), ++ ++ /* CRU_SOFTRST_CON32 */ ++ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14), ++ RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15), ++ ++ /* CRU_SOFTRST_CON33 */ ++ RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1), ++ ++ /* CRU_SOFTRST_CON34 */ ++ RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9), ++ ++ /* CRU_SOFTRST_CON36 */ ++ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14), ++ ++ /* CRU_SOFTRST_CON37 */ ++ RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14), ++ RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15), ++ ++ /* CRU_SOFTRST_CON38 */ ++ RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10), ++ ++ /* CRU_SOFTRST_CON39 */ ++ RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15), ++ ++ /* CRU_SOFTRST_CON40 */ ++ RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14), ++ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15), ++ ++ /* CRU_SOFTRST_CON41 */ ++ RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10), ++ ++ /* CRU_SOFTRST_CON42 */ ++ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13), ++ ++ /* CRU_SOFTRST_CON43 */ ++ RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14), ++ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15), ++ ++ /* CRU_SOFTRST_CON44 */ ++ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0), ++ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7), ++ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12), ++ ++ /* CRU_SOFTRST_CON45 */ ++ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1), ++ RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2), ++ RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3), ++ RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4), ++ RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5), ++ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6), ++ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8), ++ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9), ++ RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10), ++ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11), ++ RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12), ++ RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13), ++ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14), ++ RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15), ++ ++ /* CRU_SOFTRST_CON46 */ ++ RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0), ++}; ++ ++void rk3528_rst_init(struct device_node *np, void __iomem *reg_base) ++{ ++ rockchip_register_softrst_lut(np, ++ rk3528_register_offset, ++ ARRAY_SIZE(rk3528_register_offset), ++ reg_base + RK3528_SOFTRST_CON(0), ++ ROCKCHIP_SOFTRST_HIWORD_MASK); ++} diff --git a/target/linux/rockchip/patches-6.12/032-22-v6.15-pinctrl-rockchip-Add-support-for-RK3528.patch b/target/linux/rockchip/patches-6.12/032-22-v6.15-pinctrl-rockchip-Add-support-for-RK3528.patch new file mode 100644 index 0000000000..bce782de47 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-22-v6.15-pinctrl-rockchip-Add-support-for-RK3528.patch @@ -0,0 +1,238 @@ +From a5e4cde647851ed67f19a5cb54a99282f32aae99 Mon Sep 17 00:00:00 2001 +From: Steven Liu +Date: Fri, 28 Feb 2025 06:40:09 +0000 +Subject: [PATCH] pinctrl: rockchip: Add support for RK3528 + +Add gpio and pinctrl support for the 5 GPIO banks on RK3528. + +Signed-off-by: Steven Liu +Signed-off-by: Jonas Karlman +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/20250228064024.3200000-4-jonas@kwiboo.se +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/pinctrl-rockchip.c | 160 ++++++++++++++++++++++++++++- + drivers/pinctrl/pinctrl-rockchip.h | 1 + + 2 files changed, 160 insertions(+), 1 deletion(-) + +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -2003,6 +2003,115 @@ static int rk3399_calc_drv_reg_and_bit(s + return 0; + } + ++#define RK3528_DRV_BITS_PER_PIN 8 ++#define RK3528_DRV_PINS_PER_REG 2 ++#define RK3528_DRV_GPIO0_OFFSET 0x100 ++#define RK3528_DRV_GPIO1_OFFSET 0x20120 ++#define RK3528_DRV_GPIO2_OFFSET 0x30160 ++#define RK3528_DRV_GPIO3_OFFSET 0x20190 ++#define RK3528_DRV_GPIO4_OFFSET 0x101C0 ++ ++static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ ++ if (bank->bank_num == 0) ++ *reg = RK3528_DRV_GPIO0_OFFSET; ++ else if (bank->bank_num == 1) ++ *reg = RK3528_DRV_GPIO1_OFFSET; ++ else if (bank->bank_num == 2) ++ *reg = RK3528_DRV_GPIO2_OFFSET; ++ else if (bank->bank_num == 3) ++ *reg = RK3528_DRV_GPIO3_OFFSET; ++ else if (bank->bank_num == 4) ++ *reg = RK3528_DRV_GPIO4_OFFSET; ++ else ++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); ++ ++ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3528_DRV_PINS_PER_REG; ++ *bit *= RK3528_DRV_BITS_PER_PIN; ++ ++ return 0; ++} ++ ++#define RK3528_PULL_BITS_PER_PIN 2 ++#define RK3528_PULL_PINS_PER_REG 8 ++#define RK3528_PULL_GPIO0_OFFSET 0x200 ++#define RK3528_PULL_GPIO1_OFFSET 0x20210 ++#define RK3528_PULL_GPIO2_OFFSET 0x30220 ++#define RK3528_PULL_GPIO3_OFFSET 0x20230 ++#define RK3528_PULL_GPIO4_OFFSET 0x10240 ++ ++static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ ++ if (bank->bank_num == 0) ++ *reg = RK3528_PULL_GPIO0_OFFSET; ++ else if (bank->bank_num == 1) ++ *reg = RK3528_PULL_GPIO1_OFFSET; ++ else if (bank->bank_num == 2) ++ *reg = RK3528_PULL_GPIO2_OFFSET; ++ else if (bank->bank_num == 3) ++ *reg = RK3528_PULL_GPIO3_OFFSET; ++ else if (bank->bank_num == 4) ++ *reg = RK3528_PULL_GPIO4_OFFSET; ++ else ++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); ++ ++ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3528_PULL_PINS_PER_REG; ++ *bit *= RK3528_PULL_BITS_PER_PIN; ++ ++ return 0; ++} ++ ++#define RK3528_SMT_BITS_PER_PIN 1 ++#define RK3528_SMT_PINS_PER_REG 8 ++#define RK3528_SMT_GPIO0_OFFSET 0x400 ++#define RK3528_SMT_GPIO1_OFFSET 0x20410 ++#define RK3528_SMT_GPIO2_OFFSET 0x30420 ++#define RK3528_SMT_GPIO3_OFFSET 0x20430 ++#define RK3528_SMT_GPIO4_OFFSET 0x10440 ++ ++static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, ++ struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ ++ if (bank->bank_num == 0) ++ *reg = RK3528_SMT_GPIO0_OFFSET; ++ else if (bank->bank_num == 1) ++ *reg = RK3528_SMT_GPIO1_OFFSET; ++ else if (bank->bank_num == 2) ++ *reg = RK3528_SMT_GPIO2_OFFSET; ++ else if (bank->bank_num == 3) ++ *reg = RK3528_SMT_GPIO3_OFFSET; ++ else if (bank->bank_num == 4) ++ *reg = RK3528_SMT_GPIO4_OFFSET; ++ else ++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); ++ ++ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3528_SMT_PINS_PER_REG; ++ *bit *= RK3528_SMT_BITS_PER_PIN; ++ ++ return 0; ++} ++ + #define RK3568_PULL_PMU_OFFSET 0x20 + #define RK3568_PULL_GRF_OFFSET 0x80 + #define RK3568_PULL_BITS_PER_PIN 2 +@@ -2495,7 +2604,8 @@ static int rockchip_set_drive_perpin(str + rmask_bits = RK3588_DRV_BITS_PER_PIN; + ret = strength; + goto config; +- } else if (ctrl->type == RK3568) { ++ } else if (ctrl->type == RK3528 || ++ ctrl->type == RK3568) { + rmask_bits = RK3568_DRV_BITS_PER_PIN; + ret = (1 << (strength + 1)) - 1; + goto config; +@@ -2639,6 +2749,7 @@ static int rockchip_get_pull(struct rock + case RK3328: + case RK3368: + case RK3399: ++ case RK3528: + case RK3568: + case RK3576: + case RK3588: +@@ -2699,6 +2810,7 @@ static int rockchip_set_pull(struct rock + case RK3328: + case RK3368: + case RK3399: ++ case RK3528: + case RK3568: + case RK3576: + case RK3588: +@@ -2965,6 +3077,7 @@ static bool rockchip_pinconf_pull_valid( + case RK3328: + case RK3368: + case RK3399: ++ case RK3528: + case RK3568: + case RK3576: + case RK3588: +@@ -4084,6 +4197,49 @@ static struct rockchip_pin_ctrl rk3399_p + .drv_calc_reg = rk3399_calc_drv_reg_and_bit, + }; + ++static struct rockchip_pin_bank rk3528_pin_banks[] = { ++ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0, 0, 0, 0), ++ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0x20020, 0x20028, 0x20030, 0x20038), ++ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0x30040, 0, 0, 0), ++ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0x20060, 0x20068, 0x20070, 0), ++ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ 0x10080, 0x10088, 0x10090, 0x10098), ++}; ++ ++static struct rockchip_pin_ctrl rk3528_pin_ctrl = { ++ .pin_banks = rk3528_pin_banks, ++ .nr_banks = ARRAY_SIZE(rk3528_pin_banks), ++ .label = "RK3528-GPIO", ++ .type = RK3528, ++ .pull_calc_reg = rk3528_calc_pull_reg_and_bit, ++ .drv_calc_reg = rk3528_calc_drv_reg_and_bit, ++ .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit, ++}; ++ + static struct rockchip_pin_bank rk3568_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, +@@ -4208,6 +4364,8 @@ static const struct of_device_id rockchi + .data = &rk3368_pin_ctrl }, + { .compatible = "rockchip,rk3399-pinctrl", + .data = &rk3399_pin_ctrl }, ++ { .compatible = "rockchip,rk3528-pinctrl", ++ .data = &rk3528_pin_ctrl }, + { .compatible = "rockchip,rk3568-pinctrl", + .data = &rk3568_pin_ctrl }, + { .compatible = "rockchip,rk3576-pinctrl", +--- a/drivers/pinctrl/pinctrl-rockchip.h ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type { + RK3328, + RK3368, + RK3399, ++ RK3528, + RK3568, + RK3576, + RK3588, diff --git a/target/linux/rockchip/patches-6.12/032-23-v6.16-dt-bindings-clock-Add-GRF-clock-definition-for-RK3528.patch b/target/linux/rockchip/patches-6.12/032-23-v6.16-dt-bindings-clock-Add-GRF-clock-definition-for-RK3528.patch new file mode 100644 index 0000000000..e15d2cc14f --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-23-v6.16-dt-bindings-clock-Add-GRF-clock-definition-for-RK3528.patch @@ -0,0 +1,31 @@ +From 8a023e86f3d999007f2687952afe78ef34a6aa91 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 6 May 2025 09:22:02 +0000 +Subject: [PATCH] dt-bindings: clock: Add GRF clock definition for RK3528 + +These clocks are for SD/SDIO tuning purpose and come with registers +in GRF syscon. + +Signed-off-by: Yao Zi +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20250506092206.46143-2-ziyao@disroot.org +Signed-off-by: Heiko Stuebner +--- + include/dt-bindings/clock/rockchip,rk3528-cru.h | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/include/dt-bindings/clock/rockchip,rk3528-cru.h ++++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h +@@ -414,6 +414,12 @@ + #define MCLK_I2S2_2CH_SAI_SRC_PRE 402 + #define MCLK_I2S3_8CH_SAI_SRC_PRE 403 + #define MCLK_SDPDIF_SRC_PRE 404 ++#define SCLK_SDMMC_DRV 405 ++#define SCLK_SDMMC_SAMPLE 406 ++#define SCLK_SDIO0_DRV 407 ++#define SCLK_SDIO0_SAMPLE 408 ++#define SCLK_SDIO1_DRV 409 ++#define SCLK_SDIO1_SAMPLE 410 + + /* scmi-clocks indices */ + #define SCMI_PCLK_KEYREADER 0 diff --git a/target/linux/rockchip/patches-6.12/032-24-v6.16-clk-rockchip-Support-MMC-clocks-in-GRF-region.patch b/target/linux/rockchip/patches-6.12/032-24-v6.16-clk-rockchip-Support-MMC-clocks-in-GRF-region.patch new file mode 100644 index 0000000000..760c221536 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-24-v6.16-clk-rockchip-Support-MMC-clocks-in-GRF-region.patch @@ -0,0 +1,156 @@ +From 621ba4d9f6db560a7406fd732af1b495ff5aa103 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 6 May 2025 09:22:03 +0000 +Subject: [PATCH] clk: rockchip: Support MMC clocks in GRF region + +Registers of MMC drive/sample clocks in Rockchip RV1106 and RK3528 +locate in GRF regions. Adjust MMC clock code to support register +operations through regmap. + +Signed-off-by: Yao Zi +Link: https://lore.kernel.org/r/20250506092206.46143-3-ziyao@disroot.org +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-mmc-phase.c | 24 ++++++++++++++++++++---- + drivers/clk/rockchip/clk.c | 16 ++++++++++++++-- + drivers/clk/rockchip/clk.h | 17 ++++++++++++++++- + 3 files changed, 50 insertions(+), 7 deletions(-) + +--- a/drivers/clk/rockchip/clk-mmc-phase.c ++++ b/drivers/clk/rockchip/clk-mmc-phase.c +@@ -9,11 +9,14 @@ + #include + #include + #include ++#include + #include "clk.h" + + struct rockchip_mmc_clock { + struct clk_hw hw; + void __iomem *reg; ++ struct regmap *grf; ++ int grf_reg; + int shift; + int cached_phase; + struct notifier_block clk_rate_change_nb; +@@ -54,7 +57,12 @@ static int rockchip_mmc_get_phase(struct + if (!rate) + return 0; + +- raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); ++ if (mmc_clock->grf) ++ regmap_read(mmc_clock->grf, mmc_clock->grf_reg, &raw_value); ++ else ++ raw_value = readl(mmc_clock->reg); ++ ++ raw_value >>= mmc_clock->shift; + + degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; + +@@ -134,8 +142,12 @@ static int rockchip_mmc_set_phase(struct + raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; + raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; + raw_value |= nineties; +- writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), +- mmc_clock->reg); ++ raw_value = HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift); ++ ++ if (mmc_clock->grf) ++ regmap_write(mmc_clock->grf, mmc_clock->grf_reg, raw_value); ++ else ++ writel(raw_value, mmc_clock->reg); + + pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", + clk_hw_get_name(hw), degrees, delay_num, +@@ -189,7 +201,9 @@ static int rockchip_mmc_clk_rate_notify( + + struct clk *rockchip_clk_register_mmc(const char *name, + const char *const *parent_names, u8 num_parents, +- void __iomem *reg, int shift) ++ void __iomem *reg, ++ struct regmap *grf, int grf_reg, ++ int shift) + { + struct clk_init_data init; + struct rockchip_mmc_clock *mmc_clock; +@@ -208,6 +222,8 @@ struct clk *rockchip_clk_register_mmc(co + + mmc_clock->hw.init = &init; + mmc_clock->reg = reg; ++ mmc_clock->grf = grf; ++ mmc_clock->grf_reg = grf_reg; + mmc_clock->shift = shift; + + clk = clk_register(NULL, &mmc_clock->hw); +--- a/drivers/clk/rockchip/clk.c ++++ b/drivers/clk/rockchip/clk.c +@@ -509,8 +509,10 @@ void rockchip_clk_register_branches(stru + clk = NULL; + + /* for GRF-dependent branches, choose the right grf first */ +- if ((list->branch_type == branch_muxgrf || list->branch_type == branch_grf_gate) && +- list->grf_type != grf_type_sys) { ++ if ((list->branch_type == branch_muxgrf || ++ list->branch_type == branch_grf_gate || ++ list->branch_type == branch_grf_mmc) && ++ list->grf_type != grf_type_sys) { + hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) { + if (agrf->type == list->grf_type) { + grf = agrf->grf; +@@ -612,6 +614,16 @@ void rockchip_clk_register_branches(stru + list->name, + list->parent_names, list->num_parents, + ctx->reg_base + list->muxdiv_offset, ++ NULL, 0, ++ list->div_shift ++ ); ++ break; ++ case branch_grf_mmc: ++ clk = rockchip_clk_register_mmc( ++ list->name, ++ list->parent_names, list->num_parents, ++ 0, ++ grf, list->muxdiv_offset, + list->div_shift + ); + break; +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -580,7 +580,9 @@ struct clk *rockchip_clk_register_cpuclk + + struct clk *rockchip_clk_register_mmc(const char *name, + const char *const *parent_names, u8 num_parents, +- void __iomem *reg, int shift); ++ void __iomem *reg, ++ struct regmap *grf, int grf_reg, ++ int shift); + + /* + * DDRCLK flags, including method of setting the rate +@@ -625,6 +627,7 @@ enum rockchip_clk_branch_type { + branch_grf_gate, + branch_linked_gate, + branch_mmc, ++ branch_grf_mmc, + branch_inverter, + branch_factor, + branch_ddrclk, +@@ -991,6 +994,18 @@ struct rockchip_clk_branch { + .div_shift = shift, \ + } + ++#define MMC_GRF(_id, cname, pname, offset, shift, grftype) \ ++ { \ ++ .id = _id, \ ++ .branch_type = branch_grf_mmc, \ ++ .name = cname, \ ++ .parent_names = (const char *[]){ pname }, \ ++ .num_parents = 1, \ ++ .muxdiv_offset = offset, \ ++ .div_shift = shift, \ ++ .grf_type = grftype, \ ++ } ++ + #define INVERTER(_id, cname, pname, io, is, if) \ + { \ + .id = _id, \ diff --git a/target/linux/rockchip/patches-6.12/032-25-v6.16-clk-rockchip-Pass-NULL-as-reg-pointer-when-registering-GR.patch b/target/linux/rockchip/patches-6.12/032-25-v6.16-clk-rockchip-Pass-NULL-as-reg-pointer-when-registering-GR.patch new file mode 100644 index 0000000000..12711fdf69 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-25-v6.16-clk-rockchip-Pass-NULL-as-reg-pointer-when-registering-GR.patch @@ -0,0 +1,30 @@ +From 61bf658a4d95e8f982b6e66dea763bff57996349 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Sat, 10 May 2025 07:52:49 +0000 +Subject: [PATCH] clk: rockchip: Pass NULL as reg pointer when registering GRF + MMC clocks + +This corrects the type and suppresses sparse warnings about passing +plain integers as NULL pointer. + +Fixes: 621ba4d9f6db ("clk: rockchip: Support MMC clocks in GRF region") +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202505100302.YVtB1zhF-lkp@intel.com/ +Signed-off-by: Yao Zi +Link: https://lore.kernel.org/r/20250510075248.34006-2-ziyao@disroot.org +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/rockchip/clk.c ++++ b/drivers/clk/rockchip/clk.c +@@ -622,7 +622,7 @@ void rockchip_clk_register_branches(stru + clk = rockchip_clk_register_mmc( + list->name, + list->parent_names, list->num_parents, +- 0, ++ NULL, + grf, list->muxdiv_offset, + list->div_shift + ); diff --git a/target/linux/rockchip/patches-6.12/032-26-v6.16-clk-rockchip-rk3528-Add-SD-SDIO-tuning-clocks-in-GRF.patch b/target/linux/rockchip/patches-6.12/032-26-v6.16-clk-rockchip-rk3528-Add-SD-SDIO-tuning-clocks-in-GRF.patch new file mode 100644 index 0000000000..f35af6bec0 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-26-v6.16-clk-rockchip-rk3528-Add-SD-SDIO-tuning-clocks-in-GRF.patch @@ -0,0 +1,157 @@ +From 306d2f5ddaa765f04ffb54fc9437a6318f904b53 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 6 May 2025 09:22:04 +0000 +Subject: [PATCH] clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF + region + +These clocks locate in VO and VPU GRF, serving for SD/SDIO controller +tuning purpose. Add their definitions and register them in driver if +corresponding GRF is available. + +GRFs are looked up by compatible to simplify devicetree binding. + +Signed-off-by: Yao Zi +Link: https://lore.kernel.org/r/20250506092206.46143-4-ziyao@disroot.org +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3528.c | 82 ++++++++++++++++++++++++++++--- + drivers/clk/rockchip/clk.h | 5 ++ + 2 files changed, 81 insertions(+), 6 deletions(-) + +--- a/drivers/clk/rockchip/clk-rk3528.c ++++ b/drivers/clk/rockchip/clk-rk3528.c +@@ -10,6 +10,8 @@ + #include + #include + #include ++#include ++#include + + #include + +@@ -1061,23 +1063,65 @@ static struct rockchip_clk_branch rk3528 + 0, 1, 1), + }; + ++static struct rockchip_clk_branch rk3528_vo_clk_branches[] __initdata = { ++ MMC_GRF(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc0", ++ RK3528_SDMMC_CON(0), 1, grf_type_vo), ++ MMC_GRF(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc0", ++ RK3528_SDMMC_CON(1), 1, grf_type_vo), ++}; ++ ++static struct rockchip_clk_branch rk3528_vpu_clk_branches[] __initdata = { ++ MMC_GRF(SCLK_SDIO0_DRV, "sdio0_drv", "cclk_src_sdio0", ++ RK3528_SDIO0_CON(0), 1, grf_type_vpu), ++ MMC_GRF(SCLK_SDIO0_SAMPLE, "sdio0_sample", "cclk_src_sdio0", ++ RK3528_SDIO0_CON(1), 1, grf_type_vpu), ++ MMC_GRF(SCLK_SDIO1_DRV, "sdio1_drv", "cclk_src_sdio1", ++ RK3528_SDIO1_CON(0), 1, grf_type_vpu), ++ MMC_GRF(SCLK_SDIO1_SAMPLE, "sdio1_sample", "cclk_src_sdio1", ++ RK3528_SDIO1_CON(1), 1, grf_type_vpu), ++}; ++ + static int __init clk_rk3528_probe(struct platform_device *pdev) + { +- struct rockchip_clk_provider *ctx; ++ unsigned long nr_vpu_branches = ARRAY_SIZE(rk3528_vpu_clk_branches); ++ unsigned long nr_vo_branches = ARRAY_SIZE(rk3528_vo_clk_branches); ++ unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches); ++ unsigned long nr_clks, nr_vo_clks, nr_vpu_clks; ++ struct rockchip_aux_grf *vo_grf_e, *vpu_grf_e; ++ struct regmap *vo_grf, *vpu_grf; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; +- unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches); +- unsigned long nr_clks; ++ struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + +- nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches, +- nr_branches) + 1; +- + reg_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg_base)) + return dev_err_probe(dev, PTR_ERR(reg_base), + "could not map cru region"); + ++ nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches, ++ nr_branches) + 1; ++ ++ vo_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vo-grf"); ++ if (!IS_ERR(vo_grf)) { ++ nr_vo_clks = rockchip_clk_find_max_clk_id(rk3528_vo_clk_branches, ++ nr_vo_branches) + 1; ++ nr_clks = max(nr_clks, nr_vo_clks); ++ } else if (PTR_ERR(vo_grf) != -ENODEV) { ++ return dev_err_probe(dev, PTR_ERR(vo_grf), ++ "failed to look up VO GRF\n"); ++ } ++ ++ vpu_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vpu-grf"); ++ if (!IS_ERR(vpu_grf)) { ++ nr_vpu_clks = rockchip_clk_find_max_clk_id(rk3528_vpu_clk_branches, ++ nr_vpu_branches) + 1; ++ nr_clks = max(nr_clks, nr_vpu_clks); ++ } else if (PTR_ERR(vpu_grf) != -ENODEV) { ++ return dev_err_probe(dev, PTR_ERR(vpu_grf), ++ "failed to look up VPU GRF\n"); ++ } ++ + ctx = rockchip_clk_init(np, reg_base, nr_clks); + if (IS_ERR(ctx)) + return dev_err_probe(dev, PTR_ERR(ctx), +@@ -1092,6 +1136,32 @@ static int __init clk_rk3528_probe(struc + ARRAY_SIZE(rk3528_cpuclk_rates)); + rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches); + ++ if (!IS_ERR(vo_grf)) { ++ vo_grf_e = devm_kzalloc(dev, sizeof(*vo_grf_e), GFP_KERNEL); ++ if (!vo_grf_e) ++ return -ENOMEM; ++ ++ vo_grf_e->grf = vo_grf; ++ vo_grf_e->type = grf_type_vo; ++ hash_add(ctx->aux_grf_table, &vo_grf_e->node, grf_type_vo); ++ ++ rockchip_clk_register_branches(ctx, rk3528_vo_clk_branches, ++ nr_vo_branches); ++ } ++ ++ if (!IS_ERR(vpu_grf)) { ++ vpu_grf_e = devm_kzalloc(dev, sizeof(*vpu_grf_e), GFP_KERNEL); ++ if (!vpu_grf_e) ++ return -ENOMEM; ++ ++ vpu_grf_e->grf = vpu_grf; ++ vpu_grf_e->type = grf_type_vpu; ++ hash_add(ctx->aux_grf_table, &vpu_grf_e->node, grf_type_vpu); ++ ++ rockchip_clk_register_branches(ctx, rk3528_vpu_clk_branches, ++ nr_vpu_branches); ++ } ++ + rk3528_rst_init(np, reg_base); + + rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL); +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -218,6 +218,9 @@ struct clk; + #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) + #define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) + #define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) ++#define RK3528_SDMMC_CON(x) ((x) * 0x4 + 0x24) ++#define RK3528_SDIO0_CON(x) ((x) * 0x4 + 0x4) ++#define RK3528_SDIO1_CON(x) ((x) * 0x4 + 0xc) + #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) + #define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) + #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) +@@ -407,6 +410,8 @@ enum rockchip_grf_type { + grf_type_pmu0, + grf_type_pmu1, + grf_type_ioc, ++ grf_type_vo, ++ grf_type_vpu, + }; + + /* ceil(sqrt(enums in rockchip_grf_type - 1)) */ diff --git a/target/linux/rockchip/patches-6.12/032-27-v6.16-clk-rockchip-rk3528-add-slab-h-header-include.patch b/target/linux/rockchip/patches-6.12/032-27-v6.16-clk-rockchip-rk3528-add-slab-h-header-include.patch new file mode 100644 index 0000000000..1b03b1fd61 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-27-v6.16-clk-rockchip-rk3528-add-slab-h-header-include.patch @@ -0,0 +1,30 @@ +From 276036283716b9135525b195675ea42801bde204 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Thu, 15 May 2025 10:26:52 +0200 +Subject: [PATCH] clk: rockchip: rk3528: add slab.h header include + +The newly added GRF types introduced kzalloc usage into the rk3528. +At least for the similar rk3576 driver, the kernel-test-robot reported the +missing prototype, which warranted adding a slab.h include. + +While it did not complain about the rk3528, so the header might be included +"accidentially" right now, add a real include to make sure we keep it +included in the future. + +Fixes: 306d2f5ddaa7 ("clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region") +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20250515082652.2503063-2-heiko@sntech.de +--- + drivers/clk/rockchip/clk-rk3528.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/rockchip/clk-rk3528.c ++++ b/drivers/clk/rockchip/clk-rk3528.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + #include + diff --git a/target/linux/rockchip/patches-6.12/032-28-v6.17-dt-bindings-power-rockchip-Add-support-for-RK3528.patch b/target/linux/rockchip/patches-6.12/032-28-v6.17-dt-bindings-power-rockchip-Add-support-for-RK3528.patch new file mode 100644 index 0000000000..d235a4c2c1 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/032-28-v6.17-dt-bindings-power-rockchip-Add-support-for-RK3528.patch @@ -0,0 +1,49 @@ +From 8358102806c619d8d6c814010173617fb374b77e Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 18 May 2025 22:06:48 +0000 +Subject: [PATCH] dt-bindings: power: rockchip: Add support for RK3528 + +Add the compatible string and power domains for RK3528 SoC. + +Signed-off-by: Jonas Karlman +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20250518220707.669515-2-jonas@kwiboo.se +Signed-off-by: Ulf Hansson +--- + .../power/rockchip,power-controller.yaml | 1 + + .../dt-bindings/power/rockchip,rk3528-power.h | 19 +++++++++++++++++++ + 2 files changed, 20 insertions(+) + create mode 100644 include/dt-bindings/power/rockchip,rk3528-power.h + +--- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml ++++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +@@ -40,6 +40,7 @@ properties: + - rockchip,rk3366-power-controller + - rockchip,rk3368-power-controller + - rockchip,rk3399-power-controller ++ - rockchip,rk3528-power-controller + - rockchip,rk3568-power-controller + - rockchip,rk3576-power-controller + - rockchip,rk3588-power-controller +--- /dev/null ++++ b/include/dt-bindings/power/rockchip,rk3528-power.h +@@ -0,0 +1,19 @@ ++/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ ++#ifndef __DT_BINDINGS_POWER_RK3528_POWER_H__ ++#define __DT_BINDINGS_POWER_RK3528_POWER_H__ ++ ++#define RK3528_PD_PMU 0 ++#define RK3528_PD_BUS 1 ++#define RK3528_PD_DDR 2 ++#define RK3528_PD_MSCH 3 ++ ++/* VD_GPU */ ++#define RK3528_PD_GPU 4 ++ ++/* VD_LOGIC */ ++#define RK3528_PD_RKVDEC 5 ++#define RK3528_PD_RKVENC 6 ++#define RK3528_PD_VO 7 ++#define RK3528_PD_VPU 8 ++ ++#endif diff --git a/target/linux/rockchip/patches-6.12/033-04-v6.17-pmdomain-rockchip-Add-support-for-RK3528.patch b/target/linux/rockchip/patches-6.12/033-04-v6.17-pmdomain-rockchip-Add-support-for-RK3528.patch new file mode 100644 index 0000000000..8d06cc6385 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/033-04-v6.17-pmdomain-rockchip-Add-support-for-RK3528.patch @@ -0,0 +1,81 @@ +From 3068b386232f0a7d84da6d1366dbd0b7926c5652 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 18 May 2025 22:06:49 +0000 +Subject: [PATCH] pmdomain: rockchip: Add support for RK3528 + +Add configuration and power domains for RK3528 SoC. + +Only PD_GPU can fully be powered down. PD_RKVDEC, PD_RKVENC, PD_VO and +PD_VPU are used by miscellaneous devices in RK3528. + +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20250518220707.669515-3-jonas@kwiboo.se +Signed-off-by: Ulf Hansson +--- + drivers/pmdomain/rockchip/pm-domains.c | 27 ++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/drivers/pmdomain/rockchip/pm-domains.c ++++ b/drivers/pmdomain/rockchip/pm-domains.c +@@ -34,6 +34,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -196,6 +197,9 @@ struct rockchip_pmu { + #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, req, wakeup) + ++#define DOMAIN_RK3528(name, pwr, req) \ ++ DOMAIN_M(name, pwr, pwr, req, req, req, false) ++ + #define DOMAIN_RK3568(name, pwr, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) + +@@ -1139,6 +1143,14 @@ static const struct rockchip_domain_info + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), + }; + ++static const struct rockchip_domain_info rk3528_pm_domains[] = { ++ [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4)), ++ [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5)), ++ [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6)), ++ [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7)), ++ [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8)), ++}; ++ + static const struct rockchip_domain_info rk3568_pm_domains[] = { + [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), + [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), +@@ -1340,6 +1352,17 @@ static const struct rockchip_pmu_info rk + .domain_info = rk3399_pm_domains, + }; + ++static const struct rockchip_pmu_info rk3528_pmu = { ++ .pwr_offset = 0x1210, ++ .status_offset = 0x1230, ++ .req_offset = 0x1110, ++ .idle_offset = 0x1128, ++ .ack_offset = 0x1120, ++ ++ .num_domains = ARRAY_SIZE(rk3528_pm_domains), ++ .domain_info = rk3528_pm_domains, ++}; ++ + static const struct rockchip_pmu_info rk3568_pmu = { + .pwr_offset = 0xa0, + .status_offset = 0x98, +@@ -1439,6 +1462,10 @@ static const struct of_device_id rockchi + .data = (void *)&rk3399_pmu, + }, + { ++ .compatible = "rockchip,rk3528-power-controller", ++ .data = (void *)&rk3528_pmu, ++ }, ++ { + .compatible = "rockchip,rk3568-power-controller", + .data = (void *)&rk3568_pmu, + }, diff --git a/target/linux/rockchip/patches-6.12/036-07-v6.18-phy-rockchip-naneng-combphy-Add-SoC-prefix-to-register.patch b/target/linux/rockchip/patches-6.12/036-07-v6.18-phy-rockchip-naneng-combphy-Add-SoC-prefix-to-register.patch new file mode 100644 index 0000000000..8ad4bb5516 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/036-07-v6.18-phy-rockchip-naneng-combphy-Add-SoC-prefix-to-register.patch @@ -0,0 +1,758 @@ +From 11f1896e60f61ca1948cb7920585a79ce5254c0c Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Mon, 28 Jul 2025 10:29:46 +0000 +Subject: [PATCH] phy: rockchip: naneng-combphy: Add SoC prefix to register + definitions + +All supported variants of naneng-combphy follow a register layout +similar to the RK3568 variant with some exceptions of SoC-specific +registers. + +Add RK3568 prefix for the common set of registers and the corresponding +SoC prefix for SoC-specific registers, making usage of definitions clear +and preparing for future COMBPHY variants with a different register +layout. + +Signed-off-by: Yao Zi +Reviewed-by: Heiko Stuebner +Reviewed-by: Neil Armstrong +Link: https://lore.kernel.org/r/20250728102947.38984-6-ziyao@disroot.org +Signed-off-by: Vinod Koul +--- + .../rockchip/phy-rockchip-naneng-combphy.c | 560 +++++++++--------- + 1 file changed, 288 insertions(+), 272 deletions(-) + +--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -21,78 +21,80 @@ + #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) + + /* COMBO PHY REG */ +-#define PHYREG6 0x14 +-#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6) +-#define PHYREG6_PLL_DIV_SHIFT 6 +-#define PHYREG6_PLL_DIV_2 1 +- +-#define PHYREG7 0x18 +-#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4) +-#define PHYREG7_TX_RTERM_SHIFT 4 +-#define PHYREG7_TX_RTERM_50OHM 8 +-#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0) +-#define PHYREG7_RX_RTERM_SHIFT 0 +-#define PHYREG7_RX_RTERM_44OHM 15 +- +-#define PHYREG8 0x1C +-#define PHYREG8_SSC_EN BIT(4) +- +-#define PHYREG10 0x24 +-#define PHYREG10_SSC_PCM_MASK GENMASK(3, 0) +-#define PHYREG10_SSC_PCM_3500PPM 7 +- +-#define PHYREG11 0x28 +-#define PHYREG11_SU_TRIM_0_7 0xF0 +- +-#define PHYREG12 0x2C +-#define PHYREG12_PLL_LPF_ADJ_VALUE 4 +- +-#define PHYREG13 0x30 +-#define PHYREG13_RESISTER_MASK GENMASK(5, 4) +-#define PHYREG13_RESISTER_SHIFT 0x4 +-#define PHYREG13_RESISTER_HIGH_Z 3 +-#define PHYREG13_CKRCV_AMP0 BIT(7) +- +-#define PHYREG14 0x34 +-#define PHYREG14_CKRCV_AMP1 BIT(0) +- +-#define PHYREG15 0x38 +-#define PHYREG15_CTLE_EN BIT(0) +-#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6) +-#define PHYREG15_SSC_CNT_SHIFT 6 +-#define PHYREG15_SSC_CNT_VALUE 1 +- +-#define PHYREG16 0x3C +-#define PHYREG16_SSC_CNT_VALUE 0x5f +- +-#define PHYREG17 0x40 +- +-#define PHYREG18 0x44 +-#define PHYREG18_PLL_LOOP 0x32 +- +-#define PHYREG21 0x50 +-#define PHYREG21_RX_SQUELCH_VAL 0x0D +- +-#define PHYREG27 0x6C +-#define PHYREG27_RX_TRIM_RK3588 0x4C +- +-#define PHYREG30 0x74 +- +-#define PHYREG32 0x7C +-#define PHYREG32_SSC_MASK GENMASK(7, 4) +-#define PHYREG32_SSC_DIR_MASK GENMASK(5, 4) +-#define PHYREG32_SSC_DIR_SHIFT 4 +-#define PHYREG32_SSC_UPWARD 0 +-#define PHYREG32_SSC_DOWNWARD 1 +-#define PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6) +-#define PHYREG32_SSC_OFFSET_SHIFT 6 +-#define PHYREG32_SSC_OFFSET_500PPM 1 +- +-#define PHYREG33 0x80 +-#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) +-#define PHYREG33_PLL_KVCO_SHIFT 2 +-#define PHYREG33_PLL_KVCO_VALUE 2 +-#define PHYREG33_PLL_KVCO_VALUE_RK3576 4 ++#define RK3568_PHYREG6 0x14 ++#define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6) ++#define RK3568_PHYREG6_PLL_DIV_SHIFT 6 ++#define RK3568_PHYREG6_PLL_DIV_2 1 ++ ++#define RK3568_PHYREG7 0x18 ++#define RK3568_PHYREG7_TX_RTERM_MASK GENMASK(7, 4) ++#define RK3568_PHYREG7_TX_RTERM_SHIFT 4 ++#define RK3568_PHYREG7_TX_RTERM_50OHM 8 ++#define RK3568_PHYREG7_RX_RTERM_MASK GENMASK(3, 0) ++#define RK3568_PHYREG7_RX_RTERM_SHIFT 0 ++#define RK3568_PHYREG7_RX_RTERM_44OHM 15 ++ ++#define RK3568_PHYREG8 0x1C ++#define RK3568_PHYREG8_SSC_EN BIT(4) ++ ++#define RK3568_PHYREG11 0x28 ++#define RK3568_PHYREG11_SU_TRIM_0_7 0xF0 ++ ++#define RK3568_PHYREG12 0x2C ++#define RK3568_PHYREG12_PLL_LPF_ADJ_VALUE 4 ++ ++#define RK3568_PHYREG13 0x30 ++#define RK3568_PHYREG13_RESISTER_MASK GENMASK(5, 4) ++#define RK3568_PHYREG13_RESISTER_SHIFT 0x4 ++#define RK3568_PHYREG13_RESISTER_HIGH_Z 3 ++#define RK3568_PHYREG13_CKRCV_AMP0 BIT(7) ++ ++#define RK3568_PHYREG14 0x34 ++#define RK3568_PHYREG14_CKRCV_AMP1 BIT(0) ++ ++#define RK3568_PHYREG15 0x38 ++#define RK3568_PHYREG15_CTLE_EN BIT(0) ++#define RK3568_PHYREG15_SSC_CNT_MASK GENMASK(7, 6) ++#define RK3568_PHYREG15_SSC_CNT_SHIFT 6 ++#define RK3568_PHYREG15_SSC_CNT_VALUE 1 ++ ++#define RK3568_PHYREG16 0x3C ++#define RK3568_PHYREG16_SSC_CNT_VALUE 0x5f ++ ++#define RK3568_PHYREG18 0x44 ++#define RK3568_PHYREG18_PLL_LOOP 0x32 ++ ++#define RK3568_PHYREG32 0x7C ++#define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4) ++#define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4) ++#define RK3568_PHYREG32_SSC_DIR_SHIFT 4 ++#define RK3568_PHYREG32_SSC_UPWARD 0 ++#define RK3568_PHYREG32_SSC_DOWNWARD 1 ++#define RK3568_PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6) ++#define RK3568_PHYREG32_SSC_OFFSET_SHIFT 6 ++#define RK3568_PHYREG32_SSC_OFFSET_500PPM 1 ++ ++#define RK3568_PHYREG33 0x80 ++#define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) ++#define RK3568_PHYREG33_PLL_KVCO_SHIFT 2 ++#define RK3568_PHYREG33_PLL_KVCO_VALUE 2 ++#define RK3576_PHYREG33_PLL_KVCO_VALUE 4 ++ ++/* RK3588 COMBO PHY registers */ ++#define RK3588_PHYREG27 0x6C ++#define RK3588_PHYREG27_RX_TRIM 0x4C ++ ++/* RK3576 COMBO PHY registers */ ++#define RK3576_PHYREG10 0x24 ++#define RK3576_PHYREG10_SSC_PCM_MASK GENMASK(3, 0) ++#define RK3576_PHYREG10_SSC_PCM_3500PPM 7 ++ ++#define RK3576_PHYREG17 0x40 ++ ++#define RK3576_PHYREG21 0x50 ++#define RK3576_PHYREG21_RX_SQUELCH_VAL 0x0D ++ ++#define RK3576_PHYREG30 0x74 + + struct rockchip_combphy_priv; + +@@ -407,9 +409,9 @@ static int rk3568_combphy_cfg(struct roc + switch (priv->type) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum. */ +- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, +- PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, +- PHYREG32); ++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; ++ ++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); +@@ -419,30 +421,28 @@ static int rk3568_combphy_cfg(struct roc + + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum. */ +- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, +- PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, +- PHYREG32); ++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT, ++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); + + /* Enable adaptive CTLE for USB3.0 Rx. */ +- val = readl(priv->mmio + PHYREG15); +- val |= PHYREG15_CTLE_EN; +- writel(val, priv->mmio + PHYREG15); ++ val = readl(priv->mmio + RK3568_PHYREG15); ++ val |= RK3568_PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + RK3568_PHYREG15); + + /* Set PLL KVCO fine tuning signals. */ +- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, +- PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, +- PHYREG33); ++ val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33); + + /* Enable controlling random jitter. */ +- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); + + /* Set PLL input clock divider 1/2. */ +- rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, +- PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, +- PHYREG6); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, ++ RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT, ++ RK3568_PHYREG6); + +- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); +- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); ++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); +@@ -460,16 +460,16 @@ static int rk3568_combphy_cfg(struct roc + + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx. */ +- val = readl(priv->mmio + PHYREG15); +- val |= PHYREG15_CTLE_EN; +- writel(val, priv->mmio + PHYREG15); ++ val = readl(priv->mmio + RK3568_PHYREG15); ++ val |= RK3568_PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + RK3568_PHYREG15); + /* + * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. + * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) + */ +- val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; +- val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; +- writel(val, priv->mmio + PHYREG7); ++ val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; ++ val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; ++ writel(val, priv->mmio + RK3568_PHYREG7); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); +@@ -504,11 +504,11 @@ static int rk3568_combphy_cfg(struct roc + case REF_CLOCK_24MHz: + if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ +- val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; +- rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, +- val, PHYREG15); ++ val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, ++ val, RK3568_PHYREG15); + +- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); + } + break; + +@@ -520,24 +520,26 @@ static int rk3568_combphy_cfg(struct roc + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->type == PHY_TYPE_PCIE) { + /* PLL KVCO fine tuning. */ +- val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT; +- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, +- val, PHYREG33); ++ val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, ++ val, RK3568_PHYREG33); + + /* Enable controlling random jitter. */ +- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); + +- val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; +- rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, +- val, PHYREG6); ++ val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, ++ val, RK3568_PHYREG6); + +- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); +- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); ++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); + } else if (priv->type == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ +- val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; +- val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; +- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; ++ val |= RK3568_PHYREG32_SSC_OFFSET_500PPM << ++ RK3568_PHYREG32_SSC_OFFSET_SHIFT; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, ++ RK3568_PHYREG32); + } + break; + +@@ -549,20 +551,21 @@ static int rk3568_combphy_cfg(struct roc + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { +- val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; +- val |= PHYREG13_CKRCV_AMP0; +- rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); +- +- val = readl(priv->mmio + PHYREG14); +- val |= PHYREG14_CKRCV_AMP1; +- writel(val, priv->mmio + PHYREG14); ++ val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT; ++ val |= RK3568_PHYREG13_CKRCV_AMP0; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, ++ RK3568_PHYREG13); ++ ++ val = readl(priv->mmio + RK3568_PHYREG14); ++ val |= RK3568_PHYREG14_CKRCV_AMP1; ++ writel(val, priv->mmio + RK3568_PHYREG14); + } + } + + if (priv->enable_ssc) { +- val = readl(priv->mmio + PHYREG8); +- val |= PHYREG8_SSC_EN; +- writel(val, priv->mmio + PHYREG8); ++ val = readl(priv->mmio + RK3568_PHYREG8); ++ val |= RK3568_PHYREG8_SSC_EN; ++ writel(val, priv->mmio + RK3568_PHYREG8); + } + + return 0; +@@ -623,8 +626,8 @@ static int rk3576_combphy_cfg(struct roc + switch (priv->type) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ +- val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD); +- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); +@@ -634,32 +637,33 @@ static int rk3576_combphy_cfg(struct roc + + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ +- val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD); +- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); + + /* Enable adaptive CTLE for USB3.0 Rx */ +- val = readl(priv->mmio + PHYREG15); +- val |= PHYREG15_CTLE_EN; +- writel(val, priv->mmio + PHYREG15); ++ val = readl(priv->mmio + RK3568_PHYREG15); ++ val |= RK3568_PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + RK3568_PHYREG15); + + /* Set PLL KVCO fine tuning signals */ +- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3), ++ RK3568_PHYREG33); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ +- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); + + /* Set PLL input clock divider 1/2 */ +- val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2); +- rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6); ++ val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6); + + /* Set PLL loop divider */ +- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); ++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ +- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); + + /* Set Rx squelch input filler bandwidth */ +- writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21); ++ writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); +@@ -668,14 +672,14 @@ static int rk3576_combphy_cfg(struct roc + + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx */ +- val = readl(priv->mmio + PHYREG15); +- val |= PHYREG15_CTLE_EN; +- writel(val, priv->mmio + PHYREG15); ++ val = readl(priv->mmio + RK3568_PHYREG15); ++ val |= RK3568_PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + RK3568_PHYREG15); + + /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ +- val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; +- val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; +- writel(val, priv->mmio + PHYREG7); ++ val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; ++ val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; ++ writel(val, priv->mmio + RK3568_PHYREG7); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); +@@ -697,19 +701,21 @@ static int rk3576_combphy_cfg(struct roc + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); + if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ +- val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE); +- rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, +- val, PHYREG15); ++ val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK, ++ RK3568_PHYREG15_SSC_CNT_VALUE); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, ++ val, RK3568_PHYREG15); + +- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); + } else if (priv->type == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ +- val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); +- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, +- val, PHYREG33); ++ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, ++ RK3576_PHYREG33_PLL_KVCO_VALUE); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, ++ val, RK3568_PHYREG33); + + /* Set up rx_pck invert and rx msb to disable */ +- writel(0x00, priv->mmio + PHYREG27); ++ writel(0x00, priv->mmio + RK3588_PHYREG27); + + /* + * Set up SU adjust signal: +@@ -717,11 +723,11 @@ static int rk3576_combphy_cfg(struct roc + * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b011 + * su_trim[31:24], CKDRV adjust + */ +- writel(0x90, priv->mmio + PHYREG11); +- writel(0x02, priv->mmio + PHYREG12); +- writel(0x57, priv->mmio + PHYREG14); ++ writel(0x90, priv->mmio + RK3568_PHYREG11); ++ writel(0x02, priv->mmio + RK3568_PHYREG12); ++ writel(0x57, priv->mmio + RK3568_PHYREG14); + +- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); + } + break; + +@@ -733,15 +739,16 @@ static int rk3576_combphy_cfg(struct roc + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->type == PHY_TYPE_PCIE) { + /* gate_tx_pck_sel length select work for L1SS */ +- writel(0xc0, priv->mmio + PHYREG30); ++ writel(0xc0, priv->mmio + RK3576_PHYREG30); + + /* PLL KVCO tuning fine */ +- val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); +- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, +- val, PHYREG33); ++ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, ++ RK3576_PHYREG33_PLL_KVCO_VALUE); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, ++ val, RK3568_PHYREG33); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ +- writel(0x4c, priv->mmio + PHYREG27); ++ writel(0x4c, priv->mmio + RK3588_PHYREG27); + + /* + * Set up SU adjust signal: +@@ -751,20 +758,23 @@ static int rk3576_combphy_cfg(struct roc + * su_trim[23:16], CKRCV adjust + * su_trim[31:24], CKDRV adjust + */ +- writel(0x90, priv->mmio + PHYREG11); +- writel(0x43, priv->mmio + PHYREG12); +- writel(0x88, priv->mmio + PHYREG13); +- writel(0x56, priv->mmio + PHYREG14); ++ writel(0x90, priv->mmio + RK3568_PHYREG11); ++ writel(0x43, priv->mmio + RK3568_PHYREG12); ++ writel(0x88, priv->mmio + RK3568_PHYREG13); ++ writel(0x56, priv->mmio + RK3568_PHYREG14); + } else if (priv->type == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ +- val = FIELD_PREP(PHYREG32_SSC_DIR_MASK, PHYREG32_SSC_DOWNWARD); +- val |= FIELD_PREP(PHYREG32_SSC_OFFSET_MASK, PHYREG32_SSC_OFFSET_500PPM); +- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK, ++ RK3568_PHYREG32_SSC_DOWNWARD); ++ val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK, ++ RK3568_PHYREG32_SSC_OFFSET_500PPM); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, ++ RK3568_PHYREG32); + + /* ssc ppm adjust to 3500ppm */ +- rockchip_combphy_updatel(priv, PHYREG10_SSC_PCM_MASK, +- PHYREG10_SSC_PCM_3500PPM, +- PHYREG10); ++ rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK, ++ RK3576_PHYREG10_SSC_PCM_3500PPM, ++ RK3576_PHYREG10); + } + break; + +@@ -776,12 +786,13 @@ static int rk3576_combphy_cfg(struct roc + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { +- val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); +- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, +- val, PHYREG33); ++ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, ++ RK3576_PHYREG33_PLL_KVCO_VALUE); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, ++ val, RK3568_PHYREG33); + + /* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */ +- writel(0x0c, priv->mmio + PHYREG27); ++ writel(0x0c, priv->mmio + RK3588_PHYREG27); + + /* + * Set up SU adjust signal: +@@ -791,25 +802,25 @@ static int rk3576_combphy_cfg(struct roc + * su_trim[23:16], CKRCV adjust + * su_trim[31:24], CKDRV adjust + */ +- writel(0x90, priv->mmio + PHYREG11); +- writel(0x43, priv->mmio + PHYREG12); +- writel(0x88, priv->mmio + PHYREG13); +- writel(0x56, priv->mmio + PHYREG14); ++ writel(0x90, priv->mmio + RK3568_PHYREG11); ++ writel(0x43, priv->mmio + RK3568_PHYREG12); ++ writel(0x88, priv->mmio + RK3568_PHYREG13); ++ writel(0x56, priv->mmio + RK3568_PHYREG14); + } + } + + if (priv->enable_ssc) { +- val = readl(priv->mmio + PHYREG8); +- val |= PHYREG8_SSC_EN; +- writel(val, priv->mmio + PHYREG8); ++ val = readl(priv->mmio + RK3568_PHYREG8); ++ val |= RK3568_PHYREG8_SSC_EN; ++ writel(val, priv->mmio + RK3568_PHYREG8); + + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { + /* Set PLL loop divider */ +- writel(0x00, priv->mmio + PHYREG17); +- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); ++ writel(0x00, priv->mmio + RK3576_PHYREG17); ++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); + + /* Set up rx_pck invert and rx msb to disable */ +- writel(0x00, priv->mmio + PHYREG27); ++ writel(0x00, priv->mmio + RK3588_PHYREG27); + + /* + * Set up SU adjust signal: +@@ -818,16 +829,17 @@ static int rk3576_combphy_cfg(struct roc + * su_trim[23:16], CKRCV adjust + * su_trim[31:24], CKDRV adjust + */ +- writel(0x90, priv->mmio + PHYREG11); +- writel(0x02, priv->mmio + PHYREG12); +- writel(0x08, priv->mmio + PHYREG13); +- writel(0x57, priv->mmio + PHYREG14); +- writel(0x40, priv->mmio + PHYREG15); +- +- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); +- +- val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); +- writel(val, priv->mmio + PHYREG33); ++ writel(0x90, priv->mmio + RK3568_PHYREG11); ++ writel(0x02, priv->mmio + RK3568_PHYREG12); ++ writel(0x08, priv->mmio + RK3568_PHYREG13); ++ writel(0x57, priv->mmio + RK3568_PHYREG14); ++ writel(0x40, priv->mmio + RK3568_PHYREG15); ++ ++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); ++ ++ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, ++ RK3576_PHYREG33_PLL_KVCO_VALUE); ++ writel(val, priv->mmio + RK3568_PHYREG33); + } + } + +@@ -897,30 +909,28 @@ static int rk3588_combphy_cfg(struct roc + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ +- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, +- PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, +- PHYREG32); ++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); + + /* Enable adaptive CTLE for USB3.0 Rx. */ +- val = readl(priv->mmio + PHYREG15); +- val |= PHYREG15_CTLE_EN; +- writel(val, priv->mmio + PHYREG15); ++ val = readl(priv->mmio + RK3568_PHYREG15); ++ val |= RK3568_PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + RK3568_PHYREG15); + + /* Set PLL KVCO fine tuning signals. */ +- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, +- PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, +- PHYREG33); ++ val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT, ++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33); + + /* Enable controlling random jitter. */ +- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); + + /* Set PLL input clock divider 1/2. */ +- rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, +- PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, +- PHYREG6); ++ rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, ++ RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT, ++ RK3568_PHYREG6); + +- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); +- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); ++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); +@@ -928,16 +938,16 @@ static int rk3588_combphy_cfg(struct roc + break; + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx. */ +- val = readl(priv->mmio + PHYREG15); +- val |= PHYREG15_CTLE_EN; +- writel(val, priv->mmio + PHYREG15); ++ val = readl(priv->mmio + RK3568_PHYREG15); ++ val |= RK3568_PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + RK3568_PHYREG15); + /* + * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. + * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) + */ +- val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; +- val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; +- writel(val, priv->mmio + PHYREG7); ++ val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; ++ val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; ++ writel(val, priv->mmio + RK3568_PHYREG7); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); +@@ -959,11 +969,11 @@ static int rk3588_combphy_cfg(struct roc + case REF_CLOCK_24MHz: + if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ +- val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; +- rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, +- val, PHYREG15); ++ val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, ++ val, RK3568_PHYREG15); + +- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); + } + break; + +@@ -974,23 +984,25 @@ static int rk3588_combphy_cfg(struct roc + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->type == PHY_TYPE_PCIE) { + /* PLL KVCO fine tuning. */ +- val = 4 << PHYREG33_PLL_KVCO_SHIFT; +- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, +- val, PHYREG33); ++ val = 4 << RK3568_PHYREG33_PLL_KVCO_SHIFT; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, ++ val, RK3568_PHYREG33); + + /* Enable controlling random jitter. */ +- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ +- writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); ++ writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27); + + /* Set up su_trim: */ +- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); + } else if (priv->type == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ +- val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; +- val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; +- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; ++ val |= RK3568_PHYREG32_SSC_OFFSET_500PPM << ++ RK3568_PHYREG32_SSC_OFFSET_SHIFT; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, ++ RK3568_PHYREG32); + } + break; + default: +@@ -1001,20 +1013,21 @@ static int rk3588_combphy_cfg(struct roc + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { +- val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; +- val |= PHYREG13_CKRCV_AMP0; +- rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); +- +- val = readl(priv->mmio + PHYREG14); +- val |= PHYREG14_CKRCV_AMP1; +- writel(val, priv->mmio + PHYREG14); ++ val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT; ++ val |= RK3568_PHYREG13_CKRCV_AMP0; ++ rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, ++ RK3568_PHYREG13); ++ ++ val = readl(priv->mmio + RK3568_PHYREG14); ++ val |= RK3568_PHYREG14_CKRCV_AMP1; ++ writel(val, priv->mmio + RK3568_PHYREG14); + } + } + + if (priv->enable_ssc) { +- val = readl(priv->mmio + PHYREG8); +- val |= PHYREG8_SSC_EN; +- writel(val, priv->mmio + PHYREG8); ++ val = readl(priv->mmio + RK3568_PHYREG8); ++ val |= RK3568_PHYREG8_SSC_EN; ++ writel(val, priv->mmio + RK3568_PHYREG8); + } + + return 0; diff --git a/target/linux/rockchip/patches-6.12/036-08-v6.18-phy-rockchip-naneng-combphy-Add-RK3528-support.patch b/target/linux/rockchip/patches-6.12/036-08-v6.18-phy-rockchip-naneng-combphy-Add-RK3528-support.patch new file mode 100644 index 0000000000..c95e0ba932 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/036-08-v6.18-phy-rockchip-naneng-combphy-Add-RK3528-support.patch @@ -0,0 +1,231 @@ +From aee07ee1b97d9a3825e8db609a1c76157218cc59 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Mon, 28 Jul 2025 10:29:47 +0000 +Subject: [PATCH] phy: rockchip: naneng-combphy: Add RK3528 support + +Rockchip RK3528 integrates one naneng-combphy that is able to operate in +PCIe and USB3 mode. The control logic is similar to previous variants of +naneng-combphy but the register layout is apparently different from the +RK3568 one. + +Signed-off-by: Yao Zi +Reviewed-by: Heiko Stuebner +Reviewed-by: Neil Armstrong +Link: https://lore.kernel.org/r/20250728102947.38984-7-ziyao@disroot.org +Signed-off-by: Vinod Koul +--- + .../rockchip/phy-rockchip-naneng-combphy.c | 189 +++++++++++++++++- + 1 file changed, 188 insertions(+), 1 deletion(-) + +--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -20,7 +20,46 @@ + #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) + #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) + +-/* COMBO PHY REG */ ++/* RK3528 COMBO PHY REG */ ++#define RK3528_PHYREG6 0x18 ++#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10) ++#define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2 ++#define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4) ++#define RK3528_PHYREG6_SSC_UPWARD 0 ++#define RK3528_PHYREG6_SSC_DOWNWARD 1 ++ ++#define RK3528_PHYREG40 0x100 ++#define RK3528_PHYREG40_SSC_EN BIT(20) ++#define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0) ++#define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d ++ ++#define RK3528_PHYREG42 0x108 ++#define RK3528_PHYREG42_CKDRV_CLK_SEL BIT(29) ++#define RK3528_PHYREG42_CKDRV_CLK_PLL 0 ++#define RK3528_PHYREG42_CKDRV_CLK_CKRCV 1 ++#define RK3528_PHYREG42_PLL_LPF_R1_ADJ GENMASK(10, 7) ++#define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9 ++#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ GENMASK(6, 4) ++#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7 ++#define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0) ++#define RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE 0x0 ++ ++#define RK3528_PHYREG80 0x200 ++#define RK3528_PHYREG80_CTLE_EN BIT(17) ++ ++#define RK3528_PHYREG81 0x204 ++#define RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X BIT(5) ++#define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0) ++#define RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW 0x7 ++ ++#define RK3528_PHYREG83 0x20c ++#define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0) ++#define RK3528_PHYREG83_RX_SQUELCH_VALUE 0x6 ++ ++#define RK3528_PHYREG86 0x218 ++#define RK3528_PHYREG86_RTERM_DET_CLK_EN BIT(14) ++ ++/* RK3568 COMBO PHY REG */ + #define RK3568_PHYREG6 0x14 + #define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6) + #define RK3568_PHYREG6_PLL_DIV_SHIFT 6 +@@ -400,6 +439,150 @@ static int rockchip_combphy_probe(struct + return PTR_ERR_OR_ZERO(phy_provider); + } + ++static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) ++{ ++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; ++ unsigned long rate; ++ u32 val; ++ ++ /* Set SSC downward spread spectrum */ ++ val = FIELD_PREP(RK3528_PHYREG6_SSC_DIR, RK3528_PHYREG6_SSC_DOWNWARD); ++ rockchip_combphy_updatel(priv, RK3528_PHYREG6_SSC_DIR, val, RK3528_PHYREG6); ++ ++ switch (priv->type) { ++ case PHY_TYPE_PCIE: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); ++ break; ++ case PHY_TYPE_USB3: ++ /* Enable adaptive CTLE for USB3.0 Rx */ ++ rockchip_combphy_updatel(priv, RK3528_PHYREG80_CTLE_EN, RK3528_PHYREG80_CTLE_EN, ++ RK3528_PHYREG80); ++ ++ /* Set slow slew rate control for PI */ ++ val = FIELD_PREP(RK3528_PHYREG81_SLEW_RATE_CTRL, ++ RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW); ++ rockchip_combphy_updatel(priv, RK3528_PHYREG81_SLEW_RATE_CTRL, val, ++ RK3528_PHYREG81); ++ ++ /* Set CDR phase path with 2x gain */ ++ rockchip_combphy_updatel(priv, RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, ++ RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, RK3528_PHYREG81); ++ ++ /* Set Rx squelch input filler bandwidth */ ++ val = FIELD_PREP(RK3528_PHYREG83_RX_SQUELCH, RK3528_PHYREG83_RX_SQUELCH_VALUE); ++ rockchip_combphy_updatel(priv, RK3528_PHYREG83_RX_SQUELCH, val, RK3528_PHYREG83); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); ++ break; ++ default: ++ dev_err(priv->dev, "incompatible PHY type\n"); ++ return -EINVAL; ++ } ++ ++ rate = clk_get_rate(priv->refclk); ++ ++ switch (rate) { ++ case REF_CLOCK_24MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); ++ if (priv->type == PHY_TYPE_USB3) { ++ /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */ ++ val = FIELD_PREP(RK3528_PHYREG40_SSC_CNT, RK3528_PHYREG40_SSC_CNT_VALUE); ++ rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_CNT, val, ++ RK3528_PHYREG40); ++ } else if (priv->type == PHY_TYPE_PCIE) { ++ /* tx_trim[14]=1, Enable the counting clock of the rterm detect */ ++ rockchip_combphy_updatel(priv, RK3528_PHYREG86_RTERM_DET_CLK_EN, ++ RK3528_PHYREG86_RTERM_DET_CLK_EN, RK3528_PHYREG86); ++ } ++ break; ++ case REF_CLOCK_100MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); ++ if (priv->type == PHY_TYPE_PCIE) { ++ /* PLL KVCO tuning fine */ ++ val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE); ++ rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val, ++ RK3528_PHYREG6); ++ ++ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */ ++ writel(0x570804f0, priv->mmio + RK3528_PHYREG42); ++ } ++ break; ++ default: ++ dev_err(priv->dev, "Unsupported rate: %lu\n", rate); ++ return -EINVAL; ++ } ++ ++ if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); ++ ++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { ++ val = FIELD_PREP(RK3528_PHYREG42_CKDRV_CLK_SEL, ++ RK3528_PHYREG42_CKDRV_CLK_CKRCV); ++ val |= FIELD_PREP(RK3528_PHYREG42_PLL_LPF_R1_ADJ, ++ RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE); ++ val |= FIELD_PREP(RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ, ++ RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE); ++ val |= FIELD_PREP(RK3528_PHYREG42_PLL_KVCO_ADJ, ++ RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE); ++ rockchip_combphy_updatel(priv, ++ RK3528_PHYREG42_CKDRV_CLK_SEL | ++ RK3528_PHYREG42_PLL_LPF_R1_ADJ | ++ RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ | ++ RK3528_PHYREG42_PLL_KVCO_ADJ, ++ val, RK3528_PHYREG42); ++ ++ val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE); ++ rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val, ++ RK3528_PHYREG6); ++ } ++ } ++ ++ if (priv->type == PHY_TYPE_PCIE) { ++ if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) ++ rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN, ++ RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40); ++ } ++ ++ return 0; ++} ++ ++static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { ++ /* pipe-phy-grf */ ++ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, ++ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, ++ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, ++ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, ++ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, ++ .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, ++ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, ++ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, ++ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, ++ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, ++ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, ++ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, ++ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 }, ++ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 }, ++ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 }, ++ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, ++ /* pipe-grf */ ++ .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 }, ++}; ++ ++static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { ++ .num_phys = 1, ++ .phy_ids = { ++ 0xffdc0000, ++ }, ++ .grfcfg = &rk3528_combphy_grfcfgs, ++ .combphy_cfg = rk3528_combphy_cfg, ++}; ++ + static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) + { + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; +@@ -1075,6 +1258,10 @@ static const struct rockchip_combphy_cfg + + static const struct of_device_id rockchip_combphy_of_match[] = { + { ++ .compatible = "rockchip,rk3528-naneng-combphy", ++ .data = &rk3528_combphy_cfgs, ++ }, ++ { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = &rk3568_combphy_cfgs, + }, diff --git a/target/linux/rockchip/patches-6.12/038-v6.15-iio-adc-rockchip_saradc-Add-support-for-RK3528.patch b/target/linux/rockchip/patches-6.12/038-v6.15-iio-adc-rockchip_saradc-Add-support-for-RK3528.patch new file mode 100644 index 0000000000..0273ea2616 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/038-v6.15-iio-adc-rockchip_saradc-Add-support-for-RK3528.patch @@ -0,0 +1,57 @@ +From 8a9aa0bbd615c9b377bd82e671519f0c4cb272dd Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Thu, 27 Feb 2025 18:40:51 +0000 +Subject: [PATCH] iio: adc: rockchip_saradc: Add support for RK3528 + +The Successive Approximation ADC (SARADC) in RK3528 uses the v2 +controller and support: +- 10-bit resolution +- Up to 1MS/s sampling rate +- 4 single-ended input channels +- Current consumption: 0.5mA @ 1MS/s + +Add support for the 4 channels of 10-bit resolution supported by SARADC +in RK3528. + +Signed-off-by: Jonas Karlman +Reviewed-by: Heiko Stuebner +Link: https://patch.msgid.link/20250227184058.2964204-3-jonas@kwiboo.se +Signed-off-by: Jonathan Cameron +--- + drivers/iio/adc/rockchip_saradc.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/drivers/iio/adc/rockchip_saradc.c ++++ b/drivers/iio/adc/rockchip_saradc.c +@@ -275,6 +275,21 @@ static const struct rockchip_saradc_data + .power_down = rockchip_saradc_power_down_v1, + }; + ++static const struct iio_chan_spec rockchip_rk3528_saradc_iio_channels[] = { ++ SARADC_CHANNEL(0, "adc0", 10), ++ SARADC_CHANNEL(1, "adc1", 10), ++ SARADC_CHANNEL(2, "adc2", 10), ++ SARADC_CHANNEL(3, "adc3", 10), ++}; ++ ++static const struct rockchip_saradc_data rk3528_saradc_data = { ++ .channels = rockchip_rk3528_saradc_iio_channels, ++ .num_channels = ARRAY_SIZE(rockchip_rk3528_saradc_iio_channels), ++ .clk_rate = 1000000, ++ .start = rockchip_saradc_start_v2, ++ .read = rockchip_saradc_read_v2, ++}; ++ + static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = { + SARADC_CHANNEL(0, "adc0", 10), + SARADC_CHANNEL(1, "adc1", 10), +@@ -325,6 +340,9 @@ static const struct of_device_id rockchi + .compatible = "rockchip,rk3399-saradc", + .data = &rk3399_saradc_data, + }, { ++ .compatible = "rockchip,rk3528-saradc", ++ .data = &rk3528_saradc_data, ++ }, { + .compatible = "rockchip,rk3568-saradc", + .data = &rk3568_saradc_data, + }, { diff --git a/target/linux/rockchip/patches-6.12/039-01-v6.15-net-stmmac-dwmac-rk-Add-GMAC-support-for-RK3528.patch b/target/linux/rockchip/patches-6.12/039-01-v6.15-net-stmmac-dwmac-rk-Add-GMAC-support-for-RK3528.patch new file mode 100644 index 0000000000..cc810b38b0 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/039-01-v6.15-net-stmmac-dwmac-rk-Add-GMAC-support-for-RK3528.patch @@ -0,0 +1,166 @@ +From 1725f0eb37d621ce48303ccc14748fb66d618c9e Mon Sep 17 00:00:00 2001 +From: David Wu +Date: Wed, 19 Mar 2025 21:44:06 +0000 +Subject: [PATCH] net: stmmac: dwmac-rk: Add GMAC support for RK3528 + +Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC +Ethernet QoS IP. + +Add initial support for the RK3528 GMAC variant. + +Signed-off-by: David Wu +Signed-off-by: Jonas Karlman +Link: https://patch.msgid.link/20250319214415.3086027-3-jonas@kwiboo.se +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 132 ++++++++++++++++++ + 1 file changed, 132 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -1014,6 +1014,137 @@ static const struct rk_gmac_ops rk3399_o + .set_rmii_speed = rk3399_set_rmii_speed, + }; + ++#define RK3528_VO_GRF_GMAC_CON 0x0018 ++#define RK3528_VO_GRF_MACPHY_CON0 0x001c ++#define RK3528_VO_GRF_MACPHY_CON1 0x0020 ++#define RK3528_VPU_GRF_GMAC_CON5 0x0018 ++#define RK3528_VPU_GRF_GMAC_CON6 0x001c ++ ++#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) ++#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) ++#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) ++#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) ++ ++#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) ++#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) ++ ++#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) ++#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) ++#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) ++ ++#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) ++#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) ++ ++#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) ++#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) ++#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) ++#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) ++ ++#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) ++#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) ++#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) ++ ++#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) ++#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) ++#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) ++#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) ++ ++static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, ++ int tx_delay, int rx_delay) ++{ ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, ++ RK3528_GMAC1_PHY_INTF_SEL_RGMII); ++ ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, ++ DELAY_ENABLE(RK3528, tx_delay, rx_delay)); ++ ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, ++ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | ++ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); ++} ++ ++static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) ++{ ++ if (bsp_priv->id == 1) ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, ++ RK3528_GMAC1_PHY_INTF_SEL_RMII); ++ else ++ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, ++ RK3528_GMAC0_PHY_INTF_SEL_RMII | ++ RK3528_GMAC0_CLK_RMII_DIV2); ++} ++ ++static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ ++ if (speed == 10) ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, ++ RK3528_GMAC1_CLK_RGMII_DIV50); ++ else if (speed == 100) ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, ++ RK3528_GMAC1_CLK_RGMII_DIV5); ++ else if (speed == 1000) ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, ++ RK3528_GMAC1_CLK_RGMII_DIV1); ++ else ++ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); ++} ++ ++static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ unsigned int reg, val; ++ ++ if (speed == 10) ++ val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 : ++ RK3528_GMAC0_CLK_RMII_DIV20; ++ else if (speed == 100) ++ val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 : ++ RK3528_GMAC0_CLK_RMII_DIV2; ++ else { ++ dev_err(dev, "unknown speed value for RMII! speed=%d", speed); ++ return; ++ } ++ ++ reg = bsp_priv->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 : ++ RK3528_VO_GRF_GMAC_CON; ++ ++ regmap_write(bsp_priv->grf, reg, val); ++} ++ ++static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, ++ bool input, bool enable) ++{ ++ unsigned int val; ++ ++ if (bsp_priv->id == 1) { ++ val = input ? RK3528_GMAC1_CLK_SELECT_IO : ++ RK3528_GMAC1_CLK_SELECT_CRU; ++ val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : ++ RK3528_GMAC1_CLK_RMII_GATE; ++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); ++ } else { ++ val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : ++ RK3528_GMAC0_CLK_RMII_GATE; ++ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); ++ } ++} ++ ++static const struct rk_gmac_ops rk3528_ops = { ++ .set_to_rgmii = rk3528_set_to_rgmii, ++ .set_to_rmii = rk3528_set_to_rmii, ++ .set_rgmii_speed = rk3528_set_rgmii_speed, ++ .set_rmii_speed = rk3528_set_rmii_speed, ++ .set_clock_selection = rk3528_set_clock_selection, ++ .regs_valid = true, ++ .regs = { ++ 0xffbd0000, /* gmac0 */ ++ 0xffbe0000, /* gmac1 */ ++ 0x0, /* sentinel */ ++ }, ++}; ++ + #define RK3568_GRF_GMAC0_CON0 0x0380 + #define RK3568_GRF_GMAC0_CON1 0x0384 + #define RK3568_GRF_GMAC1_CON0 0x0388 +@@ -2080,6 +2211,7 @@ static const struct of_device_id rk_gmac + { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, + { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, + { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, ++ { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, + { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, + { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, + { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, diff --git a/target/linux/rockchip/patches-6.12/039-02-v6.15-net-stmmac-dwmac-rk-Move-integrated_phy_powerup-down.patch b/target/linux/rockchip/patches-6.12/039-02-v6.15-net-stmmac-dwmac-rk-Move-integrated_phy_powerup-down.patch new file mode 100644 index 0000000000..ad7182ffb7 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/039-02-v6.15-net-stmmac-dwmac-rk-Move-integrated_phy_powerup-down.patch @@ -0,0 +1,126 @@ +From 0bed91f2b183bc38c216299ce035b44210148785 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Wed, 19 Mar 2025 21:44:07 +0000 +Subject: [PATCH] net: stmmac: dwmac-rk: Move integrated_phy_powerup/down + functions + +Rockchip RK3528 (and RV1106) has a different integrated PHY compared to +the integrated PHY on RK3228/RK3328. Current powerup/down operation is +not compatible with the integrated PHY found in these SoCs. + +Move the rk_gmac_integrated_phy_powerup/down functions to top of the +file to prepare for them to be called directly by a GMAC variant +specific powerup/down operation. + +Signed-off-by: Jonas Karlman +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20250319214415.3086027-4-jonas@kwiboo.se +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 88 +++++++++---------- + 1 file changed, 44 insertions(+), 44 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -92,6 +92,50 @@ struct rk_priv_data { + (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ + ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) + ++#define RK_GRF_MACPHY_CON0 0xb00 ++#define RK_GRF_MACPHY_CON1 0xb04 ++#define RK_GRF_MACPHY_CON2 0xb08 ++#define RK_GRF_MACPHY_CON3 0xb0c ++ ++#define RK_MACPHY_ENABLE GRF_BIT(0) ++#define RK_MACPHY_DISABLE GRF_CLR_BIT(0) ++#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) ++#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) ++#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) ++#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) ++ ++static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) ++{ ++ if (priv->ops->integrated_phy_powerup) ++ priv->ops->integrated_phy_powerup(priv); ++ ++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); ++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); ++ ++ regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); ++ regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); ++ ++ if (priv->phy_reset) { ++ /* PHY needs to be disabled before trying to reset it */ ++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); ++ if (priv->phy_reset) ++ reset_control_assert(priv->phy_reset); ++ usleep_range(10, 20); ++ if (priv->phy_reset) ++ reset_control_deassert(priv->phy_reset); ++ usleep_range(10, 20); ++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); ++ msleep(30); ++ } ++} ++ ++static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) ++{ ++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); ++ if (priv->phy_reset) ++ reset_control_assert(priv->phy_reset); ++} ++ + #define PX30_GRF_GMAC_CON1 0x0904 + + /* PX30_GRF_GMAC_CON1 */ +@@ -1730,50 +1774,6 @@ static const struct rk_gmac_ops rv1126_o + .set_rmii_speed = rv1126_set_rmii_speed, + }; + +-#define RK_GRF_MACPHY_CON0 0xb00 +-#define RK_GRF_MACPHY_CON1 0xb04 +-#define RK_GRF_MACPHY_CON2 0xb08 +-#define RK_GRF_MACPHY_CON3 0xb0c +- +-#define RK_MACPHY_ENABLE GRF_BIT(0) +-#define RK_MACPHY_DISABLE GRF_CLR_BIT(0) +-#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) +-#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) +-#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) +-#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) +- +-static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) +-{ +- if (priv->ops->integrated_phy_powerup) +- priv->ops->integrated_phy_powerup(priv); +- +- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); +- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); +- +- regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); +- regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); +- +- if (priv->phy_reset) { +- /* PHY needs to be disabled before trying to reset it */ +- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); +- if (priv->phy_reset) +- reset_control_assert(priv->phy_reset); +- usleep_range(10, 20); +- if (priv->phy_reset) +- reset_control_deassert(priv->phy_reset); +- usleep_range(10, 20); +- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); +- msleep(30); +- } +-} +- +-static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) +-{ +- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); +- if (priv->phy_reset) +- reset_control_assert(priv->phy_reset); +-} +- + static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) + { + struct rk_priv_data *bsp_priv = plat->bsp_priv; diff --git a/target/linux/rockchip/patches-6.12/039-03-v6.15-net-stmmac-dwmac-rk-Add-integrated_phy_powerdown-operatio.patch b/target/linux/rockchip/patches-6.12/039-03-v6.15-net-stmmac-dwmac-rk-Add-integrated_phy_powerdown-operatio.patch new file mode 100644 index 0000000000..ea45fb6625 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/039-03-v6.15-net-stmmac-dwmac-rk-Add-integrated_phy_powerdown-operatio.patch @@ -0,0 +1,112 @@ +From 32c7bc0747bbd8ee4ee32026d36a24be56117d96 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Wed, 19 Mar 2025 21:44:08 +0000 +Subject: [PATCH] net: stmmac: dwmac-rk: Add integrated_phy_powerdown operation + +Rockchip RK3528 (and RV1106) has a different integrated PHY compared to +the integrated PHY on RK3228/RK3328. Current powerup/down operation is +not compatible with the integrated PHY found in these newer SoCs. + +Add a new integrated_phy_powerdown operation and change the call chain +for integrated_phy_powerup to prepare support for the integrated PHY +found in these newer SoCs. + +Signed-off-by: Jonas Karlman +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20250319214415.3086027-5-jonas@kwiboo.se +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 26 +++++++++++-------- + 1 file changed, 15 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -33,6 +33,7 @@ struct rk_gmac_ops { + void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, + bool enable); + void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); ++ void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); + bool php_grf_required; + bool regs_valid; + u32 regs[]; +@@ -104,11 +105,8 @@ struct rk_priv_data { + #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) + #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) + +-static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) ++static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv) + { +- if (priv->ops->integrated_phy_powerup) +- priv->ops->integrated_phy_powerup(priv); +- + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); + +@@ -129,7 +127,7 @@ static void rk_gmac_integrated_phy_power + } + } + +-static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) ++static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv) + { + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); + if (priv->phy_reset) +@@ -423,6 +421,8 @@ static void rk3228_integrated_phy_poweru + { + regmap_write(priv->grf, RK3228_GRF_CON_MUX, + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); ++ ++ rk_gmac_integrated_ephy_powerup(priv); + } + + static const struct rk_gmac_ops rk3228_ops = { +@@ -430,7 +430,8 @@ static const struct rk_gmac_ops rk3228_o + .set_to_rmii = rk3228_set_to_rmii, + .set_rgmii_speed = rk3228_set_rgmii_speed, + .set_rmii_speed = rk3228_set_rmii_speed, +- .integrated_phy_powerup = rk3228_integrated_phy_powerup, ++ .integrated_phy_powerup = rk3228_integrated_phy_powerup, ++ .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, + }; + + #define RK3288_GRF_SOC_CON1 0x0248 +@@ -715,6 +716,8 @@ static void rk3328_integrated_phy_poweru + { + regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, + RK3328_MACPHY_RMII_MODE); ++ ++ rk_gmac_integrated_ephy_powerup(priv); + } + + static const struct rk_gmac_ops rk3328_ops = { +@@ -722,7 +725,8 @@ static const struct rk_gmac_ops rk3328_o + .set_to_rmii = rk3328_set_to_rmii, + .set_rgmii_speed = rk3328_set_rgmii_speed, + .set_rmii_speed = rk3328_set_rmii_speed, +- .integrated_phy_powerup = rk3328_integrated_phy_powerup, ++ .integrated_phy_powerup = rk3328_integrated_phy_powerup, ++ .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, + }; + + #define RK3366_GRF_SOC_CON6 0x0418 +@@ -2070,16 +2074,16 @@ static int rk_gmac_powerup(struct rk_pri + + pm_runtime_get_sync(dev); + +- if (bsp_priv->integrated_phy) +- rk_gmac_integrated_phy_powerup(bsp_priv); ++ if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup) ++ bsp_priv->ops->integrated_phy_powerup(bsp_priv); + + return 0; + } + + static void rk_gmac_powerdown(struct rk_priv_data *gmac) + { +- if (gmac->integrated_phy) +- rk_gmac_integrated_phy_powerdown(gmac); ++ if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown) ++ gmac->ops->integrated_phy_powerdown(gmac); + + pm_runtime_put_sync(&gmac->pdev->dev); + diff --git a/target/linux/rockchip/patches-6.12/039-04-v6.15-net-stmmac-dwmac-rk-Add-initial-support-for-RK3528.patch b/target/linux/rockchip/patches-6.12/039-04-v6.15-net-stmmac-dwmac-rk-Add-initial-support-for-RK3528.patch new file mode 100644 index 0000000000..d5208ec01d --- /dev/null +++ b/target/linux/rockchip/patches-6.12/039-04-v6.15-net-stmmac-dwmac-rk-Add-initial-support-for-RK3528.patch @@ -0,0 +1,84 @@ +From 83e7b35c7879497b51fd3fcd3a17b0b07f89e81b Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Wed, 19 Mar 2025 21:44:09 +0000 +Subject: [PATCH] net: stmmac: dwmac-rk: Add initial support for RK3528 + integrated PHY + +Rockchip RK3528 (and RV1106) has a different integrated PHY compared to +the integrated PHY on RK3228/RK3328. Current powerup/down operation is +not compatible with the integrated PHY found in these newer SoCs. + +Add operations to powerup/down the integrated PHY found in RK3528. +Use helpers that can be used by other GMAC variants in the future. + +Signed-off-by: Jonas Karlman +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20250319214415.3086027-6-jonas@kwiboo.se +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 41 +++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -134,6 +134,35 @@ static void rk_gmac_integrated_ephy_powe + reset_control_assert(priv->phy_reset); + } + ++#define RK_FEPHY_SHUTDOWN GRF_BIT(1) ++#define RK_FEPHY_POWERUP GRF_CLR_BIT(1) ++#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) ++#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) ++#define RK_FEPHY_PHY_ID GRF_BIT(11) ++ ++static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv, ++ unsigned int reg) ++{ ++ reset_control_assert(priv->phy_reset); ++ usleep_range(20, 30); ++ ++ regmap_write(priv->grf, reg, ++ RK_FEPHY_POWERUP | ++ RK_FEPHY_INTERNAL_RMII_SEL | ++ RK_FEPHY_24M_CLK_SEL | ++ RK_FEPHY_PHY_ID); ++ usleep_range(10000, 12000); ++ ++ reset_control_deassert(priv->phy_reset); ++ usleep_range(50000, 60000); ++} ++ ++static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, ++ unsigned int reg) ++{ ++ regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); ++} ++ + #define PX30_GRF_GMAC_CON1 0x0904 + + /* PX30_GRF_GMAC_CON1 */ +@@ -1179,12 +1208,24 @@ static void rk3528_set_clock_selection(s + } + } + ++static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv) ++{ ++ rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); ++} ++ ++static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv) ++{ ++ rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); ++} ++ + static const struct rk_gmac_ops rk3528_ops = { + .set_to_rgmii = rk3528_set_to_rgmii, + .set_to_rmii = rk3528_set_to_rmii, + .set_rgmii_speed = rk3528_set_rgmii_speed, + .set_rmii_speed = rk3528_set_rmii_speed, + .set_clock_selection = rk3528_set_clock_selection, ++ .integrated_phy_powerup = rk3528_integrated_phy_powerup, ++ .integrated_phy_powerdown = rk3528_integrated_phy_powerdown, + .regs_valid = true, + .regs = { + 0xffbd0000, /* gmac0 */ diff --git a/target/linux/rockchip/patches-6.12/039-05-v6.15-net-stmmac-dwmac-rk-Remove-unneeded-GRF-and-peripheral-GR.patch b/target/linux/rockchip/patches-6.12/039-05-v6.15-net-stmmac-dwmac-rk-Remove-unneeded-GRF-and-peripheral-GR.patch new file mode 100644 index 0000000000..c778d9ea40 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/039-05-v6.15-net-stmmac-dwmac-rk-Remove-unneeded-GRF-and-peripheral-GR.patch @@ -0,0 +1,572 @@ +From 41f35564cb71e7043e0afcf30078b4a6145cab64 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 8 Mar 2025 21:37:15 +0000 +Subject: [PATCH] net: stmmac: dwmac-rk: Remove unneeded GRF and peripheral GRF + checks + +Now that GRF, and peripheral GRF where needed, is validated at probe +time there is no longer any need to check and log an error in each SoC +specific operation. + +Remove unneeded IS_ERR() checks and early bail out from each SoC +specific operation. + +Signed-off-by: Jonas Karlman +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/20250308213720.2517944-4-jonas@kwiboo.se +Reviewed-by: Sebastian Reichel +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 249 ------------------ + 1 file changed, 249 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -173,13 +173,6 @@ static void rk_gmac_integrated_fephy_pow + + static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, + PX30_GMAC_PHY_INTF_SEL_RMII); + } +@@ -253,13 +246,6 @@ static const struct rk_gmac_ops px30_ops + static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, + RK3128_GMAC_PHY_INTF_SEL_RGMII | + RK3128_GMAC_RMII_MODE_CLR); +@@ -271,13 +257,6 @@ static void rk3128_set_to_rgmii(struct r + + static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, + RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); + } +@@ -286,11 +265,6 @@ static void rk3128_set_rgmii_speed(struc + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + if (speed == 10) + regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, + RK3128_GMAC_CLK_2_5M); +@@ -308,11 +282,6 @@ static void rk3128_set_rmii_speed(struct + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + if (speed == 10) { + regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, + RK3128_GMAC_RMII_CLK_2_5M | +@@ -369,13 +338,6 @@ static const struct rk_gmac_ops rk3128_o + static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, + RK3228_GMAC_PHY_INTF_SEL_RGMII | + RK3228_GMAC_RMII_MODE_CLR | +@@ -388,13 +350,6 @@ static void rk3228_set_to_rgmii(struct r + + static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, + RK3228_GMAC_PHY_INTF_SEL_RMII | + RK3228_GMAC_RMII_MODE); +@@ -407,11 +362,6 @@ static void rk3228_set_rgmii_speed(struc + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + if (speed == 10) + regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, + RK3228_GMAC_CLK_2_5M); +@@ -429,11 +379,6 @@ static void rk3228_set_rmii_speed(struct + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + if (speed == 10) + regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, + RK3228_GMAC_RMII_CLK_2_5M | +@@ -494,13 +439,6 @@ static const struct rk_gmac_ops rk3228_o + static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, + RK3288_GMAC_PHY_INTF_SEL_RGMII | + RK3288_GMAC_RMII_MODE_CLR); +@@ -512,13 +450,6 @@ static void rk3288_set_to_rgmii(struct r + + static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, + RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); + } +@@ -527,11 +458,6 @@ static void rk3288_set_rgmii_speed(struc + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + if (speed == 10) + regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, + RK3288_GMAC_CLK_2_5M); +@@ -549,11 +475,6 @@ static void rk3288_set_rmii_speed(struct + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + if (speed == 10) { + regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, + RK3288_GMAC_RMII_CLK_2_5M | +@@ -586,13 +507,6 @@ static const struct rk_gmac_ops rk3288_o + + static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, + RK3308_GMAC_PHY_INTF_SEL_RMII); + } +@@ -601,11 +515,6 @@ static void rk3308_set_rmii_speed(struct + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + if (speed == 10) { + regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, + RK3308_GMAC_SPEED_10M); +@@ -658,13 +567,6 @@ static const struct rk_gmac_ops rk3308_o + static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, + RK3328_GMAC_PHY_INTF_SEL_RGMII | + RK3328_GMAC_RMII_MODE_CLR | +@@ -678,14 +580,8 @@ static void rk3328_set_to_rgmii(struct r + + static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; + unsigned int reg; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : + RK3328_GRF_MAC_CON1; + +@@ -698,11 +594,6 @@ static void rk3328_set_rgmii_speed(struc + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + if (speed == 10) + regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, + RK3328_GMAC_CLK_2_5M); +@@ -721,11 +612,6 @@ static void rk3328_set_rmii_speed(struct + struct device *dev = &bsp_priv->pdev->dev; + unsigned int reg; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : + RK3328_GRF_MAC_CON1; + +@@ -789,13 +675,6 @@ static const struct rk_gmac_ops rk3328_o + static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, + RK3366_GMAC_PHY_INTF_SEL_RGMII | + RK3366_GMAC_RMII_MODE_CLR); +@@ -807,13 +686,6 @@ static void rk3366_set_to_rgmii(struct r + + static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, + RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); + } +@@ -822,11 +694,6 @@ static void rk3366_set_rgmii_speed(struc + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + if (speed == 10) + regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, + RK3366_GMAC_CLK_2_5M); +@@ -844,11 +711,6 @@ static void rk3366_set_rmii_speed(struct + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + if (speed == 10) { + regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, + RK3366_GMAC_RMII_CLK_2_5M | +@@ -900,13 +762,6 @@ static const struct rk_gmac_ops rk3366_o + static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_PHY_INTF_SEL_RGMII | + RK3368_GMAC_RMII_MODE_CLR); +@@ -918,13 +773,6 @@ static void rk3368_set_to_rgmii(struct r + + static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); + } +@@ -933,11 +781,6 @@ static void rk3368_set_rgmii_speed(struc + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + if (speed == 10) + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_CLK_2_5M); +@@ -955,11 +798,6 @@ static void rk3368_set_rmii_speed(struct + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + if (speed == 10) { + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_RMII_CLK_2_5M | +@@ -1011,13 +849,6 @@ static const struct rk_gmac_ops rk3368_o + static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, + RK3399_GMAC_PHY_INTF_SEL_RGMII | + RK3399_GMAC_RMII_MODE_CLR); +@@ -1029,13 +860,6 @@ static void rk3399_set_to_rgmii(struct r + + static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, + RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); + } +@@ -1044,11 +868,6 @@ static void rk3399_set_rgmii_speed(struc + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + if (speed == 10) + regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, + RK3399_GMAC_CLK_2_5M); +@@ -1066,11 +885,6 @@ static void rk3399_set_rmii_speed(struct + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + if (speed == 10) { + regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, + RK3399_GMAC_RMII_CLK_2_5M | +@@ -1258,14 +1072,8 @@ static const struct rk_gmac_ops rk3528_o + static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; + u32 con0, con1; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : + RK3568_GRF_GMAC0_CON0; + con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : +@@ -1283,14 +1091,8 @@ static void rk3568_set_to_rgmii(struct r + + static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; + u32 con1; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : + RK3568_GRF_GMAC0_CON1; + regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); +@@ -1377,14 +1179,8 @@ static const struct rk_gmac_ops rk3568_o + static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; + unsigned int offset_con; + +- if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { +- dev_err(dev, "Missing rockchip,grf or rockchip,php-grf property\n"); +- return; +- } +- + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : + RK3576_GRF_GMAC_CON0; + +@@ -1410,14 +1206,8 @@ static void rk3576_set_to_rgmii(struct r + + static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; + unsigned int offset_con; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : + RK3576_GRF_GMAC_CON0; + +@@ -1537,14 +1327,8 @@ static const struct rk_gmac_ops rk3576_o + static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; + u32 offset_con, id = bsp_priv->id; + +- if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { +- dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n"); +- return; +- } +- + offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : + RK3588_GRF_GMAC_CON8; + +@@ -1565,13 +1349,6 @@ static void rk3588_set_to_rgmii(struct r + + static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->php_grf)) { +- dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, + RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); + +@@ -1655,13 +1432,6 @@ static const struct rk_gmac_ops rk3588_o + + static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, + RV1108_GMAC_PHY_INTF_SEL_RMII); + } +@@ -1670,11 +1440,6 @@ static void rv1108_set_rmii_speed(struct + { + struct device *dev = &bsp_priv->pdev->dev; + +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + if (speed == 10) { + regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, + RV1108_GMAC_RMII_CLK_2_5M | +@@ -1723,13 +1488,6 @@ static const struct rk_gmac_ops rv1108_o + static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "Missing rockchip,grf property\n"); +- return; +- } +- + regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, + RV1126_GMAC_PHY_INTF_SEL_RGMII | + RV1126_GMAC_M0_RXCLK_DLY_ENABLE | +@@ -1748,13 +1506,6 @@ static void rv1126_set_to_rgmii(struct r + + static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) + { +- struct device *dev = &bsp_priv->pdev->dev; +- +- if (IS_ERR(bsp_priv->grf)) { +- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); +- return; +- } +- + regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, + RV1126_GMAC_PHY_INTF_SEL_RMII); + }