From: Zoltan HERPAI Date: Fri, 21 May 2021 21:58:20 +0000 (+0200) Subject: ixp4xx: bring back as a modernized target X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=afb526d4e195ad22ee17a2df82177608230f506b;p=openwrt%2Fstaging%2Fwigyori.git ixp4xx: bring back as a modernized target Work is in progress to modernize support for the SoC family, moving board config to DTS and upgrading all required drivers. As a first step, re-add a basic target with updated image creation, the updated ethernet, PCI and flash driver, and cherry-pick some of the older patches. Further legacy patches will be brought in as required, and board support DTSes will be added as they come online. Signed-off-by: Zoltan HERPAI --- diff --git a/target/linux/ixp4xx/Makefile b/target/linux/ixp4xx/Makefile new file mode 100644 index 0000000000..7b5dc65268 --- /dev/null +++ b/target/linux/ixp4xx/Makefile @@ -0,0 +1,22 @@ +# +# Copyright (C) 2021 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=armeb +#ARCH:=arm +BOARD:=ixp4xx +BOARDNAME:=Intel IXP4xx +FEATURES:=squashfs +CPU_TYPE:=xscale + +KERNEL_PATCHVER:=5.10 + +include $(INCLUDE_DIR)/target.mk + +KERNELNAME:=zImage dtbs + +$(eval $(call BuildTarget)) diff --git a/target/linux/ixp4xx/base-files/etc/board.d/02_network b/target/linux/ixp4xx/base-files/etc/board.d/02_network new file mode 100755 index 0000000000..76d7665ae2 --- /dev/null +++ b/target/linux/ixp4xx/base-files/etc/board.d/02_network @@ -0,0 +1,24 @@ +#!/bin/sh +# +# Copyright (C) 2013-2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh + +board_config_update + +case $(board_name) in +adi,pronghornmetro|\ +gateway,7001|\ +gateworks,gw2358|\ +titanwireless,tw266) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; +*) + ucidef_set_interface_lan "eth0" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/ixp4xx/base-files/lib/upgrade/platform.sh b/target/linux/ixp4xx/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000000..f83aa430cf --- /dev/null +++ b/target/linux/ixp4xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,137 @@ +CI_BLKSZ=65536 +CI_LDADR=0x00800000 + +platform_find_partitions() { + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + vmlinux.bin.l7|kernel|linux|rootfs) + if [ -z "$first" ]; then + first="$name" + else + echo "$erasesize:$first:$name" + break + fi + ;; + esac + done < /proc/mtd +} + +platform_find_kernelpart() { + local part + for part in "${1%:*}" "${1#*:}"; do + case "$part" in + vmlinux.bin.l7|kernel|linux) + echo "$part" + break + ;; + esac + done +} + +platform_find_part_size() { + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + [ "$name" = "$1" ] && { + echo "$size" + break + } + done < /proc/mtd +} + +platform_do_upgrade_combined() { + local partitions=$(platform_find_partitions) + local kernelpart=$(platform_find_kernelpart "${partitions#*:}") + local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}" + local kern_part_size=0x$(platform_find_part_size "$kernelpart") + local kern_part_blocks=$(($kern_part_size / $CI_BLKSZ)) + local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local kern_blocks=$(($kern_length / $CI_BLKSZ)) + local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ)) + + v "platform_do_upgrade_combined" + v "partitions=$partitions" + v "kernelpart=$kernelpart" + v "kernel_part_size=$kern_part_size" + v "kernel_part_blocks=$kern_part_blocks" + v "kern_length=$kern_length" + v "erase_size=$erase_size" + v "kern_blocks=$kern_blocks" + v "root_blocks=$root_blocks" + v "kern_pad_blocks=$(($kern_part_blocks-$kern_blocks))" + + if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \ + [ ${kern_blocks:-0} -gt 0 ] && \ + [ ${root_blocks:-0} -gt 0 ] && \ + [ ${erase_size:-0} -gt 0 ]; + then + local append="" + [ -f "$UPGRADE_BACKUP" ] && append="-j $UPGRADE_BACKUP" + + # write the kernel + dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null | \ + mtd -F$kernelpart:$kern_part_size:$CI_LDADR write - $kernelpart + # write the rootfs + dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null | \ + mtd $append write - rootfs + else + echo "invalid image" + fi +} + +platform_check_image() { + local board=$(board_name) + local magic="$(get_magic_word "$1")" + local partitions=$(platform_find_partitions) + local kernelpart=$(platform_find_kernelpart "${partitions#*:}") + local kern_part_size=0x$(platform_find_part_size "$kernelpart") + local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + + [ "$#" -gt 1 ] && return 1 + + case "$board" in + avila | cambria ) + [ "$magic" != "4349" ] && { + echo "Invalid image. Use *-sysupgrade.bin files on this board" + return 1 + } + + kern_length_b=$(printf '%d' $kern_length) + kern_part_size_b=$(printf '%d' $kern_part_size) + if [ $kern_length_b -gt $kern_part_size_b ]; then + echo "Invalid image. Kernel size ($kern_length) exceeds kernel partition ($kern_part_size)" + return 1 + fi + + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then + return 0 + else + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + + return 0 + ;; + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_do_upgrade() { + local board=$(board_name) + + v "board=$board" + case "$board" in + avila | cambria ) + platform_do_upgrade_combined "$1" + ;; + *) + default_do_upgrade "$1" + ;; + esac +} diff --git a/target/linux/ixp4xx/config-5.10 b/target/linux/ixp4xx/config-5.10 new file mode 100644 index 0000000000..ac21a5fac4 --- /dev/null +++ b/target/linux/ixp4xx/config-5.10 @@ -0,0 +1,243 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_IXP4XX=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_NO_SG_CHAIN=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +# CONFIG_ARCH_PRPMC1100 is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PTDUMP_CORE=y +CONFIG_ARM_PTDUMP_DEBUGFS=y +# CONFIG_ARM_THUMB is not set +CONFIG_ARM_UNWIND=y +CONFIG_ASN1=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_ATAGS=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BOUNCE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_COMMON_CLK is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_ENDIAN_BE32=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CPU_XSCALE=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_DEV_IXP4XX is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA256=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_LL_UART_8250=y +CONFIG_DEBUG_UART_8250=y +CONFIG_DEBUG_UART_8250_SHIFT=2 +CONFIG_DEBUG_UART_PHYS=0xc8001003 +CONFIG_DEBUG_UART_VIRT=0xfec01003 +CONFIG_DMABOUNCE=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_IXP4XX=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDENED_USERCOPY_FALLBACK=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_IXP4XX=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_IOP3XX=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IWMMXT is not set +CONFIG_IXP4XX_ETH=y +CONFIG_IXP4XX_IRQ=y +CONFIG_IXP4XX_NPE=y +# CONFIG_IXP4XX_PCI_LEGACY is not set +CONFIG_IXP4XX_QMGR=y +CONFIG_IXP4XX_TIMER=y +CONFIG_IXP4XX_WATCHDOG=y +CONFIG_KEYS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LLD_VERSION=0 +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_MACH_DEVIXP is not set +# CONFIG_MACH_GORAMO_MLR is not set +# CONFIG_MACH_IXDP465 is not set +CONFIG_MACH_IXP4XX_OF=y +# CONFIG_MACH_KIXRP435 is not set +# CONFIG_MACH_MIC256 is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MPILIB=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_IXP4XX=y +CONFIG_MTD_OTP=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_IXP4XX=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_VENDOR_XSCALE=y +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OID_REGISTRY=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_IXP4XX=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1672=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_X1205=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SRCU=y +CONFIG_SWPHY=y +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/ixp4xx/image/Makefile b/target/linux/ixp4xx/image/Makefile new file mode 100644 index 0000000000..c52689acb0 --- /dev/null +++ b/target/linux/ixp4xx/image/Makefile @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2021 OpenWrt.org +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +DEVICE_VARS := DEVICE_DTS + +define Build/arm-magic + $(TOPDIR)/scripts/arm-magic-v2.sh $@ $@.new $(1) + mv $@.new $@ +endef + +# Build sysupgrade image +define BuildFirmware/Generic + dd if=$(KDIR)/zImage of=$(KDIR)/zImage.pad bs=64k conv=sync; \ + dd if=$(KDIR)/root.$(1) of=$(KDIR)/root.$(1).pad bs=128k conv=sync; \ + sh $(TOPDIR)/scripts/combined-image.sh \ + $(KDIR)/zImage.pad \ + $(KDIR)/root.$(1).pad \ + $(BIN_DIR)/$(IMG_PREFIX)-$(patsubst jffs2-%,jffs2,$(patsubst squashfs-%,squashfs,$(1)))-sysupgrade.bin +endef + +define Image/Build + $(call Image/Build/$(1),$(1)) + $(call BuildFirmware/Generic,$(1)) +endef + + +define Device/Default + KERNEL_NAME := zImage + FILESYSTEMS := squashfs + PROFILES := Default + DEVICE_DTS = intel-$$(SOC)-$(lastword $(subst _,-,$(1))) + KERNEL := kernel-bin | append-dtb + IMAGES := kernel.bin rootfs.bin + BLOCKSIZE := 128k + IMAGE/kernel.bin := append-kernel + IMAGE/rootfs.bin := append-rootfs +endef + +define Device/adi_pronghorn-metro + DEVICE_VENDOR := ADI + DEVICE_MODEL := Pronghorn Metro +# KERNEL := kernel-bin | arm-magic 1040 | append-dtb +# KERNEL := kernel-bin | append-dtb + SOC := ixp42x +endef +TARGET_DEVICES += adi_pronghorn-metro + + +define Device/gateway_7001 + DEVICE_VENDOR := Gateway + DEVICE_MODEL := 7001 +# KERNEL := kernel-bin | append-dtb +# KERNEL := kernel-bin | arm-magic 731 | append-dtb + SOC := ixp42x +endef +TARGET_DEVICES += gateway_7001 + + +define Device/linksys_nslu2 + DEVICE_VENDOR := Linksys + DEVICE_MODEL := NSLU2 +# KERNEL := kernel-bin | arm-magic 597 | append-dtb + SOC := ixp42x +endef +TARGET_DEVICES += linksys_nslu2 + + +define Device/titanwireless_tw2662 + DEVICE_VENDOR := Titan Wireless + DEVICE_MODEL := TW 266-2 +# KERNEL := kernel-bin | append-dtb + SOC := ixp42x +endef +TARGET_DEVICES += titanwireless_tw2662 + +$(eval $(call BuildImage)) diff --git a/target/linux/ixp4xx/patches-5.10/100-net-ixp4xx_eth-Use-DEFINE_SPINLOCK_for_spinlock.patch b/target/linux/ixp4xx/patches-5.10/100-net-ixp4xx_eth-Use-DEFINE_SPINLOCK_for_spinlock.patch new file mode 100644 index 0000000000..158bfff0f9 --- /dev/null +++ b/target/linux/ixp4xx/patches-5.10/100-net-ixp4xx_eth-Use-DEFINE_SPINLOCK_for_spinlock.patch @@ -0,0 +1,40 @@ +From 1454c51d1ec1277a54505159c5de62be0c2a2597 Mon Sep 17 00:00:00 2001 +From: Zheng Yongjun +Date: Tue, 29 Dec 2020 21:49:47 +0800 +Subject: net: ixp4xx_eth: Use DEFINE_SPINLOCK() for spinlock + +spinlock can be initialized automatically with DEFINE_SPINLOCK() +rather than explicitly calling spin_lock_init(). + +Signed-off-by: Zheng Yongjun +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/xscale/ixp4xx_eth.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +(limited to 'drivers/net/ethernet/xscale/ixp4xx_eth.c') + +diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c +index 2e52029235104..0152f1e707834 100644 +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -247,7 +247,7 @@ static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) + } + #endif + +-static spinlock_t mdio_lock; ++static DEFINE_SPINLOCK(mdio_lock); + static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ + static struct mii_bus *mdio_bus; + static int ports_open; +@@ -528,7 +528,6 @@ static int ixp4xx_mdio_register(struct eth_regs __iomem *regs) + + mdio_regs = regs; + __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); +- spin_lock_init(&mdio_lock); + mdio_bus->name = "IXP4xx MII Bus"; + mdio_bus->read = &ixp4xx_mdio_read; + mdio_bus->write = &ixp4xx_mdio_write; +-- +cgit 1.2.3-1.el7 + diff --git a/target/linux/ixp4xx/patches-5.10/110-net-ethernet-ixp4xx-Retire-ancient-phy-retrieval.patch b/target/linux/ixp4xx/patches-5.10/110-net-ethernet-ixp4xx-Retire-ancient-phy-retrieval.patch new file mode 100644 index 0000000000..ff6659e80b --- /dev/null +++ b/target/linux/ixp4xx/patches-5.10/110-net-ethernet-ixp4xx-Retire-ancient-phy-retrieval.patch @@ -0,0 +1,52 @@ +From 3e8047a98553e234a751f4f7f42d687ba98c0822 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Sun, 25 Apr 2021 02:30:37 +0200 +Subject: net: ethernet: ixp4xx: Retire ancient phy retrieveal + +This driver was using a really dated way of obtaining the +phy by printing a string and using it with phy_connect(). +Switch to using more reasonable modern interfaces. + +Suggested-by: Andrew Lunn +Reviewed-by: Andrew Lunn +Signed-off-by: Linus Walleij +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/xscale/ixp4xx_eth.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c +index 0152f1e707834..9d323e8595e2b 100644 +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -1360,7 +1360,6 @@ static const struct net_device_ops ixp4xx_netdev_ops = { + + static int ixp4xx_eth_probe(struct platform_device *pdev) + { +- char phy_id[MII_BUS_ID_SIZE + 3]; + struct phy_device *phydev = NULL; + struct device *dev = &pdev->dev; + struct eth_plat_info *plat; +@@ -1459,14 +1458,15 @@ static int ixp4xx_eth_probe(struct platform_device *pdev) + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); + udelay(50); + +- snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, +- mdio_bus->id, plat->phy); +- phydev = phy_connect(ndev, phy_id, &ixp4xx_adjust_link, +- PHY_INTERFACE_MODE_MII); ++ phydev = mdiobus_get_phy(mdio_bus, plat->phy); + if (IS_ERR(phydev)) { + err = PTR_ERR(phydev); + goto err_free_mem; + } ++ err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link, ++ PHY_INTERFACE_MODE_MII); ++ if (err) ++ goto err_free_mem; + + phydev->irq = PHY_POLL; + +-- +cgit 1.2.3-1.el7 + diff --git a/target/linux/ixp4xx/patches-5.10/111-net-ethernet-ixp4xx-Support-device-tree-probing.patch b/target/linux/ixp4xx/patches-5.10/111-net-ethernet-ixp4xx-Support-device-tree-probing.patch new file mode 100644 index 0000000000..ca9af84809 --- /dev/null +++ b/target/linux/ixp4xx/patches-5.10/111-net-ethernet-ixp4xx-Support-device-tree-probing.patch @@ -0,0 +1,365 @@ +From 95aafe911db602d19b00d2a88c3d54a84119f5dc Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Sun, 25 Apr 2021 02:30:38 +0200 +Subject: net: ethernet: ixp4xx: Support device tree probing + +This adds device tree probing to the IXP4xx ethernet +driver. + +Add a platform data bool to tell us whether to +register an MDIO bus for the device or not, as well +as the corresponding NPE. + +We need to drop the memory region request as part of +this since the OF core will request the memory for the +device. + +Cc: Zoltan HERPAI +Cc: Raylynn Knight +Signed-off-by: Linus Walleij +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/xscale/Kconfig | 1 + + drivers/net/ethernet/xscale/ixp4xx_eth.c | 210 +++++++++++++++++++++---------- + include/linux/platform_data/eth_ixp4xx.h | 2 + + 3 files changed, 150 insertions(+), 63 deletions(-) + +diff --git a/drivers/net/ethernet/xscale/Kconfig b/drivers/net/ethernet/xscale/Kconfig +index 7b83a6e5d894d..468ffe3d17075 100644 +--- a/drivers/net/ethernet/xscale/Kconfig ++++ b/drivers/net/ethernet/xscale/Kconfig +@@ -22,6 +22,7 @@ config IXP4XX_ETH + tristate "Intel IXP4xx Ethernet support" + depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR + select PHYLIB ++ select OF_MDIO if OF + select NET_PTP_CLASSIFY + help + Say Y here if you want to use built-in Ethernet ports +diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c +index 9d323e8595e2b..1149e88e64546 100644 +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -28,6 +28,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -165,7 +166,6 @@ struct eth_regs { + }; + + struct port { +- struct resource *mem_res; + struct eth_regs __iomem *regs; + struct npe *npe; + struct net_device *netdev; +@@ -250,6 +250,7 @@ static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) + static DEFINE_SPINLOCK(mdio_lock); + static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ + static struct mii_bus *mdio_bus; ++static struct device_node *mdio_bus_np; + static int ports_open; + static struct port *npe_port_tab[MAX_NPES]; + static struct dma_pool *dma_pool; +@@ -533,7 +534,8 @@ static int ixp4xx_mdio_register(struct eth_regs __iomem *regs) + mdio_bus->write = &ixp4xx_mdio_write; + snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0"); + +- if ((err = mdiobus_register(mdio_bus))) ++ err = of_mdiobus_register(mdio_bus, mdio_bus_np); ++ if (err) + mdiobus_free(mdio_bus); + return err; + } +@@ -1358,18 +1360,118 @@ static const struct net_device_ops ixp4xx_netdev_ops = { + .ndo_validate_addr = eth_validate_addr, + }; + ++#ifdef CONFIG_OF ++static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) ++{ ++ struct device_node *np = dev->of_node; ++ struct of_phandle_args queue_spec; ++ struct of_phandle_args npe_spec; ++ struct device_node *mdio_np; ++ struct eth_plat_info *plat; ++ int ret; ++ ++ plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL); ++ if (!plat) ++ return NULL; ++ ++ ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0, ++ &npe_spec); ++ if (ret) { ++ dev_err(dev, "no NPE engine specified\n"); ++ return NULL; ++ } ++ /* NPE ID 0x00, 0x10, 0x20... */ ++ plat->npe = (npe_spec.args[0] << 4); ++ ++ /* Check if this device has an MDIO bus */ ++ mdio_np = of_get_child_by_name(np, "mdio"); ++ if (mdio_np) { ++ plat->has_mdio = true; ++ mdio_bus_np = mdio_np; ++ /* DO NOT put the mdio_np, it will be used */ ++ } ++ ++ /* Get the rx queue as a resource from queue manager */ ++ ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0, ++ &queue_spec); ++ if (ret) { ++ dev_err(dev, "no rx queue phandle\n"); ++ return NULL; ++ } ++ plat->rxq = queue_spec.args[0]; ++ ++ /* Get the txready queue as resource from queue manager */ ++ ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0, ++ &queue_spec); ++ if (ret) { ++ dev_err(dev, "no txready queue phandle\n"); ++ return NULL; ++ } ++ plat->txreadyq = queue_spec.args[0]; ++ ++ return plat; ++} ++#else ++static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) ++{ ++ return NULL; ++} ++#endif ++ + static int ixp4xx_eth_probe(struct platform_device *pdev) + { + struct phy_device *phydev = NULL; + struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; + struct eth_plat_info *plat; +- resource_size_t regs_phys; + struct net_device *ndev; + struct resource *res; + struct port *port; + int err; + +- plat = dev_get_platdata(dev); ++ if (np) { ++ plat = ixp4xx_of_get_platdata(dev); ++ if (!plat) ++ return -ENODEV; ++ } else { ++ plat = dev_get_platdata(dev); ++ if (!plat) ++ return -ENODEV; ++ plat->npe = pdev->id; ++ switch (plat->npe) { ++ case IXP4XX_ETH_NPEA: ++ /* If the MDIO bus is not up yet, defer probe */ ++ break; ++ case IXP4XX_ETH_NPEB: ++ /* On all except IXP43x, NPE-B is used for the MDIO bus. ++ * If there is no NPE-B in the feature set, bail out, ++ * else we have the MDIO bus here. ++ */ ++ if (!cpu_is_ixp43x()) { ++ if (!(ixp4xx_read_feature_bits() & ++ IXP4XX_FEATURE_NPEB_ETH0)) ++ return -ENODEV; ++ /* Else register the MDIO bus on NPE-B */ ++ plat->has_mdio = true; ++ } ++ break; ++ case IXP4XX_ETH_NPEC: ++ /* IXP43x lacks NPE-B and uses NPE-C for the MDIO bus ++ * access, if there is no NPE-C, no bus, nothing works, ++ * so bail out. ++ */ ++ if (cpu_is_ixp43x()) { ++ if (!(ixp4xx_read_feature_bits() & ++ IXP4XX_FEATURE_NPEC_ETH)) ++ return -ENODEV; ++ /* Else register the MDIO bus on NPE-B */ ++ plat->has_mdio = true; ++ } ++ break; ++ default: ++ return -ENODEV; ++ } ++ } + + if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port)))) + return -ENOMEM; +@@ -1377,59 +1479,29 @@ static int ixp4xx_eth_probe(struct platform_device *pdev) + SET_NETDEV_DEV(ndev, dev); + port = netdev_priv(ndev); + port->netdev = ndev; +- port->id = pdev->id; ++ port->id = plat->npe; + + /* Get the port resource and remap */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; +- regs_phys = res->start; + port->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(port->regs)) + return PTR_ERR(port->regs); + +- switch (port->id) { +- case IXP4XX_ETH_NPEA: +- /* If the MDIO bus is not up yet, defer probe */ +- if (!mdio_bus) +- return -EPROBE_DEFER; +- break; +- case IXP4XX_ETH_NPEB: +- /* +- * On all except IXP43x, NPE-B is used for the MDIO bus. +- * If there is no NPE-B in the feature set, bail out, else +- * register the MDIO bus. +- */ +- if (!cpu_is_ixp43x()) { +- if (!(ixp4xx_read_feature_bits() & +- IXP4XX_FEATURE_NPEB_ETH0)) +- return -ENODEV; +- /* Else register the MDIO bus on NPE-B */ +- if ((err = ixp4xx_mdio_register(port->regs))) +- return err; +- } +- if (!mdio_bus) +- return -EPROBE_DEFER; +- break; +- case IXP4XX_ETH_NPEC: +- /* +- * IXP43x lacks NPE-B and uses NPE-C for the MDIO bus access, +- * of there is no NPE-C, no bus, nothing works, so bail out. +- */ +- if (cpu_is_ixp43x()) { +- if (!(ixp4xx_read_feature_bits() & +- IXP4XX_FEATURE_NPEC_ETH)) +- return -ENODEV; +- /* Else register the MDIO bus on NPE-C */ +- if ((err = ixp4xx_mdio_register(port->regs))) +- return err; ++ /* Register the MDIO bus if we have it */ ++ if (plat->has_mdio) { ++ err = ixp4xx_mdio_register(port->regs); ++ if (err) { ++ dev_err(dev, "failed to register MDIO bus\n"); ++ return err; + } +- if (!mdio_bus) +- return -EPROBE_DEFER; +- break; +- default: +- return -ENODEV; + } ++ /* If the instance with the MDIO bus has not yet appeared, ++ * defer probing until it gets probed. ++ */ ++ if (!mdio_bus) ++ return -EPROBE_DEFER; + + ndev->netdev_ops = &ixp4xx_netdev_ops; + ndev->ethtool_ops = &ixp4xx_ethtool_ops; +@@ -1440,12 +1512,6 @@ static int ixp4xx_eth_probe(struct platform_device *pdev) + if (!(port->npe = npe_request(NPE_ID(port->id)))) + return -EIO; + +- port->mem_res = request_mem_region(regs_phys, REGS_SIZE, ndev->name); +- if (!port->mem_res) { +- err = -EBUSY; +- goto err_npe_rel; +- } +- + port->plat = plat; + npe_port_tab[NPE_ID(port->id)] = port; + memcpy(ndev->dev_addr, plat->hwaddr, ETH_ALEN); +@@ -1458,15 +1524,26 @@ static int ixp4xx_eth_probe(struct platform_device *pdev) + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); + udelay(50); + +- phydev = mdiobus_get_phy(mdio_bus, plat->phy); +- if (IS_ERR(phydev)) { +- err = PTR_ERR(phydev); +- goto err_free_mem; ++ if (np) { ++ phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link); ++ } else { ++ phydev = mdiobus_get_phy(mdio_bus, plat->phy); ++ if (IS_ERR(phydev)) { ++ err = PTR_ERR(phydev); ++ dev_err(dev, "could not connect phydev (%d)\n", err); ++ goto err_free_mem; ++ } ++ err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link, ++ PHY_INTERFACE_MODE_MII); ++ if (err) ++ goto err_free_mem; ++ + } +- err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link, +- PHY_INTERFACE_MODE_MII); +- if (err) ++ if (!phydev) { ++ err = -ENODEV; ++ dev_err(dev, "no phydev\n"); + goto err_free_mem; ++ } + + phydev->irq = PHY_POLL; + +@@ -1482,8 +1559,6 @@ err_phy_dis: + phy_disconnect(phydev); + err_free_mem: + npe_port_tab[NPE_ID(port->id)] = NULL; +- release_resource(port->mem_res); +-err_npe_rel: + npe_release(port->npe); + return err; + } +@@ -1499,12 +1574,21 @@ static int ixp4xx_eth_remove(struct platform_device *pdev) + ixp4xx_mdio_remove(); + npe_port_tab[NPE_ID(port->id)] = NULL; + npe_release(port->npe); +- release_resource(port->mem_res); + return 0; + } + ++static const struct of_device_id ixp4xx_eth_of_match[] = { ++ { ++ .compatible = "intel,ixp4xx-ethernet", ++ }, ++ { }, ++}; ++ + static struct platform_driver ixp4xx_eth_driver = { +- .driver.name = DRV_NAME, ++ .driver = { ++ .name = DRV_NAME, ++ .of_match_table = of_match_ptr(ixp4xx_eth_of_match), ++ }, + .probe = ixp4xx_eth_probe, + .remove = ixp4xx_eth_remove, + }; +diff --git a/include/linux/platform_data/eth_ixp4xx.h b/include/linux/platform_data/eth_ixp4xx.h +index 6f652ea0c6ae2..114b0940729f5 100644 +--- a/include/linux/platform_data/eth_ixp4xx.h ++++ b/include/linux/platform_data/eth_ixp4xx.h +@@ -14,6 +14,8 @@ struct eth_plat_info { + u8 rxq; /* configurable, currently 0 - 31 only */ + u8 txreadyq; + u8 hwaddr[6]; ++ u8 npe; /* NPE instance used by this interface */ ++ bool has_mdio; /* If this instance has an MDIO bus */ + }; + + #endif +-- +cgit 1.2.3-1.el7 + diff --git a/target/linux/ixp4xx/patches-5.10/112-ARM-dts-ixp4xx_Add-ethernet.patch b/target/linux/ixp4xx/patches-5.10/112-ARM-dts-ixp4xx_Add-ethernet.patch new file mode 100644 index 0000000000..50c9c34b3a --- /dev/null +++ b/target/linux/ixp4xx/patches-5.10/112-ARM-dts-ixp4xx_Add-ethernet.patch @@ -0,0 +1,294 @@ +From patchwork Mon May 10 10:49:06 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Linus Walleij +X-Patchwork-Id: 12247667 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, + DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, + INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 14601C433B4 + for ; + Mon, 10 May 2021 11:20:17 +0000 (UTC) +Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by mail.kernel.org (Postfix) with ESMTPS id 8901661075 + for ; + Mon, 10 May 2021 11:20:16 +0000 (UTC) +DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8901661075 +Authentication-Results: mail.kernel.org; + dmarc=fail (p=none dis=none) header.from=linaro.org +Authentication-Results: mail.kernel.org; + spf=none + smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding + :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: + List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc:To:From: + Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender + :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; + bh=5qkyxZ+UJ46zB/g4P1tCk13eDWmYREdNQ+MfrPmV51k=; b=SVsGgq4K3LXtffB5AptLRertnB + xtFb0DUAj/aENNWvRxVPKbofCzoQ8/rGi1AEwa1jPccxIvLcr6C0msN8db2AP33/W2setb1J1Q+7y + G3aNkazvmgnAaPPTWHTxqQX9JsF+fThUHUulT2fDa2V9d/vp8X+eUZaJfWdiIOxKnqzKgijOyd3up + 2AtzAe+Jidh4sV+Fnzj4A5xkYGCNxLon3JVXwG+9PgyYIOKDfGOKA6rdn5eUgiI5nx6SYRFd56P5o + ujO/uoyCszk4RSbuiu88TCKOHX4/ieoikKf6pt2bBz9Q4xISeJUZs5saedu157W8O9l3Tjq/3up05 + co4MGygw==; +Received: from localhost ([::1] helo=desiato.infradead.org) + by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) + id 1lg3uv-00E3dQ-Ph; Mon, 10 May 2021 11:17:42 +0000 +Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) + by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) + id 1lg3TU-00DztP-3K + for linux-arm-kernel@desiato.infradead.org; Mon, 10 May 2021 10:49:20 +0000 +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: + MIME-Version:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: + Content-ID:Content-Description:In-Reply-To:References; + bh=Dc9lTYDk2w1qC1UrDqj0pos3vOiNr3FtS2kDu12yHUU=; b=yQKUJ6mekgWast1xBblPv99TYD + 1EcZiS8D1DXViKHGEC2TdKVFm4v0xBaG5Dt/x8UNBR5q8NChqjgndexg95PvkhHBfrWrfHczWn4SI + 1nmDlHDU9AX0FYnwLvftxL/ScmcqD/dizyLyV9KBLdbN/TxdEwtngDmPR3tZFyztHQb4M9LNJNtPq + yJUjBbdwWv3Mln9H4D67lJ1mwFYiHSo2HZYdHtOEujnrPGQKpkDIGKLTmWsdBRjjRgBZxGu94j1az + Q8fUfu+RdV0W3kP3io93eVPfB9zPnbaR1sHCr49A0mZOyEH+RMtwNMr2u01PGcvK2kKvti3+WilzD + EOKz/kWQ==; +Received: from mail-lf1-x12b.google.com ([2a00:1450:4864:20::12b]) + by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) + id 1lg3TQ-008ZIt-Th + for linux-arm-kernel@lists.infradead.org; Mon, 10 May 2021 10:49:18 +0000 +Received: by mail-lf1-x12b.google.com with SMTP id z9so22623712lfu.8 + for ; + Mon, 10 May 2021 03:49:14 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; + h=from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=Dc9lTYDk2w1qC1UrDqj0pos3vOiNr3FtS2kDu12yHUU=; + b=pPQCSrOaOCVtJJmqE4pYIim3TyGAnbB3T/ufBTF98MXLHy/4B0FFVyS5SeUhLSchcm + +X2MQy0D5zFXja+jUMgKL51r7dmtnXOiJ6lolq7g/gGtX1fM2oEGmUW+G6G14qrNO8O5 + obccM5oNzhy3il/0yMMoTAuNNUumx/z6zUXwG1ycBOXLP4TPmznfHVe/GTvvc8UTt82+ + li0PhT4pYbusV63AV0nIIMVoOWNjyfQOKptfVaGqgNR+GY5b8cjGHxI/nuI4tjNnc85E + RZ/WWwbD0VWHKcIK4aCFz4juwVstTfxtVkHvNOyu64iLy4AIWWenF+lKuBHRRdWeAzl0 + uhEg== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=Dc9lTYDk2w1qC1UrDqj0pos3vOiNr3FtS2kDu12yHUU=; + b=oVAC9gJrpbHs2NyJFsl/3zLp/71aNx6yON/J6L6A4IBPR5lcqHeLHh8nwJnmolgEui + q54AYdQnhQglFoRx/3UQkdgoat62aeWm3dsODwd+ASTwCG05rKHRJfUTj993f8WzeoLV + tJwJT95zBvGIzseB5MaS32quS2EQETbox/Yp038Wqe5u60kT5U2kVFlguq2XarJPQxwg + 5QQNlTZD6WwBmsIZgTgwRn+OqMpU7mBXkdTspjnJ999sOQliH7voZb3agyxMvaRARgpj + TQydHwisOaQpMzwMq2gw8mU5/OJPMP9ffd6e9UJR3Mlumcrlf05nDIo/GmuszBfo6M+t + yrGw== +X-Gm-Message-State: AOAM532Q97ytRrQnCNAzWGTaTOFLDhlRYiiwpdyaoyx0dLSsl4Ec6Xo/ + dR0I8nb6ZCSSaz5fBahWyv1xBIqZefxmSQ== +X-Google-Smtp-Source: + ABdhPJyQqVP0M4DcWjxmBw2XTmW42T+VphzZjZI3+t2eVROd6vLsGWAaeqF40UekmgYs8jAsw+uwgA== +X-Received: by 2002:a05:6512:1116:: with SMTP id + l22mr16523555lfg.473.1620643752864; + Mon, 10 May 2021 03:49:12 -0700 (PDT) +Received: from localhost.localdomain + (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) + by smtp.gmail.com with ESMTPSA id m17sm2078126ljb.122.2021.05.10.03.49.12 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Mon, 10 May 2021 03:49:12 -0700 (PDT) +From: Linus Walleij +To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , + Krzysztof Halasa +Cc: Linus Walleij , Zoltan HERPAI , + Raylynn Knight +Subject: [PATCH] ARM: dts: ixp4xx: Add ethernet +Date: Mon, 10 May 2021 12:49:06 +0200 +Message-Id: <20210510104906.439171-1-linus.walleij@linaro.org> +X-Mailer: git-send-email 2.30.2 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20210510_034917_037810_D3AE7078 +X-CRM114-Status: GOOD ( 13.57 ) +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +This adds ethernet to the IXP4xx device trees. + +Cc: Zoltan HERPAI +Cc: Raylynn Knight +Signed-off-by: Linus Walleij +--- +ChangeLog v1->v2: +- Adapt to the changes adding the proper MDIO bus and + phy references in the nodes. +- Use phandle for reference the NPE +--- + .../boot/dts/intel-ixp42x-linksys-nslu2.dts | 19 ++++++++ + .../dts/intel-ixp43x-gateworks-gw2358.dts | 19 ++++++++ + arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi | 44 +++++++++++++++++++ + arch/arm/boot/dts/intel-ixp4xx.dtsi | 24 +++++++++- + 4 files changed, 105 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +index 8fcd95805ff4..8cacf035dc32 100644 +--- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts ++++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +@@ -106,4 +106,23 @@ partitions { + fis-index-block = <0x3f>; + }; + }; ++ ++ soc { ++ ethernet@c8009000 { ++ status = "ok"; ++ queue-rx = <&qmgr 3>; ++ queue-txready = <&qmgr 20>; ++ phy-mode = "rgmii"; ++ phy-handle = <&phy1>; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ }; + }; +diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +index ba1163a1e1e7..f89d41b496ab 100644 +--- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts ++++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +@@ -91,4 +91,23 @@ partitions { + fis-index-block = <0xff>; + }; + }; ++ ++ soc { ++ ethernet@c800a000 { ++ status = "ok"; ++ queue-rx = <&qmgr 4>; ++ queue-txready = <&qmgr 21>; ++ phy-mode = "rgmii"; ++ phy-handle = <&phy1>; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ }; + }; +diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi +index f8cd506659dc..ef3696e369b8 100644 +--- a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi ++++ b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi +@@ -30,5 +30,49 @@ i2c@c8011000 { + interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; ++ ++ /* This is known as EthA */ ++ ethernet@c800c000 { ++ compatible = "intel,ixp4xx-ethernet"; ++ reg = <0xc800c000 0x1000>; ++ status = "disabled"; ++ intel,npe = <0>; ++ /* Dummy values that depend on firmware */ ++ queue-rx = <&qmgr 0>; ++ queue-txready = <&qmgr 0>; ++ }; ++ ++ /* This is known as EthB1 */ ++ ethernet@c800d000 { ++ compatible = "intel,ixp4xx-ethernet"; ++ reg = <0xc800d000 0x1000>; ++ status = "disabled"; ++ intel,npe = <1>; ++ /* Dummy values that depend on firmware */ ++ queue-rx = <&qmgr 0>; ++ queue-txready = <&qmgr 0>; ++ }; ++ ++ /* This is known as EthB2 */ ++ ethernet@c800e000 { ++ compatible = "intel,ixp4xx-ethernet"; ++ reg = <0xc800e000 0x1000>; ++ status = "disabled"; ++ intel,npe = <2>; ++ /* Dummy values that depend on firmware */ ++ queue-rx = <&qmgr 0>; ++ queue-txready = <&qmgr 0>; ++ }; ++ ++ /* This is known as EthB3 */ ++ ethernet@c800f000 { ++ compatible = "intel,ixp4xx-ethernet"; ++ reg = <0xc800f000 0x1000>; ++ status = "disabled"; ++ intel,npe = <3>; ++ /* Dummy values that depend on firmware */ ++ queue-rx = <&qmgr 0>; ++ queue-txready = <&qmgr 0>; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi +index d4a09584f417..b3de0501cf6f 100644 +--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi ++++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi +@@ -61,9 +61,31 @@ timer@c8005000 { + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + }; + +- npe@c8006000 { ++ npe: npe@c8006000 { + compatible = "intel,ixp4xx-network-processing-engine"; + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + }; ++ ++ /* This is known as EthB */ ++ ethernet@c8009000 { ++ compatible = "intel,ixp4xx-ethernet"; ++ reg = <0xc8009000 0x1000>; ++ status = "disabled"; ++ /* Dummy values that depend on firmware */ ++ queue-rx = <&qmgr 3>; ++ queue-txready = <&qmgr 20>; ++ intel,npe-handle = <&npe 1>; ++ }; ++ ++ /* This is known as EthC */ ++ ethernet@c800a000 { ++ compatible = "intel,ixp4xx-ethernet"; ++ reg = <0xc800a000 0x1000>; ++ status = "disabled"; ++ /* Dummy values that depend on firmware */ ++ queue-rx = <&qmgr 0>; ++ queue-txready = <&qmgr 0>; ++ intel,npe-handle = <&npe 2>; ++ }; + }; + }; diff --git a/target/linux/ixp4xx/patches-5.10/120-ARM-dts-ixp4xx_Add-PCI-hosts.patch b/target/linux/ixp4xx/patches-5.10/120-ARM-dts-ixp4xx_Add-PCI-hosts.patch new file mode 100644 index 0000000000..f0eac69317 --- /dev/null +++ b/target/linux/ixp4xx/patches-5.10/120-ARM-dts-ixp4xx_Add-PCI-hosts.patch @@ -0,0 +1,230 @@ +From patchwork Mon May 10 21:40:18 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Linus Walleij +X-Patchwork-Id: 12250325 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, + DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, + INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, + USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 8DC14C433ED + for ; + Tue, 11 May 2021 09:35:56 +0000 (UTC) +Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by mail.kernel.org (Postfix) with ESMTPS id 0A0CA61001 + for ; + Tue, 11 May 2021 09:35:56 +0000 (UTC) +DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0A0CA61001 +Authentication-Results: mail.kernel.org; + dmarc=fail (p=none dis=none) header.from=linaro.org +Authentication-Results: mail.kernel.org; + spf=none + smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding + :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: + List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc:To:From: + Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender + :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; + bh=xDWD17BbuY6MdGgtt5oz7rk7MIbcknvFhyf1osCLR5Q=; b=bOlTNwSXSvVoneBEhNZRduHCBd + exM5wNZBnBdtq1Y9Ldv/gtP1Pk7OtjAFptAPV91VlPWYy91d+j+QRvXYK5rDW7Xl6goHYlIyokSOj + MO/4QDTJshve6XDgSvEdnyQObCwxSeF2RtaF45mer5E2Y6n5hPLt437mHDkqkjOIFfgsBDmynjUm7 + pv4ag5nnhTnNd6jhChUlCrr8pr80cZcyVLeDQjCPc9MFPTpADBCtMSD8NLfYqsn/SWJyLRkTHYZTD + m7+F+Os1u6mvwKdIosPNO6JKFOeV8cEFwWlLT1vo4sbzbk4YomFep1Mv4KvcYeiU6oISXDpeBCFnU + 8pjfi1WQ==; +Received: from localhost ([::1] helo=desiato.infradead.org) + by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) + id 1lgOmn-00Gi7k-Fn; Tue, 11 May 2021 09:34:42 +0000 +Received: from [2607:7c80:54:e::133] (helo=bombadil.infradead.org) + by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) + id 1lgDdl-00Flrs-9k + for linux-arm-kernel@desiato.infradead.org; Mon, 10 May 2021 21:40:39 +0000 +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: + MIME-Version:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: + Content-ID:Content-Description:In-Reply-To:References; + bh=XznhLAqjGhAeOXRKMwVR6Rf7MCA7wt/7fX8LXZE5ClI=; b=bTy5fWzhPgpgHG/oC2rdKTlFSs + OD0u+P2YE29WmMfYeqwREj0lHhjSNpX9VLJfWmNkoq9o5W685DshYQgSnFRSV02ex6SewmWvYC97p + WmR1n0cFBKc1C6lGwBd4nyShEHdtjs0JF/3QuWNCRZbQ6KoNjlY6S3BUQ9lwYsL4uzzjz8PNfxujD + FBSv0NN9JX2t9rz8KxWd6bVHQ8puNqDrLAvZpcBPIGVU2ThIpB+rgAivogGjWjJFBKyJ7fAigJm5D + XKGqnJ+W7jqj/Q+1E3SfVW1Vt+uRKVk3tfxHRjNEYXPY8oCa4h4jSJVWnfFD8AViC3mXw3SNj5ZqV + Cu2sDAlA==; +Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) + by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) + id 1lgDdi-0098Zl-6r + for linux-arm-kernel@lists.infradead.org; Mon, 10 May 2021 21:40:36 +0000 +Received: by mail-lf1-x136.google.com with SMTP id j10so25523248lfb.12 + for ; + Mon, 10 May 2021 14:40:33 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; + h=from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=XznhLAqjGhAeOXRKMwVR6Rf7MCA7wt/7fX8LXZE5ClI=; + b=Pe26FGhk+2IF9moQqznF19Yx8Cf9b43Kp04o1zKxjcIjvUVycmWUz+lQ2oeGGwqjS9 + iys7uEfdTgVMbHKZbd20/s3eXgwZPPF+oAd+Ju6ibnUxV9AjMt40WYTuFeqaLGuNTJX4 + M/xaDSBRtt0N4UA3gEcbvvYwN964YHw0ar9fMYVYV0Vk60BdOZv6NiqVkipz3V/Ged4s + K5rIEMMjC6YpB+JNbbY/fTN502zQQMuSb2YO4jjWRzDRZjZO3yvdOfrHD5oZbuR/6SNT + jEAB0PwQo3BokKpWbEfq5WhnVv1mzDEJLP2uHv+O4g6XlzhEvEK8B6Iq/rvvieCBYtVW + t7HQ== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=XznhLAqjGhAeOXRKMwVR6Rf7MCA7wt/7fX8LXZE5ClI=; + b=FGmgwkcyBu9LWqjOwoUyhu5mVf2NRgnnKM23dqN099RoqZokn4DfGmivmIGprlNWuB + 9cBhRs/XdiinWpKjUjiQNq4Inhjp/qfkJpI8KVmQHGnu5UCecQCgjTdFR7y9HhuAGj6R + Z/6CoEpWpAsKbzPKbQhN+gM/OCHzxmFv5Enlc3jED5S41ZFIghPDeFWRh642we8Vx/Vd + VgwaK1Mf6ZuOzluxpaFji/10ZduGRaOhz38P0pgM1B/WyQwcIrmBsN4IexXkzDJfoQ8b + mddqRWsnZGRkvnY2Pvq4V7c5FLGIpXziKb23Vj4ocMp+dnfHATyqQGOrGdn0GjhOR2k4 + 8JTw== +X-Gm-Message-State: AOAM533wemapljubmWtJICNGJ3MDHD4JQ0+Ni2zAs9V5aFTdQ/Lzue3j + 2CrOB2CytX6lrNxo0assk1bwWCyLZlbcyA== +X-Google-Smtp-Source: + ABdhPJwvcbGS6B2Symz58FB/2SlCOrr36yI1eStUY/QBo/3RyknJIWk3O5e8X9266kxraE596+serg== +X-Received: by 2002:a05:6512:3aa:: with SMTP id + v10mr17988787lfp.263.1620682832379; + Mon, 10 May 2021 14:40:32 -0700 (PDT) +Received: from localhost.localdomain + (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) + by smtp.gmail.com with ESMTPSA id t12sm2391855lfl.254.2021.05.10.14.40.29 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Mon, 10 May 2021 14:40:32 -0700 (PDT) +From: Linus Walleij +To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , + Krzysztof Halasa +Cc: Linus Walleij , Zoltan HERPAI , + Raylynn Knight +Subject: [PATCH] ARM: dts: ixp4xx: Add PCI hosts +Date: Mon, 10 May 2021 23:40:18 +0200 +Message-Id: <20210510214018.601580-1-linus.walleij@linaro.org> +X-Mailer: git-send-email 2.30.2 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20210510_144034_335163_852B83CC +X-CRM114-Status: GOOD ( 19.15 ) +/bin/ln: failed to access + 'reaver_cache/texts/20210510_144034_335163_852B83CC': No such file or + directory +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20210510_144034_335163_852B83CC +X-CRM114-Status: GOOD ( 15.80 ) +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +This adds a basic PCI host definition to the base device +tree for IXP4xx and then further details it in the 42x +and 43x device tree include, also the specific target +devices NSLU2 and GW2358 get proper PCI swizzling +defined. + +Cc: Zoltan HERPAI +Cc: Raylynn Knight +Signed-off-by: Linus Walleij +--- + .../boot/dts/intel-ixp42x-linksys-nslu2.dts | 27 +++++++++++ + arch/arm/boot/dts/intel-ixp42x.dtsi | 4 ++ + .../dts/intel-ixp43x-gateworks-gw2358.dts | 46 +++++++++++++++++++ + arch/arm/boot/dts/intel-ixp43x.dtsi | 4 ++ + arch/arm/boot/dts/intel-ixp4xx.dtsi | 36 +++++++++++++++ + 5 files changed, 117 insertions(+) + +diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi +index a9622ca850cc..5fa063ed396c 100644 +--- a/arch/arm/boot/dts/intel-ixp42x.dtsi ++++ b/arch/arm/boot/dts/intel-ixp42x.dtsi +@@ -7,6 +7,10 @@ + + / { + soc { ++ pci@c0000000 { ++ compatible = "intel,ixp42x-pci"; ++ }; ++ + interrupt-controller@c8003000 { + compatible = "intel,ixp42x-interrupt"; + }; +diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel-ixp43x.dtsi +index 494fb2ff57a0..1d0817c6e3f9 100644 +--- a/arch/arm/boot/dts/intel-ixp43x.dtsi ++++ b/arch/arm/boot/dts/intel-ixp43x.dtsi +@@ -8,6 +8,10 @@ + + / { + soc { ++ pci@c0000000 { ++ compatible = "intel,ixp43x-pci"; ++ }; ++ + interrupt-controller@c8003000 { + compatible = "intel,ixp43x-interrupt"; + }; +diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi +index d4a09584f417..52ba8e4a49cc 100644 +--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi ++++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi +@@ -20,6 +20,42 @@ qmgr: queue-manager@60000000 { + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; + }; + ++ pci@c0000000 { ++ compatible = "intel,ixp43x-pci"; ++ reg = <0xc0000000 0x1000>; ++ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, ++ <9 IRQ_TYPE_LEVEL_HIGH>, ++ <10 IRQ_TYPE_LEVEL_HIGH>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ bus-range = <0x00 0xff>; ++ status = "disabled"; ++ ++ ranges = ++ /* ++ * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff ++ * done in 4 chunks of 16MB each. ++ */ ++ <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, ++ /* 64KB I/O space at 0x4c000000 */ ++ <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; ++ ++ /* ++ * This needs to map to the start of physical memory so ++ * PCI devices can see all (hopefully) memory. This is done ++ * using 4 1:1 16MB windows, so the RAM should not be more than ++ * 64 MB for this to work. If your memory is anywhere else ++ * than at 0x0 you need to alter this. ++ */ ++ dma-ranges = ++ <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0xf800 0 0 7>; ++ /* Each unique DTS using PCI must specify the swizzling */ ++ }; ++ + uart0: serial@c8000000 { + compatible = "intel,xscale-uart"; + reg = <0xc8000000 0x1000>; diff --git a/target/linux/ixp4xx/patches-5.10/121-ixp4xx-pci-rework.patch b/target/linux/ixp4xx/patches-5.10/121-ixp4xx-pci-rework.patch new file mode 100644 index 0000000000..4830643436 --- /dev/null +++ b/target/linux/ixp4xx/patches-5.10/121-ixp4xx-pci-rework.patch @@ -0,0 +1,1712 @@ +From patchwork Sun May 9 22:20:52 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Linus Walleij +X-Patchwork-Id: 1475993 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org + (client-ip=23.128.96.18; helo=vger.kernel.org; + envelope-from=linux-pci-owner@vger.kernel.org; receiver=) +Authentication-Results: ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 + header.s=google header.b=E/riOnsy; + dkim-atps=neutral +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by ozlabs.org (Postfix) with ESMTP id 4Fddtp0j1Wz9tlN + for ; Mon, 10 May 2021 08:21:06 +1000 (AEST) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S229925AbhEIWWI (ORCPT ); + Sun, 9 May 2021 18:22:08 -0400 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47568 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S229699AbhEIWWI (ORCPT + ); Sun, 9 May 2021 18:22:08 -0400 +Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com + [IPv6:2a00:1450:4864:20::133]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A138AC061573 + for ; Sun, 9 May 2021 15:21:03 -0700 (PDT) +Received: by mail-lf1-x133.google.com with SMTP id i9so13944168lfe.13 + for ; Sun, 09 May 2021 15:21:03 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=linaro.org; s=google; + h=from:to:cc:subject:date:message-id:in-reply-to:references + :mime-version:content-transfer-encoding; + bh=gNke3Wg2Ntk9EmsCen3APo/ovEtU9o2zaCxzSbnHEjc=; + b=E/riOnsyi0z1LVj74roTINvavou0wy/aH+tbOcLOWKnNl52bsoqcZY0xvpiMktv/xI + 5A69KJogEoICmslVDQxGNcmoDP67ec3mVcUBA8xxRYR9REsd0Ht4iaODg/B7CGdwna+6 + /IkxbUE5wOkjx8zmltpMRmt15a1pg2TIm8XxszspCuyftJnCZZXqfIEX9ZSlwDv0KtEv + I7U4XZjHFrW4SENTQ48qVXZKbQpRbK2aTqbRx/sw7pQBA0T0QfNwuDFBowXsY333Iwnm + McHw7WiVLXuiB2CucJhrMN7KSHfZGqLxYtrvFHmynWnIHFP04CvJcx98CJzurvf7xFKp + DWHw== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to + :references:mime-version:content-transfer-encoding; + bh=gNke3Wg2Ntk9EmsCen3APo/ovEtU9o2zaCxzSbnHEjc=; + b=gQGZUxhIfdOO0fV0Xr7yBX2ZK+Ly67R1HIS6dxJTF6JbGOaROWc025cnbYcNN7EekA + 4v9iJbHa2cO3N103hqRi+KVZeJ9aMX8ltcQDJWHwPpjrPVrC9zBR1umx/r6RxP/7Q7qP + 94OVIBzMbnLVzcZtf7yMyjHXEeROUBxtTBSe3lxreqiubxlyfrbvNZfRROJSoMjgEc5P + DylF6lgoGgX4RcUHaxY6fTk52BNDDu9x4CO8z9pvbu7U7VZF7BNXYlj7UDt4QXE8km3k + 71nIJ5Ov6TZy8prbWcvHltiYX4w+gJGoJdhT7ZbXOuNqk4ozTKp7Q4Eej8y5wgYXRmwg + sPtw== +X-Gm-Message-State: AOAM530kYdWDP7TzhIg7am/8LSXFf2MfdgoYncXdrLr7cZQqNVUKH9lK + unbrMSsk3sagwTxVAAlauuvTQux0J76qvg== +X-Google-Smtp-Source: + ABdhPJxWl2X24W0gh7u2BYDaANrXtvvx7rcfVGg85va5f0PByl5HL9ebofT8nhpAYJ9sk+10RCHTjA== +X-Received: by 2002:a05:6512:3d0f:: with SMTP id + d15mr14937066lfv.639.1620598862132; + Sun, 09 May 2021 15:21:02 -0700 (PDT) +Received: from localhost.localdomain + (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) + by smtp.gmail.com with ESMTPSA id + u12sm2978012ljo.82.2021.05.09.15.21.01 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Sun, 09 May 2021 15:21:01 -0700 (PDT) +From: Linus Walleij +To: Bjorn Helgaas +Cc: linux-pci@vger.kernel.org, Arnd Bergmann , + Imre Kaloz , + Krzysztof Halasa , + Zoltan HERPAI , + Raylynn Knight , + Linus Walleij +Subject: [PATCH 1/4 v3] ARM/ixp4xx: Move the virtual IObases +Date: Mon, 10 May 2021 00:20:52 +0200 +Message-Id: <20210509222055.341945-2-linus.walleij@linaro.org> +X-Mailer: git-send-email 2.30.2 +In-Reply-To: <20210509222055.341945-1-linus.walleij@linaro.org> +References: <20210509222055.341945-1-linus.walleij@linaro.org> +MIME-Version: 1.0 +Precedence: bulk +List-ID: +X-Mailing-List: linux-pci@vger.kernel.org + +UART1, UART2 and the expansion bus config registers +are the only registers mapped in a fixed location +when using device tree. + +For device tree we also want to get rid of the custom + for IXP4xx. So we need to undefine +CONFIG_NEED_MACH_IO_H. Doing that activates the fixed +mapping of the PCI IO space to PCI_IO_VIRT_BASE which +is hardcoded to 0xFEE00000 and this would collide with +the old fixed mappings. + +Move the fixed virtual IO base address from 0xFEF00000 +to 0xFEC00000 in order to avoid the collision. + +For the OF-only boot path let's even cut the reliance +on and just hardcode the one single virtbase +we need apart from the UART, which is hardcoded in +Kconfig.debug. + +Cc: Arnd Bergmann +Cc: Imre Kaloz +Cc: Krzysztof Halasa +Cc: Zoltan HERPAI +Cc: Raylynn Knight +Signed-off-by: Linus Walleij +--- +ChangeLog v2->v3: +- No changes, resend with the rest of the patches. +ChangeLog v1->v2: +- Instead of handling the UART and expansion ports + separately just move all peripherals from 0xfef00000 + to 0xfec00000. +- Stay out of the fixmap area, that area has special + uses. + +PCI maintainers: this patch is mostly FYI, will be +merged through ARM SoC +--- + arch/arm/Kconfig.debug | 4 ++-- + arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h | 7 ++++--- + arch/arm/mach-ixp4xx/ixp4xx-of.c | 8 ++++++-- + 3 files changed, 12 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug +index 9e0b5e7f12af..f672b23301e6 100644 +--- a/arch/arm/Kconfig.debug ++++ b/arch/arm/Kconfig.debug +@@ -1803,8 +1803,8 @@ config DEBUG_UART_VIRT + default 0xfedc0000 if DEBUG_EP93XX + default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1 + default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART +- default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN +- default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN ++ default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN ++ default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN + default 0xfef36000 if DEBUG_HIGHBANK_UART + default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 + default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 +diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +index 708d085ce39f..f375c1c005d4 100644 +--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h ++++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +@@ -45,21 +45,21 @@ + * it can be used with the low-level debug code. + */ + #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 +-#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000) ++#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000) + #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 + + /* + * PCI Config registers + */ + #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 +-#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000) ++#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000) + #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 + + /* + * Expansion BUS Configuration registers + */ + #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 +-#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000 ++#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000 + #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 + + #define IXP4XX_EXP_CS0_OFFSET 0x00 +@@ -120,6 +120,7 @@ + #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) + + ++/* The UART is explicitly put in the beginning of fixmap */ + #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) + #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) + #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) +diff --git a/arch/arm/mach-ixp4xx/ixp4xx-of.c b/arch/arm/mach-ixp4xx/ixp4xx-of.c +index 7449b8319c8a..f9904716ec7f 100644 +--- a/arch/arm/mach-ixp4xx/ixp4xx-of.c ++++ b/arch/arm/mach-ixp4xx/ixp4xx-of.c +@@ -9,8 +9,12 @@ + #include + #include + +-#include +-#include ++/* ++ * These are the only fixed phys to virt mappings we ever need ++ * we put it right after the UART mapping at 0xffc80000-0xffc81fff ++ */ ++#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 ++#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000 + + static struct map_desc ixp4xx_of_io_desc[] __initdata = { + /* + +From patchwork Sun May 9 22:20:53 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Linus Walleij +X-Patchwork-Id: 1475994 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org + (client-ip=23.128.96.18; helo=vger.kernel.org; + envelope-from=linux-pci-owner@vger.kernel.org; receiver=) +Authentication-Results: ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 + header.s=google header.b=N5ug85eb; + dkim-atps=neutral +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by ozlabs.org (Postfix) with ESMTP id 4Fddtq1Hkwz9tlN + for ; Mon, 10 May 2021 08:21:07 +1000 (AEST) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S229933AbhEIWWJ (ORCPT ); + Sun, 9 May 2021 18:22:09 -0400 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47576 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S229973AbhEIWWJ (ORCPT + ); Sun, 9 May 2021 18:22:09 -0400 +Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com + [IPv6:2a00:1450:4864:20::134]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AA24C061573 + for ; Sun, 9 May 2021 15:21:05 -0700 (PDT) +Received: by mail-lf1-x134.google.com with SMTP id c3so20502850lfs.7 + for ; Sun, 09 May 2021 15:21:05 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=linaro.org; s=google; + h=from:to:cc:subject:date:message-id:in-reply-to:references + :mime-version:content-transfer-encoding; + bh=zf+S7hvXyl8k4/OTCUtnv5DVgW50Qe9kDD2QLo75Eic=; + b=N5ug85ebB91Ju07EvncOpKAYdBT1sOVqmHUdsUsgsrOoJuEvxnJRiIDNV/Y8s9Bvm5 + VVL7HRX+537AbZ6w1RAzREwmyBTh8rYUbL2f1MJ44NmBGHU9DjVjljIL96et25XIxj67 + u9fH4cX3Fb5h8DOSSXPBYvx0YNewx5q6wA8sD7/Y0lYTEmO7/G0lyoDI4RNqdgBfCYdw + 1H6Z5G3MfB8HgOh6ztH2tD0gLHwD0rV/RUL96YWPCdwdIbeQnzNo2KNzVYgmiLQRKzDN + HIXjQic8B9MMn6rMnBqwuAcK4JVQI7AO3HvTQvhAUmG5pELC4Ey8LUVmcyCBXomxfhFr + s8nw== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to + :references:mime-version:content-transfer-encoding; + bh=zf+S7hvXyl8k4/OTCUtnv5DVgW50Qe9kDD2QLo75Eic=; + b=ODkBlC9ARXGLWzrsUK1q2U9tZ9H2C/HXiG79lJBZ52kvH4qRKj9opOFobqwCpRPOUb + eKdvxZkdIGlXPB4G52PuARuquLtUEj6v8t8NfF3THjDlNLymO6bz2rqeOMwJEORe/Obj + 8HZZVM2+wtP4Z9GDxKV/YMq9MEENiq2AZEyK9/IT25u/i/71pIJPXJWDM6JwhR/ODrYl + Z1NXdsdC3+u4DDwW1pGadU1t7WsWlF3SR6UEaDPi8UkJslm5iWUu5MD0jEJaivZ4NnhC + kjMNYK6//ettPbJ86awcZ0AHov6klD8m8WNLULagoF7h7jA11bPydSOEUoQ/IlC0YSZg + k8kA== +X-Gm-Message-State: AOAM531uOKv/GEXmQTZdvjGDPQlBFdnU9sLW7eTB83j24nvy2gr/SzWN + JrgK6jV6FZipJKPniX0yjkT50g== +X-Google-Smtp-Source: + ABdhPJygLiDXDZtYmq8f0GFbVIJ8L9U7adTeiB5wUhFzMFYjEzXyvieC46iqA5iRNgU8NEkBfFOpfw== +X-Received: by 2002:a05:6512:12d0:: with SMTP id + p16mr14832876lfg.232.1620598863857; + Sun, 09 May 2021 15:21:03 -0700 (PDT) +Received: from localhost.localdomain + (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) + by smtp.gmail.com with ESMTPSA id + u12sm2978012ljo.82.2021.05.09.15.21.02 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Sun, 09 May 2021 15:21:03 -0700 (PDT) +From: Linus Walleij +To: Bjorn Helgaas +Cc: linux-pci@vger.kernel.org, Arnd Bergmann , + Imre Kaloz , + Krzysztof Halasa , + Zoltan HERPAI , + Raylynn Knight , + Linus Walleij +Subject: [PATCH 2/4 v3] ARM/ixp4xx: Make NEED_MACH_IO_H optional +Date: Mon, 10 May 2021 00:20:53 +0200 +Message-Id: <20210509222055.341945-3-linus.walleij@linaro.org> +X-Mailer: git-send-email 2.30.2 +In-Reply-To: <20210509222055.341945-1-linus.walleij@linaro.org> +References: <20210509222055.341945-1-linus.walleij@linaro.org> +MIME-Version: 1.0 +Precedence: bulk +List-ID: +X-Mailing-List: linux-pci@vger.kernel.org + +In order to create a proper PCI driver for the IXP4xx +we need to make the old PCI driver and its reliance +on optional. + +Create a new Kconfig symbol for the legacy PCI driver +IXP4XX_PCI_LEGACY and only activate NEED_MACH_IO_H +for this driver. + +A few files need to be adjusted to explicitly include +the and headers that +they previously obtained implicitly using +that would include and in turn include +these two headers. + +This breaks our reliance on the old PCI and indirect +PCI support so we can reimplement a proper purely +DT-based driver in the PCI subsystem. + +Cc: Arnd Bergmann +Cc: Imre Kaloz +Cc: Krzysztof Halasa +Cc: Zoltan HERPAI +Cc: Raylynn Knight +Signed-off-by: Linus Walleij +--- +ChangeLog v2->v3: +- No changes, resend with the rest of the patches. + +PCI maintainers: this patch is mostly FYI, will be +merged through ARM SoC +--- + arch/arm/Kconfig | 3 ++- + arch/arm/mach-ixp4xx/Kconfig | 33 +++++++++++++++--------- + arch/arm/mach-ixp4xx/common.c | 1 - + arch/arm/mach-ixp4xx/fsg-setup.c | 1 + + arch/arm/mach-ixp4xx/nas100d-setup.c | 1 + + arch/arm/mach-ixp4xx/nslu2-setup.c | 1 + + drivers/ata/pata_ixp4xx_cf.c | 1 + + drivers/net/ethernet/xscale/ixp4xx_eth.c | 1 + + drivers/soc/ixp4xx/ixp4xx-npe.c | 2 ++ + drivers/soc/ixp4xx/ixp4xx-qmgr.c | 2 ++ + 10 files changed, 32 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 853aab5ab327..4ca2ab19d265 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -394,7 +394,8 @@ config ARCH_IXP4XX + select HAVE_PCI + select IXP4XX_IRQ + select IXP4XX_TIMER +- select NEED_MACH_IO_H ++ # With the new PCI driver this is not needed ++ select NEED_MACH_IO_H if PCI_IXP4XX_LEGACY + select USB_EHCI_BIG_ENDIAN_DESC + select USB_EHCI_BIG_ENDIAN_MMIO + help +diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig +index 165c184801e1..cabb37232704 100644 +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -20,7 +20,7 @@ config MACH_IXP4XX_OF + config MACH_NSLU2 + bool + prompt "Linksys NSLU2" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support Linksys's + NSLU2 NAS device. For more information on this platform, +@@ -28,7 +28,7 @@ config MACH_NSLU2 + + config MACH_AVILA + bool "Avila" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support the Gateworks + Avila Network Platform. For more information on this platform, +@@ -44,7 +44,7 @@ config MACH_LOFT + + config ARCH_ADI_COYOTE + bool "Coyote" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support the ADI + Engineering Coyote Gateway Reference Platform. For more +@@ -52,7 +52,7 @@ config ARCH_ADI_COYOTE + + config MACH_GATEWAY7001 + bool "Gateway 7001" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support Gateway's + 7001 Access Point. For more information on this platform, +@@ -60,7 +60,7 @@ config MACH_GATEWAY7001 + + config MACH_WG302V2 + bool "Netgear WG302 v2 / WAG302 v2" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support Netgear's + WG302 v2 or WAG302 v2 Access Points. For more information +@@ -68,6 +68,7 @@ config MACH_WG302V2 + + config ARCH_IXDP425 + bool "IXDP425" ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support Intel's + IXDP425 Development Platform (Also known as Richfield). +@@ -75,6 +76,7 @@ config ARCH_IXDP425 + + config MACH_IXDPG425 + bool "IXDPG425" ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support Intel's + IXDPG425 Development Platform (Also known as Montajade). +@@ -120,7 +122,7 @@ config ARCH_PRPMC1100 + config MACH_NAS100D + bool + prompt "NAS100D" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support Iomega's + NAS 100d device. For more information on this platform, +@@ -129,7 +131,7 @@ config MACH_NAS100D + config MACH_DSMG600 + bool + prompt "D-Link DSM-G600 RevA" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support D-Link's + DSM-G600 RevA device. For more information on this platform, +@@ -143,7 +145,7 @@ config ARCH_IXDP4XX + config MACH_FSG + bool + prompt "Freecom FSG-3" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support Freecom's + FSG-3 device. For more information on this platform, +@@ -152,7 +154,7 @@ config MACH_FSG + config MACH_ARCOM_VULCAN + bool + prompt "Arcom/Eurotech Vulcan" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support Arcom's + Vulcan board. +@@ -173,7 +175,7 @@ config CPU_IXP43X + config MACH_GTWX5715 + bool "Gemtek WX5715 (Linksys WRV54G)" + depends on ARCH_IXP4XX +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + This board is currently inside the Linksys WRV54G Gateways. + +@@ -196,7 +198,7 @@ config MACH_DEVIXP + + config MACH_MICCPT + bool "Omicron MICCPT" +- select FORCE_PCI ++ depends on IXP4XX_PCI_LEGACY + help + Say 'Y' here if you want your kernel to support the MICCPT + board from OMICRON electronics GmbH. +@@ -209,9 +211,16 @@ config MACH_MIC256 + + comment "IXP4xx Options" + ++config IXP4XX_PCI_LEGACY ++ bool "IXP4xx legacy PCI driver support" ++ depends on PCI ++ help ++ Selects legacy PCI driver. ++ Not recommended for new development. ++ + config IXP4XX_INDIRECT_PCI + bool "Use indirect PCI memory access" +- depends on PCI ++ depends on IXP4XX_PCI_LEGACY + help + IXP4xx provides two methods of accessing PCI memory space: + +diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c +index 000f672a94c9..431da1b4f6bd 100644 +--- a/arch/arm/mach-ixp4xx/common.c ++++ b/arch/arm/mach-ixp4xx/common.c +@@ -32,7 +32,6 @@ + #include + #include + #include +-#include + #include + #include + #include +diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c +index 507ee3878769..844329c5610d 100644 +--- a/arch/arm/mach-ixp4xx/fsg-setup.c ++++ b/arch/arm/mach-ixp4xx/fsg-setup.c +@@ -28,6 +28,7 @@ + #include + #include + #include ++#include + + #include "irqs.h" + +diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c +index 6959ad2e3aec..6133cf01cbe4 100644 +--- a/arch/arm/mach-ixp4xx/nas100d-setup.c ++++ b/arch/arm/mach-ixp4xx/nas100d-setup.c +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + + #include "irqs.h" + +diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c +index a428bb918703..8526a70e401b 100644 +--- a/arch/arm/mach-ixp4xx/nslu2-setup.c ++++ b/arch/arm/mach-ixp4xx/nslu2-setup.c +@@ -31,6 +31,7 @@ + #include + #include + #include ++#include + + #include "irqs.h" + +diff --git a/drivers/ata/pata_ixp4xx_cf.c b/drivers/ata/pata_ixp4xx_cf.c +index d1644a8ef9fa..9929d0150141 100644 +--- a/drivers/ata/pata_ixp4xx_cf.c ++++ b/drivers/ata/pata_ixp4xx_cf.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + + #define DRV_NAME "pata_ixp4xx_cf" + #define DRV_VERSION "0.2" +diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c +index 0152f1e70783..88ad1639a7da 100644 +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + + #include "ixp46x_ts.h" + +diff --git a/drivers/soc/ixp4xx/ixp4xx-npe.c b/drivers/soc/ixp4xx/ixp4xx-npe.c +index ec90b44fa0cd..0a16ac46ab59 100644 +--- a/drivers/soc/ixp4xx/ixp4xx-npe.c ++++ b/drivers/soc/ixp4xx/ixp4xx-npe.c +@@ -20,6 +20,8 @@ + #include + #include + #include ++#include ++#include + + #define DEBUG_MSG 0 + #define DEBUG_FW 0 +diff --git a/drivers/soc/ixp4xx/ixp4xx-qmgr.c b/drivers/soc/ixp4xx/ixp4xx-qmgr.c +index 8c968382cea7..1b1631ac0438 100644 +--- a/drivers/soc/ixp4xx/ixp4xx-qmgr.c ++++ b/drivers/soc/ixp4xx/ixp4xx-qmgr.c +@@ -12,6 +12,8 @@ + #include + #include + #include ++#include ++#include + + static struct qmgr_regs __iomem *qmgr_regs; + static int qmgr_irq_1; + +From patchwork Sun May 9 22:20:54 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Linus Walleij +X-Patchwork-Id: 1475995 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org + (client-ip=23.128.96.18; helo=vger.kernel.org; + envelope-from=linux-pci-owner@vger.kernel.org; receiver=) +Authentication-Results: ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 + header.s=google header.b=bHKoczEP; + dkim-atps=neutral +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by ozlabs.org (Postfix) with ESMTP id 4Fddtt39Ttz9tlN + for ; Mon, 10 May 2021 08:21:10 +1000 (AEST) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S230001AbhEIWWN (ORCPT ); + Sun, 9 May 2021 18:22:13 -0400 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47588 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S229977AbhEIWWL (ORCPT + ); Sun, 9 May 2021 18:22:11 -0400 +Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com + [IPv6:2a00:1450:4864:20::12e]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1420EC061573 + for ; Sun, 9 May 2021 15:21:07 -0700 (PDT) +Received: by mail-lf1-x12e.google.com with SMTP id 7so43886lfp.9 + for ; Sun, 09 May 2021 15:21:06 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=linaro.org; s=google; + h=from:to:cc:subject:date:message-id:in-reply-to:references + :mime-version:content-transfer-encoding; + bh=sjNmqgcstGAxj0Xo8lZD7LTDFmxFM0Yqxj4VjUg9Qdw=; + b=bHKoczEPIMs4+OuEfUaeip+Kx4QcMrQRhH1/FpV85lJgzzgdMedlKhBPf074UYfLXT + yAuzfmjaqjz/jNdg4XUgVKAXJ+xR0F0GQ6fx0fQE7onCHFb2cOE0QDcduG3phiVWb3ta + wNR5Fmxbm4wXPSCmpr222cLSxbQ3uA7RtL9uFNAW4dhzAziKqKHTe5/ZYMbq9pvNTuHT + 3J3jcOMat4gxGNc03EJvYmzShUEOOM+jrqqw5PPyFPugSE++IImG/5VXpLuEJ5Scg+uZ + NWwWu2or1nv3u9ShsCDAdR7MBP17UnpV5dRGhF3XzGZ3w6XLsNZK3i/i8AsYQQmwg3vB + IV6A== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to + :references:mime-version:content-transfer-encoding; + bh=sjNmqgcstGAxj0Xo8lZD7LTDFmxFM0Yqxj4VjUg9Qdw=; + b=qKHwpcfwF9facukQef6HgAyvqUs/GYAgOZJ/wICu5UWS07w2N3LOqQZaARkc11iYpu + OeLvtX5Glr6DxJtjXjEigBWeiI3xgnl0+gbJCF1A6N2c0rVvJKi2thyDJa1zwM12F8K3 + lIydjWaz+TKrW0DclnwFi16LM5wU/YX/YgqoWmdqM2gvqfgojNz62277My15evxCeoiD + M+uo7bm3QNnm2GRwynBS9S5hgWAHCdgEyKzPhVg/GIE9L0ufct+MJ1WqIha7SVbVlG4g + 7RkAUnIEhbVpRmYQXM5ILnV1dqaD7N+4xHcveqCoWSgCD2qThyO4C+V6XpJA5wS3Emh8 + vlFA== +X-Gm-Message-State: AOAM530ZNyrHdlIT42YWjuOs9q6OS58z7kHPvNflUcpx+Bp/A5iz/Hrv + uf3wqWDg8neJ6WX6nmj/D6KWNw== +X-Google-Smtp-Source: + ABdhPJw6BKQQGcIDZdsMlJ9qaiNbzUsRzwi01N8Yn7U0BfQ91i9Ou6kqCQL4toNmGMfOdugqMKV50A== +X-Received: by 2002:a05:6512:acc:: with SMTP id + n12mr14168468lfu.408.1620598865621; + Sun, 09 May 2021 15:21:05 -0700 (PDT) +Received: from localhost.localdomain + (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) + by smtp.gmail.com with ESMTPSA id + u12sm2978012ljo.82.2021.05.09.15.21.04 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Sun, 09 May 2021 15:21:05 -0700 (PDT) +From: Linus Walleij +To: Bjorn Helgaas +Cc: linux-pci@vger.kernel.org, Arnd Bergmann , + Imre Kaloz , + Krzysztof Halasa , + Zoltan HERPAI , + Raylynn Knight , + Linus Walleij , + devicetree@vger.kernel.org +Subject: [PATCH 3/4 v3] PCI: ixp4xx: Add device tree bindings for IXP4xx +Date: Mon, 10 May 2021 00:20:54 +0200 +Message-Id: <20210509222055.341945-4-linus.walleij@linaro.org> +X-Mailer: git-send-email 2.30.2 +In-Reply-To: <20210509222055.341945-1-linus.walleij@linaro.org> +References: <20210509222055.341945-1-linus.walleij@linaro.org> +MIME-Version: 1.0 +Precedence: bulk +List-ID: +X-Mailing-List: linux-pci@vger.kernel.org + +This adds device tree bindings for the Intel IXP4xx +PCI controller which can be used as both host and +option. + +Cc: devicetree@vger.kernel.org +Cc: Arnd Bergmann +Cc: Imre Kaloz +Cc: Krzysztof Halasa +Cc: Zoltan HERPAI +Cc: Raylynn Knight +Signed-off-by: Linus Walleij +Reviewed-by: Rob Herring +--- +ChangeLog v2->v3: +- Drop ranges, these are part of pci-bus.yaml +- Drop status = "disabled" on the node +ChangeLog v1->v2: +- Add the three controller interrupts to the binding. + +PCI maintainers: mainly looking for a review and ACK (if +you care about DT bindings) the patch will be merged +through ARM SoC. +--- + .../bindings/pci/intel,ixp4xx-pci.yaml | 100 ++++++++++++++++++ + 1 file changed, 100 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml + +diff --git a/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml +new file mode 100644 +index 000000000000..debfb54a8042 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml +@@ -0,0 +1,100 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Intel IXP4xx PCI controller ++ ++maintainers: ++ - Linus Walleij ++ ++description: PCI host controller found in the Intel IXP4xx SoC series. ++ ++allOf: ++ - $ref: /schemas/pci/pci-bus.yaml# ++ ++properties: ++ compatible: ++ items: ++ - enum: ++ - intel,ixp42x-pci ++ - intel,ixp43x-pci ++ description: The two supported variants are ixp42x and ixp43x, ++ though more variants may exist. ++ ++ reg: ++ items: ++ - description: IXP4xx-specific registers ++ ++ interrupts: ++ items: ++ - description: Main PCI interrupt ++ - description: PCI DMA interrupt 1 ++ - description: PCI DMA interrupt 2 ++ ++ ranges: ++ maxItems: 2 ++ description: Typically one memory range of 64MB and one IO ++ space range of 64KB. ++ ++ dma-ranges: ++ maxItems: 1 ++ description: The DMA range tells the PCI host which addresses ++ the RAM is at. It can map only 64MB so if the RAM is bigger ++ than 64MB the DMA access has to be restricted to these ++ addresses. ++ ++ "#interrupt-cells": true ++ ++ interrupt-map: true ++ ++ interrupt-map-mask: ++ items: ++ - const: 0xf800 ++ - const: 0 ++ - const: 0 ++ - const: 7 ++ ++required: ++ - compatible ++ - reg ++ - dma-ranges ++ - "#interrupt-cells" ++ - interrupt-map ++ - interrupt-map-mask ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ pci@c0000000 { ++ compatible = "intel,ixp43x-pci"; ++ reg = <0xc0000000 0x1000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ bus-range = <0x00 0xff>; ++ ++ ranges = ++ <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, ++ <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; ++ dma-ranges = ++ <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0xf800 0 0 7>; ++ interrupt-map = ++ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */ ++ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */ ++ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */ ++ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */ ++ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */ ++ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */ ++ <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */ ++ <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */ ++ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */ ++ <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */ ++ <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */ ++ <0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */ ++ }; + +From patchwork Sun May 9 22:20:55 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Linus Walleij +X-Patchwork-Id: 1475997 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org + (client-ip=23.128.96.18; helo=vger.kernel.org; + envelope-from=linux-pci-owner@vger.kernel.org; receiver=) +Authentication-Results: ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 + header.s=google header.b=dNbB4YJO; + dkim-atps=neutral +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by ozlabs.org (Postfix) with ESMTP id 4Fddtv292vz9tlN + for ; Mon, 10 May 2021 08:21:11 +1000 (AEST) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S229699AbhEIWWO (ORCPT ); + Sun, 9 May 2021 18:22:14 -0400 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47600 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S229847AbhEIWWN (ORCPT + ); Sun, 9 May 2021 18:22:13 -0400 +Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com + [IPv6:2a00:1450:4864:20::134]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76657C061573 + for ; Sun, 9 May 2021 15:21:08 -0700 (PDT) +Received: by mail-lf1-x134.google.com with SMTP id x20so20529051lfu.6 + for ; Sun, 09 May 2021 15:21:08 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=linaro.org; s=google; + h=from:to:cc:subject:date:message-id:in-reply-to:references + :mime-version:content-transfer-encoding; + bh=6FxZJIZJKsIXSdwmLwW0dcAjXO7AU+sUjkMzDxOe2zQ=; + b=dNbB4YJOWtRNhJm2wJweaJu9aYxZOM2fQ7lxGl8DC5V8DlItGRk2z+ApMZpVuyVVyr + aQWR+wrYP96QuP4elWugjIGZ7F/T0VuhSxIMEZLArr4D4+rL90s+GIRCZuA7iE8qSVCw + 6kNNUznDcB5FUIPajM7zM938PMVIlfI1r39GZK7MHpFnXEo51h53r8hbPnFmGN06XhpI + ccPVmXVL9G43jlFzEQQg0Q6vZOW8XqlJwILw3cQLu6A5kYmPIMAgy2wtlE4SgeKv5obp + vN39K9uKdPqwS9SDsg+rWmCFSk4YKLBadKW8gOXn0ob7wWnuoayB8G2m/4wYLajt4c9o + GFEg== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to + :references:mime-version:content-transfer-encoding; + bh=6FxZJIZJKsIXSdwmLwW0dcAjXO7AU+sUjkMzDxOe2zQ=; + b=l5ul/r0sOjlR/8YAxEbdFyFTEBMweKk74SPObV43bMdfHGidfoi9cRqeYKWHp9I+Yu + Pg7jTajBGOXAxYAjMGoTUF9XbqxPUixJEVQ6DG9mLlamxpeqnQkDqpmFzArsc6xZMeM/ + iQuaI7vOiqrPaWyFjFHgQJwBBYCqBnqRJoG5s2wCezNv6DkMp+l31EPZr8KV6DsXL+0Q + gzOBZW7rjmVxpDRimUIlVInQZOlA2vCf5VKWkvdn9HF4ZJcMnKS5x/NisQQwstxPgqtP + SRahIfGTyjQFCpUsGvlUuJFbf7/9bdfK5sw7b1S2YBcKqC5ggltF87XnFdDjjrkpD1om + t/ZQ== +X-Gm-Message-State: AOAM532pLFO1Euiz1u0BRgooHgFfEUG8sQqvfSZFWCMMg/c4DbFTF9YV + f1cXo0YvCu8VyEDFR7VaXRo6B9TBxftrig== +X-Google-Smtp-Source: + ABdhPJwsZG5hhkYgAVVyr3BgGn68+GmnJz5Nc0ymbw0PwuCzcgUHcQuJAhfrtNNK8UQUZHvpOfAQaA== +X-Received: by 2002:ac2:528f:: with SMTP id + q15mr15401765lfm.145.1620598866907; + Sun, 09 May 2021 15:21:06 -0700 (PDT) +Received: from localhost.localdomain + (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) + by smtp.gmail.com with ESMTPSA id + u12sm2978012ljo.82.2021.05.09.15.21.06 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Sun, 09 May 2021 15:21:06 -0700 (PDT) +From: Linus Walleij +To: Bjorn Helgaas +Cc: linux-pci@vger.kernel.org, Arnd Bergmann , + Imre Kaloz , + Krzysztof Halasa , + Zoltan HERPAI , + Raylynn Knight , + Linus Walleij +Subject: [PATCH 4/4 v3] PCI: ixp4xx: Add a new driver for IXP4xx +Date: Mon, 10 May 2021 00:20:55 +0200 +Message-Id: <20210509222055.341945-5-linus.walleij@linaro.org> +X-Mailer: git-send-email 2.30.2 +In-Reply-To: <20210509222055.341945-1-linus.walleij@linaro.org> +References: <20210509222055.341945-1-linus.walleij@linaro.org> +MIME-Version: 1.0 +Precedence: bulk +List-ID: +X-Mailing-List: linux-pci@vger.kernel.org + +This adds a new PCI controller driver for the Intel IXP4xx +(IX425, IXP435 etc), based on the XScale microarchitecture. + +This replaces the old driver in arch/arm/mach-ixp4xx/common-pci.c +which utilized the ARM-specific BIOS32 PCI framework, +and all parameterization for such things as memory and +IO space as well as interrupt swizzling is done from the +device tree. + +The __raw_writel() and __raw_readl() are used for accessing +the PCI controller for the same reason that these accessors +are used in the timer, IRQ and GPIO drivers: the platform +will alter its address bus pattern based on whether the +system is booted in big- or little-endian mode. For this +reason all register on IXP4xx must always be accessed in +native (CPU) endianness. + +This driver supports 64MB of PCI memory space, but not the +indirect access of 1GB that is available in the old driver. +We can address that later if and only if there are users +that need all 1GB of PCI address space. + +Tested by booting the NSLU2, attaching a USB stick, mounting +and browsing the drive. + +Cc: Arnd Bergmann +Cc: Imre Kaloz +Cc: Krzysztof Halasa +Cc: Zoltan HERPAI +Cc: Raylynn Knight +Signed-off-by: Linus Walleij +--- +ChangeLog v2->v3: +- Fix a double assignment of .suppress_bind_attrs +ChangeLog v1->v2: +- Add dependencies on ARM to Kconfig since we are regisering + and ARM only abort handler. +- Create ixp4xx_readl() and ixp4xx_writel() static inline + wrappers around the __raw_readl() and __raw_writel() calls + with a big comment block explaining what is going on. +- Drop bus pointer from state container, it is only used in + probe() +- Use pci_host_probe() and get rid of a lot of boilerplate. +- Use builtin_driver_probe() and explain why this is + necessary with comments in the code. + +PCI maintainers: looking for review or ACK to take this +driver throght ARM SoC since it is dependent on the first +patches in the series in order not to cause build +problems. +--- + MAINTAINERS | 6 + + drivers/pci/controller/Kconfig | 8 + + drivers/pci/controller/Makefile | 1 + + drivers/pci/controller/pci-ixp4xx.c | 705 ++++++++++++++++++++++++++++ + 4 files changed, 720 insertions(+) + create mode 100644 drivers/pci/controller/pci-ixp4xx.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index d92f85ca831d..ae220d52a6d7 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -13692,6 +13692,12 @@ S: Maintained + F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt + F: drivers/pci/controller/dwc/*imx6* + ++PCI DRIVER FOR INTEL IXP4XX ++M: Linus Walleij ++S: Maintained ++F: Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml ++F: drivers/pci/controller/pci-ixp4xx.c ++ + PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD) + M: Jonathan Derrick + L: linux-pci@vger.kernel.org +diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig +index 5aa8977d7b0f..b9a9a05be0e7 100644 +--- a/drivers/pci/controller/Kconfig ++++ b/drivers/pci/controller/Kconfig +@@ -37,6 +37,14 @@ config PCI_FTPCI100 + depends on OF + default ARCH_GEMINI + ++config PCI_IXP4XX ++ bool "Intel IXP4xx PCI controller" ++ depends on ARM && OF ++ default ARCH_IXP4XX ++ help ++ Say Y here if you want support for the PCI host controller found ++ in the Intel IXP4xx XScale-based network processor SoC. ++ + config PCI_TEGRA + bool "NVIDIA Tegra PCIe controller" + depends on ARCH_TEGRA || COMPILE_TEST +diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile +index e4559f2182f2..f81f3fd7a9e0 100644 +--- a/drivers/pci/controller/Makefile ++++ b/drivers/pci/controller/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_PCIE_CADENCE) += cadence/ + obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o ++obj-$(CONFIG_PCI_IXP4XX) += pci-ixp4xx.o + obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o + obj-$(CONFIG_PCI_HYPERV_INTERFACE) += pci-hyperv-intf.o + obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o +diff --git a/drivers/pci/controller/pci-ixp4xx.c b/drivers/pci/controller/pci-ixp4xx.c +new file mode 100644 +index 000000000000..c6912fd630b4 +--- /dev/null ++++ b/drivers/pci/controller/pci-ixp4xx.c +@@ -0,0 +1,705 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Support for Intel IXP4xx PCI host controller ++ * ++ * Copyright (C) 2017 Linus Walleij ++ * ++ * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver ++ * Copyright (C) 2002 Intel Corporation ++ * Copyright (C) 2003 Greg Ungerer ++ * Copyright (C) 2003-2004 MontaVista Software, Inc. ++ * Copyright (C) 2005 Deepak Saxena ++ * Copyright (C) 2005 Alessandro Zummo ++ * ++ * TODO: ++ * - Test IO-space access ++ * - DMA support ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Register offsets */ ++#define IXP4XX_PCI_NP_AD 0x00 ++#define IXP4XX_PCI_NP_CBE 0x04 ++#define IXP4XX_PCI_NP_WDATA 0x08 ++#define IXP4XX_PCI_NP_RDATA 0x0c ++#define IXP4XX_PCI_CRP_AD_CBE 0x10 ++#define IXP4XX_PCI_CRP_WDATA 0x14 ++#define IXP4XX_PCI_CRP_RDATA 0x18 ++#define IXP4XX_PCI_CSR 0x1c ++#define IXP4XX_PCI_ISR 0x20 ++#define IXP4XX_PCI_INTEN 0x24 ++#define IXP4XX_PCI_DMACTRL 0x28 ++#define IXP4XX_PCI_AHBMEMBASE 0x2c ++#define IXP4XX_PCI_AHBIOBASE 0x30 ++#define IXP4XX_PCI_PCIMEMBASE 0x34 ++#define IXP4XX_PCI_AHBDOORBELL 0x38 ++#define IXP4XX_PCI_PCIDOORBELL 0x3C ++#define IXP4XX_PCI_ATPDMA0_AHBADDR 0x40 ++#define IXP4XX_PCI_ATPDMA0_PCIADDR 0x44 ++#define IXP4XX_PCI_ATPDMA0_LENADDR 0x48 ++#define IXP4XX_PCI_ATPDMA1_AHBADDR 0x4C ++#define IXP4XX_PCI_ATPDMA1_PCIADDR 0x50 ++#define IXP4XX_PCI_ATPDMA1_LENADDR 0x54 ++ ++/* CSR bit definitions */ ++#define IXP4XX_PCI_CSR_HOST BIT(0) ++#define IXP4XX_PCI_CSR_ARBEN BIT(1) ++#define IXP4XX_PCI_CSR_ADS BIT(2) ++#define IXP4XX_PCI_CSR_PDS BIT(3) ++#define IXP4XX_PCI_CSR_ABE BIT(4) ++#define IXP4XX_PCI_CSR_DBT BIT(5) ++#define IXP4XX_PCI_CSR_ASE BIT(8) ++#define IXP4XX_PCI_CSR_IC BIT(15) ++#define IXP4XX_PCI_CSR_PRST BIT(16) ++ ++/* ISR (Interrupt status) Register bit definitions */ ++#define IXP4XX_PCI_ISR_PSE BIT(0) ++#define IXP4XX_PCI_ISR_PFE BIT(1) ++#define IXP4XX_PCI_ISR_PPE BIT(2) ++#define IXP4XX_PCI_ISR_AHBE BIT(3) ++#define IXP4XX_PCI_ISR_APDC BIT(4) ++#define IXP4XX_PCI_ISR_PADC BIT(5) ++#define IXP4XX_PCI_ISR_ADB BIT(6) ++#define IXP4XX_PCI_ISR_PDB BIT(7) ++ ++/* INTEN (Interrupt Enable) Register bit definitions */ ++#define IXP4XX_PCI_INTEN_PSE BIT(0) ++#define IXP4XX_PCI_INTEN_PFE BIT(1) ++#define IXP4XX_PCI_INTEN_PPE BIT(2) ++#define IXP4XX_PCI_INTEN_AHBE BIT(3) ++#define IXP4XX_PCI_INTEN_APDC BIT(4) ++#define IXP4XX_PCI_INTEN_PADC BIT(5) ++#define IXP4XX_PCI_INTEN_ADB BIT(6) ++#define IXP4XX_PCI_INTEN_PDB BIT(7) ++ ++/* Shift value for byte enable on NP cmd/byte enable register */ ++#define IXP4XX_PCI_NP_CBE_BESL 4 ++ ++/* PCI commands supported by NP access unit */ ++#define NP_CMD_IOREAD 0x2 ++#define NP_CMD_IOWRITE 0x3 ++#define NP_CMD_CONFIGREAD 0xa ++#define NP_CMD_CONFIGWRITE 0xb ++#define NP_CMD_MEMREAD 0x6 ++#define NP_CMD_MEMWRITE 0x7 ++ ++/* Constants for CRP access into local config space */ ++#define CRP_AD_CBE_BESL 20 ++#define CRP_AD_CBE_WRITE 0x00010000 ++ ++/* Special PCI configuration space registers for this controller */ ++#define IXP4XX_PCI_RTOTTO 0x40 ++ ++struct ixp4xx_pci { ++ struct device *dev; ++ void __iomem *base; ++ raw_spinlock_t lock; /* Protects bus writes */ ++ bool errata_hammer; ++ bool host_mode; ++}; ++ ++/* ++ * The IXP4xx has a peculiar address bus that will change the ++ * byte order on SoC peripherals depending on whether the device ++ * operates in big endian or little endian mode. That means that ++ * readl() and writel() that always use little-endian access ++ * will not work for SoC peripherals such as the PCI controller ++ * when used in big endian mode. The accesses to the individual ++ * PCI devices on the other hand, are always little-endian and ++ * can use readl() and writel(). ++ * ++ * For local AHB bus access we need to use __raw_[readl|writel]() ++ * to make sure that we access the SoC devices in the CPU native ++ * endianness. ++ */ ++static inline u32 ixp4xx_readl(struct ixp4xx_pci *p, u32 reg) ++{ ++ return __raw_readl(p->base + reg); ++} ++ ++static inline void ixp4xx_writel(struct ixp4xx_pci *p, u32 reg, u32 val) ++{ ++ __raw_writel(val, p->base + reg); ++} ++ ++static int ixp4xx_pci_check_master_abort(struct ixp4xx_pci *p) ++{ ++ u32 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); ++ ++ if (isr & IXP4XX_PCI_ISR_PFE) { ++ /* Make sure the master abort bit is reset */ ++ ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); ++ dev_dbg(p->dev, "master abort detected\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int ixp4xx_pci_read(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data) ++{ ++ unsigned long flags; ++ int ret; ++ ++ raw_spin_lock_irqsave(&p->lock, flags); ++ ++ ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); ++ ++ if (p->errata_hammer) { ++ int i; ++ ++ /* ++ * PCI workaround - only works if NP PCI space reads have ++ * no side effects. Hammer the register and read twice 8 ++ * times. last one will be good. ++ */ ++ for (i = 0; i < 8; i++) { ++ ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); ++ *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); ++ *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); ++ } ++ } else { ++ ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); ++ *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); ++ } ++ ++ /* Check for master abort */ ++ ret = ixp4xx_pci_check_master_abort(p); ++ ++ raw_spin_unlock_irqrestore(&p->lock, flags); ++ return ret; ++} ++ ++static int ixp4xx_pci_write(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data) ++{ ++ unsigned long flags; ++ int ret; ++ ++ raw_spin_lock_irqsave(&p->lock, flags); ++ ++ ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); ++ ++ /* Set up the write */ ++ ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); ++ ++ /* Execute the write by writing to NP_WDATA */ ++ ixp4xx_writel(p, IXP4XX_PCI_NP_WDATA, data); ++ ++ /* Check for master abort */ ++ ret = ixp4xx_pci_check_master_abort(p); ++ ++ raw_spin_unlock_irqrestore(&p->lock, flags); ++ return ret; ++} ++ ++static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) ++{ ++ u32 addr; ++ ++ if (!bus_num) { ++ /* type 0 */ ++ addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | ++ (where & ~3); ++ } else { ++ /* type 1 */ ++ addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | ++ ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1; ++ } ++ return addr; ++} ++ ++/* ++ * CRP functions are "Controller Configuration Port" accesses ++ * initiated from within this driver itself to read/write PCI ++ * control information in the config space. ++ */ ++static u32 ixp4xx_crp_byte_lane_enable_bits(u32 n, int size) ++{ ++ if (size == 1) ++ return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; ++ if (size == 2) ++ return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; ++ if (size == 4) ++ return 0; ++ return 0xffffffff; ++} ++ ++static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size, ++ u32 *value) ++{ ++ unsigned long flags; ++ u32 n, cmd, val; ++ ++ n = where % 4; ++ cmd = where & ~3; ++ ++ dev_dbg(p->dev, "%s from %d size %d cmd %08x\n", ++ __func__, where, size, cmd); ++ ++ raw_spin_lock_irqsave(&p->lock, flags); ++ ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); ++ val = ixp4xx_readl(p, IXP4XX_PCI_CRP_RDATA); ++ raw_spin_unlock_irqrestore(&p->lock, flags); ++ ++ val >>= (8*n); ++ switch (size) { ++ case 1: ++ val &= U8_MAX; ++ dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); ++ break; ++ case 2: ++ val &= U16_MAX; ++ dev_dbg(p->dev, "%s read word %04x\n", __func__, val); ++ break; ++ case 4: ++ val &= U32_MAX; ++ dev_dbg(p->dev, "%s read long %08x\n", __func__, val); ++ break; ++ default: ++ /* Should not happen */ ++ dev_err(p->dev, "%s illegal size\n", __func__); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } ++ *value = val; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size, ++ u32 value) ++{ ++ unsigned long flags; ++ u32 n, cmd, val; ++ ++ n = where % 4; ++ cmd = ixp4xx_crp_byte_lane_enable_bits(n, size); ++ if (cmd == 0xffffffff) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ cmd |= where & ~3; ++ cmd |= CRP_AD_CBE_WRITE; ++ ++ val = value << (8*n); ++ ++ dev_dbg(p->dev, "%s to %d size %d cmd %08x val %08x\n", ++ __func__, where, size, cmd, val); ++ ++ raw_spin_lock_irqsave(&p->lock, flags); ++ ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); ++ ixp4xx_writel(p, IXP4XX_PCI_CRP_WDATA, val); ++ raw_spin_unlock_irqrestore(&p->lock, flags); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++/* ++ * Then follows the functions that read and write from the common ++ * PCI configuration space. ++ */ ++ ++static u32 ixp4xx_byte_lane_enable_bits(u32 n, int size) ++{ ++ if (size == 1) ++ return (0xf & ~BIT(n)) << 4; ++ if (size == 2) ++ return (0xf & ~(BIT(n) | BIT(n+1))) << 4; ++ if (size == 4) ++ return 0; ++ return 0xffffffff; ++} ++ ++static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *value) ++{ ++ struct ixp4xx_pci *p = bus->sysdata; ++ u32 n, addr, val, cmd; ++ u8 bus_num = bus->number; ++ int ret; ++ ++ *value = 0xffffffff; ++ n = where % 4; ++ cmd = ixp4xx_byte_lane_enable_bits(n, size); ++ if (cmd == 0xffffffff) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ addr = ixp4xx_config_addr(bus_num, devfn, where); ++ cmd |= NP_CMD_CONFIGREAD; ++ dev_dbg(p->dev, "read_config from %d size %d dev %d:%d:%d address: %08x cmd: %08x\n", ++ where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); ++ ++ ret = ixp4xx_pci_read(p, addr, cmd, &val); ++ if (ret) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ val >>= (8*n); ++ switch (size) { ++ case 1: ++ val &= U8_MAX; ++ dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); ++ break; ++ case 2: ++ val &= U16_MAX; ++ dev_dbg(p->dev, "%s read word %04x\n", __func__, val); ++ break; ++ case 4: ++ val &= U32_MAX; ++ dev_dbg(p->dev, "%s read long %08x\n", __func__, val); ++ break; ++ default: ++ /* Should not happen */ ++ dev_err(p->dev, "%s illegal size\n", __func__); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } ++ *value = val; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ struct ixp4xx_pci *p = bus->sysdata; ++ u32 n, addr, val, cmd; ++ u8 bus_num = bus->number; ++ int ret; ++ ++ n = where % 4; ++ cmd = ixp4xx_byte_lane_enable_bits(n, size); ++ if (cmd == 0xffffffff) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ addr = ixp4xx_config_addr(bus_num, devfn, where); ++ cmd |= NP_CMD_CONFIGWRITE; ++ val = value << (8*n); ++ ++ dev_dbg(p->dev, "write_config_byte %#x to %d size %d dev %d:%d:%d addr: %08x cmd %08x\n", ++ value, where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); ++ ++ ret = ixp4xx_pci_write(p, addr, cmd, val); ++ if (ret) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static struct pci_ops ixp4xx_pci_ops = { ++ .read = ixp4xx_pci_read_config, ++ .write = ixp4xx_pci_write_config, ++}; ++ ++static u32 ixp4xx_pci_addr_to_64mconf(phys_addr_t addr) ++{ ++ u8 base; ++ ++ base = ((addr & 0xff000000) >> 24); ++ return (base << 24) | ((base + 1) << 16) ++ | ((base + 2) << 8) | (base + 3); ++} ++ ++static int ixp4xx_pci_parse_map_ranges(struct ixp4xx_pci *p) ++{ ++ struct device *dev = p->dev; ++ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); ++ struct resource_entry *win; ++ struct resource *res; ++ phys_addr_t addr; ++ ++ win = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); ++ if (win) { ++ u32 pcimembase; ++ ++ res = win->res; ++ addr = res->start - win->offset; ++ ++ if (res->flags & IORESOURCE_PREFETCH) ++ res->name = "IXP4xx PCI PRE-MEM"; ++ else ++ res->name = "IXP4xx PCI NON-PRE-MEM"; ++ ++ dev_dbg(dev, "%s window %pR, bus addr %pa\n", ++ res->name, res, &addr); ++ if (resource_size(res) != SZ_64M) { ++ dev_err(dev, "memory range is not 64MB\n"); ++ return -EINVAL; ++ } ++ ++ pcimembase = ixp4xx_pci_addr_to_64mconf(addr); ++ /* Commit configuration */ ++ ixp4xx_writel(p, IXP4XX_PCI_PCIMEMBASE, pcimembase); ++ } else { ++ dev_err(dev, "no AHB memory mapping defined\n"); ++ } ++ ++ win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); ++ if (win) { ++ res = win->res; ++ ++ addr = pci_pio_to_address(res->start); ++ if (addr & 0xff) { ++ dev_err(dev, "IO mem at uneven address: %pa\n", &addr); ++ return -EINVAL; ++ } ++ ++ res->name = "IXP4xx PCI IO MEM"; ++ /* ++ * Setup I/O space location for PCI->AHB access, the ++ * upper 24 bits of the address goes into the lower ++ * 24 bits of this register. ++ */ ++ ixp4xx_writel(p, IXP4XX_PCI_AHBIOBASE, (addr >> 8)); ++ } else { ++ dev_info(dev, "no IO space AHB memory mapping defined\n"); ++ } ++ ++ return 0; ++} ++ ++static int ixp4xx_pci_parse_map_dma_ranges(struct ixp4xx_pci *p) ++{ ++ struct device *dev = p->dev; ++ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); ++ struct resource_entry *win; ++ struct resource *res; ++ phys_addr_t addr; ++ u32 ahbmembase; ++ ++ win = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM); ++ if (win) { ++ res = win->res; ++ addr = res->start - win->offset; ++ ++ if (resource_size(res) != SZ_64M) { ++ dev_err(dev, "DMA memory range is not 64MB\n"); ++ return -EINVAL; ++ } ++ ++ dev_dbg(dev, "DMA MEM BASE: %pa\n", &addr); ++ /* ++ * 4 PCI-to-AHB windows of 16 MB each, write the 8 high bits ++ * into each byte of the PCI_AHBMEMBASE register. ++ */ ++ ahbmembase = ixp4xx_pci_addr_to_64mconf(addr); ++ /* Commit AHB membase */ ++ ixp4xx_writel(p, IXP4XX_PCI_AHBMEMBASE, ahbmembase); ++ } else { ++ dev_err(dev, "no DMA memory range defined\n"); ++ } ++ ++ return 0; ++} ++ ++/* Only used to get context for abort handling */ ++static struct ixp4xx_pci *ixp4xx_pci_abort_singleton; ++ ++static int ixp4xx_pci_abort_handler(unsigned long addr, unsigned int fsr, ++ struct pt_regs *regs) ++{ ++ struct ixp4xx_pci *p = ixp4xx_pci_abort_singleton; ++ u32 isr, status; ++ int ret; ++ ++ isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); ++ ret = ixp4xx_crp_read_config(p, PCI_STATUS, 2, &status); ++ if (ret) { ++ dev_err(p->dev, "unable to read abort status\n"); ++ return -EINVAL; ++ } ++ ++ dev_err(p->dev, ++ "PCI: abort_handler addr = %#lx, isr = %#x, status = %#x\n", ++ addr, isr, status); ++ ++ /* Make sure the Master Abort bit is reset */ ++ ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); ++ status |= PCI_STATUS_REC_MASTER_ABORT; ++ ret = ixp4xx_crp_write_config(p, PCI_STATUS, 2, status); ++ if (ret) ++ dev_err(p->dev, "unable to clear abort status bit\n"); ++ ++ /* ++ * If it was an imprecise abort, then we need to correct the ++ * return address to be _after_ the instruction. ++ */ ++ if (fsr & (1 << 10)) { ++ dev_err(p->dev, "imprecise abort\n"); ++ regs->ARM_pc += 4; ++ } ++ ++ return 0; ++} ++ ++static int __init ixp4xx_pci_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct ixp4xx_pci *p; ++ struct pci_host_bridge *host; ++ int ret; ++ u32 val; ++ phys_addr_t addr; ++ u32 basereg[4] = { ++ PCI_BASE_ADDRESS_0, ++ PCI_BASE_ADDRESS_1, ++ PCI_BASE_ADDRESS_2, ++ PCI_BASE_ADDRESS_3, ++ }; ++ int i; ++ ++ host = devm_pci_alloc_host_bridge(dev, sizeof(*p)); ++ if (!host) ++ return -ENOMEM; ++ ++ host->ops = &ixp4xx_pci_ops; ++ p = pci_host_bridge_priv(host); ++ host->sysdata = p; ++ p->dev = dev; ++ raw_spin_lock_init(&p->lock); ++ dev_set_drvdata(dev, p); ++ ++ /* ++ * Set up quirk for erratic behaviour in the 42x variant ++ * when accessing config space. ++ */ ++ if (of_device_is_compatible(np, "intel,ixp42x-pci")) { ++ p->errata_hammer = true; ++ dev_info(dev, "activate hammering errata\n"); ++ } ++ ++ p->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(p->base)) ++ return PTR_ERR(p->base); ++ ++ val = ixp4xx_readl(p, IXP4XX_PCI_CSR); ++ p->host_mode = !!(val & IXP4XX_PCI_CSR_HOST); ++ dev_info(dev, "controller is in %s mode\n", ++ p->host_mode ? "host" : "option"); ++ ++ /* Hook in our fault handler for PCI errors */ ++ ixp4xx_pci_abort_singleton = p; ++ hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0, ++ "imprecise external abort"); ++ ++ ret = ixp4xx_pci_parse_map_ranges(p); ++ if (ret) ++ return ret; ++ ++ ret = ixp4xx_pci_parse_map_dma_ranges(p); ++ if (ret) ++ return ret; ++ ++ /* This is only configured in host mode */ ++ if (p->host_mode) { ++ addr = __pa(PAGE_OFFSET); ++ /* This is a noop (0x00) but explains what is going on */ ++ addr |= PCI_BASE_ADDRESS_SPACE_MEMORY; ++ ++ for (i = 0; i < 4; i++) { ++ /* Write this directly into the config space */ ++ ret = ixp4xx_crp_write_config(p, basereg[i], 4, addr); ++ if (ret) ++ dev_err(dev, "failed to set up PCI_BASE_ADDRESS_%d\n", i); ++ else ++ dev_info(dev, "set PCI_BASE_ADDR_%d to %pa\n", i, &addr); ++ addr += SZ_16M; ++ } ++ ++ /* ++ * Enable CSR window at 64 MiB to allow PCI masters to continue ++ * prefetching past the 64 MiB boundary, if all AHB to PCI windows ++ * are consecutive. ++ */ ++ ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_4, 4, addr); ++ if (ret) ++ dev_err(dev, "failed to set up PCI_BASE_ADDRESS_4\n"); ++ else ++ dev_info(dev, "set PCI_BASE_ADDR_4 to %pa\n", &addr); ++ ++ /* ++ * Put the IO memory at the very end of physical memory at ++ * 0xfffffc00. This is when the PCI is trying to access IO ++ * memory over AHB. ++ */ ++ addr = 0xfffffc00; ++ addr |= PCI_BASE_ADDRESS_SPACE_IO; ++ ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_5, 4, addr); ++ if (ret) ++ dev_err(dev, "failed to set up PCI_BASE_ADDRESS_5\n"); ++ else ++ dev_info(dev, "set PCI_BASE_ADDR_5 to %pa\n", &addr); ++ ++ /* ++ * Retry timeout to 0x80 ++ * Transfer ready timeout to 0xff ++ */ ++ ret = ixp4xx_crp_write_config(p, IXP4XX_PCI_RTOTTO, 4, ++ 0x000080ff); ++ if (ret) ++ dev_err(dev, "failed to set up TRDY limit\n"); ++ else ++ dev_info(dev, "set TRDY limit to 0x80ff\n"); ++ } ++ ++ /* Clear interrupts */ ++ val = IXP4XX_PCI_ISR_PSE | IXP4XX_PCI_ISR_PFE | IXP4XX_PCI_ISR_PPE | IXP4XX_PCI_ISR_AHBE; ++ ixp4xx_writel(p, IXP4XX_PCI_ISR, val); ++ ++ /* ++ * Set Initialize Complete in PCI Control Register: allow IXP4XX to ++ * respond to PCI configuration cycles. Specify that the AHB bus is ++ * operating in big endian mode. Set up byte lane swapping between ++ * little-endian PCI and the big-endian AHB bus. ++ */ ++ val = IXP4XX_PCI_CSR_IC | IXP4XX_PCI_CSR_ABE; ++#ifdef __ARMEB__ ++ val |= (IXP4XX_PCI_CSR_PDS | IXP4XX_PCI_CSR_ADS); ++#endif ++ ixp4xx_writel(p, IXP4XX_PCI_CSR, val); ++ ++ ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ++ if (ret) ++ dev_err(dev, "unable to initialize master and command memory\n"); ++ else ++ dev_info(dev, "initialized as master\n"); ++ ++ pci_host_probe(host); ++ ++ return 0; ++} ++ ++static const struct of_device_id ixp4xx_pci_of_match[] = { ++ { ++ .compatible = "intel,ixp42x-pci", ++ }, ++ { ++ .compatible = "intel,ixp43x-pci", ++ }, ++ {}, ++}; ++ ++/* ++ * This driver needs to be a builtin module with suppressed bind ++ * attributes since the probe() is initializing a hard exception ++ * handler and this can only be done from __init-tagged code ++ * sections. This module cannot be removed and inserted at all. ++ */ ++static struct platform_driver ixp4xx_pci_driver = { ++ .driver = { ++ .name = "ixp4xx-pci", ++ .suppress_bind_attrs = true, ++ .of_match_table = of_match_ptr(ixp4xx_pci_of_match), ++ }, ++}; ++/* ++ * This is the only way to have an __init tagged probe that does ++ * not cause link errors. ++ */ ++builtin_platform_driver_probe(ixp4xx_pci_driver, ixp4xx_pci_probe); diff --git a/target/linux/ixp4xx/patches-5.10/130-ARM-dts-ixp4xx_Create-a-proper-expansion-bus.patch b/target/linux/ixp4xx/patches-5.10/130-ARM-dts-ixp4xx_Create-a-proper-expansion-bus.patch new file mode 100644 index 0000000000..342a558eed --- /dev/null +++ b/target/linux/ixp4xx/patches-5.10/130-ARM-dts-ixp4xx_Create-a-proper-expansion-bus.patch @@ -0,0 +1,177 @@ +From patchwork Tue May 11 07:48:12 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Linus Walleij +X-Patchwork-Id: 12250773 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, + DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, + INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, + USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 83290C433ED + for ; + Tue, 11 May 2021 11:54:04 +0000 (UTC) +Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by mail.kernel.org (Postfix) with ESMTPS id E218061007 + for ; + Tue, 11 May 2021 11:54:03 +0000 (UTC) +DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E218061007 +Authentication-Results: mail.kernel.org; + dmarc=fail (p=none dis=none) header.from=linaro.org +Authentication-Results: mail.kernel.org; + spf=none + smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding + :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: + List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc:To:From: + Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender + :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; + bh=g765uKjvjkKfjO8LWNg1gK7jQ+Y0LmUhsLXiilecQF4=; b=XFxF/p+DHRwFseqlT1wJaRidsM + f4a5BU8CnoywivvY17CSSmiWZRp6oAtd4v42MsDSwVT+692hJZOv6/oUl+tUNCosVBtRXC25sUM6Z + iS61j0hrR7rrSU5HreqYL4l1dcPKhh4kT0kqjRSdhZZshIt3xUdjQmlFyq2fH2nvg/EI5E9iHyqJ7 + aGmWT2XhOdVnQkjdKI9qPSNGdRrYpG/zm+6fTpU9WG6k+NwH0f7ylvWxhcbZTNE1Lz7izvcLkPyhn + TlhBcx0hn78pO9Hx3xrgihJ/jfPDQtqsWbeAPJB7Zcx5ptKsfRebxX7gICkw6Rd2sglO9c9JBhue6 + KwwT+raA==; +Received: from localhost ([::1] helo=desiato.infradead.org) + by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) + id 1lgQwb-00HEDP-4v; Tue, 11 May 2021 11:52:57 +0000 +Received: from [2607:7c80:54:e::133] (helo=bombadil.infradead.org) + by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) + id 1lgN7t-00GXaU-R2 + for linux-arm-kernel@desiato.infradead.org; Tue, 11 May 2021 07:48:24 +0000 +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: + MIME-Version:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: + Content-ID:Content-Description:In-Reply-To:References; + bh=uiKzkDkAIIB8aIVLUtCNC9v++yEKPQ+huL0oPtIoFiU=; b=dwx5eJ0BZXvKN9g3IpVuFgQ/nQ + o1QaPLkK2NQFtSOI5gAj1l7NBfhsZT5vJ/Q3q/vnAkd9uoR6hsXScZtcdA/sgwjRxyyl9VugJ4C/v + UCNRgE39O6d0Cz6RRzP/JI/9q9ai/wBASnXe0PvJoZHRWI3gil1XNw8pzuvRboOXJoDhCC6ruJiUb + aYCvJpvnZNGvt0VdypUXdse/+cLxHYlgxxxMxHXQZEjEwbrVcF5rNspCVs2Pjiq7n9zzRbElqSQXx + Y7Wnv7OuPln14kfsVxIxrF7f6MJukj9mBBxTa+Od1/oLZbYJqmXHsHEQW4pCvBrX6G30kIwNUI2QZ + 0k5LDTcw==; +Received: from mail-lf1-x12c.google.com ([2a00:1450:4864:20::12c]) + by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) + id 1lgN7q-009N6i-Pm + for linux-arm-kernel@lists.infradead.org; Tue, 11 May 2021 07:48:20 +0000 +Received: by mail-lf1-x12c.google.com with SMTP id x19so27302622lfa.2 + for ; + Tue, 11 May 2021 00:48:17 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; + h=from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=uiKzkDkAIIB8aIVLUtCNC9v++yEKPQ+huL0oPtIoFiU=; + b=xd8lQqOgF4BPgdJAxHeAbrYTihLfDqyzCy9Np2NfWhXII/t6VxYMfYfPih6gWmfyfR + 2lk70h32l2/6mbbJzjyvCQWRDnH9ALoer3FuAtICFBI1fCsePkm9H1A1HxnnWFaAy9AE + zswFD0qAabrpQK+JfKYLtCJip/e5x9rwvhDxWRtq0DfyegIRR5ORBa5Nsz61Hv3vAZOh + 3bOtsrNR2Z8gXfDn3o+Js4TMhTsqIOxSXk0D4FMtCasWSC03nCOdglImOgbGVRqiL6Lh + 6ylzRSO4BB7biy+fdlVS97M/YLEu9u4nt/va7miIU+KRzwa8iJ9an9g/1CDgivmbMJSb + CH6Q== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=uiKzkDkAIIB8aIVLUtCNC9v++yEKPQ+huL0oPtIoFiU=; + b=Ey4BwXhoVLPCRrElbGu6o2HhFA0EsLLCE0BNz7PFCeWzqSVWEY0dFOLKSAV5XO3td/ + HviV8trdIdoHzG1dLZ/yOC6qjOGU+fmD1UGJSHhnj/DjJTvZGNP88hKsbnRTkkzDFey8 + 9cRL1YP9YGsB6kINWwEYyHh5S6HIVAMDAzlIthrM/pLbg6QVOY+1oOIL5A6XA8a+grRQ + kTSRbTbsAA7xRtqM7X7ASQCjgU/8jhOaBDFAEtaRid0Z6/r667CwewBJ9LMaO6TTxIoO + mQM4MT+PiMv2FAWfIoKcPbFtAGjbFv//T9Mlp+HehTuuuOr6uB060mcqi/uSiWIwzMxM + wj1w== +X-Gm-Message-State: AOAM531AvP4reKClqBnIfiG8Cmx/KVXOhqMIHahz/SSDCW5rAbbCex74 + y9++aUkXP3RycT0pMBXFtIotR1NoFhdfvQ== +X-Google-Smtp-Source: + ABdhPJwgnsNg6Zb73boGFz0PGlPUFmfUifBg+Wdn9u5M0TPtC8ZIoy0cYi4mauxGYAqYTeOmtb/sBg== +X-Received: by 2002:a05:6512:3619:: with SMTP id + f25mr17425959lfs.399.1620719296375; + Tue, 11 May 2021 00:48:16 -0700 (PDT) +Received: from localhost.localdomain + (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) + by smtp.gmail.com with ESMTPSA id e8sm3609866ljk.7.2021.05.11.00.48.15 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Tue, 11 May 2021 00:48:16 -0700 (PDT) +From: Linus Walleij +To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , + Krzysztof Halasa +Cc: Linus Walleij , Zoltan HERPAI , + Raylynn Knight +Subject: [PATCH] ARM: dts: ixp4xx: Create a proper expansion bus +Date: Tue, 11 May 2021 09:48:12 +0200 +Message-Id: <20210511074812.686159-1-linus.walleij@linaro.org> +X-Mailer: git-send-email 2.30.2 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20210511_004818_880101_953A10A6 +X-CRM114-Status: GOOD ( 15.01 ) +/bin/ln: failed to access + 'reaver_cache/texts/20210511_004818_880101_953A10A6': No such file or + directory +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20210511_004818_880101_953A10A6 +X-CRM114-Status: GOOD ( 11.49 ) +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +The IXP4xx expansion bus is 24 bits (256 MB) that is memory +mapped between 0x50000000-0x5fffffff usin a set of chip +selects. The size of the windows is 16 or 32MB defined by +the boot loader system configuration at runtime. + +Create a rudimentary simple-bus and move the flash memories +to the expansion bus, inside the SoC. + +Cc: Zoltan HERPAI +Cc: Raylynn Knight +Signed-off-by: Linus Walleij +--- + .../boot/dts/intel-ixp42x-linksys-nslu2.dts | 34 +++++++++++-------- + .../dts/intel-ixp43x-gateworks-gw2358.dts | 30 ++++++++-------- + arch/arm/boot/dts/intel-ixp4xx.dtsi | 13 +++++++ + 3 files changed, 49 insertions(+), 28 deletions(-) + +diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi +index 17a712e9d582..2848f8c543af 100644 +--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi ++++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi +@@ -14,6 +14,19 @@ soc { + compatible = "simple-bus"; + interrupt-parent = <&intcon>; + ++ /* ++ * The IXP4xx expansion bus is a set of 16 or 32MB ++ * windows in the 256MB space from 0x50000000 to ++ * 0x5fffffff. ++ */ ++ bus@50000000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x00000000 0x50000000 0x10000000>; ++ dma-ranges = <0x00000000 0x50000000 0x10000000>; ++ }; ++ + qmgr: queue-manager@60000000 { + compatible = "intel,ixp4xx-ahb-queue-manager"; + reg = <0x60000000 0x4000>; diff --git a/target/linux/ixp4xx/patches-5.10/600-skb_avoid_dmabounce.patch b/target/linux/ixp4xx/patches-5.10/600-skb_avoid_dmabounce.patch new file mode 100644 index 0000000000..80688a4c0a --- /dev/null +++ b/target/linux/ixp4xx/patches-5.10/600-skb_avoid_dmabounce.patch @@ -0,0 +1,23 @@ +--- a/net/core/skbuff.c ++++ b/net/core/skbuff.c +@@ -215,6 +215,9 @@ struct sk_buff *__alloc_skb(unsigned int + + if (sk_memalloc_socks() && (flags & SKB_ALLOC_RX)) + gfp_mask |= __GFP_MEMALLOC; ++#ifdef CONFIG_ARCH_IXP4XX ++ gfp_mask |= GFP_DMA; ++#endif + + /* Get the HEAD */ + skb = kmem_cache_alloc_node(cache, gfp_mask & ~__GFP_DMA, node); +@@ -1223,6 +1226,10 @@ int pskb_expand_head(struct sk_buff *skb + if (skb_shared(skb)) + BUG(); + ++#ifdef CONFIG_ARCH_IXP4XX ++ gfp_mask |= GFP_DMA; ++#endif ++ + size = SKB_DATA_ALIGN(size); + + if (skb_pfmemalloc(skb)) diff --git a/target/linux/ixp4xx/patches-5.10/900-scripts-Makefile-add-lpthread.patch b/target/linux/ixp4xx/patches-5.10/900-scripts-Makefile-add-lpthread.patch new file mode 100644 index 0000000000..a1ffc45f80 --- /dev/null +++ b/target/linux/ixp4xx/patches-5.10/900-scripts-Makefile-add-lpthread.patch @@ -0,0 +1,12 @@ +diff -ruN a/scripts/Makefile b/scripts/Makefile +--- a/scripts/Makefile 2021-05-21 17:43:33.989097196 +0200 ++++ b/scripts/Makefile 2021-05-21 11:41:14.174017561 +0200 +@@ -20,7 +20,7 @@ + HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS) + HOSTLDLIBS_sign-file = $(CRYPTO_LIBS) + HOSTCFLAGS_extract-cert.o = $(CRYPTO_CFLAGS) +-HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) ++HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) -lpthread + + ifdef CONFIG_UNWINDER_ORC + ifeq ($(ARCH),x86_64)