From: Robert Marko Date: Thu, 25 Sep 2025 20:44:10 +0000 (+0200) Subject: microchipsw: lan969x: add Microchip EV23X71A X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=5205c0c426073aed5912d2bf35f3a3b56670911e;p=openwrt%2Fstaging%2Fstintel.git microchipsw: lan969x: add Microchip EV23X71A Microchip EV23X71A is a LAN9696 based EVB. Specifications: * CPU: Microchip LAN9696 switch SoC * DRAM: 1GB DDR4 * Storage: * 2MB QSPI NOR * 4GB eMMC * Networking: * 24 x 10/100/1000 RJ45 via LAN8814 Quad PHY-s over QSGMII * 4 x 100/1000/2500/5000/10000 SFP+ ports * 1 x 10/100/1000 management RJ45 via LAN8840 PHY over RGMII (U-Boot too) * USB: 1 x USB2.0 Type-A * Management via USB-C (MCP2200): * UART @ 115200 baud * GPIO-s for bootstrap, reset and clock selection * DIP switch for boostrap configuration * LED-s: * 2 per networking port (Green and Yellow) * Green status LED * Yellow reset LED * Hard reset button * Power: * 12V DC barrel jack * 48/56V DC screw terminal * Selectable via toggle switch * PTP support: * Sync-E DPLL ZL30732B to generate the board required clocks * Two SMAs for PTP and two for Station clock inputs and outputs * Two ITU-T G.8275-compliant RS-422 interfaces for PTP applications * External PoE: * Option for PoE add-on, like EV14Y36A (IEEE 802.3af/at/bt Type 4 standard com-pliant) * Option for external CPU control via SPI and PCIe Installation instructions: 1. Connect to UART via the USB-C port 2. Connect the management port 3. Boot and interrupt U-Boot 4. TFTP the OpenWrt initramfs image and boot it 5. SCP the OpenWrt eMMC GPT image to a running OpenWrt initramfs to /tmp openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img.gz And decompress it via: gzip -d /tmp/openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img.gz 6. Wipe eMMC with: dd if=/dev/zero of=/dev/mmcblk0 bs=1M 7. Flash OpenWrt eMMC image with: dd if=/tmp/openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img of=/dev/mmcblk0 After a restart OpenWrt will boot, and then regular sysupgrade can be used for upgrades. Signed-off-by: Robert Marko --- diff --git a/config/Config-images.in b/config/Config-images.in index 9b04ddbeec..fcc5fa52cb 100644 --- a/config/Config-images.in +++ b/config/Config-images.in @@ -336,7 +336,7 @@ menu "Target Images" int "Root filesystem partition size (in MiB)" depends on USES_ROOTFS_PART || TARGET_ROOTFS_EXT4FS default 232 if TARGET_loongarch64 - default 448 if TARGET_mediatek + default 448 if TARGET_mediatek || TARGET_microchipsw default 104 help Select the root filesystem partition size. diff --git a/package/boot/arm-trusted-firmware-microchipsw/Makefile b/package/boot/arm-trusted-firmware-microchipsw/Makefile new file mode 100644 index 0000000000..fae462aa0b --- /dev/null +++ b/package/boot/arm-trusted-firmware-microchipsw/Makefile @@ -0,0 +1,78 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=arm-trusted-firmware-microchipsw +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL=https://github.com/microchip-ung/arm-trusted-firmware.git +PKG_SOURCE_DATE:=2024-08-13 +PKG_SOURCE_VERSION:=67fcfcab71f78ac7d4af834c37b29f8c98dd5ff1 +PKG_MIRROR_HASH:=777c68273e84028de77750f3fe8a1219b02f01d43ce35948893ac642d8eb10d7 + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/trusted-firmware-a.mk +include $(INCLUDE_DIR)/package.mk + +define Trusted-Firmware-A/Default + BUILD_TARGET:=microchipsw + TFA_IMAGE:=fip.bin fwu_fip.bin fwu.html +endef + +define Trusted-Firmware-A/ev23x71a + NAME:=Microchip EV23X71A + BUILD_SUBTARGET:=lan969x + BUILD_DEVICES:=microchip_ev23x71a + PLAT:=lan969x_a0 + DEPENDS:=+u-boot-ev23x71a +endef + +TFA_TARGETS:= ev23x71a + +MBEDTLS_NAME:=mbedtls +MBEDTLS_RELEASE:=2.28.10 +MBEDTLS_SOURCE:=$(MBEDTLS_NAME)-$(MBEDTLS_RELEASE).tar.zst + +define Download/mbedtls + FILE:=$(MBEDTLS_SOURCE) + PROTO:=git + URL:=https://github.com/Mbed-TLS/mbedtls.git + SOURCE_VERSION:=2fc8413bfcb51354c8e679141b17b3f1a5942561 + MIRROR_HASH:=40b94a76572ad1ca89738929ab81d6024f678f22691eb3bd633c076ac18a334a + SUBDIR:=$(MBEDTLS_NAME) +endef + +define Build/Prepare + # Download mbedtls + $(eval $(call Download,mbedtls)) + + $(call Build/Prepare/Default,) + + $(TAR) -C $(PKG_BUILD_DIR) -xf $(DL_DIR)/$(MBEDTLS_SOURCE) +endef + +# We must not pass OPENSSL_DIR as locally built mbedtls is used +define Build/Compile + +unset CC; \ + $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \ + CROSS_COMPILE=$(TARGET_CROSS) \ + $(if $(DTC),DTC="$(DTC)") \ + PLAT=$(PLAT) \ + BUILD_STRING="OpenWrt $(PKG_VERSION_PREFIX)$(PKG_VERSION)-$(PKG_RELEASE) ($(VARIANT))" \ + $(TFA_MAKE_FLAGS) +endef + +TFA_MAKE_FLAGS += \ + MBEDTLS_DIR=$(PKG_BUILD_DIR)/$(MBEDTLS_NAME) \ + BL33=$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.bin \ + KEY_ALG=ecdsa GENERATE_COT=1 TRUSTED_BOARD_BOOT=1 \ + all fip fwu_fip + +define Package/trusted-firmware-a/install + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/fip.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-fip.bin + $(CP) $(patsubst %,$(PKG_BUILD_DIR)/build/$(PLAT)/release/%,$(TFA_IMAGE)) $(1)/ +endef + +$(eval $(call BuildPackage/Trusted-Firmware-A)) diff --git a/package/boot/uboot-microchipsw/Makefile b/package/boot/uboot-microchipsw/Makefile new file mode 100644 index 0000000000..f727739276 --- /dev/null +++ b/package/boot/uboot-microchipsw/Makefile @@ -0,0 +1,37 @@ +include $(TOPDIR)/rules.mk + +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/microchip-ung/u-boot.git +PKG_SOURCE_DATE:=2025-09-22 +PKG_SOURCE_VERSION:=c1abab62a00a6b8f43f663a0a30dd0a7fd6a4e95 +PKG_MIRROR_HASH:=6405c426afd8bacbb4cc985da4ca1bd04b54a0d2aa3bb3ba8f7571dbe5913055 + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/u-boot.mk +include $(INCLUDE_DIR)/package.mk +include $(INCLUDE_DIR)/kernel.mk + +define U-Boot/Default + BUILD_TARGET:=microchipsw + HIDDEN:=1 + UBOOT_IMAGE:=u-boot.bin +endef + +define U-Boot/ev23x71a + NAME:=Microchip EV23X71A + BUILD_DEVICES:=microchip_ev23x71a + BUILD_SUBTARGET:=lan969x + UBOOT_CONFIG:=mchp_lan969x +endef + +UBOOT_TARGETS:= ev23x71a + +define Build/InstallDev + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE) +endef + +$(eval $(call BuildPackage/U-Boot)) diff --git a/package/boot/uboot-microchipsw/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-microchipsw/patches/200-cmd-add-imsz-and-imszb.patch new file mode 100644 index 0000000000..9872ccbf26 --- /dev/null +++ b/package/boot/uboot-microchipsw/patches/200-cmd-add-imsz-and-imszb.patch @@ -0,0 +1,139 @@ +--- a/cmd/bootm.c ++++ b/cmd/bootm.c +@@ -260,6 +260,76 @@ U_BOOT_CMD( + /* iminfo - print header info for a requested image */ + /*******************************************************************/ + #if defined(CONFIG_CMD_IMI) ++#define SECTOR_SHIFT 9 ++static int image_totalsize(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[], short int in_blocks) ++{ ++ ulong addr; ++ void *hdr; ++ uint32_t bsize, tsize = 0; ++ char buf[16]; ++ ++ if (argc >= 2) ++ addr = simple_strtoul(argv[1], NULL, 16); ++ else ++ addr = image_load_addr; ++ ++ hdr = (void *)map_sysmem(addr, 0); ++ ++ switch (genimg_get_format(hdr)) { ++ case IMAGE_FORMAT_LEGACY: ++ if(CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) ++ tsize = image_get_image_size(hdr); ++ break; ++ case IMAGE_FORMAT_FIT: ++ if(CONFIG_IS_ENABLED(FIT)) ++ tsize = fit_get_totalsize(hdr); ++ break; ++ } ++ ++ unmap_sysmem(hdr); ++ if (tsize == 0) ++ return 1; ++ ++ bsize = (tsize >> SECTOR_SHIFT) + ((tsize & ((1 << SECTOR_SHIFT) - 1))?1:0); ++ ++ if (!in_blocks) ++ snprintf(buf, sizeof(buf), "%x", tsize); ++ else ++ snprintf(buf, sizeof(buf), "%x", bsize); ++ ++ if (argc >= 3) ++ return env_set(argv[2], buf); ++ else ++ printf("%s\n", buf); ++ ++ return 0; ++} ++ ++static int do_imsz(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ return image_totalsize(cmdtp, flag, argc, argv, 0); ++} ++ ++static int do_imszb(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ return image_totalsize(cmdtp, flag, argc, argv, 1); ++} ++ ++U_BOOT_CMD( ++ imsz, CONFIG_SYS_MAXARGS, 1, do_imsz, ++ "get image total size (in bytes)", ++ "addr [maxhdrlen] [varname]\n" ++); ++ ++U_BOOT_CMD( ++ imszb, CONFIG_SYS_MAXARGS, 1, do_imszb, ++ "get image total size (in blocks)", ++ "addr [maxhdrlen] [varname]\n" ++); ++ + static int do_iminfo(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) + { +--- a/boot/image-fit.c ++++ b/boot/image-fit.c +@@ -2054,6 +2054,47 @@ static const char *fit_get_image_type_pr + return "unknown"; + } + ++size_t fit_get_totalsize(const void *fit) ++{ ++ int ret, ndepth, noffset, images_noffset; ++ size_t data_size, hdrsize, img_total, max_size = 0; ++ const void *data; ++ ++ ret = fdt_check_header(fit); ++ if (ret) { ++ debug("Wrong FIT format: not a flattened device tree (err=%d)\n", ++ ret); ++ return 0; ++ } ++ ++ hdrsize = fdt_totalsize(fit); ++ ++ /* take care of simple FIT with internal images */ ++ max_size = hdrsize; ++ ++ images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); ++ if (images_noffset < 0) ++ goto out; ++ ++ for (ndepth = 0, ++ noffset = fdt_next_node(fit, images_noffset, &ndepth); ++ (noffset >= 0) && (ndepth > 0); ++ noffset = fdt_next_node(fit, noffset, &ndepth)) { ++ if (ndepth == 1) { ++ ret = fit_image_get_data(fit, noffset, &data, &data_size); ++ if (ret) ++ goto out; ++ ++ img_total = data_size + (data - fit); ++ ++ max_size = (max_size > img_total) ? max_size : img_total; ++ } ++ } ++ ++out: ++ return max_size; ++} ++ + int fit_image_load(struct bootm_headers *images, ulong addr, + const char **fit_unamep, const char **fit_uname_configp, + int arch, int ph_type, int bootstage_id, +--- a/include/image.h ++++ b/include/image.h +@@ -1113,6 +1113,7 @@ int fit_parse_subimage(const char *spec, + ulong *addr, const char **image_name); + + int fit_get_subimage_count(const void *fit, int images_noffset); ++size_t fit_get_totalsize(const void *fit); + void fit_print_contents(const void *fit); + void fit_image_print(const void *fit, int noffset, const char *p); + diff --git a/package/boot/uboot-microchipsw/src/board/microchip/lan969x/lan969x.env b/package/boot/uboot-microchipsw/src/board/microchip/lan969x/lan969x.env new file mode 100644 index 0000000000..4ea48bca0c --- /dev/null +++ b/package/boot/uboot-microchipsw/src/board/microchip/lan969x/lan969x.env @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +fdt_high=0xffffffff +baudrate=115200 +bootdelay=3 +loadaddr=0x64000000 +bootargs=console=ttyAT0,115200 root=PARTLABEL=rootfs rootwait +mmc_read_kernel=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr $part_addr $image_size +boot_system=part start mmc 0 kernel part_addr && part size mmc 0 kernel part_size && run mmc_read_kernel && bootm +bootcmd=run boot_system diff --git a/target/linux/microchipsw/dts/lan9696-ev23x71a.dts b/target/linux/microchipsw/dts/lan9696-ev23x71a.dts new file mode 100644 index 0000000000..2ccc0345ac --- /dev/null +++ b/target/linux/microchipsw/dts/lan9696-ev23x71a.dts @@ -0,0 +1,787 @@ +/dts-v1/; + +#include +#include +#include "lan969x.dtsi" + +/ { + model = "Microchip EV23X71A"; + compatible = "microchip,ev23x71a", "microchip,lan969x"; + + aliases { + serial0 = &usart0; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 60 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c3>; + + mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH + &sgpio_out 0 2 GPIO_ACTIVE_HIGH + &sgpio_out 0 3 GPIO_ACTIVE_HIGH>; + idle-state = <0x8>; + + i2c_sfp0: i2c@0 { + reg = <0x0>; + }; + + i2c_sfp1: i2c@1 { + reg = <0x1>; + }; + + i2c_sfp2: i2c@2 { + reg = <0x2>; + }; + + i2c_sfp3: i2c@3 { + reg = <0x3>; + }; + + i2c_poe: i2c@7 { + reg = <0x7>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status: led-status { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio 61 GPIO_ACTIVE_LOW>; + }; + + led-sfp1-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp1-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp2-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp2-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp3-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp3-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp4-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp4-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>, + <&sgpio_out 1 3 GPIO_ACTIVE_LOW>; + }; + + sfp0: sfp0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp0>; + tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>; + }; + + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>; + }; + + sfp3: sfp3 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&usart0 { + pinctrl-0 = <&fc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flx2 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&spi2 { + pinctrl-0 = <&fc2_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&fc3_pins>; + pinctrl-names = "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; +}; + +&gpio { + emmc_sd_pins: emmc-sd-pins { + /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */ + pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17", + "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21", + "GPIO_22", "GPIO_23", "GPIO_24"; + function = "emmc_sd"; + }; + + fan_pins: fan-pins { + pins = "GPIO_25", "GPIO_26"; + function = "fan"; + }; + + fc0_pins: fc0-pins { + pins = "GPIO_3", "GPIO_4"; + function = "fc"; + }; + + fc2_pins: fc2-pins { + pins = "GPIO_64", "GPIO_65", "GPIO_66"; + function = "fc"; + }; + + fc3_pins: fc3-pins { + pins = "GPIO_55", "GPIO_56"; + function = "fc"; + }; + + mdio_pins: mdio-pins { + pins = "GPIO_9", "GPIO_10"; + function = "miim"; + }; + + mdio_irq_pins: mdio-irq-pins { + pins = "GPIO_11"; + function = "miim_irq"; + }; + + sgpio_pins: sgpio-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8"; + function = "sgpio_a"; + }; + + usb_ulpi_pins: usb-ulpi-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33", + "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", + "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41"; + function = "usb_ulpi"; + }; + + usb_rst_pins: usb-rst-pins { + pins = "GPIO_12"; + function = "usb2phy_rst"; + }; + + usb_over_pins: usb-over-pins { + pins = "GPIO_13"; + function = "usb_over_detect"; + }; + + usb_power_pins: usb-power-pins { + pins = "GPIO_1"; + function = "usb_power"; + }; + + ptp_out_pins: ptp-out-pins { + pins = "GPIO_58"; + function = "ptpsync_4"; + }; + + ptp_ext_pins: ptp-ext-pins { + pins = "GPIO_59"; + function = "ptpsync_5"; + }; +}; + +&qspi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + #address-cells = <1>; + #size-cells = <1>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; + +&sdmmc0 { + pinctrl-0 = <&emmc_sd_pins>; + pinctrl-names = "default"; + max-frequency = <100000000>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + disable-wp; + status = "okay"; +}; + +&tmon { + pinctrl-0 = <&fan_pins>; + pinctrl-names = "default"; +}; + +&mdio0 { + pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>; + status = "okay"; + + phy3: phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy4: phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy5: phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy7: phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy8: phy@8 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <8>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy9: phy@9 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <9>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy10: phy@10 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <10>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy11: phy@11 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <11>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy12: phy@12 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <12>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy13: phy@13 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <13>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy14: phy@14 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <14>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy15: phy@15 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <15>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy16: phy@16 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <16>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy17: phy@17 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <17>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy18: phy@18 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <18>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy19: phy@19 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <19>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy20: phy@20 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <20>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy21: phy@21 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <21>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy22: phy@22 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <22>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy23: phy@23 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <23>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy24: phy@24 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <24>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy25: phy@25 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <25>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy26: phy@26 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <26>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy27: phy@27 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <27>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_pins>; + pinctrl-names = "default"; + + microchip,sgpio-port-ranges = <0 1>, <6 9>; + status = "okay"; + + gpio@0 { + ngpios = <128>; + }; + gpio@1 { + ngpios = <128>; + }; +}; + +&switch { + pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>; + pinctrl-names = "default"; + + status = "okay"; + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + microchip,bandwidth = <1000>; + phy-handle = <&phy4>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + }; + + port1: port@1 { + reg = <1>; + microchip,bandwidth = <1000>; + phy-handle = <&phy5>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + }; + + port2: port@2 { + reg = <2>; + microchip,bandwidth = <1000>; + phy-handle = <&phy6>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + }; + + port3: port@3 { + reg = <3>; + microchip,bandwidth = <1000>; + phy-handle = <&phy7>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + }; + + port4: port@4 { + reg = <4>; + microchip,bandwidth = <1000>; + phy-handle = <&phy8>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + }; + + port5: port@5 { + reg = <5>; + microchip,bandwidth = <1000>; + phy-handle = <&phy9>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + }; + + port6: port@6 { + reg = <6>; + microchip,bandwidth = <1000>; + phy-handle = <&phy10>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + }; + + port7: port@7 { + reg = <7>; + microchip,bandwidth = <1000>; + phy-handle = <&phy11>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + }; + + port8: port@8 { + reg = <8>; + microchip,bandwidth = <1000>; + phy-handle = <&phy12>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + }; + + port9: port@9 { + reg = <9>; + microchip,bandwidth = <1000>; + phy-handle = <&phy13>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + }; + + port10: port@10 { + reg = <10>; + microchip,bandwidth = <1000>; + phy-handle = <&phy14>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + }; + + port11: port@11 { + reg = <11>; + microchip,bandwidth = <1000>; + phy-handle = <&phy15>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + }; + + port12: port@12 { + reg = <12>; + microchip,bandwidth = <1000>; + phy-handle = <&phy16>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + }; + + port13: port@13 { + reg = <13>; + microchip,bandwidth = <1000>; + phy-handle = <&phy17>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + }; + + port14: port@14 { + reg = <14>; + microchip,bandwidth = <1000>; + phy-handle = <&phy18>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + }; + + port15: port@15 { + reg = <15>; + microchip,bandwidth = <1000>; + phy-handle = <&phy19>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + }; + + port16: port@16 { + reg = <16>; + microchip,bandwidth = <1000>; + phy-handle = <&phy20>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + }; + + port17: port@17 { + reg = <17>; + microchip,bandwidth = <1000>; + phy-handle = <&phy21>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + }; + + port18: port@18 { + reg = <18>; + microchip,bandwidth = <1000>; + phy-handle = <&phy22>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + }; + + port19: port@19 { + reg = <19>; + microchip,bandwidth = <1000>; + phy-handle = <&phy23>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + }; + + port20: port@20 { + reg = <20>; + microchip,bandwidth = <1000>; + phy-handle = <&phy24>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + }; + + port21: port@21 { + reg = <21>; + microchip,bandwidth = <1000>; + phy-handle = <&phy25>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + }; + + port22: port@22 { + reg = <22>; + microchip,bandwidth = <1000>; + phy-handle = <&phy26>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + }; + + port23: port@23 { + reg = <23>; + microchip,bandwidth = <1000>; + phy-handle = <&phy27>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + }; + + port24: port@24 { + reg = <24>; + microchip,bandwidth = <10000>; + phys = <&serdes 6>; + phy-mode = "10gbase-r"; + sfp = <&sfp0>; + microchip,sd-sgpio = <24>; + managed = "in-band-status"; + }; + + port25: port@25 { + reg = <25>; + microchip,bandwidth = <10000>; + phys = <&serdes 7>; + phy-mode = "10gbase-r"; + sfp = <&sfp1>; + microchip,sd-sgpio = <28>; + managed = "in-band-status"; + }; + + port26: port@26 { + reg = <26>; + microchip,bandwidth = <10000>; + phys = <&serdes 8>; + phy-mode = "10gbase-r"; + sfp = <&sfp2>; + microchip,sd-sgpio = <32>; + managed = "in-band-status"; + }; + + port27: port@27 { + reg = <27>; + microchip,bandwidth = <10000>; + phys = <&serdes 9>; + phy-mode = "10gbase-r"; + sfp = <&sfp3>; + microchip,sd-sgpio = <36>; + managed = "in-band-status"; + }; + + port29: port@29 { + reg = <29>; + microchip,bandwidth = <1000>; + phys = <&serdes 11>; + phy-handle = <&phy3>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <1000>; + tx-internal-delay-ps = <1000>; + }; + }; +}; + +&usb { + status = "okay"; + pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>; + pinctrl-names = "default"; +}; diff --git a/target/linux/microchipsw/image/Makefile b/target/linux/microchipsw/image/Makefile index 4bee818578..2922c366c0 100644 --- a/target/linux/microchipsw/image/Makefile +++ b/target/linux/microchipsw/image/Makefile @@ -18,4 +18,6 @@ define Device/FitImage KERNEL_NAME := Image endef +include $(SUBTARGET).mk + $(eval $(call BuildImage)) diff --git a/target/linux/microchipsw/image/lan969x.mk b/target/linux/microchipsw/image/lan969x.mk new file mode 100644 index 0000000000..04b681b017 --- /dev/null +++ b/target/linux/microchipsw/image/lan969x.mk @@ -0,0 +1,41 @@ +define Build/lan969x-fip + cat $(STAGING_DIR_IMAGE)/$1-fip.bin >> $@ +endef + +define Build/lan969x-gpt-emmc + cp $@ $@.tmp 2>/dev/null || true + ptgen -g -o $@.tmp -a 1 -l 1024 \ + -t 0x83 -N fip -r -p 8M@1M \ + -t 0x83 -N fip.bak -r -p 8M@9M \ + -t 0x83 -N Env -r -p 2M@17M \ + $(if $(findstring flash,$1), \ + -t 0x2e -N kernel -p $(CONFIG_TARGET_KERNEL_PARTSIZE)M@19M \ + -t 0x2e -N rootfs -p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M + ) + cat $@.tmp >> $@ + rm $@.tmp +endef + +define Build/append-kernel-part + dd if=$(IMAGE_KERNEL) bs=$(CONFIG_TARGET_KERNEL_PARTSIZE)M conv=sync >> $@ +endef + +define Device/microchip_ev23x71a + $(call Device/FitImage) + DEVICE_VENDOR := Microchip + DEVICE_MODEL := EV23X71A + SOC := lan9696 + DEVICE_PACKAGES := kmod-i2c-mux-gpio + IMAGES += emmc-atf-gpt.gz emmc-gpt.img.gz + IMAGE/emmc-atf-gpt.gz := lan969x-gpt-emmc |\ + pad-to 1M | lan969x-fip ev23x71a |\ + pad-to 9M | lan969x-fip ev23x71a |\ + gzip + IMAGE/emmc-gpt.img.gz := lan969x-gpt-emmc flash |\ + pad-to 1M | lan969x-fip ev23x71a |\ + pad-to 9M | lan969x-fip ev23x71a |\ + pad-to 19M | append-kernel-part |\ + append-rootfs |\ + gzip +endef +TARGET_DEVICES += microchip_ev23x71a diff --git a/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds b/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds new file mode 100644 index 0000000000..6e3da9e0ec --- /dev/null +++ b/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds @@ -0,0 +1,23 @@ + +. /lib/functions/uci-defaults.sh + +board_config_update + +board=$(board_name) + +case "$board" in +microchip,ev23x71a) + ucidef_set_led_netdev "sfp1-link" "SFP1-LINK" "green:lan-0" "eth24" "link" + ucidef_set_led_netdev "sfp1-traffic" "SFP1-TRAFFIC" "yellow:lan-0" "eth24" "tx rx" + ucidef_set_led_netdev "sfp2-link" "SFP2-LINK" "green:lan-1" "eth25" "link" + ucidef_set_led_netdev "sfp2-traffic" "SFP2-TRAFFIC" "yellow:lan-1" "eth25" "tx rx" + ucidef_set_led_netdev "sfp3-link" "SFP3-LINK" "green:lan-2" "eth26" "link" + ucidef_set_led_netdev "sfp3-traffic" "SFP3-TRAFFIC" "yellow:lan-2" "eth26" "tx rx" + ucidef_set_led_netdev "sfp4-link" "SFP4-LINK" "green:lan-3" "eth27" "link" + ucidef_set_led_netdev "sfp4-traffic" "SFP4-TRAFFIC" "yellow:lan-3" "eth27" "tx rx" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network b/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network new file mode 100644 index 0000000000..be28e56192 --- /dev/null +++ b/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network @@ -0,0 +1,25 @@ + +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh + +lan969x_setup_interfaces() +{ + local board="$1" + + case "$board" in + microchip,ev23x71a) + lan_list=$(ls -1 -v -d /sys/class/net/eth* | xargs -n1 basename | xargs) + ucidef_set_interface_lan "$lan_list" + ;; + *) + echo "Unsupported hardware. Network interfaces not initialized" + ;; + esac +} + +board_config_update +board=$(board_name) +lan969x_setup_interfaces $board +board_config_flush + +exit 0 diff --git a/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh b/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000000..a3d4b488f0 --- /dev/null +++ b/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh @@ -0,0 +1,31 @@ +PART_NAME=firmware +REQUIRE_IMAGE_METADATA=1 + +RAMFS_COPY_BIN='fw_printenv fw_setenv' +RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock' + +platform_check_image() { + return 0; +} + +platform_do_upgrade() { + case "$(board_name)" in + microchip,ev23x71a) + CI_KERNPART="kernel" + CI_ROOTPART="rootfs" + emmc_do_upgrade "$1" + ;; + *) + default_do_upgrade "$1" + ;; + esac +} + +platform_copy_config() { + case "$(board_name)" in + microchip,ev23x71a) + emmc_copy_config + ;; + esac + return 0; +} diff --git a/target/linux/microchipsw/lan969x/config-default b/target/linux/microchipsw/lan969x/config-default index fd4b7424e8..620c2e61ce 100644 --- a/target/linux/microchipsw/lan969x/config-default +++ b/target/linux/microchipsw/lan969x/config-default @@ -44,6 +44,7 @@ CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_PSCI_FW=y CONFIG_AT_XDMAC=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BLK_DEV_LOOP=y CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y CONFIG_CC_HAVE_SHADOW_CALL_STACK=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y diff --git a/target/linux/microchipsw/lan969x/target.mk b/target/linux/microchipsw/lan969x/target.mk index dce697a82d..bc77e62a5b 100644 --- a/target/linux/microchipsw/lan969x/target.mk +++ b/target/linux/microchipsw/lan969x/target.mk @@ -1,7 +1,10 @@ SUBTARGET:=lan969x BOARDNAME:=Microchip LAN969x switches +FEATURES+= boot-part rootfs-part -DEFAULT_PACKAGES += kmod-usb3 kmod-usb-dwc3 +DEFAULT_PACKAGES += kmod-usb3 kmod-usb-dwc3 \ + e2fsprogs kmod-fs-ext4 losetup \ + kmod-fs-f2fs f2fs-tools define Target/Description Build firmware images for Microchip LAN969x switch based boards.