From: Tianling Shen Date: Mon, 1 Sep 2025 09:48:18 +0000 (+0800) Subject: rockchip: refresh and reorder patches X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=3735317acceabfdebd541145f5169add421f2efd;p=openwrt%2Fstaging%2Fnbd.git rockchip: refresh and reorder patches - Replace NanoPi R3S patch with upstreamed version - Merge NanoPC T6 mmc fixes patches - Reorder patches to start from 001 Signed-off-by: Tianling Shen Link: https://github.com/openwrt/openwrt/pull/19925 Signed-off-by: Hauke Mehrtens --- diff --git a/target/linux/rockchip/patches-6.12/000-01-v6.13-arm64-dts-rockchip-Split-up-RK3588-s-PCIe-pinctrls.patch b/target/linux/rockchip/patches-6.12/000-01-v6.13-arm64-dts-rockchip-Split-up-RK3588-s-PCIe-pinctrls.patch deleted file mode 100644 index 9a58adf4cd..0000000000 --- a/target/linux/rockchip/patches-6.12/000-01-v6.13-arm64-dts-rockchip-Split-up-RK3588-s-PCIe-pinctrls.patch +++ /dev/null @@ -1,444 +0,0 @@ -From 4294e32111781b3de4d73b944cbd1bc1662a9a7a Mon Sep 17 00:00:00 2001 -From: Sam Edwards -Date: Wed, 11 Sep 2024 19:50:30 -0700 -Subject: arm64: dts: rockchip: Split up RK3588's PCIe pinctrls - -These pinctrls manage the low-speed PCIe signals: -- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to - request that external clock-generation circuitry provide a clock. -- PERST#: An input on the RK3588 in EP mode, used to detect a reset - signal from the RC. In RC mode, the hardware does not use this signal: - Linux itself generates it by putting the pin in GPIO mode. -- WAKE#: In EP mode, this is an output; in RC mode, this is an input. - -Each of these signals serves a distinct purpose, and more importantly, -PERST# should not be muxed when the RK3588 is in the RC role. Bundling -them together in pinctrl groups prevents proper use: indeed, almost none -of the current board-specific .dts files make any use of them. -(Exception: Rock 5A recently had a patch land that misuses _pins; this - patch corrects that.) - -However, on some RK3588 boards, the PCIe 3 controller will indefinitely -stall the boot if CLKREQ# is not muxed (details in the next patch). -This patch unbundles the signals to allow them to be used. - -Signed-off-by: Sam Edwards -Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi -@@ -1612,23 +1612,43 @@ - - pcie20x1 { - /omit-if-no-ref/ -- pcie20x1m0_pins: pcie20x1m0-pins { -+ pcie20x1m0_clkreqn: pcie20x1m0-clkreqn { - rockchip,pins = - /* pcie20x1_2_clkreqn_m0 */ -- <3 RK_PC7 4 &pcfg_pull_none>, -+ <3 RK_PC7 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie20x1m0_perstn: pcie20x1m0-perstn { -+ rockchip,pins = - /* pcie20x1_2_perstn_m0 */ -- <3 RK_PD1 4 &pcfg_pull_none>, -+ <3 RK_PD1 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie20x1m0_waken: pcie20x1m0-waken { -+ rockchip,pins = - /* pcie20x1_2_waken_m0 */ - <3 RK_PD0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ -- pcie20x1m1_pins: pcie20x1m1-pins { -+ pcie20x1m1_clkreqn: pcie20x1m1-clkreqn { - rockchip,pins = - /* pcie20x1_2_clkreqn_m1 */ -- <4 RK_PB7 4 &pcfg_pull_none>, -+ <4 RK_PB7 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie20x1m1_perstn: pcie20x1m1-perstn { -+ rockchip,pins = - /* pcie20x1_2_perstn_m1 */ -- <4 RK_PC1 4 &pcfg_pull_none>, -+ <4 RK_PC1 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie20x1m1_waken: pcie20x1m1-waken { -+ rockchip,pins = - /* pcie20x1_2_waken_m1 */ - <4 RK_PC0 4 &pcfg_pull_none>; - }; -@@ -1654,52 +1674,127 @@ - - pcie30x1 { - /omit-if-no-ref/ -- pcie30x1m0_pins: pcie30x1m0-pins { -+ pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn { - rockchip,pins = - /* pcie30x1_0_clkreqn_m0 */ -- <0 RK_PC0 12 &pcfg_pull_none>, -+ <0 RK_PC0 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m0_0_perstn: pcie30x1m0-0-perstn { -+ rockchip,pins = - /* pcie30x1_0_perstn_m0 */ -- <0 RK_PC5 12 &pcfg_pull_none>, -+ <0 RK_PC5 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m0_0_waken: pcie30x1m0-0-waken { -+ rockchip,pins = - /* pcie30x1_0_waken_m0 */ -- <0 RK_PC4 12 &pcfg_pull_none>, -+ <0 RK_PC4 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn { -+ rockchip,pins = - /* pcie30x1_1_clkreqn_m0 */ -- <0 RK_PB5 12 &pcfg_pull_none>, -+ <0 RK_PB5 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m0_1_perstn: pcie30x1m0-1-perstn { -+ rockchip,pins = - /* pcie30x1_1_perstn_m0 */ -- <0 RK_PB7 12 &pcfg_pull_none>, -+ <0 RK_PB7 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m0_1_waken: pcie30x1m0-1-waken { -+ rockchip,pins = - /* pcie30x1_1_waken_m0 */ - <0 RK_PB6 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ -- pcie30x1m1_pins: pcie30x1m1-pins { -+ pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn { - rockchip,pins = - /* pcie30x1_0_clkreqn_m1 */ -- <4 RK_PA3 4 &pcfg_pull_none>, -+ <4 RK_PA3 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m1_0_perstn: pcie30x1m1-0-perstn { -+ rockchip,pins = - /* pcie30x1_0_perstn_m1 */ -- <4 RK_PA5 4 &pcfg_pull_none>, -+ <4 RK_PA5 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m1_0_waken: pcie30x1m1-0-waken { -+ rockchip,pins = - /* pcie30x1_0_waken_m1 */ -- <4 RK_PA4 4 &pcfg_pull_none>, -+ <4 RK_PA4 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn { -+ rockchip,pins = - /* pcie30x1_1_clkreqn_m1 */ -- <4 RK_PA0 4 &pcfg_pull_none>, -+ <4 RK_PA0 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m1_1_perstn: pcie30x1m1-1-perstn { -+ rockchip,pins = - /* pcie30x1_1_perstn_m1 */ -- <4 RK_PA2 4 &pcfg_pull_none>, -+ <4 RK_PA2 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m1_1_waken: pcie30x1m1-1-waken { -+ rockchip,pins = - /* pcie30x1_1_waken_m1 */ - <4 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ -- pcie30x1m2_pins: pcie30x1m2-pins { -+ pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn { - rockchip,pins = - /* pcie30x1_0_clkreqn_m2 */ -- <1 RK_PB5 4 &pcfg_pull_none>, -+ <1 RK_PB5 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m2_0_perstn: pcie30x1m2-0-perstn { -+ rockchip,pins = - /* pcie30x1_0_perstn_m2 */ -- <1 RK_PB4 4 &pcfg_pull_none>, -+ <1 RK_PB4 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m2_0_waken: pcie30x1m2-0-waken { -+ rockchip,pins = - /* pcie30x1_0_waken_m2 */ -- <1 RK_PB3 4 &pcfg_pull_none>, -+ <1 RK_PB3 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn { -+ rockchip,pins = - /* pcie30x1_1_clkreqn_m2 */ -- <1 RK_PA0 4 &pcfg_pull_none>, -+ <1 RK_PA0 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m2_1_perstn: pcie30x1m2-1-perstn { -+ rockchip,pins = - /* pcie30x1_1_perstn_m2 */ -- <1 RK_PA7 4 &pcfg_pull_none>, -+ <1 RK_PA7 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x1m2_1_waken: pcie30x1m2-1-waken { -+ rockchip,pins = - /* pcie30x1_1_waken_m2 */ - <1 RK_PA1 4 &pcfg_pull_none>; - }; -@@ -1721,45 +1816,85 @@ - - pcie30x2 { - /omit-if-no-ref/ -- pcie30x2m0_pins: pcie30x2m0-pins { -+ pcie30x2m0_clkreqn: pcie30x2m0-clkreqn { - rockchip,pins = - /* pcie30x2_clkreqn_m0 */ -- <0 RK_PD1 12 &pcfg_pull_none>, -+ <0 RK_PD1 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m0_perstn: pcie30x2m0-perstn { -+ rockchip,pins = - /* pcie30x2_perstn_m0 */ -- <0 RK_PD4 12 &pcfg_pull_none>, -+ <0 RK_PD4 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m0_waken: pcie30x2m0-waken { -+ rockchip,pins = - /* pcie30x2_waken_m0 */ - <0 RK_PD2 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ -- pcie30x2m1_pins: pcie30x2m1-pins { -+ pcie30x2m1_clkreqn: pcie30x2m1-clkreqn { - rockchip,pins = - /* pcie30x2_clkreqn_m1 */ -- <4 RK_PA6 4 &pcfg_pull_none>, -+ <4 RK_PA6 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m1_perstn: pcie30x2m1-perstn { -+ rockchip,pins = - /* pcie30x2_perstn_m1 */ -- <4 RK_PB0 4 &pcfg_pull_none>, -+ <4 RK_PB0 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m1_waken: pcie30x2m1-waken { -+ rockchip,pins = - /* pcie30x2_waken_m1 */ - <4 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ -- pcie30x2m2_pins: pcie30x2m2-pins { -+ pcie30x2m2_clkreqn: pcie30x2m2-clkreqn { - rockchip,pins = - /* pcie30x2_clkreqn_m2 */ -- <3 RK_PD2 4 &pcfg_pull_none>, -+ <3 RK_PD2 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m2_perstn: pcie30x2m2-perstn { -+ rockchip,pins = - /* pcie30x2_perstn_m2 */ -- <3 RK_PD4 4 &pcfg_pull_none>, -+ <3 RK_PD4 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m2_waken: pcie30x2m2-waken { -+ rockchip,pins = - /* pcie30x2_waken_m2 */ - <3 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ -- pcie30x2m3_pins: pcie30x2m3-pins { -+ pcie30x2m3_clkreqn: pcie30x2m3-clkreqn { - rockchip,pins = - /* pcie30x2_clkreqn_m3 */ -- <1 RK_PD7 4 &pcfg_pull_none>, -+ <1 RK_PD7 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m3_perstn: pcie30x2m3-perstn { -+ rockchip,pins = - /* pcie30x2_perstn_m3 */ -- <1 RK_PB7 4 &pcfg_pull_none>, -+ <1 RK_PB7 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x2m3_waken: pcie30x2m3-waken { -+ rockchip,pins = - /* pcie30x2_waken_m3 */ - <1 RK_PB6 4 &pcfg_pull_none>; - }; -@@ -1774,45 +1909,85 @@ - - pcie30x4 { - /omit-if-no-ref/ -- pcie30x4m0_pins: pcie30x4m0-pins { -+ pcie30x4m0_clkreqn: pcie30x4m0-clkreqn { - rockchip,pins = - /* pcie30x4_clkreqn_m0 */ -- <0 RK_PC6 12 &pcfg_pull_none>, -+ <0 RK_PC6 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m0_perstn: pcie30x4m0-perstn { -+ rockchip,pins = - /* pcie30x4_perstn_m0 */ -- <0 RK_PD0 12 &pcfg_pull_none>, -+ <0 RK_PD0 12 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m0_waken: pcie30x4m0-waken { -+ rockchip,pins = - /* pcie30x4_waken_m0 */ - <0 RK_PC7 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ -- pcie30x4m1_pins: pcie30x4m1-pins { -+ pcie30x4m1_clkreqn: pcie30x4m1-clkreqn { - rockchip,pins = - /* pcie30x4_clkreqn_m1 */ -- <4 RK_PB4 4 &pcfg_pull_none>, -+ <4 RK_PB4 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m1_perstn: pcie30x4m1-perstn { -+ rockchip,pins = - /* pcie30x4_perstn_m1 */ -- <4 RK_PB6 4 &pcfg_pull_none>, -+ <4 RK_PB6 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m1_waken: pcie30x4m1-waken { -+ rockchip,pins = - /* pcie30x4_waken_m1 */ - <4 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ -- pcie30x4m2_pins: pcie30x4m2-pins { -+ pcie30x4m2_clkreqn: pcie30x4m2-clkreqn { - rockchip,pins = - /* pcie30x4_clkreqn_m2 */ -- <3 RK_PC4 4 &pcfg_pull_none>, -+ <3 RK_PC4 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m2_perstn: pcie30x4m2-perstn { -+ rockchip,pins = - /* pcie30x4_perstn_m2 */ -- <3 RK_PC6 4 &pcfg_pull_none>, -+ <3 RK_PC6 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m2_waken: pcie30x4m2-waken { -+ rockchip,pins = - /* pcie30x4_waken_m2 */ - <3 RK_PC5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ -- pcie30x4m3_pins: pcie30x4m3-pins { -+ pcie30x4m3_clkreqn: pcie30x4m3-clkreqn { - rockchip,pins = - /* pcie30x4_clkreqn_m3 */ -- <1 RK_PB0 4 &pcfg_pull_none>, -+ <1 RK_PB0 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m3_perstn: pcie30x4m3-perstn { -+ rockchip,pins = - /* pcie30x4_perstn_m3 */ -- <1 RK_PB2 4 &pcfg_pull_none>, -+ <1 RK_PB2 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4m3_waken: pcie30x4m3-waken { -+ rockchip,pins = - /* pcie30x4_waken_m3 */ - <1 RK_PB1 4 &pcfg_pull_none>; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -310,7 +310,7 @@ - }; - - &pcie2x1l2 { -- pinctrl-0 = <&pcie20x1m0_pins>; -+ pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>; - pinctrl-names = "default"; - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_wf>; -@@ -328,6 +328,10 @@ - pow_en: pow-en { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ -+ pcie2_reset: pcie2-reset { -+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; - }; - - power { diff --git a/target/linux/rockchip/patches-6.12/000-02-v6.13-arm64-dts-rockchip-Add-HDMI0-node-to-rk3588.patch b/target/linux/rockchip/patches-6.12/000-02-v6.13-arm64-dts-rockchip-Add-HDMI0-node-to-rk3588.patch deleted file mode 100644 index 135e79342f..0000000000 --- a/target/linux/rockchip/patches-6.12/000-02-v6.13-arm64-dts-rockchip-Add-HDMI0-node-to-rk3588.patch +++ /dev/null @@ -1,61 +0,0 @@ -From d7bb71e69f58c1b3665a9f926bf8d3855111bf8e Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 19 Oct 2024 13:12:10 +0300 -Subject: arm64: dts: rockchip: Add HDMI0 node to rk3588 - -Add support for the HDMI0 output port found on RK3588 SoC. - -Signed-off-by: Cristian Ciocaltea -Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1369,6 +1369,47 @@ - status = "disabled"; - }; - -+ hdmi0: hdmi@fde80000 { -+ compatible = "rockchip,rk3588-dw-hdmi-qp"; -+ reg = <0x0 0xfde80000 0x0 0x20000>; -+ clocks = <&cru PCLK_HDMITX0>, -+ <&cru CLK_HDMITX0_EARC>, -+ <&cru CLK_HDMITX0_REF>, -+ <&cru MCLK_I2S5_8CH_TX>, -+ <&cru CLK_HDMIHDP0>, -+ <&cru HCLK_VO1>; -+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "avp", "cec", "earc", "main", "hpd"; -+ phys = <&hdptxphy_hdmi0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd -+ &hdmim0_tx0_scl &hdmim0_tx0_sda>; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; -+ reset-names = "ref", "hdp"; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vo-grf = <&vo1_grf>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hdmi0_in: port@0 { -+ reg = <0>; -+ }; -+ -+ hdmi0_out: port@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ - qos_gpu_m0: qos@fdf35000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35000 0x0 0x20>; diff --git a/target/linux/rockchip/patches-6.12/000-03-v6.15-arm64-dts-rockchip-Use-dma-noncoherent-in-base-RK358.patch b/target/linux/rockchip/patches-6.12/000-03-v6.15-arm64-dts-rockchip-Use-dma-noncoherent-in-base-RK358.patch deleted file mode 100644 index 0f3a564413..0000000000 --- a/target/linux/rockchip/patches-6.12/000-03-v6.15-arm64-dts-rockchip-Use-dma-noncoherent-in-base-RK358.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 33b561eb66f1e271f2899e103c857d20425076f4 Mon Sep 17 00:00:00 2001 -From: Dragan Simic -Date: Wed, 8 Jan 2025 05:26:45 +0100 -Subject: arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi - -The preferred way to denote hardware with non-coherent DMA is to use the -"dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS -levels, [1] instead of relying on the compatibles to handle hardware errata, -in this case the Rockchip 3588001 errata. [2] - -Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi, -which also goes along with adding initial support for the Rockchip RK3582 SoC -variant, with its separate compatible. [2][3] - -[1] Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml -[2] https://lore.kernel.org/linux-rockchip/86msgoozqa.wl-maz@kernel.org/ -[3] https://lore.kernel.org/linux-rockchip/20241222030355.2246-4-naoki@radxa.com/ - -Cc: Marc Zyngier -Cc: FUKAUMI Naoki -Acked-by: Marc Zyngier -Signed-off-by: Dragan Simic -Link: https://lore.kernel.org/r/fa1a672dae3644bb3caa58f03216d0ca349db88b.1736279094.git.dsimic@manjaro.org -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -2020,6 +2020,7 @@ - <0x0 0xfe680000 0 0x100000>; /* GICR */ - interrupts = ; - interrupt-controller; -+ dma-noncoherent; - mbi-alias = <0x0 0xfe610000>; - mbi-ranges = <424 56>; - msi-controller; -@@ -2031,6 +2032,7 @@ - its0: msi-controller@fe640000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe640000 0x0 0x20000>; -+ dma-noncoherent; - msi-controller; - #msi-cells = <1>; - }; -@@ -2038,6 +2040,7 @@ - its1: msi-controller@fe660000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe660000 0x0 0x20000>; -+ dma-noncoherent; - msi-controller; - #msi-cells = <1>; - }; diff --git a/target/linux/rockchip/patches-6.12/000-04-v6.15-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch b/target/linux/rockchip/patches-6.12/000-04-v6.15-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch deleted file mode 100644 index 4a6c2ab64c..0000000000 --- a/target/linux/rockchip/patches-6.12/000-04-v6.15-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d0f17738778c12be629ba77ff00c43c3e9eb8428 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Tue, 4 Feb 2025 14:40:07 +0200 -Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 - -Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock -provider support"), the HDMI PHY PLL can be used as an alternative and -more accurate pixel clock source for VOP2 to improve display modes -handling on RK3588 SoC. - -Add the missing #clock-cells property to allow using the clock provider -functionality of HDMI0 PHY. - -Signed-off-by: Cristian Ciocaltea -Tested-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -2813,6 +2813,7 @@ - reg = <0x0 0xfed60000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; - clock-names = "ref", "apb"; -+ #clock-cells = <0>; - #phy-cells = <0>; - resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, - <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, diff --git a/target/linux/rockchip/patches-6.12/000-05-v6.15-arm64-dts-rockchip-Add-HDMI0-PHY-PLL-clock-source-to.patch b/target/linux/rockchip/patches-6.12/000-05-v6.15-arm64-dts-rockchip-Add-HDMI0-PHY-PLL-clock-source-to.patch deleted file mode 100644 index 9fc343efd4..0000000000 --- a/target/linux/rockchip/patches-6.12/000-05-v6.15-arm64-dts-rockchip-Add-HDMI0-PHY-PLL-clock-source-to.patch +++ /dev/null @@ -1,38 +0,0 @@ -From eb4262203d7d85eb7b6f2696816db272e41f5464 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Tue, 4 Feb 2025 14:40:08 +0200 -Subject: arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on - RK3588 - -VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and -more accurate pixel clock source to improve handling of display modes up -to 4K@60Hz on video ports 0, 1 and 2. - -For now only HDMI0 output is supported, hence add the related PLL clock. - -Tested-by: FUKAUMI Naoki -Signed-off-by: Cristian Ciocaltea -Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1261,14 +1261,16 @@ - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, -- <&cru PCLK_VOP_ROOT>; -+ <&cru PCLK_VOP_ROOT>, -+ <&hdptxphy_hdmi0>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", -- "pclk_vop"; -+ "pclk_vop", -+ "pll_hdmiphy0"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; diff --git a/target/linux/rockchip/patches-6.12/000-06-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch b/target/linux/rockchip/patches-6.12/000-06-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch deleted file mode 100644 index 6decd6e33f..0000000000 --- a/target/linux/rockchip/patches-6.12/000-06-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001 -From: Damon Ding -Date: Thu, 6 Feb 2025 11:03:30 +0800 -Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588 - -The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP -and eDP Link. Therefore, it is better to name it hdptxphy0 other than -hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes. - -Signed-off-by: Damon Ding -Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com -[added armsom-sige7, where hdmi-support was added recently and also - the hdptxphy0-as-dclk source I just added] -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1262,7 +1262,7 @@ - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>, -- <&hdptxphy_hdmi0>; -+ <&hdptxphy0>; - clock-names = "aclk", - "hclk", - "dclk_vp0", -@@ -1387,7 +1387,7 @@ - , - ; - interrupt-names = "avp", "cec", "earc", "main", "hpd"; -- phys = <&hdptxphy_hdmi0>; -+ phys = <&hdptxphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd - &hdmim0_tx0_scl &hdmim0_tx0_sda>; -@@ -2810,7 +2810,7 @@ - #dma-cells = <1>; - }; - -- hdptxphy_hdmi0: phy@fed60000 { -+ hdptxphy0: phy@fed60000 { - compatible = "rockchip,rk3588-hdptx-phy"; - reg = <0x0 0xfed60000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; diff --git a/target/linux/rockchip/patches-6.12/000-07-v6.15-arm64-dts-rockchip-Add-PHY-node-for-HDMI1-TX-port-on.patch b/target/linux/rockchip/patches-6.12/000-07-v6.15-arm64-dts-rockchip-Add-PHY-node-for-HDMI1-TX-port-on.patch deleted file mode 100644 index 62371943f0..0000000000 --- a/target/linux/rockchip/patches-6.12/000-07-v6.15-arm64-dts-rockchip-Add-PHY-node-for-HDMI1-TX-port-on.patch +++ /dev/null @@ -1,52 +0,0 @@ -From ea97212a0f66b7bd71c23c12f781f1770dd6fcff Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Wed, 11 Dec 2024 01:06:15 +0200 -Subject: arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588 - -In preparation to enable the second HDMI output port found on RK3588 -SoC, add the related PHY node. This requires a GRF, hence add the -dependent node as well. - -Signed-off-by: Cristian Ciocaltea -Tested-by: Jagan Teki # edgeble-6tops-modules -Tested-by: Alexandre ARNOUD -Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -67,6 +67,11 @@ - }; - }; - -+ hdptxphy1_grf: syscon@fd5e4000 { -+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; -+ reg = <0x0 0xfd5e4000 0x0 0x100>; -+ }; -+ - i2s8_8ch: i2s@fddc8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc8000 0x0 0x1000>; -@@ -395,6 +400,22 @@ - }; - }; - -+ hdptxphy1: phy@fed70000 { -+ compatible = "rockchip,rk3588-hdptx-phy"; -+ reg = <0x0 0xfed70000 0x0 0x2000>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; -+ clock-names = "ref", "apb"; -+ #phy-cells = <0>; -+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, -+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, -+ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, -+ <&cru SRST_HDPTX1_LCPLL>; -+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", -+ "lcpll"; -+ rockchip,grf = <&hdptxphy1_grf>; -+ status = "disabled"; -+ }; -+ - usbdp_phy1: phy@fed90000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed90000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.12/000-08-v6.15-arm64-dts-rockchip-Add-HDMI1-node-on-RK3588.patch b/target/linux/rockchip/patches-6.12/000-08-v6.15-arm64-dts-rockchip-Add-HDMI1-node-on-RK3588.patch deleted file mode 100644 index 26672d90b4..0000000000 --- a/target/linux/rockchip/patches-6.12/000-08-v6.15-arm64-dts-rockchip-Add-HDMI1-node-on-RK3588.patch +++ /dev/null @@ -1,63 +0,0 @@ -From bed6964e779b5853de042da14320edf9f79506fe Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Wed, 11 Dec 2024 01:06:16 +0200 -Subject: arm64: dts: rockchip: Add HDMI1 node on RK3588 - -Add support for the second HDMI TX port found on RK3588 SoC. - -Signed-off-by: Cristian Ciocaltea -Tested-by: Jagan Teki # edgeble-6tops-modules -Tested-by: Alexandre ARNOUD -Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-3-02cdca22ff68@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -140,6 +140,47 @@ - status = "disabled"; - }; - -+ hdmi1: hdmi@fdea0000 { -+ compatible = "rockchip,rk3588-dw-hdmi-qp"; -+ reg = <0x0 0xfdea0000 0x0 0x20000>; -+ clocks = <&cru PCLK_HDMITX1>, -+ <&cru CLK_HDMITX1_EARC>, -+ <&cru CLK_HDMITX1_REF>, -+ <&cru MCLK_I2S6_8CH_TX>, -+ <&cru CLK_HDMIHDP1>, -+ <&cru HCLK_VO1>; -+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "avp", "cec", "earc", "main", "hpd"; -+ phys = <&hdptxphy1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd -+ &hdmim1_tx1_scl &hdmim1_tx1_sda>; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; -+ reset-names = "ref", "hdp"; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vo-grf = <&vo1_grf>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hdmi1_in: port@0 { -+ reg = <0>; -+ }; -+ -+ hdmi1_out: port@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ - pcie3x4: pcie@fe150000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; diff --git a/target/linux/rockchip/patches-6.12/000-09-v6.15-arm64-dts-rockchip-Enable-HDMI1-PHY-clk-provider-on-.patch b/target/linux/rockchip/patches-6.12/000-09-v6.15-arm64-dts-rockchip-Enable-HDMI1-PHY-clk-provider-on-.patch deleted file mode 100644 index 3503f1a6e9..0000000000 --- a/target/linux/rockchip/patches-6.12/000-09-v6.15-arm64-dts-rockchip-Enable-HDMI1-PHY-clk-provider-on-.patch +++ /dev/null @@ -1,27 +0,0 @@ -From aadaa27956e3430217d9e6b8af5880e39b05b961 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sun, 23 Feb 2025 11:31:39 +0200 -Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 - -Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock -provider support"), the HDMI PHY PLL can be used as an alternative and -more accurate pixel clock source for VOP2 to improve display modes -handling on RK3588 SoC. - -Add the missing #clock-cells property to allow using the clock provider -functionality of HDMI1 PHY. - -Signed-off-by: Cristian Ciocaltea -Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -446,6 +446,7 @@ - reg = <0x0 0xfed70000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; - clock-names = "ref", "apb"; -+ #clock-cells = <0>; - #phy-cells = <0>; - resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, - <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, diff --git a/target/linux/rockchip/patches-6.12/000-10-v6.15-arm64-dts-rockchip-Add-HDMI1-PHY-PLL-clock-source-to.patch b/target/linux/rockchip/patches-6.12/000-10-v6.15-arm64-dts-rockchip-Add-HDMI1-PHY-PLL-clock-source-to.patch deleted file mode 100644 index eec7d0ad10..0000000000 --- a/target/linux/rockchip/patches-6.12/000-10-v6.15-arm64-dts-rockchip-Add-HDMI1-PHY-PLL-clock-source-to.patch +++ /dev/null @@ -1,48 +0,0 @@ -From b2e668a60ed866ba960acb5310d1fb6bf81d154f Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sun, 23 Feb 2025 11:31:40 +0200 -Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on - RK3588 - -VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and -more accurate pixel clock source to improve handling of display modes up -to 4K@60Hz on video ports 0, 1 and 2. - -The HDMI1 PHY PLL clock source cannot be added directly to vop node in -rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an -optional feature and its PHY node belongs to a separate (extra) DT file. - -Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its -clocks & clock-names properties in the extra DT file. - -Signed-off-by: Cristian Ciocaltea -Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -509,3 +509,24 @@ - status = "disabled"; - }; - }; -+ -+&vop { -+ clocks = <&cru ACLK_VOP>, -+ <&cru HCLK_VOP>, -+ <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, -+ <&cru DCLK_VOP2>, -+ <&cru DCLK_VOP3>, -+ <&cru PCLK_VOP_ROOT>, -+ <&hdptxphy0>, -+ <&hdptxphy1>; -+ clock-names = "aclk", -+ "hclk", -+ "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2", -+ "dclk_vp3", -+ "pclk_vop", -+ "pll_hdmiphy0", -+ "pll_hdmiphy1"; -+}; diff --git a/target/linux/rockchip/patches-6.12/000-11-v6.15-arm64-dts-rockchip-Add-HDMI-audio-outputs-for-rk3588.patch b/target/linux/rockchip/patches-6.12/000-11-v6.15-arm64-dts-rockchip-Add-HDMI-audio-outputs-for-rk3588.patch deleted file mode 100644 index 3e4ba5bf10..0000000000 --- a/target/linux/rockchip/patches-6.12/000-11-v6.15-arm64-dts-rockchip-Add-HDMI-audio-outputs-for-rk3588.patch +++ /dev/null @@ -1,91 +0,0 @@ -From b8c6c136971c0e9750eec89f367529b2854d3a3c Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Mon, 17 Feb 2025 16:47:41 -0500 -Subject: arm64: dts: rockchip: Add HDMI audio outputs for rk3588 - -For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node -as CODEC and the i2s5 device as CPU. - -Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is -i2s6, but only added in the rk3588-extra.dtsi device tree as the second -TX HDMI port is not available on base versions of the SoC. - -The simple-audio-card,mclk-fs value is set to 128 as it is done in -the downstream driver. - -The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so -that they can be used as audio codec nodes. - -Tested-by: Quentin Schulz # RK3588 Tiger Haikou -Signed-off-by: Detlev Casanova -Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") -Signed-off-by: Kuninori Morimoto -Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -382,6 +382,22 @@ - }; - }; - -+ hdmi0_sound: hdmi0-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <128>; -+ simple-audio-card,name = "hdmi0"; -+ status = "disabled"; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi0>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s5_8ch>; -+ }; -+ }; -+ - pmu-a55 { - compatible = "arm,cortex-a55-pmu"; - interrupts = ; -@@ -1396,6 +1412,7 @@ - reset-names = "ref", "hdp"; - rockchip,grf = <&sys_grf>; - rockchip,vo-grf = <&vo1_grf>; -+ #sound-dai-cells = <0>; - status = "disabled"; - - ports { ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -7,6 +7,22 @@ - #include "rk3588-extra-pinctrl.dtsi" - - / { -+ hdmi1_sound: hdmi1-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <128>; -+ simple-audio-card,name = "hdmi1"; -+ status = "disabled"; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi1>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s6_8ch>; -+ }; -+ }; -+ - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; -@@ -165,6 +181,7 @@ - reset-names = "ref", "hdp"; - rockchip,grf = <&sys_grf>; - rockchip,vo-grf = <&vo1_grf>; -+ #sound-dai-cells = <0>; - status = "disabled"; - - ports { diff --git a/target/linux/rockchip/patches-6.12/000-12-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/000-12-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch deleted file mode 100644 index 5ad1c88d6d..0000000000 --- a/target/linux/rockchip/patches-6.12/000-12-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch +++ /dev/null @@ -1,46 +0,0 @@ -From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 20 Feb 2025 19:58:11 +0100 -Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for - RK3588 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enabling the GPU power domain requires that the GPU regulator is -enabled. The regulator is enabled at boot time, but gets disabled -automatically when there are no users. - -This means the system might run into a failure state hanging the -whole system for the following use cases: - - * if the GPU driver is being probed late (e.g. build as a - module and firmware is not in initramfs), the regulator - might already have been disabled. In that case the power - domain is enabled before the regulator. - * unbinding the GPU driver will disable the PM domain and - the regulator. When the driver is bound again, the PM - domain will be enabled before the regulator and error - appears. - -Avoid this by adding an explicit regulator dependency to the -power domain. - -Tested-by: Heiko Stuebner -Reported-by: Adrián Martínez Larumbe -Tested-by: Adrian Larumbe # On Rock 5B -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -880,7 +880,7 @@ - }; - }; - /* These power domains are grouped by VD_GPU */ -- power-domain@RK3588_PD_GPU { -+ pd_gpu: power-domain@RK3588_PD_GPU { - reg = ; - clocks = <&cru CLK_GPU>, - <&cru CLK_GPU_COREGROUP>, diff --git a/target/linux/rockchip/patches-6.12/000-13-v6.15-arm64-dts-rockchip-Add-device-tree-support-for-HDMI-.patch b/target/linux/rockchip/patches-6.12/000-13-v6.15-arm64-dts-rockchip-Add-device-tree-support-for-HDMI-.patch deleted file mode 100644 index f269185be5..0000000000 --- a/target/linux/rockchip/patches-6.12/000-13-v6.15-arm64-dts-rockchip-Add-device-tree-support-for-HDMI-.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 0327238991ba2d1de25e1116b1c064f433e45b8d Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Fri, 7 Mar 2025 12:18:56 +0300 -Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller - -Add device tree support for Synopsys DesignWare HDMI RX -Controller. - -Reviewed-by: Dmitry Osipenko -Tested-by: Dmitry Osipenko -Co-developed-by: Dingxian Wen -Signed-off-by: Dingxian Wen -Signed-off-by: Shreeya Patel -Signed-off-by: Dmitry Osipenko -Link: https://lore.kernel.org/r/20250307091857.646581-2-dmitry.osipenko@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -23,6 +23,30 @@ - }; - }; - -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* -+ * The 4k HDMI capture controller works only with 32bit -+ * phys addresses and doesn't support IOMMU. HDMI RX CMA -+ * must be reserved below 4GB. -+ * The size of 160MB was determined as follows: -+ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB -+ * To ensure sufficient support for practical use-cases, -+ * we doubled the 66MB value. -+ */ -+ hdmi_receiver_cma: hdmi-receiver-cma { -+ compatible = "shared-dma-pool"; -+ alloc-ranges = <0x0 0x0 0x0 0xffffffff>; -+ size = <0x0 (160 * 0x100000)>; /* 160MiB */ -+ alignment = <0x0 0x40000>; /* 64K */ -+ no-map; -+ status = "disabled"; -+ }; -+ }; -+ - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; -@@ -198,6 +222,37 @@ - }; - }; - -+ hdmi_receiver: hdmi_receiver@fdee0000 { -+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; -+ reg = <0x0 0xfdee0000 0x0 0x6000>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "cec", "hdmi", "dma"; -+ clocks = <&cru ACLK_HDMIRX>, -+ <&cru CLK_HDMIRX_AUD>, -+ <&cru CLK_CR_PARA>, -+ <&cru PCLK_HDMIRX>, -+ <&cru CLK_HDMIRX_REF>, -+ <&cru PCLK_S_HDMIRX>, -+ <&cru HCLK_VO1>; -+ clock-names = "aclk", -+ "audio", -+ "cr_para", -+ "pclk", -+ "ref", -+ "hclk_s_hdmirx", -+ "hclk_vo1"; -+ memory-region = <&hdmi_receiver_cma>; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, -+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; -+ reset-names = "axi", "apb", "ref", "biu"; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vo1-grf = <&vo1_grf>; -+ status = "disabled"; -+ }; -+ - pcie3x4: pcie@fe150000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; diff --git a/target/linux/rockchip/patches-6.12/001-01-v6.13-arm64-dts-rockchip-Split-up-RK3588-s-PCIe-pinctrls.patch b/target/linux/rockchip/patches-6.12/001-01-v6.13-arm64-dts-rockchip-Split-up-RK3588-s-PCIe-pinctrls.patch new file mode 100644 index 0000000000..9a58adf4cd --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-01-v6.13-arm64-dts-rockchip-Split-up-RK3588-s-PCIe-pinctrls.patch @@ -0,0 +1,444 @@ +From 4294e32111781b3de4d73b944cbd1bc1662a9a7a Mon Sep 17 00:00:00 2001 +From: Sam Edwards +Date: Wed, 11 Sep 2024 19:50:30 -0700 +Subject: arm64: dts: rockchip: Split up RK3588's PCIe pinctrls + +These pinctrls manage the low-speed PCIe signals: +- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to + request that external clock-generation circuitry provide a clock. +- PERST#: An input on the RK3588 in EP mode, used to detect a reset + signal from the RC. In RC mode, the hardware does not use this signal: + Linux itself generates it by putting the pin in GPIO mode. +- WAKE#: In EP mode, this is an output; in RC mode, this is an input. + +Each of these signals serves a distinct purpose, and more importantly, +PERST# should not be muxed when the RK3588 is in the RC role. Bundling +them together in pinctrl groups prevents proper use: indeed, almost none +of the current board-specific .dts files make any use of them. +(Exception: Rock 5A recently had a patch land that misuses _pins; this + patch corrects that.) + +However, on some RK3588 boards, the PCIe 3 controller will indefinitely +stall the boot if CLKREQ# is not muxed (details in the next patch). +This patch unbundles the signals to allow them to be used. + +Signed-off-by: Sam Edwards +Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi +@@ -1612,23 +1612,43 @@ + + pcie20x1 { + /omit-if-no-ref/ +- pcie20x1m0_pins: pcie20x1m0-pins { ++ pcie20x1m0_clkreqn: pcie20x1m0-clkreqn { + rockchip,pins = + /* pcie20x1_2_clkreqn_m0 */ +- <3 RK_PC7 4 &pcfg_pull_none>, ++ <3 RK_PC7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie20x1m0_perstn: pcie20x1m0-perstn { ++ rockchip,pins = + /* pcie20x1_2_perstn_m0 */ +- <3 RK_PD1 4 &pcfg_pull_none>, ++ <3 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie20x1m0_waken: pcie20x1m0-waken { ++ rockchip,pins = + /* pcie20x1_2_waken_m0 */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ +- pcie20x1m1_pins: pcie20x1m1-pins { ++ pcie20x1m1_clkreqn: pcie20x1m1-clkreqn { + rockchip,pins = + /* pcie20x1_2_clkreqn_m1 */ +- <4 RK_PB7 4 &pcfg_pull_none>, ++ <4 RK_PB7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie20x1m1_perstn: pcie20x1m1-perstn { ++ rockchip,pins = + /* pcie20x1_2_perstn_m1 */ +- <4 RK_PC1 4 &pcfg_pull_none>, ++ <4 RK_PC1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie20x1m1_waken: pcie20x1m1-waken { ++ rockchip,pins = + /* pcie20x1_2_waken_m1 */ + <4 RK_PC0 4 &pcfg_pull_none>; + }; +@@ -1654,52 +1674,127 @@ + + pcie30x1 { + /omit-if-no-ref/ +- pcie30x1m0_pins: pcie30x1m0-pins { ++ pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn { + rockchip,pins = + /* pcie30x1_0_clkreqn_m0 */ +- <0 RK_PC0 12 &pcfg_pull_none>, ++ <0 RK_PC0 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m0_0_perstn: pcie30x1m0-0-perstn { ++ rockchip,pins = + /* pcie30x1_0_perstn_m0 */ +- <0 RK_PC5 12 &pcfg_pull_none>, ++ <0 RK_PC5 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m0_0_waken: pcie30x1m0-0-waken { ++ rockchip,pins = + /* pcie30x1_0_waken_m0 */ +- <0 RK_PC4 12 &pcfg_pull_none>, ++ <0 RK_PC4 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn { ++ rockchip,pins = + /* pcie30x1_1_clkreqn_m0 */ +- <0 RK_PB5 12 &pcfg_pull_none>, ++ <0 RK_PB5 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m0_1_perstn: pcie30x1m0-1-perstn { ++ rockchip,pins = + /* pcie30x1_1_perstn_m0 */ +- <0 RK_PB7 12 &pcfg_pull_none>, ++ <0 RK_PB7 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m0_1_waken: pcie30x1m0-1-waken { ++ rockchip,pins = + /* pcie30x1_1_waken_m0 */ + <0 RK_PB6 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ +- pcie30x1m1_pins: pcie30x1m1-pins { ++ pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn { + rockchip,pins = + /* pcie30x1_0_clkreqn_m1 */ +- <4 RK_PA3 4 &pcfg_pull_none>, ++ <4 RK_PA3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m1_0_perstn: pcie30x1m1-0-perstn { ++ rockchip,pins = + /* pcie30x1_0_perstn_m1 */ +- <4 RK_PA5 4 &pcfg_pull_none>, ++ <4 RK_PA5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m1_0_waken: pcie30x1m1-0-waken { ++ rockchip,pins = + /* pcie30x1_0_waken_m1 */ +- <4 RK_PA4 4 &pcfg_pull_none>, ++ <4 RK_PA4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn { ++ rockchip,pins = + /* pcie30x1_1_clkreqn_m1 */ +- <4 RK_PA0 4 &pcfg_pull_none>, ++ <4 RK_PA0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m1_1_perstn: pcie30x1m1-1-perstn { ++ rockchip,pins = + /* pcie30x1_1_perstn_m1 */ +- <4 RK_PA2 4 &pcfg_pull_none>, ++ <4 RK_PA2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m1_1_waken: pcie30x1m1-1-waken { ++ rockchip,pins = + /* pcie30x1_1_waken_m1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ +- pcie30x1m2_pins: pcie30x1m2-pins { ++ pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn { + rockchip,pins = + /* pcie30x1_0_clkreqn_m2 */ +- <1 RK_PB5 4 &pcfg_pull_none>, ++ <1 RK_PB5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m2_0_perstn: pcie30x1m2-0-perstn { ++ rockchip,pins = + /* pcie30x1_0_perstn_m2 */ +- <1 RK_PB4 4 &pcfg_pull_none>, ++ <1 RK_PB4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m2_0_waken: pcie30x1m2-0-waken { ++ rockchip,pins = + /* pcie30x1_0_waken_m2 */ +- <1 RK_PB3 4 &pcfg_pull_none>, ++ <1 RK_PB3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn { ++ rockchip,pins = + /* pcie30x1_1_clkreqn_m2 */ +- <1 RK_PA0 4 &pcfg_pull_none>, ++ <1 RK_PA0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m2_1_perstn: pcie30x1m2-1-perstn { ++ rockchip,pins = + /* pcie30x1_1_perstn_m2 */ +- <1 RK_PA7 4 &pcfg_pull_none>, ++ <1 RK_PA7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m2_1_waken: pcie30x1m2-1-waken { ++ rockchip,pins = + /* pcie30x1_1_waken_m2 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; +@@ -1721,45 +1816,85 @@ + + pcie30x2 { + /omit-if-no-ref/ +- pcie30x2m0_pins: pcie30x2m0-pins { ++ pcie30x2m0_clkreqn: pcie30x2m0-clkreqn { + rockchip,pins = + /* pcie30x2_clkreqn_m0 */ +- <0 RK_PD1 12 &pcfg_pull_none>, ++ <0 RK_PD1 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m0_perstn: pcie30x2m0-perstn { ++ rockchip,pins = + /* pcie30x2_perstn_m0 */ +- <0 RK_PD4 12 &pcfg_pull_none>, ++ <0 RK_PD4 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m0_waken: pcie30x2m0-waken { ++ rockchip,pins = + /* pcie30x2_waken_m0 */ + <0 RK_PD2 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ +- pcie30x2m1_pins: pcie30x2m1-pins { ++ pcie30x2m1_clkreqn: pcie30x2m1-clkreqn { + rockchip,pins = + /* pcie30x2_clkreqn_m1 */ +- <4 RK_PA6 4 &pcfg_pull_none>, ++ <4 RK_PA6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m1_perstn: pcie30x2m1-perstn { ++ rockchip,pins = + /* pcie30x2_perstn_m1 */ +- <4 RK_PB0 4 &pcfg_pull_none>, ++ <4 RK_PB0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m1_waken: pcie30x2m1-waken { ++ rockchip,pins = + /* pcie30x2_waken_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ +- pcie30x2m2_pins: pcie30x2m2-pins { ++ pcie30x2m2_clkreqn: pcie30x2m2-clkreqn { + rockchip,pins = + /* pcie30x2_clkreqn_m2 */ +- <3 RK_PD2 4 &pcfg_pull_none>, ++ <3 RK_PD2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m2_perstn: pcie30x2m2-perstn { ++ rockchip,pins = + /* pcie30x2_perstn_m2 */ +- <3 RK_PD4 4 &pcfg_pull_none>, ++ <3 RK_PD4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m2_waken: pcie30x2m2-waken { ++ rockchip,pins = + /* pcie30x2_waken_m2 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ +- pcie30x2m3_pins: pcie30x2m3-pins { ++ pcie30x2m3_clkreqn: pcie30x2m3-clkreqn { + rockchip,pins = + /* pcie30x2_clkreqn_m3 */ +- <1 RK_PD7 4 &pcfg_pull_none>, ++ <1 RK_PD7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m3_perstn: pcie30x2m3-perstn { ++ rockchip,pins = + /* pcie30x2_perstn_m3 */ +- <1 RK_PB7 4 &pcfg_pull_none>, ++ <1 RK_PB7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m3_waken: pcie30x2m3-waken { ++ rockchip,pins = + /* pcie30x2_waken_m3 */ + <1 RK_PB6 4 &pcfg_pull_none>; + }; +@@ -1774,45 +1909,85 @@ + + pcie30x4 { + /omit-if-no-ref/ +- pcie30x4m0_pins: pcie30x4m0-pins { ++ pcie30x4m0_clkreqn: pcie30x4m0-clkreqn { + rockchip,pins = + /* pcie30x4_clkreqn_m0 */ +- <0 RK_PC6 12 &pcfg_pull_none>, ++ <0 RK_PC6 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m0_perstn: pcie30x4m0-perstn { ++ rockchip,pins = + /* pcie30x4_perstn_m0 */ +- <0 RK_PD0 12 &pcfg_pull_none>, ++ <0 RK_PD0 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m0_waken: pcie30x4m0-waken { ++ rockchip,pins = + /* pcie30x4_waken_m0 */ + <0 RK_PC7 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ +- pcie30x4m1_pins: pcie30x4m1-pins { ++ pcie30x4m1_clkreqn: pcie30x4m1-clkreqn { + rockchip,pins = + /* pcie30x4_clkreqn_m1 */ +- <4 RK_PB4 4 &pcfg_pull_none>, ++ <4 RK_PB4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m1_perstn: pcie30x4m1-perstn { ++ rockchip,pins = + /* pcie30x4_perstn_m1 */ +- <4 RK_PB6 4 &pcfg_pull_none>, ++ <4 RK_PB6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m1_waken: pcie30x4m1-waken { ++ rockchip,pins = + /* pcie30x4_waken_m1 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ +- pcie30x4m2_pins: pcie30x4m2-pins { ++ pcie30x4m2_clkreqn: pcie30x4m2-clkreqn { + rockchip,pins = + /* pcie30x4_clkreqn_m2 */ +- <3 RK_PC4 4 &pcfg_pull_none>, ++ <3 RK_PC4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m2_perstn: pcie30x4m2-perstn { ++ rockchip,pins = + /* pcie30x4_perstn_m2 */ +- <3 RK_PC6 4 &pcfg_pull_none>, ++ <3 RK_PC6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m2_waken: pcie30x4m2-waken { ++ rockchip,pins = + /* pcie30x4_waken_m2 */ + <3 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ +- pcie30x4m3_pins: pcie30x4m3-pins { ++ pcie30x4m3_clkreqn: pcie30x4m3-clkreqn { + rockchip,pins = + /* pcie30x4_clkreqn_m3 */ +- <1 RK_PB0 4 &pcfg_pull_none>, ++ <1 RK_PB0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m3_perstn: pcie30x4m3-perstn { ++ rockchip,pins = + /* pcie30x4_perstn_m3 */ +- <1 RK_PB2 4 &pcfg_pull_none>, ++ <1 RK_PB2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m3_waken: pcie30x4m3-waken { ++ rockchip,pins = + /* pcie30x4_waken_m3 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -310,7 +310,7 @@ + }; + + &pcie2x1l2 { +- pinctrl-0 = <&pcie20x1m0_pins>; ++ pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>; + pinctrl-names = "default"; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_wf>; +@@ -328,6 +328,10 @@ + pow_en: pow-en { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; ++ ++ pcie2_reset: pcie2-reset { ++ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; + }; + + power { diff --git a/target/linux/rockchip/patches-6.12/001-01-v6.13-arm64-dts-rockchip-add-and-enable-gpu-node-for-Radxa.patch b/target/linux/rockchip/patches-6.12/001-01-v6.13-arm64-dts-rockchip-add-and-enable-gpu-node-for-Radxa.patch deleted file mode 100644 index 55cec3dcf7..0000000000 --- a/target/linux/rockchip/patches-6.12/001-01-v6.13-arm64-dts-rockchip-add-and-enable-gpu-node-for-Radxa.patch +++ /dev/null @@ -1,25 +0,0 @@ -From a98053d098c4ad91a45a3a55604d9574dfc6ffdb Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Sat, 19 Oct 2024 02:50:08 +0000 -Subject: arm64: dts: rockchip: add and enable gpu node for Radxa ROCK 5A - -add gpu node to make it usable on Radxa ROCK 5A. - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20241019025008.852-1-naoki@radxa.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -166,6 +166,11 @@ - cpu-supply = <&vdd_cpu_lit_s0>; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; diff --git a/target/linux/rockchip/patches-6.12/001-02-v6.13-arm64-dts-rockchip-Add-HDMI0-node-to-rk3588.patch b/target/linux/rockchip/patches-6.12/001-02-v6.13-arm64-dts-rockchip-Add-HDMI0-node-to-rk3588.patch new file mode 100644 index 0000000000..135e79342f --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-02-v6.13-arm64-dts-rockchip-Add-HDMI0-node-to-rk3588.patch @@ -0,0 +1,61 @@ +From d7bb71e69f58c1b3665a9f926bf8d3855111bf8e Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sat, 19 Oct 2024 13:12:10 +0300 +Subject: arm64: dts: rockchip: Add HDMI0 node to rk3588 + +Add support for the HDMI0 output port found on RK3588 SoC. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -1369,6 +1369,47 @@ + status = "disabled"; + }; + ++ hdmi0: hdmi@fde80000 { ++ compatible = "rockchip,rk3588-dw-hdmi-qp"; ++ reg = <0x0 0xfde80000 0x0 0x20000>; ++ clocks = <&cru PCLK_HDMITX0>, ++ <&cru CLK_HDMITX0_EARC>, ++ <&cru CLK_HDMITX0_REF>, ++ <&cru MCLK_I2S5_8CH_TX>, ++ <&cru CLK_HDMIHDP0>, ++ <&cru HCLK_VO1>; ++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "avp", "cec", "earc", "main", "hpd"; ++ phys = <&hdptxphy_hdmi0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd ++ &hdmim0_tx0_scl &hdmim0_tx0_sda>; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; ++ reset-names = "ref", "hdp"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo-grf = <&vo1_grf>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi0_in: port@0 { ++ reg = <0>; ++ }; ++ ++ hdmi0_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ + qos_gpu_m0: qos@fdf35000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; diff --git a/target/linux/rockchip/patches-6.12/001-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5a.patch b/target/linux/rockchip/patches-6.12/001-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5a.patch deleted file mode 100644 index c305197183..0000000000 --- a/target/linux/rockchip/patches-6.12/001-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5a.patch +++ /dev/null @@ -1,90 +0,0 @@ -From f57a8daf6bbd8e71f16693ad6d8421cb881c7fe0 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Tue, 22 Oct 2024 19:04:42 +0300 -Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5a - -Add the necessary DT changes to enable HDMI0 on Radxa ROCK 5A. - -Signed-off-by: Cristian Ciocaltea -Link: https://lore.kernel.org/r/20241022-rk3588-hdmi0-dt-v3-1-3cc981e89afb@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -5,6 +5,7 @@ - #include - #include - #include -+#include - #include "rk3588s.dtsi" - - / { -@@ -35,6 +36,17 @@ - stdout-path = "serial2:1500000n8"; - }; - -+ hdmi0-con { -+ compatible = "hdmi-connector"; -+ type = "d"; -+ -+ port { -+ hdmi0_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -301,6 +313,31 @@ - status = "okay"; - }; - -+&hdmi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmim0_tx0_cec -+ &hdmim1_tx0_hpd -+ &hdmim0_tx0_scl -+ &hdmim0_tx0_sda>; -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi0_con_in>; -+ }; -+}; -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ - &mdio1 { - rgmii_phy1: ethernet-phy@1 { - /* RTL8211F */ -@@ -793,3 +830,18 @@ - &usb_host2_xhci { - status = "okay"; - }; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.12/001-03-v6.13-arm64-dts-rockchip-sort-rk3588s-rock5a-properly-in-M.patch b/target/linux/rockchip/patches-6.12/001-03-v6.13-arm64-dts-rockchip-sort-rk3588s-rock5a-properly-in-M.patch deleted file mode 100644 index 3cab321f25..0000000000 --- a/target/linux/rockchip/patches-6.12/001-03-v6.13-arm64-dts-rockchip-sort-rk3588s-rock5a-properly-in-M.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 9f3360b42bb5b0c99073827a3dd81d2568b2a4ed Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Mon, 28 Oct 2024 07:23:44 +0000 -Subject: arm64: dts: rockchip: sort rk3588s-rock5a properly in Makefile - -sort target dtb files properly in Makefile for rockchip. - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20241028072344.1514-1-naoki@radxa.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -151,6 +151,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-i - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb --dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb diff --git a/target/linux/rockchip/patches-6.12/001-03-v6.15-arm64-dts-rockchip-Use-dma-noncoherent-in-base-RK358.patch b/target/linux/rockchip/patches-6.12/001-03-v6.15-arm64-dts-rockchip-Use-dma-noncoherent-in-base-RK358.patch new file mode 100644 index 0000000000..0f3a564413 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-03-v6.15-arm64-dts-rockchip-Use-dma-noncoherent-in-base-RK358.patch @@ -0,0 +1,51 @@ +From 33b561eb66f1e271f2899e103c857d20425076f4 Mon Sep 17 00:00:00 2001 +From: Dragan Simic +Date: Wed, 8 Jan 2025 05:26:45 +0100 +Subject: arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi + +The preferred way to denote hardware with non-coherent DMA is to use the +"dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS +levels, [1] instead of relying on the compatibles to handle hardware errata, +in this case the Rockchip 3588001 errata. [2] + +Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi, +which also goes along with adding initial support for the Rockchip RK3582 SoC +variant, with its separate compatible. [2][3] + +[1] Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +[2] https://lore.kernel.org/linux-rockchip/86msgoozqa.wl-maz@kernel.org/ +[3] https://lore.kernel.org/linux-rockchip/20241222030355.2246-4-naoki@radxa.com/ + +Cc: Marc Zyngier +Cc: FUKAUMI Naoki +Acked-by: Marc Zyngier +Signed-off-by: Dragan Simic +Link: https://lore.kernel.org/r/fa1a672dae3644bb3caa58f03216d0ca349db88b.1736279094.git.dsimic@manjaro.org +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -2020,6 +2020,7 @@ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = ; + interrupt-controller; ++ dma-noncoherent; + mbi-alias = <0x0 0xfe610000>; + mbi-ranges = <424 56>; + msi-controller; +@@ -2031,6 +2032,7 @@ + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; ++ dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; +@@ -2038,6 +2040,7 @@ + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; ++ dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; diff --git a/target/linux/rockchip/patches-6.12/001-04-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch b/target/linux/rockchip/patches-6.12/001-04-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch deleted file mode 100644 index d485ebf448..0000000000 --- a/target/linux/rockchip/patches-6.12/001-04-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 5c96e63301978f4657c9082c55a066763c8db7b1 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sat, 5 Oct 2024 22:40:12 +0200 -Subject: arm64: dts: rockchip: adapt regulator nodenames to preferred form - -The preferred nodename for fixed-regulators has changed to -pattern: '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$' - -Fix all Rockchip DT regulator nodenames. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/0ae40493-93e9-40cd-9ca9-990ae064f21a@gmail.com -[adapted rebased on top of a number of other changes and included - neu6a-wifi + wolfvision-pf5-io-expander overlays] -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -68,7 +68,7 @@ - #cooling-cells = <2>; - }; - -- vcc12v_dcin: vcc12v-dcin-regulator { -+ vcc12v_dcin: regulator-vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; -@@ -77,7 +77,7 @@ - regulator-max-microvolt = <12000000>; - }; - -- vcc3v3_wf: vcc3v3-wf-regulator { -+ vcc3v3_wf: regulator-vcc3v3-wf { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_wf"; - regulator-min-microvolt = <3300000>; -@@ -89,7 +89,7 @@ - vin-supply = <&vcc5v0_sys>; - }; - -- vcc5v0_host: vcc5v0-host-regulator { -+ vcc5v0_host: regulator-vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; -@@ -103,7 +103,7 @@ - vin-supply = <&vcc5v0_sys>; - }; - -- vcc5v0_sys: vcc5v0-sys-regulator { -+ vcc5v0_sys: regulator-vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; -@@ -113,7 +113,7 @@ - vin-supply = <&vcc12v_dcin>; - }; - -- vcc_5v0: vcc-5v0-regulator { -+ vcc_5v0: regulator-vcc-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-min-microvolt = <5000000>; -@@ -127,7 +127,7 @@ - vin-supply = <&vcc5v0_sys>; - }; - -- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; diff --git a/target/linux/rockchip/patches-6.12/001-04-v6.15-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch b/target/linux/rockchip/patches-6.12/001-04-v6.15-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch new file mode 100644 index 0000000000..4a6c2ab64c --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-04-v6.15-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch @@ -0,0 +1,28 @@ +From d0f17738778c12be629ba77ff00c43c3e9eb8428 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Tue, 4 Feb 2025 14:40:07 +0200 +Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 + +Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock +provider support"), the HDMI PHY PLL can be used as an alternative and +more accurate pixel clock source for VOP2 to improve display modes +handling on RK3588 SoC. + +Add the missing #clock-cells property to allow using the clock provider +functionality of HDMI0 PHY. + +Signed-off-by: Cristian Ciocaltea +Tested-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -2813,6 +2813,7 @@ + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; ++ #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, diff --git a/target/linux/rockchip/patches-6.12/001-05-v6.15-arm64-dts-rockchip-Add-HDMI0-PHY-PLL-clock-source-to.patch b/target/linux/rockchip/patches-6.12/001-05-v6.15-arm64-dts-rockchip-Add-HDMI0-PHY-PLL-clock-source-to.patch new file mode 100644 index 0000000000..9fc343efd4 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-05-v6.15-arm64-dts-rockchip-Add-HDMI0-PHY-PLL-clock-source-to.patch @@ -0,0 +1,38 @@ +From eb4262203d7d85eb7b6f2696816db272e41f5464 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Tue, 4 Feb 2025 14:40:08 +0200 +Subject: arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on + RK3588 + +VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and +more accurate pixel clock source to improve handling of display modes up +to 4K@60Hz on video ports 0, 1 and 2. + +For now only HDMI0 output is supported, hence add the related PLL clock. + +Tested-by: FUKAUMI Naoki +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -1261,14 +1261,16 @@ + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, +- <&cru PCLK_VOP_ROOT>; ++ <&cru PCLK_VOP_ROOT>, ++ <&hdptxphy_hdmi0>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", +- "pclk_vop"; ++ "pclk_vop", ++ "pll_hdmiphy0"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; diff --git a/target/linux/rockchip/patches-6.12/001-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch b/target/linux/rockchip/patches-6.12/001-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch deleted file mode 100644 index 0e30195847..0000000000 --- a/target/linux/rockchip/patches-6.12/001-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001 -From: Damon Ding -Date: Thu, 6 Feb 2025 11:03:30 +0800 -Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588 - -The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP -and eDP Link. Therefore, it is better to name it hdptxphy0 other than -hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes. - -Signed-off-by: Damon Ding -Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com -[added armsom-sige7, where hdmi-support was added recently and also - the hdptxphy0-as-dclk source I just added] -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -334,7 +334,7 @@ - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - diff --git a/target/linux/rockchip/patches-6.12/001-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/001-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch deleted file mode 100644 index c11bc86c9d..0000000000 --- a/target/linux/rockchip/patches-6.12/001-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch +++ /dev/null @@ -1,48 +0,0 @@ -From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 20 Feb 2025 19:58:11 +0100 -Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for - RK3588 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enabling the GPU power domain requires that the GPU regulator is -enabled. The regulator is enabled at boot time, but gets disabled -automatically when there are no users. - -This means the system might run into a failure state hanging the -whole system for the following use cases: - - * if the GPU driver is being probed late (e.g. build as a - module and firmware is not in initramfs), the regulator - might already have been disabled. In that case the power - domain is enabled before the regulator. - * unbinding the GPU driver will disable the PM domain and - the regulator. When the driver is bound again, the PM - domain will be enabled before the regulator and error - appears. - -Avoid this by adding an explicit regulator dependency to the -power domain. - -Tested-by: Heiko Stuebner -Reported-by: Adrián Martínez Larumbe -Tested-by: Adrian Larumbe # On Rock 5B -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -359,6 +359,10 @@ - status = "okay"; - }; - -+&pd_gpu { -+ domain-supply = <&vdd_gpu_s0>; -+}; -+ - &pinctrl { - leds { - io_led: io-led { diff --git a/target/linux/rockchip/patches-6.12/001-06-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch b/target/linux/rockchip/patches-6.12/001-06-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch new file mode 100644 index 0000000000..6decd6e33f --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-06-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch @@ -0,0 +1,44 @@ +From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001 +From: Damon Ding +Date: Thu, 6 Feb 2025 11:03:30 +0800 +Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588 + +The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP +and eDP Link. Therefore, it is better to name it hdptxphy0 other than +hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes. + +Signed-off-by: Damon Ding +Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com +[added armsom-sige7, where hdmi-support was added recently and also + the hdptxphy0-as-dclk source I just added] +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -1262,7 +1262,7 @@ + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>, +- <&hdptxphy_hdmi0>; ++ <&hdptxphy0>; + clock-names = "aclk", + "hclk", + "dclk_vp0", +@@ -1387,7 +1387,7 @@ + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; +- phys = <&hdptxphy_hdmi0>; ++ phys = <&hdptxphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda>; +@@ -2810,7 +2810,7 @@ + #dma-cells = <1>; + }; + +- hdptxphy_hdmi0: phy@fed60000 { ++ hdptxphy0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; diff --git a/target/linux/rockchip/patches-6.12/001-07-v6.15-arm64-dts-rockchip-Add-PHY-node-for-HDMI1-TX-port-on.patch b/target/linux/rockchip/patches-6.12/001-07-v6.15-arm64-dts-rockchip-Add-PHY-node-for-HDMI1-TX-port-on.patch new file mode 100644 index 0000000000..62371943f0 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-07-v6.15-arm64-dts-rockchip-Add-PHY-node-for-HDMI1-TX-port-on.patch @@ -0,0 +1,52 @@ +From ea97212a0f66b7bd71c23c12f781f1770dd6fcff Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Wed, 11 Dec 2024 01:06:15 +0200 +Subject: arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588 + +In preparation to enable the second HDMI output port found on RK3588 +SoC, add the related PHY node. This requires a GRF, hence add the +dependent node as well. + +Signed-off-by: Cristian Ciocaltea +Tested-by: Jagan Teki # edgeble-6tops-modules +Tested-by: Alexandre ARNOUD +Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +@@ -67,6 +67,11 @@ + }; + }; + ++ hdptxphy1_grf: syscon@fd5e4000 { ++ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; ++ reg = <0x0 0xfd5e4000 0x0 0x100>; ++ }; ++ + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; +@@ -395,6 +400,22 @@ + }; + }; + ++ hdptxphy1: phy@fed70000 { ++ compatible = "rockchip,rk3588-hdptx-phy"; ++ reg = <0x0 0xfed70000 0x0 0x2000>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; ++ clock-names = "ref", "apb"; ++ #phy-cells = <0>; ++ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, ++ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, ++ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, ++ <&cru SRST_HDPTX1_LCPLL>; ++ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", ++ "lcpll"; ++ rockchip,grf = <&hdptxphy1_grf>; ++ status = "disabled"; ++ }; ++ + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.12/001-08-v6.15-arm64-dts-rockchip-Add-HDMI1-node-on-RK3588.patch b/target/linux/rockchip/patches-6.12/001-08-v6.15-arm64-dts-rockchip-Add-HDMI1-node-on-RK3588.patch new file mode 100644 index 0000000000..26672d90b4 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-08-v6.15-arm64-dts-rockchip-Add-HDMI1-node-on-RK3588.patch @@ -0,0 +1,63 @@ +From bed6964e779b5853de042da14320edf9f79506fe Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Wed, 11 Dec 2024 01:06:16 +0200 +Subject: arm64: dts: rockchip: Add HDMI1 node on RK3588 + +Add support for the second HDMI TX port found on RK3588 SoC. + +Signed-off-by: Cristian Ciocaltea +Tested-by: Jagan Teki # edgeble-6tops-modules +Tested-by: Alexandre ARNOUD +Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-3-02cdca22ff68@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +@@ -140,6 +140,47 @@ + status = "disabled"; + }; + ++ hdmi1: hdmi@fdea0000 { ++ compatible = "rockchip,rk3588-dw-hdmi-qp"; ++ reg = <0x0 0xfdea0000 0x0 0x20000>; ++ clocks = <&cru PCLK_HDMITX1>, ++ <&cru CLK_HDMITX1_EARC>, ++ <&cru CLK_HDMITX1_REF>, ++ <&cru MCLK_I2S6_8CH_TX>, ++ <&cru CLK_HDMIHDP1>, ++ <&cru HCLK_VO1>; ++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "avp", "cec", "earc", "main", "hpd"; ++ phys = <&hdptxphy1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; ++ reset-names = "ref", "hdp"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo-grf = <&vo1_grf>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi1_in: port@0 { ++ reg = <0>; ++ }; ++ ++ hdmi1_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; diff --git a/target/linux/rockchip/patches-6.12/001-09-v6.15-arm64-dts-rockchip-Enable-HDMI1-PHY-clk-provider-on-.patch b/target/linux/rockchip/patches-6.12/001-09-v6.15-arm64-dts-rockchip-Enable-HDMI1-PHY-clk-provider-on-.patch new file mode 100644 index 0000000000..3503f1a6e9 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-09-v6.15-arm64-dts-rockchip-Enable-HDMI1-PHY-clk-provider-on-.patch @@ -0,0 +1,27 @@ +From aadaa27956e3430217d9e6b8af5880e39b05b961 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 23 Feb 2025 11:31:39 +0200 +Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 + +Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock +provider support"), the HDMI PHY PLL can be used as an alternative and +more accurate pixel clock source for VOP2 to improve display modes +handling on RK3588 SoC. + +Add the missing #clock-cells property to allow using the clock provider +functionality of HDMI1 PHY. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +@@ -446,6 +446,7 @@ + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; ++ #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, diff --git a/target/linux/rockchip/patches-6.12/001-10-v6.15-arm64-dts-rockchip-Add-HDMI1-PHY-PLL-clock-source-to.patch b/target/linux/rockchip/patches-6.12/001-10-v6.15-arm64-dts-rockchip-Add-HDMI1-PHY-PLL-clock-source-to.patch new file mode 100644 index 0000000000..eec7d0ad10 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-10-v6.15-arm64-dts-rockchip-Add-HDMI1-PHY-PLL-clock-source-to.patch @@ -0,0 +1,48 @@ +From b2e668a60ed866ba960acb5310d1fb6bf81d154f Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 23 Feb 2025 11:31:40 +0200 +Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on + RK3588 + +VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and +more accurate pixel clock source to improve handling of display modes up +to 4K@60Hz on video ports 0, 1 and 2. + +The HDMI1 PHY PLL clock source cannot be added directly to vop node in +rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an +optional feature and its PHY node belongs to a separate (extra) DT file. + +Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its +clocks & clock-names properties in the extra DT file. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +@@ -509,3 +509,24 @@ + status = "disabled"; + }; + }; ++ ++&vop { ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, ++ <&cru DCLK_VOP2>, ++ <&cru DCLK_VOP3>, ++ <&cru PCLK_VOP_ROOT>, ++ <&hdptxphy0>, ++ <&hdptxphy1>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3", ++ "pclk_vop", ++ "pll_hdmiphy0", ++ "pll_hdmiphy1"; ++}; diff --git a/target/linux/rockchip/patches-6.12/001-11-v6.15-arm64-dts-rockchip-Add-rng-node-to-RK3588.patch b/target/linux/rockchip/patches-6.12/001-11-v6.15-arm64-dts-rockchip-Add-rng-node-to-RK3588.patch new file mode 100644 index 0000000000..1d955f8c14 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-11-v6.15-arm64-dts-rockchip-Add-rng-node-to-RK3588.patch @@ -0,0 +1,34 @@ +From 6ee0b9ad3995ee5fa229035c69013b7dd0d3634b Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 4 Feb 2025 16:35:51 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add rng node to RK3588 + +Add the RK3588's standalone hardware random number generator node to its +device tree, and enable it. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20250204-rk3588-trng-submission-v2-6-608172b6fd91@collabora.com +[changed reset-id to its numeric value while the constant makes its + way through the crypto tree] +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -1921,6 +1921,14 @@ + status = "disabled"; + }; + ++ rng@fe378000 { ++ compatible = "rockchip,rk3588-rng"; ++ reg = <0x0 0xfe378000 0x0 0x200>; ++ interrupts = ; ++ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; ++ resets = <&scmi_reset 48>; ++ }; ++ + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.12/001-12-v6.15-arm64-dts-rockchip-Add-HDMI-audio-outputs-for-rk3588.patch b/target/linux/rockchip/patches-6.12/001-12-v6.15-arm64-dts-rockchip-Add-HDMI-audio-outputs-for-rk3588.patch new file mode 100644 index 0000000000..3e4ba5bf10 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-12-v6.15-arm64-dts-rockchip-Add-HDMI-audio-outputs-for-rk3588.patch @@ -0,0 +1,91 @@ +From b8c6c136971c0e9750eec89f367529b2854d3a3c Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Mon, 17 Feb 2025 16:47:41 -0500 +Subject: arm64: dts: rockchip: Add HDMI audio outputs for rk3588 + +For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node +as CODEC and the i2s5 device as CPU. + +Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is +i2s6, but only added in the rk3588-extra.dtsi device tree as the second +TX HDMI port is not available on base versions of the SoC. + +The simple-audio-card,mclk-fs value is set to 128 as it is done in +the downstream driver. + +The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so +that they can be used as audio codec nodes. + +Tested-by: Quentin Schulz # RK3588 Tiger Haikou +Signed-off-by: Detlev Casanova +Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") +Signed-off-by: Kuninori Morimoto +Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -382,6 +382,22 @@ + }; + }; + ++ hdmi0_sound: hdmi0-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,name = "hdmi0"; ++ status = "disabled"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi0>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s5_8ch>; ++ }; ++ }; ++ + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; +@@ -1396,6 +1412,7 @@ + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; ++ #sound-dai-cells = <0>; + status = "disabled"; + + ports { +--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +@@ -7,6 +7,22 @@ + #include "rk3588-extra-pinctrl.dtsi" + + / { ++ hdmi1_sound: hdmi1-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,name = "hdmi1"; ++ status = "disabled"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi1>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s6_8ch>; ++ }; ++ }; ++ + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; +@@ -165,6 +181,7 @@ + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; ++ #sound-dai-cells = <0>; + status = "disabled"; + + ports { diff --git a/target/linux/rockchip/patches-6.12/001-13-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/001-13-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch new file mode 100644 index 0000000000..5ad1c88d6d --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-13-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch @@ -0,0 +1,46 @@ +From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Feb 2025 19:58:11 +0100 +Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for + RK3588 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enabling the GPU power domain requires that the GPU regulator is +enabled. The regulator is enabled at boot time, but gets disabled +automatically when there are no users. + +This means the system might run into a failure state hanging the +whole system for the following use cases: + + * if the GPU driver is being probed late (e.g. build as a + module and firmware is not in initramfs), the regulator + might already have been disabled. In that case the power + domain is enabled before the regulator. + * unbinding the GPU driver will disable the PM domain and + the regulator. When the driver is bound again, the PM + domain will be enabled before the regulator and error + appears. + +Avoid this by adding an explicit regulator dependency to the +power domain. + +Tested-by: Heiko Stuebner +Reported-by: Adrián Martínez Larumbe +Tested-by: Adrian Larumbe # On Rock 5B +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -880,7 +880,7 @@ + }; + }; + /* These power domains are grouped by VD_GPU */ +- power-domain@RK3588_PD_GPU { ++ pd_gpu: power-domain@RK3588_PD_GPU { + reg = ; + clocks = <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, diff --git a/target/linux/rockchip/patches-6.12/001-14-v6.15-arm64-dts-rockchip-change-rng-reset-id-back-to-its-c.patch b/target/linux/rockchip/patches-6.12/001-14-v6.15-arm64-dts-rockchip-change-rng-reset-id-back-to-its-c.patch new file mode 100644 index 0000000000..91045bc80e --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-14-v6.15-arm64-dts-rockchip-change-rng-reset-id-back-to-its-c.patch @@ -0,0 +1,25 @@ +From 55a43c346d24434e46ef7fcc09a9df8179c346e4 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Sun, 16 Feb 2025 16:27:42 +0100 +Subject: [PATCH] arm64: dts: rockchip: change rng reset id back to its + constant value + +With the binding header now providing the SCMI_SRST_H_TRNG_NS constant, +switch back to it from the temporary numeric value. + +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -1943,7 +1943,7 @@ + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = ; + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; +- resets = <&scmi_reset 48>; ++ resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; + }; + + i2s0_8ch: i2s@fe470000 { diff --git a/target/linux/rockchip/patches-6.12/001-15-v6.15-arm64-dts-rockchip-Add-device-tree-support-for-HDMI-.patch b/target/linux/rockchip/patches-6.12/001-15-v6.15-arm64-dts-rockchip-Add-device-tree-support-for-HDMI-.patch new file mode 100644 index 0000000000..f269185be5 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/001-15-v6.15-arm64-dts-rockchip-Add-device-tree-support-for-HDMI-.patch @@ -0,0 +1,88 @@ +From 0327238991ba2d1de25e1116b1c064f433e45b8d Mon Sep 17 00:00:00 2001 +From: Shreeya Patel +Date: Fri, 7 Mar 2025 12:18:56 +0300 +Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller + +Add device tree support for Synopsys DesignWare HDMI RX +Controller. + +Reviewed-by: Dmitry Osipenko +Tested-by: Dmitry Osipenko +Co-developed-by: Dingxian Wen +Signed-off-by: Dingxian Wen +Signed-off-by: Shreeya Patel +Signed-off-by: Dmitry Osipenko +Link: https://lore.kernel.org/r/20250307091857.646581-2-dmitry.osipenko@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +@@ -23,6 +23,30 @@ + }; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* ++ * The 4k HDMI capture controller works only with 32bit ++ * phys addresses and doesn't support IOMMU. HDMI RX CMA ++ * must be reserved below 4GB. ++ * The size of 160MB was determined as follows: ++ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB ++ * To ensure sufficient support for practical use-cases, ++ * we doubled the 66MB value. ++ */ ++ hdmi_receiver_cma: hdmi-receiver-cma { ++ compatible = "shared-dma-pool"; ++ alloc-ranges = <0x0 0x0 0x0 0xffffffff>; ++ size = <0x0 (160 * 0x100000)>; /* 160MiB */ ++ alignment = <0x0 0x40000>; /* 64K */ ++ no-map; ++ status = "disabled"; ++ }; ++ }; ++ + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; +@@ -198,6 +222,37 @@ + }; + }; + ++ hdmi_receiver: hdmi_receiver@fdee0000 { ++ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; ++ reg = <0x0 0xfdee0000 0x0 0x6000>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "cec", "hdmi", "dma"; ++ clocks = <&cru ACLK_HDMIRX>, ++ <&cru CLK_HDMIRX_AUD>, ++ <&cru CLK_CR_PARA>, ++ <&cru PCLK_HDMIRX>, ++ <&cru CLK_HDMIRX_REF>, ++ <&cru PCLK_S_HDMIRX>, ++ <&cru HCLK_VO1>; ++ clock-names = "aclk", ++ "audio", ++ "cr_para", ++ "pclk", ++ "ref", ++ "hclk_s_hdmirx", ++ "hclk_vo1"; ++ memory-region = <&hdmi_receiver_cma>; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, ++ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; ++ reset-names = "axi", "apb", "ref", "biu"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo1-grf = <&vo1_grf>; ++ status = "disabled"; ++ }; ++ + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; diff --git a/target/linux/rockchip/patches-6.12/002-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch b/target/linux/rockchip/patches-6.12/002-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch deleted file mode 100644 index c4bbc314cd..0000000000 --- a/target/linux/rockchip/patches-6.12/002-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 3ca743f8a5b568dc5e5d5f1bab0298a4a43c2360 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Fri, 27 Sep 2024 14:42:22 +0200 -Subject: arm64: dts: rockchip: Switch to hp-det-gpios - -Replace the deprecated "hp-det-gpio" property by "hp-det-gpios" in Audio -Graph Card and Realtek RT5651 Audio Codec device nodes. - -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/717e7c9527139c3a3e5246dd367a3ad98c5c81b6.1727438777.git.geert+renesas@glider.be -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -32,7 +32,7 @@ - "Headphones", "HPOR"; - - dais = <&i2s0_8ch_p0>; -- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; -+ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - }; diff --git a/target/linux/rockchip/patches-6.12/002-01-v6.13-arm64-dts-rockchip-add-and-enable-gpu-node-for-Radxa.patch b/target/linux/rockchip/patches-6.12/002-01-v6.13-arm64-dts-rockchip-add-and-enable-gpu-node-for-Radxa.patch new file mode 100644 index 0000000000..55cec3dcf7 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/002-01-v6.13-arm64-dts-rockchip-add-and-enable-gpu-node-for-Radxa.patch @@ -0,0 +1,25 @@ +From a98053d098c4ad91a45a3a55604d9574dfc6ffdb Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Sat, 19 Oct 2024 02:50:08 +0000 +Subject: arm64: dts: rockchip: add and enable gpu node for Radxa ROCK 5A + +add gpu node to make it usable on Radxa ROCK 5A. + +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20241019025008.852-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -166,6 +166,11 @@ + cpu-supply = <&vdd_cpu_lit_s0>; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; diff --git a/target/linux/rockchip/patches-6.12/002-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5a.patch b/target/linux/rockchip/patches-6.12/002-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5a.patch new file mode 100644 index 0000000000..c305197183 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/002-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5a.patch @@ -0,0 +1,90 @@ +From f57a8daf6bbd8e71f16693ad6d8421cb881c7fe0 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Tue, 22 Oct 2024 19:04:42 +0300 +Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5a + +Add the necessary DT changes to enable HDMI0 on Radxa ROCK 5A. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20241022-rk3588-hdmi0-dt-v3-1-3cc981e89afb@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -5,6 +5,7 @@ + #include + #include + #include ++#include + #include "rk3588s.dtsi" + + / { +@@ -35,6 +36,17 @@ + stdout-path = "serial2:1500000n8"; + }; + ++ hdmi0-con { ++ compatible = "hdmi-connector"; ++ type = "d"; ++ ++ port { ++ hdmi0_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -301,6 +313,31 @@ + status = "okay"; + }; + ++&hdmi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim0_tx0_cec ++ &hdmim1_tx0_hpd ++ &hdmim0_tx0_scl ++ &hdmim0_tx0_sda>; ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi0_con_in>; ++ }; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ + &mdio1 { + rgmii_phy1: ethernet-phy@1 { + /* RTL8211F */ +@@ -793,3 +830,18 @@ + &usb_host2_xhci { + status = "okay"; + }; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.12/002-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch b/target/linux/rockchip/patches-6.12/002-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch deleted file mode 100644 index ee6fdf67db..0000000000 --- a/target/linux/rockchip/patches-6.12/002-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch +++ /dev/null @@ -1,86 +0,0 @@ -From c8152f79c2dd8039e14073be76fdbce8760175da Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 19 Oct 2024 13:12:11 +0300 -Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5b - -Add the necessary DT changes to enable HDMI0 on Radxa ROCK 5B. - -Tested-by: FUKAUMI Naoki -Signed-off-by: Cristian Ciocaltea -Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-2-466cd80e8ff9@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3588.dtsi" - - / { -@@ -37,6 +38,17 @@ - pinctrl-0 = <&hp_detect>; - }; - -+ hdmi0-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi0_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -192,6 +204,26 @@ - status = "okay"; - }; - -+&hdmi0 { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi0_con_in>; -+ }; -+}; -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -858,3 +890,18 @@ - &usb_host2_xhci { - status = "okay"; - }; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.12/002-03-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch b/target/linux/rockchip/patches-6.12/002-03-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch deleted file mode 100644 index d276b305d0..0000000000 --- a/target/linux/rockchip/patches-6.12/002-03-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 5c96e63301978f4657c9082c55a066763c8db7b1 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sat, 5 Oct 2024 22:40:12 +0200 -Subject: arm64: dts: rockchip: adapt regulator nodenames to preferred form - -The preferred nodename for fixed-regulators has changed to -pattern: '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$' - -Fix all Rockchip DT regulator nodenames. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/0ae40493-93e9-40cd-9ca9-990ae064f21a@gmail.com -[adapted rebased on top of a number of other changes and included - neu6a-wifi + wolfvision-pf5-io-expander overlays] -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -84,7 +84,7 @@ - shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - }; - -- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { -+ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -@@ -99,7 +99,7 @@ - vin-supply = <&vcc5v0_sys>; - }; - -- vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { -+ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie2x1l2"; - regulator-min-microvolt = <3300000>; -@@ -108,7 +108,7 @@ - vin-supply = <&vcc_3v3_s3>; - }; - -- vcc3v3_pcie30: vcc3v3-pcie30-regulator { -+ vcc3v3_pcie30: regulator-vcc3v3-pcie30 { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -@@ -121,7 +121,7 @@ - vin-supply = <&vcc5v0_sys>; - }; - -- vcc5v0_host: vcc5v0-host-regulator { -+ vcc5v0_host: regulator-vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; -@@ -135,7 +135,7 @@ - vin-supply = <&vcc5v0_sys>; - }; - -- vcc5v0_sys: vcc5v0-sys-regulator { -+ vcc5v0_sys: regulator-vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; -@@ -144,7 +144,7 @@ - regulator-max-microvolt = <5000000>; - }; - -- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; diff --git a/target/linux/rockchip/patches-6.12/002-03-v6.13-arm64-dts-rockchip-sort-rk3588s-rock5a-properly-in-M.patch b/target/linux/rockchip/patches-6.12/002-03-v6.13-arm64-dts-rockchip-sort-rk3588s-rock5a-properly-in-M.patch new file mode 100644 index 0000000000..3cab321f25 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/002-03-v6.13-arm64-dts-rockchip-sort-rk3588s-rock5a-properly-in-M.patch @@ -0,0 +1,21 @@ +From 9f3360b42bb5b0c99073827a3dd81d2568b2a4ed Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Mon, 28 Oct 2024 07:23:44 +0000 +Subject: arm64: dts: rockchip: sort rk3588s-rock5a properly in Makefile + +sort target dtb files properly in Makefile for rockchip. + +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20241028072344.1514-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -151,6 +151,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-i + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb +-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb diff --git a/target/linux/rockchip/patches-6.12/002-04-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch b/target/linux/rockchip/patches-6.12/002-04-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch new file mode 100644 index 0000000000..d485ebf448 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/002-04-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch @@ -0,0 +1,72 @@ +From 5c96e63301978f4657c9082c55a066763c8db7b1 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Sat, 5 Oct 2024 22:40:12 +0200 +Subject: arm64: dts: rockchip: adapt regulator nodenames to preferred form + +The preferred nodename for fixed-regulators has changed to +pattern: '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$' + +Fix all Rockchip DT regulator nodenames. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/0ae40493-93e9-40cd-9ca9-990ae064f21a@gmail.com +[adapted rebased on top of a number of other changes and included + neu6a-wifi + wolfvision-pf5-io-expander overlays] +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -68,7 +68,7 @@ + #cooling-cells = <2>; + }; + +- vcc12v_dcin: vcc12v-dcin-regulator { ++ vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; +@@ -77,7 +77,7 @@ + regulator-max-microvolt = <12000000>; + }; + +- vcc3v3_wf: vcc3v3-wf-regulator { ++ vcc3v3_wf: regulator-vcc3v3-wf { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_wf"; + regulator-min-microvolt = <3300000>; +@@ -89,7 +89,7 @@ + vin-supply = <&vcc5v0_sys>; + }; + +- vcc5v0_host: vcc5v0-host-regulator { ++ vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; +@@ -103,7 +103,7 @@ + vin-supply = <&vcc5v0_sys>; + }; + +- vcc5v0_sys: vcc5v0-sys-regulator { ++ vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; +@@ -113,7 +113,7 @@ + vin-supply = <&vcc12v_dcin>; + }; + +- vcc_5v0: vcc-5v0-regulator { ++ vcc_5v0: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; +@@ -127,7 +127,7 @@ + vin-supply = <&vcc5v0_sys>; + }; + +- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; diff --git a/target/linux/rockchip/patches-6.12/002-04-v6.13-arm64-dts-rockchip-rename-rfkill-label-for-Radxa-ROC.patch b/target/linux/rockchip/patches-6.12/002-04-v6.13-arm64-dts-rockchip-rename-rfkill-label-for-Radxa-ROC.patch deleted file mode 100644 index 2066e5c57e..0000000000 --- a/target/linux/rockchip/patches-6.12/002-04-v6.13-arm64-dts-rockchip-rename-rfkill-label-for-Radxa-ROC.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 2ddd93481bce86c6a46223f45accdb3b149a43e4 Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Thu, 28 Nov 2024 12:06:30 +0000 -Subject: arm64: dts: rockchip: rename rfkill label for Radxa ROCK 5B - -on ROCK 5B, there is no PCIe slot, instead there is a M.2 slot. -rfkill pin is not exclusive to PCIe devices, there is SDIO Wi-Fi -devices. - -rename rfkill label from "rfkill-pcie-wlan" to "rfkill-m2-wlan", it -matches with rfkill-bt. - -Fixes: 82d40b141a4c ("arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b") -Reviewed-by: Dragan Simic -Signed-off-by: FUKAUMI Naoki -Fixes: 82d40b141a4c ("arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b") -Link: https://lore.kernel.org/r/20241128120631.37458-1-naoki@radxa.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -72,7 +72,7 @@ - - rfkill { - compatible = "rfkill-gpio"; -- label = "rfkill-pcie-wlan"; -+ label = "rfkill-m2-wlan"; - radio-type = "wlan"; - shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - }; diff --git a/target/linux/rockchip/patches-6.12/002-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch b/target/linux/rockchip/patches-6.12/002-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch index ee6f743b71..0e30195847 100644 --- a/target/linux/rockchip/patches-6.12/002-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch +++ b/target/linux/rockchip/patches-6.12/002-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch @@ -13,9 +13,9 @@ Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.co the hdptxphy0-as-dclk source I just added] Signed-off-by: Heiko Stuebner ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -220,7 +220,7 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -334,7 +334,7 @@ }; }; diff --git a/target/linux/rockchip/patches-6.12/002-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/002-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch new file mode 100644 index 0000000000..c11bc86c9d --- /dev/null +++ b/target/linux/rockchip/patches-6.12/002-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch @@ -0,0 +1,48 @@ +From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Feb 2025 19:58:11 +0100 +Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for + RK3588 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enabling the GPU power domain requires that the GPU regulator is +enabled. The regulator is enabled at boot time, but gets disabled +automatically when there are no users. + +This means the system might run into a failure state hanging the +whole system for the following use cases: + + * if the GPU driver is being probed late (e.g. build as a + module and firmware is not in initramfs), the regulator + might already have been disabled. In that case the power + domain is enabled before the regulator. + * unbinding the GPU driver will disable the PM domain and + the regulator. When the driver is bound again, the PM + domain will be enabled before the regulator and error + appears. + +Avoid this by adding an explicit regulator dependency to the +power domain. + +Tested-by: Heiko Stuebner +Reported-by: Adrián Martínez Larumbe +Tested-by: Adrian Larumbe # On Rock 5B +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -359,6 +359,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + io_led: io-led { diff --git a/target/linux/rockchip/patches-6.12/002-06-v6.15-arm64-dts-rockchip-Enable-HDMI1-on-rock-5b.patch b/target/linux/rockchip/patches-6.12/002-06-v6.15-arm64-dts-rockchip-Enable-HDMI1-on-rock-5b.patch deleted file mode 100644 index 542a6c375d..0000000000 --- a/target/linux/rockchip/patches-6.12/002-06-v6.15-arm64-dts-rockchip-Enable-HDMI1-on-rock-5b.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 77cea7ca13680e14119a3b9635c7ef16cd7ee44e Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Wed, 11 Dec 2024 01:06:17 +0200 -Subject: arm64: dts: rockchip: Enable HDMI1 on rock-5b - -Add the necessary DT changes to enable the second HDMI output port on -Radxa ROCK 5B. - -While at it, switch the position of &vop_mmu and @vop to maintain the -alphabetical order. - -Signed-off-by: Cristian Ciocaltea -Tested-by: Alexandre ARNOUD -Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-4-02cdca22ff68@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -49,6 +49,17 @@ - }; - }; - -+ hdmi1-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi1_con_in: endpoint { -+ remote-endpoint = <&hdmi1_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -220,10 +231,32 @@ - }; - }; - -+&hdmi1 { -+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd -+ &hdmim1_tx1_scl &hdmim1_tx1_sda>; -+ status = "okay"; -+}; -+ -+&hdmi1_in { -+ hdmi1_in_vp1: endpoint { -+ remote-endpoint = <&vp1_out_hdmi1>; -+ }; -+}; -+ -+&hdmi1_out { -+ hdmi1_out_con: endpoint { -+ remote-endpoint = <&hdmi1_con_in>; -+ }; -+}; -+ - &hdptxphy0 { - status = "okay"; - }; - -+&hdptxphy1 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -891,11 +924,11 @@ - status = "okay"; - }; - --&vop_mmu { -+&vop { - status = "okay"; - }; - --&vop { -+&vop_mmu { - status = "okay"; - }; - -@@ -905,3 +938,10 @@ - remote-endpoint = <&hdmi0_in_vp0>; - }; - }; -+ -+&vp1 { -+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -+ reg = ; -+ remote-endpoint = <&hdmi1_in_vp1>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.12/002-07-v6.15-arm64-dts-rockchip-Enable-HDMI-audio-outputs-for-Roc.patch b/target/linux/rockchip/patches-6.12/002-07-v6.15-arm64-dts-rockchip-Enable-HDMI-audio-outputs-for-Roc.patch deleted file mode 100644 index 2392f45d79..0000000000 --- a/target/linux/rockchip/patches-6.12/002-07-v6.15-arm64-dts-rockchip-Enable-HDMI-audio-outputs-for-Roc.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 97aa62ed1e970bf8aa9f57e87c946a95fa3d5bef Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Mon, 17 Feb 2025 16:47:42 -0500 -Subject: arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5B - -HDMI audio is available on the Rock 5B HDMI TX ports. -Enable it for both ports. - -Reviewed-by: Quentin Schulz -Signed-off-by: Detlev Casanova -Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") -Signed-off-by: Kuninori Morimoto -Link: https://lore.kernel.org/r/20250217215641.372723-4-detlev.casanova@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -231,6 +231,10 @@ - }; - }; - -+&hdmi0_sound { -+ status = "okay"; -+}; -+ - &hdmi1 { - pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd - &hdmim1_tx1_scl &hdmim1_tx1_sda>; -@@ -249,6 +253,10 @@ - }; - }; - -+&hdmi1_sound { -+ status = "okay"; -+}; -+ - &hdptxphy0 { - status = "okay"; - }; -@@ -351,6 +359,14 @@ - }; - }; - -+&i2s5_8ch { -+ status = "okay"; -+}; -+ -+&i2s6_8ch { -+ status = "okay"; -+}; -+ - &package_thermal { - polling-delay = <1000>; - diff --git a/target/linux/rockchip/patches-6.12/002-08-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/002-08-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch deleted file mode 100644 index 13de83b80c..0000000000 --- a/target/linux/rockchip/patches-6.12/002-08-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch +++ /dev/null @@ -1,48 +0,0 @@ -From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 20 Feb 2025 19:58:11 +0100 -Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for - RK3588 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enabling the GPU power domain requires that the GPU regulator is -enabled. The regulator is enabled at boot time, but gets disabled -automatically when there are no users. - -This means the system might run into a failure state hanging the -whole system for the following use cases: - - * if the GPU driver is being probed late (e.g. build as a - module and firmware is not in initramfs), the regulator - might already have been disabled. In that case the power - domain is enabled before the regulator. - * unbinding the GPU driver will disable the PM domain and - the regulator. When the driver is bound again, the PM - domain will be enabled before the regulator and error - appears. - -Avoid this by adding an explicit regulator dependency to the -power domain. - -Tested-by: Heiko Stuebner -Reported-by: Adrián Martínez Larumbe -Tested-by: Adrian Larumbe # On Rock 5B -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -425,6 +425,10 @@ - status = "okay"; - }; - -+&pd_gpu { -+ domain-supply = <&vdd_gpu_s0>; -+}; -+ - &pinctrl { - hym8563 { - hym8563_int: hym8563-int { diff --git a/target/linux/rockchip/patches-6.12/002-09-v6.15-arm64-dts-rockchip-Enable-HDMI-receiver-on-rock-5b.patch b/target/linux/rockchip/patches-6.12/002-09-v6.15-arm64-dts-rockchip-Enable-HDMI-receiver-on-rock-5b.patch deleted file mode 100644 index 897d043364..0000000000 --- a/target/linux/rockchip/patches-6.12/002-09-v6.15-arm64-dts-rockchip-Enable-HDMI-receiver-on-rock-5b.patch +++ /dev/null @@ -1,47 +0,0 @@ -From c62d8fdb27391ee72bfdf53328463813997844f1 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 7 Mar 2025 12:18:57 +0300 -Subject: arm64: dts: rockchip: Enable HDMI receiver on rock-5b - -The Rock 5B has a Micro HDMI port, which can be used for receiving -HDMI data. This enables support for it. - -Signed-off-by: Sebastian Reichel -Signed-off-by: Shreeya Patel -Signed-off-by: Dmitry Osipenko -Link: https://lore.kernel.org/r/20250307091857.646581-3-dmitry.osipenko@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -257,6 +257,17 @@ - status = "okay"; - }; - -+&hdmi_receiver_cma { -+ status = "okay"; -+}; -+ -+&hdmi_receiver { -+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ - &hdptxphy0 { - status = "okay"; - }; -@@ -430,6 +441,12 @@ - }; - - &pinctrl { -+ hdmirx { -+ hdmirx_hpd: hdmirx-5v-detection { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.12/002-10-v6.16-arm64-dts-rockchip-Add-vcc-supply-to-SPI-flash-on-rk.patch b/target/linux/rockchip/patches-6.12/002-10-v6.16-arm64-dts-rockchip-Add-vcc-supply-to-SPI-flash-on-rk.patch deleted file mode 100644 index 92ad95c4a3..0000000000 --- a/target/linux/rockchip/patches-6.12/002-10-v6.16-arm64-dts-rockchip-Add-vcc-supply-to-SPI-flash-on-rk.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 425af91c58023a8924cc2330384e040d388adc4e Mon Sep 17 00:00:00 2001 -From: Diederik de Haas -Date: Fri, 25 Apr 2025 10:44:44 +0200 -Subject: arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3588-rock-5b - -The Radxa Rock 5B component placement document identifies the SPI Nor -Flash chip as 'U4300' which is described on page 25 of the Schematic -v1.45. There we can see that the VCC connector is connected to the -VCC_3V3_S3 power source. - -This fixes the following warning: - - spi-nor spi5.0: supply vcc not found, using dummy regulator - -Signed-off-by: Diederik de Haas -Link: https://lore.kernel.org/r/20250425092601.56549-5-didi.debian@cknow.org -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -562,6 +562,7 @@ - spi-max-frequency = <104000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; -+ vcc-supply = <&vcc_3v3_s3>; - }; - }; - diff --git a/target/linux/rockchip/patches-6.12/002-11-v6.16-arm64-dts-rockchip-move-rock-5b-to-include-file.patch b/target/linux/rockchip/patches-6.12/002-11-v6.16-arm64-dts-rockchip-move-rock-5b-to-include-file.patch deleted file mode 100644 index 7760f00de1..0000000000 --- a/target/linux/rockchip/patches-6.12/002-11-v6.16-arm64-dts-rockchip-move-rock-5b-to-include-file.patch +++ /dev/null @@ -1,1948 +0,0 @@ -From aadfbdcf7e1e7f3892e0e4bdcc3c9c7c9adfb723 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 8 May 2025 19:48:50 +0200 -Subject: arm64: dts: rockchip: move rock 5b to include file - -Radxa released some more boards, which are based on the original -Rock 5B. Move its board description into an include file to avoid -unnecessary duplication. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-1-677033cc1ac2@kernel.org -Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-2-677033cc1ac2@kernel.org - -[The original submission was split into two elements, renaming the file - and then moving some nodes around. This was done to make review easier - due to the diff being smaller. This commit is a squash of both of them - to facilitate bisectability and was also intended by the original author] -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -2,532 +2,11 @@ - - /dts-v1/; - --#include --#include --#include --#include "rk3588.dtsi" -+#include "rk3588-rock-5b.dtsi" - - / { - model = "Radxa ROCK 5B"; - compatible = "radxa,rock-5b", "rockchip,rk3588"; -- -- aliases { -- mmc0 = &sdhci; -- mmc1 = &sdmmc; -- mmc2 = &sdio; -- }; -- -- chosen { -- stdout-path = "serial2:1500000n8"; -- }; -- -- analog-sound { -- compatible = "audio-graph-card"; -- label = "rk3588-es8316"; -- -- widgets = "Microphone", "Mic Jack", -- "Headphone", "Headphones"; -- -- routing = "MIC2", "Mic Jack", -- "Headphones", "HPOL", -- "Headphones", "HPOR"; -- -- dais = <&i2s0_8ch_p0>; -- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&hp_detect>; -- }; -- -- hdmi0-con { -- compatible = "hdmi-connector"; -- type = "a"; -- -- port { -- hdmi0_con_in: endpoint { -- remote-endpoint = <&hdmi0_out_con>; -- }; -- }; -- }; -- -- hdmi1-con { -- compatible = "hdmi-connector"; -- type = "a"; -- -- port { -- hdmi1_con_in: endpoint { -- remote-endpoint = <&hdmi1_out_con>; -- }; -- }; -- }; -- -- leds { -- compatible = "gpio-leds"; -- pinctrl-names = "default"; -- pinctrl-0 = <&led_rgb_b>; -- -- led_rgb_b { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; -- }; -- }; -- -- fan: pwm-fan { -- compatible = "pwm-fan"; -- cooling-levels = <0 120 150 180 210 240 255>; -- fan-supply = <&vcc5v0_sys>; -- pwms = <&pwm1 0 50000 0>; -- #cooling-cells = <2>; -- }; -- -- rfkill { -- compatible = "rfkill-gpio"; -- label = "rfkill-m2-wlan"; -- radio-type = "wlan"; -- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -- }; -- -- rfkill-bt { -- compatible = "rfkill-gpio"; -- label = "rfkill-m2-bt"; -- radio-type = "bluetooth"; -- shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -- }; -- -- vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_0_vcc3v3_en>; -- regulator-name = "vcc3v3_pcie2x1l0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- startup-delay-us = <50000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { -- compatible = "regulator-fixed"; -- regulator-name = "vcc3v3_pcie2x1l2"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- startup-delay-us = <5000>; -- vin-supply = <&vcc_3v3_s3>; -- }; -- -- vcc3v3_pcie30: regulator-vcc3v3-pcie30 { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_vcc3v3_en>; -- regulator-name = "vcc3v3_pcie30"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- startup-delay-us = <5000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc5v0_host: regulator-vcc5v0-host { -- compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_host"; -- regulator-boot-on; -- regulator-always-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- enable-active-high; -- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&vcc5v0_host_en>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc5v0_sys: regulator-vcc5v0-sys { -- compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_sys"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- }; -- -- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { -- compatible = "regulator-fixed"; -- regulator-name = "vcc_1v1_nldo_s3"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1100000>; -- regulator-max-microvolt = <1100000>; -- vin-supply = <&vcc5v0_sys>; -- }; --}; -- --&combphy0_ps { -- status = "okay"; --}; -- --&combphy1_ps { -- status = "okay"; --}; -- --&combphy2_psu { -- status = "okay"; --}; -- --&cpu_b0 { -- cpu-supply = <&vdd_cpu_big0_s0>; --}; -- --&cpu_b1 { -- cpu-supply = <&vdd_cpu_big0_s0>; --}; -- --&cpu_b2 { -- cpu-supply = <&vdd_cpu_big1_s0>; --}; -- --&cpu_b3 { -- cpu-supply = <&vdd_cpu_big1_s0>; --}; -- --&cpu_l0 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l1 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l2 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l3 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&gpu { -- mali-supply = <&vdd_gpu_s0>; -- status = "okay"; --}; -- --&hdmi0 { -- status = "okay"; --}; -- --&hdmi0_in { -- hdmi0_in_vp0: endpoint { -- remote-endpoint = <&vp0_out_hdmi0>; -- }; --}; -- --&hdmi0_out { -- hdmi0_out_con: endpoint { -- remote-endpoint = <&hdmi0_con_in>; -- }; --}; -- --&hdmi0_sound { -- status = "okay"; --}; -- --&hdmi1 { -- pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd -- &hdmim1_tx1_scl &hdmim1_tx1_sda>; -- status = "okay"; --}; -- --&hdmi1_in { -- hdmi1_in_vp1: endpoint { -- remote-endpoint = <&vp1_out_hdmi1>; -- }; --}; -- --&hdmi1_out { -- hdmi1_out_con: endpoint { -- remote-endpoint = <&hdmi1_con_in>; -- }; --}; -- --&hdmi1_sound { -- status = "okay"; --}; -- --&hdmi_receiver_cma { -- status = "okay"; --}; -- --&hdmi_receiver { -- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -- pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; -- pinctrl-names = "default"; -- status = "okay"; --}; -- --&hdptxphy0 { -- status = "okay"; --}; -- --&hdptxphy1 { -- status = "okay"; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0m2_xfer>; -- status = "okay"; -- -- vdd_cpu_big0_s0: regulator@42 { -- compatible = "rockchip,rk8602"; -- reg = <0x42>; -- fcs,suspend-voltage-selector = <1>; -- regulator-name = "vdd_cpu_big0_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <1050000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc5v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_cpu_big1_s0: regulator@43 { -- compatible = "rockchip,rk8603", "rockchip,rk8602"; -- reg = <0x43>; -- fcs,suspend-voltage-selector = <1>; -- regulator-name = "vdd_cpu_big1_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <1050000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc5v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; --}; -- --&i2c6 { -- status = "okay"; -- -- hym8563: rtc@51 { -- compatible = "haoyu,hym8563"; -- reg = <0x51>; -- #clock-cells = <0>; -- clock-output-names = "hym8563"; -- pinctrl-names = "default"; -- pinctrl-0 = <&hym8563_int>; -- interrupt-parent = <&gpio0>; -- interrupts = ; -- wakeup-source; -- }; --}; -- --&i2c7 { -- status = "okay"; -- -- es8316: audio-codec@11 { -- compatible = "everest,es8316"; -- reg = <0x11>; -- clocks = <&cru I2S0_8CH_MCLKOUT>; -- clock-names = "mclk"; -- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -- assigned-clock-rates = <12288000>; -- #sound-dai-cells = <0>; -- -- port { -- es8316_p0_0: endpoint { -- remote-endpoint = <&i2s0_8ch_p0_0>; -- }; -- }; -- }; --}; -- --&i2s0_8ch { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2s0_lrck -- &i2s0_mclk -- &i2s0_sclk -- &i2s0_sdi0 -- &i2s0_sdo0>; -- status = "okay"; -- -- i2s0_8ch_p0: port { -- i2s0_8ch_p0_0: endpoint { -- dai-format = "i2s"; -- mclk-fs = <256>; -- remote-endpoint = <&es8316_p0_0>; -- }; -- }; --}; -- --&i2s5_8ch { -- status = "okay"; --}; -- --&i2s6_8ch { -- status = "okay"; --}; -- --&package_thermal { -- polling-delay = <1000>; -- -- trips { -- package_fan0: package-fan0 { -- temperature = <55000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- -- package_fan1: package-fan1 { -- temperature = <65000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- }; -- -- cooling-maps { -- map0 { -- trip = <&package_fan0>; -- cooling-device = <&fan THERMAL_NO_LIMIT 1>; -- }; -- -- map1 { -- trip = <&package_fan1>; -- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -- }; -- }; --}; -- --&pcie2x1l0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_0_rst>; -- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; -- status = "okay"; --}; -- --&pcie2x1l2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_2_rst>; -- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; -- status = "okay"; --}; -- --&pcie30phy { -- status = "okay"; --}; -- --&pcie3x4 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_rst>; -- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie30>; -- status = "okay"; --}; -- --&pd_gpu { -- domain-supply = <&vdd_gpu_s0>; --}; -- --&pinctrl { -- hdmirx { -- hdmirx_hpd: hdmirx-5v-detection { -- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- hym8563 { -- hym8563_int: hym8563-int { -- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- leds { -- led_rgb_b: led-rgb-b { -- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- sound { -- hp_detect: hp-detect { -- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- pcie2 { -- pcie2_0_rst: pcie2-0-rst { -- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie2_0_vcc3v3_en: pcie2-0-vcc-en { -- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie2_2_rst: pcie2-2-rst { -- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- pcie3 { -- pcie3_rst: pcie3-rst { -- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie3_vcc3v3_en: pcie3-vcc3v3-en { -- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- usb { -- vcc5v0_host_en: vcc5v0-host-en { -- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; --}; -- --&pwm1 { -- status = "okay"; --}; -- --&saradc { -- vref-supply = <&avcc_1v8_s0>; -- status = "okay"; --}; -- --&sdhci { -- bus-width = <8>; -- no-sdio; -- no-sd; -- non-removable; -- mmc-hs400-1_8v; -- mmc-hs400-enhanced-strobe; -- status = "okay"; --}; -- --&sdmmc { -- max-frequency = <200000000>; -- no-sdio; -- no-mmc; -- bus-width = <4>; -- cap-mmc-highspeed; -- cap-sd-highspeed; -- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -- disable-wp; -- sd-uhs-sdr104; -- vmmc-supply = <&vcc_3v3_s3>; -- vqmmc-supply = <&vccio_sd_s0>; -- status = "okay"; - }; - - &sdio { -@@ -551,435 +30,23 @@ - status = "okay"; - }; - --&sfc { -- pinctrl-names = "default"; -- pinctrl-0 = <&fspim2_pins>; -- status = "okay"; -- -- flash@0 { -- compatible = "jedec,spi-nor"; -- reg = <0>; -- spi-max-frequency = <104000000>; -- spi-rx-bus-width = <4>; -- spi-tx-bus-width = <1>; -- vcc-supply = <&vcc_3v3_s3>; -- }; --}; -- - &uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; - status = "okay"; - }; - --&spi2 { -- status = "okay"; -- assigned-clocks = <&cru CLK_SPI2>; -- assigned-clock-rates = <200000000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -- num-cs = <1>; -- -- pmic@0 { -- compatible = "rockchip,rk806"; -- spi-max-frequency = <1000000>; -- reg = <0x0>; -- -- interrupt-parent = <&gpio0>; -- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -- -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -- <&rk806_dvs2_null>, <&rk806_dvs3_null>; -- -- system-power-controller; -- -- vcc1-supply = <&vcc5v0_sys>; -- vcc2-supply = <&vcc5v0_sys>; -- vcc3-supply = <&vcc5v0_sys>; -- vcc4-supply = <&vcc5v0_sys>; -- vcc5-supply = <&vcc5v0_sys>; -- vcc6-supply = <&vcc5v0_sys>; -- vcc7-supply = <&vcc5v0_sys>; -- vcc8-supply = <&vcc5v0_sys>; -- vcc9-supply = <&vcc5v0_sys>; -- vcc10-supply = <&vcc5v0_sys>; -- vcc11-supply = <&vcc_2v0_pldo_s3>; -- vcc12-supply = <&vcc5v0_sys>; -- vcc13-supply = <&vcc_1v1_nldo_s3>; -- vcc14-supply = <&vcc_1v1_nldo_s3>; -- vcca-supply = <&vcc5v0_sys>; -- -- gpio-controller; -- #gpio-cells = <2>; -- -- rk806_dvs1_null: dvs1-null-pins { -- pins = "gpio_pwrctrl1"; -- function = "pin_fun0"; -- }; -- -- rk806_dvs2_null: dvs2-null-pins { -- pins = "gpio_pwrctrl2"; -- function = "pin_fun0"; -- }; -- -- rk806_dvs3_null: dvs3-null-pins { -- pins = "gpio_pwrctrl3"; -- function = "pin_fun0"; -- }; -- -- regulators { -- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_gpu_s0"; -- regulator-enable-ramp-delay = <400>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_cpu_lit_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_log_s0: dcdc-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <675000>; -- regulator-max-microvolt = <750000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_log_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <750000>; -- }; -- }; -- -- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_vdenc_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_ddr_s0: dcdc-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <675000>; -- regulator-max-microvolt = <900000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_ddr_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <850000>; -- }; -- }; -- -- vdd2_ddr_s3: dcdc-reg6 { -- regulator-always-on; -- regulator-boot-on; -- regulator-name = "vdd2_ddr_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- }; -- }; -- -- vcc_2v0_pldo_s3: dcdc-reg7 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <2000000>; -- regulator-max-microvolt = <2000000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_2v0_pldo_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <2000000>; -- }; -- }; -- -- vcc_3v3_s3: dcdc-reg8 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-name = "vcc_3v3_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <3300000>; -- }; -- }; -- -- vddq_ddr_s0: dcdc-reg9 { -- regulator-always-on; -- regulator-boot-on; -- regulator-name = "vddq_ddr_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_1v8_s3: dcdc-reg10 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "vcc_1v8_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- avcc_1v8_s0: pldo-reg1 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "avcc_1v8_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_1v8_s0: pldo-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "vcc_1v8_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- avdd_1v2_s0: pldo-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1200000>; -- regulator-max-microvolt = <1200000>; -- regulator-name = "avdd_1v2_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_3v3_s0: pldo-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vcc_3v3_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vccio_sd_s0: pldo-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <3300000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vccio_sd_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- pldo6_s3: pldo-reg6 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "pldo6_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- vdd_0v75_s3: nldo-reg1 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "vdd_0v75_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <750000>; -- }; -- }; -- -- vdd_ddr_pll_s0: nldo-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-name = "vdd_ddr_pll_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <850000>; -- }; -- }; -- -- avdd_0v75_s0: nldo-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "avdd_0v75_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_0v85_s0: nldo-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-name = "vdd_0v85_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_0v75_s0: nldo-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "vdd_0v75_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -+&pinctrl { -+ usb { -+ vcc5v0_host_en: vcc5v0-host-en { -+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - }; - --&tsadc { -- status = "okay"; --}; -- --&uart2 { -- pinctrl-0 = <&uart2m0_xfer>; -- status = "okay"; --}; -- --&u2phy1 { -- status = "okay"; --}; -- --&u2phy1_otg { -- status = "okay"; --}; -- --&u2phy2 { -- status = "okay"; --}; -- --&u2phy2_host { -- /* connected to USB hub, which is powered by vcc5v0_sys */ -- phy-supply = <&vcc5v0_sys>; -- status = "okay"; --}; -- --&u2phy3 { -- status = "okay"; --}; -- --&u2phy3_host { -- phy-supply = <&vcc5v0_host>; -- status = "okay"; --}; -- --&usbdp_phy1 { -- status = "okay"; --}; -- --&usb_host0_ehci { -- status = "okay"; --}; -- --&usb_host0_ohci { -- status = "okay"; --}; -- --&usb_host1_ehci { -- status = "okay"; --}; -- --&usb_host1_ohci { -- status = "okay"; --}; -- --&usb_host1_xhci { -- dr_mode = "host"; -- status = "okay"; --}; -- --&usb_host2_xhci { -- status = "okay"; --}; -- --&vop { -- status = "okay"; --}; -- --&vop_mmu { -- status = "okay"; --}; -- --&vp0 { -- vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -- reg = ; -- remote-endpoint = <&hdmi0_in_vp0>; -- }; --}; -- --&vp1 { -- vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -- reg = ; -- remote-endpoint = <&hdmi1_in_vp1>; -- }; -+&vcc5v0_host { -+ enable-active-high; -+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; - }; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi -@@ -0,0 +1,945 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include "rk3588.dtsi" -+ -+/ { -+ aliases { -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; -+ mmc2 = &sdio; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ analog-sound { -+ compatible = "audio-graph-card"; -+ label = "rk3588-es8316"; -+ -+ widgets = "Microphone", "Mic Jack", -+ "Headphone", "Headphones"; -+ -+ routing = "MIC2", "Mic Jack", -+ "Headphones", "HPOL", -+ "Headphones", "HPOR"; -+ -+ dais = <&i2s0_8ch_p0>; -+ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_detect>; -+ }; -+ -+ hdmi0-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi0_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ -+ hdmi1-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi1_con_in: endpoint { -+ remote-endpoint = <&hdmi1_out_con>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_rgb_b>; -+ -+ led_rgb_b { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ cooling-levels = <0 120 150 180 210 240 255>; -+ fan-supply = <&vcc5v0_sys>; -+ pwms = <&pwm1 0 50000 0>; -+ #cooling-cells = <2>; -+ }; -+ -+ rfkill { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-m2-wlan"; -+ radio-type = "wlan"; -+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ rfkill-bt { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-m2-bt"; -+ radio-type = "bluetooth"; -+ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_vcc3v3_en>; -+ regulator-name = "vcc3v3_pcie2x1l0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie2x1l2"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcc3v3_pcie30: regulator-vcc3v3-pcie30 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3_vcc3v3_en>; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_host: regulator-vcc5v0-host { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: regulator-vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_1v1_nldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy1_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ -+&hdmi0 { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi0_con_in>; -+ }; -+}; -+ -+&hdmi0_sound { -+ status = "okay"; -+}; -+ -+&hdmi1 { -+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd -+ &hdmim1_tx1_scl &hdmim1_tx1_sda>; -+ status = "okay"; -+}; -+ -+&hdmi1_in { -+ hdmi1_in_vp1: endpoint { -+ remote-endpoint = <&vp1_out_hdmi1>; -+ }; -+}; -+ -+&hdmi1_out { -+ hdmi1_out_con: endpoint { -+ remote-endpoint = <&hdmi1_con_in>; -+ }; -+}; -+ -+&hdmi1_sound { -+ status = "okay"; -+}; -+ -+&hdmi_receiver_cma { -+ status = "okay"; -+}; -+ -+&hdmi_receiver { -+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&hdptxphy0 { -+ status = "okay"; -+}; -+ -+&hdptxphy1 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c6 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ wakeup-source; -+ }; -+}; -+ -+&i2c7 { -+ status = "okay"; -+ -+ es8316: audio-codec@11 { -+ compatible = "everest,es8316"; -+ reg = <0x11>; -+ clocks = <&cru I2S0_8CH_MCLKOUT>; -+ clock-names = "mclk"; -+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -+ assigned-clock-rates = <12288000>; -+ #sound-dai-cells = <0>; -+ -+ port { -+ es8316_p0_0: endpoint { -+ remote-endpoint = <&i2s0_8ch_p0_0>; -+ }; -+ }; -+ }; -+}; -+ -+&i2s0_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_lrck -+ &i2s0_mclk -+ &i2s0_sclk -+ &i2s0_sdi0 -+ &i2s0_sdo0>; -+ status = "okay"; -+ -+ i2s0_8ch_p0: port { -+ i2s0_8ch_p0_0: endpoint { -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ remote-endpoint = <&es8316_p0_0>; -+ }; -+ }; -+}; -+ -+&i2s5_8ch { -+ status = "okay"; -+}; -+ -+&i2s6_8ch { -+ status = "okay"; -+}; -+ -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ package_fan1: package-fan1 { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&package_fan0>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map1 { -+ trip = <&package_fan1>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ -+&pcie2x1l0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_rst>; -+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; -+ status = "okay"; -+}; -+ -+&pcie2x1l2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_2_rst>; -+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3_rst>; -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+}; -+ -+&pd_gpu { -+ domain-supply = <&vdd_gpu_s0>; -+}; -+ -+&pinctrl { -+ hdmirx { -+ hdmirx_hpd: hdmirx-5v-detection { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ led_rgb_b: led-rgb-b { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sound { -+ hp_detect: hp-detect { -+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie2 { -+ pcie2_0_rst: pcie2-0-rst { -+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { -+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie2_2_rst: pcie2-2-rst { -+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie3 { -+ pcie3_rst: pcie3-rst { -+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie3_vcc3v3_en: pcie3-vcc3v3-en { -+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&avcc_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ no-sdio; -+ no-sd; -+ non-removable; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ max-frequency = <200000000>; -+ no-sdio; -+ no-mmc; -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_s3>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim2_pins>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <104000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ vcc-supply = <&vcc_3v3_s3>; -+ }; -+}; -+ -+&spi2 { -+ status = "okay"; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ num-cs = <1>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ spi-max-frequency = <1000000>; -+ reg = <0x0>; -+ -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ -+ system-power-controller; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_gpu_s0"; -+ regulator-enable-ramp-delay = <400>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_lit_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_log_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vdd2_ddr_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_2v0_pldo_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vddq_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "avcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avdd_1v2_s0: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "avdd_1v2_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_s0: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vccio_sd_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "pldo6_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_ddr_pll_s0: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_ddr_pll_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "avdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v85_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_0v85_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+}; -+ -+&u2phy2_host { -+ /* connected to USB hub, which is powered by vcc5v0_sys */ -+ phy-supply = <&vcc5v0_sys>; -+ status = "okay"; -+}; -+ -+&u2phy3 { -+ status = "okay"; -+}; -+ -+&u2phy3_host { -+ phy-supply = <&vcc5v0_host>; -+ status = "okay"; -+}; -+ -+&usbdp_phy1 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host2_xhci { -+ status = "okay"; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; -+ -+&vp1 { -+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -+ reg = ; -+ remote-endpoint = <&hdmi1_in_vp1>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.12/002-12-v6.16-arm64-dts-rockchip-add-Rock-5B.patch b/target/linux/rockchip/patches-6.12/002-12-v6.16-arm64-dts-rockchip-add-Rock-5B.patch deleted file mode 100644 index f83c945638..0000000000 --- a/target/linux/rockchip/patches-6.12/002-12-v6.16-arm64-dts-rockchip-add-Rock-5B.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 376cb9696298df2028afb620a9dc6c4b10a18605 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 8 May 2025 19:48:53 +0200 -Subject: arm64: dts: rockchip: add Rock 5B+ - -Add ROCK 5B+, which is an improved version of the ROCK 5B with the -following changes: - - * Memory LPDDR4X -> LPDDR5 - * HDMI input connector size - * eMMC socket -> onboard - * M.2 E-Key is replaced by onboard RTL8852BE WLAN/BT - * M.2 M-Key 1x4 lanes is replaced by 2x2 lanes - * Added M.2 B-Key for USB connected WWAN modules (untested) - * Add second camera port (not yet supported in upstream Linux) - * Add dedicated USB-C port for device power (no impact in DT; - the existing port has not been changed and the new port is - handled by CH224D standalone chip) - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-4-677033cc1ac2@kernel.org -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts -@@ -0,0 +1,113 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include "rk3588-rock-5b.dtsi" -+ -+/ { -+ model = "Radxa ROCK 5B+"; -+ compatible = "radxa,rock-5b-plus", "rockchip,rk3588"; -+ -+ rfkill-wwan { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-m2-wwan"; -+ radio-type = "wwan"; -+ shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vcc3v3_4g: regulator-vcc3v3-4g { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -+ /* pinctrl for the GPIO is requested by vcc3v3_pcie2x1l0 */ -+ regulator-name = "vcc3v3_4g"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_wwan_pwr: regulator-vcc3v3-wwan { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wwan_power_en>; -+ regulator-name = "vcc3v3_wwan_pwr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_4g>; -+ }; -+}; -+ -+&gpio0 { -+ wwan-disable2-n-hog { -+ gpios = ; -+ output-low; -+ line-name = "M.2 B-key W_DISABLE2#"; -+ gpio-hog; -+ }; -+}; -+ -+&gpio2 { -+ wwan-reset-n-hog { -+ gpios = ; -+ output-low; -+ line-name = "M.2 B-key RESET#"; -+ gpio-hog; -+ }; -+ -+ wwan-wake-n-hog { -+ gpios = ; -+ input; -+ line-name = "M.2 B-key WoWWAN#"; -+ gpio-hog; -+ }; -+}; -+ -+&pcie30phy { -+ data-lanes = <1 1 2 2>; -+}; -+ -+&pcie3x2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3x2_rst>; -+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ num-lanes = <2>; -+}; -+ -+&pinctrl { -+ wwan { -+ wwan_power_en: wwan-pwr-en { -+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie3 { -+ pcie3x2_rst: pcie3x2-rst { -+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_host_en: vcc5v0-host-en { -+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&vcc5v0_host { -+ enable-active-high; -+ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; -+}; diff --git a/target/linux/rockchip/patches-6.12/002-13-v6.17-arm64-dts-rockchip-rename-rk3588-rock-5b.dtsi.patch b/target/linux/rockchip/patches-6.12/002-13-v6.17-arm64-dts-rockchip-rename-rk3588-rock-5b.dtsi.patch deleted file mode 100644 index 65eebe02f2..0000000000 --- a/target/linux/rockchip/patches-6.12/002-13-v6.17-arm64-dts-rockchip-rename-rk3588-rock-5b.dtsi.patch +++ /dev/null @@ -1,1934 +0,0 @@ -From 8b76abf78321ea3361c01e849c8dc3a6793c05d6 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 20 May 2025 20:50:09 +0200 -Subject: arm64: dts: rockchip: rename rk3588-rock-5b.dtsi - -As subsequent patches will add ROCK 5T support, rename the .dtsi file to -reflect that it's shared between ROCK 5B, ROCK 5B+ and ROCK 5T. - -This is done separately from moving the 5B and 5B+ only nodes to a -common tree so that the history stays bisectable and the diff easily -reviewable. - -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-2-1f1971850a20@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts -@@ -2,7 +2,7 @@ - - /dts-v1/; - --#include "rk3588-rock-5b.dtsi" -+#include "rk3588-rock-5b-5bp-5t.dtsi" - - / { - model = "Radxa ROCK 5B+"; ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -2,7 +2,7 @@ - - /dts-v1/; - --#include "rk3588-rock-5b.dtsi" -+#include "rk3588-rock-5b-5bp-5t.dtsi" - - / { - model = "Radxa ROCK 5B"; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi -@@ -0,0 +1,945 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include "rk3588.dtsi" -+ -+/ { -+ aliases { -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; -+ mmc2 = &sdio; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ analog-sound { -+ compatible = "audio-graph-card"; -+ label = "rk3588-es8316"; -+ -+ widgets = "Microphone", "Mic Jack", -+ "Headphone", "Headphones"; -+ -+ routing = "MIC2", "Mic Jack", -+ "Headphones", "HPOL", -+ "Headphones", "HPOR"; -+ -+ dais = <&i2s0_8ch_p0>; -+ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_detect>; -+ }; -+ -+ hdmi0-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi0_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ -+ hdmi1-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi1_con_in: endpoint { -+ remote-endpoint = <&hdmi1_out_con>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_rgb_b>; -+ -+ led_rgb_b { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ cooling-levels = <0 120 150 180 210 240 255>; -+ fan-supply = <&vcc5v0_sys>; -+ pwms = <&pwm1 0 50000 0>; -+ #cooling-cells = <2>; -+ }; -+ -+ rfkill { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-m2-wlan"; -+ radio-type = "wlan"; -+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ rfkill-bt { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-m2-bt"; -+ radio-type = "bluetooth"; -+ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_vcc3v3_en>; -+ regulator-name = "vcc3v3_pcie2x1l0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie2x1l2"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcc3v3_pcie30: regulator-vcc3v3-pcie30 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3_vcc3v3_en>; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_host: regulator-vcc5v0-host { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: regulator-vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_1v1_nldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy1_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ -+&hdmi0 { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi0_con_in>; -+ }; -+}; -+ -+&hdmi0_sound { -+ status = "okay"; -+}; -+ -+&hdmi1 { -+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd -+ &hdmim1_tx1_scl &hdmim1_tx1_sda>; -+ status = "okay"; -+}; -+ -+&hdmi1_in { -+ hdmi1_in_vp1: endpoint { -+ remote-endpoint = <&vp1_out_hdmi1>; -+ }; -+}; -+ -+&hdmi1_out { -+ hdmi1_out_con: endpoint { -+ remote-endpoint = <&hdmi1_con_in>; -+ }; -+}; -+ -+&hdmi1_sound { -+ status = "okay"; -+}; -+ -+&hdmi_receiver_cma { -+ status = "okay"; -+}; -+ -+&hdmi_receiver { -+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&hdptxphy0 { -+ status = "okay"; -+}; -+ -+&hdptxphy1 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c6 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ wakeup-source; -+ }; -+}; -+ -+&i2c7 { -+ status = "okay"; -+ -+ es8316: audio-codec@11 { -+ compatible = "everest,es8316"; -+ reg = <0x11>; -+ clocks = <&cru I2S0_8CH_MCLKOUT>; -+ clock-names = "mclk"; -+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -+ assigned-clock-rates = <12288000>; -+ #sound-dai-cells = <0>; -+ -+ port { -+ es8316_p0_0: endpoint { -+ remote-endpoint = <&i2s0_8ch_p0_0>; -+ }; -+ }; -+ }; -+}; -+ -+&i2s0_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_lrck -+ &i2s0_mclk -+ &i2s0_sclk -+ &i2s0_sdi0 -+ &i2s0_sdo0>; -+ status = "okay"; -+ -+ i2s0_8ch_p0: port { -+ i2s0_8ch_p0_0: endpoint { -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ remote-endpoint = <&es8316_p0_0>; -+ }; -+ }; -+}; -+ -+&i2s5_8ch { -+ status = "okay"; -+}; -+ -+&i2s6_8ch { -+ status = "okay"; -+}; -+ -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ package_fan1: package-fan1 { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&package_fan0>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map1 { -+ trip = <&package_fan1>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ -+&pcie2x1l0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_rst>; -+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; -+ status = "okay"; -+}; -+ -+&pcie2x1l2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_2_rst>; -+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3_rst>; -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+}; -+ -+&pd_gpu { -+ domain-supply = <&vdd_gpu_s0>; -+}; -+ -+&pinctrl { -+ hdmirx { -+ hdmirx_hpd: hdmirx-5v-detection { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ led_rgb_b: led-rgb-b { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sound { -+ hp_detect: hp-detect { -+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie2 { -+ pcie2_0_rst: pcie2-0-rst { -+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { -+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie2_2_rst: pcie2-2-rst { -+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie3 { -+ pcie3_rst: pcie3-rst { -+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie3_vcc3v3_en: pcie3-vcc3v3-en { -+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&avcc_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ no-sdio; -+ no-sd; -+ non-removable; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ max-frequency = <200000000>; -+ no-sdio; -+ no-mmc; -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_s3>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim2_pins>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <104000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ vcc-supply = <&vcc_3v3_s3>; -+ }; -+}; -+ -+&spi2 { -+ status = "okay"; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ num-cs = <1>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ spi-max-frequency = <1000000>; -+ reg = <0x0>; -+ -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ -+ system-power-controller; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_gpu_s0"; -+ regulator-enable-ramp-delay = <400>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_lit_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_log_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vdd2_ddr_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_2v0_pldo_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vddq_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "avcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avdd_1v2_s0: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "avdd_1v2_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_s0: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vccio_sd_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "pldo6_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_ddr_pll_s0: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_ddr_pll_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "avdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v85_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_0v85_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+}; -+ -+&u2phy2_host { -+ /* connected to USB hub, which is powered by vcc5v0_sys */ -+ phy-supply = <&vcc5v0_sys>; -+ status = "okay"; -+}; -+ -+&u2phy3 { -+ status = "okay"; -+}; -+ -+&u2phy3_host { -+ phy-supply = <&vcc5v0_host>; -+ status = "okay"; -+}; -+ -+&usbdp_phy1 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host2_xhci { -+ status = "okay"; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; -+ -+&vp1 { -+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -+ reg = ; -+ remote-endpoint = <&hdmi1_in_vp1>; -+ }; -+}; ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi -+++ /dev/null -@@ -1,945 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -- --/dts-v1/; -- --#include --#include --#include --#include "rk3588.dtsi" -- --/ { -- aliases { -- mmc0 = &sdhci; -- mmc1 = &sdmmc; -- mmc2 = &sdio; -- }; -- -- chosen { -- stdout-path = "serial2:1500000n8"; -- }; -- -- analog-sound { -- compatible = "audio-graph-card"; -- label = "rk3588-es8316"; -- -- widgets = "Microphone", "Mic Jack", -- "Headphone", "Headphones"; -- -- routing = "MIC2", "Mic Jack", -- "Headphones", "HPOL", -- "Headphones", "HPOR"; -- -- dais = <&i2s0_8ch_p0>; -- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&hp_detect>; -- }; -- -- hdmi0-con { -- compatible = "hdmi-connector"; -- type = "a"; -- -- port { -- hdmi0_con_in: endpoint { -- remote-endpoint = <&hdmi0_out_con>; -- }; -- }; -- }; -- -- hdmi1-con { -- compatible = "hdmi-connector"; -- type = "a"; -- -- port { -- hdmi1_con_in: endpoint { -- remote-endpoint = <&hdmi1_out_con>; -- }; -- }; -- }; -- -- leds { -- compatible = "gpio-leds"; -- pinctrl-names = "default"; -- pinctrl-0 = <&led_rgb_b>; -- -- led_rgb_b { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; -- }; -- }; -- -- fan: pwm-fan { -- compatible = "pwm-fan"; -- cooling-levels = <0 120 150 180 210 240 255>; -- fan-supply = <&vcc5v0_sys>; -- pwms = <&pwm1 0 50000 0>; -- #cooling-cells = <2>; -- }; -- -- rfkill { -- compatible = "rfkill-gpio"; -- label = "rfkill-m2-wlan"; -- radio-type = "wlan"; -- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -- }; -- -- rfkill-bt { -- compatible = "rfkill-gpio"; -- label = "rfkill-m2-bt"; -- radio-type = "bluetooth"; -- shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -- }; -- -- vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_0_vcc3v3_en>; -- regulator-name = "vcc3v3_pcie2x1l0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- startup-delay-us = <50000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { -- compatible = "regulator-fixed"; -- regulator-name = "vcc3v3_pcie2x1l2"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- startup-delay-us = <5000>; -- vin-supply = <&vcc_3v3_s3>; -- }; -- -- vcc3v3_pcie30: regulator-vcc3v3-pcie30 { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_vcc3v3_en>; -- regulator-name = "vcc3v3_pcie30"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- startup-delay-us = <5000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc5v0_host: regulator-vcc5v0-host { -- compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_host"; -- regulator-boot-on; -- regulator-always-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc5v0_sys: regulator-vcc5v0-sys { -- compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_sys"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- }; -- -- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { -- compatible = "regulator-fixed"; -- regulator-name = "vcc_1v1_nldo_s3"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1100000>; -- regulator-max-microvolt = <1100000>; -- vin-supply = <&vcc5v0_sys>; -- }; --}; -- --&combphy0_ps { -- status = "okay"; --}; -- --&combphy1_ps { -- status = "okay"; --}; -- --&combphy2_psu { -- status = "okay"; --}; -- --&cpu_b0 { -- cpu-supply = <&vdd_cpu_big0_s0>; --}; -- --&cpu_b1 { -- cpu-supply = <&vdd_cpu_big0_s0>; --}; -- --&cpu_b2 { -- cpu-supply = <&vdd_cpu_big1_s0>; --}; -- --&cpu_b3 { -- cpu-supply = <&vdd_cpu_big1_s0>; --}; -- --&cpu_l0 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l1 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l2 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l3 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&gpu { -- mali-supply = <&vdd_gpu_s0>; -- status = "okay"; --}; -- --&hdmi0 { -- status = "okay"; --}; -- --&hdmi0_in { -- hdmi0_in_vp0: endpoint { -- remote-endpoint = <&vp0_out_hdmi0>; -- }; --}; -- --&hdmi0_out { -- hdmi0_out_con: endpoint { -- remote-endpoint = <&hdmi0_con_in>; -- }; --}; -- --&hdmi0_sound { -- status = "okay"; --}; -- --&hdmi1 { -- pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd -- &hdmim1_tx1_scl &hdmim1_tx1_sda>; -- status = "okay"; --}; -- --&hdmi1_in { -- hdmi1_in_vp1: endpoint { -- remote-endpoint = <&vp1_out_hdmi1>; -- }; --}; -- --&hdmi1_out { -- hdmi1_out_con: endpoint { -- remote-endpoint = <&hdmi1_con_in>; -- }; --}; -- --&hdmi1_sound { -- status = "okay"; --}; -- --&hdmi_receiver_cma { -- status = "okay"; --}; -- --&hdmi_receiver { -- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -- pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; -- pinctrl-names = "default"; -- status = "okay"; --}; -- --&hdptxphy0 { -- status = "okay"; --}; -- --&hdptxphy1 { -- status = "okay"; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0m2_xfer>; -- status = "okay"; -- -- vdd_cpu_big0_s0: regulator@42 { -- compatible = "rockchip,rk8602"; -- reg = <0x42>; -- fcs,suspend-voltage-selector = <1>; -- regulator-name = "vdd_cpu_big0_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <1050000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc5v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_cpu_big1_s0: regulator@43 { -- compatible = "rockchip,rk8603", "rockchip,rk8602"; -- reg = <0x43>; -- fcs,suspend-voltage-selector = <1>; -- regulator-name = "vdd_cpu_big1_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <1050000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc5v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; --}; -- --&i2c6 { -- status = "okay"; -- -- hym8563: rtc@51 { -- compatible = "haoyu,hym8563"; -- reg = <0x51>; -- #clock-cells = <0>; -- clock-output-names = "hym8563"; -- pinctrl-names = "default"; -- pinctrl-0 = <&hym8563_int>; -- interrupt-parent = <&gpio0>; -- interrupts = ; -- wakeup-source; -- }; --}; -- --&i2c7 { -- status = "okay"; -- -- es8316: audio-codec@11 { -- compatible = "everest,es8316"; -- reg = <0x11>; -- clocks = <&cru I2S0_8CH_MCLKOUT>; -- clock-names = "mclk"; -- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -- assigned-clock-rates = <12288000>; -- #sound-dai-cells = <0>; -- -- port { -- es8316_p0_0: endpoint { -- remote-endpoint = <&i2s0_8ch_p0_0>; -- }; -- }; -- }; --}; -- --&i2s0_8ch { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2s0_lrck -- &i2s0_mclk -- &i2s0_sclk -- &i2s0_sdi0 -- &i2s0_sdo0>; -- status = "okay"; -- -- i2s0_8ch_p0: port { -- i2s0_8ch_p0_0: endpoint { -- dai-format = "i2s"; -- mclk-fs = <256>; -- remote-endpoint = <&es8316_p0_0>; -- }; -- }; --}; -- --&i2s5_8ch { -- status = "okay"; --}; -- --&i2s6_8ch { -- status = "okay"; --}; -- --&package_thermal { -- polling-delay = <1000>; -- -- trips { -- package_fan0: package-fan0 { -- temperature = <55000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- -- package_fan1: package-fan1 { -- temperature = <65000>; -- hysteresis = <2000>; -- type = "active"; -- }; -- }; -- -- cooling-maps { -- map0 { -- trip = <&package_fan0>; -- cooling-device = <&fan THERMAL_NO_LIMIT 1>; -- }; -- -- map1 { -- trip = <&package_fan1>; -- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -- }; -- }; --}; -- --&pcie2x1l0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_0_rst>; -- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; -- status = "okay"; --}; -- --&pcie2x1l2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_2_rst>; -- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; -- status = "okay"; --}; -- --&pcie30phy { -- status = "okay"; --}; -- --&pcie3x4 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_rst>; -- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie30>; -- status = "okay"; --}; -- --&pd_gpu { -- domain-supply = <&vdd_gpu_s0>; --}; -- --&pinctrl { -- hdmirx { -- hdmirx_hpd: hdmirx-5v-detection { -- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- hym8563 { -- hym8563_int: hym8563-int { -- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- leds { -- led_rgb_b: led-rgb-b { -- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- sound { -- hp_detect: hp-detect { -- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- pcie2 { -- pcie2_0_rst: pcie2-0-rst { -- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie2_0_vcc3v3_en: pcie2-0-vcc-en { -- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie2_2_rst: pcie2-2-rst { -- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- pcie3 { -- pcie3_rst: pcie3-rst { -- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie3_vcc3v3_en: pcie3-vcc3v3-en { -- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; --}; -- --&pwm1 { -- status = "okay"; --}; -- --&saradc { -- vref-supply = <&avcc_1v8_s0>; -- status = "okay"; --}; -- --&sdhci { -- bus-width = <8>; -- no-sdio; -- no-sd; -- non-removable; -- mmc-hs400-1_8v; -- mmc-hs400-enhanced-strobe; -- status = "okay"; --}; -- --&sdmmc { -- max-frequency = <200000000>; -- no-sdio; -- no-mmc; -- bus-width = <4>; -- cap-mmc-highspeed; -- cap-sd-highspeed; -- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -- disable-wp; -- sd-uhs-sdr104; -- vmmc-supply = <&vcc_3v3_s3>; -- vqmmc-supply = <&vccio_sd_s0>; -- status = "okay"; --}; -- --&sfc { -- pinctrl-names = "default"; -- pinctrl-0 = <&fspim2_pins>; -- status = "okay"; -- -- flash@0 { -- compatible = "jedec,spi-nor"; -- reg = <0>; -- spi-max-frequency = <104000000>; -- spi-rx-bus-width = <4>; -- spi-tx-bus-width = <1>; -- vcc-supply = <&vcc_3v3_s3>; -- }; --}; -- --&spi2 { -- status = "okay"; -- assigned-clocks = <&cru CLK_SPI2>; -- assigned-clock-rates = <200000000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -- num-cs = <1>; -- -- pmic@0 { -- compatible = "rockchip,rk806"; -- spi-max-frequency = <1000000>; -- reg = <0x0>; -- -- interrupt-parent = <&gpio0>; -- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -- -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -- <&rk806_dvs2_null>, <&rk806_dvs3_null>; -- -- system-power-controller; -- -- vcc1-supply = <&vcc5v0_sys>; -- vcc2-supply = <&vcc5v0_sys>; -- vcc3-supply = <&vcc5v0_sys>; -- vcc4-supply = <&vcc5v0_sys>; -- vcc5-supply = <&vcc5v0_sys>; -- vcc6-supply = <&vcc5v0_sys>; -- vcc7-supply = <&vcc5v0_sys>; -- vcc8-supply = <&vcc5v0_sys>; -- vcc9-supply = <&vcc5v0_sys>; -- vcc10-supply = <&vcc5v0_sys>; -- vcc11-supply = <&vcc_2v0_pldo_s3>; -- vcc12-supply = <&vcc5v0_sys>; -- vcc13-supply = <&vcc_1v1_nldo_s3>; -- vcc14-supply = <&vcc_1v1_nldo_s3>; -- vcca-supply = <&vcc5v0_sys>; -- -- gpio-controller; -- #gpio-cells = <2>; -- -- rk806_dvs1_null: dvs1-null-pins { -- pins = "gpio_pwrctrl1"; -- function = "pin_fun0"; -- }; -- -- rk806_dvs2_null: dvs2-null-pins { -- pins = "gpio_pwrctrl2"; -- function = "pin_fun0"; -- }; -- -- rk806_dvs3_null: dvs3-null-pins { -- pins = "gpio_pwrctrl3"; -- function = "pin_fun0"; -- }; -- -- regulators { -- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_gpu_s0"; -- regulator-enable-ramp-delay = <400>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_cpu_lit_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_log_s0: dcdc-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <675000>; -- regulator-max-microvolt = <750000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_log_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <750000>; -- }; -- }; -- -- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_vdenc_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_ddr_s0: dcdc-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <675000>; -- regulator-max-microvolt = <900000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_ddr_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <850000>; -- }; -- }; -- -- vdd2_ddr_s3: dcdc-reg6 { -- regulator-always-on; -- regulator-boot-on; -- regulator-name = "vdd2_ddr_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- }; -- }; -- -- vcc_2v0_pldo_s3: dcdc-reg7 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <2000000>; -- regulator-max-microvolt = <2000000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_2v0_pldo_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <2000000>; -- }; -- }; -- -- vcc_3v3_s3: dcdc-reg8 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-name = "vcc_3v3_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <3300000>; -- }; -- }; -- -- vddq_ddr_s0: dcdc-reg9 { -- regulator-always-on; -- regulator-boot-on; -- regulator-name = "vddq_ddr_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_1v8_s3: dcdc-reg10 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "vcc_1v8_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- avcc_1v8_s0: pldo-reg1 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "avcc_1v8_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_1v8_s0: pldo-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "vcc_1v8_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- avdd_1v2_s0: pldo-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1200000>; -- regulator-max-microvolt = <1200000>; -- regulator-name = "avdd_1v2_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_3v3_s0: pldo-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vcc_3v3_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vccio_sd_s0: pldo-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <3300000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vccio_sd_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- pldo6_s3: pldo-reg6 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "pldo6_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- vdd_0v75_s3: nldo-reg1 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "vdd_0v75_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <750000>; -- }; -- }; -- -- vdd_ddr_pll_s0: nldo-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-name = "vdd_ddr_pll_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <850000>; -- }; -- }; -- -- avdd_0v75_s0: nldo-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "avdd_0v75_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_0v85_s0: nldo-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-name = "vdd_0v85_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_0v75_s0: nldo-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "vdd_0v75_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- }; -- }; --}; -- --&tsadc { -- status = "okay"; --}; -- --&uart2 { -- pinctrl-0 = <&uart2m0_xfer>; -- status = "okay"; --}; -- --&u2phy1 { -- status = "okay"; --}; -- --&u2phy1_otg { -- status = "okay"; --}; -- --&u2phy2 { -- status = "okay"; --}; -- --&u2phy2_host { -- /* connected to USB hub, which is powered by vcc5v0_sys */ -- phy-supply = <&vcc5v0_sys>; -- status = "okay"; --}; -- --&u2phy3 { -- status = "okay"; --}; -- --&u2phy3_host { -- phy-supply = <&vcc5v0_host>; -- status = "okay"; --}; -- --&usbdp_phy1 { -- status = "okay"; --}; -- --&usb_host0_ehci { -- status = "okay"; --}; -- --&usb_host0_ohci { -- status = "okay"; --}; -- --&usb_host1_ehci { -- status = "okay"; --}; -- --&usb_host1_ohci { -- status = "okay"; --}; -- --&usb_host1_xhci { -- dr_mode = "host"; -- status = "okay"; --}; -- --&usb_host2_xhci { -- status = "okay"; --}; -- --&vop { -- status = "okay"; --}; -- --&vop_mmu { -- status = "okay"; --}; -- --&vp0 { -- vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -- reg = ; -- remote-endpoint = <&hdmi0_in_vp0>; -- }; --}; -- --&vp1 { -- vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -- reg = ; -- remote-endpoint = <&hdmi1_in_vp1>; -- }; --}; diff --git a/target/linux/rockchip/patches-6.12/002-14-v6.17-arm64-dts-rockchip-move-common-ROCK-5B-nodes-into-ow.patch b/target/linux/rockchip/patches-6.12/002-14-v6.17-arm64-dts-rockchip-move-common-ROCK-5B-nodes-into-ow.patch deleted file mode 100644 index 6b9035d34f..0000000000 --- a/target/linux/rockchip/patches-6.12/002-14-v6.17-arm64-dts-rockchip-move-common-ROCK-5B-nodes-into-ow.patch +++ /dev/null @@ -1,265 +0,0 @@ -From 988035f152709549a095b12fcdcb3cf26cbad63f Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 20 May 2025 20:50:10 +0200 -Subject: arm64: dts: rockchip: move common ROCK 5B/+ nodes into own tree - -A few device tree nodes are shared between ROCK 5B and ROCK 5B+ that are -not shared with ROCK 5T. - -Move them into their own device tree include. - -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-3-1f1971850a20@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi -@@ -18,23 +18,6 @@ - stdout-path = "serial2:1500000n8"; - }; - -- analog-sound { -- compatible = "audio-graph-card"; -- label = "rk3588-es8316"; -- -- widgets = "Microphone", "Mic Jack", -- "Headphone", "Headphones"; -- -- routing = "MIC2", "Mic Jack", -- "Headphones", "HPOL", -- "Headphones", "HPOR"; -- -- dais = <&i2s0_8ch_p0>; -- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&hp_detect>; -- }; -- - hdmi0-con { - compatible = "hdmi-connector"; - type = "a"; -@@ -57,19 +40,6 @@ - }; - }; - -- leds { -- compatible = "gpio-leds"; -- pinctrl-names = "default"; -- pinctrl-0 = <&led_rgb_b>; -- -- led_rgb_b { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; -- }; -- }; -- - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 120 150 180 210 240 255>; -@@ -78,13 +48,6 @@ - #cooling-cells = <2>; - }; - -- rfkill { -- compatible = "rfkill-gpio"; -- label = "rfkill-m2-wlan"; -- radio-type = "wlan"; -- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -- }; -- - rfkill-bt { - compatible = "rfkill-gpio"; - label = "rfkill-m2-bt"; -@@ -95,9 +58,6 @@ - vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { - compatible = "regulator-fixed"; - enable-active-high; -- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_0_vcc3v3_en>; - regulator-name = "vcc3v3_pcie2x1l0"; - regulator-always-on; - regulator-boot-on; -@@ -105,6 +65,7 @@ - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - vin-supply = <&vcc5v0_sys>; -+ status = "disabled"; - }; - - vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { -@@ -255,10 +216,8 @@ - }; - - &hdmi_receiver { -- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; - pinctrl-names = "default"; -- status = "okay"; - }; - - &hdptxphy0 { -@@ -434,39 +393,17 @@ - }; - - &pinctrl { -- hdmirx { -- hdmirx_hpd: hdmirx-5v-detection { -- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - -- leds { -- led_rgb_b: led-rgb-b { -- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- sound { -- hp_detect: hp-detect { -- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - -- pcie2_0_vcc3v3_en: pcie2-0-vcc-en { -- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; -@@ -918,10 +855,6 @@ - status = "okay"; - }; - --&usb_host2_xhci { -- status = "okay"; --}; -- - &vop { - status = "okay"; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts -@@ -2,7 +2,7 @@ - - /dts-v1/; - --#include "rk3588-rock-5b-5bp-5t.dtsi" -+#include "rk3588-rock-5b.dtsi" - - / { - model = "Radxa ROCK 5B+"; ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -2,7 +2,7 @@ - - /dts-v1/; - --#include "rk3588-rock-5b-5bp-5t.dtsi" -+#include "rk3588-rock-5b.dtsi" - - / { - model = "Radxa ROCK 5B"; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include "rk3588-rock-5b-5bp-5t.dtsi" -+ -+/ { -+ analog-sound { -+ compatible = "audio-graph-card"; -+ label = "rk3588-es8316"; -+ -+ widgets = "Microphone", "Mic Jack", -+ "Headphone", "Headphones"; -+ -+ routing = "MIC2", "Mic Jack", -+ "Headphones", "HPOL", -+ "Headphones", "HPOR"; -+ -+ dais = <&i2s0_8ch_p0>; -+ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_detect>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_rgb_b>; -+ -+ led_rgb_b { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ rfkill { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-m2-wlan"; -+ radio-type = "wlan"; -+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&hdmi_receiver { -+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ hdmirx { -+ hdmirx_hpd: hdmirx-5v-detection { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ led_rgb_b: led-rgb-b { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie2 { -+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { -+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sound { -+ hp_detect: hp-detect { -+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&usb_host2_xhci { -+ status = "okay"; -+}; -+ -+&vcc3v3_pcie2x1l0 { -+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_vcc3v3_en>; -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.12/002-15-v6.17-arm64-dts-rockchip-add-ROCK-5T-device-tree.patch b/target/linux/rockchip/patches-6.12/002-15-v6.17-arm64-dts-rockchip-add-ROCK-5T-device-tree.patch deleted file mode 100644 index 6a7a9e2cff..0000000000 --- a/target/linux/rockchip/patches-6.12/002-15-v6.17-arm64-dts-rockchip-add-ROCK-5T-device-tree.patch +++ /dev/null @@ -1,134 +0,0 @@ -From 0ea651de9b79a17cbe410a69399877805c136b76 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 20 May 2025 20:50:11 +0200 -Subject: arm64: dts: rockchip: add ROCK 5T device tree - -The RADXA ROCK 5T is a single board computer quite similar to the ROCK -5B+, except it has one more PCIe-to-Ethernet controller (at the expense -of a USB3 port) and a barrel jack for power input instead. Some pins are -shuffled around as well. - -Add a device tree for it. - -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-4-1f1971850a20@collabora.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -143,6 +143,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5t.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts -@@ -0,0 +1,105 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include "rk3588-rock-5b-5bp-5t.dtsi" -+ -+/ { -+ model = "Radxa ROCK 5T"; -+ compatible = "radxa,rock-5t", "rockchip,rk3588"; -+ -+ analog-sound { -+ compatible = "audio-graph-card"; -+ label = "rk3588-es8316"; -+ -+ widgets = "Microphone", "Mic Jack", -+ "Headphone", "Headphones"; -+ -+ routing = "MIC2", "Mic Jack", -+ "Headphones", "HPOL", -+ "Headphones", "HPOR"; -+ -+ dais = <&i2s0_8ch_p0>; -+ hp-det-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_detect>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_rgb_b>; -+ -+ led_rgb_b { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ rfkill { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-m2-wlan"; -+ radio-type = "wlan"; -+ shutdown-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vcc3v3_pcie2x1l1: regulator-vcc3v3-pcie2x1l2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie2x1l1"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <5000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+}; -+ -+&hdmi_receiver { -+ hpd-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&pcie2x1l1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_1_rst>; -+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie2x1l1>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ hdmirx { -+ hdmirx_hpd: hdmirx-5v-detection { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ led_rgb_b: led-rgb-b { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie2 { -+ pcie2_1_rst: pcie2-1-rst { -+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { -+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sound { -+ hp_detect: hp-detect { -+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&vcc3v3_pcie2x1l0 { -+ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_vcc3v3_en>; -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.12/002-16-v6.17-arm64-dts-rockchip-fix-USB-on-RADXA-ROCK-5T.patch b/target/linux/rockchip/patches-6.12/002-16-v6.17-arm64-dts-rockchip-fix-USB-on-RADXA-ROCK-5T.patch deleted file mode 100644 index cb40a82c55..0000000000 --- a/target/linux/rockchip/patches-6.12/002-16-v6.17-arm64-dts-rockchip-fix-USB-on-RADXA-ROCK-5T.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Mon, 25 Aug 2025 09:27:08 +0200 -Subject: arm64: dts: rockchip: fix USB on RADXA ROCK 5T - -The RADXA ROCK 5T board uses the same GPIO pin for controlling the USB -host port regulator. This control pin was mistakenly left out of the -ROCK 5T device tree. - -Reported-by: FUKAUMI Naoki -Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38609886; -Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree") -Signed-off-by: Nicolas Frattaroli - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts -@@ -95,6 +95,12 @@ - rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -+ -+ usb { -+ vcc5v0_host_en: vcc5v0-host-en { -+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; - }; - - &vcc3v3_pcie2x1l0 { -@@ -103,3 +109,10 @@ - pinctrl-0 = <&pcie2_0_vcc3v3_en>; - status = "okay"; - }; -+ -+&vcc5v0_host { -+ enable-active-high; -+ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; -+}; diff --git a/target/linux/rockchip/patches-6.12/002-17-v6.17-arm64-dts-rockchip-fix-second-M.2-slot-on-ROCK-5T.patch b/target/linux/rockchip/patches-6.12/002-17-v6.17-arm64-dts-rockchip-fix-second-M.2-slot-on-ROCK-5T.patch deleted file mode 100644 index 23e57509c5..0000000000 --- a/target/linux/rockchip/patches-6.12/002-17-v6.17-arm64-dts-rockchip-fix-second-M.2-slot-on-ROCK-5T.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 26 Aug 2025 10:08:36 +0200 -Subject: arm64: dts: rockchip: fix second M.2 slot on ROCK 5T - -The Radxa ROCK 5T has two M.2 slots, much like the Radxa Rock 5B+. As it -stands, the board won't be able to use PCIe3 if the second M.2 slot is -in use. - -Fix this by adding the necessary node enablement and data-lanes property -to the ROCK 5T device tree, mirroring what's in the ROCK 5B+ device -tree. - -Reported-by: FUKAUMI Naoki -Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38610630; -Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree") -Signed-off-by: Nicolas Frattaroli - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts -@@ -68,6 +68,22 @@ - status = "okay"; - }; - -+&pcie30phy { -+ data-lanes = <1 1 2 2>; -+}; -+ -+&pcie3x2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie3x2_rst>; -+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ num-lanes = <2>; -+}; -+ - &pinctrl { - hdmirx { - hdmirx_hpd: hdmirx-5v-detection { -@@ -90,6 +106,12 @@ - }; - }; - -+ pcie3 { -+ pcie3x2_rst: pcie3x2-rst { -+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - sound { - hp_detect: hp-detect { - rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.12/003-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch b/target/linux/rockchip/patches-6.12/003-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch index a9e5994234..c4bbc314cd 100644 --- a/target/linux/rockchip/patches-6.12/003-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch +++ b/target/linux/rockchip/patches-6.12/003-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch @@ -11,14 +11,14 @@ Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/717e7c9527139c3a3e5246dd367a3ad98c5c81b6.1727438777.git.geert+renesas@glider.be Signed-off-by: Heiko Stuebner ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -@@ -46,7 +46,7 @@ - compatible = "audio-graph-card"; - label = "rk3588-es8316"; +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -32,7 +32,7 @@ + "Headphones", "HPOR"; + dais = <&i2s0_8ch_p0>; - hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hp_detect>; - routing = "MIC2", "Mic Jack", + }; diff --git a/target/linux/rockchip/patches-6.12/003-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch b/target/linux/rockchip/patches-6.12/003-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch new file mode 100644 index 0000000000..ee6fdf67db --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch @@ -0,0 +1,86 @@ +From c8152f79c2dd8039e14073be76fdbce8760175da Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sat, 19 Oct 2024 13:12:11 +0300 +Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5b + +Add the necessary DT changes to enable HDMI0 on Radxa ROCK 5B. + +Tested-by: FUKAUMI Naoki +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-2-466cd80e8ff9@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -37,6 +38,17 @@ + pinctrl-0 = <&hp_detect>; + }; + ++ hdmi0-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi0_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -192,6 +204,26 @@ + status = "okay"; + }; + ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi0_con_in>; ++ }; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +@@ -858,3 +890,18 @@ + &usb_host2_xhci { + status = "okay"; + }; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.12/003-02-v6.13-arm64-dts-rockchip-fix-the-pcie-refclock-oscillator-.patch b/target/linux/rockchip/patches-6.12/003-02-v6.13-arm64-dts-rockchip-fix-the-pcie-refclock-oscillator-.patch deleted file mode 100644 index fcdd0eaef8..0000000000 --- a/target/linux/rockchip/patches-6.12/003-02-v6.13-arm64-dts-rockchip-fix-the-pcie-refclock-oscillator-.patch +++ /dev/null @@ -1,94 +0,0 @@ -From e684f02492f99d6f6f037a35a613607339cf8e8f Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Fri, 6 Sep 2024 10:25:11 +0200 -Subject: arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX - -The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its -SATA controller with 2 lanes each. The supply for the refclk oscillator is -the same that supplies the M.2 slot, but the SATA controller port is -supplied by a different rail. - -This leads to the effect that if the PCIe30x4 controller for the M.2 -probes first, everything works normally. But if the PCIe30x2 controller -that is connected to the SATA controller probes first, it will hang on -the first DBI read as nothing will have enabled the refclock before. - -Fix this by describing the clock generator with its supplies so that -both controllers can reference it as needed. - -Signed-off-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20240906082511.2963890-6-heiko@sntech.de - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -@@ -72,6 +72,15 @@ - }; - }; - -+ /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ -+ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { -+ compatible = "gated-fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "pcie30_refclk"; -+ vdd-supply = <&vcc3v3_pi6c_05>; -+ }; -+ - fan0: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; -@@ -146,13 +155,14 @@ - vin-supply = <&vcc_3v3_s3>; - }; - -- vcc3v3_mkey: regulator-vcc3v3-mkey { -+ /* The PCIE30x4_PWREN_H controls two regulators */ -+ vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x4_pwren_h>; -- regulator-name = "vcc3v3_mkey"; -+ regulator-name = "vcc3v3_pi6c_05"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; -@@ -513,6 +523,18 @@ - - /* ASMedia ASM1164 Sata controller */ - &pcie3x2 { -+ /* -+ * The board has a "pcie_refclk" oscillator that needs enabling, -+ * so add it to the list of clocks. -+ */ -+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, -+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, -+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>, -+ <&pcie30_port1_refclk>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe", -+ "ref"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x2_perstn_m1_l>; - reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -@@ -522,6 +544,18 @@ - - /* M.2 M.key */ - &pcie3x4 { -+ /* -+ * The board has a "pcie_refclk" oscillator that needs enabling, -+ * so add it to the list of clocks. -+ */ -+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, -+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, -+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, -+ <&pcie30_port0_refclk>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe", -+ "ref"; - num-lanes = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x4_perstn_m1_l>; diff --git a/target/linux/rockchip/patches-6.12/003-03-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch b/target/linux/rockchip/patches-6.12/003-03-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch new file mode 100644 index 0000000000..d276b305d0 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-03-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch @@ -0,0 +1,72 @@ +From 5c96e63301978f4657c9082c55a066763c8db7b1 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Sat, 5 Oct 2024 22:40:12 +0200 +Subject: arm64: dts: rockchip: adapt regulator nodenames to preferred form + +The preferred nodename for fixed-regulators has changed to +pattern: '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$' + +Fix all Rockchip DT regulator nodenames. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/0ae40493-93e9-40cd-9ca9-990ae064f21a@gmail.com +[adapted rebased on top of a number of other changes and included + neu6a-wifi + wolfvision-pf5-io-expander overlays] +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -84,7 +84,7 @@ + shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + +- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { ++ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; +@@ -99,7 +99,7 @@ + vin-supply = <&vcc5v0_sys>; + }; + +- vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { ++ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; +@@ -108,7 +108,7 @@ + vin-supply = <&vcc_3v3_s3>; + }; + +- vcc3v3_pcie30: vcc3v3-pcie30-regulator { ++ vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; +@@ -121,7 +121,7 @@ + vin-supply = <&vcc5v0_sys>; + }; + +- vcc5v0_host: vcc5v0-host-regulator { ++ vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; +@@ -135,7 +135,7 @@ + vin-supply = <&vcc5v0_sys>; + }; + +- vcc5v0_sys: vcc5v0-sys-regulator { ++ vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; +@@ -144,7 +144,7 @@ + regulator-max-microvolt = <5000000>; + }; + +- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; diff --git a/target/linux/rockchip/patches-6.12/003-03-v6.14-arm64-dts-rockchip-slow-down-emmc-freq-for-rock-5-it.patch b/target/linux/rockchip/patches-6.12/003-03-v6.14-arm64-dts-rockchip-slow-down-emmc-freq-for-rock-5-it.patch deleted file mode 100644 index 31577a490b..0000000000 --- a/target/linux/rockchip/patches-6.12/003-03-v6.14-arm64-dts-rockchip-slow-down-emmc-freq-for-rock-5-it.patch +++ /dev/null @@ -1,35 +0,0 @@ -From b36402e4a0772d1b3da06a4f5fbd1cfe4d6f1cc0 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Fri, 28 Feb 2025 22:33:08 +0800 -Subject: arm64: dts: rockchip: slow down emmc freq for rock 5 itx - -The current max-frequency 200000000 of emmc is not stable. When doing -heavy write there will be I/O Error. After setting max-frequency to -150000000 the emmc is stable under write. - -Also remove property mmc-hs200-1_8v because we are already running at -HS400 mode. - -Tested with fio command: -fio -filename=./test_randread -direct=1 -iodepth 1 -thread \ --rw=randwrite -ioengine=psync -bs=16k -size=1G -numjobs=10 \ --runtime=600 -group_reporting -name=mytest - -Signed-off-by: Jianfeng Liu -Link: https://lore.kernel.org/r/20250228143341.70244-1-liujianfeng1994@gmail.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -@@ -690,10 +690,9 @@ - - &sdhci { - bus-width = <8>; -- max-frequency = <200000000>; -+ max-frequency = <150000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; -- mmc-hs200-1_8v; - no-sdio; - no-sd; - non-removable; diff --git a/target/linux/rockchip/patches-6.12/003-04-v6.13-arm64-dts-rockchip-rename-rfkill-label-for-Radxa-ROC.patch b/target/linux/rockchip/patches-6.12/003-04-v6.13-arm64-dts-rockchip-rename-rfkill-label-for-Radxa-ROC.patch new file mode 100644 index 0000000000..2066e5c57e --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-04-v6.13-arm64-dts-rockchip-rename-rfkill-label-for-Radxa-ROC.patch @@ -0,0 +1,30 @@ +From 2ddd93481bce86c6a46223f45accdb3b149a43e4 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Thu, 28 Nov 2024 12:06:30 +0000 +Subject: arm64: dts: rockchip: rename rfkill label for Radxa ROCK 5B + +on ROCK 5B, there is no PCIe slot, instead there is a M.2 slot. +rfkill pin is not exclusive to PCIe devices, there is SDIO Wi-Fi +devices. + +rename rfkill label from "rfkill-pcie-wlan" to "rfkill-m2-wlan", it +matches with rfkill-bt. + +Fixes: 82d40b141a4c ("arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b") +Reviewed-by: Dragan Simic +Signed-off-by: FUKAUMI Naoki +Fixes: 82d40b141a4c ("arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b") +Link: https://lore.kernel.org/r/20241128120631.37458-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -72,7 +72,7 @@ + + rfkill { + compatible = "rfkill-gpio"; +- label = "rfkill-pcie-wlan"; ++ label = "rfkill-m2-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + }; diff --git a/target/linux/rockchip/patches-6.12/003-04-v6.15-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch b/target/linux/rockchip/patches-6.12/003-04-v6.15-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch deleted file mode 100644 index e83132ddb2..0000000000 --- a/target/linux/rockchip/patches-6.12/003-04-v6.15-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 3eac9319af62dbc56d1f06fcb240e4a092fa5b2f Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Tue, 25 Feb 2025 11:08:48 +0800 -Subject: arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX - -Enable the HDMI port next to ethernet port. - -Signed-off-by: Jianfeng Liu -Link: https://lore.kernel.org/r/20250225030904.2813023-1-liujianfeng1994@gmail.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include "dt-bindings/usb/pd.h" - #include "rk3588.dtsi" - -@@ -72,6 +73,17 @@ - }; - }; - -+ hdmi1-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi1_con_in: endpoint { -+ remote-endpoint = <&hdmi1_out_con>; -+ }; -+ }; -+ }; -+ - /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ - pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { - compatible = "gated-fixed-clock"; -@@ -261,6 +273,28 @@ - status = "okay"; - }; - -+&hdmi1 { -+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd -+ &hdmim1_tx1_scl &hdmim1_tx1_sda>; -+ status = "okay"; -+}; -+ -+&hdmi1_in { -+ hdmi1_in_vp1: endpoint { -+ remote-endpoint = <&vp1_out_hdmi1>; -+ }; -+}; -+ -+&hdmi1_out { -+ hdmi1_out_con: endpoint { -+ remote-endpoint = <&hdmi1_con_in>; -+ }; -+}; -+ -+&hdptxphy1 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -1208,3 +1242,18 @@ - rockchip,dp-lane-mux = <2 3>; - status = "okay"; - }; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp1 { -+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -+ reg = ; -+ remote-endpoint = <&hdmi1_in_vp1>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.12/003-05-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/003-05-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch deleted file mode 100644 index 8d2e86dfac..0000000000 --- a/target/linux/rockchip/patches-6.12/003-05-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch +++ /dev/null @@ -1,48 +0,0 @@ -From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 20 Feb 2025 19:58:11 +0100 -Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for - RK3588 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enabling the GPU power domain requires that the GPU regulator is -enabled. The regulator is enabled at boot time, but gets disabled -automatically when there are no users. - -This means the system might run into a failure state hanging the -whole system for the following use cases: - - * if the GPU driver is being probed late (e.g. build as a - module and firmware is not in initramfs), the regulator - might already have been disabled. In that case the power - domain is enabled before the regulator. - * unbinding the GPU driver will disable the PM domain and - the regulator. When the driver is bound again, the PM - domain will be enabled before the regulator and error - appears. - -Avoid this by adding an explicit regulator dependency to the -power domain. - -Tested-by: Heiko Stuebner -Reported-by: Adrián Martínez Larumbe -Tested-by: Adrian Larumbe # On Rock 5B -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -@@ -598,6 +598,10 @@ - status = "okay"; - }; - -+&pd_gpu { -+ domain-supply = <&vdd_gpu_s0>; -+}; -+ - &pinctrl { - hym8563 { - rtc_int: rtc-int { diff --git a/target/linux/rockchip/patches-6.12/003-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch b/target/linux/rockchip/patches-6.12/003-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch new file mode 100644 index 0000000000..ee6f743b71 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch @@ -0,0 +1,26 @@ +From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001 +From: Damon Ding +Date: Thu, 6 Feb 2025 11:03:30 +0800 +Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588 + +The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP +and eDP Link. Therefore, it is better to name it hdptxphy0 other than +hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes. + +Signed-off-by: Damon Ding +Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com +[added armsom-sige7, where hdmi-support was added recently and also + the hdptxphy0-as-dclk source I just added] +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -220,7 +220,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + diff --git a/target/linux/rockchip/patches-6.12/003-06-v6.15-arm64-dts-rockchip-Enable-HDMI1-on-rock-5b.patch b/target/linux/rockchip/patches-6.12/003-06-v6.15-arm64-dts-rockchip-Enable-HDMI1-on-rock-5b.patch new file mode 100644 index 0000000000..542a6c375d --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-06-v6.15-arm64-dts-rockchip-Enable-HDMI1-on-rock-5b.patch @@ -0,0 +1,94 @@ +From 77cea7ca13680e14119a3b9635c7ef16cd7ee44e Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Wed, 11 Dec 2024 01:06:17 +0200 +Subject: arm64: dts: rockchip: Enable HDMI1 on rock-5b + +Add the necessary DT changes to enable the second HDMI output port on +Radxa ROCK 5B. + +While at it, switch the position of &vop_mmu and @vop to maintain the +alphabetical order. + +Signed-off-by: Cristian Ciocaltea +Tested-by: Alexandre ARNOUD +Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-4-02cdca22ff68@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -49,6 +49,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -220,10 +231,32 @@ + }; + }; + ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ + &hdptxphy0 { + status = "okay"; + }; + ++&hdptxphy1 { ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +@@ -891,11 +924,11 @@ + status = "okay"; + }; + +-&vop_mmu { ++&vop { + status = "okay"; + }; + +-&vop { ++&vop_mmu { + status = "okay"; + }; + +@@ -905,3 +938,10 @@ + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.12/003-07-v6.15-arm64-dts-rockchip-Enable-HDMI-audio-outputs-for-Roc.patch b/target/linux/rockchip/patches-6.12/003-07-v6.15-arm64-dts-rockchip-Enable-HDMI-audio-outputs-for-Roc.patch new file mode 100644 index 0000000000..2392f45d79 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-07-v6.15-arm64-dts-rockchip-Enable-HDMI-audio-outputs-for-Roc.patch @@ -0,0 +1,54 @@ +From 97aa62ed1e970bf8aa9f57e87c946a95fa3d5bef Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Mon, 17 Feb 2025 16:47:42 -0500 +Subject: arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5B + +HDMI audio is available on the Rock 5B HDMI TX ports. +Enable it for both ports. + +Reviewed-by: Quentin Schulz +Signed-off-by: Detlev Casanova +Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") +Signed-off-by: Kuninori Morimoto +Link: https://lore.kernel.org/r/20250217215641.372723-4-detlev.casanova@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -231,6 +231,10 @@ + }; + }; + ++&hdmi0_sound { ++ status = "okay"; ++}; ++ + &hdmi1 { + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; +@@ -249,6 +253,10 @@ + }; + }; + ++&hdmi1_sound { ++ status = "okay"; ++}; ++ + &hdptxphy0 { + status = "okay"; + }; +@@ -351,6 +359,14 @@ + }; + }; + ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ + &package_thermal { + polling-delay = <1000>; + diff --git a/target/linux/rockchip/patches-6.12/003-08-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/003-08-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch new file mode 100644 index 0000000000..13de83b80c --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-08-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch @@ -0,0 +1,48 @@ +From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Feb 2025 19:58:11 +0100 +Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for + RK3588 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enabling the GPU power domain requires that the GPU regulator is +enabled. The regulator is enabled at boot time, but gets disabled +automatically when there are no users. + +This means the system might run into a failure state hanging the +whole system for the following use cases: + + * if the GPU driver is being probed late (e.g. build as a + module and firmware is not in initramfs), the regulator + might already have been disabled. In that case the power + domain is enabled before the regulator. + * unbinding the GPU driver will disable the PM domain and + the regulator. When the driver is bound again, the PM + domain will be enabled before the regulator and error + appears. + +Avoid this by adding an explicit regulator dependency to the +power domain. + +Tested-by: Heiko Stuebner +Reported-by: Adrián Martínez Larumbe +Tested-by: Adrian Larumbe # On Rock 5B +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -425,6 +425,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { diff --git a/target/linux/rockchip/patches-6.12/003-09-v6.15-arm64-dts-rockchip-Enable-HDMI-receiver-on-rock-5b.patch b/target/linux/rockchip/patches-6.12/003-09-v6.15-arm64-dts-rockchip-Enable-HDMI-receiver-on-rock-5b.patch new file mode 100644 index 0000000000..897d043364 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-09-v6.15-arm64-dts-rockchip-Enable-HDMI-receiver-on-rock-5b.patch @@ -0,0 +1,47 @@ +From c62d8fdb27391ee72bfdf53328463813997844f1 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 7 Mar 2025 12:18:57 +0300 +Subject: arm64: dts: rockchip: Enable HDMI receiver on rock-5b + +The Rock 5B has a Micro HDMI port, which can be used for receiving +HDMI data. This enables support for it. + +Signed-off-by: Sebastian Reichel +Signed-off-by: Shreeya Patel +Signed-off-by: Dmitry Osipenko +Link: https://lore.kernel.org/r/20250307091857.646581-3-dmitry.osipenko@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -257,6 +257,17 @@ + status = "okay"; + }; + ++&hdmi_receiver_cma { ++ status = "okay"; ++}; ++ ++&hdmi_receiver { ++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ + &hdptxphy0 { + status = "okay"; + }; +@@ -430,6 +441,12 @@ + }; + + &pinctrl { ++ hdmirx { ++ hdmirx_hpd: hdmirx-5v-detection { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.12/003-10-v6.16-arm64-dts-rockchip-Add-vcc-supply-to-SPI-flash-on-rk.patch b/target/linux/rockchip/patches-6.12/003-10-v6.16-arm64-dts-rockchip-Add-vcc-supply-to-SPI-flash-on-rk.patch new file mode 100644 index 0000000000..92ad95c4a3 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-10-v6.16-arm64-dts-rockchip-Add-vcc-supply-to-SPI-flash-on-rk.patch @@ -0,0 +1,28 @@ +From 425af91c58023a8924cc2330384e040d388adc4e Mon Sep 17 00:00:00 2001 +From: Diederik de Haas +Date: Fri, 25 Apr 2025 10:44:44 +0200 +Subject: arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3588-rock-5b + +The Radxa Rock 5B component placement document identifies the SPI Nor +Flash chip as 'U4300' which is described on page 25 of the Schematic +v1.45. There we can see that the VCC connector is connected to the +VCC_3V3_S3 power source. + +This fixes the following warning: + + spi-nor spi5.0: supply vcc not found, using dummy regulator + +Signed-off-by: Diederik de Haas +Link: https://lore.kernel.org/r/20250425092601.56549-5-didi.debian@cknow.org +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -562,6 +562,7 @@ + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; ++ vcc-supply = <&vcc_3v3_s3>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.12/003-11-v6.16-arm64-dts-rockchip-move-rock-5b-to-include-file.patch b/target/linux/rockchip/patches-6.12/003-11-v6.16-arm64-dts-rockchip-move-rock-5b-to-include-file.patch new file mode 100644 index 0000000000..7760f00de1 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-11-v6.16-arm64-dts-rockchip-move-rock-5b-to-include-file.patch @@ -0,0 +1,1948 @@ +From aadfbdcf7e1e7f3892e0e4bdcc3c9c7c9adfb723 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 8 May 2025 19:48:50 +0200 +Subject: arm64: dts: rockchip: move rock 5b to include file + +Radxa released some more boards, which are based on the original +Rock 5B. Move its board description into an include file to avoid +unnecessary duplication. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-1-677033cc1ac2@kernel.org +Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-2-677033cc1ac2@kernel.org + +[The original submission was split into two elements, renaming the file + and then moving some nodes around. This was done to make review easier + due to the diff being smaller. This commit is a squash of both of them + to facilitate bisectability and was also intended by the original author] +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -2,532 +2,11 @@ + + /dts-v1/; + +-#include +-#include +-#include +-#include "rk3588.dtsi" ++#include "rk3588-rock-5b.dtsi" + + / { + model = "Radxa ROCK 5B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; +- +- aliases { +- mmc0 = &sdhci; +- mmc1 = &sdmmc; +- mmc2 = &sdio; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- analog-sound { +- compatible = "audio-graph-card"; +- label = "rk3588-es8316"; +- +- widgets = "Microphone", "Mic Jack", +- "Headphone", "Headphones"; +- +- routing = "MIC2", "Mic Jack", +- "Headphones", "HPOL", +- "Headphones", "HPOR"; +- +- dais = <&i2s0_8ch_p0>; +- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hp_detect>; +- }; +- +- hdmi0-con { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi0_con_in: endpoint { +- remote-endpoint = <&hdmi0_out_con>; +- }; +- }; +- }; +- +- hdmi1-con { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi1_con_in: endpoint { +- remote-endpoint = <&hdmi1_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_rgb_b>; +- +- led_rgb_b { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- fan: pwm-fan { +- compatible = "pwm-fan"; +- cooling-levels = <0 120 150 180 210 240 255>; +- fan-supply = <&vcc5v0_sys>; +- pwms = <&pwm1 0 50000 0>; +- #cooling-cells = <2>; +- }; +- +- rfkill { +- compatible = "rfkill-gpio"; +- label = "rfkill-m2-wlan"; +- radio-type = "wlan"; +- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; +- }; +- +- rfkill-bt { +- compatible = "rfkill-gpio"; +- label = "rfkill-m2-bt"; +- radio-type = "bluetooth"; +- shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- }; +- +- vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_0_vcc3v3_en>; +- regulator-name = "vcc3v3_pcie2x1l0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <50000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_pcie2x1l2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <5000>; +- vin-supply = <&vcc_3v3_s3>; +- }; +- +- vcc3v3_pcie30: regulator-vcc3v3-pcie30 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_vcc3v3_en>; +- regulator-name = "vcc3v3_pcie30"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <5000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_host: regulator-vcc5v0-host { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_host"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_sys: regulator-vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_1v1_nldo_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&combphy0_ps { +- status = "okay"; +-}; +- +-&combphy1_ps { +- status = "okay"; +-}; +- +-&combphy2_psu { +- status = "okay"; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_big0_s0>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_big0_s0>; +-}; +- +-&cpu_b2 { +- cpu-supply = <&vdd_cpu_big1_s0>; +-}; +- +-&cpu_b3 { +- cpu-supply = <&vdd_cpu_big1_s0>; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu_s0>; +- status = "okay"; +-}; +- +-&hdmi0 { +- status = "okay"; +-}; +- +-&hdmi0_in { +- hdmi0_in_vp0: endpoint { +- remote-endpoint = <&vp0_out_hdmi0>; +- }; +-}; +- +-&hdmi0_out { +- hdmi0_out_con: endpoint { +- remote-endpoint = <&hdmi0_con_in>; +- }; +-}; +- +-&hdmi0_sound { +- status = "okay"; +-}; +- +-&hdmi1 { +- pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd +- &hdmim1_tx1_scl &hdmim1_tx1_sda>; +- status = "okay"; +-}; +- +-&hdmi1_in { +- hdmi1_in_vp1: endpoint { +- remote-endpoint = <&vp1_out_hdmi1>; +- }; +-}; +- +-&hdmi1_out { +- hdmi1_out_con: endpoint { +- remote-endpoint = <&hdmi1_con_in>; +- }; +-}; +- +-&hdmi1_sound { +- status = "okay"; +-}; +- +-&hdmi_receiver_cma { +- status = "okay"; +-}; +- +-&hdmi_receiver { +- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&hdptxphy0 { +- status = "okay"; +-}; +- +-&hdptxphy1 { +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0m2_xfer>; +- status = "okay"; +- +- vdd_cpu_big0_s0: regulator@42 { +- compatible = "rockchip,rk8602"; +- reg = <0x42>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_big0_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_big1_s0: regulator@43 { +- compatible = "rockchip,rk8603", "rockchip,rk8602"; +- reg = <0x43>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_big1_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- +- hym8563: rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-output-names = "hym8563"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hym8563_int>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- wakeup-source; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- es8316: audio-codec@11 { +- compatible = "everest,es8316"; +- reg = <0x11>; +- clocks = <&cru I2S0_8CH_MCLKOUT>; +- clock-names = "mclk"; +- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +- assigned-clock-rates = <12288000>; +- #sound-dai-cells = <0>; +- +- port { +- es8316_p0_0: endpoint { +- remote-endpoint = <&i2s0_8ch_p0_0>; +- }; +- }; +- }; +-}; +- +-&i2s0_8ch { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_lrck +- &i2s0_mclk +- &i2s0_sclk +- &i2s0_sdi0 +- &i2s0_sdo0>; +- status = "okay"; +- +- i2s0_8ch_p0: port { +- i2s0_8ch_p0_0: endpoint { +- dai-format = "i2s"; +- mclk-fs = <256>; +- remote-endpoint = <&es8316_p0_0>; +- }; +- }; +-}; +- +-&i2s5_8ch { +- status = "okay"; +-}; +- +-&i2s6_8ch { +- status = "okay"; +-}; +- +-&package_thermal { +- polling-delay = <1000>; +- +- trips { +- package_fan0: package-fan0 { +- temperature = <55000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- package_fan1: package-fan1 { +- temperature = <65000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&package_fan0>; +- cooling-device = <&fan THERMAL_NO_LIMIT 1>; +- }; +- +- map1 { +- trip = <&package_fan1>; +- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&pcie2x1l0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_0_rst>; +- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; +- status = "okay"; +-}; +- +-&pcie2x1l2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_2_rst>; +- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; +- status = "okay"; +-}; +- +-&pcie30phy { +- status = "okay"; +-}; +- +-&pcie3x4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_rst>; +- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie30>; +- status = "okay"; +-}; +- +-&pd_gpu { +- domain-supply = <&vdd_gpu_s0>; +-}; +- +-&pinctrl { +- hdmirx { +- hdmirx_hpd: hdmirx-5v-detection { +- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hym8563 { +- hym8563_int: hym8563-int { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- leds { +- led_rgb_b: led-rgb-b { +- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sound { +- hp_detect: hp-detect { +- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie2 { +- pcie2_0_rst: pcie2-0-rst { +- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie2_0_vcc3v3_en: pcie2-0-vcc-en { +- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie2_2_rst: pcie2-2-rst { +- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie3 { +- pcie3_rst: pcie3-rst { +- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie3_vcc3v3_en: pcie3-vcc3v3-en { +- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&avcc_1v8_s0>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- no-sdio; +- no-sd; +- non-removable; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- status = "okay"; +-}; +- +-&sdmmc { +- max-frequency = <200000000>; +- no-sdio; +- no-mmc; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +- disable-wp; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_3v3_s3>; +- vqmmc-supply = <&vccio_sd_s0>; +- status = "okay"; + }; + + &sdio { +@@ -551,435 +30,23 @@ + status = "okay"; + }; + +-&sfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&fspim2_pins>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- vcc-supply = <&vcc_3v3_s3>; +- }; +-}; +- + &uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status = "okay"; + }; + +-&spi2 { +- status = "okay"; +- assigned-clocks = <&cru CLK_SPI2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; +- num-cs = <1>; +- +- pmic@0 { +- compatible = "rockchip,rk806"; +- spi-max-frequency = <1000000>; +- reg = <0x0>; +- +- interrupt-parent = <&gpio0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, +- <&rk806_dvs2_null>, <&rk806_dvs3_null>; +- +- system-power-controller; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc5-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc5v0_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc_2v0_pldo_s3>; +- vcc12-supply = <&vcc5v0_sys>; +- vcc13-supply = <&vcc_1v1_nldo_s3>; +- vcc14-supply = <&vcc_1v1_nldo_s3>; +- vcca-supply = <&vcc5v0_sys>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- rk806_dvs1_null: dvs1-null-pins { +- pins = "gpio_pwrctrl1"; +- function = "pin_fun0"; +- }; +- +- rk806_dvs2_null: dvs2-null-pins { +- pins = "gpio_pwrctrl2"; +- function = "pin_fun0"; +- }; +- +- rk806_dvs3_null: dvs3-null-pins { +- pins = "gpio_pwrctrl3"; +- function = "pin_fun0"; +- }; +- +- regulators { +- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_gpu_s0"; +- regulator-enable-ramp-delay = <400>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_cpu_lit_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_log_s0: dcdc-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <750000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_log_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <750000>; +- }; +- }; +- +- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_vdenc_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_ddr_s0: dcdc-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <900000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_ddr_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <850000>; +- }; +- }; +- +- vdd2_ddr_s3: dcdc-reg6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vdd2_ddr_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_2v0_pldo_s3: dcdc-reg7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_2v0_pldo_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <2000000>; +- }; +- }; +- +- vcc_3v3_s3: dcdc-reg8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_3v3_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vddq_ddr_s0: dcdc-reg9 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vddq_ddr_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8_s3: dcdc-reg10 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_1v8_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- avcc_1v8_s0: pldo-reg1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "avcc_1v8_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8_s0: pldo-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_1v8_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- avdd_1v2_s0: pldo-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "avdd_1v2_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v3_s0: pldo-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vcc_3v3_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vccio_sd_s0: pldo-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vccio_sd_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- pldo6_s3: pldo-reg6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "pldo6_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_0v75_s3: nldo-reg1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "vdd_0v75_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <750000>; +- }; +- }; +- +- vdd_ddr_pll_s0: nldo-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-name = "vdd_ddr_pll_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <850000>; +- }; +- }; +- +- avdd_0v75_s0: nldo-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "avdd_0v75_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_0v85_s0: nldo-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-name = "vdd_0v85_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_0v75_s0: nldo-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "vdd_0v75_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; ++&pinctrl { ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + +-&tsadc { +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-0 = <&uart2m0_xfer>; +- status = "okay"; +-}; +- +-&u2phy1 { +- status = "okay"; +-}; +- +-&u2phy1_otg { +- status = "okay"; +-}; +- +-&u2phy2 { +- status = "okay"; +-}; +- +-&u2phy2_host { +- /* connected to USB hub, which is powered by vcc5v0_sys */ +- phy-supply = <&vcc5v0_sys>; +- status = "okay"; +-}; +- +-&u2phy3 { +- status = "okay"; +-}; +- +-&u2phy3_host { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +-}; +- +-&usbdp_phy1 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usb_host1_xhci { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host2_xhci { +- status = "okay"; +-}; +- +-&vop { +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +- +-&vp0 { +- vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { +- reg = ; +- remote-endpoint = <&hdmi0_in_vp0>; +- }; +-}; +- +-&vp1 { +- vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { +- reg = ; +- remote-endpoint = <&hdmi1_in_vp1>; +- }; ++&vcc5v0_host { ++ enable-active-high; ++ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; + }; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi +@@ -0,0 +1,945 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3588.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ mmc2 = &sdio; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ analog-sound { ++ compatible = "audio-graph-card"; ++ label = "rk3588-es8316"; ++ ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ ++ dais = <&i2s0_8ch_p0>; ++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ }; ++ ++ hdmi0-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi0_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_b>; ++ ++ led_rgb_b { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ cooling-levels = <0 120 150 180 210 240 255>; ++ fan-supply = <&vcc5v0_sys>; ++ pwms = <&pwm1 0 50000 0>; ++ #cooling-cells = <2>; ++ }; ++ ++ rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ rfkill-bt { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-bt"; ++ radio-type = "bluetooth"; ++ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_vcc3v3_en>; ++ regulator-name = "vcc3v3_pcie2x1l0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l2"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc3v3_pcie30: regulator-vcc3v3-pcie30 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_vcc3v3_en>; ++ regulator-name = "vcc3v3_pcie30"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_host: regulator-vcc5v0-host { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy1_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi0_con_in>; ++ }; ++}; ++ ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { ++ status = "okay"; ++}; ++ ++&hdmi_receiver_cma { ++ status = "okay"; ++}; ++ ++&hdmi_receiver { ++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&i2c7 { ++ status = "okay"; ++ ++ es8316: audio-codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_8ch_p0_0>; ++ }; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++ ++ i2s0_8ch_p0: port { ++ i2s0_8ch_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; ++}; ++ ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map1 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&pcie2x1l0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_rst>; ++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; ++ status = "okay"; ++}; ++ ++&pcie2x1l2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_2_rst>; ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_rst>; ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ ++&pinctrl { ++ hdmirx { ++ hdmirx_hpd: hdmirx-5v-detection { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_rgb_b: led-rgb-b { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie2 { ++ pcie2_0_rst: pcie2-0-rst { ++ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_2_rst: pcie2-2-rst { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie3 { ++ pcie3_rst: pcie3-rst { ++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie3_vcc3v3_en: pcie3-vcc3v3-en { ++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ max-frequency = <200000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&sfc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fspim2_pins>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ vcc-supply = <&vcc_3v3_s3>; ++ }; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ num-cs = <1>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <1000000>; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ system-power-controller; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ /* connected to USB hub, which is powered by vcc5v0_sys */ ++ phy-supply = <&vcc5v0_sys>; ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usbdp_phy1 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host2_xhci { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.12/003-12-v6.16-arm64-dts-rockchip-add-Rock-5B.patch b/target/linux/rockchip/patches-6.12/003-12-v6.16-arm64-dts-rockchip-add-Rock-5B.patch new file mode 100644 index 0000000000..f83c945638 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-12-v6.16-arm64-dts-rockchip-add-Rock-5B.patch @@ -0,0 +1,149 @@ +From 376cb9696298df2028afb620a9dc6c4b10a18605 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 8 May 2025 19:48:53 +0200 +Subject: arm64: dts: rockchip: add Rock 5B+ + +Add ROCK 5B+, which is an improved version of the ROCK 5B with the +following changes: + + * Memory LPDDR4X -> LPDDR5 + * HDMI input connector size + * eMMC socket -> onboard + * M.2 E-Key is replaced by onboard RTL8852BE WLAN/BT + * M.2 M-Key 1x4 lanes is replaced by 2x2 lanes + * Added M.2 B-Key for USB connected WWAN modules (untested) + * Add second camera port (not yet supported in upstream Linux) + * Add dedicated USB-C port for device power (no impact in DT; + the existing port has not been changed and the new port is + handled by CH224D standalone chip) + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-4-677033cc1ac2@kernel.org +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts +@@ -0,0 +1,113 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3588-rock-5b.dtsi" ++ ++/ { ++ model = "Radxa ROCK 5B+"; ++ compatible = "radxa,rock-5b-plus", "rockchip,rk3588"; ++ ++ rfkill-wwan { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-wwan"; ++ radio-type = "wwan"; ++ shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vcc3v3_4g: regulator-vcc3v3-4g { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ /* pinctrl for the GPIO is requested by vcc3v3_pcie2x1l0 */ ++ regulator-name = "vcc3v3_4g"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_wwan_pwr: regulator-vcc3v3-wwan { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wwan_power_en>; ++ regulator-name = "vcc3v3_wwan_pwr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_4g>; ++ }; ++}; ++ ++&gpio0 { ++ wwan-disable2-n-hog { ++ gpios = ; ++ output-low; ++ line-name = "M.2 B-key W_DISABLE2#"; ++ gpio-hog; ++ }; ++}; ++ ++&gpio2 { ++ wwan-reset-n-hog { ++ gpios = ; ++ output-low; ++ line-name = "M.2 B-key RESET#"; ++ gpio-hog; ++ }; ++ ++ wwan-wake-n-hog { ++ gpios = ; ++ input; ++ line-name = "M.2 B-key WoWWAN#"; ++ gpio-hog; ++ }; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 1 2 2>; ++}; ++ ++&pcie3x2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3x2_rst>; ++ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ num-lanes = <2>; ++}; ++ ++&pinctrl { ++ wwan { ++ wwan_power_en: wwan-pwr-en { ++ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie3 { ++ pcie3x2_rst: pcie3x2-rst { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&vcc5v0_host { ++ enable-active-high; ++ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++}; diff --git a/target/linux/rockchip/patches-6.12/003-13-v6.17-arm64-dts-rockchip-rename-rk3588-rock-5b.dtsi.patch b/target/linux/rockchip/patches-6.12/003-13-v6.17-arm64-dts-rockchip-rename-rk3588-rock-5b.dtsi.patch new file mode 100644 index 0000000000..65eebe02f2 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-13-v6.17-arm64-dts-rockchip-rename-rk3588-rock-5b.dtsi.patch @@ -0,0 +1,1934 @@ +From 8b76abf78321ea3361c01e849c8dc3a6793c05d6 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 20 May 2025 20:50:09 +0200 +Subject: arm64: dts: rockchip: rename rk3588-rock-5b.dtsi + +As subsequent patches will add ROCK 5T support, rename the .dtsi file to +reflect that it's shared between ROCK 5B, ROCK 5B+ and ROCK 5T. + +This is done separately from moving the 5B and 5B+ only nodes to a +common tree so that the history stays bisectable and the diff easily +reviewable. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-2-1f1971850a20@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts +@@ -2,7 +2,7 @@ + + /dts-v1/; + +-#include "rk3588-rock-5b.dtsi" ++#include "rk3588-rock-5b-5bp-5t.dtsi" + + / { + model = "Radxa ROCK 5B+"; +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -2,7 +2,7 @@ + + /dts-v1/; + +-#include "rk3588-rock-5b.dtsi" ++#include "rk3588-rock-5b-5bp-5t.dtsi" + + / { + model = "Radxa ROCK 5B"; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +@@ -0,0 +1,945 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3588.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ mmc2 = &sdio; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ analog-sound { ++ compatible = "audio-graph-card"; ++ label = "rk3588-es8316"; ++ ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ ++ dais = <&i2s0_8ch_p0>; ++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ }; ++ ++ hdmi0-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi0_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_b>; ++ ++ led_rgb_b { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ cooling-levels = <0 120 150 180 210 240 255>; ++ fan-supply = <&vcc5v0_sys>; ++ pwms = <&pwm1 0 50000 0>; ++ #cooling-cells = <2>; ++ }; ++ ++ rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ rfkill-bt { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-bt"; ++ radio-type = "bluetooth"; ++ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_vcc3v3_en>; ++ regulator-name = "vcc3v3_pcie2x1l0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l2"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc3v3_pcie30: regulator-vcc3v3-pcie30 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_vcc3v3_en>; ++ regulator-name = "vcc3v3_pcie30"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_host: regulator-vcc5v0-host { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy1_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi0_con_in>; ++ }; ++}; ++ ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { ++ status = "okay"; ++}; ++ ++&hdmi_receiver_cma { ++ status = "okay"; ++}; ++ ++&hdmi_receiver { ++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&i2c7 { ++ status = "okay"; ++ ++ es8316: audio-codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_8ch_p0_0>; ++ }; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++ ++ i2s0_8ch_p0: port { ++ i2s0_8ch_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; ++}; ++ ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map1 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&pcie2x1l0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_rst>; ++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; ++ status = "okay"; ++}; ++ ++&pcie2x1l2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_2_rst>; ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_rst>; ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ ++&pinctrl { ++ hdmirx { ++ hdmirx_hpd: hdmirx-5v-detection { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_rgb_b: led-rgb-b { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie2 { ++ pcie2_0_rst: pcie2-0-rst { ++ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_2_rst: pcie2-2-rst { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie3 { ++ pcie3_rst: pcie3-rst { ++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie3_vcc3v3_en: pcie3-vcc3v3-en { ++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ max-frequency = <200000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&sfc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fspim2_pins>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ vcc-supply = <&vcc_3v3_s3>; ++ }; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ num-cs = <1>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <1000000>; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ system-power-controller; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ /* connected to USB hub, which is powered by vcc5v0_sys */ ++ phy-supply = <&vcc5v0_sys>; ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usbdp_phy1 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host2_xhci { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi ++++ /dev/null +@@ -1,945 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include "rk3588.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdhci; +- mmc1 = &sdmmc; +- mmc2 = &sdio; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- analog-sound { +- compatible = "audio-graph-card"; +- label = "rk3588-es8316"; +- +- widgets = "Microphone", "Mic Jack", +- "Headphone", "Headphones"; +- +- routing = "MIC2", "Mic Jack", +- "Headphones", "HPOL", +- "Headphones", "HPOR"; +- +- dais = <&i2s0_8ch_p0>; +- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hp_detect>; +- }; +- +- hdmi0-con { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi0_con_in: endpoint { +- remote-endpoint = <&hdmi0_out_con>; +- }; +- }; +- }; +- +- hdmi1-con { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi1_con_in: endpoint { +- remote-endpoint = <&hdmi1_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_rgb_b>; +- +- led_rgb_b { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- fan: pwm-fan { +- compatible = "pwm-fan"; +- cooling-levels = <0 120 150 180 210 240 255>; +- fan-supply = <&vcc5v0_sys>; +- pwms = <&pwm1 0 50000 0>; +- #cooling-cells = <2>; +- }; +- +- rfkill { +- compatible = "rfkill-gpio"; +- label = "rfkill-m2-wlan"; +- radio-type = "wlan"; +- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; +- }; +- +- rfkill-bt { +- compatible = "rfkill-gpio"; +- label = "rfkill-m2-bt"; +- radio-type = "bluetooth"; +- shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- }; +- +- vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_0_vcc3v3_en>; +- regulator-name = "vcc3v3_pcie2x1l0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <50000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_pcie2x1l2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <5000>; +- vin-supply = <&vcc_3v3_s3>; +- }; +- +- vcc3v3_pcie30: regulator-vcc3v3-pcie30 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_vcc3v3_en>; +- regulator-name = "vcc3v3_pcie30"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <5000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_host: regulator-vcc5v0-host { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_host"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_sys: regulator-vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_1v1_nldo_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&combphy0_ps { +- status = "okay"; +-}; +- +-&combphy1_ps { +- status = "okay"; +-}; +- +-&combphy2_psu { +- status = "okay"; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_big0_s0>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_big0_s0>; +-}; +- +-&cpu_b2 { +- cpu-supply = <&vdd_cpu_big1_s0>; +-}; +- +-&cpu_b3 { +- cpu-supply = <&vdd_cpu_big1_s0>; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu_s0>; +- status = "okay"; +-}; +- +-&hdmi0 { +- status = "okay"; +-}; +- +-&hdmi0_in { +- hdmi0_in_vp0: endpoint { +- remote-endpoint = <&vp0_out_hdmi0>; +- }; +-}; +- +-&hdmi0_out { +- hdmi0_out_con: endpoint { +- remote-endpoint = <&hdmi0_con_in>; +- }; +-}; +- +-&hdmi0_sound { +- status = "okay"; +-}; +- +-&hdmi1 { +- pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd +- &hdmim1_tx1_scl &hdmim1_tx1_sda>; +- status = "okay"; +-}; +- +-&hdmi1_in { +- hdmi1_in_vp1: endpoint { +- remote-endpoint = <&vp1_out_hdmi1>; +- }; +-}; +- +-&hdmi1_out { +- hdmi1_out_con: endpoint { +- remote-endpoint = <&hdmi1_con_in>; +- }; +-}; +- +-&hdmi1_sound { +- status = "okay"; +-}; +- +-&hdmi_receiver_cma { +- status = "okay"; +-}; +- +-&hdmi_receiver { +- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&hdptxphy0 { +- status = "okay"; +-}; +- +-&hdptxphy1 { +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0m2_xfer>; +- status = "okay"; +- +- vdd_cpu_big0_s0: regulator@42 { +- compatible = "rockchip,rk8602"; +- reg = <0x42>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_big0_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_big1_s0: regulator@43 { +- compatible = "rockchip,rk8603", "rockchip,rk8602"; +- reg = <0x43>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_big1_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- +- hym8563: rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-output-names = "hym8563"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hym8563_int>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- wakeup-source; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- es8316: audio-codec@11 { +- compatible = "everest,es8316"; +- reg = <0x11>; +- clocks = <&cru I2S0_8CH_MCLKOUT>; +- clock-names = "mclk"; +- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +- assigned-clock-rates = <12288000>; +- #sound-dai-cells = <0>; +- +- port { +- es8316_p0_0: endpoint { +- remote-endpoint = <&i2s0_8ch_p0_0>; +- }; +- }; +- }; +-}; +- +-&i2s0_8ch { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_lrck +- &i2s0_mclk +- &i2s0_sclk +- &i2s0_sdi0 +- &i2s0_sdo0>; +- status = "okay"; +- +- i2s0_8ch_p0: port { +- i2s0_8ch_p0_0: endpoint { +- dai-format = "i2s"; +- mclk-fs = <256>; +- remote-endpoint = <&es8316_p0_0>; +- }; +- }; +-}; +- +-&i2s5_8ch { +- status = "okay"; +-}; +- +-&i2s6_8ch { +- status = "okay"; +-}; +- +-&package_thermal { +- polling-delay = <1000>; +- +- trips { +- package_fan0: package-fan0 { +- temperature = <55000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- package_fan1: package-fan1 { +- temperature = <65000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&package_fan0>; +- cooling-device = <&fan THERMAL_NO_LIMIT 1>; +- }; +- +- map1 { +- trip = <&package_fan1>; +- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&pcie2x1l0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_0_rst>; +- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; +- status = "okay"; +-}; +- +-&pcie2x1l2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_2_rst>; +- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; +- status = "okay"; +-}; +- +-&pcie30phy { +- status = "okay"; +-}; +- +-&pcie3x4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_rst>; +- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie30>; +- status = "okay"; +-}; +- +-&pd_gpu { +- domain-supply = <&vdd_gpu_s0>; +-}; +- +-&pinctrl { +- hdmirx { +- hdmirx_hpd: hdmirx-5v-detection { +- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- hym8563 { +- hym8563_int: hym8563-int { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- leds { +- led_rgb_b: led-rgb-b { +- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sound { +- hp_detect: hp-detect { +- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie2 { +- pcie2_0_rst: pcie2-0-rst { +- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie2_0_vcc3v3_en: pcie2-0-vcc-en { +- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie2_2_rst: pcie2-2-rst { +- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie3 { +- pcie3_rst: pcie3-rst { +- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie3_vcc3v3_en: pcie3-vcc3v3-en { +- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&avcc_1v8_s0>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- no-sdio; +- no-sd; +- non-removable; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- status = "okay"; +-}; +- +-&sdmmc { +- max-frequency = <200000000>; +- no-sdio; +- no-mmc; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +- disable-wp; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_3v3_s3>; +- vqmmc-supply = <&vccio_sd_s0>; +- status = "okay"; +-}; +- +-&sfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&fspim2_pins>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- vcc-supply = <&vcc_3v3_s3>; +- }; +-}; +- +-&spi2 { +- status = "okay"; +- assigned-clocks = <&cru CLK_SPI2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; +- num-cs = <1>; +- +- pmic@0 { +- compatible = "rockchip,rk806"; +- spi-max-frequency = <1000000>; +- reg = <0x0>; +- +- interrupt-parent = <&gpio0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, +- <&rk806_dvs2_null>, <&rk806_dvs3_null>; +- +- system-power-controller; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc5-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc5v0_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc_2v0_pldo_s3>; +- vcc12-supply = <&vcc5v0_sys>; +- vcc13-supply = <&vcc_1v1_nldo_s3>; +- vcc14-supply = <&vcc_1v1_nldo_s3>; +- vcca-supply = <&vcc5v0_sys>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- rk806_dvs1_null: dvs1-null-pins { +- pins = "gpio_pwrctrl1"; +- function = "pin_fun0"; +- }; +- +- rk806_dvs2_null: dvs2-null-pins { +- pins = "gpio_pwrctrl2"; +- function = "pin_fun0"; +- }; +- +- rk806_dvs3_null: dvs3-null-pins { +- pins = "gpio_pwrctrl3"; +- function = "pin_fun0"; +- }; +- +- regulators { +- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_gpu_s0"; +- regulator-enable-ramp-delay = <400>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_cpu_lit_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_log_s0: dcdc-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <750000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_log_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <750000>; +- }; +- }; +- +- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_vdenc_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_ddr_s0: dcdc-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <900000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_ddr_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <850000>; +- }; +- }; +- +- vdd2_ddr_s3: dcdc-reg6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vdd2_ddr_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_2v0_pldo_s3: dcdc-reg7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_2v0_pldo_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <2000000>; +- }; +- }; +- +- vcc_3v3_s3: dcdc-reg8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_3v3_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vddq_ddr_s0: dcdc-reg9 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vddq_ddr_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8_s3: dcdc-reg10 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_1v8_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- avcc_1v8_s0: pldo-reg1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "avcc_1v8_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8_s0: pldo-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_1v8_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- avdd_1v2_s0: pldo-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "avdd_1v2_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v3_s0: pldo-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vcc_3v3_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vccio_sd_s0: pldo-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vccio_sd_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- pldo6_s3: pldo-reg6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "pldo6_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_0v75_s3: nldo-reg1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "vdd_0v75_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <750000>; +- }; +- }; +- +- vdd_ddr_pll_s0: nldo-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-name = "vdd_ddr_pll_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <850000>; +- }; +- }; +- +- avdd_0v75_s0: nldo-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "avdd_0v75_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_0v85_s0: nldo-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-name = "vdd_0v85_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_0v75_s0: nldo-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "vdd_0v75_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&tsadc { +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-0 = <&uart2m0_xfer>; +- status = "okay"; +-}; +- +-&u2phy1 { +- status = "okay"; +-}; +- +-&u2phy1_otg { +- status = "okay"; +-}; +- +-&u2phy2 { +- status = "okay"; +-}; +- +-&u2phy2_host { +- /* connected to USB hub, which is powered by vcc5v0_sys */ +- phy-supply = <&vcc5v0_sys>; +- status = "okay"; +-}; +- +-&u2phy3 { +- status = "okay"; +-}; +- +-&u2phy3_host { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +-}; +- +-&usbdp_phy1 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usb_host1_xhci { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host2_xhci { +- status = "okay"; +-}; +- +-&vop { +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +- +-&vp0 { +- vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { +- reg = ; +- remote-endpoint = <&hdmi0_in_vp0>; +- }; +-}; +- +-&vp1 { +- vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { +- reg = ; +- remote-endpoint = <&hdmi1_in_vp1>; +- }; +-}; diff --git a/target/linux/rockchip/patches-6.12/003-14-v6.17-arm64-dts-rockchip-move-common-ROCK-5B-nodes-into-ow.patch b/target/linux/rockchip/patches-6.12/003-14-v6.17-arm64-dts-rockchip-move-common-ROCK-5B-nodes-into-ow.patch new file mode 100644 index 0000000000..6b9035d34f --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-14-v6.17-arm64-dts-rockchip-move-common-ROCK-5B-nodes-into-ow.patch @@ -0,0 +1,265 @@ +From 988035f152709549a095b12fcdcb3cf26cbad63f Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 20 May 2025 20:50:10 +0200 +Subject: arm64: dts: rockchip: move common ROCK 5B/+ nodes into own tree + +A few device tree nodes are shared between ROCK 5B and ROCK 5B+ that are +not shared with ROCK 5T. + +Move them into their own device tree include. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-3-1f1971850a20@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +@@ -18,23 +18,6 @@ + stdout-path = "serial2:1500000n8"; + }; + +- analog-sound { +- compatible = "audio-graph-card"; +- label = "rk3588-es8316"; +- +- widgets = "Microphone", "Mic Jack", +- "Headphone", "Headphones"; +- +- routing = "MIC2", "Mic Jack", +- "Headphones", "HPOL", +- "Headphones", "HPOR"; +- +- dais = <&i2s0_8ch_p0>; +- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hp_detect>; +- }; +- + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; +@@ -57,19 +40,6 @@ + }; + }; + +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_rgb_b>; +- +- led_rgb_b { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 120 150 180 210 240 255>; +@@ -78,13 +48,6 @@ + #cooling-cells = <2>; + }; + +- rfkill { +- compatible = "rfkill-gpio"; +- label = "rfkill-m2-wlan"; +- radio-type = "wlan"; +- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; +- }; +- + rfkill-bt { + compatible = "rfkill-gpio"; + label = "rfkill-m2-bt"; +@@ -95,9 +58,6 @@ + vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + enable-active-high; +- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_0_vcc3v3_en>; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-always-on; + regulator-boot-on; +@@ -105,6 +65,7 @@ + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; ++ status = "disabled"; + }; + + vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { +@@ -255,10 +216,8 @@ + }; + + &hdmi_receiver { +- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; +- status = "okay"; + }; + + &hdptxphy0 { +@@ -434,39 +393,17 @@ + }; + + &pinctrl { +- hdmirx { +- hdmirx_hpd: hdmirx-5v-detection { +- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +- leds { +- led_rgb_b: led-rgb-b { +- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sound { +- hp_detect: hp-detect { +- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + +- pcie2_0_vcc3v3_en: pcie2-0-vcc-en { +- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; +@@ -918,10 +855,6 @@ + status = "okay"; + }; + +-&usb_host2_xhci { +- status = "okay"; +-}; +- + &vop { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts +@@ -2,7 +2,7 @@ + + /dts-v1/; + +-#include "rk3588-rock-5b-5bp-5t.dtsi" ++#include "rk3588-rock-5b.dtsi" + + / { + model = "Radxa ROCK 5B+"; +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -2,7 +2,7 @@ + + /dts-v1/; + +-#include "rk3588-rock-5b-5bp-5t.dtsi" ++#include "rk3588-rock-5b.dtsi" + + / { + model = "Radxa ROCK 5B"; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi +@@ -0,0 +1,86 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3588-rock-5b-5bp-5t.dtsi" ++ ++/ { ++ analog-sound { ++ compatible = "audio-graph-card"; ++ label = "rk3588-es8316"; ++ ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ ++ dais = <&i2s0_8ch_p0>; ++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_b>; ++ ++ led_rgb_b { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&hdmi_receiver { ++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ hdmirx { ++ hdmirx_hpd: hdmirx-5v-detection { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_rgb_b: led-rgb-b { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie2 { ++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&usb_host2_xhci { ++ status = "okay"; ++}; ++ ++&vcc3v3_pcie2x1l0 { ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_vcc3v3_en>; ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.12/003-15-v6.17-arm64-dts-rockchip-add-ROCK-5T-device-tree.patch b/target/linux/rockchip/patches-6.12/003-15-v6.17-arm64-dts-rockchip-add-ROCK-5T-device-tree.patch new file mode 100644 index 0000000000..6a7a9e2cff --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-15-v6.17-arm64-dts-rockchip-add-ROCK-5T-device-tree.patch @@ -0,0 +1,134 @@ +From 0ea651de9b79a17cbe410a69399877805c136b76 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 20 May 2025 20:50:11 +0200 +Subject: arm64: dts: rockchip: add ROCK 5T device tree + +The RADXA ROCK 5T is a single board computer quite similar to the ROCK +5B+, except it has one more PCIe-to-Ethernet controller (at the expense +of a USB3 port) and a barrel jack for power input instead. Some pins are +shuffled around as well. + +Add a device tree for it. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-4-1f1971850a20@collabora.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -143,6 +143,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5t.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts +@@ -0,0 +1,105 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3588-rock-5b-5bp-5t.dtsi" ++ ++/ { ++ model = "Radxa ROCK 5T"; ++ compatible = "radxa,rock-5t", "rockchip,rk3588"; ++ ++ analog-sound { ++ compatible = "audio-graph-card"; ++ label = "rk3588-es8316"; ++ ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ ++ dais = <&i2s0_8ch_p0>; ++ hp-det-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_b>; ++ ++ led_rgb_b { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vcc3v3_pcie2x1l1: regulator-vcc3v3-pcie2x1l2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l1"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++}; ++ ++&hdmi_receiver { ++ hpd-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie2x1l1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_1_rst>; ++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l1>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ hdmirx { ++ hdmirx_hpd: hdmirx-5v-detection { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_rgb_b: led-rgb-b { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie2 { ++ pcie2_1_rst: pcie2-1-rst { ++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { ++ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&vcc3v3_pcie2x1l0 { ++ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_vcc3v3_en>; ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.12/003-16-v6.17-arm64-dts-rockchip-fix-USB-on-RADXA-ROCK-5T.patch b/target/linux/rockchip/patches-6.12/003-16-v6.17-arm64-dts-rockchip-fix-USB-on-RADXA-ROCK-5T.patch new file mode 100644 index 0000000000..cb40a82c55 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-16-v6.17-arm64-dts-rockchip-fix-USB-on-RADXA-ROCK-5T.patch @@ -0,0 +1,40 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Mon, 25 Aug 2025 09:27:08 +0200 +Subject: arm64: dts: rockchip: fix USB on RADXA ROCK 5T + +The RADXA ROCK 5T board uses the same GPIO pin for controlling the USB +host port regulator. This control pin was mistakenly left out of the +ROCK 5T device tree. + +Reported-by: FUKAUMI Naoki +Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38609886; +Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree") +Signed-off-by: Nicolas Frattaroli + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts +@@ -95,6 +95,12 @@ + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + + &vcc3v3_pcie2x1l0 { +@@ -103,3 +109,10 @@ + pinctrl-0 = <&pcie2_0_vcc3v3_en>; + status = "okay"; + }; ++ ++&vcc5v0_host { ++ enable-active-high; ++ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++}; diff --git a/target/linux/rockchip/patches-6.12/003-17-v6.17-arm64-dts-rockchip-fix-second-M.2-slot-on-ROCK-5T.patch b/target/linux/rockchip/patches-6.12/003-17-v6.17-arm64-dts-rockchip-fix-second-M.2-slot-on-ROCK-5T.patch new file mode 100644 index 0000000000..23e57509c5 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/003-17-v6.17-arm64-dts-rockchip-fix-second-M.2-slot-on-ROCK-5T.patch @@ -0,0 +1,56 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 26 Aug 2025 10:08:36 +0200 +Subject: arm64: dts: rockchip: fix second M.2 slot on ROCK 5T + +The Radxa ROCK 5T has two M.2 slots, much like the Radxa Rock 5B+. As it +stands, the board won't be able to use PCIe3 if the second M.2 slot is +in use. + +Fix this by adding the necessary node enablement and data-lanes property +to the ROCK 5T device tree, mirroring what's in the ROCK 5B+ device +tree. + +Reported-by: FUKAUMI Naoki +Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38610630; +Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree") +Signed-off-by: Nicolas Frattaroli + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts +@@ -68,6 +68,22 @@ + status = "okay"; + }; + ++&pcie30phy { ++ data-lanes = <1 1 2 2>; ++}; ++ ++&pcie3x2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3x2_rst>; ++ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ num-lanes = <2>; ++}; ++ + &pinctrl { + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { +@@ -90,6 +106,12 @@ + }; + }; + ++ pcie3 { ++ pcie3x2_rst: pcie3x2-rst { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + sound { + hp_detect: hp-detect { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.12/004-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch b/target/linux/rockchip/patches-6.12/004-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch new file mode 100644 index 0000000000..a9e5994234 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/004-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch @@ -0,0 +1,24 @@ +From 3ca743f8a5b568dc5e5d5f1bab0298a4a43c2360 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Fri, 27 Sep 2024 14:42:22 +0200 +Subject: arm64: dts: rockchip: Switch to hp-det-gpios + +Replace the deprecated "hp-det-gpio" property by "hp-det-gpios" in Audio +Graph Card and Realtek RT5651 Audio Codec device nodes. + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/717e7c9527139c3a3e5246dd367a3ad98c5c81b6.1727438777.git.geert+renesas@glider.be +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +@@ -46,7 +46,7 @@ + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + dais = <&i2s0_8ch_p0>; +- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; ++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + routing = "MIC2", "Mic Jack", diff --git a/target/linux/rockchip/patches-6.12/004-01-v6.13-arm64-dts-rockchip-add-Radxa-ROCK-5C.patch b/target/linux/rockchip/patches-6.12/004-01-v6.13-arm64-dts-rockchip-add-Radxa-ROCK-5C.patch deleted file mode 100644 index d021e5d724..0000000000 --- a/target/linux/rockchip/patches-6.12/004-01-v6.13-arm64-dts-rockchip-add-Radxa-ROCK-5C.patch +++ /dev/null @@ -1,957 +0,0 @@ -From 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Mon, 21 Oct 2024 09:05:47 +0000 -Subject: arm64: dts: rockchip: add Radxa ROCK 5C - -Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip -RK3588S2 chip: - -- Rockchip RK3588S2 -- Quad A76 and Quad A55 CPU -- 6 TOPS NPU -- up to 32GB LPDDR4x RAM -- eMMC / SPI flash connector -- Micro SD Card slot -- Gigabit ethernet port (supports PoE with add-on PoE HAT) -- WiFi6 / BT5.4 -- 1x USB 3.0 Type-A HOST port -- 1x USB 3.0 Type-A OTG port -- 2x USB 2.0 Type-A HOST port -- 1x USB Type-C 5V power port - -[1] https://radxa.com/products/rock5/5c - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20241021090548.1052-2-naoki@radxa.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -156,3 +156,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-n - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -@@ -0,0 +1,920 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include "rk3588s.dtsi" -+ -+/ { -+ model = "Radxa ROCK 5C"; -+ compatible = "radxa,rock-5c", "rockchip,rk3588s"; -+ -+ aliases { -+ ethernet0 = &gmac1; -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ analog-sound { -+ compatible = "audio-graph-card"; -+ label = "rk3588-es8316"; -+ dais = <&i2s0_8ch_p0>; -+ routing = "MIC2", "Mic Jack", -+ "Headphones", "HPOL", -+ "Headphones", "HPOR"; -+ widgets = "Microphone", "Mic Jack", -+ "Headphone", "Headphones"; -+ }; -+ -+ hdmi0-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi0_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_pins>; -+ -+ led-0 { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_POWER; -+ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-1 { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_HEARTBEAT; -+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ fan { -+ compatible = "pwm-fan"; -+ #cooling-cells = <2>; -+ cooling-levels = <0 64 128 192 255>; -+ fan-supply = <&vcc_5v0>; -+ pwms = <&pwm3 0 10000 0>; -+ }; -+ -+ pcie2x1l2_3v3: regulator-pcie2x1l2-3v3 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pow_en>; -+ regulator-name = "pcie2x1l2_3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vcc5v_dcin: regulator-vcc5v-dcin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc5v0_usb_host: regulator-vcc5v0-usb-host { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_host_pwren_h>; -+ regulator-name = "vcc5v0_usb_host"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_otg_pwren_h>; -+ regulator-name = "vcc5v0_usb_otg0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_1v1_nldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vcc_3v3_pmu: regulator-vcc-3v3-pmu { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcc_3v3_s0: regulator-vcc-3v3-s0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_1v8_s0>; -+ }; -+ -+ vcc_5v0: regulator-vcc-5v0 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_5v0_pwren_h>; -+ regulator-name = "vcc_5v0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vcc_sysin: regulator-vcc-sysin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sysin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v_dcin>; -+ }; -+ -+ vcca: regulator-vcca { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vdd_3v3: regulator-vdd-3v3 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_wifi_pwr>; -+ regulator-name = "vdd_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&gmac1 { -+ phy-handle = <&rgmii_phy1>; -+ phy-mode = "rgmii-id"; -+ phy-supply = <&vcc_3v3_s0>; -+ pinctrl-0 = <&gmac1_miim -+ &gmac1_tx_bus2 -+ &gmac1_rx_bus2 -+ &gmac1_rgmii_clk -+ &gmac1_rgmii_bus -+ &gmac1_clkinout>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ -+&hdmi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmim0_tx0_cec -+ &hdmim1_tx0_hpd -+ &hdmim0_tx0_scl -+ &hdmim0_tx0_sda>; -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi0_con_in>; -+ }; -+}; -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ eeprom@50 { -+ compatible = "belling,bl24c16a", "atmel,24c16"; -+ reg = <0x50>; -+ pagesize = <16>; -+ vcc-supply = <&vcc_3v3_pmu>; -+ }; -+}; -+ -+&i2c2 { -+ status = "okay"; -+ -+ vdd_npu_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_npu_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c5m2_xfer>; -+ status = "okay"; -+ -+ rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "rtcic_32kout"; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtc_int_l>; -+ }; -+}; -+ -+&i2c7 { -+ status = "okay"; -+ -+ audio-codec@11 { -+ compatible = "everest,es8316"; -+ reg = <0x11>; -+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -+ assigned-clock-rates = <12288000>; -+ clocks = <&cru I2S0_8CH_MCLKOUT>; -+ clock-names = "mclk"; -+ #sound-dai-cells = <0>; -+ -+ port { -+ es8316_p0_0: endpoint { -+ remote-endpoint = <&i2s0_8ch_p0_0>; -+ }; -+ }; -+ }; -+}; -+ -+&i2s0_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_lrck -+ &i2s0_mclk -+ &i2s0_sclk -+ &i2s0_sdi0 -+ &i2s0_sdo0>; -+ status = "okay"; -+ -+ i2s0_8ch_p0: port { -+ i2s0_8ch_p0_0: endpoint { -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ remote-endpoint = <&es8316_p0_0>; -+ }; -+ }; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c916"; -+ reg = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1_rstn>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <100000>; -+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pcie2x1l2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie20x1_2_perstn_m0>; -+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&pcie2x1l2_3v3>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ leds { -+ led_pins: led-pins { -+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, -+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ mdio { -+ gmac1_rstn: gmac1-rstn { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 { -+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pow_en: pow-en { -+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ rtc { -+ rtc_int_l: rtc-int-l { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ usb_host_pwren_h: usb-host-pwren-h { -+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ usb_otg_pwren_h: usb-otg-pwren-h { -+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ usb_wifi_pwr: usb-wifi-pwr { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc_5v0_pwren_h: vcc-5v0-pwren-h { -+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pwm3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm3m1_pins>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ no-sdio; -+ no-sd; -+ non-removable; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ no-sdio; -+ no-mmc; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_s3>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim0_pins>; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <104000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ -+&spi2 { -+ status = "okay"; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ num-cs = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ reg = <0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ spi-max-frequency = <1000000>; -+ system-power-controller; -+ -+ vcc1-supply = <&vcc_sysin>; -+ vcc2-supply = <&vcc_sysin>; -+ vcc3-supply = <&vcc_sysin>; -+ vcc4-supply = <&vcc_sysin>; -+ vcc5-supply = <&vcc_sysin>; -+ vcc6-supply = <&vcc_sysin>; -+ vcc7-supply = <&vcc_sysin>; -+ vcc8-supply = <&vcc_sysin>; -+ vcc9-supply = <&vcc_sysin>; -+ vcc10-supply = <&vcc_sysin>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc_sysin>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcca>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: dcdc-reg1 { -+ regulator-name = "vdd_gpu_s0"; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-enable-ramp-delay = <400>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: dcdc-reg2 { -+ regulator-name = "vdd_cpu_lit_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_logic_s0: dcdc-reg3 { -+ regulator-name = "vdd_logic_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: dcdc-reg4 { -+ regulator-name = "vdd_vdenc_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-name = "vdd_ddr_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-name = "vdd2_ddr_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-name = "vdd_2v0_pldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-name = "vcc_3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-name = "vddq_ddr_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_pmu_ddr_s3: dcdc-reg10 { -+ regulator-name = "vcc1v8_pmu_ddr_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg1 { -+ regulator-name = "vcc_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca_1v8_s0: pldo-reg2 { -+ regulator-name = "vcca_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdda_1v2_s0: pldo-reg3 { -+ regulator-name = "vdda_1v2_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca_3v3_s0: pldo-reg4 { -+ regulator-name = "vcca_3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-name = "vccio_sd_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-name = "pldo6_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-name = "vdd_0v75_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdda_ddr_pll_s0: nldo-reg2 { -+ regulator-name = "vdda_ddr_pll_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdda_0v75_s0: nldo-reg3 { -+ regulator-name = "vdda_0v75_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v85_s0: nldo-reg4 { -+ regulator-name = "vdda_0v85_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-name = "vdd_0v75_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ phy-supply = <&vcc5v0_usb_otg0>; -+ status = "okay"; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+}; -+ -+&u2phy2_host { -+ /* connected to USB hub, which is powered by vcc_5v0 */ -+ phy-supply = <&vcc_5v0>; -+ status = "okay"; -+}; -+ -+&u2phy3 { -+ status = "okay"; -+}; -+ -+&u2phy3_host { -+ phy-supply = <&vcc5v0_usb_host>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&usbdp_phy0 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb_host2_xhci { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.12/004-02-v6.13-arm64-dts-rockchip-fix-the-pcie-refclock-oscillator-.patch b/target/linux/rockchip/patches-6.12/004-02-v6.13-arm64-dts-rockchip-fix-the-pcie-refclock-oscillator-.patch new file mode 100644 index 0000000000..fcdd0eaef8 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/004-02-v6.13-arm64-dts-rockchip-fix-the-pcie-refclock-oscillator-.patch @@ -0,0 +1,94 @@ +From e684f02492f99d6f6f037a35a613607339cf8e8f Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Fri, 6 Sep 2024 10:25:11 +0200 +Subject: arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX + +The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its +SATA controller with 2 lanes each. The supply for the refclk oscillator is +the same that supplies the M.2 slot, but the SATA controller port is +supplied by a different rail. + +This leads to the effect that if the PCIe30x4 controller for the M.2 +probes first, everything works normally. But if the PCIe30x2 controller +that is connected to the SATA controller probes first, it will hang on +the first DBI read as nothing will have enabled the refclock before. + +Fix this by describing the clock generator with its supplies so that +both controllers can reference it as needed. + +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20240906082511.2963890-6-heiko@sntech.de + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +@@ -72,6 +72,15 @@ + }; + }; + ++ /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ ++ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { ++ compatible = "gated-fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <100000000>; ++ clock-output-names = "pcie30_refclk"; ++ vdd-supply = <&vcc3v3_pi6c_05>; ++ }; ++ + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; +@@ -146,13 +155,14 @@ + vin-supply = <&vcc_3v3_s3>; + }; + +- vcc3v3_mkey: regulator-vcc3v3-mkey { ++ /* The PCIE30x4_PWREN_H controls two regulators */ ++ vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_pwren_h>; +- regulator-name = "vcc3v3_mkey"; ++ regulator-name = "vcc3v3_pi6c_05"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; +@@ -513,6 +523,18 @@ + + /* ASMedia ASM1164 Sata controller */ + &pcie3x2 { ++ /* ++ * The board has a "pcie_refclk" oscillator that needs enabling, ++ * so add it to the list of clocks. ++ */ ++ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, ++ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, ++ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>, ++ <&pcie30_port1_refclk>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", ++ "aux", "pipe", ++ "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; +@@ -522,6 +544,18 @@ + + /* M.2 M.key */ + &pcie3x4 { ++ /* ++ * The board has a "pcie_refclk" oscillator that needs enabling, ++ * so add it to the list of clocks. ++ */ ++ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, ++ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, ++ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, ++ <&pcie30_port0_refclk>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", ++ "aux", "pipe", ++ "ref"; + num-lanes = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_perstn_m1_l>; diff --git a/target/linux/rockchip/patches-6.12/004-02-v6.15-arm64-dts-rockchip-Add-finer-grained-PWM-states-for-.patch b/target/linux/rockchip/patches-6.12/004-02-v6.15-arm64-dts-rockchip-Add-finer-grained-PWM-states-for-.patch deleted file mode 100644 index 802ab6b581..0000000000 --- a/target/linux/rockchip/patches-6.12/004-02-v6.15-arm64-dts-rockchip-Add-finer-grained-PWM-states-for-.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 6ed35e6ff556626734c400fff5a636b38b91fe19 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 20 Jan 2025 23:22:46 +0400 -Subject: arm64: dts: rockchip: Add finer-grained PWM states for the fan on - Rock 5C - -Radxa Heatsink 6540B, which is the official cooling accessory for the -Rock 5C board, includes a small 5V fan, which in my testing spins up -reliably at a PWM setting of 24 (out of 255). It is also quite loud -at the current minimum setting of 64, and noticeably less so at 24. - -Introduce two intermediate PWM states at the lower end of the fan's -operating range to enable better balance between noise and cooling. - -Note further that, in my testing, having the fan run at 44 is enough -to keep the system from thermal throttling with sustained 100% load -on its 8 CPU cores (in 22C ambient temperature and no case) - -Signed-off-by: Alexey Charkov -Acked-by: Dragan Simic -Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-1-5fb8446c981b@gmail.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -@@ -71,7 +71,7 @@ - fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; -- cooling-levels = <0 64 128 192 255>; -+ cooling-levels = <0 24 44 64 128 192 255>; - fan-supply = <&vcc_5v0>; - pwms = <&pwm3 0 10000 0>; - }; diff --git a/target/linux/rockchip/patches-6.12/004-03-v6.14-arm64-dts-rockchip-slow-down-emmc-freq-for-rock-5-it.patch b/target/linux/rockchip/patches-6.12/004-03-v6.14-arm64-dts-rockchip-slow-down-emmc-freq-for-rock-5-it.patch new file mode 100644 index 0000000000..31577a490b --- /dev/null +++ b/target/linux/rockchip/patches-6.12/004-03-v6.14-arm64-dts-rockchip-slow-down-emmc-freq-for-rock-5-it.patch @@ -0,0 +1,35 @@ +From b36402e4a0772d1b3da06a4f5fbd1cfe4d6f1cc0 Mon Sep 17 00:00:00 2001 +From: Jianfeng Liu +Date: Fri, 28 Feb 2025 22:33:08 +0800 +Subject: arm64: dts: rockchip: slow down emmc freq for rock 5 itx + +The current max-frequency 200000000 of emmc is not stable. When doing +heavy write there will be I/O Error. After setting max-frequency to +150000000 the emmc is stable under write. + +Also remove property mmc-hs200-1_8v because we are already running at +HS400 mode. + +Tested with fio command: +fio -filename=./test_randread -direct=1 -iodepth 1 -thread \ +-rw=randwrite -ioengine=psync -bs=16k -size=1G -numjobs=10 \ +-runtime=600 -group_reporting -name=mytest + +Signed-off-by: Jianfeng Liu +Link: https://lore.kernel.org/r/20250228143341.70244-1-liujianfeng1994@gmail.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +@@ -690,10 +690,9 @@ + + &sdhci { + bus-width = <8>; +- max-frequency = <200000000>; ++ max-frequency = <150000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +- mmc-hs200-1_8v; + no-sdio; + no-sd; + non-removable; diff --git a/target/linux/rockchip/patches-6.12/004-03-v6.15-arm64-dts-rockchip-Enable-automatic-fan-control-on-R.patch b/target/linux/rockchip/patches-6.12/004-03-v6.15-arm64-dts-rockchip-Enable-automatic-fan-control-on-R.patch deleted file mode 100644 index df9f58d25e..0000000000 --- a/target/linux/rockchip/patches-6.12/004-03-v6.15-arm64-dts-rockchip-Enable-automatic-fan-control-on-R.patch +++ /dev/null @@ -1,62 +0,0 @@ -From cd5681e63fb9887bd05d4ef59151d6a6b39c9d33 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 20 Jan 2025 23:22:47 +0400 -Subject: arm64: dts: rockchip: Enable automatic fan control on Radxa Rock 5C - -Add the necessary cooling map to enable the kernel's thermal subsystem -to manage the fan speed automatically depending on the overall SoC -package temperature on Radxa Rock 5C - -Signed-off-by: Alexey Charkov -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-2-5fb8446c981b@gmail.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -@@ -68,7 +68,7 @@ - }; - }; - -- fan { -+ fan: fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-levels = <0 24 44 64 128 192 255>; -@@ -417,6 +417,36 @@ - }; - }; - -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ package_fan1: package-fan1 { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&package_fan0>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map1 { -+ trip = <&package_fan1>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ - &pcie2x1l2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie20x1_2_perstn_m0>; diff --git a/target/linux/rockchip/patches-6.12/004-04-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch b/target/linux/rockchip/patches-6.12/004-04-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch deleted file mode 100644 index 97fa8ef158..0000000000 --- a/target/linux/rockchip/patches-6.12/004-04-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001 -From: Damon Ding -Date: Thu, 6 Feb 2025 11:03:30 +0800 -Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588 - -The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP -and eDP Link. Therefore, it is better to name it hdptxphy0 other than -hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes. - -Signed-off-by: Damon Ding -Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com -[added armsom-sige7, where hdmi-support was added recently and also - the hdptxphy0-as-dclk source I just added] -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -@@ -278,7 +278,7 @@ - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - diff --git a/target/linux/rockchip/patches-6.12/004-04-v6.15-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch b/target/linux/rockchip/patches-6.12/004-04-v6.15-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch new file mode 100644 index 0000000000..e83132ddb2 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/004-04-v6.15-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch @@ -0,0 +1,87 @@ +From 3eac9319af62dbc56d1f06fcb240e4a092fa5b2f Mon Sep 17 00:00:00 2001 +From: Jianfeng Liu +Date: Tue, 25 Feb 2025 11:08:48 +0800 +Subject: arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX + +Enable the HDMI port next to ethernet port. + +Signed-off-by: Jianfeng Liu +Link: https://lore.kernel.org/r/20250225030904.2813023-1-liujianfeng1994@gmail.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include "dt-bindings/usb/pd.h" + #include "rk3588.dtsi" + +@@ -72,6 +73,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; +@@ -261,6 +273,28 @@ + status = "okay"; + }; + ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +@@ -1208,3 +1242,18 @@ + rockchip,dp-lane-mux = <2 3>; + status = "okay"; + }; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.12/004-05-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/004-05-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch new file mode 100644 index 0000000000..8d2e86dfac --- /dev/null +++ b/target/linux/rockchip/patches-6.12/004-05-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch @@ -0,0 +1,48 @@ +From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Feb 2025 19:58:11 +0100 +Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for + RK3588 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enabling the GPU power domain requires that the GPU regulator is +enabled. The regulator is enabled at boot time, but gets disabled +automatically when there are no users. + +This means the system might run into a failure state hanging the +whole system for the following use cases: + + * if the GPU driver is being probed late (e.g. build as a + module and firmware is not in initramfs), the regulator + might already have been disabled. In that case the power + domain is enabled before the regulator. + * unbinding the GPU driver will disable the PM domain and + the regulator. When the driver is bound again, the PM + domain will be enabled before the regulator and error + appears. + +Avoid this by adding an explicit regulator dependency to the +power domain. + +Tested-by: Heiko Stuebner +Reported-by: Adrián Martínez Larumbe +Tested-by: Adrian Larumbe # On Rock 5B +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +@@ -598,6 +598,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + rtc_int: rtc-int { diff --git a/target/linux/rockchip/patches-6.12/004-05-v6.15-arm64-dts-rockchip-switch-Rock-5C-to-PMIC-based-TSHU.patch b/target/linux/rockchip/patches-6.12/004-05-v6.15-arm64-dts-rockchip-switch-Rock-5C-to-PMIC-based-TSHU.patch deleted file mode 100644 index dbc5caf82d..0000000000 --- a/target/linux/rockchip/patches-6.12/004-05-v6.15-arm64-dts-rockchip-switch-Rock-5C-to-PMIC-based-TSHU.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 52cababc9c1914ebf50929bfb9a67c8f74cd60ab Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Tue, 4 Feb 2025 13:02:28 +0400 -Subject: arm64: dts: rockchip: switch Rock 5C to PMIC-based TSHUT reset - -Radxa Rock 5C supports both CRU-based (default) and PMIC-based reset -upon thermal runaway conditions. The former resets the SoC by internally -poking the CRU from TSADC, while the latter power-cycles the whole board -by pulling the PMIC reset line low in case of uncontrolled overheating. - -Switch to a PMIC-based reset, as the more 'thorough' of the two. - -Tested by temporarily setting rockchip,hw-tshut-temp to 65C to simulate -overheating - this causes the board to reset when any of the on-chip -temperature sensors surpasses the tshut temperature. - -Requires Alexander's patch [1] fixing TSADC pinctrl assignment - -[1] https://lore.kernel.org/r/20250130053849.4902-1-eagle.alexander923@gmail.com - -Signed-off-by: Alexey Charkov -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20250204-rock-5c-tshut-v1-1-33301e4eef64@gmail.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -@@ -873,6 +873,8 @@ - }; - - &tsadc { -+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; - }; - diff --git a/target/linux/rockchip/patches-6.12/004-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/004-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch deleted file mode 100644 index 140ab58d12..0000000000 --- a/target/linux/rockchip/patches-6.12/004-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch +++ /dev/null @@ -1,48 +0,0 @@ -From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 20 Feb 2025 19:58:11 +0100 -Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for - RK3588 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enabling the GPU power domain requires that the GPU regulator is -enabled. The regulator is enabled at boot time, but gets disabled -automatically when there are no users. - -This means the system might run into a failure state hanging the -whole system for the following use cases: - - * if the GPU driver is being probed late (e.g. build as a - module and firmware is not in initramfs), the regulator - might already have been disabled. In that case the power - domain is enabled before the regulator. - * unbinding the GPU driver will disable the PM domain and - the regulator. When the driver is bound again, the PM - domain will be enabled before the regulator and error - appears. - -Avoid this by adding an explicit regulator dependency to the -power domain. - -Tested-by: Heiko Stuebner -Reported-by: Adrián Martínez Larumbe -Tested-by: Adrian Larumbe # On Rock 5B -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -@@ -455,6 +455,10 @@ - status = "okay"; - }; - -+&pd_gpu { -+ domain-supply = <&vdd_gpu_s0>; -+}; -+ - &pinctrl { - leds { - led_pins: led-pins { diff --git a/target/linux/rockchip/patches-6.12/005-01-v6.13-arm64-dts-rockchip-add-Radxa-ROCK-5C.patch b/target/linux/rockchip/patches-6.12/005-01-v6.13-arm64-dts-rockchip-add-Radxa-ROCK-5C.patch new file mode 100644 index 0000000000..d021e5d724 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/005-01-v6.13-arm64-dts-rockchip-add-Radxa-ROCK-5C.patch @@ -0,0 +1,957 @@ +From 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Mon, 21 Oct 2024 09:05:47 +0000 +Subject: arm64: dts: rockchip: add Radxa ROCK 5C + +Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip +RK3588S2 chip: + +- Rockchip RK3588S2 +- Quad A76 and Quad A55 CPU +- 6 TOPS NPU +- up to 32GB LPDDR4x RAM +- eMMC / SPI flash connector +- Micro SD Card slot +- Gigabit ethernet port (supports PoE with add-on PoE HAT) +- WiFi6 / BT5.4 +- 1x USB 3.0 Type-A HOST port +- 1x USB 3.0 Type-A OTG port +- 2x USB 2.0 Type-A HOST port +- 1x USB Type-C 5V power port + +[1] https://radxa.com/products/rock5/5c + +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20241021090548.1052-2-naoki@radxa.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -156,3 +156,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-n + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +@@ -0,0 +1,920 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include "rk3588s.dtsi" ++ ++/ { ++ model = "Radxa ROCK 5C"; ++ compatible = "radxa,rock-5c", "rockchip,rk3588s"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ analog-sound { ++ compatible = "audio-graph-card"; ++ label = "rk3588-es8316"; ++ dais = <&i2s0_8ch_p0>; ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ }; ++ ++ hdmi0-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi0_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_pins>; ++ ++ led-0 { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_POWER; ++ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-1 { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_HEARTBEAT; ++ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ fan { ++ compatible = "pwm-fan"; ++ #cooling-cells = <2>; ++ cooling-levels = <0 64 128 192 255>; ++ fan-supply = <&vcc_5v0>; ++ pwms = <&pwm3 0 10000 0>; ++ }; ++ ++ pcie2x1l2_3v3: regulator-pcie2x1l2-3v3 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pow_en>; ++ regulator-name = "pcie2x1l2_3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vcc5v_dcin: regulator-vcc5v-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc5v0_usb_host: regulator-vcc5v0-usb-host { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_host_pwren_h>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_otg_pwren_h>; ++ regulator-name = "vcc5v0_usb_otg0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vcc_3v3_pmu: regulator-vcc-3v3-pmu { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc_3v3_s0: regulator-vcc-3v3-s0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_1v8_s0>; ++ }; ++ ++ vcc_5v0: regulator-vcc-5v0 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_5v0_pwren_h>; ++ regulator-name = "vcc_5v0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vcc_sysin: regulator-vcc-sysin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sysin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v_dcin>; ++ }; ++ ++ vcca: regulator-vcca { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vdd_3v3: regulator-vdd-3v3 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_wifi_pwr>; ++ regulator-name = "vdd_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gmac1 { ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <&vcc_3v3_s0>; ++ pinctrl-0 = <&gmac1_miim ++ &gmac1_tx_bus2 ++ &gmac1_rx_bus2 ++ &gmac1_rgmii_clk ++ &gmac1_rgmii_bus ++ &gmac1_clkinout>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ ++&hdmi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim0_tx0_cec ++ &hdmim1_tx0_hpd ++ &hdmim0_tx0_scl ++ &hdmim0_tx0_sda>; ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi0_con_in>; ++ }; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sysin>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sysin>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ eeprom@50 { ++ compatible = "belling,bl24c16a", "atmel,24c16"; ++ reg = <0x50>; ++ pagesize = <16>; ++ vcc-supply = <&vcc_3v3_pmu>; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ vdd_npu_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_npu_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sysin>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c5m2_xfer>; ++ status = "okay"; ++ ++ rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_int_l>; ++ }; ++}; ++ ++&i2c7 { ++ status = "okay"; ++ ++ audio-codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_8ch_p0_0>; ++ }; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++ ++ i2s0_8ch_p0: port { ++ i2s0_8ch_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-id001c.c916"; ++ reg = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1_rstn>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1l2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20x1_2_perstn_m0>; ++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&pcie2x1l2_3v3>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ leds { ++ led_pins: led-pins { ++ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, ++ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ mdio { ++ gmac1_rstn: gmac1-rstn { ++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 { ++ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pow_en: pow-en { ++ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ rtc { ++ rtc_int_l: rtc-int-l { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ usb_host_pwren_h: usb-host-pwren-h { ++ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ usb_otg_pwren_h: usb-otg-pwren-h { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ usb_wifi_pwr: usb-wifi-pwr { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc_5v0_pwren_h: vcc-5v0-pwren-h { ++ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm3m1_pins>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ no-sdio; ++ no-sd; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ no-sdio; ++ no-mmc; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&sfc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fspim0_pins>; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ num-cs = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ reg = <0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ spi-max-frequency = <1000000>; ++ system-power-controller; ++ ++ vcc1-supply = <&vcc_sysin>; ++ vcc2-supply = <&vcc_sysin>; ++ vcc3-supply = <&vcc_sysin>; ++ vcc4-supply = <&vcc_sysin>; ++ vcc5-supply = <&vcc_sysin>; ++ vcc6-supply = <&vcc_sysin>; ++ vcc7-supply = <&vcc_sysin>; ++ vcc8-supply = <&vcc_sysin>; ++ vcc9-supply = <&vcc_sysin>; ++ vcc10-supply = <&vcc_sysin>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc_sysin>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcca>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: dcdc-reg1 { ++ regulator-name = "vdd_gpu_s0"; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: dcdc-reg2 { ++ regulator-name = "vdd_cpu_lit_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_logic_s0: dcdc-reg3 { ++ regulator-name = "vdd_logic_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: dcdc-reg4 { ++ regulator-name = "vdd_vdenc_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-name = "vdd_ddr_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-name = "vdd2_ddr_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-name = "vdd_2v0_pldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-name = "vcc_3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-name = "vddq_ddr_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmu_ddr_s3: dcdc-reg10 { ++ regulator-name = "vcc1v8_pmu_ddr_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg1 { ++ regulator-name = "vcc_1v8_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca_1v8_s0: pldo-reg2 { ++ regulator-name = "vcca_1v8_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdda_1v2_s0: pldo-reg3 { ++ regulator-name = "vdda_1v2_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca_3v3_s0: pldo-reg4 { ++ regulator-name = "vcca_3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-name = "vccio_sd_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-name = "pldo6_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-name = "vdd_0v75_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdda_ddr_pll_s0: nldo-reg2 { ++ regulator-name = "vdda_ddr_pll_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdda_0v75_s0: nldo-reg3 { ++ regulator-name = "vdda_0v75_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v85_s0: nldo-reg4 { ++ regulator-name = "vdda_0v85_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-name = "vdd_0v75_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ phy-supply = <&vcc5v0_usb_otg0>; ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ /* connected to USB hub, which is powered by vcc_5v0 */ ++ phy-supply = <&vcc_5v0>; ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&usbdp_phy0 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host2_xhci { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.12/005-01-v6.14-arm64-dts-rockchip-Add-Radxa-E52C.patch b/target/linux/rockchip/patches-6.12/005-01-v6.14-arm64-dts-rockchip-Add-Radxa-E52C.patch deleted file mode 100644 index 5139b09f00..0000000000 --- a/target/linux/rockchip/patches-6.12/005-01-v6.14-arm64-dts-rockchip-Add-Radxa-E52C.patch +++ /dev/null @@ -1,780 +0,0 @@ -From 9be4171219b659a8f0fa0a7913af2c6ab20c714e Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Thu, 26 Dec 2024 02:46:30 +0000 -Subject: arm64: dts: rockchip: Add Radxa E52C - -Radxa E52C[1] is a compact network computer based on the Rockchip -RK3582 SoC: - -- Dual Cortex-A76 and quad Cortex-A55 CPU -- 5TOPS NPU -- 2GB/4GB/8GB LPDDR4 RAM -- 16GB/32GB/64GB on-board eMMC -- microSD card slot -- USB 3.0 Type-A HOST port -- USB Type-C debug port -- USB Type-C power port (5V only) -- 2x 2.5GbE ports - -[1] https://radxa.com/products/network-computer/e52c - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20241226024630.13702-3-naoki@radxa.com -Signed-off-by: Heiko Stuebner - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-genbook.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts -@@ -0,0 +1,743 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include -+#include "rk3588s.dtsi" -+ -+/ { -+ model = "Radxa E52C"; -+ compatible = "radxa,e52c", "rockchip,rk3582", "rockchip,rk3588s"; -+ -+ aliases { -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ keys-0 { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 0>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <18000>; -+ poll-interval = <100>; -+ -+ button-0 { -+ label = "Maskrom"; -+ linux,code = ; -+ press-threshold-microvolt = <0>; -+ }; -+ }; -+ -+ keys-1 { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&btn_0>; -+ -+ button-1 { -+ label = "User"; -+ gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ leds-0 { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_0>; -+ -+ led-0 { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ leds-1 { -+ compatible = "pwm-leds"; -+ -+ led-1 { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_LAN; -+ linux,default-trigger = "netdev"; -+ pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>; -+ max-brightness = <255>; -+ }; -+ -+ led-2 { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_WAN; -+ linux,default-trigger = "netdev"; -+ pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>; -+ max-brightness = <255>; -+ }; -+ }; -+ -+ vcc_1v1_nldo_s3: regulator-1v1 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_1v1_nldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vcc_3v3_pmu: regulator-3v3-0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcc_3v3_s0: regulator-3v3-1 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcca: regulator-4v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vcc5v0_usb_otg0: regulator-5v0-0 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_otg_pwren_h>; -+ regulator-name = "vcc5v0_usb_otg0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vcc_5v0: regulator-5v0-1 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_5v0_pwren_h>; -+ regulator-name = "vcc_5v0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_sysin>; -+ }; -+ -+ vcc_sysin: regulator-5v0-2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sysin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+/* -+ * In the Rockchip RK3582 SoC, some CPU cores end up disabled -+ * and unused because they're marked in the efuses as defective. -+ * The disabling in the DT is performed by the boot loader. -+ */ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ eeprom@50 { -+ compatible = "belling,bl24c16a", "atmel,24c16"; -+ reg = <0x50>; -+ pagesize = <16>; -+ vcc-supply = <&vcc_3v3_pmu>; -+ }; -+}; -+ -+&i2c2 { -+ status = "okay"; -+ -+ vdd_npu_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_npu_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c5m2_xfer>; -+ status = "okay"; -+ -+ rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "rtcic_32kout"; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtc_int_l>; -+ wakeup-source; -+ }; -+}; -+ -+&pcie2x1l1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie20x1_1_perstn_m1>; -+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc_3v3_s3>; -+ status = "okay"; -+}; -+ -+&pcie2x1l2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie20x1_2_perstn_m0>; -+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc_3v3_s3>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ keys { -+ btn_0: button-0 { -+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ led_0: led-0 { -+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie20x1_1_perstn_m1: pcie-1 { -+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie20x1_2_perstn_m0: pcie-2 { -+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ regulators { -+ vcc_5v0_pwren_h: regulator-5v0-1 { -+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ rtc { -+ rtc_int_l: rtc-0 { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ usb_otg_pwren_h: regulator-5v0-0 { -+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pwm11 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm11m1_pins>; -+ status = "okay"; -+}; -+ -+&pwm14 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm14m1_pins>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ no-sd; -+ no-sdio; -+ non-removable; -+ vmmc-supply = <&vcc_3v3_s0>; -+ vqmmc-supply = <&vcc_1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ no-sdio; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_s3>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&spi2 { -+ status = "okay"; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ num-cs = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ reg = <0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ spi-max-frequency = <1000000>; -+ system-power-controller; -+ -+ vcc1-supply = <&vcc_sysin>; -+ vcc2-supply = <&vcc_sysin>; -+ vcc3-supply = <&vcc_sysin>; -+ vcc4-supply = <&vcc_sysin>; -+ vcc5-supply = <&vcc_sysin>; -+ vcc6-supply = <&vcc_sysin>; -+ vcc7-supply = <&vcc_sysin>; -+ vcc8-supply = <&vcc_sysin>; -+ vcc9-supply = <&vcc_sysin>; -+ vcc10-supply = <&vcc_sysin>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc_sysin>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcca>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: dcdc-reg1 { -+ regulator-name = "vdd_gpu_s0"; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-enable-ramp-delay = <400>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: dcdc-reg2 { -+ regulator-name = "vdd_cpu_lit_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_logic_s0: dcdc-reg3 { -+ regulator-name = "vdd_logic_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: dcdc-reg4 { -+ regulator-name = "vdd_vdenc_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-name = "vdd_ddr_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-name = "vdd2_ddr_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-name = "vcc_2v0_pldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-name = "vcc_3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-name = "vddq_ddr_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-name = "vcc_1v8_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg1 { -+ regulator-name = "vcc_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca_1v8_s0: pldo-reg2 { -+ regulator-name = "vcca_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdda_1v2_s0: pldo-reg3 { -+ regulator-name = "vdda_1v2_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca_3v3_s0: pldo-reg4 { -+ regulator-name = "vcca_3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-name = "vccio_sd_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-name = "pldo6_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-name = "vdd_0v75_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdda_ddr_pll_s0: nldo-reg2 { -+ regulator-name = "vdda_ddr_pll_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdda_0v75_s0: nldo-reg3 { -+ regulator-name = "vdda_0v75_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdda_0v85_s0: nldo-reg4 { -+ regulator-name = "vdda_0v85_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-name = "vdd_0v75_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ phy-supply = <&vcc5v0_usb_otg0>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdp_phy0 { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.12/005-02-v6.15-arm64-dts-rockchip-Add-finer-grained-PWM-states-for-.patch b/target/linux/rockchip/patches-6.12/005-02-v6.15-arm64-dts-rockchip-Add-finer-grained-PWM-states-for-.patch new file mode 100644 index 0000000000..802ab6b581 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/005-02-v6.15-arm64-dts-rockchip-Add-finer-grained-PWM-states-for-.patch @@ -0,0 +1,34 @@ +From 6ed35e6ff556626734c400fff5a636b38b91fe19 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 20 Jan 2025 23:22:46 +0400 +Subject: arm64: dts: rockchip: Add finer-grained PWM states for the fan on + Rock 5C + +Radxa Heatsink 6540B, which is the official cooling accessory for the +Rock 5C board, includes a small 5V fan, which in my testing spins up +reliably at a PWM setting of 24 (out of 255). It is also quite loud +at the current minimum setting of 64, and noticeably less so at 24. + +Introduce two intermediate PWM states at the lower end of the fan's +operating range to enable better balance between noise and cooling. + +Note further that, in my testing, having the fan run at 44 is enough +to keep the system from thermal throttling with sustained 100% load +on its 8 CPU cores (in 22C ambient temperature and no case) + +Signed-off-by: Alexey Charkov +Acked-by: Dragan Simic +Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-1-5fb8446c981b@gmail.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +@@ -71,7 +71,7 @@ + fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; +- cooling-levels = <0 64 128 192 255>; ++ cooling-levels = <0 24 44 64 128 192 255>; + fan-supply = <&vcc_5v0>; + pwms = <&pwm3 0 10000 0>; + }; diff --git a/target/linux/rockchip/patches-6.12/005-03-v6.15-arm64-dts-rockchip-Enable-automatic-fan-control-on-R.patch b/target/linux/rockchip/patches-6.12/005-03-v6.15-arm64-dts-rockchip-Enable-automatic-fan-control-on-R.patch new file mode 100644 index 0000000000..df9f58d25e --- /dev/null +++ b/target/linux/rockchip/patches-6.12/005-03-v6.15-arm64-dts-rockchip-Enable-automatic-fan-control-on-R.patch @@ -0,0 +1,62 @@ +From cd5681e63fb9887bd05d4ef59151d6a6b39c9d33 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 20 Jan 2025 23:22:47 +0400 +Subject: arm64: dts: rockchip: Enable automatic fan control on Radxa Rock 5C + +Add the necessary cooling map to enable the kernel's thermal subsystem +to manage the fan speed automatically depending on the overall SoC +package temperature on Radxa Rock 5C + +Signed-off-by: Alexey Charkov +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-2-5fb8446c981b@gmail.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +@@ -68,7 +68,7 @@ + }; + }; + +- fan { ++ fan: fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 24 44 64 128 192 255>; +@@ -417,6 +417,36 @@ + }; + }; + ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map1 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20x1_2_perstn_m0>; diff --git a/target/linux/rockchip/patches-6.12/005-04-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch b/target/linux/rockchip/patches-6.12/005-04-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch new file mode 100644 index 0000000000..97fa8ef158 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/005-04-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch @@ -0,0 +1,26 @@ +From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001 +From: Damon Ding +Date: Thu, 6 Feb 2025 11:03:30 +0800 +Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588 + +The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP +and eDP Link. Therefore, it is better to name it hdptxphy0 other than +hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes. + +Signed-off-by: Damon Ding +Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com +[added armsom-sige7, where hdmi-support was added recently and also + the hdptxphy0-as-dclk source I just added] +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +@@ -278,7 +278,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + diff --git a/target/linux/rockchip/patches-6.12/005-05-v6.15-arm64-dts-rockchip-switch-Rock-5C-to-PMIC-based-TSHU.patch b/target/linux/rockchip/patches-6.12/005-05-v6.15-arm64-dts-rockchip-switch-Rock-5C-to-PMIC-based-TSHU.patch new file mode 100644 index 0000000000..dbc5caf82d --- /dev/null +++ b/target/linux/rockchip/patches-6.12/005-05-v6.15-arm64-dts-rockchip-switch-Rock-5C-to-PMIC-based-TSHU.patch @@ -0,0 +1,36 @@ +From 52cababc9c1914ebf50929bfb9a67c8f74cd60ab Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Tue, 4 Feb 2025 13:02:28 +0400 +Subject: arm64: dts: rockchip: switch Rock 5C to PMIC-based TSHUT reset + +Radxa Rock 5C supports both CRU-based (default) and PMIC-based reset +upon thermal runaway conditions. The former resets the SoC by internally +poking the CRU from TSADC, while the latter power-cycles the whole board +by pulling the PMIC reset line low in case of uncontrolled overheating. + +Switch to a PMIC-based reset, as the more 'thorough' of the two. + +Tested by temporarily setting rockchip,hw-tshut-temp to 65C to simulate +overheating - this causes the board to reset when any of the on-chip +temperature sensors surpasses the tshut temperature. + +Requires Alexander's patch [1] fixing TSADC pinctrl assignment + +[1] https://lore.kernel.org/r/20250130053849.4902-1-eagle.alexander923@gmail.com + +Signed-off-by: Alexey Charkov +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20250204-rock-5c-tshut-v1-1-33301e4eef64@gmail.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +@@ -873,6 +873,8 @@ + }; + + &tsadc { ++ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; + }; + diff --git a/target/linux/rockchip/patches-6.12/005-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch b/target/linux/rockchip/patches-6.12/005-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch new file mode 100644 index 0000000000..140ab58d12 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/005-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch @@ -0,0 +1,48 @@ +From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Feb 2025 19:58:11 +0100 +Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for + RK3588 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enabling the GPU power domain requires that the GPU regulator is +enabled. The regulator is enabled at boot time, but gets disabled +automatically when there are no users. + +This means the system might run into a failure state hanging the +whole system for the following use cases: + + * if the GPU driver is being probed late (e.g. build as a + module and firmware is not in initramfs), the regulator + might already have been disabled. In that case the power + domain is enabled before the regulator. + * unbinding the GPU driver will disable the PM domain and + the regulator. When the driver is bound again, the PM + domain will be enabled before the regulator and error + appears. + +Avoid this by adding an explicit regulator dependency to the +power domain. + +Tested-by: Heiko Stuebner +Reported-by: Adrián Martínez Larumbe +Tested-by: Adrian Larumbe # On Rock 5B +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +@@ -455,6 +455,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + led_pins: led-pins { diff --git a/target/linux/rockchip/patches-6.12/006-01-v6.14-arm64-dts-rockchip-Add-Radxa-E52C.patch b/target/linux/rockchip/patches-6.12/006-01-v6.14-arm64-dts-rockchip-Add-Radxa-E52C.patch new file mode 100644 index 0000000000..5139b09f00 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/006-01-v6.14-arm64-dts-rockchip-Add-Radxa-E52C.patch @@ -0,0 +1,780 @@ +From 9be4171219b659a8f0fa0a7913af2c6ab20c714e Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Thu, 26 Dec 2024 02:46:30 +0000 +Subject: arm64: dts: rockchip: Add Radxa E52C + +Radxa E52C[1] is a compact network computer based on the Rockchip +RK3582 SoC: + +- Dual Cortex-A76 and quad Cortex-A55 CPU +- 5TOPS NPU +- 2GB/4GB/8GB LPDDR4 RAM +- 16GB/32GB/64GB on-board eMMC +- microSD card slot +- USB 3.0 Type-A HOST port +- USB Type-C debug port +- USB Type-C power port (5V only) +- 2x 2.5GbE ports + +[1] https://radxa.com/products/network-computer/e52c + +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20241226024630.13702-3-naoki@radxa.com +Signed-off-by: Heiko Stuebner + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-genbook.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts +@@ -0,0 +1,743 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include ++#include "rk3588s.dtsi" ++ ++/ { ++ model = "Radxa E52C"; ++ compatible = "radxa,e52c", "rockchip,rk3582", "rockchip,rk3588s"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ keys-0 { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 0>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <18000>; ++ poll-interval = <100>; ++ ++ button-0 { ++ label = "Maskrom"; ++ linux,code = ; ++ press-threshold-microvolt = <0>; ++ }; ++ }; ++ ++ keys-1 { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&btn_0>; ++ ++ button-1 { ++ label = "User"; ++ gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ leds-0 { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_0>; ++ ++ led-0 { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ leds-1 { ++ compatible = "pwm-leds"; ++ ++ led-1 { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_LAN; ++ linux,default-trigger = "netdev"; ++ pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>; ++ max-brightness = <255>; ++ }; ++ ++ led-2 { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_WAN; ++ linux,default-trigger = "netdev"; ++ pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>; ++ max-brightness = <255>; ++ }; ++ }; ++ ++ vcc_1v1_nldo_s3: regulator-1v1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vcc_3v3_pmu: regulator-3v3-0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc_3v3_s0: regulator-3v3-1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcca: regulator-4v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vcc5v0_usb_otg0: regulator-5v0-0 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_otg_pwren_h>; ++ regulator-name = "vcc5v0_usb_otg0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vcc_5v0: regulator-5v0-1 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_5v0_pwren_h>; ++ regulator-name = "vcc_5v0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_sysin>; ++ }; ++ ++ vcc_sysin: regulator-5v0-2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sysin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++/* ++ * In the Rockchip RK3582 SoC, some CPU cores end up disabled ++ * and unused because they're marked in the efuses as defective. ++ * The disabling in the DT is performed by the boot loader. ++ */ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sysin>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sysin>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ eeprom@50 { ++ compatible = "belling,bl24c16a", "atmel,24c16"; ++ reg = <0x50>; ++ pagesize = <16>; ++ vcc-supply = <&vcc_3v3_pmu>; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ vdd_npu_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_npu_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sysin>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c5m2_xfer>; ++ status = "okay"; ++ ++ rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_int_l>; ++ wakeup-source; ++ }; ++}; ++ ++&pcie2x1l1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20x1_1_perstn_m1>; ++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_s3>; ++ status = "okay"; ++}; ++ ++&pcie2x1l2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20x1_2_perstn_m0>; ++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_s3>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ keys { ++ btn_0: button-0 { ++ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_0: led-0 { ++ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie20x1_1_perstn_m1: pcie-1 { ++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie20x1_2_perstn_m0: pcie-2 { ++ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ regulators { ++ vcc_5v0_pwren_h: regulator-5v0-1 { ++ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ rtc { ++ rtc_int_l: rtc-0 { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ usb_otg_pwren_h: regulator-5v0-0 { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm11 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm11m1_pins>; ++ status = "okay"; ++}; ++ ++&pwm14 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm14m1_pins>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ no-sd; ++ no-sdio; ++ non-removable; ++ vmmc-supply = <&vcc_3v3_s0>; ++ vqmmc-supply = <&vcc_1v8_s3>; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ no-sdio; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ num-cs = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ reg = <0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ spi-max-frequency = <1000000>; ++ system-power-controller; ++ ++ vcc1-supply = <&vcc_sysin>; ++ vcc2-supply = <&vcc_sysin>; ++ vcc3-supply = <&vcc_sysin>; ++ vcc4-supply = <&vcc_sysin>; ++ vcc5-supply = <&vcc_sysin>; ++ vcc6-supply = <&vcc_sysin>; ++ vcc7-supply = <&vcc_sysin>; ++ vcc8-supply = <&vcc_sysin>; ++ vcc9-supply = <&vcc_sysin>; ++ vcc10-supply = <&vcc_sysin>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc_sysin>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcca>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: dcdc-reg1 { ++ regulator-name = "vdd_gpu_s0"; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: dcdc-reg2 { ++ regulator-name = "vdd_cpu_lit_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_logic_s0: dcdc-reg3 { ++ regulator-name = "vdd_logic_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: dcdc-reg4 { ++ regulator-name = "vdd_vdenc_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-name = "vdd_ddr_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-name = "vdd2_ddr_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-name = "vcc_2v0_pldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-name = "vcc_3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-name = "vddq_ddr_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-name = "vcc_1v8_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg1 { ++ regulator-name = "vcc_1v8_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca_1v8_s0: pldo-reg2 { ++ regulator-name = "vcca_1v8_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdda_1v2_s0: pldo-reg3 { ++ regulator-name = "vdda_1v2_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca_3v3_s0: pldo-reg4 { ++ regulator-name = "vcca_3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-name = "vccio_sd_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-name = "pldo6_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-name = "vdd_0v75_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdda_ddr_pll_s0: nldo-reg2 { ++ regulator-name = "vdda_ddr_pll_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdda_0v75_s0: nldo-reg3 { ++ regulator-name = "vdda_0v75_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdda_0v85_s0: nldo-reg4 { ++ regulator-name = "vdda_0v85_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-name = "vdd_0v75_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ phy-supply = <&vcc5v0_usb_otg0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usbdp_phy0 { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.12/007-01-v6.13-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R3S-board.patch b/target/linux/rockchip/patches-6.12/007-01-v6.13-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R3S-board.patch new file mode 100644 index 0000000000..fb367b44be --- /dev/null +++ b/target/linux/rockchip/patches-6.12/007-01-v6.13-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R3S-board.patch @@ -0,0 +1,596 @@ +From 50decd493c8394c52d04561fe4ede34df27a46ba Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Mon, 21 Oct 2024 01:39:46 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board + +The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps +Ethernet ports designed and developed by FriendlyElec for IoT +applications. + +Specification: +- Rockchip RK3566 +- 2GB LPDDR4X RAM +- optional 32GB eMMC module +- SD card slot +- 2x 1000 Base-T +- 3x LEDs (POWER, LAN, WAN) +- 2x Buttons (Reset, MaskROM) +- 1x USB 3.0 Port +- Type-C 5V 2A Power + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20241020173946.225960-2-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3566-nanopi-r3s.dts | 554 ++++++++++++++++++ + 2 files changed, 555 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-an + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-odroid-m1s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts +@@ -0,0 +1,554 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2020 Rockchip Electronics Co., Ltd. ++ * ++ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2024 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include ++#include "rk3566.dtsi" ++ ++/ { ++ model = "FriendlyARM NanoPi R3S"; ++ compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ button-reset { ++ label = "reset"; ++ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <50>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>; ++ ++ power_led: led-0 { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ lan_led: led-1 { ++ color = ; ++ function = LED_FUNCTION_LAN; ++ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ wan_led: led-2 { ++ color = ; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ vcc3v3_sys: regulator-vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_usb: regulator-vcc5v0_usb { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en>; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vdd_usbc: regulator-vdd-usbc { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_usbc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&rgmii_phy1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m0_miim ++ &gmac1m0_tx_bus2_level3 ++ &gmac1m0_rx_bus2 ++ &gmac1m0_rgmii_clk_level2 ++ &gmac1m0_rgmii_bus_level3>; ++ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 20ms, 100ms for rtl8211f */ ++ snps,reset-delays-us = <0 20000 100000>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ interrupt-parent = <&gpio4>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ gmac { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pcie { ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic-int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rtc { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb_host_en: vcc5v0-usb-host-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ status = "okay"; ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_3v3>; ++ vccio5-supply = <&vcc_1v8>; ++ vccio6-supply = <&vcc_3v3>; ++ vccio7-supply = <&vcc_3v3>; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ no-sdio; ++ no-mmc; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ sd-uhs-sdr50; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.12/007-02-v6.13-arm64-dts-rockchip-fix-model-name-for-FriendlyElec-NanoPi.patch b/target/linux/rockchip/patches-6.12/007-02-v6.13-arm64-dts-rockchip-fix-model-name-for-FriendlyElec-NanoPi.patch new file mode 100644 index 0000000000..f7dbaff7f0 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/007-02-v6.13-arm64-dts-rockchip-fix-model-name-for-FriendlyElec-NanoPi.patch @@ -0,0 +1,38 @@ +From b5bf84206a5c77528f9dd4cbca4e72caa063c102 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Wed, 23 Oct 2024 03:35:26 +0800 +Subject: [PATCH] arm64: dts: rockchip: fix model name for FriendlyElec NanoPi + R3S + +Use the marketing name for model name, this matches the dt-binding. +Also update the website url in copyright. + +Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") +Suggested-by: Jonas Karlman +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20241022193537.1117919-2-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts +@@ -3,7 +3,7 @@ + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. +- * (http://www.friendlyarm.com) ++ * (http://www.friendlyelec.com) + * + * Copyright (c) 2024 Tianling Shen + */ +@@ -17,7 +17,7 @@ + #include "rk3566.dtsi" + + / { +- model = "FriendlyARM NanoPi R3S"; ++ model = "FriendlyElec NanoPi R3S"; + compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; + + aliases { diff --git a/target/linux/rockchip/patches-6.12/007-03-v1.13-arm64-dts-rockchip-replace-deprecated-snps-reset-props-fo.patch b/target/linux/rockchip/patches-6.12/007-03-v1.13-arm64-dts-rockchip-replace-deprecated-snps-reset-props-fo.patch new file mode 100644 index 0000000000..2b7c092cab --- /dev/null +++ b/target/linux/rockchip/patches-6.12/007-03-v1.13-arm64-dts-rockchip-replace-deprecated-snps-reset-props-fo.patch @@ -0,0 +1,40 @@ +From 82b2868937883b65732da498b26366d34db61510 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Wed, 23 Oct 2024 03:35:27 +0800 +Subject: [PATCH] arm64: dts: rockchip: replace deprecated snps,reset props for + NanoPi R3S + +Replace deprecated snps,reset props and move them to the PHY node. + +Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") +Suggested-by: Jonas Karlman +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20241022193537.1117919-3-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts +@@ -149,10 +149,6 @@ + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk_level2 + &gmac1m0_rgmii_bus_level3>; +- snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- /* Reset time is 20ms, 100ms for rtl8211f */ +- snps,reset-delays-us = <0 20000 100000>; + status = "okay"; + }; + +@@ -414,6 +410,9 @@ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_reset_pin>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.12/007-04-v6.13-arm64-dts-rockchip-sort-props-in-pmu_io_domains-node-for.patch b/target/linux/rockchip/patches-6.12/007-04-v6.13-arm64-dts-rockchip-sort-props-in-pmu_io_domains-node-for.patch new file mode 100644 index 0000000000..6b09fc96a4 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/007-04-v6.13-arm64-dts-rockchip-sort-props-in-pmu_io_domains-node-for.patch @@ -0,0 +1,35 @@ +From 17e150fdd983c7e59b9240e34a166285f3c3fb39 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Wed, 23 Oct 2024 03:35:28 +0800 +Subject: [PATCH] arm64: dts: rockchip: sort props in pmu_io_domains node for + NanoPi R3S + +The status prop is typically the last prop. + +Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") +Suggested-by: Jonas Karlman +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20241022193537.1117919-4-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts +@@ -476,7 +476,6 @@ + }; + + &pmu_io_domains { +- status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; +@@ -486,6 +485,7 @@ + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; ++ status = "okay"; + }; + + &sdhci { diff --git a/target/linux/rockchip/patches-6.12/007-05-v6.13-arm64-dts-rockchip-enable-eMMC-HS200-mode-for-NanoPi-R3S.patch b/target/linux/rockchip/patches-6.12/007-05-v6.13-arm64-dts-rockchip-enable-eMMC-HS200-mode-for-NanoPi-R3S.patch new file mode 100644 index 0000000000..bbe8ccfe69 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/007-05-v6.13-arm64-dts-rockchip-enable-eMMC-HS200-mode-for-NanoPi-R3S.patch @@ -0,0 +1,26 @@ +From 1b5365034410f1ca21adadadd492b99bdf4f2c55 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Wed, 23 Oct 2024 03:35:29 +0800 +Subject: [PATCH] arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S + +It is required to boot from eMMC without additional patch in u-boot. + +Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") +Suggested-by: Jonas Karlman +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20241022193537.1117919-5-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts +@@ -491,6 +491,7 @@ + &sdhci { + bus-width = <8>; + max-frequency = <200000000>; ++ mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; diff --git a/target/linux/rockchip/patches-6.12/007-06-v6.13-arm64-dts-rockchip-reorder-mmc-aliases-for-NanoPi-R3S.patch b/target/linux/rockchip/patches-6.12/007-06-v6.13-arm64-dts-rockchip-reorder-mmc-aliases-for-NanoPi-R3S.patch new file mode 100644 index 0000000000..f262e251e2 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/007-06-v6.13-arm64-dts-rockchip-reorder-mmc-aliases-for-NanoPi-R3S.patch @@ -0,0 +1,31 @@ +From b7cd1115456d312f8c5e60c80fdc35fd35ea6eab Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Wed, 23 Oct 2024 03:35:30 +0800 +Subject: [PATCH] arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S + +Typically any non-removable storage (emmc) is listed before removable +storage (sd-card) options. Also U-Boot will try to override and use +mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards. + +Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") +Suggested-by: Jonas Karlman +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20241022193537.1117919-6-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts +@@ -22,8 +22,8 @@ + + aliases { + ethernet0 = &gmac1; +- mmc0 = &sdmmc0; +- mmc1 = &sdhci; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; + }; + + chosen: chosen { diff --git a/target/linux/rockchip/patches-6.12/008-01-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch b/target/linux/rockchip/patches-6.12/008-01-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch new file mode 100644 index 0000000000..a31e4595c4 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/008-01-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch @@ -0,0 +1,51 @@ +From f15be3d4a0a55db2b50f319c378a2d16ceb21f86 Mon Sep 17 00:00:00 2001 +From: Dmitry Osipenko +Date: Mon, 17 Feb 2025 01:16:33 +0300 +Subject: [PATCH] arm64: dts: rockchip: rk356x: Add MSI controller node + +Rockchip 356x SoC's GIC has two hardware integration issues that +affect MSI functionality of the GIC. Previously, both these GIC +issues were worked around by using MBI for MSI instead of ITS +because kernel GIC driver didn't have necessary quirks. + +First issue is about RK356x GIC not supporting programmable +shareability, while reporting it as supported in a GIC's feature +register. Rockchip assigned Erratum ID #3568001 for this issue. This +patch adds dma-noncoherent property to the GIC node, denoting that a SW +workaround is required for mitigating the issue. + +Second issue is about GIC AXI master interface addressing limited to +the first 4GB of physical address space. Rockchip assigned Erratum +ID #3568002 for this issue. + +Now that kernel supports quirks for both of the erratums, add +MSI controller node to RK356x device-tree. + +Signed-off-by: Dmitry Osipenko +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/all/20250216221634.364158-3-dmitry.osipenko@collabora.com +--- + arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -364,6 +364,18 @@ + mbi-alias = <0x0 0xfd410000>; + mbi-ranges = <296 24>; + msi-controller; ++ ranges; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ dma-noncoherent; ++ ++ its: msi-controller@fd440000 { ++ compatible = "arm,gic-v3-its"; ++ reg = <0x0 0xfd440000 0 0x20000>; ++ dma-noncoherent; ++ msi-controller; ++ #msi-cells = <1>; ++ }; + }; + + usb_host0_ehci: usb@fd800000 { diff --git a/target/linux/rockchip/patches-6.12/008-02-v6.15-arm64-dts-rockchip-rk356x-Move-PCIe-MSI-to-use-GIC.patch b/target/linux/rockchip/patches-6.12/008-02-v6.15-arm64-dts-rockchip-rk356x-Move-PCIe-MSI-to-use-GIC.patch new file mode 100644 index 0000000000..bfe88205ed --- /dev/null +++ b/target/linux/rockchip/patches-6.12/008-02-v6.15-arm64-dts-rockchip-rk356x-Move-PCIe-MSI-to-use-GIC.patch @@ -0,0 +1,28 @@ +From b956c9de91757c9478e24fc9f6a57fd46f0a49f0 Mon Sep 17 00:00:00 2001 +From: Dmitry Osipenko +Date: Mon, 17 Feb 2025 01:16:34 +0300 +Subject: [PATCH] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC + ITS instead of MBI + +Rockchip 356x device-tree now supports GIC ITS. Move PCIe controller's +MSI to use ITS instead of MBI. This removes extra CPU overhead of handling +PCIe MBIs by letting GIC's ITS to serve the PCIe MSIs. + +Signed-off-by: Dmitry Osipenko +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/all/20250216221634.364158-4-dmitry.osipenko@collabora.com +--- + arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1050,7 +1050,7 @@ + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <2>; +- msi-map = <0x0 &gic 0x0 0x1000>; ++ msi-map = <0x0 &its 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; diff --git a/target/linux/rockchip/patches-6.12/008-03-v6.16-arm64-dts-rockchip-Move-rk3568-PCIe3-MSI-to-use-GIC-.patch b/target/linux/rockchip/patches-6.12/008-03-v6.16-arm64-dts-rockchip-Move-rk3568-PCIe3-MSI-to-use-GIC-.patch new file mode 100644 index 0000000000..c5bbaed492 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/008-03-v6.16-arm64-dts-rockchip-Move-rk3568-PCIe3-MSI-to-use-GIC-.patch @@ -0,0 +1,54 @@ +From fbea35a661ed100cee2f3bab8015fb0155508106 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 8 Mar 2025 17:30:08 +0800 +Subject: [PATCH] arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS + +Following commit b956c9de9175 ("arm64: dts: rockchip: rk356x: Move +PCIe MSI to use GIC ITS instead of MBI"), change the PCIe3 controller's +MSI on rk3568 to use ITS, so that all MSI-X can work properly. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20250308093008.568437-2-amadeus@jmu.edu.cn +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -64,7 +64,7 @@ + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; +- bus-range = <0x0 0xf>; ++ bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>; +@@ -87,7 +87,7 @@ + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; +- msi-map = <0x0 &gic 0x1000 0x1000>; ++ msi-map = <0x1000 &its 0x1000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; +@@ -117,7 +117,7 @@ + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; +- bus-range = <0x0 0xf>; ++ bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>; +@@ -140,7 +140,7 @@ + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; +- msi-map = <0x0 &gic 0x2000 0x1000>; ++ msi-map = <0x2000 &its 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; diff --git a/target/linux/rockchip/patches-6.12/009-v6.13-arm64-dts-rockchip-enable-USB3-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.12/009-v6.13-arm64-dts-rockchip-enable-USB3-on-NanoPC-T6.patch new file mode 100644 index 0000000000..f7686cd439 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/009-v6.13-arm64-dts-rockchip-enable-USB3-on-NanoPC-T6.patch @@ -0,0 +1,87 @@ +From a6ae420439dc47a58550a6e61e596e9dd1562caf Mon Sep 17 00:00:00 2001 +From: Rick Wertenbroek +Date: Wed, 6 Nov 2024 14:03:13 +0100 +Subject: [PATCH] arm64: dts: rockchip: enable USB3 on NanoPC-T6 + +Enable the USB3 port on FriendlyELEC NanoPC-T6. + +Signed-off-by: Rick Wertenbroek +Link: https://lore.kernel.org/r/20241106130314.1289055-1-rick.wertenbroek@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 36 +++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +@@ -159,6 +159,20 @@ + vin-supply = <&vcc5v0_sys>; + }; + ++ vbus5v0_usb: vbus5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb5v_pwren>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vbus5v0_usb"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + enable-active-high; +@@ -575,6 +589,10 @@ + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + ++ usb5v_pwren: usb5v_pwren { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; +@@ -973,6 +991,14 @@ + status = "okay"; + }; + ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ + &u2phy2_host { + status = "okay"; + }; +@@ -1012,6 +1038,11 @@ + }; + }; + ++&usbdp_phy1 { ++ phy-supply = <&vbus5v0_usb>; ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + }; +@@ -1032,6 +1063,11 @@ + }; + }; + ++&usb_host1_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &usb_host1_ehci { + status = "okay"; + }; diff --git a/target/linux/rockchip/patches-6.12/020-v6.13-irqchip-gic-v3-its-Share-ITS-tables-with-a-non-trust.patch b/target/linux/rockchip/patches-6.12/020-v6.13-irqchip-gic-v3-its-Share-ITS-tables-with-a-non-trust.patch deleted file mode 100644 index ef1e51f1cc..0000000000 --- a/target/linux/rockchip/patches-6.12/020-v6.13-irqchip-gic-v3-its-Share-ITS-tables-with-a-non-trust.patch +++ /dev/null @@ -1,337 +0,0 @@ -From b08e2f42e86b5848add254da45b56fc672e2bced Mon Sep 17 00:00:00 2001 -From: Steven Price -Date: Wed, 2 Oct 2024 15:16:29 +0100 -Subject: [PATCH] irqchip/gic-v3-its: Share ITS tables with a non-trusted - hypervisor - -Within a realm guest the ITS is emulated by the host. This means the -allocations must have been made available to the host by a call to -set_memory_decrypted(). Introduce an allocation function which performs -this extra call. - -For the ITT use a custom genpool-based allocator that calls -set_memory_decrypted() for each page allocated, but then suballocates the -size needed for each ITT. Note that there is no mechanism implemented to -return pages from the genpool, but it is unlikely that the peak number of -devices will be much larger than the normal level - so this isn't expected -to be an issue. - -Co-developed-by: Suzuki K Poulose -Signed-off-by: Suzuki K Poulose -Signed-off-by: Steven Price -Signed-off-by: Thomas Gleixner -Tested-by: Will Deacon -Reviewed-by: Marc Zyngier -Link: https://lore.kernel.org/all/20241002141630.433502-2-steven.price@arm.com ---- - drivers/irqchip/irq-gic-v3-its.c | 138 +++++++++++++++++++++++++------ - 1 file changed, 115 insertions(+), 23 deletions(-) - ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -12,12 +12,14 @@ - #include - #include - #include -+#include - #include - #include - #include - #include - #include - #include -+#include - #include - #include - #include -@@ -27,6 +29,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -166,6 +169,7 @@ struct its_device { - struct its_node *its; - struct event_lpi_map event_map; - void *itt; -+ u32 itt_sz; - u32 nr_ites; - u32 device_id; - bool shared; -@@ -201,6 +205,87 @@ static DEFINE_IDA(its_vpeid_ida); - #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) - #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) - -+static struct page *its_alloc_pages_node(int node, gfp_t gfp, -+ unsigned int order) -+{ -+ struct page *page; -+ int ret = 0; -+ -+ page = alloc_pages_node(node, gfp, order); -+ -+ if (!page) -+ return NULL; -+ -+ ret = set_memory_decrypted((unsigned long)page_address(page), -+ 1 << order); -+ /* -+ * If set_memory_decrypted() fails then we don't know what state the -+ * page is in, so we can't free it. Instead we leak it. -+ * set_memory_decrypted() will already have WARNed. -+ */ -+ if (ret) -+ return NULL; -+ -+ return page; -+} -+ -+static struct page *its_alloc_pages(gfp_t gfp, unsigned int order) -+{ -+ return its_alloc_pages_node(NUMA_NO_NODE, gfp, order); -+} -+ -+static void its_free_pages(void *addr, unsigned int order) -+{ -+ /* -+ * If the memory cannot be encrypted again then we must leak the pages. -+ * set_memory_encrypted() will already have WARNed. -+ */ -+ if (set_memory_encrypted((unsigned long)addr, 1 << order)) -+ return; -+ free_pages((unsigned long)addr, order); -+} -+ -+static struct gen_pool *itt_pool; -+ -+static void *itt_alloc_pool(int node, int size) -+{ -+ unsigned long addr; -+ struct page *page; -+ -+ if (size >= PAGE_SIZE) { -+ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, get_order(size)); -+ -+ return page ? page_address(page) : NULL; -+ } -+ -+ do { -+ addr = gen_pool_alloc(itt_pool, size); -+ if (addr) -+ break; -+ -+ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1); -+ if (!page) -+ break; -+ -+ gen_pool_add(itt_pool, (unsigned long)page_address(page), PAGE_SIZE, node); -+ } while (!addr); -+ -+ return (void *)addr; -+} -+ -+static void itt_free_pool(void *addr, int size) -+{ -+ if (!addr) -+ return; -+ -+ if (size >= PAGE_SIZE) { -+ its_free_pages(addr, get_order(size)); -+ return; -+ } -+ -+ gen_pool_free(itt_pool, (unsigned long)addr, size); -+} -+ - /* - * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we - * always have vSGIs mapped. -@@ -2183,7 +2268,8 @@ static struct page *its_allocate_prop_ta - { - struct page *prop_page; - -- prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); -+ prop_page = its_alloc_pages(gfp_flags, -+ get_order(LPI_PROPBASE_SZ)); - if (!prop_page) - return NULL; - -@@ -2194,8 +2280,7 @@ static struct page *its_allocate_prop_ta - - static void its_free_prop_table(struct page *prop_page) - { -- free_pages((unsigned long)page_address(prop_page), -- get_order(LPI_PROPBASE_SZ)); -+ its_free_pages(page_address(prop_page), get_order(LPI_PROPBASE_SZ)); - } - - static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size) -@@ -2317,7 +2402,7 @@ static int its_setup_baser(struct its_no - order = get_order(GITS_BASER_PAGES_MAX * psz); - } - -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); -+ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); - if (!page) - return -ENOMEM; - -@@ -2330,7 +2415,7 @@ static int its_setup_baser(struct its_no - /* 52bit PA is supported only when PageSize=64K */ - if (psz != SZ_64K) { - pr_err("ITS: no 52bit PA support when psz=%d\n", psz); -- free_pages((unsigned long)base, order); -+ its_free_pages(base, order); - return -ENXIO; - } - -@@ -2386,7 +2471,7 @@ retry_baser: - pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", - &its->phys_base, its_base_type_string[type], - val, tmp); -- free_pages((unsigned long)base, order); -+ its_free_pages(base, order); - return -ENXIO; - } - -@@ -2525,8 +2610,7 @@ static void its_free_tables(struct its_n - - for (i = 0; i < GITS_BASER_NR_REGS; i++) { - if (its->tables[i].base) { -- free_pages((unsigned long)its->tables[i].base, -- its->tables[i].order); -+ its_free_pages(its->tables[i].base, its->tables[i].order); - its->tables[i].base = NULL; - } - } -@@ -2792,7 +2876,7 @@ static bool allocate_vpe_l2_table(int cp - - /* Allocate memory for 2nd level table */ - if (!table[idx]) { -- page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz)); -+ page = its_alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz)); - if (!page) - return false; - -@@ -2911,7 +2995,7 @@ static int allocate_vpe_l1_table(void) - - pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n", - np, npg, psz, epp, esz); -- page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE)); -+ page = its_alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE)); - if (!page) - return -ENOMEM; - -@@ -2957,8 +3041,7 @@ static struct page *its_allocate_pending - { - struct page *pend_page; - -- pend_page = alloc_pages(gfp_flags | __GFP_ZERO, -- get_order(LPI_PENDBASE_SZ)); -+ pend_page = its_alloc_pages(gfp_flags | __GFP_ZERO, get_order(LPI_PENDBASE_SZ)); - if (!pend_page) - return NULL; - -@@ -2970,7 +3053,7 @@ static struct page *its_allocate_pending - - static void its_free_pending_table(struct page *pt) - { -- free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ)); -+ its_free_pages(page_address(pt), get_order(LPI_PENDBASE_SZ)); - } - - /* -@@ -3305,8 +3388,8 @@ static bool its_alloc_table_entry(struct - - /* Allocate memory for 2nd level table */ - if (!table[idx]) { -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -- get_order(baser->psz)); -+ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -+ get_order(baser->psz)); - if (!page) - return false; - -@@ -3401,7 +3484,6 @@ static struct its_device *its_create_dev - if (WARN_ON(!is_power_of_2(nvecs))) - nvecs = roundup_pow_of_two(nvecs); - -- dev = kzalloc(sizeof(*dev), GFP_KERNEL); - /* - * Even if the device wants a single LPI, the ITT must be - * sized as a power of two (and you need at least one bit...). -@@ -3409,7 +3491,11 @@ static struct its_device *its_create_dev - nr_ites = max(2, nvecs); - sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); - sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; -- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); -+ -+ itt = itt_alloc_pool(its->numa_node, sz); -+ -+ dev = kzalloc(sizeof(*dev), GFP_KERNEL); -+ - if (alloc_lpis) { - lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); - if (lpi_map) -@@ -3421,9 +3507,9 @@ static struct its_device *its_create_dev - lpi_base = 0; - } - -- if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { -+ if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { - kfree(dev); -- kfree(itt); -+ itt_free_pool(itt, sz); - bitmap_free(lpi_map); - kfree(col_map); - return NULL; -@@ -3433,6 +3519,7 @@ static struct its_device *its_create_dev - - dev->its = its; - dev->itt = itt; -+ dev->itt_sz = sz; - dev->nr_ites = nr_ites; - dev->event_map.lpi_map = lpi_map; - dev->event_map.col_map = col_map; -@@ -3460,7 +3547,7 @@ static void its_free_device(struct its_d - list_del(&its_dev->entry); - raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); - kfree(its_dev->event_map.col_map); -- kfree(its_dev->itt); -+ itt_free_pool(its_dev->itt, its_dev->itt_sz); - kfree(its_dev); - } - -@@ -5160,8 +5247,9 @@ static int __init its_probe_one(struct i - } - } - -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -- get_order(ITS_CMD_QUEUE_SZ)); -+ page = its_alloc_pages_node(its->numa_node, -+ GFP_KERNEL | __GFP_ZERO, -+ get_order(ITS_CMD_QUEUE_SZ)); - if (!page) { - err = -ENOMEM; - goto out_unmap_sgir; -@@ -5225,7 +5313,7 @@ static int __init its_probe_one(struct i - out_free_tables: - its_free_tables(its); - out_free_cmd: -- free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); -+ its_free_pages(its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); - out_unmap_sgir: - if (its->sgir_base) - iounmap(its->sgir_base); -@@ -5711,6 +5799,10 @@ int __init its_init(struct fwnode_handle - bool has_v4_1 = false; - int err; - -+ itt_pool = gen_pool_create(get_order(ITS_ITT_ALIGN), -1); -+ if (!itt_pool) -+ return -ENOMEM; -+ - gic_rdists = rdists; - - lpi_prop_prio = irq_prio; diff --git a/target/linux/rockchip/patches-6.12/021-v6.13-irqchip-gic-v3-its-Fix-over-allocation-in-itt_alloc.patch b/target/linux/rockchip/patches-6.12/021-v6.13-irqchip-gic-v3-its-Fix-over-allocation-in-itt_alloc.patch deleted file mode 100644 index 6378534273..0000000000 --- a/target/linux/rockchip/patches-6.12/021-v6.13-irqchip-gic-v3-its-Fix-over-allocation-in-itt_alloc.patch +++ /dev/null @@ -1,33 +0,0 @@ -From bc88d44bd7e45b992cf8c2c2ffbc7bb3e24db4a7 Mon Sep 17 00:00:00 2001 -From: Steven Price -Date: Mon, 21 Oct 2024 11:41:05 +0100 -Subject: [PATCH] irqchip/gic-v3-its: Fix over allocation in - itt_alloc_pool() - -itt_alloc_pool() calls its_alloc_pages_node() to allocate an individual -page to add to the pool (for allocations -Signed-off-by: Steven Price -Signed-off-by: Thomas Gleixner -Link: https://lore.kernel.org/all/1f6e19c4-1fb9-43ab-a8a2-a465c9cff84b@arm.com -Closes: https://lore.kernel.org/r/ed65312a-245c-4fa5-91ad-5d620cab7c6b%40nvidia.com ---- - drivers/irqchip/irq-gic-v3-its.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -263,7 +263,7 @@ static void *itt_alloc_pool(int node, in - if (addr) - break; - -- page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1); -+ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 0); - if (!page) - break; - diff --git a/target/linux/rockchip/patches-6.12/022-v6.15-irqchip-gic-v3-Add-Rockchip-3568002-erratum-workaround.patch b/target/linux/rockchip/patches-6.12/022-v6.15-irqchip-gic-v3-Add-Rockchip-3568002-erratum-workaround.patch deleted file mode 100644 index 17a4e528ca..0000000000 --- a/target/linux/rockchip/patches-6.12/022-v6.15-irqchip-gic-v3-Add-Rockchip-3568002-erratum-workaround.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 2d81e1bb625238d40a686ed909ff3e1abab7556a Mon Sep 17 00:00:00 2001 -From: Dmitry Osipenko -Date: Mon, 17 Feb 2025 01:16:32 +0300 -Subject: [PATCH] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround - -Rockchip RK3566/RK3568 GIC600 integration has DDR addressing -limited to the first 32bit of physical address space. Rockchip -assigned Erratum ID #3568002 for this issue. Add driver quirk for -this Rockchip GIC Erratum. - -Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is -common for many ARM GICv3 implementations. Hence, there is an extra -of_machine_is_compatible() check. - -Signed-off-by: Dmitry Osipenko -Signed-off-by: Thomas Gleixner -Acked-by: Marc Zyngier -Link: https://lore.kernel.org/all/20250216221634.364158-2-dmitry.osipenko@collabora.com ---- - Documentation/arch/arm64/silicon-errata.rst | 2 ++ - arch/arm64/Kconfig | 9 ++++++++ - drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++++- - 3 files changed, 33 insertions(+), 1 deletion(-) - ---- a/Documentation/arch/arm64/silicon-errata.rst -+++ b/Documentation/arch/arm64/silicon-errata.rst -@@ -283,6 +283,8 @@ stable kernels. - +----------------+-----------------+-----------------+-----------------------------+ - | Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 | - +----------------+-----------------+-----------------+-----------------------------+ -+| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 | -++----------------+-----------------+-----------------+-----------------------------+ - +----------------+-----------------+-----------------+-----------------------------+ - | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | - +----------------+-----------------+-----------------+-----------------------------+ ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -1295,6 +1295,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM - - If unsure, say Y. - -+config ROCKCHIP_ERRATUM_3568002 -+ bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" -+ default y -+ help -+ The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI -+ addressing limited to the first 32bit of physical address space. -+ -+ If unsure, say Y. -+ - config ROCKCHIP_ERRATUM_3588001 - bool "Rockchip 3588001: GIC600 can not support shareability attributes" - default y ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -205,13 +205,15 @@ static DEFINE_IDA(its_vpeid_ida); - #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) - #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) - -+static gfp_t gfp_flags_quirk; -+ - static struct page *its_alloc_pages_node(int node, gfp_t gfp, - unsigned int order) - { - struct page *page; - int ret = 0; - -- page = alloc_pages_node(node, gfp, order); -+ page = alloc_pages_node(node, gfp | gfp_flags_quirk, order); - - if (!page) - return NULL; -@@ -4888,6 +4890,17 @@ static bool __maybe_unused its_enable_qu - return true; - } - -+static bool __maybe_unused its_enable_rk3568002(void *data) -+{ -+ if (!of_machine_is_compatible("rockchip,rk3566") && -+ !of_machine_is_compatible("rockchip,rk3568")) -+ return false; -+ -+ gfp_flags_quirk |= GFP_DMA32; -+ -+ return true; -+} -+ - static const struct gic_quirk its_quirks[] = { - #ifdef CONFIG_CAVIUM_ERRATUM_22375 - { -@@ -4955,6 +4968,14 @@ static const struct gic_quirk its_quirks - .property = "dma-noncoherent", - .init = its_set_non_coherent, - }, -+#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002 -+ { -+ .desc = "ITS: Rockchip erratum RK3568002", -+ .iidr = 0x0201743b, -+ .mask = 0xffffffff, -+ .init = its_enable_rk3568002, -+ }, -+#endif - { - } - }; diff --git a/target/linux/rockchip/patches-6.12/023-01-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch b/target/linux/rockchip/patches-6.12/023-01-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch deleted file mode 100644 index a31e4595c4..0000000000 --- a/target/linux/rockchip/patches-6.12/023-01-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch +++ /dev/null @@ -1,51 +0,0 @@ -From f15be3d4a0a55db2b50f319c378a2d16ceb21f86 Mon Sep 17 00:00:00 2001 -From: Dmitry Osipenko -Date: Mon, 17 Feb 2025 01:16:33 +0300 -Subject: [PATCH] arm64: dts: rockchip: rk356x: Add MSI controller node - -Rockchip 356x SoC's GIC has two hardware integration issues that -affect MSI functionality of the GIC. Previously, both these GIC -issues were worked around by using MBI for MSI instead of ITS -because kernel GIC driver didn't have necessary quirks. - -First issue is about RK356x GIC not supporting programmable -shareability, while reporting it as supported in a GIC's feature -register. Rockchip assigned Erratum ID #3568001 for this issue. This -patch adds dma-noncoherent property to the GIC node, denoting that a SW -workaround is required for mitigating the issue. - -Second issue is about GIC AXI master interface addressing limited to -the first 4GB of physical address space. Rockchip assigned Erratum -ID #3568002 for this issue. - -Now that kernel supports quirks for both of the erratums, add -MSI controller node to RK356x device-tree. - -Signed-off-by: Dmitry Osipenko -Signed-off-by: Thomas Gleixner -Link: https://lore.kernel.org/all/20250216221634.364158-3-dmitry.osipenko@collabora.com ---- - arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -364,6 +364,18 @@ - mbi-alias = <0x0 0xfd410000>; - mbi-ranges = <296 24>; - msi-controller; -+ ranges; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ dma-noncoherent; -+ -+ its: msi-controller@fd440000 { -+ compatible = "arm,gic-v3-its"; -+ reg = <0x0 0xfd440000 0 0x20000>; -+ dma-noncoherent; -+ msi-controller; -+ #msi-cells = <1>; -+ }; - }; - - usb_host0_ehci: usb@fd800000 { diff --git a/target/linux/rockchip/patches-6.12/023-02-v6.15-arm64-dts-rockchip-rk356x-Move-PCIe-MSI-to-use-GIC.patch b/target/linux/rockchip/patches-6.12/023-02-v6.15-arm64-dts-rockchip-rk356x-Move-PCIe-MSI-to-use-GIC.patch deleted file mode 100644 index bfe88205ed..0000000000 --- a/target/linux/rockchip/patches-6.12/023-02-v6.15-arm64-dts-rockchip-rk356x-Move-PCIe-MSI-to-use-GIC.patch +++ /dev/null @@ -1,28 +0,0 @@ -From b956c9de91757c9478e24fc9f6a57fd46f0a49f0 Mon Sep 17 00:00:00 2001 -From: Dmitry Osipenko -Date: Mon, 17 Feb 2025 01:16:34 +0300 -Subject: [PATCH] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC - ITS instead of MBI - -Rockchip 356x device-tree now supports GIC ITS. Move PCIe controller's -MSI to use ITS instead of MBI. This removes extra CPU overhead of handling -PCIe MBIs by letting GIC's ITS to serve the PCIe MSIs. - -Signed-off-by: Dmitry Osipenko -Signed-off-by: Thomas Gleixner -Link: https://lore.kernel.org/all/20250216221634.364158-4-dmitry.osipenko@collabora.com ---- - arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -1050,7 +1050,7 @@ - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <2>; -- msi-map = <0x0 &gic 0x0 0x1000>; -+ msi-map = <0x0 &its 0x0 0x1000>; - num-lanes = <1>; - phys = <&combphy2 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; diff --git a/target/linux/rockchip/patches-6.12/024-v6.16-arm64-dts-rockchip-Move-rk3568-PCIe3-MSI-to-use-GIC-.patch b/target/linux/rockchip/patches-6.12/024-v6.16-arm64-dts-rockchip-Move-rk3568-PCIe3-MSI-to-use-GIC-.patch deleted file mode 100644 index c5bbaed492..0000000000 --- a/target/linux/rockchip/patches-6.12/024-v6.16-arm64-dts-rockchip-Move-rk3568-PCIe3-MSI-to-use-GIC-.patch +++ /dev/null @@ -1,54 +0,0 @@ -From fbea35a661ed100cee2f3bab8015fb0155508106 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 8 Mar 2025 17:30:08 +0800 -Subject: [PATCH] arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS - -Following commit b956c9de9175 ("arm64: dts: rockchip: rk356x: Move -PCIe MSI to use GIC ITS instead of MBI"), change the PCIe3 controller's -MSI on rk3568 to use ITS, so that all MSI-X can work properly. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20250308093008.568437-2-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -64,7 +64,7 @@ - compatible = "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; -- bus-range = <0x0 0xf>; -+ bus-range = <0x10 0x1f>; - clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, - <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, - <&cru CLK_PCIE30X1_AUX_NDFT>; -@@ -87,7 +87,7 @@ - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <3>; -- msi-map = <0x0 &gic 0x1000 0x1000>; -+ msi-map = <0x1000 &its 0x1000 0x1000>; - num-lanes = <1>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; -@@ -117,7 +117,7 @@ - compatible = "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; -- bus-range = <0x0 0xf>; -+ bus-range = <0x20 0x2f>; - clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, - <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, - <&cru CLK_PCIE30X2_AUX_NDFT>; -@@ -140,7 +140,7 @@ - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <3>; -- msi-map = <0x0 &gic 0x2000 0x1000>; -+ msi-map = <0x2000 &its 0x2000 0x1000>; - num-lanes = <2>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; diff --git a/target/linux/rockchip/patches-6.12/030-01-v6.13-irqchip-gic-v3-its-Share-ITS-tables-with-a-non-trust.patch b/target/linux/rockchip/patches-6.12/030-01-v6.13-irqchip-gic-v3-its-Share-ITS-tables-with-a-non-trust.patch new file mode 100644 index 0000000000..ef1e51f1cc --- /dev/null +++ b/target/linux/rockchip/patches-6.12/030-01-v6.13-irqchip-gic-v3-its-Share-ITS-tables-with-a-non-trust.patch @@ -0,0 +1,337 @@ +From b08e2f42e86b5848add254da45b56fc672e2bced Mon Sep 17 00:00:00 2001 +From: Steven Price +Date: Wed, 2 Oct 2024 15:16:29 +0100 +Subject: [PATCH] irqchip/gic-v3-its: Share ITS tables with a non-trusted + hypervisor + +Within a realm guest the ITS is emulated by the host. This means the +allocations must have been made available to the host by a call to +set_memory_decrypted(). Introduce an allocation function which performs +this extra call. + +For the ITT use a custom genpool-based allocator that calls +set_memory_decrypted() for each page allocated, but then suballocates the +size needed for each ITT. Note that there is no mechanism implemented to +return pages from the genpool, but it is unlikely that the peak number of +devices will be much larger than the normal level - so this isn't expected +to be an issue. + +Co-developed-by: Suzuki K Poulose +Signed-off-by: Suzuki K Poulose +Signed-off-by: Steven Price +Signed-off-by: Thomas Gleixner +Tested-by: Will Deacon +Reviewed-by: Marc Zyngier +Link: https://lore.kernel.org/all/20241002141630.433502-2-steven.price@arm.com +--- + drivers/irqchip/irq-gic-v3-its.c | 138 +++++++++++++++++++++++++------ + 1 file changed, 115 insertions(+), 23 deletions(-) + +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -12,12 +12,14 @@ + #include + #include + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + #include + #include + #include +@@ -27,6 +29,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -166,6 +169,7 @@ struct its_device { + struct its_node *its; + struct event_lpi_map event_map; + void *itt; ++ u32 itt_sz; + u32 nr_ites; + u32 device_id; + bool shared; +@@ -201,6 +205,87 @@ static DEFINE_IDA(its_vpeid_ida); + #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) + #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) + ++static struct page *its_alloc_pages_node(int node, gfp_t gfp, ++ unsigned int order) ++{ ++ struct page *page; ++ int ret = 0; ++ ++ page = alloc_pages_node(node, gfp, order); ++ ++ if (!page) ++ return NULL; ++ ++ ret = set_memory_decrypted((unsigned long)page_address(page), ++ 1 << order); ++ /* ++ * If set_memory_decrypted() fails then we don't know what state the ++ * page is in, so we can't free it. Instead we leak it. ++ * set_memory_decrypted() will already have WARNed. ++ */ ++ if (ret) ++ return NULL; ++ ++ return page; ++} ++ ++static struct page *its_alloc_pages(gfp_t gfp, unsigned int order) ++{ ++ return its_alloc_pages_node(NUMA_NO_NODE, gfp, order); ++} ++ ++static void its_free_pages(void *addr, unsigned int order) ++{ ++ /* ++ * If the memory cannot be encrypted again then we must leak the pages. ++ * set_memory_encrypted() will already have WARNed. ++ */ ++ if (set_memory_encrypted((unsigned long)addr, 1 << order)) ++ return; ++ free_pages((unsigned long)addr, order); ++} ++ ++static struct gen_pool *itt_pool; ++ ++static void *itt_alloc_pool(int node, int size) ++{ ++ unsigned long addr; ++ struct page *page; ++ ++ if (size >= PAGE_SIZE) { ++ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, get_order(size)); ++ ++ return page ? page_address(page) : NULL; ++ } ++ ++ do { ++ addr = gen_pool_alloc(itt_pool, size); ++ if (addr) ++ break; ++ ++ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1); ++ if (!page) ++ break; ++ ++ gen_pool_add(itt_pool, (unsigned long)page_address(page), PAGE_SIZE, node); ++ } while (!addr); ++ ++ return (void *)addr; ++} ++ ++static void itt_free_pool(void *addr, int size) ++{ ++ if (!addr) ++ return; ++ ++ if (size >= PAGE_SIZE) { ++ its_free_pages(addr, get_order(size)); ++ return; ++ } ++ ++ gen_pool_free(itt_pool, (unsigned long)addr, size); ++} ++ + /* + * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we + * always have vSGIs mapped. +@@ -2183,7 +2268,8 @@ static struct page *its_allocate_prop_ta + { + struct page *prop_page; + +- prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); ++ prop_page = its_alloc_pages(gfp_flags, ++ get_order(LPI_PROPBASE_SZ)); + if (!prop_page) + return NULL; + +@@ -2194,8 +2280,7 @@ static struct page *its_allocate_prop_ta + + static void its_free_prop_table(struct page *prop_page) + { +- free_pages((unsigned long)page_address(prop_page), +- get_order(LPI_PROPBASE_SZ)); ++ its_free_pages(page_address(prop_page), get_order(LPI_PROPBASE_SZ)); + } + + static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size) +@@ -2317,7 +2402,7 @@ static int its_setup_baser(struct its_no + order = get_order(GITS_BASER_PAGES_MAX * psz); + } + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); ++ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); + if (!page) + return -ENOMEM; + +@@ -2330,7 +2415,7 @@ static int its_setup_baser(struct its_no + /* 52bit PA is supported only when PageSize=64K */ + if (psz != SZ_64K) { + pr_err("ITS: no 52bit PA support when psz=%d\n", psz); +- free_pages((unsigned long)base, order); ++ its_free_pages(base, order); + return -ENXIO; + } + +@@ -2386,7 +2471,7 @@ retry_baser: + pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", + &its->phys_base, its_base_type_string[type], + val, tmp); +- free_pages((unsigned long)base, order); ++ its_free_pages(base, order); + return -ENXIO; + } + +@@ -2525,8 +2610,7 @@ static void its_free_tables(struct its_n + + for (i = 0; i < GITS_BASER_NR_REGS; i++) { + if (its->tables[i].base) { +- free_pages((unsigned long)its->tables[i].base, +- its->tables[i].order); ++ its_free_pages(its->tables[i].base, its->tables[i].order); + its->tables[i].base = NULL; + } + } +@@ -2792,7 +2876,7 @@ static bool allocate_vpe_l2_table(int cp + + /* Allocate memory for 2nd level table */ + if (!table[idx]) { +- page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz)); ++ page = its_alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz)); + if (!page) + return false; + +@@ -2911,7 +2995,7 @@ static int allocate_vpe_l1_table(void) + + pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n", + np, npg, psz, epp, esz); +- page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE)); ++ page = its_alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE)); + if (!page) + return -ENOMEM; + +@@ -2957,8 +3041,7 @@ static struct page *its_allocate_pending + { + struct page *pend_page; + +- pend_page = alloc_pages(gfp_flags | __GFP_ZERO, +- get_order(LPI_PENDBASE_SZ)); ++ pend_page = its_alloc_pages(gfp_flags | __GFP_ZERO, get_order(LPI_PENDBASE_SZ)); + if (!pend_page) + return NULL; + +@@ -2970,7 +3053,7 @@ static struct page *its_allocate_pending + + static void its_free_pending_table(struct page *pt) + { +- free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ)); ++ its_free_pages(page_address(pt), get_order(LPI_PENDBASE_SZ)); + } + + /* +@@ -3305,8 +3388,8 @@ static bool its_alloc_table_entry(struct + + /* Allocate memory for 2nd level table */ + if (!table[idx]) { +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, +- get_order(baser->psz)); ++ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, ++ get_order(baser->psz)); + if (!page) + return false; + +@@ -3401,7 +3484,6 @@ static struct its_device *its_create_dev + if (WARN_ON(!is_power_of_2(nvecs))) + nvecs = roundup_pow_of_two(nvecs); + +- dev = kzalloc(sizeof(*dev), GFP_KERNEL); + /* + * Even if the device wants a single LPI, the ITT must be + * sized as a power of two (and you need at least one bit...). +@@ -3409,7 +3491,11 @@ static struct its_device *its_create_dev + nr_ites = max(2, nvecs); + sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); + sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; +- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); ++ ++ itt = itt_alloc_pool(its->numa_node, sz); ++ ++ dev = kzalloc(sizeof(*dev), GFP_KERNEL); ++ + if (alloc_lpis) { + lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); + if (lpi_map) +@@ -3421,9 +3507,9 @@ static struct its_device *its_create_dev + lpi_base = 0; + } + +- if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { ++ if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { + kfree(dev); +- kfree(itt); ++ itt_free_pool(itt, sz); + bitmap_free(lpi_map); + kfree(col_map); + return NULL; +@@ -3433,6 +3519,7 @@ static struct its_device *its_create_dev + + dev->its = its; + dev->itt = itt; ++ dev->itt_sz = sz; + dev->nr_ites = nr_ites; + dev->event_map.lpi_map = lpi_map; + dev->event_map.col_map = col_map; +@@ -3460,7 +3547,7 @@ static void its_free_device(struct its_d + list_del(&its_dev->entry); + raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); + kfree(its_dev->event_map.col_map); +- kfree(its_dev->itt); ++ itt_free_pool(its_dev->itt, its_dev->itt_sz); + kfree(its_dev); + } + +@@ -5160,8 +5247,9 @@ static int __init its_probe_one(struct i + } + } + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, +- get_order(ITS_CMD_QUEUE_SZ)); ++ page = its_alloc_pages_node(its->numa_node, ++ GFP_KERNEL | __GFP_ZERO, ++ get_order(ITS_CMD_QUEUE_SZ)); + if (!page) { + err = -ENOMEM; + goto out_unmap_sgir; +@@ -5225,7 +5313,7 @@ static int __init its_probe_one(struct i + out_free_tables: + its_free_tables(its); + out_free_cmd: +- free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); ++ its_free_pages(its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); + out_unmap_sgir: + if (its->sgir_base) + iounmap(its->sgir_base); +@@ -5711,6 +5799,10 @@ int __init its_init(struct fwnode_handle + bool has_v4_1 = false; + int err; + ++ itt_pool = gen_pool_create(get_order(ITS_ITT_ALIGN), -1); ++ if (!itt_pool) ++ return -ENOMEM; ++ + gic_rdists = rdists; + + lpi_prop_prio = irq_prio; diff --git a/target/linux/rockchip/patches-6.12/030-02-v6.13-irqchip-gic-v3-its-Fix-over-allocation-in-itt_alloc.patch b/target/linux/rockchip/patches-6.12/030-02-v6.13-irqchip-gic-v3-its-Fix-over-allocation-in-itt_alloc.patch new file mode 100644 index 0000000000..6378534273 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/030-02-v6.13-irqchip-gic-v3-its-Fix-over-allocation-in-itt_alloc.patch @@ -0,0 +1,33 @@ +From bc88d44bd7e45b992cf8c2c2ffbc7bb3e24db4a7 Mon Sep 17 00:00:00 2001 +From: Steven Price +Date: Mon, 21 Oct 2024 11:41:05 +0100 +Subject: [PATCH] irqchip/gic-v3-its: Fix over allocation in + itt_alloc_pool() + +itt_alloc_pool() calls its_alloc_pages_node() to allocate an individual +page to add to the pool (for allocations +Signed-off-by: Steven Price +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/all/1f6e19c4-1fb9-43ab-a8a2-a465c9cff84b@arm.com +Closes: https://lore.kernel.org/r/ed65312a-245c-4fa5-91ad-5d620cab7c6b%40nvidia.com +--- + drivers/irqchip/irq-gic-v3-its.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -263,7 +263,7 @@ static void *itt_alloc_pool(int node, in + if (addr) + break; + +- page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1); ++ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 0); + if (!page) + break; + diff --git a/target/linux/rockchip/patches-6.12/030-03-v6.15-irqchip-gic-v3-Add-Rockchip-3568002-erratum-workaround.patch b/target/linux/rockchip/patches-6.12/030-03-v6.15-irqchip-gic-v3-Add-Rockchip-3568002-erratum-workaround.patch new file mode 100644 index 0000000000..17a4e528ca --- /dev/null +++ b/target/linux/rockchip/patches-6.12/030-03-v6.15-irqchip-gic-v3-Add-Rockchip-3568002-erratum-workaround.patch @@ -0,0 +1,105 @@ +From 2d81e1bb625238d40a686ed909ff3e1abab7556a Mon Sep 17 00:00:00 2001 +From: Dmitry Osipenko +Date: Mon, 17 Feb 2025 01:16:32 +0300 +Subject: [PATCH] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround + +Rockchip RK3566/RK3568 GIC600 integration has DDR addressing +limited to the first 32bit of physical address space. Rockchip +assigned Erratum ID #3568002 for this issue. Add driver quirk for +this Rockchip GIC Erratum. + +Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is +common for many ARM GICv3 implementations. Hence, there is an extra +of_machine_is_compatible() check. + +Signed-off-by: Dmitry Osipenko +Signed-off-by: Thomas Gleixner +Acked-by: Marc Zyngier +Link: https://lore.kernel.org/all/20250216221634.364158-2-dmitry.osipenko@collabora.com +--- + Documentation/arch/arm64/silicon-errata.rst | 2 ++ + arch/arm64/Kconfig | 9 ++++++++ + drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++++- + 3 files changed, 33 insertions(+), 1 deletion(-) + +--- a/Documentation/arch/arm64/silicon-errata.rst ++++ b/Documentation/arch/arm64/silicon-errata.rst +@@ -283,6 +283,8 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 | + +----------------+-----------------+-----------------+-----------------------------+ ++| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 | +++----------------+-----------------+-----------------+-----------------------------+ + +----------------+-----------------+-----------------+-----------------------------+ + | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | + +----------------+-----------------+-----------------+-----------------------------+ +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -1295,6 +1295,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM + + If unsure, say Y. + ++config ROCKCHIP_ERRATUM_3568002 ++ bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" ++ default y ++ help ++ The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI ++ addressing limited to the first 32bit of physical address space. ++ ++ If unsure, say Y. ++ + config ROCKCHIP_ERRATUM_3588001 + bool "Rockchip 3588001: GIC600 can not support shareability attributes" + default y +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -205,13 +205,15 @@ static DEFINE_IDA(its_vpeid_ida); + #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) + #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) + ++static gfp_t gfp_flags_quirk; ++ + static struct page *its_alloc_pages_node(int node, gfp_t gfp, + unsigned int order) + { + struct page *page; + int ret = 0; + +- page = alloc_pages_node(node, gfp, order); ++ page = alloc_pages_node(node, gfp | gfp_flags_quirk, order); + + if (!page) + return NULL; +@@ -4888,6 +4890,17 @@ static bool __maybe_unused its_enable_qu + return true; + } + ++static bool __maybe_unused its_enable_rk3568002(void *data) ++{ ++ if (!of_machine_is_compatible("rockchip,rk3566") && ++ !of_machine_is_compatible("rockchip,rk3568")) ++ return false; ++ ++ gfp_flags_quirk |= GFP_DMA32; ++ ++ return true; ++} ++ + static const struct gic_quirk its_quirks[] = { + #ifdef CONFIG_CAVIUM_ERRATUM_22375 + { +@@ -4955,6 +4968,14 @@ static const struct gic_quirk its_quirks + .property = "dma-noncoherent", + .init = its_set_non_coherent, + }, ++#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002 ++ { ++ .desc = "ITS: Rockchip erratum RK3568002", ++ .iidr = 0x0201743b, ++ .mask = 0xffffffff, ++ .init = its_enable_rk3568002, ++ }, ++#endif + { + } + }; diff --git a/target/linux/rockchip/patches-6.12/031-01-v6.15-dt-bindings-reset-Add-SCMI-reset-IDs-for-RK3588.patch b/target/linux/rockchip/patches-6.12/031-01-v6.15-dt-bindings-reset-Add-SCMI-reset-IDs-for-RK3588.patch new file mode 100644 index 0000000000..8f98680aea --- /dev/null +++ b/target/linux/rockchip/patches-6.12/031-01-v6.15-dt-bindings-reset-Add-SCMI-reset-IDs-for-RK3588.patch @@ -0,0 +1,74 @@ +From 849d9db170fc8a03ce9f64133a1d0cd46c135105 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 4 Feb 2025 16:35:46 +0100 +Subject: [PATCH] dt-bindings: reset: Add SCMI reset IDs for RK3588 + +When TF-A is used to assert/deassert the resets through SCMI, the +IDs communicated to it are different than the ones mainline Linux uses. + +Import the list of SCMI reset IDs from mainline TF-A so that devicetrees +can use these IDs more easily. + +Co-developed-by: XiaoDong Huang +Signed-off-by: XiaoDong Huang +Acked-by: Conor Dooley +Signed-off-by: Nicolas Frattaroli +Signed-off-by: Herbert Xu +--- + .../dt-bindings/reset/rockchip,rk3588-cru.h | 41 ++++++++++++++++++- + 1 file changed, 40 insertions(+), 1 deletion(-) + +--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h ++++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + /* +- * Copyright (c) 2021 Rockchip Electronics Co. Ltd. ++ * Copyright (c) 2021, 2024 Rockchip Electronics Co. Ltd. + * Copyright (c) 2022 Collabora Ltd. + * + * Author: Elaine Zhang +@@ -753,4 +753,43 @@ + + #define SRST_A_HDMIRX_BIU 660 + ++/* SCMI Secure Resets */ ++ ++/* Name=SECURE_SOFTRST_CON00,Offset=0xA00 */ ++#define SCMI_SRST_A_SECURE_NS_BIU 10 ++#define SCMI_SRST_H_SECURE_NS_BIU 11 ++#define SCMI_SRST_A_SECURE_S_BIU 12 ++#define SCMI_SRST_H_SECURE_S_BIU 13 ++#define SCMI_SRST_P_SECURE_S_BIU 14 ++#define SCMI_SRST_CRYPTO_CORE 15 ++/* Name=SECURE_SOFTRST_CON01,Offset=0xA04 */ ++#define SCMI_SRST_CRYPTO_PKA 16 ++#define SCMI_SRST_CRYPTO_RNG 17 ++#define SCMI_SRST_A_CRYPTO 18 ++#define SCMI_SRST_H_CRYPTO 19 ++#define SCMI_SRST_KEYLADDER_CORE 25 ++#define SCMI_SRST_KEYLADDER_RNG 26 ++#define SCMI_SRST_A_KEYLADDER 27 ++#define SCMI_SRST_H_KEYLADDER 28 ++#define SCMI_SRST_P_OTPC_S 29 ++#define SCMI_SRST_OTPC_S 30 ++#define SCMI_SRST_WDT_S 31 ++/* Name=SECURE_SOFTRST_CON02,Offset=0xA08 */ ++#define SCMI_SRST_T_WDT_S 32 ++#define SCMI_SRST_H_BOOTROM 33 ++#define SCMI_SRST_A_DCF 34 ++#define SCMI_SRST_P_DCF 35 ++#define SCMI_SRST_H_BOOTROM_NS 37 ++#define SCMI_SRST_P_KEYLADDER 46 ++#define SCMI_SRST_H_TRNG_S 47 ++/* Name=SECURE_SOFTRST_CON03,Offset=0xA0C */ ++#define SCMI_SRST_H_TRNG_NS 48 ++#define SCMI_SRST_D_SDMMC_BUFFER 49 ++#define SCMI_SRST_H_SDMMC 50 ++#define SCMI_SRST_H_SDMMC_BUFFER 51 ++#define SCMI_SRST_SDMMC 52 ++#define SCMI_SRST_P_TRNG_CHK 53 ++#define SCMI_SRST_TRNG_S 54 ++ ++ + #endif diff --git a/target/linux/rockchip/patches-6.12/031-02-v6.15-dt-bindings-rng-add-binding-for-Rockchip-RK3588-RNG.patch b/target/linux/rockchip/patches-6.12/031-02-v6.15-dt-bindings-rng-add-binding-for-Rockchip-RK3588-RNG.patch new file mode 100644 index 0000000000..cb7e15527b --- /dev/null +++ b/target/linux/rockchip/patches-6.12/031-02-v6.15-dt-bindings-rng-add-binding-for-Rockchip-RK3588-RNG.patch @@ -0,0 +1,91 @@ +From e00fc3d6e7c2d0b2ab5cf03a576df39cd94479aa Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 4 Feb 2025 16:35:47 +0100 +Subject: [PATCH] dt-bindings: rng: add binding for Rockchip RK3588 RNG + +The Rockchip RK3588 SoC has two hardware RNGs accessible to the +non-secure world: an RNG in the Crypto IP, and a standalone RNG that is +new to this SoC. + +Add a binding for this new standalone RNG. It is distinct hardware from +the existing rockchip,rk3568-rng, and therefore gets its own binding as +the two hardware IPs are unrelated other than both being made by the +same vendor. + +The RNG is capable of firing an interrupt when entropy is ready. + +The reset is optional, as the hardware does a power-on reset, and +functions without the software manually resetting it. + +Signed-off-by: Nicolas Frattaroli +Acked-by: Conor Dooley +Signed-off-by: Herbert Xu +--- + .../bindings/rng/rockchip,rk3588-rng.yaml | 60 +++++++++++++++++++ + MAINTAINERS | 1 + + 2 files changed, 61 insertions(+) + create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml +@@ -0,0 +1,60 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/rng/rockchip,rk3588-rng.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip RK3588 TRNG ++ ++description: True Random Number Generator on Rockchip RK3588 SoC ++ ++maintainers: ++ - Nicolas Frattaroli ++ ++properties: ++ compatible: ++ enum: ++ - rockchip,rk3588-rng ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: TRNG AHB clock ++ ++ interrupts: ++ maxItems: 1 ++ ++ resets: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - interrupts ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ #include ++ bus { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ rng@fe378000 { ++ compatible = "rockchip,rk3588-rng"; ++ reg = <0x0 0xfe378000 0x0 0x200>; ++ interrupts = ; ++ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; ++ resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; ++ status = "okay"; ++ }; ++ }; ++ ++... diff --git a/target/linux/rockchip/patches-6.12/031-03-v6.15-dt-bindings-rng-rockchip-rk3588-rng-Drop-unnecessary.patch b/target/linux/rockchip/patches-6.12/031-03-v6.15-dt-bindings-rng-rockchip-rk3588-rng-Drop-unnecessary.patch new file mode 100644 index 0000000000..1dde09f1af --- /dev/null +++ b/target/linux/rockchip/patches-6.12/031-03-v6.15-dt-bindings-rng-rockchip-rk3588-rng-Drop-unnecessary.patch @@ -0,0 +1,27 @@ +From 52b3b329d8e589575d16d8d9adbca9e08041ee82 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Fri, 7 Mar 2025 10:33:09 +0100 +Subject: [PATCH] dt-bindings: rng: rockchip,rk3588-rng: Drop unnecessary + status from example + +Device nodes are enabled by default, so no need for 'status = "okay"' in +the DTS example. + +Reviewed-by: Heiko Stuebner +Signed-off-by: Krzysztof Kozlowski +Acked-by: Rob Herring (Arm) +Signed-off-by: Herbert Xu +--- + Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml | 1 - + 1 file changed, 1 deletion(-) + +--- a/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml ++++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml +@@ -53,7 +53,6 @@ examples: + interrupts = ; + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; + resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; +- status = "okay"; + }; + }; + diff --git a/target/linux/rockchip/patches-6.12/031-04-v6.15-hwrng-rockchip-store-dev-pointer-in-driver-struct.patch b/target/linux/rockchip/patches-6.12/031-04-v6.15-hwrng-rockchip-store-dev-pointer-in-driver-struct.patch new file mode 100644 index 0000000000..2f14fcd888 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/031-04-v6.15-hwrng-rockchip-store-dev-pointer-in-driver-struct.patch @@ -0,0 +1,67 @@ +From 8bb8609293ff3d8998d75c8db605c0529e83bcd9 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 4 Feb 2025 16:35:48 +0100 +Subject: [PATCH] hwrng: rockchip - store dev pointer in driver struct + +The rockchip rng driver does a dance to store the dev pointer in the +hwrng's unsigned long "priv" member. However, since the struct hwrng +member of rk_rng is not a pointer, we can use container_of to get the +struct rk_rng instance from just the struct hwrng*, which means we don't +have to subvert what little there is in C of a type system and can +instead store a pointer to the device struct in the rk_rng itself. + +Signed-off-by: Nicolas Frattaroli +Signed-off-by: Herbert Xu +--- + drivers/char/hw_random/rockchip-rng.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/char/hw_random/rockchip-rng.c ++++ b/drivers/char/hw_random/rockchip-rng.c +@@ -54,6 +54,7 @@ struct rk_rng { + void __iomem *base; + int clk_num; + struct clk_bulk_data *clk_bulks; ++ struct device *dev; + }; + + /* The mask in the upper 16 bits determines the bits that are updated */ +@@ -70,8 +71,7 @@ static int rk_rng_init(struct hwrng *rng + /* start clocks */ + ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); + if (ret < 0) { +- dev_err((struct device *) rk_rng->rng.priv, +- "Failed to enable clks %d\n", ret); ++ dev_err(rk_rng->dev, "Failed to enable clocks: %d\n", ret); + return ret; + } + +@@ -105,7 +105,7 @@ static int rk_rng_read(struct hwrng *rng + u32 reg; + int ret = 0; + +- ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv); ++ ret = pm_runtime_resume_and_get(rk_rng->dev); + if (ret < 0) + return ret; + +@@ -122,8 +122,8 @@ static int rk_rng_read(struct hwrng *rng + /* Read random data stored in the registers */ + memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read); + out: +- pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv); +- pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv); ++ pm_runtime_mark_last_busy(rk_rng->dev); ++ pm_runtime_put_sync_autosuspend(rk_rng->dev); + + return (ret < 0) ? ret : to_read; + } +@@ -164,7 +164,7 @@ static int rk_rng_probe(struct platform_ + rk_rng->rng.cleanup = rk_rng_cleanup; + } + rk_rng->rng.read = rk_rng_read; +- rk_rng->rng.priv = (unsigned long) dev; ++ rk_rng->dev = dev; + rk_rng->rng.quality = 900; + + pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); diff --git a/target/linux/rockchip/patches-6.12/031-05-v6.15-hwrng-rockchip-eliminate-some-unnecessary-dereferenc.patch b/target/linux/rockchip/patches-6.12/031-05-v6.15-hwrng-rockchip-eliminate-some-unnecessary-dereferenc.patch new file mode 100644 index 0000000000..a3bdff9641 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/031-05-v6.15-hwrng-rockchip-eliminate-some-unnecessary-dereferenc.patch @@ -0,0 +1,42 @@ +From 24aaa42ed65c0811b598674a593fc653d643a7e6 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 4 Feb 2025 16:35:49 +0100 +Subject: [PATCH] hwrng: rockchip - eliminate some unnecessary dereferences + +Despite assigning a temporary variable the value of &pdev->dev early on +in the probe function, the probe function then continues to use this +construct when it could just use the local dev variable instead. + +Simplify this by using the local dev variable directly. + +Signed-off-by: Nicolas Frattaroli +Signed-off-by: Herbert Xu +--- + drivers/char/hw_random/rockchip-rng.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/char/hw_random/rockchip-rng.c ++++ b/drivers/char/hw_random/rockchip-rng.c +@@ -148,7 +148,7 @@ static int rk_rng_probe(struct platform_ + return dev_err_probe(dev, rk_rng->clk_num, + "Failed to get clks property\n"); + +- rst = devm_reset_control_array_get_exclusive(&pdev->dev); ++ rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n"); + +@@ -171,11 +171,11 @@ static int rk_rng_probe(struct platform_ + pm_runtime_use_autosuspend(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) +- return dev_err_probe(&pdev->dev, ret, "Runtime pm activation failed.\n"); ++ return dev_err_probe(dev, ret, "Runtime pm activation failed.\n"); + + ret = devm_hwrng_register(dev, &rk_rng->rng); + if (ret) +- return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n"); ++ return dev_err_probe(dev, ret, "Failed to register Rockchip hwrng\n"); + + return 0; + } diff --git a/target/linux/rockchip/patches-6.12/031-06-v6.15-hwrng-rockchip-add-support-for-rk3588-s-standalone-T.patch b/target/linux/rockchip/patches-6.12/031-06-v6.15-hwrng-rockchip-add-support-for-rk3588-s-standalone-T.patch new file mode 100644 index 0000000000..9ae621a54a --- /dev/null +++ b/target/linux/rockchip/patches-6.12/031-06-v6.15-hwrng-rockchip-add-support-for-rk3588-s-standalone-T.patch @@ -0,0 +1,422 @@ +From 8eff8eb83fc0ae8b5f76220e2bb8644d836e99ff Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 4 Feb 2025 16:35:50 +0100 +Subject: [PATCH] hwrng: rockchip - add support for rk3588's standalone TRNG + +The RK3588 SoC includes several TRNGs, one part of the Crypto IP block, +and the other one (referred to as "trngv1") as a standalone new IP. + +Add support for this new standalone TRNG to the driver by both +generalising it to support multiple different rockchip RNGs and then +implementing the required functionality for the new hardware. + +This work was partly based on the downstream vendor driver by Rockchip's +Lin Jinhan, which is why they are listed as a Co-author. + +While the hardware does support notifying the CPU with an IRQ when the +random data is ready, I've discovered while implementing the code to use +this interrupt that this results in significantly slower throughput of +the TRNG even when under heavy CPU load. I assume this is because with +only 32 bytes of data per invocation, the overhead of reinitialising a +completion, enabling the interrupt, sleeping and then triggering the +completion in the IRQ handler is way more expensive than busylooping. + +Speaking of busylooping, the poll interval for reading the ISTAT is an +atomic read with a delay of 0. In my testing, I've found that this gives +us the largest throughput, and it appears the random data is ready +pretty much the moment we begin polling, as increasing the poll delay +leads to a drop in throughput significant enough to not just be due to +the poll interval missing the ideal timing by a microsecond or two. + +According to downstream, the IP should take 1024 clock cycles to +generate 56 bits of random data, which at 150MHz should work out to +6.8us. I did not test whether the data really does take 256/56*6.8us +to arrive, though changing the readl to a __raw_readl makes no +difference in throughput, and this data does pass the rngtest FIPS +checks, so I'm not entirely sure what's going on but I presume it's got +something to do with the AHB bus speed and the memory barriers that +mainline's readl/writel functions insert. + +The only other current SoC that uses this new IP is the Rockchip RV1106, +but that SoC does not have mainline support as of the time of writing, +so we make no effort to declare it as supported for now. + +Co-developed-by: Lin Jinhan +Signed-off-by: Lin Jinhan +Signed-off-by: Nicolas Frattaroli +Signed-off-by: Herbert Xu +--- + drivers/char/hw_random/Kconfig | 3 +- + drivers/char/hw_random/rockchip-rng.c | 234 +++++++++++++++++++++++--- + 2 files changed, 216 insertions(+), 21 deletions(-) + +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -580,7 +580,8 @@ config HW_RANDOM_ROCKCHIP + default HW_RANDOM + help + This driver provides kernel-side support for the True Random Number +- Generator hardware found on some Rockchip SoC like RK3566 or RK3568. ++ Generator hardware found on some Rockchip SoCs like RK3566, RK3568 ++ or RK3588. + + To compile this driver as a module, choose M here: the + module will be called rockchip-rng. +--- a/drivers/char/hw_random/rockchip-rng.c ++++ b/drivers/char/hw_random/rockchip-rng.c +@@ -1,12 +1,14 @@ + // SPDX-License-Identifier: GPL-2.0 + /* +- * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC ++ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs + * + * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2022, Aurelien Jarno ++ * Copyright (c) 2025, Collabora Ltd. + * Authors: + * Lin Jinhan + * Aurelien Jarno ++ * Nicolas Frattaroli + */ + #include + #include +@@ -32,6 +34,9 @@ + */ + #define RK_RNG_SAMPLE_CNT 1000 + ++/* after how many bytes of output TRNGv1 implementations should be reseeded */ ++#define RK_TRNG_V1_AUTO_RESEED_CNT 16000 ++ + /* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */ + #define TRNG_RST_CTL 0x0004 + #define TRNG_RNG_CTL 0x0400 +@@ -49,25 +54,85 @@ + #define TRNG_RNG_SAMPLE_CNT 0x0404 + #define TRNG_RNG_DOUT 0x0410 + ++/* ++ * TRNG V1 register definitions ++ * The TRNG V1 IP is a stand-alone TRNG implementation (not part of a crypto IP) ++ * and can be found in the Rockchip RK3588 SoC ++ */ ++#define TRNG_V1_CTRL 0x0000 ++#define TRNG_V1_CTRL_NOP 0x00 ++#define TRNG_V1_CTRL_RAND 0x01 ++#define TRNG_V1_CTRL_SEED 0x02 ++ ++#define TRNG_V1_STAT 0x0004 ++#define TRNG_V1_STAT_SEEDED BIT(9) ++#define TRNG_V1_STAT_GENERATING BIT(30) ++#define TRNG_V1_STAT_RESEEDING BIT(31) ++ ++#define TRNG_V1_MODE 0x0008 ++#define TRNG_V1_MODE_128_BIT (0x00 << 3) ++#define TRNG_V1_MODE_256_BIT (0x01 << 3) ++ ++/* Interrupt Enable register; unused because polling is faster */ ++#define TRNG_V1_IE 0x0010 ++#define TRNG_V1_IE_GLBL_EN BIT(31) ++#define TRNG_V1_IE_SEED_DONE_EN BIT(1) ++#define TRNG_V1_IE_RAND_RDY_EN BIT(0) ++ ++#define TRNG_V1_ISTAT 0x0014 ++#define TRNG_V1_ISTAT_RAND_RDY BIT(0) ++ ++/* RAND0 ~ RAND7 */ ++#define TRNG_V1_RAND0 0x0020 ++#define TRNG_V1_RAND7 0x003C ++ ++/* Auto Reseed Register */ ++#define TRNG_V1_AUTO_RQSTS 0x0060 ++ ++#define TRNG_V1_VERSION 0x00F0 ++#define TRNG_v1_VERSION_CODE 0x46bc ++/* end of TRNG_V1 register definitions */ ++ ++/* Before removing this assert, give rk3588_rng_read an upper bound of 32 */ ++static_assert(RK_RNG_MAX_BYTE <= (TRNG_V1_RAND7 + 4 - TRNG_V1_RAND0), ++ "You raised RK_RNG_MAX_BYTE and broke rk3588-rng, congrats."); ++ + struct rk_rng { + struct hwrng rng; + void __iomem *base; + int clk_num; + struct clk_bulk_data *clk_bulks; ++ const struct rk_rng_soc_data *soc_data; + struct device *dev; + }; + ++struct rk_rng_soc_data { ++ int (*rk_rng_init)(struct hwrng *rng); ++ int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait); ++ void (*rk_rng_cleanup)(struct hwrng *rng); ++ unsigned short quality; ++ bool reset_optional; ++}; ++ + /* The mask in the upper 16 bits determines the bits that are updated */ + static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask) + { + writel((mask << 16) | val, rng->base + TRNG_RNG_CTL); + } + +-static int rk_rng_init(struct hwrng *rng) ++static inline void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset) + { +- struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); +- int ret; ++ writel(val, rng->base + offset); ++} + ++static inline u32 rk_rng_readl(struct rk_rng *rng, u32 offset) ++{ ++ return readl(rng->base + offset); ++} ++ ++static int rk_rng_enable_clks(struct rk_rng *rk_rng) ++{ ++ int ret; + /* start clocks */ + ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); + if (ret < 0) { +@@ -75,6 +140,18 @@ static int rk_rng_init(struct hwrng *rng + return ret; + } + ++ return 0; ++} ++ ++static int rk3568_rng_init(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ int ret; ++ ++ ret = rk_rng_enable_clks(rk_rng); ++ if (ret < 0) ++ return ret; ++ + /* set the sample period */ + writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); + +@@ -87,7 +164,7 @@ static int rk_rng_init(struct hwrng *rng + return 0; + } + +-static void rk_rng_cleanup(struct hwrng *rng) ++static void rk3568_rng_cleanup(struct hwrng *rng) + { + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); + +@@ -98,7 +175,7 @@ static void rk_rng_cleanup(struct hwrng + clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); + } + +-static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++static int rk3568_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) + { + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); + size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE); +@@ -128,6 +205,114 @@ out: + return (ret < 0) ? ret : to_read; + } + ++static int rk3588_rng_init(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 version, status, mask, istat; ++ int ret; ++ ++ ret = rk_rng_enable_clks(rk_rng); ++ if (ret < 0) ++ return ret; ++ ++ version = rk_rng_readl(rk_rng, TRNG_V1_VERSION); ++ if (version != TRNG_v1_VERSION_CODE) { ++ dev_err(rk_rng->dev, ++ "wrong trng version, expected = %08x, actual = %08x\n", ++ TRNG_V1_VERSION, version); ++ ret = -EFAULT; ++ goto err_disable_clk; ++ } ++ ++ mask = TRNG_V1_STAT_SEEDED | TRNG_V1_STAT_GENERATING | ++ TRNG_V1_STAT_RESEEDING; ++ if (readl_poll_timeout(rk_rng->base + TRNG_V1_STAT, status, ++ (status & mask) == TRNG_V1_STAT_SEEDED, ++ RK_RNG_POLL_PERIOD_US, RK_RNG_POLL_TIMEOUT_US) < 0) { ++ dev_err(rk_rng->dev, "timed out waiting for hwrng to reseed\n"); ++ ret = -ETIMEDOUT; ++ goto err_disable_clk; ++ } ++ ++ /* ++ * clear ISTAT flag, downstream advises to do this to avoid ++ * auto-reseeding "on power on" ++ */ ++ istat = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); ++ rk_rng_writel(rk_rng, istat, TRNG_V1_ISTAT); ++ ++ /* auto reseed after RK_TRNG_V1_AUTO_RESEED_CNT bytes */ ++ rk_rng_writel(rk_rng, RK_TRNG_V1_AUTO_RESEED_CNT / 16, TRNG_V1_AUTO_RQSTS); ++ ++ return 0; ++err_disable_clk: ++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); ++ return ret; ++} ++ ++static void rk3588_rng_cleanup(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); ++} ++ ++static int rk3588_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE); ++ int ret = 0; ++ u32 reg; ++ ++ ret = pm_runtime_resume_and_get(rk_rng->dev); ++ if (ret < 0) ++ return ret; ++ ++ /* Clear ISTAT, even without interrupts enabled, this will be updated */ ++ reg = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); ++ rk_rng_writel(rk_rng, reg, TRNG_V1_ISTAT); ++ ++ /* generate 256 bits of random data */ ++ rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE); ++ rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL); ++ ++ ret = readl_poll_timeout_atomic(rk_rng->base + TRNG_V1_ISTAT, reg, ++ (reg & TRNG_V1_ISTAT_RAND_RDY), 0, ++ RK_RNG_POLL_TIMEOUT_US); ++ if (ret < 0) ++ goto out; ++ ++ /* Read random data that's in registers TRNG_V1_RAND0 through RAND7 */ ++ memcpy_fromio(buf, rk_rng->base + TRNG_V1_RAND0, to_read); ++ ++out: ++ /* Clear ISTAT */ ++ rk_rng_writel(rk_rng, reg, TRNG_V1_ISTAT); ++ /* close the TRNG */ ++ rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL); ++ ++ pm_runtime_mark_last_busy(rk_rng->dev); ++ pm_runtime_put_sync_autosuspend(rk_rng->dev); ++ ++ return (ret < 0) ? ret : to_read; ++} ++ ++static const struct rk_rng_soc_data rk3568_soc_data = { ++ .rk_rng_init = rk3568_rng_init, ++ .rk_rng_read = rk3568_rng_read, ++ .rk_rng_cleanup = rk3568_rng_cleanup, ++ .quality = 900, ++ .reset_optional = false, ++}; ++ ++static const struct rk_rng_soc_data rk3588_soc_data = { ++ .rk_rng_init = rk3588_rng_init, ++ .rk_rng_read = rk3588_rng_read, ++ .rk_rng_cleanup = rk3588_rng_cleanup, ++ .quality = 999, /* as determined by actual testing */ ++ .reset_optional = true, ++}; ++ + static int rk_rng_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; +@@ -139,6 +324,7 @@ static int rk_rng_probe(struct platform_ + if (!rk_rng) + return -ENOMEM; + ++ rk_rng->soc_data = of_device_get_match_data(dev); + rk_rng->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rk_rng->base)) + return PTR_ERR(rk_rng->base); +@@ -148,24 +334,30 @@ static int rk_rng_probe(struct platform_ + return dev_err_probe(dev, rk_rng->clk_num, + "Failed to get clks property\n"); + +- rst = devm_reset_control_array_get_exclusive(dev); +- if (IS_ERR(rst)) +- return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n"); +- +- reset_control_assert(rst); +- udelay(2); +- reset_control_deassert(rst); ++ if (rk_rng->soc_data->reset_optional) ++ rst = devm_reset_control_array_get_optional_exclusive(dev); ++ else ++ rst = devm_reset_control_array_get_exclusive(dev); ++ ++ if (rst) { ++ if (IS_ERR(rst)) ++ return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n"); ++ ++ reset_control_assert(rst); ++ udelay(2); ++ reset_control_deassert(rst); ++ } + + platform_set_drvdata(pdev, rk_rng); + + rk_rng->rng.name = dev_driver_string(dev); + if (!IS_ENABLED(CONFIG_PM)) { +- rk_rng->rng.init = rk_rng_init; +- rk_rng->rng.cleanup = rk_rng_cleanup; ++ rk_rng->rng.init = rk_rng->soc_data->rk_rng_init; ++ rk_rng->rng.cleanup = rk_rng->soc_data->rk_rng_cleanup; + } +- rk_rng->rng.read = rk_rng_read; ++ rk_rng->rng.read = rk_rng->soc_data->rk_rng_read; + rk_rng->dev = dev; +- rk_rng->rng.quality = 900; ++ rk_rng->rng.quality = rk_rng->soc_data->quality; + + pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); + pm_runtime_use_autosuspend(dev); +@@ -184,7 +376,7 @@ static int __maybe_unused rk_rng_runtime + { + struct rk_rng *rk_rng = dev_get_drvdata(dev); + +- rk_rng_cleanup(&rk_rng->rng); ++ rk_rng->soc_data->rk_rng_cleanup(&rk_rng->rng); + + return 0; + } +@@ -193,7 +385,7 @@ static int __maybe_unused rk_rng_runtime + { + struct rk_rng *rk_rng = dev_get_drvdata(dev); + +- return rk_rng_init(&rk_rng->rng); ++ return rk_rng->soc_data->rk_rng_init(&rk_rng->rng); + } + + static const struct dev_pm_ops rk_rng_pm_ops = { +@@ -204,7 +396,8 @@ static const struct dev_pm_ops rk_rng_pm + }; + + static const struct of_device_id rk_rng_dt_match[] = { +- { .compatible = "rockchip,rk3568-rng", }, ++ { .compatible = "rockchip,rk3568-rng", .data = (void *)&rk3568_soc_data }, ++ { .compatible = "rockchip,rk3588-rng", .data = (void *)&rk3588_soc_data }, + { /* sentinel */ }, + }; + +@@ -221,8 +414,9 @@ static struct platform_driver rk_rng_dri + + module_platform_driver(rk_rng_driver); + +-MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver"); ++MODULE_DESCRIPTION("Rockchip True Random Number Generator driver"); + MODULE_AUTHOR("Lin Jinhan "); + MODULE_AUTHOR("Aurelien Jarno "); + MODULE_AUTHOR("Daniel Golle "); ++MODULE_AUTHOR("Nicolas Frattaroli "); + MODULE_LICENSE("GPL"); diff --git a/target/linux/rockchip/patches-6.12/055-16-v6.13-arm64-dts-rockchip-enable-USB3-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.12/055-16-v6.13-arm64-dts-rockchip-enable-USB3-on-NanoPC-T6.patch deleted file mode 100644 index f7686cd439..0000000000 --- a/target/linux/rockchip/patches-6.12/055-16-v6.13-arm64-dts-rockchip-enable-USB3-on-NanoPC-T6.patch +++ /dev/null @@ -1,87 +0,0 @@ -From a6ae420439dc47a58550a6e61e596e9dd1562caf Mon Sep 17 00:00:00 2001 -From: Rick Wertenbroek -Date: Wed, 6 Nov 2024 14:03:13 +0100 -Subject: [PATCH] arm64: dts: rockchip: enable USB3 on NanoPC-T6 - -Enable the USB3 port on FriendlyELEC NanoPC-T6. - -Signed-off-by: Rick Wertenbroek -Link: https://lore.kernel.org/r/20241106130314.1289055-1-rick.wertenbroek@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 36 +++++++++++++++++++ - 1 file changed, 36 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -159,6 +159,20 @@ - vin-supply = <&vcc5v0_sys>; - }; - -+ vbus5v0_usb: vbus5v0-usb-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb5v_pwren>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vbus5v0_usb"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -575,6 +589,10 @@ - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - -+ usb5v_pwren: usb5v_pwren { -+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; -@@ -973,6 +991,14 @@ - status = "okay"; - }; - -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ - &u2phy2_host { - status = "okay"; - }; -@@ -1012,6 +1038,11 @@ - }; - }; - -+&usbdp_phy1 { -+ phy-supply = <&vbus5v0_usb>; -+ status = "okay"; -+}; -+ - &usb_host0_ehci { - status = "okay"; - }; -@@ -1032,6 +1063,11 @@ - }; - }; - -+&usb_host1_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.12/057-03-v6.15-dt-bindings-reset-Add-SCMI-reset-IDs-for-RK3588.patch b/target/linux/rockchip/patches-6.12/057-03-v6.15-dt-bindings-reset-Add-SCMI-reset-IDs-for-RK3588.patch deleted file mode 100644 index 8f98680aea..0000000000 --- a/target/linux/rockchip/patches-6.12/057-03-v6.15-dt-bindings-reset-Add-SCMI-reset-IDs-for-RK3588.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 849d9db170fc8a03ce9f64133a1d0cd46c135105 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 4 Feb 2025 16:35:46 +0100 -Subject: [PATCH] dt-bindings: reset: Add SCMI reset IDs for RK3588 - -When TF-A is used to assert/deassert the resets through SCMI, the -IDs communicated to it are different than the ones mainline Linux uses. - -Import the list of SCMI reset IDs from mainline TF-A so that devicetrees -can use these IDs more easily. - -Co-developed-by: XiaoDong Huang -Signed-off-by: XiaoDong Huang -Acked-by: Conor Dooley -Signed-off-by: Nicolas Frattaroli -Signed-off-by: Herbert Xu ---- - .../dt-bindings/reset/rockchip,rk3588-cru.h | 41 ++++++++++++++++++- - 1 file changed, 40 insertions(+), 1 deletion(-) - ---- a/include/dt-bindings/reset/rockchip,rk3588-cru.h -+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h -@@ -1,6 +1,6 @@ - /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ - /* -- * Copyright (c) 2021 Rockchip Electronics Co. Ltd. -+ * Copyright (c) 2021, 2024 Rockchip Electronics Co. Ltd. - * Copyright (c) 2022 Collabora Ltd. - * - * Author: Elaine Zhang -@@ -753,4 +753,43 @@ - - #define SRST_A_HDMIRX_BIU 660 - -+/* SCMI Secure Resets */ -+ -+/* Name=SECURE_SOFTRST_CON00,Offset=0xA00 */ -+#define SCMI_SRST_A_SECURE_NS_BIU 10 -+#define SCMI_SRST_H_SECURE_NS_BIU 11 -+#define SCMI_SRST_A_SECURE_S_BIU 12 -+#define SCMI_SRST_H_SECURE_S_BIU 13 -+#define SCMI_SRST_P_SECURE_S_BIU 14 -+#define SCMI_SRST_CRYPTO_CORE 15 -+/* Name=SECURE_SOFTRST_CON01,Offset=0xA04 */ -+#define SCMI_SRST_CRYPTO_PKA 16 -+#define SCMI_SRST_CRYPTO_RNG 17 -+#define SCMI_SRST_A_CRYPTO 18 -+#define SCMI_SRST_H_CRYPTO 19 -+#define SCMI_SRST_KEYLADDER_CORE 25 -+#define SCMI_SRST_KEYLADDER_RNG 26 -+#define SCMI_SRST_A_KEYLADDER 27 -+#define SCMI_SRST_H_KEYLADDER 28 -+#define SCMI_SRST_P_OTPC_S 29 -+#define SCMI_SRST_OTPC_S 30 -+#define SCMI_SRST_WDT_S 31 -+/* Name=SECURE_SOFTRST_CON02,Offset=0xA08 */ -+#define SCMI_SRST_T_WDT_S 32 -+#define SCMI_SRST_H_BOOTROM 33 -+#define SCMI_SRST_A_DCF 34 -+#define SCMI_SRST_P_DCF 35 -+#define SCMI_SRST_H_BOOTROM_NS 37 -+#define SCMI_SRST_P_KEYLADDER 46 -+#define SCMI_SRST_H_TRNG_S 47 -+/* Name=SECURE_SOFTRST_CON03,Offset=0xA0C */ -+#define SCMI_SRST_H_TRNG_NS 48 -+#define SCMI_SRST_D_SDMMC_BUFFER 49 -+#define SCMI_SRST_H_SDMMC 50 -+#define SCMI_SRST_H_SDMMC_BUFFER 51 -+#define SCMI_SRST_SDMMC 52 -+#define SCMI_SRST_P_TRNG_CHK 53 -+#define SCMI_SRST_TRNG_S 54 -+ -+ - #endif diff --git a/target/linux/rockchip/patches-6.12/057-04-v6.15-dt-bindings-rng-add-binding-for-Rockchip-RK3588-RNG.patch b/target/linux/rockchip/patches-6.12/057-04-v6.15-dt-bindings-rng-add-binding-for-Rockchip-RK3588-RNG.patch deleted file mode 100644 index cb7e15527b..0000000000 --- a/target/linux/rockchip/patches-6.12/057-04-v6.15-dt-bindings-rng-add-binding-for-Rockchip-RK3588-RNG.patch +++ /dev/null @@ -1,91 +0,0 @@ -From e00fc3d6e7c2d0b2ab5cf03a576df39cd94479aa Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 4 Feb 2025 16:35:47 +0100 -Subject: [PATCH] dt-bindings: rng: add binding for Rockchip RK3588 RNG - -The Rockchip RK3588 SoC has two hardware RNGs accessible to the -non-secure world: an RNG in the Crypto IP, and a standalone RNG that is -new to this SoC. - -Add a binding for this new standalone RNG. It is distinct hardware from -the existing rockchip,rk3568-rng, and therefore gets its own binding as -the two hardware IPs are unrelated other than both being made by the -same vendor. - -The RNG is capable of firing an interrupt when entropy is ready. - -The reset is optional, as the hardware does a power-on reset, and -functions without the software manually resetting it. - -Signed-off-by: Nicolas Frattaroli -Acked-by: Conor Dooley -Signed-off-by: Herbert Xu ---- - .../bindings/rng/rockchip,rk3588-rng.yaml | 60 +++++++++++++++++++ - MAINTAINERS | 1 + - 2 files changed, 61 insertions(+) - create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml -@@ -0,0 +1,60 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/rng/rockchip,rk3588-rng.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip RK3588 TRNG -+ -+description: True Random Number Generator on Rockchip RK3588 SoC -+ -+maintainers: -+ - Nicolas Frattaroli -+ -+properties: -+ compatible: -+ enum: -+ - rockchip,rk3588-rng -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: TRNG AHB clock -+ -+ interrupts: -+ maxItems: 1 -+ -+ resets: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - interrupts -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ #include -+ bus { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ rng@fe378000 { -+ compatible = "rockchip,rk3588-rng"; -+ reg = <0x0 0xfe378000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; -+ resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; -+ status = "okay"; -+ }; -+ }; -+ -+... diff --git a/target/linux/rockchip/patches-6.12/057-05-v6.15-dt-bindings-rng-rockchip-rk3588-rng-Drop-unnecessary.patch b/target/linux/rockchip/patches-6.12/057-05-v6.15-dt-bindings-rng-rockchip-rk3588-rng-Drop-unnecessary.patch deleted file mode 100644 index 1dde09f1af..0000000000 --- a/target/linux/rockchip/patches-6.12/057-05-v6.15-dt-bindings-rng-rockchip-rk3588-rng-Drop-unnecessary.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 52b3b329d8e589575d16d8d9adbca9e08041ee82 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Fri, 7 Mar 2025 10:33:09 +0100 -Subject: [PATCH] dt-bindings: rng: rockchip,rk3588-rng: Drop unnecessary - status from example - -Device nodes are enabled by default, so no need for 'status = "okay"' in -the DTS example. - -Reviewed-by: Heiko Stuebner -Signed-off-by: Krzysztof Kozlowski -Acked-by: Rob Herring (Arm) -Signed-off-by: Herbert Xu ---- - Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml | 1 - - 1 file changed, 1 deletion(-) - ---- a/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml -+++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml -@@ -53,7 +53,6 @@ examples: - interrupts = ; - clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; - resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; -- status = "okay"; - }; - }; - diff --git a/target/linux/rockchip/patches-6.12/057-06-v6.15-hwrng-rockchip-store-dev-pointer-in-driver-struct.patch b/target/linux/rockchip/patches-6.12/057-06-v6.15-hwrng-rockchip-store-dev-pointer-in-driver-struct.patch deleted file mode 100644 index 2f14fcd888..0000000000 --- a/target/linux/rockchip/patches-6.12/057-06-v6.15-hwrng-rockchip-store-dev-pointer-in-driver-struct.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 8bb8609293ff3d8998d75c8db605c0529e83bcd9 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 4 Feb 2025 16:35:48 +0100 -Subject: [PATCH] hwrng: rockchip - store dev pointer in driver struct - -The rockchip rng driver does a dance to store the dev pointer in the -hwrng's unsigned long "priv" member. However, since the struct hwrng -member of rk_rng is not a pointer, we can use container_of to get the -struct rk_rng instance from just the struct hwrng*, which means we don't -have to subvert what little there is in C of a type system and can -instead store a pointer to the device struct in the rk_rng itself. - -Signed-off-by: Nicolas Frattaroli -Signed-off-by: Herbert Xu ---- - drivers/char/hw_random/rockchip-rng.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/char/hw_random/rockchip-rng.c -+++ b/drivers/char/hw_random/rockchip-rng.c -@@ -54,6 +54,7 @@ struct rk_rng { - void __iomem *base; - int clk_num; - struct clk_bulk_data *clk_bulks; -+ struct device *dev; - }; - - /* The mask in the upper 16 bits determines the bits that are updated */ -@@ -70,8 +71,7 @@ static int rk_rng_init(struct hwrng *rng - /* start clocks */ - ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); - if (ret < 0) { -- dev_err((struct device *) rk_rng->rng.priv, -- "Failed to enable clks %d\n", ret); -+ dev_err(rk_rng->dev, "Failed to enable clocks: %d\n", ret); - return ret; - } - -@@ -105,7 +105,7 @@ static int rk_rng_read(struct hwrng *rng - u32 reg; - int ret = 0; - -- ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv); -+ ret = pm_runtime_resume_and_get(rk_rng->dev); - if (ret < 0) - return ret; - -@@ -122,8 +122,8 @@ static int rk_rng_read(struct hwrng *rng - /* Read random data stored in the registers */ - memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read); - out: -- pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv); -- pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv); -+ pm_runtime_mark_last_busy(rk_rng->dev); -+ pm_runtime_put_sync_autosuspend(rk_rng->dev); - - return (ret < 0) ? ret : to_read; - } -@@ -164,7 +164,7 @@ static int rk_rng_probe(struct platform_ - rk_rng->rng.cleanup = rk_rng_cleanup; - } - rk_rng->rng.read = rk_rng_read; -- rk_rng->rng.priv = (unsigned long) dev; -+ rk_rng->dev = dev; - rk_rng->rng.quality = 900; - - pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); diff --git a/target/linux/rockchip/patches-6.12/057-07-v6.15-hwrng-rockchip-eliminate-some-unnecessary-dereferenc.patch b/target/linux/rockchip/patches-6.12/057-07-v6.15-hwrng-rockchip-eliminate-some-unnecessary-dereferenc.patch deleted file mode 100644 index a3bdff9641..0000000000 --- a/target/linux/rockchip/patches-6.12/057-07-v6.15-hwrng-rockchip-eliminate-some-unnecessary-dereferenc.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 24aaa42ed65c0811b598674a593fc653d643a7e6 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 4 Feb 2025 16:35:49 +0100 -Subject: [PATCH] hwrng: rockchip - eliminate some unnecessary dereferences - -Despite assigning a temporary variable the value of &pdev->dev early on -in the probe function, the probe function then continues to use this -construct when it could just use the local dev variable instead. - -Simplify this by using the local dev variable directly. - -Signed-off-by: Nicolas Frattaroli -Signed-off-by: Herbert Xu ---- - drivers/char/hw_random/rockchip-rng.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/char/hw_random/rockchip-rng.c -+++ b/drivers/char/hw_random/rockchip-rng.c -@@ -148,7 +148,7 @@ static int rk_rng_probe(struct platform_ - return dev_err_probe(dev, rk_rng->clk_num, - "Failed to get clks property\n"); - -- rst = devm_reset_control_array_get_exclusive(&pdev->dev); -+ rst = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(rst)) - return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n"); - -@@ -171,11 +171,11 @@ static int rk_rng_probe(struct platform_ - pm_runtime_use_autosuspend(dev); - ret = devm_pm_runtime_enable(dev); - if (ret) -- return dev_err_probe(&pdev->dev, ret, "Runtime pm activation failed.\n"); -+ return dev_err_probe(dev, ret, "Runtime pm activation failed.\n"); - - ret = devm_hwrng_register(dev, &rk_rng->rng); - if (ret) -- return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n"); -+ return dev_err_probe(dev, ret, "Failed to register Rockchip hwrng\n"); - - return 0; - } diff --git a/target/linux/rockchip/patches-6.12/057-08-v6.15-hwrng-rockchip-add-support-for-rk3588-s-standalone-T.patch b/target/linux/rockchip/patches-6.12/057-08-v6.15-hwrng-rockchip-add-support-for-rk3588-s-standalone-T.patch deleted file mode 100644 index 9ae621a54a..0000000000 --- a/target/linux/rockchip/patches-6.12/057-08-v6.15-hwrng-rockchip-add-support-for-rk3588-s-standalone-T.patch +++ /dev/null @@ -1,422 +0,0 @@ -From 8eff8eb83fc0ae8b5f76220e2bb8644d836e99ff Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 4 Feb 2025 16:35:50 +0100 -Subject: [PATCH] hwrng: rockchip - add support for rk3588's standalone TRNG - -The RK3588 SoC includes several TRNGs, one part of the Crypto IP block, -and the other one (referred to as "trngv1") as a standalone new IP. - -Add support for this new standalone TRNG to the driver by both -generalising it to support multiple different rockchip RNGs and then -implementing the required functionality for the new hardware. - -This work was partly based on the downstream vendor driver by Rockchip's -Lin Jinhan, which is why they are listed as a Co-author. - -While the hardware does support notifying the CPU with an IRQ when the -random data is ready, I've discovered while implementing the code to use -this interrupt that this results in significantly slower throughput of -the TRNG even when under heavy CPU load. I assume this is because with -only 32 bytes of data per invocation, the overhead of reinitialising a -completion, enabling the interrupt, sleeping and then triggering the -completion in the IRQ handler is way more expensive than busylooping. - -Speaking of busylooping, the poll interval for reading the ISTAT is an -atomic read with a delay of 0. In my testing, I've found that this gives -us the largest throughput, and it appears the random data is ready -pretty much the moment we begin polling, as increasing the poll delay -leads to a drop in throughput significant enough to not just be due to -the poll interval missing the ideal timing by a microsecond or two. - -According to downstream, the IP should take 1024 clock cycles to -generate 56 bits of random data, which at 150MHz should work out to -6.8us. I did not test whether the data really does take 256/56*6.8us -to arrive, though changing the readl to a __raw_readl makes no -difference in throughput, and this data does pass the rngtest FIPS -checks, so I'm not entirely sure what's going on but I presume it's got -something to do with the AHB bus speed and the memory barriers that -mainline's readl/writel functions insert. - -The only other current SoC that uses this new IP is the Rockchip RV1106, -but that SoC does not have mainline support as of the time of writing, -so we make no effort to declare it as supported for now. - -Co-developed-by: Lin Jinhan -Signed-off-by: Lin Jinhan -Signed-off-by: Nicolas Frattaroli -Signed-off-by: Herbert Xu ---- - drivers/char/hw_random/Kconfig | 3 +- - drivers/char/hw_random/rockchip-rng.c | 234 +++++++++++++++++++++++--- - 2 files changed, 216 insertions(+), 21 deletions(-) - ---- a/drivers/char/hw_random/Kconfig -+++ b/drivers/char/hw_random/Kconfig -@@ -580,7 +580,8 @@ config HW_RANDOM_ROCKCHIP - default HW_RANDOM - help - This driver provides kernel-side support for the True Random Number -- Generator hardware found on some Rockchip SoC like RK3566 or RK3568. -+ Generator hardware found on some Rockchip SoCs like RK3566, RK3568 -+ or RK3588. - - To compile this driver as a module, choose M here: the - module will be called rockchip-rng. ---- a/drivers/char/hw_random/rockchip-rng.c -+++ b/drivers/char/hw_random/rockchip-rng.c -@@ -1,12 +1,14 @@ - // SPDX-License-Identifier: GPL-2.0 - /* -- * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC -+ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs - * - * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2022, Aurelien Jarno -+ * Copyright (c) 2025, Collabora Ltd. - * Authors: - * Lin Jinhan - * Aurelien Jarno -+ * Nicolas Frattaroli - */ - #include - #include -@@ -32,6 +34,9 @@ - */ - #define RK_RNG_SAMPLE_CNT 1000 - -+/* after how many bytes of output TRNGv1 implementations should be reseeded */ -+#define RK_TRNG_V1_AUTO_RESEED_CNT 16000 -+ - /* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */ - #define TRNG_RST_CTL 0x0004 - #define TRNG_RNG_CTL 0x0400 -@@ -49,25 +54,85 @@ - #define TRNG_RNG_SAMPLE_CNT 0x0404 - #define TRNG_RNG_DOUT 0x0410 - -+/* -+ * TRNG V1 register definitions -+ * The TRNG V1 IP is a stand-alone TRNG implementation (not part of a crypto IP) -+ * and can be found in the Rockchip RK3588 SoC -+ */ -+#define TRNG_V1_CTRL 0x0000 -+#define TRNG_V1_CTRL_NOP 0x00 -+#define TRNG_V1_CTRL_RAND 0x01 -+#define TRNG_V1_CTRL_SEED 0x02 -+ -+#define TRNG_V1_STAT 0x0004 -+#define TRNG_V1_STAT_SEEDED BIT(9) -+#define TRNG_V1_STAT_GENERATING BIT(30) -+#define TRNG_V1_STAT_RESEEDING BIT(31) -+ -+#define TRNG_V1_MODE 0x0008 -+#define TRNG_V1_MODE_128_BIT (0x00 << 3) -+#define TRNG_V1_MODE_256_BIT (0x01 << 3) -+ -+/* Interrupt Enable register; unused because polling is faster */ -+#define TRNG_V1_IE 0x0010 -+#define TRNG_V1_IE_GLBL_EN BIT(31) -+#define TRNG_V1_IE_SEED_DONE_EN BIT(1) -+#define TRNG_V1_IE_RAND_RDY_EN BIT(0) -+ -+#define TRNG_V1_ISTAT 0x0014 -+#define TRNG_V1_ISTAT_RAND_RDY BIT(0) -+ -+/* RAND0 ~ RAND7 */ -+#define TRNG_V1_RAND0 0x0020 -+#define TRNG_V1_RAND7 0x003C -+ -+/* Auto Reseed Register */ -+#define TRNG_V1_AUTO_RQSTS 0x0060 -+ -+#define TRNG_V1_VERSION 0x00F0 -+#define TRNG_v1_VERSION_CODE 0x46bc -+/* end of TRNG_V1 register definitions */ -+ -+/* Before removing this assert, give rk3588_rng_read an upper bound of 32 */ -+static_assert(RK_RNG_MAX_BYTE <= (TRNG_V1_RAND7 + 4 - TRNG_V1_RAND0), -+ "You raised RK_RNG_MAX_BYTE and broke rk3588-rng, congrats."); -+ - struct rk_rng { - struct hwrng rng; - void __iomem *base; - int clk_num; - struct clk_bulk_data *clk_bulks; -+ const struct rk_rng_soc_data *soc_data; - struct device *dev; - }; - -+struct rk_rng_soc_data { -+ int (*rk_rng_init)(struct hwrng *rng); -+ int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait); -+ void (*rk_rng_cleanup)(struct hwrng *rng); -+ unsigned short quality; -+ bool reset_optional; -+}; -+ - /* The mask in the upper 16 bits determines the bits that are updated */ - static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask) - { - writel((mask << 16) | val, rng->base + TRNG_RNG_CTL); - } - --static int rk_rng_init(struct hwrng *rng) -+static inline void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset) - { -- struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -- int ret; -+ writel(val, rng->base + offset); -+} - -+static inline u32 rk_rng_readl(struct rk_rng *rng, u32 offset) -+{ -+ return readl(rng->base + offset); -+} -+ -+static int rk_rng_enable_clks(struct rk_rng *rk_rng) -+{ -+ int ret; - /* start clocks */ - ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); - if (ret < 0) { -@@ -75,6 +140,18 @@ static int rk_rng_init(struct hwrng *rng - return ret; - } - -+ return 0; -+} -+ -+static int rk3568_rng_init(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ int ret; -+ -+ ret = rk_rng_enable_clks(rk_rng); -+ if (ret < 0) -+ return ret; -+ - /* set the sample period */ - writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); - -@@ -87,7 +164,7 @@ static int rk_rng_init(struct hwrng *rng - return 0; - } - --static void rk_rng_cleanup(struct hwrng *rng) -+static void rk3568_rng_cleanup(struct hwrng *rng) - { - struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); - -@@ -98,7 +175,7 @@ static void rk_rng_cleanup(struct hwrng - clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); - } - --static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+static int rk3568_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) - { - struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); - size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE); -@@ -128,6 +205,114 @@ out: - return (ret < 0) ? ret : to_read; - } - -+static int rk3588_rng_init(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 version, status, mask, istat; -+ int ret; -+ -+ ret = rk_rng_enable_clks(rk_rng); -+ if (ret < 0) -+ return ret; -+ -+ version = rk_rng_readl(rk_rng, TRNG_V1_VERSION); -+ if (version != TRNG_v1_VERSION_CODE) { -+ dev_err(rk_rng->dev, -+ "wrong trng version, expected = %08x, actual = %08x\n", -+ TRNG_V1_VERSION, version); -+ ret = -EFAULT; -+ goto err_disable_clk; -+ } -+ -+ mask = TRNG_V1_STAT_SEEDED | TRNG_V1_STAT_GENERATING | -+ TRNG_V1_STAT_RESEEDING; -+ if (readl_poll_timeout(rk_rng->base + TRNG_V1_STAT, status, -+ (status & mask) == TRNG_V1_STAT_SEEDED, -+ RK_RNG_POLL_PERIOD_US, RK_RNG_POLL_TIMEOUT_US) < 0) { -+ dev_err(rk_rng->dev, "timed out waiting for hwrng to reseed\n"); -+ ret = -ETIMEDOUT; -+ goto err_disable_clk; -+ } -+ -+ /* -+ * clear ISTAT flag, downstream advises to do this to avoid -+ * auto-reseeding "on power on" -+ */ -+ istat = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); -+ rk_rng_writel(rk_rng, istat, TRNG_V1_ISTAT); -+ -+ /* auto reseed after RK_TRNG_V1_AUTO_RESEED_CNT bytes */ -+ rk_rng_writel(rk_rng, RK_TRNG_V1_AUTO_RESEED_CNT / 16, TRNG_V1_AUTO_RQSTS); -+ -+ return 0; -+err_disable_clk: -+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); -+ return ret; -+} -+ -+static void rk3588_rng_cleanup(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); -+} -+ -+static int rk3588_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE); -+ int ret = 0; -+ u32 reg; -+ -+ ret = pm_runtime_resume_and_get(rk_rng->dev); -+ if (ret < 0) -+ return ret; -+ -+ /* Clear ISTAT, even without interrupts enabled, this will be updated */ -+ reg = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); -+ rk_rng_writel(rk_rng, reg, TRNG_V1_ISTAT); -+ -+ /* generate 256 bits of random data */ -+ rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE); -+ rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL); -+ -+ ret = readl_poll_timeout_atomic(rk_rng->base + TRNG_V1_ISTAT, reg, -+ (reg & TRNG_V1_ISTAT_RAND_RDY), 0, -+ RK_RNG_POLL_TIMEOUT_US); -+ if (ret < 0) -+ goto out; -+ -+ /* Read random data that's in registers TRNG_V1_RAND0 through RAND7 */ -+ memcpy_fromio(buf, rk_rng->base + TRNG_V1_RAND0, to_read); -+ -+out: -+ /* Clear ISTAT */ -+ rk_rng_writel(rk_rng, reg, TRNG_V1_ISTAT); -+ /* close the TRNG */ -+ rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL); -+ -+ pm_runtime_mark_last_busy(rk_rng->dev); -+ pm_runtime_put_sync_autosuspend(rk_rng->dev); -+ -+ return (ret < 0) ? ret : to_read; -+} -+ -+static const struct rk_rng_soc_data rk3568_soc_data = { -+ .rk_rng_init = rk3568_rng_init, -+ .rk_rng_read = rk3568_rng_read, -+ .rk_rng_cleanup = rk3568_rng_cleanup, -+ .quality = 900, -+ .reset_optional = false, -+}; -+ -+static const struct rk_rng_soc_data rk3588_soc_data = { -+ .rk_rng_init = rk3588_rng_init, -+ .rk_rng_read = rk3588_rng_read, -+ .rk_rng_cleanup = rk3588_rng_cleanup, -+ .quality = 999, /* as determined by actual testing */ -+ .reset_optional = true, -+}; -+ - static int rk_rng_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -139,6 +324,7 @@ static int rk_rng_probe(struct platform_ - if (!rk_rng) - return -ENOMEM; - -+ rk_rng->soc_data = of_device_get_match_data(dev); - rk_rng->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(rk_rng->base)) - return PTR_ERR(rk_rng->base); -@@ -148,24 +334,30 @@ static int rk_rng_probe(struct platform_ - return dev_err_probe(dev, rk_rng->clk_num, - "Failed to get clks property\n"); - -- rst = devm_reset_control_array_get_exclusive(dev); -- if (IS_ERR(rst)) -- return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n"); -- -- reset_control_assert(rst); -- udelay(2); -- reset_control_deassert(rst); -+ if (rk_rng->soc_data->reset_optional) -+ rst = devm_reset_control_array_get_optional_exclusive(dev); -+ else -+ rst = devm_reset_control_array_get_exclusive(dev); -+ -+ if (rst) { -+ if (IS_ERR(rst)) -+ return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n"); -+ -+ reset_control_assert(rst); -+ udelay(2); -+ reset_control_deassert(rst); -+ } - - platform_set_drvdata(pdev, rk_rng); - - rk_rng->rng.name = dev_driver_string(dev); - if (!IS_ENABLED(CONFIG_PM)) { -- rk_rng->rng.init = rk_rng_init; -- rk_rng->rng.cleanup = rk_rng_cleanup; -+ rk_rng->rng.init = rk_rng->soc_data->rk_rng_init; -+ rk_rng->rng.cleanup = rk_rng->soc_data->rk_rng_cleanup; - } -- rk_rng->rng.read = rk_rng_read; -+ rk_rng->rng.read = rk_rng->soc_data->rk_rng_read; - rk_rng->dev = dev; -- rk_rng->rng.quality = 900; -+ rk_rng->rng.quality = rk_rng->soc_data->quality; - - pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); - pm_runtime_use_autosuspend(dev); -@@ -184,7 +376,7 @@ static int __maybe_unused rk_rng_runtime - { - struct rk_rng *rk_rng = dev_get_drvdata(dev); - -- rk_rng_cleanup(&rk_rng->rng); -+ rk_rng->soc_data->rk_rng_cleanup(&rk_rng->rng); - - return 0; - } -@@ -193,7 +385,7 @@ static int __maybe_unused rk_rng_runtime - { - struct rk_rng *rk_rng = dev_get_drvdata(dev); - -- return rk_rng_init(&rk_rng->rng); -+ return rk_rng->soc_data->rk_rng_init(&rk_rng->rng); - } - - static const struct dev_pm_ops rk_rng_pm_ops = { -@@ -204,7 +396,8 @@ static const struct dev_pm_ops rk_rng_pm - }; - - static const struct of_device_id rk_rng_dt_match[] = { -- { .compatible = "rockchip,rk3568-rng", }, -+ { .compatible = "rockchip,rk3568-rng", .data = (void *)&rk3568_soc_data }, -+ { .compatible = "rockchip,rk3588-rng", .data = (void *)&rk3588_soc_data }, - { /* sentinel */ }, - }; - -@@ -221,8 +414,9 @@ static struct platform_driver rk_rng_dri - - module_platform_driver(rk_rng_driver); - --MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver"); -+MODULE_DESCRIPTION("Rockchip True Random Number Generator driver"); - MODULE_AUTHOR("Lin Jinhan "); - MODULE_AUTHOR("Aurelien Jarno "); - MODULE_AUTHOR("Daniel Golle "); -+MODULE_AUTHOR("Nicolas Frattaroli "); - MODULE_LICENSE("GPL"); diff --git a/target/linux/rockchip/patches-6.12/057-09-v6.15-arm64-dts-rockchip-Add-rng-node-to-RK3588.patch b/target/linux/rockchip/patches-6.12/057-09-v6.15-arm64-dts-rockchip-Add-rng-node-to-RK3588.patch deleted file mode 100644 index 880c30d812..0000000000 --- a/target/linux/rockchip/patches-6.12/057-09-v6.15-arm64-dts-rockchip-Add-rng-node-to-RK3588.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 6ee0b9ad3995ee5fa229035c69013b7dd0d3634b Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Tue, 4 Feb 2025 16:35:51 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add rng node to RK3588 - -Add the RK3588's standalone hardware random number generator node to its -device tree, and enable it. - -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20250204-rk3588-trng-submission-v2-6-608172b6fd91@collabora.com -[changed reset-id to its numeric value while the constant makes its - way through the crypto tree] -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1938,6 +1938,14 @@ - status = "disabled"; - }; - -+ rng@fe378000 { -+ compatible = "rockchip,rk3588-rng"; -+ reg = <0x0 0xfe378000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; -+ resets = <&scmi_reset 48>; -+ }; -+ - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.12/057-10-v6.15-arm64-dts-rockchip-change-rng-reset-id-back-to-its-c.patch b/target/linux/rockchip/patches-6.12/057-10-v6.15-arm64-dts-rockchip-change-rng-reset-id-back-to-its-c.patch deleted file mode 100644 index 91045bc80e..0000000000 --- a/target/linux/rockchip/patches-6.12/057-10-v6.15-arm64-dts-rockchip-change-rng-reset-id-back-to-its-c.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 55a43c346d24434e46ef7fcc09a9df8179c346e4 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Sun, 16 Feb 2025 16:27:42 +0100 -Subject: [PATCH] arm64: dts: rockchip: change rng reset id back to its - constant value - -With the binding header now providing the SCMI_SRST_H_TRNG_NS constant, -switch back to it from the temporary numeric value. - -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1943,7 +1943,7 @@ - reg = <0x0 0xfe378000 0x0 0x200>; - interrupts = ; - clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; -- resets = <&scmi_reset 48>; -+ resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; - }; - - i2s0_8ch: i2s@fe470000 { diff --git a/target/linux/rockchip/patches-6.12/121-arm64-dts-rockchip-lower-mmc-speed-for-nanopc-t6.patch b/target/linux/rockchip/patches-6.12/121-arm64-dts-rockchip-lower-mmc-speed-for-nanopc-t6.patch index 0cd50bc74a..0080830f00 100644 --- a/target/linux/rockchip/patches-6.12/121-arm64-dts-rockchip-lower-mmc-speed-for-nanopc-t6.patch +++ b/target/linux/rockchip/patches-6.12/121-arm64-dts-rockchip-lower-mmc-speed-for-nanopc-t6.patch @@ -1,6 +1,16 @@ --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -632,7 +632,7 @@ +@@ -619,8 +619,7 @@ + no-sd; + non-removable; + max-frequency = <200000000>; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; ++ mmc-hs200-1_8v; + status = "okay"; + }; + +@@ -632,7 +631,7 @@ disable-wp; no-mmc; no-sdio; diff --git a/target/linux/rockchip/patches-6.12/127-arm64-dts-rockchip-rk3566-Add-Nanopi-R3S.patch b/target/linux/rockchip/patches-6.12/127-arm64-dts-rockchip-rk3566-Add-Nanopi-R3S.patch deleted file mode 100644 index 4f18677772..0000000000 --- a/target/linux/rockchip/patches-6.12/127-arm64-dts-rockchip-rk3566-Add-Nanopi-R3S.patch +++ /dev/null @@ -1,567 +0,0 @@ ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -0,0 +1,554 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd. -+ * -+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyelec.com) -+ * -+ * Copyright (c) 2024 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+#include -+#include -+#include "rk3566.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R3S"; -+ compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; -+ -+ aliases { -+ ethernet0 = &gmac1; -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc0; -+ }; -+ -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&reset_button_pin>; -+ -+ button-reset { -+ label = "reset"; -+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <50>; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>; -+ -+ power_led: led-0 { -+ color = ; -+ function = LED_FUNCTION_POWER; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ lan_led: led-1 { -+ color = ; -+ function = LED_FUNCTION_LAN; -+ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ wan_led: led-2 { -+ color = ; -+ function = LED_FUNCTION_WAN; -+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ vcc3v3_sys: regulator-vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: regulator-vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vdd_usbc>; -+ }; -+ -+ vcc5v0_usb: regulator-vcc5v0_usb { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_host_en>; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vdd_usbc: regulator-vdd-usbc { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_usbc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&combphy2 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; -+ assigned-clock-rates = <0>, <125000000>; -+ clock_in_out = "output"; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&rgmii_phy1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1m0_miim -+ &gmac1m0_tx_bus2_level3 -+ &gmac1m0_rx_bus2 -+ &gmac1m0_rgmii_clk_level2 -+ &gmac1m0_rgmii_bus_level3>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ system-power-controller; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <950000>; -+ regulator-max-microvolt = <950000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ wakeup-source; -+ }; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ interrupt-parent = <&gpio4>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <100000>; -+ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ power_led_pin: power-led-pin { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ gmac { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pcie { -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int: pmic-int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rtc { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_usb_host_en: vcc5v0-usb-host-en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_3v3>; -+ vccio5-supply = <&vcc_1v8>; -+ vccio6-supply = <&vcc_3v3>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ mmc-hs200-1_8v; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ no-sdio; -+ no-mmc; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ sd-uhs-sdr50; -+ vmmc-supply = <&vcc3v3_sd>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ extcon = <&usb2phy0>; -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-an - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-odroid-m1s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb diff --git a/target/linux/rockchip/patches-6.12/127-arm64-dts-rockchip-rk3566-Nanopi-R3S-update-LED.patch b/target/linux/rockchip/patches-6.12/127-arm64-dts-rockchip-rk3566-Nanopi-R3S-update-LED.patch new file mode 100644 index 0000000000..a7e95291de --- /dev/null +++ b/target/linux/rockchip/patches-6.12/127-arm64-dts-rockchip-rk3566-Nanopi-R3S-update-LED.patch @@ -0,0 +1,14 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts +@@ -24,6 +24,11 @@ + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; ++ ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; + }; + + chosen: chosen { diff --git a/target/linux/rockchip/patches-6.12/128-arm64-dts-rockchip-rk3566-Nanopi-R3S-update-LED.patch b/target/linux/rockchip/patches-6.12/128-arm64-dts-rockchip-rk3566-Nanopi-R3S-update-LED.patch deleted file mode 100644 index a7e95291de..0000000000 --- a/target/linux/rockchip/patches-6.12/128-arm64-dts-rockchip-rk3566-Nanopi-R3S-update-LED.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -24,6 +24,11 @@ - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc0; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen: chosen { diff --git a/target/linux/rockchip/patches-6.12/128-rock-4c-plus-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.12/128-rock-4c-plus-add-led-aliases-and-stop-heartbeat.patch new file mode 100644 index 0000000000..8106575a83 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/128-rock-4c-plus-add-led-aliases-and-stop-heartbeat.patch @@ -0,0 +1,27 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +@@ -17,6 +17,10 @@ + ethernet0 = &gmac; + mmc0 = &sdhci; + mmc1 = &sdmmc; ++ led-boot = &led_blue; ++ led-failsafe = &led_blue; ++ led-running = &led_blue; ++ led-upgrade = &led_blue; + }; + + chosen { +@@ -44,11 +48,11 @@ + }; + + /* USER_LED2 */ +- led-1 { ++ led_blue: led-1 { + function = LED_FUNCTION_STATUS; + color = ; ++ default-state = "on"; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + }; + diff --git a/target/linux/rockchip/patches-6.12/129-rock-4c-plus-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.12/129-rock-4c-plus-add-led-aliases-and-stop-heartbeat.patch deleted file mode 100644 index 8106575a83..0000000000 --- a/target/linux/rockchip/patches-6.12/129-rock-4c-plus-add-led-aliases-and-stop-heartbeat.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts -@@ -17,6 +17,10 @@ - ethernet0 = &gmac; - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ led-boot = &led_blue; -+ led-failsafe = &led_blue; -+ led-running = &led_blue; -+ led-upgrade = &led_blue; - }; - - chosen { -@@ -44,11 +48,11 @@ - }; - - /* USER_LED2 */ -- led-1 { -+ led_blue: led-1 { - function = LED_FUNCTION_STATUS; - color = ; -+ default-state = "on"; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - diff --git a/target/linux/rockchip/patches-6.12/129-rock-4se-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.12/129-rock-4se-add-led-aliases-and-stop-heartbeat.patch new file mode 100644 index 0000000000..7a02459683 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/129-rock-4se-add-led-aliases-and-stop-heartbeat.patch @@ -0,0 +1,27 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +@@ -13,6 +13,10 @@ + ethernet0 = &gmac; + mmc0 = &sdhci; + mmc1 = &sdmmc; ++ led-boot = &led_blue; ++ led-failsafe = &led_blue; ++ led-running = &led_blue; ++ led-upgrade = &led_blue; + }; + + chosen { +@@ -32,11 +36,11 @@ + pinctrl-0 = <&user_led2>; + + /* USER_LED2 */ +- led-0 { ++ led_blue: led-0 { + function = LED_FUNCTION_STATUS; + color = ; ++ default-state = "on"; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + }; + diff --git a/target/linux/rockchip/patches-6.12/130-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5-ITX.patch b/target/linux/rockchip/patches-6.12/130-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5-ITX.patch new file mode 100644 index 0000000000..b35c09200f --- /dev/null +++ b/target/linux/rockchip/patches-6.12/130-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5-ITX.patch @@ -0,0 +1,30 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +@@ -23,6 +23,10 @@ + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; + }; + + chosen { +@@ -62,12 +66,14 @@ + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + +- power-led1 { ++ power_led: power-led1 { ++ default-state = "on"; ++ function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "default-on"; + }; + + hdd-led2 { ++ function = LED_FUNCTION_DISK; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; diff --git a/target/linux/rockchip/patches-6.12/130-rock-4se-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.12/130-rock-4se-add-led-aliases-and-stop-heartbeat.patch deleted file mode 100644 index 7a02459683..0000000000 --- a/target/linux/rockchip/patches-6.12/130-rock-4se-add-led-aliases-and-stop-heartbeat.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -13,6 +13,10 @@ - ethernet0 = &gmac; - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ led-boot = &led_blue; -+ led-failsafe = &led_blue; -+ led-running = &led_blue; -+ led-upgrade = &led_blue; - }; - - chosen { -@@ -32,11 +36,11 @@ - pinctrl-0 = <&user_led2>; - - /* USER_LED2 */ -- led-0 { -+ led_blue: led-0 { - function = LED_FUNCTION_STATUS; - color = ; -+ default-state = "on"; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - diff --git a/target/linux/rockchip/patches-6.12/131-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5C.patch b/target/linux/rockchip/patches-6.12/131-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5C.patch new file mode 100644 index 0000000000..fadc372e71 --- /dev/null +++ b/target/linux/rockchip/patches-6.12/131-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5C.patch @@ -0,0 +1,33 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +@@ -19,6 +19,10 @@ + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; ++ led-boot = &led_green; ++ led-failsafe = &led_green; ++ led-running = &led_green; ++ led-upgrade = &led_green; + }; + + chosen { +@@ -52,7 +56,7 @@ + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + +- led-0 { ++ led_green: led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_POWER; +@@ -61,10 +65,8 @@ + + led-1 { + color = ; +- default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + }; + diff --git a/target/linux/rockchip/patches-6.12/131-arm64-dts-rockchip-rk3588-fix-A3A444-nanopc-t6.patch b/target/linux/rockchip/patches-6.12/131-arm64-dts-rockchip-rk3588-fix-A3A444-nanopc-t6.patch deleted file mode 100644 index 067310639a..0000000000 --- a/target/linux/rockchip/patches-6.12/131-arm64-dts-rockchip-rk3588-fix-A3A444-nanopc-t6.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Grzegorz Sterniczuk -Date: Mon, 21 Jul 2025 23:24:11 +0200 -Subject: rockchip: fix eMMC corruption on NanoPC-T6 with A3A444 chips - -Some NanoPC-T6 boards with A3A444 eMMC chips experience I/O errors and -corruption when using HS400 mode. Downgrade to HS200 mode to ensure -stable operation. - -Fixes: #18844 -Signed-off-by: Grzegorz Sterniczuk ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -619,8 +619,7 @@ - no-sd; - non-removable; - max-frequency = <200000000>; -- mmc-hs400-1_8v; -- mmc-hs400-enhanced-strobe; -+ mmc-hs200-1_8v; - status = "okay"; - }; - diff --git a/target/linux/rockchip/patches-6.12/132-arm64-dts-rockchip-Update-LED-properties-for-Radxa-E52C.patch b/target/linux/rockchip/patches-6.12/132-arm64-dts-rockchip-Update-LED-properties-for-Radxa-E52C.patch new file mode 100644 index 0000000000..7a1c79ba5c --- /dev/null +++ b/target/linux/rockchip/patches-6.12/132-arm64-dts-rockchip-Update-LED-properties-for-Radxa-E52C.patch @@ -0,0 +1,43 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts +@@ -19,6 +19,10 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; ++ led-boot = &led_green; ++ led-failsafe = &led_green; ++ led-running = &led_green; ++ led-upgrade = &led_green; + }; + + chosen { +@@ -57,12 +61,11 @@ + pinctrl-names = "default"; + pinctrl-0 = <&led_0>; + +- led-0 { ++ led_green: led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + }; + +@@ -71,7 +74,6 @@ + + led-1 { + color = ; +- default-state = "on"; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>; +@@ -80,7 +82,6 @@ + + led-2 { + color = ; +- default-state = "on"; + function = LED_FUNCTION_WAN; + linux,default-trigger = "netdev"; + pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>; diff --git a/target/linux/rockchip/patches-6.12/132-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5-ITX.patch b/target/linux/rockchip/patches-6.12/132-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5-ITX.patch deleted file mode 100644 index b35c09200f..0000000000 --- a/target/linux/rockchip/patches-6.12/132-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5-ITX.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -@@ -23,6 +23,10 @@ - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen { -@@ -62,12 +66,14 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - -- power-led1 { -+ power_led: power-led1 { -+ default-state = "on"; -+ function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "default-on"; - }; - - hdd-led2 { -+ function = LED_FUNCTION_DISK; - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; diff --git a/target/linux/rockchip/patches-6.12/133-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5C.patch b/target/linux/rockchip/patches-6.12/133-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5C.patch deleted file mode 100644 index fadc372e71..0000000000 --- a/target/linux/rockchip/patches-6.12/133-arm64-dts-rockchip-Update-LED-properties-for-Radxa-ROCK-5C.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -@@ -19,6 +19,10 @@ - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ led-boot = &led_green; -+ led-failsafe = &led_green; -+ led-running = &led_green; -+ led-upgrade = &led_green; - }; - - chosen { -@@ -52,7 +56,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - -- led-0 { -+ led_green: led-0 { - color = ; - default-state = "on"; - function = LED_FUNCTION_POWER; -@@ -61,10 +65,8 @@ - - led-1 { - color = ; -- default-state = "on"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - diff --git a/target/linux/rockchip/patches-6.12/134-arm64-dts-rockchip-Update-LED-properties-for-Radxa-E52C.patch b/target/linux/rockchip/patches-6.12/134-arm64-dts-rockchip-Update-LED-properties-for-Radxa-E52C.patch deleted file mode 100644 index 7a1c79ba5c..0000000000 --- a/target/linux/rockchip/patches-6.12/134-arm64-dts-rockchip-Update-LED-properties-for-Radxa-E52C.patch +++ /dev/null @@ -1,43 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts -@@ -19,6 +19,10 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -+ led-boot = &led_green; -+ led-failsafe = &led_green; -+ led-running = &led_green; -+ led-upgrade = &led_green; - }; - - chosen { -@@ -57,12 +61,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_0>; - -- led-0 { -+ led_green: led-0 { - color = ; - default-state = "on"; - function = LED_FUNCTION_STATUS; - gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - }; - -@@ -71,7 +74,6 @@ - - led-1 { - color = ; -- default-state = "on"; - function = LED_FUNCTION_LAN; - linux,default-trigger = "netdev"; - pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>; -@@ -80,7 +82,6 @@ - - led-2 { - color = ; -- default-state = "on"; - function = LED_FUNCTION_WAN; - linux,default-trigger = "netdev"; - pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>;