From: Christian Marangi Date: Fri, 24 Oct 2025 10:15:27 +0000 (+0200) Subject: airoha: backport cleanup patch for Airoha Ethernet driver X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=2f3ea18f9163ce2d287f76e0079f10580e01bd59;p=openwrt%2Fstaging%2Fblocktrron.git airoha: backport cleanup patch for Airoha Ethernet driver Backport cleanup patch for Airoha Ethernet patch to permit easier backport in the future. Automatically refresh all affected patch. Signed-off-by: Christian Marangi --- diff --git a/target/linux/airoha/patches-6.12/103-v6.19-net-airoha-Remove-code-duplication-in-airoha_regs.h.patch b/target/linux/airoha/patches-6.12/103-v6.19-net-airoha-Remove-code-duplication-in-airoha_regs.h.patch new file mode 100644 index 0000000000..654f287b14 --- /dev/null +++ b/target/linux/airoha/patches-6.12/103-v6.19-net-airoha-Remove-code-duplication-in-airoha_regs.h.patch @@ -0,0 +1,342 @@ +From 99ad2b6815f41acbec15ab051ccc79b11b05710a Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Wed, 22 Oct 2025 09:11:12 +0200 +Subject: [PATCH] net: airoha: Remove code duplication in airoha_regs.h + +This patch does not introduce any logical change, it just removes +duplicated code in airoha_regs.h. +Fix naming conventions in airoha_regs.h. + +Reviewed-by: Simon Horman +Signed-off-by: Lorenzo Bianconi +Link: https://patch.msgid.link/20251022-airoha-regs-cosmetics-v2-1-e0425b3f2c2c@kernel.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/airoha/airoha_eth.c | 102 ++++++++++---------- + drivers/net/ethernet/airoha/airoha_regs.h | 109 ++++++++++------------ + 2 files changed, 100 insertions(+), 111 deletions(-) + +--- a/drivers/net/ethernet/airoha/airoha_eth.c ++++ b/drivers/net/ethernet/airoha/airoha_eth.c +@@ -137,11 +137,11 @@ static void airoha_fe_maccr_init(struct + + for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) + airoha_fe_set(eth, REG_GDM_FWD_CFG(p), +- GDM_TCP_CKSUM | GDM_UDP_CKSUM | GDM_IP4_CKSUM | +- GDM_DROP_CRC_ERR); ++ GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK | ++ GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK); + +- airoha_fe_rmw(eth, REG_CDM1_VLAN_CTRL, CDM1_VLAN_MASK, +- FIELD_PREP(CDM1_VLAN_MASK, 0x8100)); ++ airoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK, ++ FIELD_PREP(CDM_VLAN_MASK, 0x8100)); + + airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); + } +@@ -403,46 +403,46 @@ static int airoha_fe_mc_vlan_clear(struc + static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) + { + /* CDM1_CRSN_QSEL */ +- airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_22 >> 2), +- CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), +- FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_22), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), + CDM_CRSN_QSEL_Q1)); +- airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_08 >> 2), +- CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), +- FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_08), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), + CDM_CRSN_QSEL_Q1)); +- airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_21 >> 2), +- CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), +- FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_21), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), + CDM_CRSN_QSEL_Q1)); +- airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_24 >> 2), +- CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), +- FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_24), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), + CDM_CRSN_QSEL_Q6)); +- airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_25 >> 2), +- CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), +- FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_25), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), + CDM_CRSN_QSEL_Q1)); + /* CDM2_CRSN_QSEL */ +- airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_08 >> 2), +- CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), +- FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_08), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), + CDM_CRSN_QSEL_Q1)); +- airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_21 >> 2), +- CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), +- FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_21), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), + CDM_CRSN_QSEL_Q1)); +- airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_22 >> 2), +- CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), +- FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_22), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), + CDM_CRSN_QSEL_Q1)); +- airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_24 >> 2), +- CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), +- FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_24), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), + CDM_CRSN_QSEL_Q6)); +- airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_25 >> 2), +- CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), +- FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), ++ airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 >> 2), ++ CDM_CRSN_QSEL_REASON_MASK(CRSN_25), ++ FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), + CDM_CRSN_QSEL_Q1)); + } + +@@ -462,18 +462,18 @@ static int airoha_fe_init(struct airoha_ + airoha_fe_wr(eth, REG_FE_PCE_CFG, + PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK); + /* set vip queue selection to ring 1 */ +- airoha_fe_rmw(eth, REG_CDM1_FWD_CFG, CDM1_VIP_QSEL_MASK, +- FIELD_PREP(CDM1_VIP_QSEL_MASK, 0x4)); +- airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_VIP_QSEL_MASK, +- FIELD_PREP(CDM2_VIP_QSEL_MASK, 0x4)); ++ airoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK, ++ FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); ++ airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK, ++ FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); + /* set GDM4 source interface offset to 8 */ +- airoha_fe_rmw(eth, REG_GDM4_SRC_PORT_SET, +- GDM4_SPORT_OFF2_MASK | +- GDM4_SPORT_OFF1_MASK | +- GDM4_SPORT_OFF0_MASK, +- FIELD_PREP(GDM4_SPORT_OFF2_MASK, 8) | +- FIELD_PREP(GDM4_SPORT_OFF1_MASK, 8) | +- FIELD_PREP(GDM4_SPORT_OFF0_MASK, 8)); ++ airoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4), ++ GDM_SPORT_OFF2_MASK | ++ GDM_SPORT_OFF1_MASK | ++ GDM_SPORT_OFF0_MASK, ++ FIELD_PREP(GDM_SPORT_OFF2_MASK, 8) | ++ FIELD_PREP(GDM_SPORT_OFF1_MASK, 8) | ++ FIELD_PREP(GDM_SPORT_OFF0_MASK, 8)); + + /* set PSE Page as 128B */ + airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, +@@ -499,8 +499,8 @@ static int airoha_fe_init(struct airoha_ + airoha_fe_set(eth, REG_GDM_MISC_CFG, + GDM2_RDM_ACK_WAIT_PREF_MASK | + GDM2_CHN_VLD_MODE_MASK); +- airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_OAM_QSEL_MASK, +- FIELD_PREP(CDM2_OAM_QSEL_MASK, 15)); ++ airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK, ++ FIELD_PREP(CDM_OAM_QSEL_MASK, 15)); + + /* init fragment and assemble Force Port */ + /* NPU Core-3, NPU Bridge Channel-3 */ +@@ -514,8 +514,8 @@ static int airoha_fe_init(struct airoha_ + FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | + FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); + +- airoha_fe_set(eth, REG_GDM3_FWD_CFG, GDM3_PAD_EN_MASK); +- airoha_fe_set(eth, REG_GDM4_FWD_CFG, GDM4_PAD_EN_MASK); ++ airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN_MASK); ++ airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN_MASK); + + airoha_fe_crsn_qsel_init(eth); + +@@ -523,7 +523,7 @@ static int airoha_fe_init(struct airoha_ + airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); + + /* default aging mode for mbi unlock issue */ +- airoha_fe_rmw(eth, REG_GDM2_CHN_RLS, ++ airoha_fe_rmw(eth, REG_GDM_CHN_RLS(2), + MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, + FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | + FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); +@@ -1697,7 +1697,7 @@ static int airhoha_set_gdm2_loopback(str + pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 + : FE_PSE_PORT_GDM4; + airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port); +- airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC); ++ airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC_MASK); + + /* Enable GDM2 loopback */ + airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff); +--- a/drivers/net/ethernet/airoha/airoha_regs.h ++++ b/drivers/net/ethernet/airoha/airoha_regs.h +@@ -23,6 +23,8 @@ + #define GDM3_BASE 0x1100 + #define GDM4_BASE 0x2500 + ++#define CDM_BASE(_n) \ ++ ((_n) == 2 ? CDM2_BASE : CDM1_BASE) + #define GDM_BASE(_n) \ + ((_n) == 4 ? GDM4_BASE : \ + (_n) == 3 ? GDM3_BASE : \ +@@ -109,30 +111,24 @@ + #define PATN_DP_MASK GENMASK(31, 16) + #define PATN_SP_MASK GENMASK(15, 0) + +-#define REG_CDM1_VLAN_CTRL CDM1_BASE +-#define CDM1_VLAN_MASK GENMASK(31, 16) ++#define REG_CDM_VLAN_CTRL(_n) CDM_BASE(_n) ++#define CDM_VLAN_MASK GENMASK(31, 16) + +-#define REG_CDM1_FWD_CFG (CDM1_BASE + 0x08) +-#define CDM1_VIP_QSEL_MASK GENMASK(24, 20) ++#define REG_CDM_FWD_CFG(_n) (CDM_BASE(_n) + 0x08) ++#define CDM_OAM_QSEL_MASK GENMASK(31, 27) ++#define CDM_VIP_QSEL_MASK GENMASK(24, 20) + +-#define REG_CDM1_CRSN_QSEL(_n) (CDM1_BASE + 0x10 + ((_n) << 2)) +-#define CDM1_CRSN_QSEL_REASON_MASK(_n) \ +- GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3)) +- +-#define REG_CDM2_FWD_CFG (CDM2_BASE + 0x08) +-#define CDM2_OAM_QSEL_MASK GENMASK(31, 27) +-#define CDM2_VIP_QSEL_MASK GENMASK(24, 20) +- +-#define REG_CDM2_CRSN_QSEL(_n) (CDM2_BASE + 0x10 + ((_n) << 2)) +-#define CDM2_CRSN_QSEL_REASON_MASK(_n) \ ++#define REG_CDM_CRSN_QSEL(_n, _m) (CDM_BASE(_n) + 0x10 + ((_m) << 2)) ++#define CDM_CRSN_QSEL_REASON_MASK(_n) \ + GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3)) + + #define REG_GDM_FWD_CFG(_n) GDM_BASE(_n) +-#define GDM_DROP_CRC_ERR BIT(23) +-#define GDM_IP4_CKSUM BIT(22) +-#define GDM_TCP_CKSUM BIT(21) +-#define GDM_UDP_CKSUM BIT(20) +-#define GDM_STRIP_CRC BIT(16) ++#define GDM_PAD_EN_MASK BIT(28) ++#define GDM_DROP_CRC_ERR_MASK BIT(23) ++#define GDM_IP4_CKSUM_MASK BIT(22) ++#define GDM_TCP_CKSUM_MASK BIT(21) ++#define GDM_UDP_CKSUM_MASK BIT(20) ++#define GDM_STRIP_CRC_MASK BIT(16) + #define GDM_UCFQ_MASK GENMASK(15, 12) + #define GDM_BCFQ_MASK GENMASK(11, 8) + #define GDM_MCFQ_MASK GENMASK(7, 4) +@@ -156,6 +152,10 @@ + #define LBK_CHAN_MODE_MASK BIT(1) + #define LPBK_EN_MASK BIT(0) + ++#define REG_GDM_CHN_RLS(_n) (GDM_BASE(_n) + 0x20) ++#define MBI_RX_AGE_SEL_MASK GENMASK(26, 25) ++#define MBI_TX_AGE_SEL_MASK GENMASK(18, 17) ++ + #define REG_GDM_TXCHN_EN(_n) (GDM_BASE(_n) + 0x24) + #define REG_GDM_RXCHN_EN(_n) (GDM_BASE(_n) + 0x28) + +@@ -168,10 +168,10 @@ + #define FE_GDM_MIB_RX_CLEAR_MASK BIT(1) + #define FE_GDM_MIB_TX_CLEAR_MASK BIT(0) + +-#define REG_FE_GDM1_MIB_CFG (GDM1_BASE + 0xf4) ++#define REG_FE_GDM_MIB_CFG(_n) (GDM_BASE(_n) + 0xf4) + #define FE_STRICT_RFC2819_MODE_MASK BIT(31) +-#define FE_GDM1_TX_MIB_SPLIT_EN_MASK BIT(17) +-#define FE_GDM1_RX_MIB_SPLIT_EN_MASK BIT(16) ++#define FE_GDM_TX_MIB_SPLIT_EN_MASK BIT(17) ++#define FE_GDM_RX_MIB_SPLIT_EN_MASK BIT(16) + #define FE_TX_MIB_ID_MASK GENMASK(15, 8) + #define FE_RX_MIB_ID_MASK GENMASK(7, 0) + +@@ -214,6 +214,33 @@ + #define REG_FE_GDM_RX_ETH_L511_CNT_L(_n) (GDM_BASE(_n) + 0x198) + #define REG_FE_GDM_RX_ETH_L1023_CNT_L(_n) (GDM_BASE(_n) + 0x19c) + ++#define REG_GDM_SRC_PORT_SET(_n) (GDM_BASE(_n) + 0x23c) ++#define GDM_SPORT_OFF2_MASK GENMASK(19, 16) ++#define GDM_SPORT_OFF1_MASK GENMASK(15, 12) ++#define GDM_SPORT_OFF0_MASK GENMASK(11, 8) ++ ++#define REG_FE_GDM_TX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x280) ++#define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x284) ++#define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x288) ++#define REG_FE_GDM_TX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x28c) ++ ++#define REG_FE_GDM_RX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x290) ++#define REG_FE_GDM_RX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x294) ++#define REG_FE_GDM_RX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x298) ++#define REG_FE_GDM_RX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x29c) ++#define REG_FE_GDM_TX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2b8) ++#define REG_FE_GDM_TX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2bc) ++#define REG_FE_GDM_TX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2c0) ++#define REG_FE_GDM_TX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2c4) ++#define REG_FE_GDM_TX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2c8) ++#define REG_FE_GDM_TX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2cc) ++#define REG_FE_GDM_RX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2e8) ++#define REG_FE_GDM_RX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2ec) ++#define REG_FE_GDM_RX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2f0) ++#define REG_FE_GDM_RX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2f4) ++#define REG_FE_GDM_RX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2f8) ++#define REG_FE_GDM_RX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2fc) ++ + #define REG_PPE_GLO_CFG(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x200) + #define PPE_GLO_CFG_BUSY_MASK BIT(31) + #define PPE_GLO_CFG_FLOW_DROP_UPDATE_MASK BIT(9) +@@ -326,44 +353,6 @@ + + #define REG_UPDMEM_DATA(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x374) + +-#define REG_FE_GDM_TX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x280) +-#define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x284) +-#define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x288) +-#define REG_FE_GDM_TX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x28c) +- +-#define REG_FE_GDM_RX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x290) +-#define REG_FE_GDM_RX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x294) +-#define REG_FE_GDM_RX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x298) +-#define REG_FE_GDM_RX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x29c) +-#define REG_FE_GDM_TX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2b8) +-#define REG_FE_GDM_TX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2bc) +-#define REG_FE_GDM_TX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2c0) +-#define REG_FE_GDM_TX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2c4) +-#define REG_FE_GDM_TX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2c8) +-#define REG_FE_GDM_TX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2cc) +-#define REG_FE_GDM_RX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2e8) +-#define REG_FE_GDM_RX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2ec) +-#define REG_FE_GDM_RX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2f0) +-#define REG_FE_GDM_RX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2f4) +-#define REG_FE_GDM_RX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2f8) +-#define REG_FE_GDM_RX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2fc) +- +-#define REG_GDM2_CHN_RLS (GDM2_BASE + 0x20) +-#define MBI_RX_AGE_SEL_MASK GENMASK(26, 25) +-#define MBI_TX_AGE_SEL_MASK GENMASK(18, 17) +- +-#define REG_GDM3_FWD_CFG GDM3_BASE +-#define GDM3_PAD_EN_MASK BIT(28) +- +-#define REG_GDM4_FWD_CFG GDM4_BASE +-#define GDM4_PAD_EN_MASK BIT(28) +-#define GDM4_SPORT_OFFSET0_MASK GENMASK(11, 8) +- +-#define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x23c) +-#define GDM4_SPORT_OFF2_MASK GENMASK(19, 16) +-#define GDM4_SPORT_OFF1_MASK GENMASK(15, 12) +-#define GDM4_SPORT_OFF0_MASK GENMASK(11, 8) +- + #define REG_IP_FRAG_FP 0x2010 + #define IP_ASSEMBLE_PORT_MASK GENMASK(24, 21) + #define IP_ASSEMBLE_NBQ_MASK GENMASK(20, 16) diff --git a/target/linux/airoha/patches-6.12/116-05-net-airoha-drop-redundant-GDM3-4-define.patch b/target/linux/airoha/patches-6.12/116-05-net-airoha-drop-redundant-GDM3-4-define.patch deleted file mode 100644 index a52ee91ed9..0000000000 --- a/target/linux/airoha/patches-6.12/116-05-net-airoha-drop-redundant-GDM3-4-define.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 6fbb7d72520393a3d447399799d436f17c03ff24 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 17 Jan 2025 10:29:52 +0100 -Subject: [PATCH 5/9] net: airoha: drop redundant GDM3/4 define - -The GDM FWD register are all the same hence it's redundant to have -specific define for GDM3 and GDM4. Drop the redundant define and use the -generic macro. - -Signed-off-by: Christian Marangi ---- - drivers/net/ethernet/airoha/airoha_eth.c | 4 ++-- - drivers/net/ethernet/airoha/airoha_regs.h | 8 +------- - 2 files changed, 3 insertions(+), 9 deletions(-) - ---- a/drivers/net/ethernet/airoha/airoha_eth.c -+++ b/drivers/net/ethernet/airoha/airoha_eth.c -@@ -514,8 +514,8 @@ static int airoha_fe_init(struct airoha_ - FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | - FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); - -- airoha_fe_set(eth, REG_GDM3_FWD_CFG, GDM3_PAD_EN_MASK); -- airoha_fe_set(eth, REG_GDM4_FWD_CFG, GDM4_PAD_EN_MASK); -+ airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN); -+ airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN); - - airoha_fe_crsn_qsel_init(eth); - ---- a/drivers/net/ethernet/airoha/airoha_regs.h -+++ b/drivers/net/ethernet/airoha/airoha_regs.h -@@ -128,6 +128,7 @@ - GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3)) - - #define REG_GDM_FWD_CFG(_n) GDM_BASE(_n) -+#define GDM_PAD_EN BIT(28) - #define GDM_DROP_CRC_ERR BIT(23) - #define GDM_IP4_CKSUM BIT(22) - #define GDM_TCP_CKSUM BIT(21) -@@ -352,13 +353,6 @@ - #define MBI_RX_AGE_SEL_MASK GENMASK(26, 25) - #define MBI_TX_AGE_SEL_MASK GENMASK(18, 17) - --#define REG_GDM3_FWD_CFG GDM3_BASE --#define GDM3_PAD_EN_MASK BIT(28) -- --#define REG_GDM4_FWD_CFG GDM4_BASE --#define GDM4_PAD_EN_MASK BIT(28) --#define GDM4_SPORT_OFFSET0_MASK GENMASK(11, 8) -- - #define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x23c) - #define GDM4_SPORT_OFF2_MASK GENMASK(19, 16) - #define GDM4_SPORT_OFF1_MASK GENMASK(15, 12) diff --git a/target/linux/airoha/patches-6.12/116-06-net-airoha-add-initial-fixup-for-GDM3-4-port-support.patch b/target/linux/airoha/patches-6.12/116-06-net-airoha-add-initial-fixup-for-GDM3-4-port-support.patch index 7e3ee7a9e8..f56e3b9356 100644 --- a/target/linux/airoha/patches-6.12/116-06-net-airoha-add-initial-fixup-for-GDM3-4-port-support.patch +++ b/target/linux/airoha/patches-6.12/116-06-net-airoha-add-initial-fixup-for-GDM3-4-port-support.patch @@ -19,12 +19,12 @@ Signed-off-by: Christian Marangi FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); -- airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN); -- airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN); +- airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN_MASK); +- airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN_MASK); + airoha_fe_set(eth, REG_GDM_FWD_CFG(3), -+ GDM_PAD_EN | GDM_STRIP_CRC); ++ GDM_PAD_EN_MASK | GDM_STRIP_CRC_MASK); + airoha_fe_set(eth, REG_GDM_FWD_CFG(4), -+ GDM_PAD_EN | GDM_STRIP_CRC); ++ GDM_PAD_EN_MASK | GDM_STRIP_CRC_MASK); airoha_fe_crsn_qsel_init(eth); diff --git a/target/linux/airoha/patches-6.12/116-07-airoha-ethernet-drop-xsi-mac-reset.patch b/target/linux/airoha/patches-6.12/116-07-airoha-ethernet-drop-xsi-mac-reset.patch index be23e27ce0..a8a9e64802 100644 --- a/target/linux/airoha/patches-6.12/116-07-airoha-ethernet-drop-xsi-mac-reset.patch +++ b/target/linux/airoha/patches-6.12/116-07-airoha-ethernet-drop-xsi-mac-reset.patch @@ -15,7 +15,7 @@ Signed-off-by: Christian Marangi --- a/drivers/net/ethernet/airoha/airoha_eth.c +++ b/drivers/net/ethernet/airoha/airoha_eth.c -@@ -3099,7 +3099,6 @@ static void airoha_remove(struct platfor +@@ -3100,7 +3100,6 @@ static void airoha_remove(struct platfor } static const char * const en7581_xsi_rsts_names[] = { @@ -23,7 +23,7 @@ Signed-off-by: Christian Marangi "hsi0-mac", "hsi1-mac", "hsi-mac", -@@ -3131,7 +3130,6 @@ static int airoha_en7581_get_src_port_id +@@ -3132,7 +3131,6 @@ static int airoha_en7581_get_src_port_id } static const char * const an7583_xsi_rsts_names[] = { diff --git a/target/linux/airoha/patches-6.12/116-10-net-airoha-add-phylink-support-for-GDM2-4.patch b/target/linux/airoha/patches-6.12/116-10-net-airoha-add-phylink-support-for-GDM2-4.patch index fd01dcda99..eb6b249b21 100644 --- a/target/linux/airoha/patches-6.12/116-10-net-airoha-add-phylink-support-for-GDM2-4.patch +++ b/target/linux/airoha/patches-6.12/116-10-net-airoha-add-phylink-support-for-GDM2-4.patch @@ -199,7 +199,7 @@ Signed-off-by: Christian Marangi err = register_netdev(dev); if (err) goto free_metadata_dst; -@@ -3064,6 +3199,10 @@ error_hw_cleanup: +@@ -3065,6 +3200,10 @@ error_hw_cleanup: if (port && port->dev->reg_state == NETREG_REGISTERED) { unregister_netdev(port->dev); airoha_metadata_dst_free(port); @@ -210,7 +210,7 @@ Signed-off-by: Christian Marangi } } free_netdev(eth->napi_dev); -@@ -3091,6 +3230,10 @@ static void airoha_remove(struct platfor +@@ -3092,6 +3231,10 @@ static void airoha_remove(struct platfor airoha_dev_stop(port->dev); unregister_netdev(port->dev); airoha_metadata_dst_free(port); @@ -236,7 +236,7 @@ Signed-off-by: Christian Marangi DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS); --- a/drivers/net/ethernet/airoha/airoha_regs.h +++ b/drivers/net/ethernet/airoha/airoha_regs.h -@@ -364,6 +364,18 @@ +@@ -359,6 +359,18 @@ #define IP_FRAGMENT_PORT_MASK GENMASK(8, 5) #define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0) diff --git a/target/linux/airoha/patches-6.12/606-net-airoha-disable-external-phy-code-if-PCS_AIROHA-i.patch b/target/linux/airoha/patches-6.12/606-net-airoha-disable-external-phy-code-if-PCS_AIROHA-i.patch index 563ef641a5..4f65e111a2 100644 --- a/target/linux/airoha/patches-6.12/606-net-airoha-disable-external-phy-code-if-PCS_AIROHA-i.patch +++ b/target/linux/airoha/patches-6.12/606-net-airoha-disable-external-phy-code-if-PCS_AIROHA-i.patch @@ -103,7 +103,7 @@ Signed-off-by: Mikhail Kshevetskiy err = register_netdev(dev); if (err) -@@ -3202,10 +3214,12 @@ error_hw_cleanup: +@@ -3203,10 +3215,12 @@ error_hw_cleanup: if (port && port->dev->reg_state == NETREG_REGISTERED) { unregister_netdev(port->dev); airoha_metadata_dst_free(port); @@ -116,7 +116,7 @@ Signed-off-by: Mikhail Kshevetskiy } } free_netdev(eth->napi_dev); -@@ -3233,10 +3247,12 @@ static void airoha_remove(struct platfor +@@ -3234,10 +3248,12 @@ static void airoha_remove(struct platfor airoha_dev_stop(port->dev); unregister_netdev(port->dev); airoha_metadata_dst_free(port);