From: Robert Marko Date: Thu, 8 May 2025 15:50:24 +0000 (+0200) Subject: qualcommax: renumber upstreamed patches X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=0b07da92f5521f0c8a121cddb122fa29f60bf617;p=openwrt%2Fstaging%2Fstintel.git qualcommax: renumber upstreamed patches In order to free up some more number space, simply renumber existing upstreamed patches starting from 0 again. Signed-off-by: Robert Marko --- diff --git a/target/linux/qualcommax/patches-6.6/0001-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch b/target/linux/qualcommax/patches-6.6/0001-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch new file mode 100644 index 0000000000..c1381a7bf3 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0001-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch @@ -0,0 +1,29 @@ +From 93e161c8f4b9b051e5e746814138cb5520b4b897 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 1 Sep 2023 20:10:04 +0200 +Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ8174 family + +IPQ8174 (Oak) family is part of the IPQ8074 family, but the ID-s for it +are missing so lets add them. + +Signed-off-by: Robert Marko +Reviewed-by: Kathiravan T +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20230901181041.1538999-1-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + include/dt-bindings/arm/qcom,ids.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/include/dt-bindings/arm/qcom,ids.h ++++ b/include/dt-bindings/arm/qcom,ids.h +@@ -203,6 +203,9 @@ + #define QCOM_ID_SM6125 394 + #define QCOM_ID_IPQ8070A 395 + #define QCOM_ID_IPQ8071A 396 ++#define QCOM_ID_IPQ8172 397 ++#define QCOM_ID_IPQ8173 398 ++#define QCOM_ID_IPQ8174 399 + #define QCOM_ID_IPQ6018 402 + #define QCOM_ID_IPQ6028 403 + #define QCOM_ID_SDM429W 416 diff --git a/target/linux/qualcommax/patches-6.6/0002-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch b/target/linux/qualcommax/patches-6.6/0002-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch new file mode 100644 index 0000000000..95c6c9505d --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0002-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch @@ -0,0 +1,123 @@ +From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 25 Oct 2023 14:57:57 +0530 +Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018 + +IPQ6018 SoC series comes in multiple SKU-s, and not all of them support +high frequency OPP points. + +SoC itself does however have a single bit in QFPROM to indicate the CPU +speed-bin. +That bit is used to indicate frequency limit of 1.5GHz, but that alone is +not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to +limit it further. + +IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device +will get created by NVMEM CPUFreq driver. + +Signed-off-by: Robert Marko +[ Viresh: Fixed rebase conflict. ] +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 1 + + drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++ + 2 files changed, 59 insertions(+) + +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -177,6 +177,7 @@ static const struct of_device_id blockli + { .compatible = "ti,am625", }, + { .compatible = "ti,am62a7", }, + ++ { .compatible = "qcom,ipq6018", }, + { .compatible = "qcom,ipq8064", }, + { .compatible = "qcom,apq8064", }, + { .compatible = "qcom,msm8974", }, +--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c ++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c +@@ -30,6 +30,8 @@ + + #include + ++#define IPQ6000_VERSION BIT(2) ++ + struct qcom_cpufreq_drv; + + struct qcom_cpufreq_match_data { +@@ -207,6 +209,57 @@ len_error: + return ret; + } + ++static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev, ++ struct nvmem_cell *speedbin_nvmem, ++ char **pvs_name, ++ struct qcom_cpufreq_drv *drv) ++{ ++ u32 msm_id; ++ int ret; ++ u8 *speedbin; ++ *pvs_name = NULL; ++ ++ ret = qcom_smem_get_soc_id(&msm_id); ++ if (ret) ++ return ret; ++ ++ speedbin = nvmem_cell_read(speedbin_nvmem, NULL); ++ if (IS_ERR(speedbin)) ++ return PTR_ERR(speedbin); ++ ++ switch (msm_id) { ++ case QCOM_ID_IPQ6005: ++ case QCOM_ID_IPQ6010: ++ case QCOM_ID_IPQ6018: ++ case QCOM_ID_IPQ6028: ++ /* Fuse Value Freq BIT to set ++ * --------------------------------- ++ * 2’b0 No Limit BIT(0) ++ * 2’b1 1.5 GHz BIT(1) ++ */ ++ drv->versions = 1 << (unsigned int)(*speedbin); ++ break; ++ case QCOM_ID_IPQ6000: ++ /* ++ * IPQ6018 family only has one bit to advertise the CPU ++ * speed-bin, but that is not enough for IPQ6000 which ++ * is only rated up to 1.2GHz. ++ * So for IPQ6000 manually set BIT(2) based on SMEM ID. ++ */ ++ drv->versions = IPQ6000_VERSION; ++ break; ++ default: ++ dev_err(cpu_dev, ++ "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n", ++ msm_id); ++ drv->versions = IPQ6000_VERSION; ++ break; ++ } ++ ++ kfree(speedbin); ++ return 0; ++} ++ + static const struct qcom_cpufreq_match_data match_data_kryo = { + .get_version = qcom_cpufreq_kryo_name_version, + }; +@@ -221,6 +274,10 @@ static const struct qcom_cpufreq_match_d + .genpd_names = qcs404_genpd_names, + }; + ++static const struct qcom_cpufreq_match_data match_data_ipq6018 = { ++ .get_version = qcom_cpufreq_ipq6018_name_version, ++}; ++ + static int qcom_cpufreq_probe(struct platform_device *pdev) + { + struct qcom_cpufreq_drv *drv; +@@ -353,6 +410,7 @@ static const struct of_device_id qcom_cp + { .compatible = "qcom,apq8096", .data = &match_data_kryo }, + { .compatible = "qcom,msm8996", .data = &match_data_kryo }, + { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, ++ { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 }, + { .compatible = "qcom,ipq8064", .data = &match_data_krait }, + { .compatible = "qcom,apq8064", .data = &match_data_krait }, + { .compatible = "qcom,msm8974", .data = &match_data_krait }, diff --git a/target/linux/qualcommax/patches-6.6/0003-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch b/target/linux/qualcommax/patches-6.6/0003-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch new file mode 100644 index 0000000000..5640038404 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0003-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch @@ -0,0 +1,113 @@ +From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 13 Oct 2023 19:20:02 +0200 +Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074 + +IPQ8074 comes in 3 families: +* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz +* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz +* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz + +So, in order to be able to share one OPP table lets add support for IPQ8074 +family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074. + +IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device +will get created by NVMEM CPUFreq driver. + +Signed-off-by: Robert Marko +Acked-by: Konrad Dybcio +[ Viresh: Fixed rebase conflict. ] +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 1 + + drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++ + 2 files changed, 49 insertions(+) + +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -179,6 +179,7 @@ static const struct of_device_id blockli + + { .compatible = "qcom,ipq6018", }, + { .compatible = "qcom,ipq8064", }, ++ { .compatible = "qcom,ipq8074", }, + { .compatible = "qcom,apq8064", }, + { .compatible = "qcom,msm8974", }, + { .compatible = "qcom,msm8960", }, +--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c ++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c +@@ -32,6 +32,11 @@ + + #define IPQ6000_VERSION BIT(2) + ++enum ipq8074_versions { ++ IPQ8074_HAWKEYE_VERSION = 0, ++ IPQ8074_ACORN_VERSION, ++}; ++ + struct qcom_cpufreq_drv; + + struct qcom_cpufreq_match_data { +@@ -260,6 +265,44 @@ static int qcom_cpufreq_ipq6018_name_ver + return 0; + } + ++static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev, ++ struct nvmem_cell *speedbin_nvmem, ++ char **pvs_name, ++ struct qcom_cpufreq_drv *drv) ++{ ++ u32 msm_id; ++ int ret; ++ *pvs_name = NULL; ++ ++ ret = qcom_smem_get_soc_id(&msm_id); ++ if (ret) ++ return ret; ++ ++ switch (msm_id) { ++ case QCOM_ID_IPQ8070A: ++ case QCOM_ID_IPQ8071A: ++ case QCOM_ID_IPQ8172: ++ case QCOM_ID_IPQ8173: ++ case QCOM_ID_IPQ8174: ++ drv->versions = BIT(IPQ8074_ACORN_VERSION); ++ break; ++ case QCOM_ID_IPQ8072A: ++ case QCOM_ID_IPQ8074A: ++ case QCOM_ID_IPQ8076A: ++ case QCOM_ID_IPQ8078A: ++ drv->versions = BIT(IPQ8074_HAWKEYE_VERSION); ++ break; ++ default: ++ dev_err(cpu_dev, ++ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n", ++ msm_id); ++ drv->versions = BIT(IPQ8074_ACORN_VERSION); ++ break; ++ } ++ ++ return 0; ++} ++ + static const struct qcom_cpufreq_match_data match_data_kryo = { + .get_version = qcom_cpufreq_kryo_name_version, + }; +@@ -278,6 +321,10 @@ static const struct qcom_cpufreq_match_d + .get_version = qcom_cpufreq_ipq6018_name_version, + }; + ++static const struct qcom_cpufreq_match_data match_data_ipq8074 = { ++ .get_version = qcom_cpufreq_ipq8074_name_version, ++}; ++ + static int qcom_cpufreq_probe(struct platform_device *pdev) + { + struct qcom_cpufreq_drv *drv; +@@ -412,6 +459,7 @@ static const struct of_device_id qcom_cp + { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, + { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 }, + { .compatible = "qcom,ipq8064", .data = &match_data_krait }, ++ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 }, + { .compatible = "qcom,apq8064", .data = &match_data_krait }, + { .compatible = "qcom,msm8974", .data = &match_data_krait }, + { .compatible = "qcom,msm8960", .data = &match_data_krait }, diff --git a/target/linux/qualcommax/patches-6.6/0004-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch b/target/linux/qualcommax/patches-6.6/0004-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch new file mode 100644 index 0000000000..ddd53f9d42 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0004-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch @@ -0,0 +1,43 @@ +From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Thu, 14 Sep 2023 12:29:57 +0530 +Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock + provider + +While the kernel is booting up, APSS PLL will be running at 800MHz with +GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be +configured and select the rate based on the opp table and the source will +be changed to APSS_PLL_EARLY. + +Without this patch, CPU Freq driver reports that CPU is running at 24MHz +instead of the 800MHz. + +Reviewed-by: Konrad Dybcio +Tested-by: Robert Marko +Signed-off-by: Kathiravan Thirumoorthy +--- + drivers/clk/qcom/apss-ipq6018.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/clk/qcom/apss-ipq6018.c ++++ b/drivers/clk/qcom/apss-ipq6018.c +@@ -20,16 +20,19 @@ + + enum { + P_XO, ++ P_GPLL0, + P_APSS_PLL_EARLY, + }; + + static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { + { .fw_name = "xo" }, ++ { .fw_name = "gpll0" }, + { .fw_name = "pll" }, + }; + + static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + { P_XO, 0 }, ++ { P_GPLL0, 4 }, + { P_APSS_PLL_EARLY, 5 }, + }; + diff --git a/target/linux/qualcommax/patches-6.6/0005-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch b/target/linux/qualcommax/patches-6.6/0005-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch new file mode 100644 index 0000000000..6b7dd2f261 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0005-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch @@ -0,0 +1,32 @@ +From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Thu, 14 Sep 2023 12:29:58 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock + provider for mailbox + +While the kernel is booting up, APSS PLL will be running at 800MHz with +GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be +configured to the rate based on the opp table and the source also will +be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, +with this inclusion, CPU Freq correctly reports that CPU is running at +800MHz rather than 24MHz. + +Signed-off-by: Kathiravan Thirumoorthy +Reviewed-by: Konrad Dybcio +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -723,8 +723,8 @@ + compatible = "qcom,ipq8074-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; +- clocks = <&a53pll>, <&xo>; +- clock-names = "pll", "xo"; ++ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; ++ clock-names = "pll", "xo", "gpll0"; + + #clock-cells = <1>; + #mbox-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.6/0006-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch b/target/linux/qualcommax/patches-6.6/0006-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch new file mode 100644 index 0000000000..d407b9c5c4 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0006-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch @@ -0,0 +1,35 @@ +From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Thu, 14 Sep 2023 12:29:59 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock + provider for mailbox + +While the kernel is booting up, APSS clock / CPU clock will be running +at 800MHz with GPLL0 as source. Once the cpufreq driver is available, +APSS PLL will be configured to the rate based on the opp table and the +source also will be changed to APSS_PLL_EARLY. So allow the mailbox to +consume the GPLL0, with this inclusion, CPU Freq correctly reports that +CPU is running at 800MHz rather than 24MHz. + +Signed-off-by: Kathiravan Thirumoorthy +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com +[bjorn: Updated commit message, as requested by Kathiravan] +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -620,8 +620,8 @@ + compatible = "qcom,ipq6018-apcs-apps-global"; + reg = <0x0 0x0b111000 0x0 0x1000>; + #clock-cells = <1>; +- clocks = <&a53pll>, <&xo>; +- clock-names = "pll", "xo"; ++ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; ++ clock-names = "pll", "xo", "gpll0"; + #mbox-cells = <1>; + }; + diff --git a/target/linux/qualcommax/patches-6.6/0007-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch b/target/linux/qualcommax/patches-6.6/0007-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch new file mode 100644 index 0000000000..eb68b87640 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0007-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch @@ -0,0 +1,57 @@ +From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 21 Oct 2023 13:55:18 +0200 +Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock + +QUP6 I2C clock is listed in the dt bindings but it was never included in +the GCC driver. +So lets add support for it, it is marked as criticial as it is used by RPM +to communicate to the external PMIC over I2C so this clock must not be +disabled. + +Signed-off-by: Robert Marko +Reviewed-by: Kathiravan Thirumoorthy +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq6018.c ++++ b/drivers/clk/qcom/gcc-ipq6018.c +@@ -2121,6 +2121,26 @@ static struct clk_branch gcc_blsp1_qup5_ + }, + }; + ++static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { ++ .halt_reg = 0x07010, ++ .clkr = { ++ .enable_reg = 0x07010, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_qup6_i2c_apps_clk", ++ .parent_hws = (const struct clk_hw *[]){ ++ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, ++ .num_parents = 1, ++ /* ++ * RPM uses QUP6 I2C to communicate with the external ++ * PMIC so it must not be disabled. ++ */ ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ + static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { + .halt_reg = 0x0700c, + .clkr = { +@@ -4277,6 +4297,7 @@ static struct clk_regmap *gcc_ipq6018_cl + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, ++ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, diff --git a/target/linux/qualcommax/patches-6.6/0008-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch b/target/linux/qualcommax/patches-6.6/0008-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch new file mode 100644 index 0000000000..6198e24f38 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0008-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch @@ -0,0 +1,85 @@ +From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 21 Oct 2023 14:00:07 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM + +IPQ6018 comes in multiple SKU-s and some of them dont support all of the +OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only +supported OPP-s based on the SoC dynamically. + +As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only +goes up to 1.5GHz and is marked as such via an eFuse. + +Signed-off-by: Robert Marko +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -96,42 +96,49 @@ + }; + + cpu_opp_table: opp-table-cpu { +- compatible = "operating-points-v2"; ++ compatible = "operating-points-v2-kryo-cpu"; ++ nvmem-cells = <&cpu_speed_bin>; + opp-shared; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <725000>; ++ opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <787500>; ++ opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <862500>; ++ opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-microvolt = <925000>; ++ opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <987500>; ++ opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1062500>; ++ opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + }; +@@ -322,6 +329,11 @@ + reg = <0x0 0x000a4000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ cpu_speed_bin: cpu-speed-bin@135 { ++ reg = <0x135 0x1>; ++ bits = <7 1>; ++ }; + }; + + prng: qrng@e3000 { diff --git a/target/linux/qualcommax/patches-6.6/0009-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch b/target/linux/qualcommax/patches-6.6/0009-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch new file mode 100644 index 0000000000..af3e132584 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0009-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch @@ -0,0 +1,81 @@ +From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sun, 3 Dec 2023 23:39:14 +0800 +Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node + +Add node to support all the QUP UART node controller inside of IPQ6018. +Some routers use these bus to connect Bluetooth chips. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -459,6 +459,26 @@ + qcom,ee = <0>; + }; + ++ blsp1_uart1: serial@78af000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x78af000 0x0 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart2: serial@78b0000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x78b0000 0x0 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ + blsp1_uart3: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x0 0x078b1000 0x0 0x200>; +@@ -467,6 +487,36 @@ + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; ++ }; ++ ++ blsp1_uart4: serial@78b2000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x078b2000 0x0 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart5: serial@78b3000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x78b3000 0x0 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart6: serial@78b4000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x078b4000 0x0 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; + }; + + blsp1_spi1: spi@78b5000 { diff --git a/target/linux/qualcommax/patches-6.6/0010-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch b/target/linux/qualcommax/patches-6.6/0010-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch new file mode 100644 index 0000000000..6559f3bbe9 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0010-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch @@ -0,0 +1,95 @@ +From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001 +From: Krishna Kurapati +Date: Fri, 26 Jan 2024 00:29:18 +0530 +Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets + +On several QUSB2 Targets, the hs_phy_irq mentioned is actually +qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq +to qusb2_phy for such targets. + +In actuality, the hs_phy_irq is also present in these targets, but +kept in for debug purposes in hw test environments. This is not +triggered by default and its functionality is mutually exclusive +to that of qusb2_phy interrupt. + +Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets. +Add missing ss_phy_irq on some targets which allows for remote +wakeup to work on a Super Speed link. + +Also modify order of interrupts in accordance to bindings update. +Since driver looks up for interrupts by name and not by index, it +is safe to modify order of these interrupts in the DT. + +Signed-off-by: Krishna Kurapati +Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++ + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ + arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++-- + arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++++-- + arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++-- + arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++---- + arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++-- + arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++-- + 8 files changed, 70 insertions(+), 14 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -431,6 +431,12 @@ + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <24000000>; ++ ++ interrupts = , ++ ; ++ interrupt-names = "pwr_event", ++ "qusb2_phy"; ++ + resets = <&gcc GCC_USB1_BCR>; + status = "disabled"; + +@@ -629,6 +635,13 @@ + <133330000>, + <24000000>; + ++ interrupts = , ++ , ++ ; ++ interrupt-names = "pwr_event", ++ "qusb2_phy", ++ "ss_phy_irq"; ++ + resets = <&gcc GCC_USB0_BCR>; + status = "disabled"; + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -632,6 +632,13 @@ + <133330000>, + <19200000>; + ++ interrupts = , ++ , ++ ; ++ interrupt-names = "pwr_event", ++ "qusb2_phy", ++ "ss_phy_irq"; ++ + power-domains = <&gcc USB0_GDSC>; + + resets = <&gcc GCC_USB0_BCR>; +@@ -675,6 +682,13 @@ + <133330000>, + <19200000>; + ++ interrupts = , ++ , ++ ; ++ interrupt-names = "pwr_event", ++ "qusb2_phy", ++ "ss_phy_irq"; ++ + power-domains = <&gcc USB1_GDSC>; + + resets = <&gcc GCC_USB1_BCR>; diff --git a/target/linux/qualcommax/patches-6.6/0011-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch b/target/linux/qualcommax/patches-6.6/0011-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch new file mode 100644 index 0000000000..25d56870a4 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0011-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch @@ -0,0 +1,32 @@ +From c3dc3d079d191c9149496b3c7fe1ece909386d93 Mon Sep 17 00:00:00 2001 +From: Vignesh Viswanathan +Date: Tue, 5 Sep 2023 15:25:35 +0530 +Subject: [PATCH] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible + +IPQ6018 has 32 tcsr_mutex hwlock registers with stride 0x1000. +The compatible string qcom,ipq6018-tcsr-mutex is mapped to +of_msm8226_tcsr_mutex which has 32 locks configured with stride of 0x80 +and doesn't match the HW present in IPQ6018. + +Remove IPQ6018 specific compatible string so that it fallsback to +of_tcsr_mutex data which maps to the correct configuration for IPQ6018. + +Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs") +Signed-off-by: Vignesh Viswanathan +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230905095535.1263113-3-quic_viswanat@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/hwspinlock/qcom_hwspinlock.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/hwspinlock/qcom_hwspinlock.c ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -115,7 +115,6 @@ static const struct of_device_id qcom_hw + { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex }, + { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex }, + { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, +- { .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, + { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, + { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, + { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, diff --git a/target/linux/qualcommax/patches-6.6/0012-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch b/target/linux/qualcommax/patches-6.6/0012-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch new file mode 100644 index 0000000000..29d2de9b23 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0012-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch @@ -0,0 +1,34 @@ +From 0b17197055b528da22e9385200e61b847b499d48 Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Thu, 25 Jan 2024 11:04:11 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add tsens node + +IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add +node for it. + +Signed-off-by: Mantas Pucka +Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -343,6 +343,16 @@ + clock-names = "core"; + }; + ++ tsens: thermal-sensor@4a9000 { ++ compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens"; ++ reg = <0x0 0x004a9000 0x0 0x1000>, ++ <0x0 0x004a8000 0x0 0x1000>; ++ interrupts = ; ++ interrupt-names = "combined"; ++ #qcom,sensors = <16>; ++ #thermal-sensor-cells = <1>; ++ }; ++ + cryptobam: dma-controller@704000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x00704000 0x0 0x20000>; diff --git a/target/linux/qualcommax/patches-6.6/0013-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch b/target/linux/qualcommax/patches-6.6/0013-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch new file mode 100644 index 0000000000..7e8c84558e --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0013-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch @@ -0,0 +1,180 @@ +From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Thu, 25 Jan 2024 11:04:12 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones + +Add thermal zones to make use of thermal sensors data. For CPU zone, +add cooling device that uses CPU frequency scaling. + +Signed-off-by: Mantas Pucka +Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++ + 1 file changed, 121 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + + / { + #address-cells = <2>; +@@ -43,6 +44,7 @@ + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; ++ #cooling-cells = <2>; + }; + + CPU1: cpu@1 { +@@ -55,6 +57,7 @@ + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; ++ #cooling-cells = <2>; + }; + + CPU2: cpu@2 { +@@ -67,6 +70,7 @@ + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; ++ #cooling-cells = <2>; + }; + + CPU3: cpu@3 { +@@ -79,6 +83,7 @@ + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; ++ #cooling-cells = <2>; + }; + + L2_0: l2-cache { +@@ -890,6 +895,122 @@ + }; + }; + ++ thermal-zones { ++ nss-top-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsens 4>; ++ ++ trips { ++ nss-top-critical { ++ temperature = <125000>; ++ hysteresis = <1000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ nss-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsens 5>; ++ ++ trips { ++ nss-critical { ++ temperature = <125000>; ++ hysteresis = <1000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ wcss-phya0-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsens 7>; ++ ++ trips { ++ wcss-phya0-critical { ++ temperature = <125000>; ++ hysteresis = <1000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ wcss-phya1-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsens 8>; ++ ++ trips { ++ wcss-phya1-critical { ++ temperature = <125000>; ++ hysteresis = <1000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cpu-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsens 13>; ++ ++ trips { ++ cpu-critical { ++ temperature = <125000>; ++ hysteresis = <1000>; ++ type = "critical"; ++ }; ++ ++ cpu_alert: cpu-passive { ++ temperature = <110000>; ++ hysteresis = <1000>; ++ type = "passive"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert>; ++ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ lpass-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsens 14>; ++ ++ trips { ++ lpass-critical { ++ temperature = <125000>; ++ hysteresis = <1000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ ddrss-top-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&tsens 15>; ++ ++ trips { ++ ddrss-top-critical { ++ temperature = <125000>; ++ hysteresis = <1000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupts = , diff --git a/target/linux/qualcommax/patches-6.6/0014-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch b/target/linux/qualcommax/patches-6.6/0014-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch new file mode 100644 index 0000000000..5f0af1352a --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0014-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch @@ -0,0 +1,50 @@ +From fd712118aa1aa758da1fd1546b3f8a1b00e42cbc Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Tue, 23 Jan 2024 11:26:09 +0200 +Subject: [PATCH] clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi + operation + +Without it system hangs upon wifi firmware load. It should be enabled by +remoteproc/wifi driver. Bindings already exist for it, so add it based +on vendor code. + +Signed-off-by: Mantas Pucka +Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/gcc-ipq6018.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq6018.c ++++ b/drivers/clk/qcom/gcc-ipq6018.c +@@ -3524,6 +3524,22 @@ static struct clk_branch gcc_prng_ahb_cl + }, + }; + ++static struct clk_branch gcc_qdss_at_clk = { ++ .halt_reg = 0x29024, ++ .clkr = { ++ .enable_reg = 0x29024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_at_clk", ++ .parent_hws = (const struct clk_hw *[]){ ++ &qdss_at_clk_src.clkr.hw }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ + static struct clk_branch gcc_qdss_dap_clk = { + .halt_reg = 0x29084, + .clkr = { +@@ -4363,6 +4379,7 @@ static struct clk_regmap *gcc_ipq6018_cl + [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr, + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, ++ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, + [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, + [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, + [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, diff --git a/target/linux/qualcommax/patches-6.6/0015-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch b/target/linux/qualcommax/patches-6.6/0015-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch new file mode 100644 index 0000000000..9021b572e8 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0015-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch @@ -0,0 +1,58 @@ +From 62a5df451ab911421da96655fcc4d1e269ff6e2f Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Tue, 23 Jan 2024 18:09:20 +0200 +Subject: [PATCH] phy: qcom-qmp-usb: fix serdes init sequence for IPQ6018 + +Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018") +noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses +separate serdes init sequence for IPQ6018. Since already existing IPQ9574 +serdes init sequence is identical, just reuse it and fix failing USB3 mode +in IPQ6018. + +Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018") +Signed-off-by: Mantas Pucka +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/1706026160-17520-3-git-send-email-mantas@8devices.com +Signed-off-by: Vinod Koul +--- + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++++++++++++++++- + 1 file changed, 19 insertions(+), 1 deletion(-) + +--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -1314,6 +1314,26 @@ static const struct qmp_usb_offsets qmp_ + .rx = 0x1000, + }; + ++static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = { ++ .lanes = 1, ++ ++ .serdes_tbl = ipq9574_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = ipq8074_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), ++ .pcs_tbl = ipq8074_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++}; ++ + static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { + .lanes = 1, + +@@ -2239,7 +2259,7 @@ err_node_put: + static const struct of_device_id qmp_usb_of_match_table[] = { + { + .compatible = "qcom,ipq6018-qmp-usb3-phy", +- .data = &ipq8074_usb3phy_cfg, ++ .data = &ipq6018_usb3phy_cfg, + }, { + .compatible = "qcom,ipq8074-qmp-usb3-phy", + .data = &ipq8074_usb3phy_cfg, diff --git a/target/linux/qualcommax/patches-6.6/0016-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch b/target/linux/qualcommax/patches-6.6/0016-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch new file mode 100644 index 0000000000..16d2437490 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0016-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch @@ -0,0 +1,38 @@ +From 6a25e70214fde6dcf900271c819c8d7fe7b9a4b0 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 23 Nov 2023 13:12:54 +0100 +Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP4 SPI node + +Add node to support the QUP4 SPI controller inside of IPQ8074. +Some devices use this bus to communicate to a Bluetooth controller. + +Signed-off-by: Robert Marko +Link: https://lore.kernel.org/r/20231123121324.1046164-1-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -536,6 +536,20 @@ + status = "disabled"; + }; + ++ blsp1_spi4: spi@78b8000 { ++ compatible = "qcom,spi-qup-v2.2.1"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x78b8000 0x600>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 18>, <&blsp_dma 19>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ + blsp1_i2c5: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.6/0017-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch b/target/linux/qualcommax/patches-6.6/0017-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch new file mode 100644 index 0000000000..e075c590fb --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0017-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch @@ -0,0 +1,32 @@ +From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001 +From: Paweł Owoc +Date: Wed, 13 Mar 2024 11:27:06 +0100 +Subject: [PATCH] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins + +gpio16 will only be used for LCD support, as its NAND/LCDC data[8] +so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8 +or 16-bit with only 8-bit one being supported in our case so that pin +is unused. + +It should be dropped from the default NAND pinctrl configuration +as its unused and only needed for LCD. + +Signed-off-by: Paweł Owoc +Reviewed-by: Kathiravan Thirumoorthy +Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -372,7 +372,7 @@ + "gpio5", "gpio6", "gpio7", + "gpio8", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", +- "gpio15", "gpio16", "gpio17"; ++ "gpio15", "gpio17"; + function = "qpic"; + drive-strength = <8>; + bias-disable; diff --git a/target/linux/qualcommax/patches-6.6/0018-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch b/target/linux/qualcommax/patches-6.6/0018-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch new file mode 100644 index 0000000000..8e973e63f2 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0018-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch @@ -0,0 +1,31 @@ +From 9cbaee8379e620f82112002f973adde19679df31 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 16 Aug 2023 18:14:00 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq5018: add watchdog + +Add the required DT node for watchdog operation. + +Signed-off-by: Robert Marko +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230816161455.3310629-2-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -181,6 +181,13 @@ + }; + }; + ++ watchdog: watchdog@b017000 { ++ compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; ++ reg = <0x0b017000 0x40>; ++ interrupts = ; ++ clocks = <&sleep_clk>; ++ }; ++ + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.6/0019-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch b/target/linux/qualcommax/patches-6.6/0019-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch new file mode 100644 index 0000000000..46d3c61398 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0019-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch @@ -0,0 +1,41 @@ +From 92dab9ea5f389c12828283146c60054642453a91 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 16 Aug 2023 18:45:38 +0200 +Subject: [PATCH] dt-bindings: firmware: qcom,scm: support indicating SDI + default state + +IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that +means that WDT being asserted or just trying to reboot will hang the board +in the debug mode and only pulling the power and repowering will help. +Some IPQ4019 boards like Google WiFI have it enabled as well. + +So, lets add a boolean property to indicate that SDI is enabled by default +and thus needs to be disabled by the kernel. + +Signed-off-by: Robert Marko +Acked-by: Mukesh Ojha +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Brian Norris +Link: https://lore.kernel.org/r/20230816164641.3371878-1-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml ++++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +@@ -89,6 +89,14 @@ properties: + protocol to handle sleeping SCM calls. + maxItems: 1 + ++ qcom,sdi-enabled: ++ description: ++ Indicates that the SDI (Secure Debug Image) has been enabled by TZ ++ by default and it needs to be disabled. ++ If not disabled WDT assertion or reboot will cause the board to hang ++ in the debug mode. ++ type: boolean ++ + qcom,dload-mode: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: diff --git a/target/linux/qualcommax/patches-6.6/0020-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch b/target/linux/qualcommax/patches-6.6/0020-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch new file mode 100644 index 0000000000..747ba7f285 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0020-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch @@ -0,0 +1,83 @@ +From ff4aa3bc98258a240b9bbab53fd8d2fb8184c485 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 16 Aug 2023 18:45:39 +0200 +Subject: [PATCH] firmware: qcom_scm: disable SDI if required + +IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that +means that WDT being asserted or just trying to reboot will hang the board +in the debug mode and only pulling the power and repowering will help. +Some IPQ4019 boards like Google WiFI have it enabled as well. + +Luckily, SDI can be disabled via an SCM call. + +So, lets use the boolean DT property to identify boards that have SDI +enabled by default and use the SCM call to disable SDI during SCM probe. +It is important to disable it as soon as possible as we might have a WDT +assertion at any time which would then leave the board in debug mode, +thus disabling it during SCM removal is not enough. + +Signed-off-by: Robert Marko +Reviewed-by: Guru Das Srinagesh +Link: https://lore.kernel.org/r/20230816164641.3371878-2-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + drivers/firmware/qcom_scm.c | 30 ++++++++++++++++++++++++++++++ + drivers/firmware/qcom_scm.h | 1 + + 2 files changed, 31 insertions(+) + +--- a/drivers/firmware/qcom_scm.c ++++ b/drivers/firmware/qcom_scm.c +@@ -410,6 +410,29 @@ int qcom_scm_set_remote_state(u32 state, + } + EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); + ++static int qcom_scm_disable_sdi(void) ++{ ++ int ret; ++ struct qcom_scm_desc desc = { ++ .svc = QCOM_SCM_SVC_BOOT, ++ .cmd = QCOM_SCM_BOOT_SDI_CONFIG, ++ .args[0] = 1, /* Disable watchdog debug */ ++ .args[1] = 0, /* Disable SDI */ ++ .arginfo = QCOM_SCM_ARGS(2), ++ .owner = ARM_SMCCC_OWNER_SIP, ++ }; ++ struct qcom_scm_res res; ++ ++ ret = qcom_scm_clk_enable(); ++ if (ret) ++ return ret; ++ ret = qcom_scm_call(__scm->dev, &desc, &res); ++ ++ qcom_scm_clk_disable(); ++ ++ return ret ? : res.result[0]; ++} ++ + static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) + { + struct qcom_scm_desc desc = { +@@ -1474,6 +1497,13 @@ static int qcom_scm_probe(struct platfor + + __get_convention(); + ++ ++ /* ++ * Disable SDI if indicated by DT that it is enabled by default. ++ */ ++ if (of_property_read_bool(pdev->dev.of_node, "qcom,sdi-enabled")) ++ qcom_scm_disable_sdi(); ++ + /* + * If requested enable "download mode", from this point on warmboot + * will cause the boot stages to enter download mode, unless +--- a/drivers/firmware/qcom_scm.h ++++ b/drivers/firmware/qcom_scm.h +@@ -80,6 +80,7 @@ extern int scm_legacy_call(struct device + #define QCOM_SCM_SVC_BOOT 0x01 + #define QCOM_SCM_BOOT_SET_ADDR 0x01 + #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 ++#define QCOM_SCM_BOOT_SDI_CONFIG 0x09 + #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 + #define QCOM_SCM_BOOT_SET_ADDR_MC 0x11 + #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a diff --git a/target/linux/qualcommax/patches-6.6/0021-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.6/0021-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch new file mode 100644 index 0000000000..d36ccddd27 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0021-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch @@ -0,0 +1,25 @@ +From f6aa7386bc40b552eea8ec1b1d2168afe3b31110 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 16 Aug 2023 18:45:40 +0200 +Subject: [PATCH] dt-bindings: firmware: qcom,scm: document IPQ5018 compatible + +It seems that IPQ5018 compatible was never documented in the bindings. + +Signed-off-by: Robert Marko +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20230816164641.3371878-3-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml ++++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +@@ -24,6 +24,7 @@ properties: + - qcom,scm-apq8064 + - qcom,scm-apq8084 + - qcom,scm-ipq4019 ++ - qcom,scm-ipq5018 + - qcom,scm-ipq5332 + - qcom,scm-ipq6018 + - qcom,scm-ipq806x diff --git a/target/linux/qualcommax/patches-6.6/0022-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch b/target/linux/qualcommax/patches-6.6/0022-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch new file mode 100644 index 0000000000..6d598bf50f --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0022-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch @@ -0,0 +1,26 @@ +From 79796e87215db9587d6c66ec6f6781e091bc6464 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 16 Aug 2023 18:45:41 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq5018: indicate that SDI should be + disabled + +Now that SCM has support for indicating that SDI has been enabled by +default, lets set the property so SCM disables it during probing. + +Signed-off-by: Robert Marko +Link: https://lore.kernel.org/r/20230816164641.3371878-4-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -57,6 +57,7 @@ + firmware { + scm { + compatible = "qcom,scm-ipq5018", "qcom,scm"; ++ qcom,sdi-enabled; + }; + }; + diff --git a/target/linux/qualcommax/patches-6.6/0023-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.6/0023-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch new file mode 100644 index 0000000000..777212249e --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0023-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch @@ -0,0 +1,28 @@ +From 1852dfaacd3f4358bbfca134b63a02bbb30c1136 Mon Sep 17 00:00:00 2001 +From: Nitheesh Sekar +Date: Mon, 4 Sep 2023 12:06:32 +0530 +Subject: [PATCH] dt-bindings: phy: qcom,m31: Add IPQ5018 compatible + +IPQ5332 qcom,m31 phy driver can support IPQ5018. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Nitheesh Sekar +Link: https://lore.kernel.org/r/20230904063635.24975-2-quic_nsekar@quicinc.com +Signed-off-by: Vinod Koul +--- + .../devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml ++++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml +@@ -17,7 +17,9 @@ description: + properties: + compatible: + items: +- - const: qcom,ipq5332-usb-hsphy ++ - enum: ++ - qcom,ipq5018-usb-hsphy ++ - qcom,ipq5332-usb-hsphy + + "#phy-cells": + const: 0 diff --git a/target/linux/qualcommax/patches-6.6/0024-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch b/target/linux/qualcommax/patches-6.6/0024-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch deleted file mode 100644 index c1381a7bf3..0000000000 --- a/target/linux/qualcommax/patches-6.6/0024-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 93e161c8f4b9b051e5e746814138cb5520b4b897 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 1 Sep 2023 20:10:04 +0200 -Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ8174 family - -IPQ8174 (Oak) family is part of the IPQ8074 family, but the ID-s for it -are missing so lets add them. - -Signed-off-by: Robert Marko -Reviewed-by: Kathiravan T -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20230901181041.1538999-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - include/dt-bindings/arm/qcom,ids.h | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/include/dt-bindings/arm/qcom,ids.h -+++ b/include/dt-bindings/arm/qcom,ids.h -@@ -203,6 +203,9 @@ - #define QCOM_ID_SM6125 394 - #define QCOM_ID_IPQ8070A 395 - #define QCOM_ID_IPQ8071A 396 -+#define QCOM_ID_IPQ8172 397 -+#define QCOM_ID_IPQ8173 398 -+#define QCOM_ID_IPQ8174 399 - #define QCOM_ID_IPQ6018 402 - #define QCOM_ID_IPQ6028 403 - #define QCOM_ID_SDM429W 416 diff --git a/target/linux/qualcommax/patches-6.6/0024-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.6/0024-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch new file mode 100644 index 0000000000..248b47c694 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0024-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch @@ -0,0 +1,89 @@ +From 68320e35f8cb1987b4ad34347fc7033832da99e3 Mon Sep 17 00:00:00 2001 +From: Nitheesh Sekar +Date: Mon, 4 Sep 2023 12:06:33 +0530 +Subject: [PATCH] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018 + +Add phy init sequence and compatible string for IPQ5018 +chipset. + +Signed-off-by: Nitheesh Sekar +Link: https://lore.kernel.org/r/20230904063635.24975-3-quic_nsekar@quicinc.com +Signed-off-by: Vinod Koul +--- + drivers/phy/qualcomm/phy-qcom-m31.c | 51 +++++++++++++++++++++++++++++ + 1 file changed, 51 insertions(+) + +--- a/drivers/phy/qualcomm/phy-qcom-m31.c ++++ b/drivers/phy/qualcomm/phy-qcom-m31.c +@@ -82,6 +82,50 @@ struct m31_priv_data { + unsigned int nregs; + }; + ++static const struct m31_phy_regs m31_ipq5018_regs[] = { ++ { ++ .off = USB_PHY_CFG0, ++ .val = UTMI_PHY_OVERRIDE_EN ++ }, ++ { ++ .off = USB_PHY_UTMI_CTRL5, ++ .val = POR_EN, ++ .delay = 15 ++ }, ++ { ++ .off = USB_PHY_FSEL_SEL, ++ .val = FREQ_SEL ++ }, ++ { ++ .off = USB_PHY_HS_PHY_CTRL_COMMON0, ++ .val = COMMONONN | FSEL | RETENABLEN ++ }, ++ { ++ .off = USB_PHY_REFCLK_CTRL, ++ .val = CLKCORE ++ }, ++ { ++ .off = USB_PHY_UTMI_CTRL5, ++ .val = POR_EN ++ }, ++ { ++ .off = USB_PHY_HS_PHY_CTRL2, ++ .val = USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN ++ }, ++ { ++ .off = USB_PHY_UTMI_CTRL5, ++ .val = 0x0 ++ }, ++ { ++ .off = USB_PHY_HS_PHY_CTRL2, ++ .val = USB2_SUSPEND_N | USB2_UTMI_CLK_EN ++ }, ++ { ++ .off = USB_PHY_CFG0, ++ .val = 0x0 ++ }, ++}; ++ + static struct m31_phy_regs m31_ipq5332_regs[] = { + { + USB_PHY_CFG0, +@@ -267,6 +311,12 @@ static int m31usb_phy_probe(struct platf + return PTR_ERR_OR_ZERO(phy_provider); + } + ++static const struct m31_priv_data m31_ipq5018_data = { ++ .ulpi_mode = false, ++ .regs = m31_ipq5018_regs, ++ .nregs = ARRAY_SIZE(m31_ipq5018_regs), ++}; ++ + static const struct m31_priv_data m31_ipq5332_data = { + .ulpi_mode = false, + .regs = m31_ipq5332_regs, +@@ -274,6 +324,7 @@ static const struct m31_priv_data m31_ip + }; + + static const struct of_device_id m31usb_phy_id_table[] = { ++ { .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data }, + { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data }, + { }, + }; diff --git a/target/linux/qualcommax/patches-6.6/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch b/target/linux/qualcommax/patches-6.6/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch deleted file mode 100644 index 95c6c9505d..0000000000 --- a/target/linux/qualcommax/patches-6.6/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 25 Oct 2023 14:57:57 +0530 -Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018 - -IPQ6018 SoC series comes in multiple SKU-s, and not all of them support -high frequency OPP points. - -SoC itself does however have a single bit in QFPROM to indicate the CPU -speed-bin. -That bit is used to indicate frequency limit of 1.5GHz, but that alone is -not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to -limit it further. - -IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device -will get created by NVMEM CPUFreq driver. - -Signed-off-by: Robert Marko -[ Viresh: Fixed rebase conflict. ] -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/cpufreq-dt-platdev.c | 1 + - drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++ - 2 files changed, 59 insertions(+) - ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -177,6 +177,7 @@ static const struct of_device_id blockli - { .compatible = "ti,am625", }, - { .compatible = "ti,am62a7", }, - -+ { .compatible = "qcom,ipq6018", }, - { .compatible = "qcom,ipq8064", }, - { .compatible = "qcom,apq8064", }, - { .compatible = "qcom,msm8974", }, ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -30,6 +30,8 @@ - - #include - -+#define IPQ6000_VERSION BIT(2) -+ - struct qcom_cpufreq_drv; - - struct qcom_cpufreq_match_data { -@@ -207,6 +209,57 @@ len_error: - return ret; - } - -+static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev, -+ struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, -+ struct qcom_cpufreq_drv *drv) -+{ -+ u32 msm_id; -+ int ret; -+ u8 *speedbin; -+ *pvs_name = NULL; -+ -+ ret = qcom_smem_get_soc_id(&msm_id); -+ if (ret) -+ return ret; -+ -+ speedbin = nvmem_cell_read(speedbin_nvmem, NULL); -+ if (IS_ERR(speedbin)) -+ return PTR_ERR(speedbin); -+ -+ switch (msm_id) { -+ case QCOM_ID_IPQ6005: -+ case QCOM_ID_IPQ6010: -+ case QCOM_ID_IPQ6018: -+ case QCOM_ID_IPQ6028: -+ /* Fuse Value Freq BIT to set -+ * --------------------------------- -+ * 2’b0 No Limit BIT(0) -+ * 2’b1 1.5 GHz BIT(1) -+ */ -+ drv->versions = 1 << (unsigned int)(*speedbin); -+ break; -+ case QCOM_ID_IPQ6000: -+ /* -+ * IPQ6018 family only has one bit to advertise the CPU -+ * speed-bin, but that is not enough for IPQ6000 which -+ * is only rated up to 1.2GHz. -+ * So for IPQ6000 manually set BIT(2) based on SMEM ID. -+ */ -+ drv->versions = IPQ6000_VERSION; -+ break; -+ default: -+ dev_err(cpu_dev, -+ "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n", -+ msm_id); -+ drv->versions = IPQ6000_VERSION; -+ break; -+ } -+ -+ kfree(speedbin); -+ return 0; -+} -+ - static const struct qcom_cpufreq_match_data match_data_kryo = { - .get_version = qcom_cpufreq_kryo_name_version, - }; -@@ -221,6 +274,10 @@ static const struct qcom_cpufreq_match_d - .genpd_names = qcs404_genpd_names, - }; - -+static const struct qcom_cpufreq_match_data match_data_ipq6018 = { -+ .get_version = qcom_cpufreq_ipq6018_name_version, -+}; -+ - static int qcom_cpufreq_probe(struct platform_device *pdev) - { - struct qcom_cpufreq_drv *drv; -@@ -353,6 +410,7 @@ static const struct of_device_id qcom_cp - { .compatible = "qcom,apq8096", .data = &match_data_kryo }, - { .compatible = "qcom,msm8996", .data = &match_data_kryo }, - { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, -+ { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 }, - { .compatible = "qcom,ipq8064", .data = &match_data_krait }, - { .compatible = "qcom,apq8064", .data = &match_data_krait }, - { .compatible = "qcom,msm8974", .data = &match_data_krait }, diff --git a/target/linux/qualcommax/patches-6.6/0025-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.6/0025-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch new file mode 100644 index 0000000000..146fcbff09 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0025-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch @@ -0,0 +1,41 @@ +From 3865a64284cc4845c61cf3dc6c7246349d80cc49 Mon Sep 17 00:00:00 2001 +From: Nitheesh Sekar +Date: Thu, 31 Aug 2023 08:35:03 +0530 +Subject: [PATCH] dt-bindings: usb: dwc3: Add IPQ5018 compatible + +Document the IPQ5018 dwc3 compatible. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Nitheesh Sekar +Link: https://lore.kernel.org/r/20230831030503.17100-1-quic_nsekar@quicinc.com +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml ++++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +@@ -14,6 +14,7 @@ properties: + items: + - enum: + - qcom,ipq4019-dwc3 ++ - qcom,ipq5018-dwc3 + - qcom,ipq5332-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8064-dwc3 +@@ -238,6 +239,7 @@ allOf: + compatible: + contains: + enum: ++ - qcom,ipq5018-dwc3 + - qcom,ipq5332-dwc3 + - qcom,msm8994-dwc3 + - qcom,qcs404-dwc3 +@@ -411,6 +413,7 @@ allOf: + compatible: + contains: + enum: ++ - qcom,ipq5018-dwc3 + - qcom,ipq5332-dwc3 + - qcom,sdm660-dwc3 + then: diff --git a/target/linux/qualcommax/patches-6.6/0026-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch b/target/linux/qualcommax/patches-6.6/0026-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch deleted file mode 100644 index 5640038404..0000000000 --- a/target/linux/qualcommax/patches-6.6/0026-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 13 Oct 2023 19:20:02 +0200 -Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074 - -IPQ8074 comes in 3 families: -* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz -* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz -* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz - -So, in order to be able to share one OPP table lets add support for IPQ8074 -family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074. - -IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device -will get created by NVMEM CPUFreq driver. - -Signed-off-by: Robert Marko -Acked-by: Konrad Dybcio -[ Viresh: Fixed rebase conflict. ] -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/cpufreq-dt-platdev.c | 1 + - drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++ - 2 files changed, 49 insertions(+) - ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -179,6 +179,7 @@ static const struct of_device_id blockli - - { .compatible = "qcom,ipq6018", }, - { .compatible = "qcom,ipq8064", }, -+ { .compatible = "qcom,ipq8074", }, - { .compatible = "qcom,apq8064", }, - { .compatible = "qcom,msm8974", }, - { .compatible = "qcom,msm8960", }, ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -32,6 +32,11 @@ - - #define IPQ6000_VERSION BIT(2) - -+enum ipq8074_versions { -+ IPQ8074_HAWKEYE_VERSION = 0, -+ IPQ8074_ACORN_VERSION, -+}; -+ - struct qcom_cpufreq_drv; - - struct qcom_cpufreq_match_data { -@@ -260,6 +265,44 @@ static int qcom_cpufreq_ipq6018_name_ver - return 0; - } - -+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev, -+ struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, -+ struct qcom_cpufreq_drv *drv) -+{ -+ u32 msm_id; -+ int ret; -+ *pvs_name = NULL; -+ -+ ret = qcom_smem_get_soc_id(&msm_id); -+ if (ret) -+ return ret; -+ -+ switch (msm_id) { -+ case QCOM_ID_IPQ8070A: -+ case QCOM_ID_IPQ8071A: -+ case QCOM_ID_IPQ8172: -+ case QCOM_ID_IPQ8173: -+ case QCOM_ID_IPQ8174: -+ drv->versions = BIT(IPQ8074_ACORN_VERSION); -+ break; -+ case QCOM_ID_IPQ8072A: -+ case QCOM_ID_IPQ8074A: -+ case QCOM_ID_IPQ8076A: -+ case QCOM_ID_IPQ8078A: -+ drv->versions = BIT(IPQ8074_HAWKEYE_VERSION); -+ break; -+ default: -+ dev_err(cpu_dev, -+ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n", -+ msm_id); -+ drv->versions = BIT(IPQ8074_ACORN_VERSION); -+ break; -+ } -+ -+ return 0; -+} -+ - static const struct qcom_cpufreq_match_data match_data_kryo = { - .get_version = qcom_cpufreq_kryo_name_version, - }; -@@ -278,6 +321,10 @@ static const struct qcom_cpufreq_match_d - .get_version = qcom_cpufreq_ipq6018_name_version, - }; - -+static const struct qcom_cpufreq_match_data match_data_ipq8074 = { -+ .get_version = qcom_cpufreq_ipq8074_name_version, -+}; -+ - static int qcom_cpufreq_probe(struct platform_device *pdev) - { - struct qcom_cpufreq_drv *drv; -@@ -412,6 +459,7 @@ static const struct of_device_id qcom_cp - { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, - { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 }, - { .compatible = "qcom,ipq8064", .data = &match_data_krait }, -+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 }, - { .compatible = "qcom,apq8064", .data = &match_data_krait }, - { .compatible = "qcom,msm8974", .data = &match_data_krait }, - { .compatible = "qcom,msm8960", .data = &match_data_krait }, diff --git a/target/linux/qualcommax/patches-6.6/0026-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch b/target/linux/qualcommax/patches-6.6/0026-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch new file mode 100644 index 0000000000..99fdae732a --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0026-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch @@ -0,0 +1,86 @@ +From e7166f2774aafefd29ff26ffbbb7f6d40ac8ea1c Mon Sep 17 00:00:00 2001 +From: Nitheesh Sekar +Date: Mon, 4 Sep 2023 12:06:34 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq5018: Add USB related nodes + +Add USB phy and controller nodes. + +Co-developed-by: Amandeep Singh +Signed-off-by: Amandeep Singh +Signed-off-by: Nitheesh Sekar +Link: https://lore.kernel.org/r/20230904063635.24975-4-quic_nsekar@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -94,6 +94,19 @@ + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + ++ usbphy0: phy@5b000 { ++ compatible = "qcom,ipq5018-usb-hsphy"; ++ reg = <0x0005b000 0x120>; ++ ++ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; ++ ++ resets = <&gcc GCC_QUSB2_0_PHY_BCR>; ++ ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5018-tlmm"; + reg = <0x01000000 0x300000>; +@@ -156,6 +169,47 @@ + status = "disabled"; + }; + ++ usb: usb@8af8800 { ++ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; ++ reg = <0x08af8800 0x400>; ++ ++ interrupts = ; ++ interrupt-names = "hs_phy_irq"; ++ ++ clocks = <&gcc GCC_USB0_MASTER_CLK>, ++ <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, ++ <&gcc GCC_USB0_SLEEP_CLK>, ++ <&gcc GCC_USB0_MOCK_UTMI_CLK>; ++ clock-names = "core", ++ "iface", ++ "sleep", ++ "mock_utmi"; ++ ++ resets = <&gcc GCC_USB0_BCR>; ++ ++ qcom,select-utmi-as-pipe-clk; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ status = "disabled"; ++ ++ usb_dwc: usb@8a00000 { ++ compatible = "snps,dwc3"; ++ reg = <0x08a00000 0xe000>; ++ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; ++ clock-names = "ref"; ++ interrupts = ; ++ phy-names = "usb2-phy"; ++ phys = <&usbphy0>; ++ tx-fifo-resize; ++ snps,is-utmi-l1-suspend; ++ snps,hird-threshold = /bits/ 8 <0x0>; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ }; ++ }; ++ + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ diff --git a/target/linux/qualcommax/patches-6.6/0027-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch b/target/linux/qualcommax/patches-6.6/0027-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch deleted file mode 100644 index ddd53f9d42..0000000000 --- a/target/linux/qualcommax/patches-6.6/0027-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch +++ /dev/null @@ -1,43 +0,0 @@ -From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Thu, 14 Sep 2023 12:29:57 +0530 -Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock - provider - -While the kernel is booting up, APSS PLL will be running at 800MHz with -GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be -configured and select the rate based on the opp table and the source will -be changed to APSS_PLL_EARLY. - -Without this patch, CPU Freq driver reports that CPU is running at 24MHz -instead of the 800MHz. - -Reviewed-by: Konrad Dybcio -Tested-by: Robert Marko -Signed-off-by: Kathiravan Thirumoorthy ---- - drivers/clk/qcom/apss-ipq6018.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/clk/qcom/apss-ipq6018.c -+++ b/drivers/clk/qcom/apss-ipq6018.c -@@ -20,16 +20,19 @@ - - enum { - P_XO, -+ P_GPLL0, - P_APSS_PLL_EARLY, - }; - - static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { - { .fw_name = "xo" }, -+ { .fw_name = "gpll0" }, - { .fw_name = "pll" }, - }; - - static const struct parent_map parents_apcs_alias0_clk_src_map[] = { - { P_XO, 0 }, -+ { P_GPLL0, 4 }, - { P_APSS_PLL_EARLY, 5 }, - }; - diff --git a/target/linux/qualcommax/patches-6.6/0027-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch b/target/linux/qualcommax/patches-6.6/0027-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch new file mode 100644 index 0000000000..d0d9e45dec --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0027-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch @@ -0,0 +1,56 @@ +From a1f42e08f0f04b72a6597f080db4bfbb3737910c Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 4 Oct 2023 21:12:30 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq5018: add QUP1 SPI controller + +Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018. + +Signed-off-by: Robert Marko +Reviewed-by: Kathiravan Thirumoorthy +Link: https://lore.kernel.org/r/20231004191303.331055-1-robimarko@gmail.com +[bjorn: Padded address to 8 digits, fixed node sort order] +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -159,6 +159,16 @@ + status = "disabled"; + }; + ++ blsp_dma: dma-controller@7884000 { ++ compatible = "qcom,bam-v1.7.0"; ++ reg = <0x07884000 0x1d000>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "bam_clk"; ++ #dma-cells = <1>; ++ qcom,ee = <0>; ++ }; ++ + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; +@@ -169,6 +179,20 @@ + status = "disabled"; + }; + ++ blsp1_spi1: spi@78b5000 { ++ compatible = "qcom,spi-qup-v2.2.1"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x078b5000 0x600>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 4>, <&blsp_dma 5>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ + usb: usb@8af8800 { + compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; diff --git a/target/linux/qualcommax/patches-6.6/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch b/target/linux/qualcommax/patches-6.6/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch deleted file mode 100644 index 6b7dd2f261..0000000000 --- a/target/linux/qualcommax/patches-6.6/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Thu, 14 Sep 2023 12:29:58 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock - provider for mailbox - -While the kernel is booting up, APSS PLL will be running at 800MHz with -GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be -configured to the rate based on the opp table and the source also will -be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, -with this inclusion, CPU Freq correctly reports that CPU is running at -800MHz rather than 24MHz. - -Signed-off-by: Kathiravan Thirumoorthy -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -723,8 +723,8 @@ - compatible = "qcom,ipq8074-apcs-apps-global", - "qcom,ipq6018-apcs-apps-global"; - reg = <0x0b111000 0x1000>; -- clocks = <&a53pll>, <&xo>; -- clock-names = "pll", "xo"; -+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; -+ clock-names = "pll", "xo", "gpll0"; - - #clock-cells = <1>; - #mbox-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.6/0028-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.6/0028-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch new file mode 100644 index 0000000000..314afa76d2 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0028-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch @@ -0,0 +1,25 @@ +From 4d45d56e17348c6b6bb2bce126a4a5ea97b19900 Mon Sep 17 00:00:00 2001 +From: Gokul Sriram Palanisamy +Date: Mon, 25 Sep 2023 15:58:24 +0530 +Subject: [PATCH] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible + +Add IPQ5018 compatible to A53 PLL bindings. + +Signed-off-by: Gokul Sriram Palanisamy +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20230925102826.405446-2-quic_gokulsri@quicinc.com +Signed-off-by: Bjorn Andersson +--- + Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml ++++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml +@@ -16,6 +16,7 @@ description: + properties: + compatible: + enum: ++ - qcom,ipq5018-a53pll + - qcom,ipq5332-a53pll + - qcom,ipq6018-a53pll + - qcom,ipq8074-a53pll diff --git a/target/linux/qualcommax/patches-6.6/0029-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.6/0029-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch new file mode 100644 index 0000000000..46dede07ca --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0029-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch @@ -0,0 +1,62 @@ +From 50492f929486c044b43cb3e2c0e040aa9b61ea2b Mon Sep 17 00:00:00 2001 +From: Gokul Sriram Palanisamy +Date: Mon, 25 Sep 2023 15:58:25 +0530 +Subject: [PATCH] clk: qcom: apss-ipq-pll: add support for IPQ5018 + +IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets, +add configuration values and the compatible. + +Co-developed-by: Sricharan Ramabadhran +Signed-off-by: Sricharan Ramabadhran +Signed-off-by: Gokul Sriram Palanisamy +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20230925102826.405446-3-quic_gokulsri@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/apss-ipq-pll.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/drivers/clk/qcom/apss-ipq-pll.c ++++ b/drivers/clk/qcom/apss-ipq-pll.c +@@ -73,6 +73,20 @@ static struct clk_alpha_pll ipq_pll_stro + }, + }; + ++static const struct alpha_pll_config ipq5018_pll_config = { ++ .l = 0x32, ++ .config_ctl_val = 0x4001075b, ++ .config_ctl_hi_val = 0x304, ++ .main_output_mask = BIT(0), ++ .aux_output_mask = BIT(1), ++ .early_output_mask = BIT(3), ++ .alpha_en_mask = BIT(24), ++ .status_val = 0x3, ++ .status_mask = GENMASK(10, 8), ++ .lock_det = BIT(2), ++ .test_ctl_hi_val = 0x00400003, ++}; ++ + static const struct alpha_pll_config ipq5332_pll_config = { + .l = 0x2d, + .config_ctl_val = 0x4001075b, +@@ -129,6 +143,12 @@ struct apss_pll_data { + const struct alpha_pll_config *pll_config; + }; + ++static const struct apss_pll_data ipq5018_pll_data = { ++ .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, ++ .pll = &ipq_pll_stromer_plus, ++ .pll_config = &ipq5018_pll_config, ++}; ++ + static struct apss_pll_data ipq5332_pll_data = { + .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, + .pll = &ipq_pll_stromer_plus, +@@ -195,6 +215,7 @@ static int apss_ipq_pll_probe(struct pla + } + + static const struct of_device_id apss_ipq_pll_match_table[] = { ++ { .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data }, + { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, + { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, + { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, diff --git a/target/linux/qualcommax/patches-6.6/0030-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch b/target/linux/qualcommax/patches-6.6/0030-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch new file mode 100644 index 0000000000..72bec54cb3 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0030-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch @@ -0,0 +1,98 @@ +From 3e4b53e04281ed3d9c7a4329c027097265c04d54 Mon Sep 17 00:00:00 2001 +From: Gokul Sriram Palanisamy +Date: Mon, 25 Sep 2023 15:58:26 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq5018: enable the CPUFreq support + +Add the APCS, A53 PLL, cpu-opp-table nodes to set +the CPU frequency at 800MHz (idle) or 1.008GHz. + +Co-developed-by: Sricharan Ramabadhran +Signed-off-by: Sricharan Ramabadhran +Signed-off-by: Gokul Sriram Palanisamy +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20230925102826.405446-4-quic_gokulsri@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -5,6 +5,7 @@ + * Copyright (c) 2023 The Linux Foundation. All rights reserved. + */ + ++#include + #include + #include + #include +@@ -36,6 +37,8 @@ + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ operating-points-v2 = <&cpu_opp_table>; + }; + + CPU1: cpu@1 { +@@ -44,6 +47,8 @@ + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ operating-points-v2 = <&cpu_opp_table>; + }; + + L2_0: l2-cache { +@@ -54,6 +59,25 @@ + }; + }; + ++ cpu_opp_table: opp-table-cpu { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ /* ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <200000>; ++ }; ++ */ ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <200000>; ++ }; ++ }; ++ + firmware { + scm { + compatible = "qcom,scm-ipq5018", "qcom,scm"; +@@ -267,6 +291,24 @@ + clocks = <&sleep_clk>; + }; + ++ apcs_glb: mailbox@b111000 { ++ compatible = "qcom,ipq5018-apcs-apps-global", ++ "qcom,ipq6018-apcs-apps-global"; ++ reg = <0x0b111000 0x1000>; ++ #clock-cells = <1>; ++ clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; ++ clock-names = "pll", "xo", "gpll0"; ++ #mbox-cells = <1>; ++ }; ++ ++ a53pll: clock@b116000 { ++ compatible = "qcom,ipq5018-a53pll"; ++ reg = <0x0b116000 0x40>; ++ #clock-cells = <0>; ++ clocks = <&xo_board_clk>; ++ clock-names = "xo"; ++ }; ++ + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.6/0031-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch b/target/linux/qualcommax/patches-6.6/0031-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch new file mode 100644 index 0000000000..97631e715a --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0031-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch @@ -0,0 +1,66 @@ +From a427dd16e61f3d145bc24f0ed09692fc25931250 Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Wed, 25 Oct 2023 22:12:12 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq5018: add few more reserved memory + regions + +Like all other IPQ SoCs, bootloader will collect the system RAM contents +upon crash for the post morterm analysis. If we don't reserve the memory +region used by bootloader, obviously linux will consume it and upon next +boot on crash, bootloader will be loaded in the same region, which will +lead to loose some of the data, sometimes we may miss out critical +information. So lets reserve the region used by the bootloader. + +Similarly SBL copies some data into the reserved region and it will be +used in the crash scenario. So reserve 1MB for SBL as well. + +While at it, enable the SMEM support along with TCSR mutex. + +Signed-off-by: Kathiravan Thirumoorthy +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20231025-ipq5018-misc-v1-1-7d14fde97fe7@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -106,6 +106,24 @@ + #size-cells = <2>; + ranges; + ++ bootloader@4a800000 { ++ reg = <0x0 0x4a800000 0x0 0x200000>; ++ no-map; ++ }; ++ ++ sbl@4aa00000 { ++ reg = <0x0 0x4aa00000 0x0 0x100000>; ++ no-map; ++ }; ++ ++ smem@4ab00000 { ++ compatible = "qcom,smem"; ++ reg = <0x0 0x4ab00000 0x0 0x100000>; ++ no-map; ++ ++ hwlocks = <&tcsr_mutex 3>; ++ }; ++ + tz_region: tz@4ac00000 { + reg = <0x0 0x4ac00000 0x0 0x200000>; + no-map; +@@ -166,6 +184,12 @@ + #power-domain-cells = <1>; + }; + ++ tcsr_mutex: hwlock@1905000 { ++ compatible = "qcom,tcsr-mutex"; ++ reg = <0x01905000 0x20000>; ++ #hwlock-cells = <1>; ++ }; ++ + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x7804000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.6/0032-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch b/target/linux/qualcommax/patches-6.6/0032-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch new file mode 100644 index 0000000000..ea6f61b57f --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0032-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch @@ -0,0 +1,83 @@ +From: Gabor Juhos +Subject: [PATCH] clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure +Date: Fri, 15 Mar 2024 17:16:41 +0100 + +Booting v6.8 results in a hang on various IPQ5018 based boards. +Investigating the problem showed that the hang happens when the +clk_alpha_pll_stromer_plus_set_rate() function tries to write +into the PLL_MODE register of the APSS PLL. + +Checking the downstream code revealed that it uses [1] stromer +specific operations for IPQ5018, whereas in the current code +the stromer plus specific operations are used. + +The ops in the 'ipq_pll_stromer_plus' clock definition can't be +changed since that is needed for IPQ5332, so add a new alpha pll +clock declaration which uses the correct stromer ops and use this +new clock for IPQ5018 to avoid the boot failure. + +Also, change pll_type in 'ipq5018_pll_data' to +CLK_ALPHA_PLL_TYPE_STROMER to better reflect that it is a Stromer +PLL and change the apss_ipq_pll_probe() function accordingly. + +1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c#L67 + +Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018") +Signed-off-by: Gabor Juhos +--- + drivers/clk/qcom/apss-ipq-pll.c | 30 +++++++++++++++++++++++++++--- + 1 file changed, 27 insertions(+), 3 deletions(-) + +--- a/drivers/clk/qcom/apss-ipq-pll.c ++++ b/drivers/clk/qcom/apss-ipq-pll.c +@@ -55,6 +55,29 @@ static struct clk_alpha_pll ipq_pll_huay + }, + }; + ++static struct clk_alpha_pll ipq_pll_stromer = { ++ .offset = 0x0, ++ /* ++ * Reuse CLK_ALPHA_PLL_TYPE_STROMER_PLUS register offsets. ++ * Although this is a bit confusing, but the offset values ++ * are correct nevertheless. ++ */ ++ .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], ++ .flags = SUPPORTS_DYNAMIC_UPDATE, ++ .clkr = { ++ .enable_reg = 0x0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "a53pll", ++ .parent_data = &(const struct clk_parent_data) { ++ .fw_name = "xo", ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_stromer_ops, ++ }, ++ }, ++}; ++ + static struct clk_alpha_pll ipq_pll_stromer_plus = { + .offset = 0x0, + .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], +@@ -144,8 +167,8 @@ struct apss_pll_data { + }; + + static const struct apss_pll_data ipq5018_pll_data = { +- .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, +- .pll = &ipq_pll_stromer_plus, ++ .pll_type = CLK_ALPHA_PLL_TYPE_STROMER, ++ .pll = &ipq_pll_stromer, + .pll_config = &ipq5018_pll_config, + }; + +@@ -203,7 +226,8 @@ static int apss_ipq_pll_probe(struct pla + + if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) + clk_alpha_pll_configure(data->pll, regmap, data->pll_config); +- else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) ++ else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER || ++ data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) + clk_stromer_pll_configure(data->pll, regmap, data->pll_config); + + ret = devm_clk_register_regmap(dev, &data->pll->clkr); diff --git a/target/linux/qualcommax/patches-6.6/0033-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.6/0033-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch new file mode 100644 index 0000000000..4bf0598c36 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0033-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch @@ -0,0 +1,32 @@ +From: Gabor Juhos +Subject: [PATCH] clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018 +Date: Tue, 26 Mar 2024 14:34:11 +0100 + +According to ipq5018.dtsi, the maximum supported rate by the +CPU is 1.008 GHz on the IPQ5018 platform, however the current +configuration of the PLL results in 1.2 GHz rate. + +Change the 'L' value in the PLL configuration to limit the +rate to 1.008 GHz. The downstream kernel also uses the same +value [1]. Also add a comment to indicate the desired +frequency. + +[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c?ref_type=heads#L151 + +Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018") +Signed-off-by: Gabor Juhos +--- + drivers/clk/qcom/apss-ipq-pll.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/clk/qcom/apss-ipq-pll.c ++++ b/drivers/clk/qcom/apss-ipq-pll.c +@@ -97,7 +97,7 @@ static struct clk_alpha_pll ipq_pll_stro + }; + + static const struct alpha_pll_config ipq5018_pll_config = { +- .l = 0x32, ++ .l = 0x2a, + .config_ctl_val = 0x4001075b, + .config_ctl_hi_val = 0x304, + .main_output_mask = BIT(0), diff --git a/target/linux/qualcommax/patches-6.6/0034-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch b/target/linux/qualcommax/patches-6.6/0034-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch new file mode 100644 index 0000000000..ddd54079fb --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0034-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch @@ -0,0 +1,26 @@ +From f2743ae3ff84579981ac513f512b9df945d109c0 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Thu, 20 Jun 2024 23:01:21 +0800 +Subject: [PATCH] clk: qcom: gcc-ipq6018: update sdcc max clock frequency + +The mmc controller of the IPQ6018 does not support HS400 mode. +So adjust the maximum clock frequency of sdcc to 200 MHz (HS200). + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/gcc-ipq6018.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/qcom/gcc-ipq6018.c ++++ b/drivers/clk/qcom/gcc-ipq6018.c +@@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_a + F(96000000, P_GPLL2, 12, 0, 0), + F(177777778, P_GPLL0, 4.5, 0, 0), + F(192000000, P_GPLL2, 6, 0, 0), +- F(384000000, P_GPLL2, 3, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), + { } + }; + diff --git a/target/linux/qualcommax/patches-6.6/0035-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch b/target/linux/qualcommax/patches-6.6/0035-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch new file mode 100644 index 0000000000..ed4b6d9e6d --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0035-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch @@ -0,0 +1,47 @@ +From 5db216f6e1f85394e79dca74ceceb83b2f8566b5 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Thu, 20 Jun 2024 23:01:22 +0800 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add sdhci node + +Add node to support mmc controller inside of IPQ6018. +This controller supports both eMMC and SD cards. + +Tested with: + eMMC (HS200) + SD Card (SDR50/SDR104) + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20240620150122.1406631-3-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -470,6 +470,25 @@ + }; + }; + ++ sdhc: mmc@7804000 { ++ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; ++ reg = <0x0 0x07804000 0x0 0x1000>, ++ <0x0 0x07805000 0x0 0x1000>; ++ reg-names = "hc", "cqhci"; ++ ++ interrupts = , ++ ; ++ interrupt-names = "hc_irq", "pwr_irq"; ++ ++ clocks = <&gcc GCC_SDCC1_AHB_CLK>, ++ <&gcc GCC_SDCC1_APPS_CLK>, ++ <&xo>; ++ clock-names = "iface", "core", "xo"; ++ resets = <&gcc GCC_SDCC1_BCR>; ++ max-frequency = <192000000>; ++ status = "disabled"; ++ }; ++ + blsp_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x07884000 0x0 0x2b000>; diff --git a/target/linux/qualcommax/patches-6.6/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch b/target/linux/qualcommax/patches-6.6/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch new file mode 100644 index 0000000000..6a1c93b869 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch @@ -0,0 +1,381 @@ +From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Tue, 22 Oct 2024 17:47:26 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case + +DTS coding style expects labels to be lowercase. No functional impact. +Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). + +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++--- + arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++----- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++------- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++----- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++-------------- + 5 files changed, 61 insertions(+), 61 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -31,27 +31,27 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; +--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi +@@ -30,47 +30,47 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -34,12 +34,12 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -47,12 +47,12 @@ + #cooling-cells = <2>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -60,12 +60,12 @@ + #cooling-cells = <2>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -73,12 +73,12 @@ + #cooling-cells = <2>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -86,7 +86,7 @@ + #cooling-cells = <2>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; +@@ -993,10 +993,10 @@ + cooling-maps { + map0 { + trip = <&cpu_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -32,39 +32,39 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -33,12 +33,12 @@ + #address-cells = <1>; + #size-cells = <0>; + +- CPU0: cpu@0 { ++ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -46,12 +46,12 @@ + #cooling-cells = <2>; + }; + +- CPU1: cpu@1 { ++ cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x1>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -59,12 +59,12 @@ + #cooling-cells = <2>; + }; + +- CPU2: cpu@2 { ++ cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x2>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -72,12 +72,12 @@ + #cooling-cells = <2>; + }; + +- CPU3: cpu@3 { ++ cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x3>; + enable-method = "psci"; +- next-level-cache = <&L2_0>; ++ next-level-cache = <&l2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +@@ -85,7 +85,7 @@ + #cooling-cells = <2>; + }; + +- L2_0: l2-cache { ++ l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; +@@ -845,10 +845,10 @@ + cooling-maps { + map0 { + trip = <&cpu0_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +@@ -875,10 +875,10 @@ + cooling-maps { + map0 { + trip = <&cpu1_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +@@ -905,10 +905,10 @@ + cooling-maps { + map0 { + trip = <&cpu2_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +@@ -935,10 +935,10 @@ + cooling-maps { + map0 { + trip = <&cpu3_alert>; +- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; diff --git a/target/linux/qualcommax/patches-6.6/0037-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch b/target/linux/qualcommax/patches-6.6/0037-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch new file mode 100644 index 0000000000..5a5a7019ab --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0037-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch @@ -0,0 +1,33 @@ +From 144230e5840c09984ad743c3df9de5fb443159a9 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 10 Feb 2025 15:01:18 +0800 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency + +The final version of IPQ6000 (SoC id: IPQ6000, SBL version: +BOOT.XF.0.3-00086-IPQ60xxLZB-1) has a max design frequency +of 1.2GHz, so add this CPU frequency. + +Signed-off-by: Chukun Pan +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250210070122.208842-2-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -119,6 +119,13 @@ + clock-latency-ns = <200000>; + }; + ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <850000>; ++ opp-supported-hw = <0x4>; ++ clock-latency-ns = <200000>; ++ }; ++ + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <862500>; diff --git a/target/linux/qualcommax/patches-6.6/0038-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch b/target/linux/qualcommax/patches-6.6/0038-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch new file mode 100644 index 0000000000..f87356c35b --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0038-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch @@ -0,0 +1,33 @@ +From a96e765a7b3f64429f7eec3471a2093355ab041e Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 10 Feb 2025 15:01:19 +0800 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency + +The early version of IPQ6000 (SoC id: IPQ6018, SBL version: +BOOT.XF.0.3-00077-IPQ60xxLZB-2) and IPQ6005 SoCs can reach +a max frequency of 1.5GHz, so add this CPU frequency. + +Signed-off-by: Chukun Pan +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250210070122.208842-3-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -140,6 +140,13 @@ + clock-latency-ns = <200000>; + }; + ++ opp-1512000000 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <937500>; ++ opp-supported-hw = <0x2>; ++ clock-latency-ns = <200000>; ++ }; ++ + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <987500>; diff --git a/target/linux/qualcommax/patches-6.6/0039-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch b/target/linux/qualcommax/patches-6.6/0039-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch new file mode 100644 index 0000000000..505a027c2e --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0039-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch @@ -0,0 +1,120 @@ +From 0c4c0f14b7d704bcb728d018a74788771dc9286b Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 10 Feb 2025 15:01:20 +0800 +Subject: [PATCH] arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsi + +Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 +pmic was never part of the IPQ60xx SoC, it's optional, so we moved +it out of the soc dtsi. + +Signed-off-by: Chukun Pan +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20250210070122.208842-4-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- + arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 35 ++++++++++++++++++++++++++++ + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 ----------- + 3 files changed, 36 insertions(+), 15 deletions(-) + create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -7,7 +7,7 @@ + + /dts-v1/; + +-#include "ipq6018.dtsi" ++#include "ipq6018-mp5496.dtsi" + + / { + model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi +@@ -0,0 +1,35 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that ++ * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC. ++ */ ++ ++#include "ipq6018.dtsi" ++ ++&cpu0 { ++ cpu-supply = <&ipq6018_s2>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&ipq6018_s2>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&ipq6018_s2>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&ipq6018_s2>; ++}; ++ ++&rpm_requests { ++ regulators { ++ compatible = "qcom,rpm-mp5496-regulators"; ++ ++ ipq6018_s2: s2 { ++ regulator-min-microvolt = <725000>; ++ regulator-max-microvolt = <1062500>; ++ regulator-always-on; ++ }; ++ }; ++}; +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -43,7 +43,6 @@ + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +- cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; + }; + +@@ -56,7 +55,6 @@ + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +- cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; + }; + +@@ -69,7 +67,6 @@ + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +- cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; + }; + +@@ -82,7 +79,6 @@ + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; +- cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; + }; + +@@ -184,16 +180,6 @@ + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq6018"; + qcom,glink-channels = "rpm_requests"; +- +- regulators { +- compatible = "qcom,rpm-mp5496-regulators"; +- +- ipq6018_s2: s2 { +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1062500>; +- regulator-always-on; +- }; +- }; + }; + }; + }; diff --git a/target/linux/qualcommax/patches-6.6/0040-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch b/target/linux/qualcommax/patches-6.6/0040-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch new file mode 100644 index 0000000000..120ce53f8c --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0040-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch @@ -0,0 +1,50 @@ +From e60f872c2dc4c1d9227977c8714373fe6328699c Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 10 Feb 2025 15:01:21 +0800 +Subject: [PATCH] arm64: dts: qcom: ipq6018: rename labels of mp5496 regulator + +Change the labels of mp5496 regulator from ipq6018 to mp5496. + +Suggested-by: Konrad Dybcio +Suggested-by: Dmitry Baryshkov +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20250210070122.208842-5-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi +@@ -7,26 +7,26 @@ + #include "ipq6018.dtsi" + + &cpu0 { +- cpu-supply = <&ipq6018_s2>; ++ cpu-supply = <&mp5496_s2>; + }; + + &cpu1 { +- cpu-supply = <&ipq6018_s2>; ++ cpu-supply = <&mp5496_s2>; + }; + + &cpu2 { +- cpu-supply = <&ipq6018_s2>; ++ cpu-supply = <&mp5496_s2>; + }; + + &cpu3 { +- cpu-supply = <&ipq6018_s2>; ++ cpu-supply = <&mp5496_s2>; + }; + + &rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + +- ipq6018_s2: s2 { ++ mp5496_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; diff --git a/target/linux/qualcommax/patches-6.6/0041-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch b/target/linux/qualcommax/patches-6.6/0041-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch new file mode 100644 index 0000000000..ce98c62f83 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0041-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch @@ -0,0 +1,33 @@ +From a566fb9ba8ffecb56c50729390a9ea076f5c9532 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 10 Feb 2025 15:01:22 +0800 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator + +Add LDOA2 regulator from MP5496 to support SDCC voltage scaling. + +Suggested-by: Robert Marko +Signed-off-by: Chukun Pan +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250210070122.208842-6-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi +@@ -31,5 +31,14 @@ + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; ++ ++ mp5496_l2: l2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ }; + }; + }; ++ ++&sdhc { ++ vqmmc-supply = <&mp5496_l2>; ++}; diff --git a/target/linux/qualcommax/patches-6.6/0042-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch b/target/linux/qualcommax/patches-6.6/0042-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch new file mode 100644 index 0000000000..937e644626 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0042-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch @@ -0,0 +1,83 @@ +From d06b1043644a1831ab141bbee2669002bba15b0f Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 20 Dec 2023 23:17:22 +0100 +Subject: [PATCH] clk: qcom: clk-rcg: introduce support for multiple conf for + same freq + +Some RCG frequency can be reached by multiple configuration. + +We currently declare multiple configuration for the same frequency but +that is not supported and always the first configuration will be taken. + +These multiple configuration are needed as based on the current parent +configuration, it may be needed to use a different configuration to +reach the same frequency. + +To handle this introduce 3 new macro, C, FM and FMS: + +- C is used to declare a freq_conf where src, pre_div, m and n are + provided. + +- FM is used to declare a freq_multi_tbl with the frequency and an + array of confs to insert all the config for the provided frequency. + +- FMS is used to declare a freq_multi_tbl with the frequency and an + array of a single conf with the provided src, pre_div, m and n. + +Struct clk_rcg2 is changed to add a union type to reference a simple +freq_tbl or a complex freq_multi_tbl. + +Signed-off-by: Christian Marangi +Acked-by: Stephen Boyd +Link: https://lore.kernel.org/r/20231220221724.3822-2-ansuelsmth@gmail.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/clk-rcg.h | 23 ++++++++++++++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +--- a/drivers/clk/qcom/clk-rcg.h ++++ b/drivers/clk/qcom/clk-rcg.h +@@ -17,6 +17,23 @@ struct freq_tbl { + u16 n; + }; + ++#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) } ++#define FM(f, confs) { (f), ARRAY_SIZE(confs), (confs) } ++#define FMS(f, s, h, m, n) { (f), 1, (const struct freq_conf []){ C(s, h, m, n) } } ++ ++struct freq_conf { ++ u8 src; ++ u8 pre_div; ++ u16 m; ++ u16 n; ++}; ++ ++struct freq_multi_tbl { ++ unsigned long freq; ++ size_t num_confs; ++ const struct freq_conf *confs; ++}; ++ + /** + * struct mn - M/N:D counter + * @mnctr_en_bit: bit to enable mn counter +@@ -138,6 +155,7 @@ extern const struct clk_ops clk_dyn_rcg_ + * @safe_src_index: safe src index value + * @parent_map: map from software's parent index to hardware's src_sel field + * @freq_tbl: frequency table ++ * @freq_multi_tbl: frequency table for clocks reachable with multiple RCGs conf + * @clkr: regmap clock handle + * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG + * @parked_cfg: cached value of the CFG register for parked RCGs +@@ -149,7 +167,10 @@ struct clk_rcg2 { + u8 hid_width; + u8 safe_src_index; + const struct parent_map *parent_map; +- const struct freq_tbl *freq_tbl; ++ union { ++ const struct freq_tbl *freq_tbl; ++ const struct freq_multi_tbl *freq_multi_tbl; ++ }; + struct clk_regmap clkr; + u8 cfg_off; + u32 parked_cfg; diff --git a/target/linux/qualcommax/patches-6.6/0043-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch b/target/linux/qualcommax/patches-6.6/0043-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch new file mode 100644 index 0000000000..478f60ed44 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0043-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch @@ -0,0 +1,296 @@ +From 89da22456af0762477d8c1345fdd17961b3ada80 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 20 Dec 2023 23:17:23 +0100 +Subject: [PATCH] clk: qcom: clk-rcg2: add support for rcg2 freq multi ops + +Some RCG frequency can be reached by multiple configuration. + +Add clk_rcg2_fm_ops ops to support these special RCG configurations. + +These alternative ops will select the frequency using a CEIL policy. + +When the correct frequency is found, the correct config is selected by +calculating the final rate (by checking the defined parent and values +in the config that is being checked) and deciding based on the one that +is less different than the requested one. + +These check are skipped if there is just one config for the requested +freq. + +qcom_find_freq_multi is added to search the freq with the new struct +freq_multi_tbl. +__clk_rcg2_select_conf is used to select the correct conf by simulating +the final clock. +If a conf can't be found due to parent not reachable, a WARN is printed +and -EINVAL is returned. + +Tested-by: Wei Lei +Signed-off-by: Christian Marangi +Acked-by: Stephen Boyd +Link: https://lore.kernel.org/r/20231220221724.3822-3-ansuelsmth@gmail.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/clk-rcg.h | 1 + + drivers/clk/qcom/clk-rcg2.c | 166 ++++++++++++++++++++++++++++++++++++ + drivers/clk/qcom/common.c | 18 ++++ + drivers/clk/qcom/common.h | 2 + + 4 files changed, 187 insertions(+) + +--- a/drivers/clk/qcom/clk-rcg.h ++++ b/drivers/clk/qcom/clk-rcg.h +@@ -190,6 +190,7 @@ struct clk_rcg2_gfx3d { + + extern const struct clk_ops clk_rcg2_ops; + extern const struct clk_ops clk_rcg2_floor_ops; ++extern const struct clk_ops clk_rcg2_fm_ops; + extern const struct clk_ops clk_rcg2_mux_closest_ops; + extern const struct clk_ops clk_edp_pixel_ops; + extern const struct clk_ops clk_byte_ops; +--- a/drivers/clk/qcom/clk-rcg2.c ++++ b/drivers/clk/qcom/clk-rcg2.c +@@ -260,6 +260,115 @@ static int _freq_tbl_determine_rate(stru + return 0; + } + ++static const struct freq_conf * ++__clk_rcg2_select_conf(struct clk_hw *hw, const struct freq_multi_tbl *f, ++ unsigned long req_rate) ++{ ++ unsigned long rate_diff, best_rate_diff = ULONG_MAX; ++ const struct freq_conf *conf, *best_conf = NULL; ++ struct clk_rcg2 *rcg = to_clk_rcg2(hw); ++ const char *name = clk_hw_get_name(hw); ++ unsigned long parent_rate, rate; ++ struct clk_hw *p; ++ int index, i; ++ ++ /* Exit early if only one config is defined */ ++ if (f->num_confs == 1) { ++ best_conf = f->confs; ++ goto exit; ++ } ++ ++ /* Search in each provided config the one that is near the wanted rate */ ++ for (i = 0, conf = f->confs; i < f->num_confs; i++, conf++) { ++ index = qcom_find_src_index(hw, rcg->parent_map, conf->src); ++ if (index < 0) ++ continue; ++ ++ p = clk_hw_get_parent_by_index(hw, index); ++ if (!p) ++ continue; ++ ++ parent_rate = clk_hw_get_rate(p); ++ rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div); ++ ++ if (rate == req_rate) { ++ best_conf = conf; ++ goto exit; ++ } ++ ++ rate_diff = abs_diff(req_rate, rate); ++ if (rate_diff < best_rate_diff) { ++ best_rate_diff = rate_diff; ++ best_conf = conf; ++ } ++ } ++ ++ /* ++ * Very unlikely. Warn if we couldn't find a correct config ++ * due to parent not found in every config. ++ */ ++ if (unlikely(!best_conf)) { ++ WARN(1, "%s: can't find a configuration for rate %lu\n", ++ name, req_rate); ++ return ERR_PTR(-EINVAL); ++ } ++ ++exit: ++ return best_conf; ++} ++ ++static int _freq_tbl_fm_determine_rate(struct clk_hw *hw, const struct freq_multi_tbl *f, ++ struct clk_rate_request *req) ++{ ++ unsigned long clk_flags, rate = req->rate; ++ struct clk_rcg2 *rcg = to_clk_rcg2(hw); ++ const struct freq_conf *conf; ++ struct clk_hw *p; ++ int index; ++ ++ f = qcom_find_freq_multi(f, rate); ++ if (!f || !f->confs) ++ return -EINVAL; ++ ++ conf = __clk_rcg2_select_conf(hw, f, rate); ++ if (IS_ERR(conf)) ++ return PTR_ERR(conf); ++ index = qcom_find_src_index(hw, rcg->parent_map, conf->src); ++ if (index < 0) ++ return index; ++ ++ clk_flags = clk_hw_get_flags(hw); ++ p = clk_hw_get_parent_by_index(hw, index); ++ if (!p) ++ return -EINVAL; ++ ++ if (clk_flags & CLK_SET_RATE_PARENT) { ++ rate = f->freq; ++ if (conf->pre_div) { ++ if (!rate) ++ rate = req->rate; ++ rate /= 2; ++ rate *= conf->pre_div + 1; ++ } ++ ++ if (conf->n) { ++ u64 tmp = rate; ++ ++ tmp = tmp * conf->n; ++ do_div(tmp, conf->m); ++ rate = tmp; ++ } ++ } else { ++ rate = clk_hw_get_rate(p); ++ } ++ ++ req->best_parent_hw = p; ++ req->best_parent_rate = rate; ++ req->rate = f->freq; ++ ++ return 0; ++} ++ + static int clk_rcg2_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) + { +@@ -276,6 +385,14 @@ static int clk_rcg2_determine_floor_rate + return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); + } + ++static int clk_rcg2_fm_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct clk_rcg2 *rcg = to_clk_rcg2(hw); ++ ++ return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req); ++} ++ + static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, + u32 *_cfg) + { +@@ -371,6 +488,30 @@ static int __clk_rcg2_set_rate(struct cl + return clk_rcg2_configure(rcg, f); + } + ++static int __clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate) ++{ ++ struct clk_rcg2 *rcg = to_clk_rcg2(hw); ++ const struct freq_multi_tbl *f; ++ const struct freq_conf *conf; ++ struct freq_tbl f_tbl = {}; ++ ++ f = qcom_find_freq_multi(rcg->freq_multi_tbl, rate); ++ if (!f || !f->confs) ++ return -EINVAL; ++ ++ conf = __clk_rcg2_select_conf(hw, f, rate); ++ if (IS_ERR(conf)) ++ return PTR_ERR(conf); ++ ++ f_tbl.freq = f->freq; ++ f_tbl.src = conf->src; ++ f_tbl.pre_div = conf->pre_div; ++ f_tbl.m = conf->m; ++ f_tbl.n = conf->n; ++ ++ return clk_rcg2_configure(rcg, &f_tbl); ++} ++ + static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) + { +@@ -383,6 +524,12 @@ static int clk_rcg2_set_floor_rate(struc + return __clk_rcg2_set_rate(hw, rate, FLOOR); + } + ++static int clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ return __clk_rcg2_fm_set_rate(hw, rate); ++} ++ + static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate, u8 index) + { +@@ -395,6 +542,12 @@ static int clk_rcg2_set_floor_rate_and_p + return __clk_rcg2_set_rate(hw, rate, FLOOR); + } + ++static int clk_rcg2_fm_set_rate_and_parent(struct clk_hw *hw, ++ unsigned long rate, unsigned long parent_rate, u8 index) ++{ ++ return __clk_rcg2_fm_set_rate(hw, rate); ++} ++ + static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) + { + struct clk_rcg2 *rcg = to_clk_rcg2(hw); +@@ -505,6 +658,19 @@ const struct clk_ops clk_rcg2_floor_ops + }; + EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); + ++const struct clk_ops clk_rcg2_fm_ops = { ++ .is_enabled = clk_rcg2_is_enabled, ++ .get_parent = clk_rcg2_get_parent, ++ .set_parent = clk_rcg2_set_parent, ++ .recalc_rate = clk_rcg2_recalc_rate, ++ .determine_rate = clk_rcg2_fm_determine_rate, ++ .set_rate = clk_rcg2_fm_set_rate, ++ .set_rate_and_parent = clk_rcg2_fm_set_rate_and_parent, ++ .get_duty_cycle = clk_rcg2_get_duty_cycle, ++ .set_duty_cycle = clk_rcg2_set_duty_cycle, ++}; ++EXPORT_SYMBOL_GPL(clk_rcg2_fm_ops); ++ + const struct clk_ops clk_rcg2_mux_closest_ops = { + .determine_rate = __clk_mux_determine_rate_closest, + .get_parent = clk_rcg2_get_parent, +--- a/drivers/clk/qcom/common.c ++++ b/drivers/clk/qcom/common.c +@@ -41,6 +41,24 @@ struct freq_tbl *qcom_find_freq(const st + } + EXPORT_SYMBOL_GPL(qcom_find_freq); + ++const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f, ++ unsigned long rate) ++{ ++ if (!f) ++ return NULL; ++ ++ if (!f->freq) ++ return f; ++ ++ for (; f->freq; f++) ++ if (rate <= f->freq) ++ return f; ++ ++ /* Default to our fastest rate */ ++ return f - 1; ++} ++EXPORT_SYMBOL_GPL(qcom_find_freq_multi); ++ + const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, + unsigned long rate) + { +--- a/drivers/clk/qcom/common.h ++++ b/drivers/clk/qcom/common.h +@@ -45,6 +45,8 @@ extern const struct freq_tbl *qcom_find_ + unsigned long rate); + extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, + unsigned long rate); ++extern const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f, ++ unsigned long rate); + extern void + qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count); + extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, diff --git a/target/linux/qualcommax/patches-6.6/0044-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch b/target/linux/qualcommax/patches-6.6/0044-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch new file mode 100644 index 0000000000..5360771df2 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0044-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch @@ -0,0 +1,227 @@ +From e88f03230dc07aa3293b6aeb078bd27370bb2594 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 20 Dec 2023 23:17:24 +0100 +Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple + conf + +Rework nss_port5/6 to use the new multiple configuration implementation +and correctly fix the clocks for these port under some corner case. + +This is particularly relevant for device that have 2.5G or 10G port +connected to port5 or port 6 on ipq8074. As the parent are shared +across multiple port it may be required to select the correct +configuration to accomplish the desired clock. Without this patch such +port doesn't work in some specific ethernet speed as the clock will be +set to the wrong frequency as we just select the first configuration for +the related frequency instead of selecting the best one. + +Signed-off-by: Christian Marangi +Acked-by: Stephen Boyd +Link: https://lore.kernel.org/r/20231220221724.3822-4-ansuelsmth@gmail.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/gcc-ipq8074.c | 120 +++++++++++++++++++++------------ + 1 file changed, 76 insertions(+), 44 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -1677,15 +1677,23 @@ static struct clk_regmap_div nss_port4_t + }, + }; + +-static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { +- F(19200000, P_XO, 1, 0, 0), +- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), +- F(25000000, P_UNIPHY0_RX, 5, 0, 0), +- F(78125000, P_UNIPHY1_RX, 4, 0, 0), +- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), +- F(125000000, P_UNIPHY0_RX, 1, 0, 0), +- F(156250000, P_UNIPHY1_RX, 2, 0, 0), +- F(312500000, P_UNIPHY1_RX, 1, 0, 0), ++static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = { ++ C(P_UNIPHY1_RX, 12.5, 0, 0), ++ C(P_UNIPHY0_RX, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = { ++ C(P_UNIPHY1_RX, 2.5, 0, 0), ++ C(P_UNIPHY0_RX, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = { ++ FMS(19200000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_port5_rx_clk_src_25), ++ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0), ++ FM(125000000, ftbl_nss_port5_rx_clk_src_125), ++ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0), ++ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0), + { } + }; + +@@ -1712,14 +1720,14 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32 + + static struct clk_rcg2 nss_port5_rx_clk_src = { + .cmd_rcgr = 0x68060, +- .freq_tbl = ftbl_nss_port5_rx_clk_src, ++ .freq_multi_tbl = ftbl_nss_port5_rx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port5_rx_clk_src", + .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias, + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias), +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_fm_ops, + }, + }; + +@@ -1739,15 +1747,23 @@ static struct clk_regmap_div nss_port5_r + }, + }; + +-static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { +- F(19200000, P_XO, 1, 0, 0), +- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), +- F(25000000, P_UNIPHY0_TX, 5, 0, 0), +- F(78125000, P_UNIPHY1_TX, 4, 0, 0), +- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), +- F(125000000, P_UNIPHY0_TX, 1, 0, 0), +- F(156250000, P_UNIPHY1_TX, 2, 0, 0), +- F(312500000, P_UNIPHY1_TX, 1, 0, 0), ++static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = { ++ C(P_UNIPHY1_TX, 12.5, 0, 0), ++ C(P_UNIPHY0_TX, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = { ++ C(P_UNIPHY1_TX, 2.5, 0, 0), ++ C(P_UNIPHY0_TX, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = { ++ FMS(19200000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_port5_tx_clk_src_25), ++ FMS(78125000, P_UNIPHY1_TX, 4, 0, 0), ++ FM(125000000, ftbl_nss_port5_tx_clk_src_125), ++ FMS(156250000, P_UNIPHY1_TX, 2, 0, 0), ++ FMS(312500000, P_UNIPHY1_TX, 1, 0, 0), + { } + }; + +@@ -1774,14 +1790,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32 + + static struct clk_rcg2 nss_port5_tx_clk_src = { + .cmd_rcgr = 0x68068, +- .freq_tbl = ftbl_nss_port5_tx_clk_src, ++ .freq_multi_tbl = ftbl_nss_port5_tx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port5_tx_clk_src", + .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias, + .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias), +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_fm_ops, + }, + }; + +@@ -1801,15 +1817,23 @@ static struct clk_regmap_div nss_port5_t + }, + }; + +-static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { +- F(19200000, P_XO, 1, 0, 0), +- F(25000000, P_UNIPHY2_RX, 5, 0, 0), +- F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), +- F(78125000, P_UNIPHY2_RX, 4, 0, 0), +- F(125000000, P_UNIPHY2_RX, 1, 0, 0), +- F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), +- F(156250000, P_UNIPHY2_RX, 2, 0, 0), +- F(312500000, P_UNIPHY2_RX, 1, 0, 0), ++static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = { ++ C(P_UNIPHY2_RX, 5, 0, 0), ++ C(P_UNIPHY2_RX, 12.5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = { ++ C(P_UNIPHY2_RX, 1, 0, 0), ++ C(P_UNIPHY2_RX, 2.5, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = { ++ FMS(19200000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_port6_rx_clk_src_25), ++ FMS(78125000, P_UNIPHY2_RX, 4, 0, 0), ++ FM(125000000, ftbl_nss_port6_rx_clk_src_125), ++ FMS(156250000, P_UNIPHY2_RX, 2, 0, 0), ++ FMS(312500000, P_UNIPHY2_RX, 1, 0, 0), + { } + }; + +@@ -1831,14 +1855,14 @@ static const struct parent_map gcc_xo_un + + static struct clk_rcg2 nss_port6_rx_clk_src = { + .cmd_rcgr = 0x68070, +- .freq_tbl = ftbl_nss_port6_rx_clk_src, ++ .freq_multi_tbl = ftbl_nss_port6_rx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port6_rx_clk_src", + .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias, + .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias), +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_fm_ops, + }, + }; + +@@ -1858,15 +1882,23 @@ static struct clk_regmap_div nss_port6_r + }, + }; + +-static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { +- F(19200000, P_XO, 1, 0, 0), +- F(25000000, P_UNIPHY2_TX, 5, 0, 0), +- F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), +- F(78125000, P_UNIPHY2_TX, 4, 0, 0), +- F(125000000, P_UNIPHY2_TX, 1, 0, 0), +- F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), +- F(156250000, P_UNIPHY2_TX, 2, 0, 0), +- F(312500000, P_UNIPHY2_TX, 1, 0, 0), ++static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = { ++ C(P_UNIPHY2_TX, 5, 0, 0), ++ C(P_UNIPHY2_TX, 12.5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = { ++ C(P_UNIPHY2_TX, 1, 0, 0), ++ C(P_UNIPHY2_TX, 2.5, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = { ++ FMS(19200000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_port6_tx_clk_src_25), ++ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0), ++ FM(125000000, ftbl_nss_port6_tx_clk_src_125), ++ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0), ++ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0), + { } + }; + +@@ -1888,14 +1920,14 @@ static const struct parent_map gcc_xo_un + + static struct clk_rcg2 nss_port6_tx_clk_src = { + .cmd_rcgr = 0x68078, +- .freq_tbl = ftbl_nss_port6_tx_clk_src, ++ .freq_multi_tbl = ftbl_nss_port6_tx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port6_tx_clk_src", + .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias, + .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias), +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_fm_ops, + }, + }; + diff --git a/target/linux/qualcommax/patches-6.6/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch b/target/linux/qualcommax/patches-6.6/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch deleted file mode 100644 index d407b9c5c4..0000000000 --- a/target/linux/qualcommax/patches-6.6/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Thu, 14 Sep 2023 12:29:59 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock - provider for mailbox - -While the kernel is booting up, APSS clock / CPU clock will be running -at 800MHz with GPLL0 as source. Once the cpufreq driver is available, -APSS PLL will be configured to the rate based on the opp table and the -source also will be changed to APSS_PLL_EARLY. So allow the mailbox to -consume the GPLL0, with this inclusion, CPU Freq correctly reports that -CPU is running at 800MHz rather than 24MHz. - -Signed-off-by: Kathiravan Thirumoorthy -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com -[bjorn: Updated commit message, as requested by Kathiravan] -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -620,8 +620,8 @@ - compatible = "qcom,ipq6018-apcs-apps-global"; - reg = <0x0 0x0b111000 0x0 0x1000>; - #clock-cells = <1>; -- clocks = <&a53pll>, <&xo>; -- clock-names = "pll", "xo"; -+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; -+ clock-names = "pll", "xo", "gpll0"; - #mbox-cells = <1>; - }; - diff --git a/target/linux/qualcommax/patches-6.6/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch b/target/linux/qualcommax/patches-6.6/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch deleted file mode 100644 index eb68b87640..0000000000 --- a/target/linux/qualcommax/patches-6.6/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 21 Oct 2023 13:55:18 +0200 -Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock - -QUP6 I2C clock is listed in the dt bindings but it was never included in -the GCC driver. -So lets add support for it, it is marked as criticial as it is used by RPM -to communicate to the external PMIC over I2C so this clock must not be -disabled. - -Signed-off-by: Robert Marko -Reviewed-by: Kathiravan Thirumoorthy -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq6018.c -+++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -2121,6 +2121,26 @@ static struct clk_branch gcc_blsp1_qup5_ - }, - }; - -+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { -+ .halt_reg = 0x07010, -+ .clkr = { -+ .enable_reg = 0x07010, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_blsp1_qup6_i2c_apps_clk", -+ .parent_hws = (const struct clk_hw *[]){ -+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, -+ .num_parents = 1, -+ /* -+ * RPM uses QUP6 I2C to communicate with the external -+ * PMIC so it must not be disabled. -+ */ -+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { - .halt_reg = 0x0700c, - .clkr = { -@@ -4277,6 +4297,7 @@ static struct clk_regmap *gcc_ipq6018_cl - [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, - [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, -+ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, - [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, - [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, diff --git a/target/linux/qualcommax/patches-6.6/0054-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch b/target/linux/qualcommax/patches-6.6/0054-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch deleted file mode 100644 index 6198e24f38..0000000000 --- a/target/linux/qualcommax/patches-6.6/0054-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 21 Oct 2023 14:00:07 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM - -IPQ6018 comes in multiple SKU-s and some of them dont support all of the -OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only -supported OPP-s based on the SoC dynamically. - -As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only -goes up to 1.5GHz and is marked as such via an eFuse. - -Signed-off-by: Robert Marko -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++- - 1 file changed, 13 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -96,42 +96,49 @@ - }; - - cpu_opp_table: opp-table-cpu { -- compatible = "operating-points-v2"; -+ compatible = "operating-points-v2-kryo-cpu"; -+ nvmem-cells = <&cpu_speed_bin>; - opp-shared; - - opp-864000000 { - opp-hz = /bits/ 64 <864000000>; - opp-microvolt = <725000>; -+ opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <787500>; -+ opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <862500>; -+ opp-supported-hw = <0x3>; - clock-latency-ns = <200000>; - }; - - opp-1440000000 { - opp-hz = /bits/ 64 <1440000000>; - opp-microvolt = <925000>; -+ opp-supported-hw = <0x3>; - clock-latency-ns = <200000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <987500>; -+ opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1062500>; -+ opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - }; -@@ -322,6 +329,11 @@ - reg = <0x0 0x000a4000 0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ cpu_speed_bin: cpu-speed-bin@135 { -+ reg = <0x135 0x1>; -+ bits = <7 1>; -+ }; - }; - - prng: qrng@e3000 { diff --git a/target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch b/target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch deleted file mode 100644 index af3e132584..0000000000 --- a/target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch +++ /dev/null @@ -1,81 +0,0 @@ -From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 3 Dec 2023 23:39:14 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node - -Add node to support all the QUP UART node controller inside of IPQ6018. -Some routers use these bus to connect Bluetooth chips. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++ - 1 file changed, 50 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -459,6 +459,26 @@ - qcom,ee = <0>; - }; - -+ blsp1_uart1: serial@78af000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x78af000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ blsp1_uart2: serial@78b0000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x78b0000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ - blsp1_uart3: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0 0x078b1000 0x0 0x200>; -@@ -467,6 +487,36 @@ - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; -+ }; -+ -+ blsp1_uart4: serial@78b2000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x078b2000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ blsp1_uart5: serial@78b3000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x78b3000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ blsp1_uart6: serial@78b4000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x0 0x078b4000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; - }; - - blsp1_spi1: spi@78b5000 { diff --git a/target/linux/qualcommax/patches-6.6/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch b/target/linux/qualcommax/patches-6.6/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch deleted file mode 100644 index 6559f3bbe9..0000000000 --- a/target/linux/qualcommax/patches-6.6/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001 -From: Krishna Kurapati -Date: Fri, 26 Jan 2024 00:29:18 +0530 -Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets - -On several QUSB2 Targets, the hs_phy_irq mentioned is actually -qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq -to qusb2_phy for such targets. - -In actuality, the hs_phy_irq is also present in these targets, but -kept in for debug purposes in hw test environments. This is not -triggered by default and its functionality is mutually exclusive -to that of qusb2_phy interrupt. - -Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets. -Add missing ss_phy_irq on some targets which allows for remote -wakeup to work on a Super Speed link. - -Also modify order of interrupts in accordance to bindings update. -Since driver looks up for interrupts by name and not by index, it -is safe to modify order of these interrupts in the DT. - -Signed-off-by: Krishna Kurapati -Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++ - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ - arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++-- - arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++++-- - arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++-- - arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++---- - arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++-- - arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++-- - 8 files changed, 70 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -431,6 +431,12 @@ - <&gcc GCC_USB1_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <24000000>; -+ -+ interrupts = , -+ ; -+ interrupt-names = "pwr_event", -+ "qusb2_phy"; -+ - resets = <&gcc GCC_USB1_BCR>; - status = "disabled"; - -@@ -629,6 +635,13 @@ - <133330000>, - <24000000>; - -+ interrupts = , -+ , -+ ; -+ interrupt-names = "pwr_event", -+ "qusb2_phy", -+ "ss_phy_irq"; -+ - resets = <&gcc GCC_USB0_BCR>; - status = "disabled"; - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -632,6 +632,13 @@ - <133330000>, - <19200000>; - -+ interrupts = , -+ , -+ ; -+ interrupt-names = "pwr_event", -+ "qusb2_phy", -+ "ss_phy_irq"; -+ - power-domains = <&gcc USB0_GDSC>; - - resets = <&gcc GCC_USB0_BCR>; -@@ -675,6 +682,13 @@ - <133330000>, - <19200000>; - -+ interrupts = , -+ , -+ ; -+ interrupt-names = "pwr_event", -+ "qusb2_phy", -+ "ss_phy_irq"; -+ - power-domains = <&gcc USB1_GDSC>; - - resets = <&gcc GCC_USB1_BCR>; diff --git a/target/linux/qualcommax/patches-6.6/0057-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch b/target/linux/qualcommax/patches-6.6/0057-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch deleted file mode 100644 index 25d56870a4..0000000000 --- a/target/linux/qualcommax/patches-6.6/0057-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch +++ /dev/null @@ -1,32 +0,0 @@ -From c3dc3d079d191c9149496b3c7fe1ece909386d93 Mon Sep 17 00:00:00 2001 -From: Vignesh Viswanathan -Date: Tue, 5 Sep 2023 15:25:35 +0530 -Subject: [PATCH] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible - -IPQ6018 has 32 tcsr_mutex hwlock registers with stride 0x1000. -The compatible string qcom,ipq6018-tcsr-mutex is mapped to -of_msm8226_tcsr_mutex which has 32 locks configured with stride of 0x80 -and doesn't match the HW present in IPQ6018. - -Remove IPQ6018 specific compatible string so that it fallsback to -of_tcsr_mutex data which maps to the correct configuration for IPQ6018. - -Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs") -Signed-off-by: Vignesh Viswanathan -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20230905095535.1263113-3-quic_viswanat@quicinc.com -Signed-off-by: Bjorn Andersson ---- - drivers/hwspinlock/qcom_hwspinlock.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/hwspinlock/qcom_hwspinlock.c -+++ b/drivers/hwspinlock/qcom_hwspinlock.c -@@ -115,7 +115,6 @@ static const struct of_device_id qcom_hw - { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex }, - { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex }, - { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, -- { .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, - { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, - { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, - { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, diff --git a/target/linux/qualcommax/patches-6.6/0058-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch b/target/linux/qualcommax/patches-6.6/0058-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch deleted file mode 100644 index 29d2de9b23..0000000000 --- a/target/linux/qualcommax/patches-6.6/0058-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0b17197055b528da22e9385200e61b847b499d48 Mon Sep 17 00:00:00 2001 -From: Mantas Pucka -Date: Thu, 25 Jan 2024 11:04:11 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add tsens node - -IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add -node for it. - -Signed-off-by: Mantas Pucka -Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -343,6 +343,16 @@ - clock-names = "core"; - }; - -+ tsens: thermal-sensor@4a9000 { -+ compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens"; -+ reg = <0x0 0x004a9000 0x0 0x1000>, -+ <0x0 0x004a8000 0x0 0x1000>; -+ interrupts = ; -+ interrupt-names = "combined"; -+ #qcom,sensors = <16>; -+ #thermal-sensor-cells = <1>; -+ }; -+ - cryptobam: dma-controller@704000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0 0x00704000 0x0 0x20000>; diff --git a/target/linux/qualcommax/patches-6.6/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch b/target/linux/qualcommax/patches-6.6/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch deleted file mode 100644 index 7e8c84558e..0000000000 --- a/target/linux/qualcommax/patches-6.6/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch +++ /dev/null @@ -1,180 +0,0 @@ -From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001 -From: Mantas Pucka -Date: Thu, 25 Jan 2024 11:04:12 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones - -Add thermal zones to make use of thermal sensors data. For CPU zone, -add cooling device that uses CPU frequency scaling. - -Signed-off-by: Mantas Pucka -Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++ - 1 file changed, 121 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - / { - #address-cells = <2>; -@@ -43,6 +44,7 @@ - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; -+ #cooling-cells = <2>; - }; - - CPU1: cpu@1 { -@@ -55,6 +57,7 @@ - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; -+ #cooling-cells = <2>; - }; - - CPU2: cpu@2 { -@@ -67,6 +70,7 @@ - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; -+ #cooling-cells = <2>; - }; - - CPU3: cpu@3 { -@@ -79,6 +83,7 @@ - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; -+ #cooling-cells = <2>; - }; - - L2_0: l2-cache { -@@ -890,6 +895,122 @@ - }; - }; - -+ thermal-zones { -+ nss-top-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 4>; -+ -+ trips { -+ nss-top-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ nss-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 5>; -+ -+ trips { -+ nss-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ wcss-phya0-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 7>; -+ -+ trips { -+ wcss-phya0-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ wcss-phya1-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 8>; -+ -+ trips { -+ wcss-phya1-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ cpu-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 13>; -+ -+ trips { -+ cpu-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ -+ cpu_alert: cpu-passive { -+ temperature = <110000>; -+ hysteresis = <1000>; -+ type = "passive"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ lpass-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 14>; -+ -+ trips { -+ lpass-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ ddrss-top-thermal { -+ polling-delay-passive = <250>; -+ polling-delay = <1000>; -+ thermal-sensors = <&tsens 15>; -+ -+ trips { -+ ddrss-top-critical { -+ temperature = <125000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupts = , diff --git a/target/linux/qualcommax/patches-6.6/0060-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch b/target/linux/qualcommax/patches-6.6/0060-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch deleted file mode 100644 index 5f0af1352a..0000000000 --- a/target/linux/qualcommax/patches-6.6/0060-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch +++ /dev/null @@ -1,50 +0,0 @@ -From fd712118aa1aa758da1fd1546b3f8a1b00e42cbc Mon Sep 17 00:00:00 2001 -From: Mantas Pucka -Date: Tue, 23 Jan 2024 11:26:09 +0200 -Subject: [PATCH] clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi - operation - -Without it system hangs upon wifi firmware load. It should be enabled by -remoteproc/wifi driver. Bindings already exist for it, so add it based -on vendor code. - -Signed-off-by: Mantas Pucka -Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/gcc-ipq6018.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq6018.c -+++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -3524,6 +3524,22 @@ static struct clk_branch gcc_prng_ahb_cl - }, - }; - -+static struct clk_branch gcc_qdss_at_clk = { -+ .halt_reg = 0x29024, -+ .clkr = { -+ .enable_reg = 0x29024, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "gcc_qdss_at_clk", -+ .parent_hws = (const struct clk_hw *[]){ -+ &qdss_at_clk_src.clkr.hw }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_qdss_dap_clk = { - .halt_reg = 0x29084, - .clkr = { -@@ -4363,6 +4379,7 @@ static struct clk_regmap *gcc_ipq6018_cl - [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr, - [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, -+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, - [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, - [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, - [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, diff --git a/target/linux/qualcommax/patches-6.6/0061-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch b/target/linux/qualcommax/patches-6.6/0061-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch deleted file mode 100644 index 9021b572e8..0000000000 --- a/target/linux/qualcommax/patches-6.6/0061-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 62a5df451ab911421da96655fcc4d1e269ff6e2f Mon Sep 17 00:00:00 2001 -From: Mantas Pucka -Date: Tue, 23 Jan 2024 18:09:20 +0200 -Subject: [PATCH] phy: qcom-qmp-usb: fix serdes init sequence for IPQ6018 - -Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018") -noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses -separate serdes init sequence for IPQ6018. Since already existing IPQ9574 -serdes init sequence is identical, just reuse it and fix failing USB3 mode -in IPQ6018. - -Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018") -Signed-off-by: Mantas Pucka -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/1706026160-17520-3-git-send-email-mantas@8devices.com -Signed-off-by: Vinod Koul ---- - drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++++++++++++++++- - 1 file changed, 19 insertions(+), 1 deletion(-) - ---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c -+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c -@@ -1314,6 +1314,26 @@ static const struct qmp_usb_offsets qmp_ - .rx = 0x1000, - }; - -+static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = { -+ .lanes = 1, -+ -+ .serdes_tbl = ipq9574_usb3_serdes_tbl, -+ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl), -+ .tx_tbl = msm8996_usb3_tx_tbl, -+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), -+ .rx_tbl = ipq8074_usb3_rx_tbl, -+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), -+ .pcs_tbl = ipq8074_usb3_pcs_tbl, -+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), -+ .clk_list = msm8996_phy_clk_l, -+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), -+ .reset_list = msm8996_usb3phy_reset_l, -+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), -+ .vreg_list = qmp_phy_vreg_l, -+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), -+ .regs = qmp_v3_usb3phy_regs_layout, -+}; -+ - static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { - .lanes = 1, - -@@ -2239,7 +2259,7 @@ err_node_put: - static const struct of_device_id qmp_usb_of_match_table[] = { - { - .compatible = "qcom,ipq6018-qmp-usb3-phy", -- .data = &ipq8074_usb3phy_cfg, -+ .data = &ipq6018_usb3phy_cfg, - }, { - .compatible = "qcom,ipq8074-qmp-usb3-phy", - .data = &ipq8074_usb3phy_cfg, diff --git a/target/linux/qualcommax/patches-6.6/0062-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch b/target/linux/qualcommax/patches-6.6/0062-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch deleted file mode 100644 index 16d2437490..0000000000 --- a/target/linux/qualcommax/patches-6.6/0062-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6a25e70214fde6dcf900271c819c8d7fe7b9a4b0 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 23 Nov 2023 13:12:54 +0100 -Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP4 SPI node - -Add node to support the QUP4 SPI controller inside of IPQ8074. -Some devices use this bus to communicate to a Bluetooth controller. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20231123121324.1046164-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -536,6 +536,20 @@ - status = "disabled"; - }; - -+ blsp1_spi4: spi@78b8000 { -+ compatible = "qcom,spi-qup-v2.2.1"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x78b8000 0x600>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ dmas = <&blsp_dma 18>, <&blsp_dma 19>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ - blsp1_i2c5: i2c@78b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.6/0063-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch b/target/linux/qualcommax/patches-6.6/0063-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch deleted file mode 100644 index e075c590fb..0000000000 --- a/target/linux/qualcommax/patches-6.6/0063-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001 -From: Paweł Owoc -Date: Wed, 13 Mar 2024 11:27:06 +0100 -Subject: [PATCH] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins - -gpio16 will only be used for LCD support, as its NAND/LCDC data[8] -so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8 -or 16-bit with only 8-bit one being supported in our case so that pin -is unused. - -It should be dropped from the default NAND pinctrl configuration -as its unused and only needed for LCD. - -Signed-off-by: Paweł Owoc -Reviewed-by: Kathiravan Thirumoorthy -Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -372,7 +372,7 @@ - "gpio5", "gpio6", "gpio7", - "gpio8", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", -- "gpio15", "gpio16", "gpio17"; -+ "gpio15", "gpio17"; - function = "qpic"; - drive-strength = <8>; - bias-disable; diff --git a/target/linux/qualcommax/patches-6.6/0065-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch b/target/linux/qualcommax/patches-6.6/0065-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch deleted file mode 100644 index 8e973e63f2..0000000000 --- a/target/linux/qualcommax/patches-6.6/0065-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 9cbaee8379e620f82112002f973adde19679df31 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:14:00 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq5018: add watchdog - -Add the required DT node for watchdog operation. - -Signed-off-by: Robert Marko -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20230816161455.3310629-2-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -181,6 +181,13 @@ - }; - }; - -+ watchdog: watchdog@b017000 { -+ compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; -+ reg = <0x0b017000 0x40>; -+ interrupts = ; -+ clocks = <&sleep_clk>; -+ }; -+ - timer@b120000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.6/0066-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch b/target/linux/qualcommax/patches-6.6/0066-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch deleted file mode 100644 index 46d3c61398..0000000000 --- a/target/linux/qualcommax/patches-6.6/0066-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 92dab9ea5f389c12828283146c60054642453a91 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:45:38 +0200 -Subject: [PATCH] dt-bindings: firmware: qcom,scm: support indicating SDI - default state - -IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that -means that WDT being asserted or just trying to reboot will hang the board -in the debug mode and only pulling the power and repowering will help. -Some IPQ4019 boards like Google WiFI have it enabled as well. - -So, lets add a boolean property to indicate that SDI is enabled by default -and thus needs to be disabled by the kernel. - -Signed-off-by: Robert Marko -Acked-by: Mukesh Ojha -Reviewed-by: Krzysztof Kozlowski -Reviewed-by: Brian Norris -Link: https://lore.kernel.org/r/20230816164641.3371878-1-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml -+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml -@@ -89,6 +89,14 @@ properties: - protocol to handle sleeping SCM calls. - maxItems: 1 - -+ qcom,sdi-enabled: -+ description: -+ Indicates that the SDI (Secure Debug Image) has been enabled by TZ -+ by default and it needs to be disabled. -+ If not disabled WDT assertion or reboot will cause the board to hang -+ in the debug mode. -+ type: boolean -+ - qcom,dload-mode: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: diff --git a/target/linux/qualcommax/patches-6.6/0067-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch b/target/linux/qualcommax/patches-6.6/0067-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch deleted file mode 100644 index 747ba7f285..0000000000 --- a/target/linux/qualcommax/patches-6.6/0067-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch +++ /dev/null @@ -1,83 +0,0 @@ -From ff4aa3bc98258a240b9bbab53fd8d2fb8184c485 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:45:39 +0200 -Subject: [PATCH] firmware: qcom_scm: disable SDI if required - -IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that -means that WDT being asserted or just trying to reboot will hang the board -in the debug mode and only pulling the power and repowering will help. -Some IPQ4019 boards like Google WiFI have it enabled as well. - -Luckily, SDI can be disabled via an SCM call. - -So, lets use the boolean DT property to identify boards that have SDI -enabled by default and use the SCM call to disable SDI during SCM probe. -It is important to disable it as soon as possible as we might have a WDT -assertion at any time which would then leave the board in debug mode, -thus disabling it during SCM removal is not enough. - -Signed-off-by: Robert Marko -Reviewed-by: Guru Das Srinagesh -Link: https://lore.kernel.org/r/20230816164641.3371878-2-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/firmware/qcom_scm.c | 30 ++++++++++++++++++++++++++++++ - drivers/firmware/qcom_scm.h | 1 + - 2 files changed, 31 insertions(+) - ---- a/drivers/firmware/qcom_scm.c -+++ b/drivers/firmware/qcom_scm.c -@@ -410,6 +410,29 @@ int qcom_scm_set_remote_state(u32 state, - } - EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); - -+static int qcom_scm_disable_sdi(void) -+{ -+ int ret; -+ struct qcom_scm_desc desc = { -+ .svc = QCOM_SCM_SVC_BOOT, -+ .cmd = QCOM_SCM_BOOT_SDI_CONFIG, -+ .args[0] = 1, /* Disable watchdog debug */ -+ .args[1] = 0, /* Disable SDI */ -+ .arginfo = QCOM_SCM_ARGS(2), -+ .owner = ARM_SMCCC_OWNER_SIP, -+ }; -+ struct qcom_scm_res res; -+ -+ ret = qcom_scm_clk_enable(); -+ if (ret) -+ return ret; -+ ret = qcom_scm_call(__scm->dev, &desc, &res); -+ -+ qcom_scm_clk_disable(); -+ -+ return ret ? : res.result[0]; -+} -+ - static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) - { - struct qcom_scm_desc desc = { -@@ -1474,6 +1497,13 @@ static int qcom_scm_probe(struct platfor - - __get_convention(); - -+ -+ /* -+ * Disable SDI if indicated by DT that it is enabled by default. -+ */ -+ if (of_property_read_bool(pdev->dev.of_node, "qcom,sdi-enabled")) -+ qcom_scm_disable_sdi(); -+ - /* - * If requested enable "download mode", from this point on warmboot - * will cause the boot stages to enter download mode, unless ---- a/drivers/firmware/qcom_scm.h -+++ b/drivers/firmware/qcom_scm.h -@@ -80,6 +80,7 @@ extern int scm_legacy_call(struct device - #define QCOM_SCM_SVC_BOOT 0x01 - #define QCOM_SCM_BOOT_SET_ADDR 0x01 - #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 -+#define QCOM_SCM_BOOT_SDI_CONFIG 0x09 - #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 - #define QCOM_SCM_BOOT_SET_ADDR_MC 0x11 - #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a diff --git a/target/linux/qualcommax/patches-6.6/0068-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.6/0068-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch deleted file mode 100644 index d36ccddd27..0000000000 --- a/target/linux/qualcommax/patches-6.6/0068-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch +++ /dev/null @@ -1,25 +0,0 @@ -From f6aa7386bc40b552eea8ec1b1d2168afe3b31110 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:45:40 +0200 -Subject: [PATCH] dt-bindings: firmware: qcom,scm: document IPQ5018 compatible - -It seems that IPQ5018 compatible was never documented in the bindings. - -Signed-off-by: Robert Marko -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20230816164641.3371878-3-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml -+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml -@@ -24,6 +24,7 @@ properties: - - qcom,scm-apq8064 - - qcom,scm-apq8084 - - qcom,scm-ipq4019 -+ - qcom,scm-ipq5018 - - qcom,scm-ipq5332 - - qcom,scm-ipq6018 - - qcom,scm-ipq806x diff --git a/target/linux/qualcommax/patches-6.6/0069-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch b/target/linux/qualcommax/patches-6.6/0069-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch deleted file mode 100644 index 6d598bf50f..0000000000 --- a/target/linux/qualcommax/patches-6.6/0069-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 79796e87215db9587d6c66ec6f6781e091bc6464 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Aug 2023 18:45:41 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq5018: indicate that SDI should be - disabled - -Now that SCM has support for indicating that SDI has been enabled by -default, lets set the property so SCM disables it during probing. - -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20230816164641.3371878-4-robimarko@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -57,6 +57,7 @@ - firmware { - scm { - compatible = "qcom,scm-ipq5018", "qcom,scm"; -+ qcom,sdi-enabled; - }; - }; - diff --git a/target/linux/qualcommax/patches-6.6/0070-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.6/0070-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch deleted file mode 100644 index 777212249e..0000000000 --- a/target/linux/qualcommax/patches-6.6/0070-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 1852dfaacd3f4358bbfca134b63a02bbb30c1136 Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Mon, 4 Sep 2023 12:06:32 +0530 -Subject: [PATCH] dt-bindings: phy: qcom,m31: Add IPQ5018 compatible - -IPQ5332 qcom,m31 phy driver can support IPQ5018. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Nitheesh Sekar -Link: https://lore.kernel.org/r/20230904063635.24975-2-quic_nsekar@quicinc.com -Signed-off-by: Vinod Koul ---- - .../devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml -+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml -@@ -17,7 +17,9 @@ description: - properties: - compatible: - items: -- - const: qcom,ipq5332-usb-hsphy -+ - enum: -+ - qcom,ipq5018-usb-hsphy -+ - qcom,ipq5332-usb-hsphy - - "#phy-cells": - const: 0 diff --git a/target/linux/qualcommax/patches-6.6/0071-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.6/0071-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch deleted file mode 100644 index 248b47c694..0000000000 --- a/target/linux/qualcommax/patches-6.6/0071-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 68320e35f8cb1987b4ad34347fc7033832da99e3 Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Mon, 4 Sep 2023 12:06:33 +0530 -Subject: [PATCH] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018 - -Add phy init sequence and compatible string for IPQ5018 -chipset. - -Signed-off-by: Nitheesh Sekar -Link: https://lore.kernel.org/r/20230904063635.24975-3-quic_nsekar@quicinc.com -Signed-off-by: Vinod Koul ---- - drivers/phy/qualcomm/phy-qcom-m31.c | 51 +++++++++++++++++++++++++++++ - 1 file changed, 51 insertions(+) - ---- a/drivers/phy/qualcomm/phy-qcom-m31.c -+++ b/drivers/phy/qualcomm/phy-qcom-m31.c -@@ -82,6 +82,50 @@ struct m31_priv_data { - unsigned int nregs; - }; - -+static const struct m31_phy_regs m31_ipq5018_regs[] = { -+ { -+ .off = USB_PHY_CFG0, -+ .val = UTMI_PHY_OVERRIDE_EN -+ }, -+ { -+ .off = USB_PHY_UTMI_CTRL5, -+ .val = POR_EN, -+ .delay = 15 -+ }, -+ { -+ .off = USB_PHY_FSEL_SEL, -+ .val = FREQ_SEL -+ }, -+ { -+ .off = USB_PHY_HS_PHY_CTRL_COMMON0, -+ .val = COMMONONN | FSEL | RETENABLEN -+ }, -+ { -+ .off = USB_PHY_REFCLK_CTRL, -+ .val = CLKCORE -+ }, -+ { -+ .off = USB_PHY_UTMI_CTRL5, -+ .val = POR_EN -+ }, -+ { -+ .off = USB_PHY_HS_PHY_CTRL2, -+ .val = USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN -+ }, -+ { -+ .off = USB_PHY_UTMI_CTRL5, -+ .val = 0x0 -+ }, -+ { -+ .off = USB_PHY_HS_PHY_CTRL2, -+ .val = USB2_SUSPEND_N | USB2_UTMI_CLK_EN -+ }, -+ { -+ .off = USB_PHY_CFG0, -+ .val = 0x0 -+ }, -+}; -+ - static struct m31_phy_regs m31_ipq5332_regs[] = { - { - USB_PHY_CFG0, -@@ -267,6 +311,12 @@ static int m31usb_phy_probe(struct platf - return PTR_ERR_OR_ZERO(phy_provider); - } - -+static const struct m31_priv_data m31_ipq5018_data = { -+ .ulpi_mode = false, -+ .regs = m31_ipq5018_regs, -+ .nregs = ARRAY_SIZE(m31_ipq5018_regs), -+}; -+ - static const struct m31_priv_data m31_ipq5332_data = { - .ulpi_mode = false, - .regs = m31_ipq5332_regs, -@@ -274,6 +324,7 @@ static const struct m31_priv_data m31_ip - }; - - static const struct of_device_id m31usb_phy_id_table[] = { -+ { .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data }, - { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data }, - { }, - }; diff --git a/target/linux/qualcommax/patches-6.6/0072-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.6/0072-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch deleted file mode 100644 index 146fcbff09..0000000000 --- a/target/linux/qualcommax/patches-6.6/0072-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 3865a64284cc4845c61cf3dc6c7246349d80cc49 Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Thu, 31 Aug 2023 08:35:03 +0530 -Subject: [PATCH] dt-bindings: usb: dwc3: Add IPQ5018 compatible - -Document the IPQ5018 dwc3 compatible. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Nitheesh Sekar -Link: https://lore.kernel.org/r/20230831030503.17100-1-quic_nsekar@quicinc.com -Signed-off-by: Greg Kroah-Hartman ---- - Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml -+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml -@@ -14,6 +14,7 @@ properties: - items: - - enum: - - qcom,ipq4019-dwc3 -+ - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - - qcom,ipq6018-dwc3 - - qcom,ipq8064-dwc3 -@@ -238,6 +239,7 @@ allOf: - compatible: - contains: - enum: -+ - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - - qcom,msm8994-dwc3 - - qcom,qcs404-dwc3 -@@ -411,6 +413,7 @@ allOf: - compatible: - contains: - enum: -+ - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - - qcom,sdm660-dwc3 - then: diff --git a/target/linux/qualcommax/patches-6.6/0073-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch b/target/linux/qualcommax/patches-6.6/0073-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch deleted file mode 100644 index 99fdae732a..0000000000 --- a/target/linux/qualcommax/patches-6.6/0073-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch +++ /dev/null @@ -1,86 +0,0 @@ -From e7166f2774aafefd29ff26ffbbb7f6d40ac8ea1c Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Mon, 4 Sep 2023 12:06:34 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq5018: Add USB related nodes - -Add USB phy and controller nodes. - -Co-developed-by: Amandeep Singh -Signed-off-by: Amandeep Singh -Signed-off-by: Nitheesh Sekar -Link: https://lore.kernel.org/r/20230904063635.24975-4-quic_nsekar@quicinc.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -94,6 +94,19 @@ - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - -+ usbphy0: phy@5b000 { -+ compatible = "qcom,ipq5018-usb-hsphy"; -+ reg = <0x0005b000 0x120>; -+ -+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; -+ -+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>; -+ -+ #phy-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq5018-tlmm"; - reg = <0x01000000 0x300000>; -@@ -156,6 +169,47 @@ - status = "disabled"; - }; - -+ usb: usb@8af8800 { -+ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; -+ reg = <0x08af8800 0x400>; -+ -+ interrupts = ; -+ interrupt-names = "hs_phy_irq"; -+ -+ clocks = <&gcc GCC_USB0_MASTER_CLK>, -+ <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, -+ <&gcc GCC_USB0_SLEEP_CLK>, -+ <&gcc GCC_USB0_MOCK_UTMI_CLK>; -+ clock-names = "core", -+ "iface", -+ "sleep", -+ "mock_utmi"; -+ -+ resets = <&gcc GCC_USB0_BCR>; -+ -+ qcom,select-utmi-as-pipe-clk; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ status = "disabled"; -+ -+ usb_dwc: usb@8a00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x08a00000 0xe000>; -+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; -+ clock-names = "ref"; -+ interrupts = ; -+ phy-names = "usb2-phy"; -+ phys = <&usbphy0>; -+ tx-fifo-resize; -+ snps,is-utmi-l1-suspend; -+ snps,hird-threshold = /bits/ 8 <0x0>; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ }; -+ }; -+ - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - reg = <0x0b000000 0x1000>, /* GICD */ diff --git a/target/linux/qualcommax/patches-6.6/0074-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch b/target/linux/qualcommax/patches-6.6/0074-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch deleted file mode 100644 index d0d9e45dec..0000000000 --- a/target/linux/qualcommax/patches-6.6/0074-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch +++ /dev/null @@ -1,56 +0,0 @@ -From a1f42e08f0f04b72a6597f080db4bfbb3737910c Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 4 Oct 2023 21:12:30 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq5018: add QUP1 SPI controller - -Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018. - -Signed-off-by: Robert Marko -Reviewed-by: Kathiravan Thirumoorthy -Link: https://lore.kernel.org/r/20231004191303.331055-1-robimarko@gmail.com -[bjorn: Padded address to 8 digits, fixed node sort order] -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -159,6 +159,16 @@ - status = "disabled"; - }; - -+ blsp_dma: dma-controller@7884000 { -+ compatible = "qcom,bam-v1.7.0"; -+ reg = <0x07884000 0x1d000>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "bam_clk"; -+ #dma-cells = <1>; -+ qcom,ee = <0>; -+ }; -+ - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; -@@ -169,6 +179,20 @@ - status = "disabled"; - }; - -+ blsp1_spi1: spi@78b5000 { -+ compatible = "qcom,spi-qup-v2.2.1"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x078b5000 0x600>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ dmas = <&blsp_dma 4>, <&blsp_dma 5>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ - usb: usb@8af8800 { - compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; - reg = <0x08af8800 0x400>; diff --git a/target/linux/qualcommax/patches-6.6/0075-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.6/0075-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch deleted file mode 100644 index 314afa76d2..0000000000 --- a/target/linux/qualcommax/patches-6.6/0075-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 4d45d56e17348c6b6bb2bce126a4a5ea97b19900 Mon Sep 17 00:00:00 2001 -From: Gokul Sriram Palanisamy -Date: Mon, 25 Sep 2023 15:58:24 +0530 -Subject: [PATCH] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible - -Add IPQ5018 compatible to A53 PLL bindings. - -Signed-off-by: Gokul Sriram Palanisamy -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20230925102826.405446-2-quic_gokulsri@quicinc.com -Signed-off-by: Bjorn Andersson ---- - Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml -+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml -@@ -16,6 +16,7 @@ description: - properties: - compatible: - enum: -+ - qcom,ipq5018-a53pll - - qcom,ipq5332-a53pll - - qcom,ipq6018-a53pll - - qcom,ipq8074-a53pll diff --git a/target/linux/qualcommax/patches-6.6/0076-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.6/0076-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch deleted file mode 100644 index 46dede07ca..0000000000 --- a/target/linux/qualcommax/patches-6.6/0076-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 50492f929486c044b43cb3e2c0e040aa9b61ea2b Mon Sep 17 00:00:00 2001 -From: Gokul Sriram Palanisamy -Date: Mon, 25 Sep 2023 15:58:25 +0530 -Subject: [PATCH] clk: qcom: apss-ipq-pll: add support for IPQ5018 - -IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets, -add configuration values and the compatible. - -Co-developed-by: Sricharan Ramabadhran -Signed-off-by: Sricharan Ramabadhran -Signed-off-by: Gokul Sriram Palanisamy -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20230925102826.405446-3-quic_gokulsri@quicinc.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/apss-ipq-pll.c | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/drivers/clk/qcom/apss-ipq-pll.c -+++ b/drivers/clk/qcom/apss-ipq-pll.c -@@ -73,6 +73,20 @@ static struct clk_alpha_pll ipq_pll_stro - }, - }; - -+static const struct alpha_pll_config ipq5018_pll_config = { -+ .l = 0x32, -+ .config_ctl_val = 0x4001075b, -+ .config_ctl_hi_val = 0x304, -+ .main_output_mask = BIT(0), -+ .aux_output_mask = BIT(1), -+ .early_output_mask = BIT(3), -+ .alpha_en_mask = BIT(24), -+ .status_val = 0x3, -+ .status_mask = GENMASK(10, 8), -+ .lock_det = BIT(2), -+ .test_ctl_hi_val = 0x00400003, -+}; -+ - static const struct alpha_pll_config ipq5332_pll_config = { - .l = 0x2d, - .config_ctl_val = 0x4001075b, -@@ -129,6 +143,12 @@ struct apss_pll_data { - const struct alpha_pll_config *pll_config; - }; - -+static const struct apss_pll_data ipq5018_pll_data = { -+ .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, -+ .pll = &ipq_pll_stromer_plus, -+ .pll_config = &ipq5018_pll_config, -+}; -+ - static struct apss_pll_data ipq5332_pll_data = { - .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, - .pll = &ipq_pll_stromer_plus, -@@ -195,6 +215,7 @@ static int apss_ipq_pll_probe(struct pla - } - - static const struct of_device_id apss_ipq_pll_match_table[] = { -+ { .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data }, - { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, - { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, - { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, diff --git a/target/linux/qualcommax/patches-6.6/0077-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch b/target/linux/qualcommax/patches-6.6/0077-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch deleted file mode 100644 index 72bec54cb3..0000000000 --- a/target/linux/qualcommax/patches-6.6/0077-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 3e4b53e04281ed3d9c7a4329c027097265c04d54 Mon Sep 17 00:00:00 2001 -From: Gokul Sriram Palanisamy -Date: Mon, 25 Sep 2023 15:58:26 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq5018: enable the CPUFreq support - -Add the APCS, A53 PLL, cpu-opp-table nodes to set -the CPU frequency at 800MHz (idle) or 1.008GHz. - -Co-developed-by: Sricharan Ramabadhran -Signed-off-by: Sricharan Ramabadhran -Signed-off-by: Gokul Sriram Palanisamy -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20230925102826.405446-4-quic_gokulsri@quicinc.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++ - 1 file changed, 40 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -5,6 +5,7 @@ - * Copyright (c) 2023 The Linux Foundation. All rights reserved. - */ - -+#include - #include - #include - #include -@@ -36,6 +37,8 @@ - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; -+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; -+ operating-points-v2 = <&cpu_opp_table>; - }; - - CPU1: cpu@1 { -@@ -44,6 +47,8 @@ - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; -+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; -+ operating-points-v2 = <&cpu_opp_table>; - }; - - L2_0: l2-cache { -@@ -54,6 +59,25 @@ - }; - }; - -+ cpu_opp_table: opp-table-cpu { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ /* -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <200000>; -+ }; -+ */ -+ -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <200000>; -+ }; -+ }; -+ - firmware { - scm { - compatible = "qcom,scm-ipq5018", "qcom,scm"; -@@ -267,6 +291,24 @@ - clocks = <&sleep_clk>; - }; - -+ apcs_glb: mailbox@b111000 { -+ compatible = "qcom,ipq5018-apcs-apps-global", -+ "qcom,ipq6018-apcs-apps-global"; -+ reg = <0x0b111000 0x1000>; -+ #clock-cells = <1>; -+ clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; -+ clock-names = "pll", "xo", "gpll0"; -+ #mbox-cells = <1>; -+ }; -+ -+ a53pll: clock@b116000 { -+ compatible = "qcom,ipq5018-a53pll"; -+ reg = <0x0b116000 0x40>; -+ #clock-cells = <0>; -+ clocks = <&xo_board_clk>; -+ clock-names = "xo"; -+ }; -+ - timer@b120000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.6/0078-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch b/target/linux/qualcommax/patches-6.6/0078-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch deleted file mode 100644 index 97631e715a..0000000000 --- a/target/linux/qualcommax/patches-6.6/0078-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch +++ /dev/null @@ -1,66 +0,0 @@ -From a427dd16e61f3d145bc24f0ed09692fc25931250 Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Wed, 25 Oct 2023 22:12:12 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq5018: add few more reserved memory - regions - -Like all other IPQ SoCs, bootloader will collect the system RAM contents -upon crash for the post morterm analysis. If we don't reserve the memory -region used by bootloader, obviously linux will consume it and upon next -boot on crash, bootloader will be loaded in the same region, which will -lead to loose some of the data, sometimes we may miss out critical -information. So lets reserve the region used by the bootloader. - -Similarly SBL copies some data into the reserved region and it will be -used in the crash scenario. So reserve 1MB for SBL as well. - -While at it, enable the SMEM support along with TCSR mutex. - -Signed-off-by: Kathiravan Thirumoorthy -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20231025-ipq5018-misc-v1-1-7d14fde97fe7@quicinc.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -106,6 +106,24 @@ - #size-cells = <2>; - ranges; - -+ bootloader@4a800000 { -+ reg = <0x0 0x4a800000 0x0 0x200000>; -+ no-map; -+ }; -+ -+ sbl@4aa00000 { -+ reg = <0x0 0x4aa00000 0x0 0x100000>; -+ no-map; -+ }; -+ -+ smem@4ab00000 { -+ compatible = "qcom,smem"; -+ reg = <0x0 0x4ab00000 0x0 0x100000>; -+ no-map; -+ -+ hwlocks = <&tcsr_mutex 3>; -+ }; -+ - tz_region: tz@4ac00000 { - reg = <0x0 0x4ac00000 0x0 0x200000>; - no-map; -@@ -166,6 +184,12 @@ - #power-domain-cells = <1>; - }; - -+ tcsr_mutex: hwlock@1905000 { -+ compatible = "qcom,tcsr-mutex"; -+ reg = <0x01905000 0x20000>; -+ #hwlock-cells = <1>; -+ }; -+ - sdhc_1: mmc@7804000 { - compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x7804000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.6/0080-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch b/target/linux/qualcommax/patches-6.6/0080-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch deleted file mode 100644 index ea6f61b57f..0000000000 --- a/target/linux/qualcommax/patches-6.6/0080-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch +++ /dev/null @@ -1,83 +0,0 @@ -From: Gabor Juhos -Subject: [PATCH] clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure -Date: Fri, 15 Mar 2024 17:16:41 +0100 - -Booting v6.8 results in a hang on various IPQ5018 based boards. -Investigating the problem showed that the hang happens when the -clk_alpha_pll_stromer_plus_set_rate() function tries to write -into the PLL_MODE register of the APSS PLL. - -Checking the downstream code revealed that it uses [1] stromer -specific operations for IPQ5018, whereas in the current code -the stromer plus specific operations are used. - -The ops in the 'ipq_pll_stromer_plus' clock definition can't be -changed since that is needed for IPQ5332, so add a new alpha pll -clock declaration which uses the correct stromer ops and use this -new clock for IPQ5018 to avoid the boot failure. - -Also, change pll_type in 'ipq5018_pll_data' to -CLK_ALPHA_PLL_TYPE_STROMER to better reflect that it is a Stromer -PLL and change the apss_ipq_pll_probe() function accordingly. - -1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c#L67 - -Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018") -Signed-off-by: Gabor Juhos ---- - drivers/clk/qcom/apss-ipq-pll.c | 30 +++++++++++++++++++++++++++--- - 1 file changed, 27 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/apss-ipq-pll.c -+++ b/drivers/clk/qcom/apss-ipq-pll.c -@@ -55,6 +55,29 @@ static struct clk_alpha_pll ipq_pll_huay - }, - }; - -+static struct clk_alpha_pll ipq_pll_stromer = { -+ .offset = 0x0, -+ /* -+ * Reuse CLK_ALPHA_PLL_TYPE_STROMER_PLUS register offsets. -+ * Although this is a bit confusing, but the offset values -+ * are correct nevertheless. -+ */ -+ .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], -+ .flags = SUPPORTS_DYNAMIC_UPDATE, -+ .clkr = { -+ .enable_reg = 0x0, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "a53pll", -+ .parent_data = &(const struct clk_parent_data) { -+ .fw_name = "xo", -+ }, -+ .num_parents = 1, -+ .ops = &clk_alpha_pll_stromer_ops, -+ }, -+ }, -+}; -+ - static struct clk_alpha_pll ipq_pll_stromer_plus = { - .offset = 0x0, - .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], -@@ -144,8 +167,8 @@ struct apss_pll_data { - }; - - static const struct apss_pll_data ipq5018_pll_data = { -- .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, -- .pll = &ipq_pll_stromer_plus, -+ .pll_type = CLK_ALPHA_PLL_TYPE_STROMER, -+ .pll = &ipq_pll_stromer, - .pll_config = &ipq5018_pll_config, - }; - -@@ -203,7 +226,8 @@ static int apss_ipq_pll_probe(struct pla - - if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) - clk_alpha_pll_configure(data->pll, regmap, data->pll_config); -- else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) -+ else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER || -+ data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) - clk_stromer_pll_configure(data->pll, regmap, data->pll_config); - - ret = devm_clk_register_regmap(dev, &data->pll->clkr); diff --git a/target/linux/qualcommax/patches-6.6/0081-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.6/0081-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch deleted file mode 100644 index 4bf0598c36..0000000000 --- a/target/linux/qualcommax/patches-6.6/0081-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch +++ /dev/null @@ -1,32 +0,0 @@ -From: Gabor Juhos -Subject: [PATCH] clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018 -Date: Tue, 26 Mar 2024 14:34:11 +0100 - -According to ipq5018.dtsi, the maximum supported rate by the -CPU is 1.008 GHz on the IPQ5018 platform, however the current -configuration of the PLL results in 1.2 GHz rate. - -Change the 'L' value in the PLL configuration to limit the -rate to 1.008 GHz. The downstream kernel also uses the same -value [1]. Also add a comment to indicate the desired -frequency. - -[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c?ref_type=heads#L151 - -Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018") -Signed-off-by: Gabor Juhos ---- - drivers/clk/qcom/apss-ipq-pll.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/apss-ipq-pll.c -+++ b/drivers/clk/qcom/apss-ipq-pll.c -@@ -97,7 +97,7 @@ static struct clk_alpha_pll ipq_pll_stro - }; - - static const struct alpha_pll_config ipq5018_pll_config = { -- .l = 0x32, -+ .l = 0x2a, - .config_ctl_val = 0x4001075b, - .config_ctl_hi_val = 0x304, - .main_output_mask = BIT(0), diff --git a/target/linux/qualcommax/patches-6.6/0082-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch b/target/linux/qualcommax/patches-6.6/0082-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch deleted file mode 100644 index ddd54079fb..0000000000 --- a/target/linux/qualcommax/patches-6.6/0082-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch +++ /dev/null @@ -1,26 +0,0 @@ -From f2743ae3ff84579981ac513f512b9df945d109c0 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Thu, 20 Jun 2024 23:01:21 +0800 -Subject: [PATCH] clk: qcom: gcc-ipq6018: update sdcc max clock frequency - -The mmc controller of the IPQ6018 does not support HS400 mode. -So adjust the maximum clock frequency of sdcc to 200 MHz (HS200). - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/gcc-ipq6018.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/qcom/gcc-ipq6018.c -+++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_a - F(96000000, P_GPLL2, 12, 0, 0), - F(177777778, P_GPLL0, 4.5, 0, 0), - F(192000000, P_GPLL2, 6, 0, 0), -- F(384000000, P_GPLL2, 3, 0, 0), -+ F(200000000, P_GPLL0, 4, 0, 0), - { } - }; - diff --git a/target/linux/qualcommax/patches-6.6/0083-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch b/target/linux/qualcommax/patches-6.6/0083-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch deleted file mode 100644 index ed4b6d9e6d..0000000000 --- a/target/linux/qualcommax/patches-6.6/0083-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 5db216f6e1f85394e79dca74ceceb83b2f8566b5 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Thu, 20 Jun 2024 23:01:22 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add sdhci node - -Add node to support mmc controller inside of IPQ6018. -This controller supports both eMMC and SD cards. - -Tested with: - eMMC (HS200) - SD Card (SDR50/SDR104) - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20240620150122.1406631-3-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -470,6 +470,25 @@ - }; - }; - -+ sdhc: mmc@7804000 { -+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; -+ reg = <0x0 0x07804000 0x0 0x1000>, -+ <0x0 0x07805000 0x0 0x1000>; -+ reg-names = "hc", "cqhci"; -+ -+ interrupts = , -+ ; -+ interrupt-names = "hc_irq", "pwr_irq"; -+ -+ clocks = <&gcc GCC_SDCC1_AHB_CLK>, -+ <&gcc GCC_SDCC1_APPS_CLK>, -+ <&xo>; -+ clock-names = "iface", "core", "xo"; -+ resets = <&gcc GCC_SDCC1_BCR>; -+ max-frequency = <192000000>; -+ status = "disabled"; -+ }; -+ - blsp_dma: dma-controller@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0 0x07884000 0x0 0x2b000>; diff --git a/target/linux/qualcommax/patches-6.6/0084-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch b/target/linux/qualcommax/patches-6.6/0084-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch deleted file mode 100644 index 6a1c93b869..0000000000 --- a/target/linux/qualcommax/patches-6.6/0084-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch +++ /dev/null @@ -1,381 +0,0 @@ -From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Tue, 22 Oct 2024 17:47:26 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case - -DTS coding style expects labels to be lowercase. No functional impact. -Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++--- - arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++----- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++------- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++----- - arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++-------------- - 5 files changed, 61 insertions(+), 61 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -31,27 +31,27 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x80000>; ---- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi -@@ -30,47 +30,47 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- CPU2: cpu@2 { -+ cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- CPU3: cpu@3 { -+ cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -34,12 +34,12 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -47,12 +47,12 @@ - #cooling-cells = <2>; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -60,12 +60,12 @@ - #cooling-cells = <2>; - }; - -- CPU2: cpu@2 { -+ cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -73,12 +73,12 @@ - #cooling-cells = <2>; - }; - -- CPU3: cpu@3 { -+ cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x3>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -86,7 +86,7 @@ - #cooling-cells = <2>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; -@@ -993,10 +993,10 @@ - cooling-maps { - map0 { - trip = <&cpu_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -32,39 +32,39 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - enable-method = "psci"; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - }; - -- CPU2: cpu@2 { -+ cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - }; - -- CPU3: cpu@3 { -+ cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x3>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; ---- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -33,12 +33,12 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -46,12 +46,12 @@ - #cooling-cells = <2>; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x1>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -59,12 +59,12 @@ - #cooling-cells = <2>; - }; - -- CPU2: cpu@2 { -+ cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x2>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -72,12 +72,12 @@ - #cooling-cells = <2>; - }; - -- CPU3: cpu@3 { -+ cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x3>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -85,7 +85,7 @@ - #cooling-cells = <2>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; -@@ -845,10 +845,10 @@ - cooling-maps { - map0 { - trip = <&cpu0_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -@@ -875,10 +875,10 @@ - cooling-maps { - map0 { - trip = <&cpu1_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -@@ -905,10 +905,10 @@ - cooling-maps { - map0 { - trip = <&cpu2_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -@@ -935,10 +935,10 @@ - cooling-maps { - map0 { - trip = <&cpu3_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; diff --git a/target/linux/qualcommax/patches-6.6/0085-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch b/target/linux/qualcommax/patches-6.6/0085-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch deleted file mode 100644 index 5a5a7019ab..0000000000 --- a/target/linux/qualcommax/patches-6.6/0085-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 144230e5840c09984ad743c3df9de5fb443159a9 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:18 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency - -The final version of IPQ6000 (SoC id: IPQ6000, SBL version: -BOOT.XF.0.3-00086-IPQ60xxLZB-1) has a max design frequency -of 1.2GHz, so add this CPU frequency. - -Signed-off-by: Chukun Pan -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20250210070122.208842-2-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -119,6 +119,13 @@ - clock-latency-ns = <200000>; - }; - -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <850000>; -+ opp-supported-hw = <0x4>; -+ clock-latency-ns = <200000>; -+ }; -+ - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <862500>; diff --git a/target/linux/qualcommax/patches-6.6/0086-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch b/target/linux/qualcommax/patches-6.6/0086-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch deleted file mode 100644 index f87356c35b..0000000000 --- a/target/linux/qualcommax/patches-6.6/0086-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a96e765a7b3f64429f7eec3471a2093355ab041e Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:19 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency - -The early version of IPQ6000 (SoC id: IPQ6018, SBL version: -BOOT.XF.0.3-00077-IPQ60xxLZB-2) and IPQ6005 SoCs can reach -a max frequency of 1.5GHz, so add this CPU frequency. - -Signed-off-by: Chukun Pan -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20250210070122.208842-3-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -140,6 +140,13 @@ - clock-latency-ns = <200000>; - }; - -+ opp-1512000000 { -+ opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <937500>; -+ opp-supported-hw = <0x2>; -+ clock-latency-ns = <200000>; -+ }; -+ - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <987500>; diff --git a/target/linux/qualcommax/patches-6.6/0087-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch b/target/linux/qualcommax/patches-6.6/0087-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch deleted file mode 100644 index 505a027c2e..0000000000 --- a/target/linux/qualcommax/patches-6.6/0087-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 0c4c0f14b7d704bcb728d018a74788771dc9286b Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:20 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsi - -Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 -pmic was never part of the IPQ60xx SoC, it's optional, so we moved -it out of the soc dtsi. - -Signed-off-by: Chukun Pan -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20250210070122.208842-4-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- - arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 35 ++++++++++++++++++++++++++++ - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 ----------- - 3 files changed, 36 insertions(+), 15 deletions(-) - create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi - ---- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts -+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts -@@ -7,7 +7,7 @@ - - /dts-v1/; - --#include "ipq6018.dtsi" -+#include "ipq6018-mp5496.dtsi" - - / { - model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; ---- /dev/null -+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -@@ -0,0 +1,35 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that -+ * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC. -+ */ -+ -+#include "ipq6018.dtsi" -+ -+&cpu0 { -+ cpu-supply = <&ipq6018_s2>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&ipq6018_s2>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&ipq6018_s2>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&ipq6018_s2>; -+}; -+ -+&rpm_requests { -+ regulators { -+ compatible = "qcom,rpm-mp5496-regulators"; -+ -+ ipq6018_s2: s2 { -+ regulator-min-microvolt = <725000>; -+ regulator-max-microvolt = <1062500>; -+ regulator-always-on; -+ }; -+ }; -+}; ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -43,7 +43,6 @@ - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -- cpu-supply = <&ipq6018_s2>; - #cooling-cells = <2>; - }; - -@@ -56,7 +55,6 @@ - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -- cpu-supply = <&ipq6018_s2>; - #cooling-cells = <2>; - }; - -@@ -69,7 +67,6 @@ - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -- cpu-supply = <&ipq6018_s2>; - #cooling-cells = <2>; - }; - -@@ -82,7 +79,6 @@ - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -- cpu-supply = <&ipq6018_s2>; - #cooling-cells = <2>; - }; - -@@ -184,16 +180,6 @@ - rpm_requests: rpm-requests { - compatible = "qcom,rpm-ipq6018"; - qcom,glink-channels = "rpm_requests"; -- -- regulators { -- compatible = "qcom,rpm-mp5496-regulators"; -- -- ipq6018_s2: s2 { -- regulator-min-microvolt = <725000>; -- regulator-max-microvolt = <1062500>; -- regulator-always-on; -- }; -- }; - }; - }; - }; diff --git a/target/linux/qualcommax/patches-6.6/0088-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch b/target/linux/qualcommax/patches-6.6/0088-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch deleted file mode 100644 index 120ce53f8c..0000000000 --- a/target/linux/qualcommax/patches-6.6/0088-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch +++ /dev/null @@ -1,50 +0,0 @@ -From e60f872c2dc4c1d9227977c8714373fe6328699c Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:21 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: rename labels of mp5496 regulator - -Change the labels of mp5496 regulator from ipq6018 to mp5496. - -Suggested-by: Konrad Dybcio -Suggested-by: Dmitry Baryshkov -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20250210070122.208842-5-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -@@ -7,26 +7,26 @@ - #include "ipq6018.dtsi" - - &cpu0 { -- cpu-supply = <&ipq6018_s2>; -+ cpu-supply = <&mp5496_s2>; - }; - - &cpu1 { -- cpu-supply = <&ipq6018_s2>; -+ cpu-supply = <&mp5496_s2>; - }; - - &cpu2 { -- cpu-supply = <&ipq6018_s2>; -+ cpu-supply = <&mp5496_s2>; - }; - - &cpu3 { -- cpu-supply = <&ipq6018_s2>; -+ cpu-supply = <&mp5496_s2>; - }; - - &rpm_requests { - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - -- ipq6018_s2: s2 { -+ mp5496_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; diff --git a/target/linux/qualcommax/patches-6.6/0089-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch b/target/linux/qualcommax/patches-6.6/0089-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch deleted file mode 100644 index ce98c62f83..0000000000 --- a/target/linux/qualcommax/patches-6.6/0089-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a566fb9ba8ffecb56c50729390a9ea076f5c9532 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:22 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator - -Add LDOA2 regulator from MP5496 to support SDCC voltage scaling. - -Suggested-by: Robert Marko -Signed-off-by: Chukun Pan -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20250210070122.208842-6-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -@@ -31,5 +31,14 @@ - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; -+ -+ mp5496_l2: l2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; - }; - }; -+ -+&sdhc { -+ vqmmc-supply = <&mp5496_l2>; -+}; diff --git a/target/linux/qualcommax/patches-6.6/0090-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch b/target/linux/qualcommax/patches-6.6/0090-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch deleted file mode 100644 index 937e644626..0000000000 --- a/target/linux/qualcommax/patches-6.6/0090-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch +++ /dev/null @@ -1,83 +0,0 @@ -From d06b1043644a1831ab141bbee2669002bba15b0f Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 20 Dec 2023 23:17:22 +0100 -Subject: [PATCH] clk: qcom: clk-rcg: introduce support for multiple conf for - same freq - -Some RCG frequency can be reached by multiple configuration. - -We currently declare multiple configuration for the same frequency but -that is not supported and always the first configuration will be taken. - -These multiple configuration are needed as based on the current parent -configuration, it may be needed to use a different configuration to -reach the same frequency. - -To handle this introduce 3 new macro, C, FM and FMS: - -- C is used to declare a freq_conf where src, pre_div, m and n are - provided. - -- FM is used to declare a freq_multi_tbl with the frequency and an - array of confs to insert all the config for the provided frequency. - -- FMS is used to declare a freq_multi_tbl with the frequency and an - array of a single conf with the provided src, pre_div, m and n. - -Struct clk_rcg2 is changed to add a union type to reference a simple -freq_tbl or a complex freq_multi_tbl. - -Signed-off-by: Christian Marangi -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20231220221724.3822-2-ansuelsmth@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/clk-rcg.h | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/clk-rcg.h -+++ b/drivers/clk/qcom/clk-rcg.h -@@ -17,6 +17,23 @@ struct freq_tbl { - u16 n; - }; - -+#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) } -+#define FM(f, confs) { (f), ARRAY_SIZE(confs), (confs) } -+#define FMS(f, s, h, m, n) { (f), 1, (const struct freq_conf []){ C(s, h, m, n) } } -+ -+struct freq_conf { -+ u8 src; -+ u8 pre_div; -+ u16 m; -+ u16 n; -+}; -+ -+struct freq_multi_tbl { -+ unsigned long freq; -+ size_t num_confs; -+ const struct freq_conf *confs; -+}; -+ - /** - * struct mn - M/N:D counter - * @mnctr_en_bit: bit to enable mn counter -@@ -138,6 +155,7 @@ extern const struct clk_ops clk_dyn_rcg_ - * @safe_src_index: safe src index value - * @parent_map: map from software's parent index to hardware's src_sel field - * @freq_tbl: frequency table -+ * @freq_multi_tbl: frequency table for clocks reachable with multiple RCGs conf - * @clkr: regmap clock handle - * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG - * @parked_cfg: cached value of the CFG register for parked RCGs -@@ -149,7 +167,10 @@ struct clk_rcg2 { - u8 hid_width; - u8 safe_src_index; - const struct parent_map *parent_map; -- const struct freq_tbl *freq_tbl; -+ union { -+ const struct freq_tbl *freq_tbl; -+ const struct freq_multi_tbl *freq_multi_tbl; -+ }; - struct clk_regmap clkr; - u8 cfg_off; - u32 parked_cfg; diff --git a/target/linux/qualcommax/patches-6.6/0091-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch b/target/linux/qualcommax/patches-6.6/0091-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch deleted file mode 100644 index 478f60ed44..0000000000 --- a/target/linux/qualcommax/patches-6.6/0091-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch +++ /dev/null @@ -1,296 +0,0 @@ -From 89da22456af0762477d8c1345fdd17961b3ada80 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 20 Dec 2023 23:17:23 +0100 -Subject: [PATCH] clk: qcom: clk-rcg2: add support for rcg2 freq multi ops - -Some RCG frequency can be reached by multiple configuration. - -Add clk_rcg2_fm_ops ops to support these special RCG configurations. - -These alternative ops will select the frequency using a CEIL policy. - -When the correct frequency is found, the correct config is selected by -calculating the final rate (by checking the defined parent and values -in the config that is being checked) and deciding based on the one that -is less different than the requested one. - -These check are skipped if there is just one config for the requested -freq. - -qcom_find_freq_multi is added to search the freq with the new struct -freq_multi_tbl. -__clk_rcg2_select_conf is used to select the correct conf by simulating -the final clock. -If a conf can't be found due to parent not reachable, a WARN is printed -and -EINVAL is returned. - -Tested-by: Wei Lei -Signed-off-by: Christian Marangi -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20231220221724.3822-3-ansuelsmth@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/clk-rcg.h | 1 + - drivers/clk/qcom/clk-rcg2.c | 166 ++++++++++++++++++++++++++++++++++++ - drivers/clk/qcom/common.c | 18 ++++ - drivers/clk/qcom/common.h | 2 + - 4 files changed, 187 insertions(+) - ---- a/drivers/clk/qcom/clk-rcg.h -+++ b/drivers/clk/qcom/clk-rcg.h -@@ -190,6 +190,7 @@ struct clk_rcg2_gfx3d { - - extern const struct clk_ops clk_rcg2_ops; - extern const struct clk_ops clk_rcg2_floor_ops; -+extern const struct clk_ops clk_rcg2_fm_ops; - extern const struct clk_ops clk_rcg2_mux_closest_ops; - extern const struct clk_ops clk_edp_pixel_ops; - extern const struct clk_ops clk_byte_ops; ---- a/drivers/clk/qcom/clk-rcg2.c -+++ b/drivers/clk/qcom/clk-rcg2.c -@@ -260,6 +260,115 @@ static int _freq_tbl_determine_rate(stru - return 0; - } - -+static const struct freq_conf * -+__clk_rcg2_select_conf(struct clk_hw *hw, const struct freq_multi_tbl *f, -+ unsigned long req_rate) -+{ -+ unsigned long rate_diff, best_rate_diff = ULONG_MAX; -+ const struct freq_conf *conf, *best_conf = NULL; -+ struct clk_rcg2 *rcg = to_clk_rcg2(hw); -+ const char *name = clk_hw_get_name(hw); -+ unsigned long parent_rate, rate; -+ struct clk_hw *p; -+ int index, i; -+ -+ /* Exit early if only one config is defined */ -+ if (f->num_confs == 1) { -+ best_conf = f->confs; -+ goto exit; -+ } -+ -+ /* Search in each provided config the one that is near the wanted rate */ -+ for (i = 0, conf = f->confs; i < f->num_confs; i++, conf++) { -+ index = qcom_find_src_index(hw, rcg->parent_map, conf->src); -+ if (index < 0) -+ continue; -+ -+ p = clk_hw_get_parent_by_index(hw, index); -+ if (!p) -+ continue; -+ -+ parent_rate = clk_hw_get_rate(p); -+ rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div); -+ -+ if (rate == req_rate) { -+ best_conf = conf; -+ goto exit; -+ } -+ -+ rate_diff = abs_diff(req_rate, rate); -+ if (rate_diff < best_rate_diff) { -+ best_rate_diff = rate_diff; -+ best_conf = conf; -+ } -+ } -+ -+ /* -+ * Very unlikely. Warn if we couldn't find a correct config -+ * due to parent not found in every config. -+ */ -+ if (unlikely(!best_conf)) { -+ WARN(1, "%s: can't find a configuration for rate %lu\n", -+ name, req_rate); -+ return ERR_PTR(-EINVAL); -+ } -+ -+exit: -+ return best_conf; -+} -+ -+static int _freq_tbl_fm_determine_rate(struct clk_hw *hw, const struct freq_multi_tbl *f, -+ struct clk_rate_request *req) -+{ -+ unsigned long clk_flags, rate = req->rate; -+ struct clk_rcg2 *rcg = to_clk_rcg2(hw); -+ const struct freq_conf *conf; -+ struct clk_hw *p; -+ int index; -+ -+ f = qcom_find_freq_multi(f, rate); -+ if (!f || !f->confs) -+ return -EINVAL; -+ -+ conf = __clk_rcg2_select_conf(hw, f, rate); -+ if (IS_ERR(conf)) -+ return PTR_ERR(conf); -+ index = qcom_find_src_index(hw, rcg->parent_map, conf->src); -+ if (index < 0) -+ return index; -+ -+ clk_flags = clk_hw_get_flags(hw); -+ p = clk_hw_get_parent_by_index(hw, index); -+ if (!p) -+ return -EINVAL; -+ -+ if (clk_flags & CLK_SET_RATE_PARENT) { -+ rate = f->freq; -+ if (conf->pre_div) { -+ if (!rate) -+ rate = req->rate; -+ rate /= 2; -+ rate *= conf->pre_div + 1; -+ } -+ -+ if (conf->n) { -+ u64 tmp = rate; -+ -+ tmp = tmp * conf->n; -+ do_div(tmp, conf->m); -+ rate = tmp; -+ } -+ } else { -+ rate = clk_hw_get_rate(p); -+ } -+ -+ req->best_parent_hw = p; -+ req->best_parent_rate = rate; -+ req->rate = f->freq; -+ -+ return 0; -+} -+ - static int clk_rcg2_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) - { -@@ -276,6 +385,14 @@ static int clk_rcg2_determine_floor_rate - return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); - } - -+static int clk_rcg2_fm_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct clk_rcg2 *rcg = to_clk_rcg2(hw); -+ -+ return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req); -+} -+ - static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, - u32 *_cfg) - { -@@ -371,6 +488,30 @@ static int __clk_rcg2_set_rate(struct cl - return clk_rcg2_configure(rcg, f); - } - -+static int __clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate) -+{ -+ struct clk_rcg2 *rcg = to_clk_rcg2(hw); -+ const struct freq_multi_tbl *f; -+ const struct freq_conf *conf; -+ struct freq_tbl f_tbl = {}; -+ -+ f = qcom_find_freq_multi(rcg->freq_multi_tbl, rate); -+ if (!f || !f->confs) -+ return -EINVAL; -+ -+ conf = __clk_rcg2_select_conf(hw, f, rate); -+ if (IS_ERR(conf)) -+ return PTR_ERR(conf); -+ -+ f_tbl.freq = f->freq; -+ f_tbl.src = conf->src; -+ f_tbl.pre_div = conf->pre_div; -+ f_tbl.m = conf->m; -+ f_tbl.n = conf->n; -+ -+ return clk_rcg2_configure(rcg, &f_tbl); -+} -+ - static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) - { -@@ -383,6 +524,12 @@ static int clk_rcg2_set_floor_rate(struc - return __clk_rcg2_set_rate(hw, rate, FLOOR); - } - -+static int clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ return __clk_rcg2_fm_set_rate(hw, rate); -+} -+ - static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate, u8 index) - { -@@ -395,6 +542,12 @@ static int clk_rcg2_set_floor_rate_and_p - return __clk_rcg2_set_rate(hw, rate, FLOOR); - } - -+static int clk_rcg2_fm_set_rate_and_parent(struct clk_hw *hw, -+ unsigned long rate, unsigned long parent_rate, u8 index) -+{ -+ return __clk_rcg2_fm_set_rate(hw, rate); -+} -+ - static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) - { - struct clk_rcg2 *rcg = to_clk_rcg2(hw); -@@ -505,6 +658,19 @@ const struct clk_ops clk_rcg2_floor_ops - }; - EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); - -+const struct clk_ops clk_rcg2_fm_ops = { -+ .is_enabled = clk_rcg2_is_enabled, -+ .get_parent = clk_rcg2_get_parent, -+ .set_parent = clk_rcg2_set_parent, -+ .recalc_rate = clk_rcg2_recalc_rate, -+ .determine_rate = clk_rcg2_fm_determine_rate, -+ .set_rate = clk_rcg2_fm_set_rate, -+ .set_rate_and_parent = clk_rcg2_fm_set_rate_and_parent, -+ .get_duty_cycle = clk_rcg2_get_duty_cycle, -+ .set_duty_cycle = clk_rcg2_set_duty_cycle, -+}; -+EXPORT_SYMBOL_GPL(clk_rcg2_fm_ops); -+ - const struct clk_ops clk_rcg2_mux_closest_ops = { - .determine_rate = __clk_mux_determine_rate_closest, - .get_parent = clk_rcg2_get_parent, ---- a/drivers/clk/qcom/common.c -+++ b/drivers/clk/qcom/common.c -@@ -41,6 +41,24 @@ struct freq_tbl *qcom_find_freq(const st - } - EXPORT_SYMBOL_GPL(qcom_find_freq); - -+const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f, -+ unsigned long rate) -+{ -+ if (!f) -+ return NULL; -+ -+ if (!f->freq) -+ return f; -+ -+ for (; f->freq; f++) -+ if (rate <= f->freq) -+ return f; -+ -+ /* Default to our fastest rate */ -+ return f - 1; -+} -+EXPORT_SYMBOL_GPL(qcom_find_freq_multi); -+ - const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, - unsigned long rate) - { ---- a/drivers/clk/qcom/common.h -+++ b/drivers/clk/qcom/common.h -@@ -45,6 +45,8 @@ extern const struct freq_tbl *qcom_find_ - unsigned long rate); - extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, - unsigned long rate); -+extern const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f, -+ unsigned long rate); - extern void - qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count); - extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, diff --git a/target/linux/qualcommax/patches-6.6/0092-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch b/target/linux/qualcommax/patches-6.6/0092-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch deleted file mode 100644 index 5360771df2..0000000000 --- a/target/linux/qualcommax/patches-6.6/0092-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch +++ /dev/null @@ -1,227 +0,0 @@ -From e88f03230dc07aa3293b6aeb078bd27370bb2594 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 20 Dec 2023 23:17:24 +0100 -Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple - conf - -Rework nss_port5/6 to use the new multiple configuration implementation -and correctly fix the clocks for these port under some corner case. - -This is particularly relevant for device that have 2.5G or 10G port -connected to port5 or port 6 on ipq8074. As the parent are shared -across multiple port it may be required to select the correct -configuration to accomplish the desired clock. Without this patch such -port doesn't work in some specific ethernet speed as the clock will be -set to the wrong frequency as we just select the first configuration for -the related frequency instead of selecting the best one. - -Signed-off-by: Christian Marangi -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20231220221724.3822-4-ansuelsmth@gmail.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/gcc-ipq8074.c | 120 +++++++++++++++++++++------------ - 1 file changed, 76 insertions(+), 44 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -1677,15 +1677,23 @@ static struct clk_regmap_div nss_port4_t - }, - }; - --static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { -- F(19200000, P_XO, 1, 0, 0), -- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), -- F(25000000, P_UNIPHY0_RX, 5, 0, 0), -- F(78125000, P_UNIPHY1_RX, 4, 0, 0), -- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), -- F(125000000, P_UNIPHY0_RX, 1, 0, 0), -- F(156250000, P_UNIPHY1_RX, 2, 0, 0), -- F(312500000, P_UNIPHY1_RX, 1, 0, 0), -+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = { -+ C(P_UNIPHY1_RX, 12.5, 0, 0), -+ C(P_UNIPHY0_RX, 5, 0, 0), -+}; -+ -+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = { -+ C(P_UNIPHY1_RX, 2.5, 0, 0), -+ C(P_UNIPHY0_RX, 1, 0, 0), -+}; -+ -+static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = { -+ FMS(19200000, P_XO, 1, 0, 0), -+ FM(25000000, ftbl_nss_port5_rx_clk_src_25), -+ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0), -+ FM(125000000, ftbl_nss_port5_rx_clk_src_125), -+ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0), -+ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0), - { } - }; - -@@ -1712,14 +1720,14 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32 - - static struct clk_rcg2 nss_port5_rx_clk_src = { - .cmd_rcgr = 0x68060, -- .freq_tbl = ftbl_nss_port5_rx_clk_src, -+ .freq_multi_tbl = ftbl_nss_port5_rx_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "nss_port5_rx_clk_src", - .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias, - .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias), -- .ops = &clk_rcg2_ops, -+ .ops = &clk_rcg2_fm_ops, - }, - }; - -@@ -1739,15 +1747,23 @@ static struct clk_regmap_div nss_port5_r - }, - }; - --static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { -- F(19200000, P_XO, 1, 0, 0), -- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), -- F(25000000, P_UNIPHY0_TX, 5, 0, 0), -- F(78125000, P_UNIPHY1_TX, 4, 0, 0), -- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), -- F(125000000, P_UNIPHY0_TX, 1, 0, 0), -- F(156250000, P_UNIPHY1_TX, 2, 0, 0), -- F(312500000, P_UNIPHY1_TX, 1, 0, 0), -+static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = { -+ C(P_UNIPHY1_TX, 12.5, 0, 0), -+ C(P_UNIPHY0_TX, 5, 0, 0), -+}; -+ -+static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = { -+ C(P_UNIPHY1_TX, 2.5, 0, 0), -+ C(P_UNIPHY0_TX, 1, 0, 0), -+}; -+ -+static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = { -+ FMS(19200000, P_XO, 1, 0, 0), -+ FM(25000000, ftbl_nss_port5_tx_clk_src_25), -+ FMS(78125000, P_UNIPHY1_TX, 4, 0, 0), -+ FM(125000000, ftbl_nss_port5_tx_clk_src_125), -+ FMS(156250000, P_UNIPHY1_TX, 2, 0, 0), -+ FMS(312500000, P_UNIPHY1_TX, 1, 0, 0), - { } - }; - -@@ -1774,14 +1790,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32 - - static struct clk_rcg2 nss_port5_tx_clk_src = { - .cmd_rcgr = 0x68068, -- .freq_tbl = ftbl_nss_port5_tx_clk_src, -+ .freq_multi_tbl = ftbl_nss_port5_tx_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "nss_port5_tx_clk_src", - .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias, - .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias), -- .ops = &clk_rcg2_ops, -+ .ops = &clk_rcg2_fm_ops, - }, - }; - -@@ -1801,15 +1817,23 @@ static struct clk_regmap_div nss_port5_t - }, - }; - --static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { -- F(19200000, P_XO, 1, 0, 0), -- F(25000000, P_UNIPHY2_RX, 5, 0, 0), -- F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), -- F(78125000, P_UNIPHY2_RX, 4, 0, 0), -- F(125000000, P_UNIPHY2_RX, 1, 0, 0), -- F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), -- F(156250000, P_UNIPHY2_RX, 2, 0, 0), -- F(312500000, P_UNIPHY2_RX, 1, 0, 0), -+static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = { -+ C(P_UNIPHY2_RX, 5, 0, 0), -+ C(P_UNIPHY2_RX, 12.5, 0, 0), -+}; -+ -+static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = { -+ C(P_UNIPHY2_RX, 1, 0, 0), -+ C(P_UNIPHY2_RX, 2.5, 0, 0), -+}; -+ -+static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = { -+ FMS(19200000, P_XO, 1, 0, 0), -+ FM(25000000, ftbl_nss_port6_rx_clk_src_25), -+ FMS(78125000, P_UNIPHY2_RX, 4, 0, 0), -+ FM(125000000, ftbl_nss_port6_rx_clk_src_125), -+ FMS(156250000, P_UNIPHY2_RX, 2, 0, 0), -+ FMS(312500000, P_UNIPHY2_RX, 1, 0, 0), - { } - }; - -@@ -1831,14 +1855,14 @@ static const struct parent_map gcc_xo_un - - static struct clk_rcg2 nss_port6_rx_clk_src = { - .cmd_rcgr = 0x68070, -- .freq_tbl = ftbl_nss_port6_rx_clk_src, -+ .freq_multi_tbl = ftbl_nss_port6_rx_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "nss_port6_rx_clk_src", - .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias, - .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias), -- .ops = &clk_rcg2_ops, -+ .ops = &clk_rcg2_fm_ops, - }, - }; - -@@ -1858,15 +1882,23 @@ static struct clk_regmap_div nss_port6_r - }, - }; - --static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { -- F(19200000, P_XO, 1, 0, 0), -- F(25000000, P_UNIPHY2_TX, 5, 0, 0), -- F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), -- F(78125000, P_UNIPHY2_TX, 4, 0, 0), -- F(125000000, P_UNIPHY2_TX, 1, 0, 0), -- F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), -- F(156250000, P_UNIPHY2_TX, 2, 0, 0), -- F(312500000, P_UNIPHY2_TX, 1, 0, 0), -+static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = { -+ C(P_UNIPHY2_TX, 5, 0, 0), -+ C(P_UNIPHY2_TX, 12.5, 0, 0), -+}; -+ -+static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = { -+ C(P_UNIPHY2_TX, 1, 0, 0), -+ C(P_UNIPHY2_TX, 2.5, 0, 0), -+}; -+ -+static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = { -+ FMS(19200000, P_XO, 1, 0, 0), -+ FM(25000000, ftbl_nss_port6_tx_clk_src_25), -+ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0), -+ FM(125000000, ftbl_nss_port6_tx_clk_src_125), -+ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0), -+ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0), - { } - }; - -@@ -1888,14 +1920,14 @@ static const struct parent_map gcc_xo_un - - static struct clk_rcg2 nss_port6_tx_clk_src = { - .cmd_rcgr = 0x68078, -- .freq_tbl = ftbl_nss_port6_tx_clk_src, -+ .freq_multi_tbl = ftbl_nss_port6_tx_clk_src, - .hid_width = 5, - .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "nss_port6_tx_clk_src", - .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias, - .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias), -- .ops = &clk_rcg2_ops, -+ .ops = &clk_rcg2_fm_ops, - }, - }; -