armv7: psci: cpu_off: flush D-Cache before disable D-Cache

Before disable cache, need to first flush cache.

There maybe dirty data in D-Cache before disable D-Cache.
After disable D-Cache, the first store instructions in
psci_v7_flush_dcache_all will directly store registers
{r4-r5, r7, r9-r11, lr} to memory.
If there is dirty data before disable D-Cache,
psci_v7_flush_dcache_all will flush data to memory,
and may overwrite the memory that hold the registers
{r4-r5, r7, r9-r11, lr}.

So before disable cache, first flush D-Cache.

Signed-off-by: Peng Fan <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Cc: Hans de Goede <[email protected]>
Cc: Hongbo Zhang <[email protected]>
Cc: York Sun <[email protected]>
Cc: Marc Zyngier <[email protected]>
Cc: Tom Rini <[email protected]>

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 6a362085a6e3914888a519211cb7685f4401f652..95b962dadf0b2c380de57ce3dcdedfda91ff9caa 100644 (file)
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -258,6 +258,10 @@ ENDPROC(psci_enable_smp)
 ENTRY(psci_cpu_off_common)
        push    {lr}
 
+       bl      psci_v7_flush_dcache_all
+
+       clrex                                   @ Why???
+
        mrc     p15, 0, r0, c1, c0, 0           @ SCTLR
        bic     r0, r0, #(1 << 2)               @ Clear C bit
        mcr     p15, 0, r0, c1, c0, 0           @ SCTLR