MIPS: OCTEON: Use correct CSR to soft reset

This fixes reboot for Octeon III boards

[[email protected]: Dropped segment for function cvmx_reset_octeon()
which was removed by the preceeding commit.]

Signed-off-by: Chandrakala Chavva <[email protected]>
Signed-off-by: Aleksey Makarov <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/9464/
Signed-off-by: Ralf Baechle <[email protected]>

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 01130e93126deb087ccc0da3cad9bf18256eea00..73348afa4b8014fc13d7cee0ba630e5a84e103cc 100644 (file)
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -416,7 +416,10 @@ static void octeon_restart(char *command)
 
        mb();
        while (1)
-               cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
+               if (OCTEON_IS_OCTEON3())
+                       cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
+               else
+                       cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
 }