ddr cfg: DRAM_RESET needs 0x00020030

The old value of 0x000e0030 will cause ethernet
timeout issues on the sabrelite and possibly other
boards using the KSZ9021.
I have no explanation as to why.

But this is a correct change, the TRM will be updated
to show that 00b is the only valid setting for bits
19-18 of DRAM_RESET.

My thanks go to Liu Hui(Jason) for this information.

Acked-by: Fabio Estevam <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Signed-off-by: Troy Kisky <[email protected]>

diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg
index c3158120a40d43ea0c7e23d13ec41298563b80ba..e5f8add7447f7b05849e5c902071519f7ddfb842 100644 (file)
--- a/board/boundary/nitrogen6x/ddr-setup.cfg
+++ b/board/boundary/nitrogen6x/ddr-setup.cfg
@@ -74,7 +74,7 @@ DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
 
-DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000