+++ /dev/null
-From c6fd43b8420f3864ad1cd64d818d9b9abc2cb711 Mon Sep 17 00:00:00 2001
-Date: Mon, 28 Aug 2023 12:30:22 +0800
-Subject: [PATCH 01/14] riscv: dts: allwinner: d1: Add PMU event node
-
-D1 has several pmu events supported by opensbi.
-These events can be used by perf for profiling.
-
-Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
-Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
----
- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
-@@ -72,4 +72,43 @@
- #interrupt-cells = <2>;
- };
- };
-+
-+ pmu {
-+ compatible = "riscv,pmu";
-+ riscv,event-to-mhpmcounters =
-+ <0x00003 0x00003 0x00000008>,
-+ <0x00004 0x00004 0x00000010>,
-+ <0x00005 0x00005 0x00000200>,
-+ <0x00006 0x00006 0x00000100>,
-+ <0x10000 0x10000 0x00004000>,
-+ <0x10001 0x10001 0x00008000>,
-+ <0x10002 0x10002 0x00010000>,
-+ <0x10003 0x10003 0x00020000>,
-+ <0x10019 0x10019 0x00000040>,
-+ <0x10021 0x10021 0x00000020>;
-+ riscv,event-to-mhpmevent =
-+ <0x00003 0x00000000 0x00000001>,
-+ <0x00004 0x00000000 0x00000002>,
-+ <0x00005 0x00000000 0x00000007>,
-+ <0x00006 0x00000000 0x00000006>,
-+ <0x10000 0x00000000 0x0000000c>,
-+ <0x10001 0x00000000 0x0000000d>,
-+ <0x10002 0x00000000 0x0000000e>,
-+ <0x10003 0x00000000 0x0000000f>,
-+ <0x10019 0x00000000 0x00000004>,
-+ <0x10021 0x00000000 0x00000003>;
-+ riscv,raw-event-to-mhpmcounters =
-+ <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
-+ <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
-+ <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
-+ <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
-+ <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
-+ <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
-+ <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
-+ <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
-+ <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
-+ <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
-+ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
-+ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
-+ };
- };
+++ /dev/null
-From 99942611816c117a01f16dbcab54908a49b378c3 Mon Sep 17 00:00:00 2001
-Date: Mon, 18 Dec 2023 12:05:39 +0100
-Subject: [PATCH 02/14] riscv: dts: allwinner: Update opp table to allow CPU
- frequency scaling
-
-Two OPPs are currently defined for the D1/D1s; one at 408MHz and
-another at 1.08GHz. Switching between these can be done with the
-"sun50i-cpufreq-nvmem" driver. This patch populates the opp table
-appropriately, inspired by
-https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi
-
-The supply voltages are PWM-controlled, but support for that IP
-is still in the works. So stick to a target vdd-cpu supply of 0.9V,
-which seems to be the default on most D1 boards.
-
----
- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++---
- 1 file changed, 15 insertions(+), 3 deletions(-)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
-@@ -36,16 +36,22 @@
- };
-
- opp_table_cpu: opp-table-cpu {
-- compatible = "operating-points-v2";
-+ compatible = "allwinner,sun20i-d1-operating-points",
-+ "allwinner,sun50i-h6-operating-points";
-+ nvmem-cells = <&cpu_speed_grade>;
-+ nvmem-cell-names = "speed";
-+ opp-shared;
-
- opp-408000000 {
-+ clock-latency-ns = <244144>; /* 8 32k periods */
- opp-hz = /bits/ 64 <408000000>;
-- opp-microvolt = <900000 900000 1100000>;
-+ opp-microvolt-speed0 = <900000 900000 1100000>;
- };
-
- opp-1080000000 {
-+ clock-latency-ns = <244144>; /* 8 32k periods */
- opp-hz = /bits/ 64 <1008000000>;
-- opp-microvolt = <900000 900000 1100000>;
-+ opp-microvolt-speed0 = <900000 900000 1100000>;
- };
- };
-
-@@ -112,3 +118,9 @@
- <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
- };
- };
-+
-+&sid {
-+ cpu_speed_grade: cpu-speed-grade@0 {
-+ reg = <0x00 0x2>;
-+ };
-+};
+++ /dev/null
-From e904f32e5fe694ed7b8d1cd914bcf2bfd67e896c Mon Sep 17 00:00:00 2001
-Date: Mon, 18 Dec 2023 12:05:40 +0100
-Subject: [PATCH 03/14] dt-bindings: opp: sun50i: Add binding for D1 CPUs
-
-Add binding for D1 CPU OPPs.
-
----
- .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
-+++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
-@@ -23,7 +23,9 @@ allOf:
-
- properties:
- compatible:
-- const: allwinner,sun50i-h6-operating-points
-+ enum:
-+ - allwinner,sun50i-h6-operating-points
-+ - allwinner,sun20i-d1-operating-points
-
- nvmem-cells:
- description: |
+++ /dev/null
-From b294def636629cc4d9feff4ed610a0d0c68a58fd Mon Sep 17 00:00:00 2001
-Date: Mon, 18 Dec 2023 12:05:41 +0100
-Subject: [PATCH 04/14] cpufreq: sun50i: Add D1 support
-
-Add support for D1 based devices to the Allwinner H6 cpufreq
-driver
-
----
- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-@@ -160,6 +160,7 @@ static struct platform_driver sun50i_cpu
-
- static const struct of_device_id sun50i_cpufreq_match_list[] = {
- { .compatible = "allwinner,sun50i-h6" },
-+ { .compatible = "allwinner,sun20i-d1" },
- {}
- };
- MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
+++ /dev/null
-From 9d78aafd278577ef2a9d92127c9d35b00989c057 Mon Sep 17 00:00:00 2001
-Date: Mon, 18 Dec 2023 12:05:42 +0100
-Subject: [PATCH 05/14] cpufreq: dt-platdev: Blocklist allwinner,sun20i-d1 SoC
-
-The Allwinner D1 uses H6 cpufreq driver. Add it to blocklist
-so the "cpufreq-dt" device is not created twice.
-
----
- drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -104,6 +104,7 @@ static const struct of_device_id allowli
- */
- static const struct of_device_id blocklist[] __initconst = {
- { .compatible = "allwinner,sun50i-h6", },
-+ { .compatible = "allwinner,sun20i-d1", },
-
- { .compatible = "apple,arm-platform", },
-
+++ /dev/null
-From e4a8ff817e133d84f8a82f78461e0592e5e9d9cc Mon Sep 17 00:00:00 2001
-Date: Mon, 18 Dec 2023 12:05:43 +0100
-Subject: [PATCH 06/14] cpufreq: Make sun50i h6 cpufreq Kconfig option arch
- generic
-
-Move the Allwinner SUN50I cpufreq driver from Kconfig.arm to the
-main Kconfig file so it supports other architectures, like RISC-V
-in our case, and drop the 'ARM_' prefix.
-
----
- drivers/cpufreq/Kconfig | 12 ++++++++++++
- drivers/cpufreq/Kconfig.arm | 12 ------------
- drivers/cpufreq/Makefile | 2 +-
- 3 files changed, 13 insertions(+), 13 deletions(-)
-
---- a/drivers/cpufreq/Kconfig
-+++ b/drivers/cpufreq/Kconfig
-@@ -312,5 +312,17 @@ config QORIQ_CPUFREQ
- This adds the CPUFreq driver support for Freescale QorIQ SoCs
- which are capable of changing the CPU's frequency dynamically.
-
-+config ALLWINNER_SUN50I_CPUFREQ_NVMEM
-+ tristate "Allwinner nvmem based SUN50I CPUFreq driver"
-+ depends on ARCH_SUNXI
-+ depends on NVMEM_SUNXI_SID
-+ select PM_OPP
-+ help
-+ This adds the nvmem based CPUFreq driver for Allwinner
-+ h6/D1 SoCs.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called sun50i-cpufreq-nvmem.
-+
- endif
- endmenu
---- a/drivers/cpufreq/Kconfig.arm
-+++ b/drivers/cpufreq/Kconfig.arm
-@@ -29,18 +29,6 @@ config ACPI_CPPC_CPUFREQ_FIE
-
- If in doubt, say N.
-
--config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
-- tristate "Allwinner nvmem based SUN50I CPUFreq driver"
-- depends on ARCH_SUNXI
-- depends on NVMEM_SUNXI_SID
-- select PM_OPP
-- help
-- This adds the nvmem based CPUFreq driver for Allwinner
-- h6 SoC.
--
-- To compile this driver as a module, choose M here: the
-- module will be called sun50i-cpufreq-nvmem.
--
- config ARM_APPLE_SOC_CPUFREQ
- tristate "Apple Silicon SoC CPUFreq support"
- depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)
---- a/drivers/cpufreq/Makefile
-+++ b/drivers/cpufreq/Makefile
-@@ -78,7 +78,7 @@ obj-$(CONFIG_ARM_SCMI_CPUFREQ) += scmi-
- obj-$(CONFIG_ARM_SCPI_CPUFREQ) += scpi-cpufreq.o
- obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
- obj-$(CONFIG_ARM_STI_CPUFREQ) += sti-cpufreq.o
--obj-$(CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o
-+obj-$(CONFIG_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o
- obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o
- obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
- obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
-@@ -232,15 +232,65 @@
+@@ -228,15 +228,65 @@
/* TODO H3 DAP (Digital Audio Processing) bits */
struct regmap_field *reg_adc_fifoc;
struct snd_dmaengine_dai_dma_data capture_dma_data;
-@@ -250,33 +300,33 @@ struct sun4i_codec {
+@@ -246,33 +296,33 @@ struct sun4i_codec {
static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
{
/* Flush TX FIFO */
}
static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
-@@ -325,8 +375,8 @@ static int sun4i_codec_prepare_capture(s
+@@ -321,8 +371,8 @@ static int sun4i_codec_prepare_capture(s
/* Set RX FIFO trigger level */
regmap_field_update_bits(scodec->reg_adc_fifoc,
/*
* FIXME: Undocumented in the datasheet, but
-@@ -360,13 +410,13 @@ static int sun4i_codec_prepare_playback(
+@@ -356,13 +406,13 @@ static int sun4i_codec_prepare_playback(
u32 val;
/* Flush the TX FIFO */
if (substream->runtime->rate > 32000)
/* Use 64 bits FIR filter */
-@@ -375,13 +425,12 @@ static int sun4i_codec_prepare_playback(
+@@ -371,13 +421,12 @@ static int sun4i_codec_prepare_playback(
/* Use 32 bits FIR filter */
val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
return 0;
};
-@@ -476,30 +525,32 @@ static int sun4i_codec_hw_params_capture
+@@ -472,30 +521,32 @@ static int sun4i_codec_hw_params_capture
7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS,
hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS);
scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
}
-@@ -514,9 +565,9 @@ static int sun4i_codec_hw_params_playbac
+@@ -510,9 +561,9 @@ static int sun4i_codec_hw_params_playbac
u32 val;
/* Set DAC sample rate */
/* Set the number of channels we want to use */
if (params_channels(params) == 1)
-@@ -524,27 +575,26 @@ static int sun4i_codec_hw_params_playbac
+@@ -520,27 +571,26 @@ static int sun4i_codec_hw_params_playbac
else
val = 0;
scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
}
-@@ -565,7 +615,11 @@ static int sun4i_codec_hw_params(struct
+@@ -561,7 +611,11 @@ static int sun4i_codec_hw_params(struct
if (!clk_freq)
return -EINVAL;
if (ret)
return ret;
-@@ -607,10 +661,14 @@ static int sun4i_codec_startup(struct sn
+@@ -587,10 +641,14 @@ static int sun4i_codec_startup(struct sn
* Stop issuing DRQ when we have room for less than 16 samples
* in our TX FIFO
*/
}
static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
-@@ -619,7 +677,11 @@ static void sun4i_codec_shutdown(struct
- struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+@@ -599,7 +657,11 @@ static void sun4i_codec_shutdown(struct
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
- clk_disable_unprepare(scodec->clk_module);
}
static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
-@@ -1229,6 +1291,55 @@ static const struct snd_soc_component_dr
+@@ -1216,6 +1278,55 @@ static const struct snd_soc_component_dr
.endianness = 1,
};
static const struct snd_soc_component_driver sun4i_codec_component = {
.name = "sun4i-codec",
.legacy_dai_naming = 1,
-@@ -1532,6 +1643,66 @@ static struct snd_soc_card *sun8i_v3s_co
+@@ -1518,6 +1629,66 @@ static struct snd_soc_card *sun8i_v3s_co
return card;
};
static const struct regmap_config sun4i_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
-@@ -1574,21 +1745,22 @@ static const struct regmap_config sun8i_
+@@ -1560,21 +1731,22 @@ static const struct regmap_config sun8i_
.max_register = SUN8I_H3_CODEC_ADC_DBG,
};
.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
};
-@@ -1597,7 +1769,11 @@ static const struct sun4i_codec_quirks s
+@@ -1583,7 +1755,11 @@ static const struct sun4i_codec_quirks s
.regmap_config = &sun6i_codec_regmap_config,
.codec = &sun6i_codec_codec,
.create_card = sun6i_codec_create_card,
.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
.has_reset = true,
-@@ -1607,7 +1783,11 @@ static const struct sun4i_codec_quirks s
+@@ -1593,7 +1769,11 @@ static const struct sun4i_codec_quirks s
.regmap_config = &sun7i_codec_regmap_config,
.codec = &sun7i_codec_codec,
.create_card = sun4i_codec_create_card,
.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
};
-@@ -1616,7 +1796,11 @@ static const struct sun4i_codec_quirks s
+@@ -1602,7 +1782,11 @@ static const struct sun4i_codec_quirks s
.regmap_config = &sun8i_a23_codec_regmap_config,
.codec = &sun8i_a23_codec_codec,
.create_card = sun8i_a23_codec_create_card,
.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
.has_reset = true,
-@@ -1631,7 +1815,11 @@ static const struct sun4i_codec_quirks s
+@@ -1617,7 +1801,11 @@ static const struct sun4i_codec_quirks s
*/
.codec = &sun8i_a23_codec_codec,
.create_card = sun8i_h3_codec_create_card,
.reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
.has_reset = true,
-@@ -1645,12 +1833,31 @@ static const struct sun4i_codec_quirks s
+@@ -1631,12 +1819,31 @@ static const struct sun4i_codec_quirks s
*/
.codec = &sun8i_a23_codec_codec,
.create_card = sun8i_v3s_codec_create_card,
static const struct of_device_id sun4i_codec_of_match[] = {
{
.compatible = "allwinner,sun4i-a10-codec",
-@@ -1676,6 +1883,10 @@ static const struct of_device_id sun4i_c
+@@ -1662,6 +1869,10 @@ static const struct of_device_id sun4i_c
.compatible = "allwinner,sun8i-v3s-codec",
.data = &sun8i_v3s_codec_quirks,
},
{}
};
MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
-@@ -1704,6 +1915,7 @@ static int sun4i_codec_probe(struct plat
+@@ -1690,6 +1901,7 @@ static int sun4i_codec_probe(struct plat
dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
return -ENODEV;
}
scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
quirks->regmap_config);
-@@ -1719,10 +1931,24 @@ static int sun4i_codec_probe(struct plat
+@@ -1705,10 +1917,24 @@ static int sun4i_codec_probe(struct plat
return PTR_ERR(scodec->clk_apb);
}
}
if (quirks->has_reset) {
-@@ -1751,6 +1977,16 @@ static int sun4i_codec_probe(struct plat
+@@ -1737,6 +1963,16 @@ static int sun4i_codec_probe(struct plat
dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
ret);
return ret;
+++ /dev/null
-From 16728b748a44f1cea060a6ba57453c03e3745c1d Mon Sep 17 00:00:00 2001
-Date: Mon, 18 Dec 2023 00:06:22 +0300
-Subject: [PATCH 11/14] dt-bindings: thermal: sun8i: Add binding for D1/T113s
- THS controller
-
-Add a binding for D1/T113s thermal sensor controller.
-
----
- .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
-+++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
-@@ -16,6 +16,7 @@ properties:
- - allwinner,sun8i-a83t-ths
- - allwinner,sun8i-h3-ths
- - allwinner,sun8i-r40-ths
-+ - allwinner,sun20i-d1-ths
- - allwinner,sun50i-a64-ths
- - allwinner,sun50i-a100-ths
- - allwinner,sun50i-h5-ths
-@@ -61,6 +62,7 @@ allOf:
- compatible:
- contains:
- enum:
-+ - allwinner,sun20i-d1-ths
- - allwinner,sun50i-a100-ths
- - allwinner,sun50i-h6-ths
-
-@@ -84,7 +86,9 @@ allOf:
- properties:
- compatible:
- contains:
-- const: allwinner,sun8i-h3-ths
-+ enum:
-+ - allwinner,sun8i-h3-ths
-+ - allwinner,sun20i-d1-ths
-
- then:
- properties:
-@@ -103,6 +107,7 @@ allOf:
- enum:
- - allwinner,sun8i-h3-ths
- - allwinner,sun8i-r40-ths
-+ - allwinner,sun20i-d1-ths
- - allwinner,sun50i-a64-ths
- - allwinner,sun50i-a100-ths
- - allwinner,sun50i-h5-ths
+++ /dev/null
-From eb7e78f9e4bb9133898875afb0e0b9f09663e802 Mon Sep 17 00:00:00 2001
-Date: Mon, 18 Dec 2023 00:06:23 +0300
-Subject: [PATCH 12/14] thermal: sun8i: Add D1/T113s THS controller support
-
-This patch adds a thermal sensor controller support for the D1/T113s,
-which is similar to the one on H6, but with only one sensor and
-different scale and offset values.
-
----
- drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun
- .calc_temp = sun8i_ths_calc_temp,
- };
-
-+static const struct ths_thermal_chip sun20i_d1_ths = {
-+ .sensor_num = 1,
-+ .has_bus_clk_reset = true,
-+ .offset = 188552,
-+ .scale = 673,
-+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
-+ .calibrate = sun50i_h6_ths_calibrate,
-+ .init = sun50i_h6_thermal_init,
-+ .irq_ack = sun50i_h6_irq_ack,
-+ .calc_temp = sun8i_ths_calc_temp,
-+};
-+
- static const struct of_device_id of_ths_match[] = {
- { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
- { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
-@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_
- { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
- { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
- { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
-+ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
- { /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, of_ths_match);
+++ /dev/null
-From 196423a17b92ef241766691b42dac0136342bdb5 Mon Sep 17 00:00:00 2001
-Date: Mon, 18 Dec 2023 00:06:24 +0300
-Subject: [PATCH 13/14] riscv: dts: allwinner: d1: Add thermal sensor
-
-This patch adds a thermal sensor controller node for the D1/T113s.
-Also it adds a THS calibration data cell to efuse node.
-
----
- .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
-@@ -166,6 +166,19 @@
- #io-channel-cells = <1>;
- };
-
-+ ths: thermal-sensor@2009400 {
-+ compatible = "allwinner,sun20i-d1-ths";
-+ reg = <0x02009400 0x400>;
-+ interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_THS>;
-+ clock-names = "bus";
-+ resets = <&ccu RST_BUS_THS>;
-+ nvmem-cells = <&ths_calibration>;
-+ nvmem-cell-names = "calibration";
-+ status = "disabled";
-+ #thermal-sensor-cells = <0>;
-+ };
-+
- dmic: dmic@2031000 {
- compatible = "allwinner,sun20i-d1-dmic",
- "allwinner,sun50i-h6-dmic";
-@@ -415,6 +428,10 @@
- reg = <0x3006000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-+
-+ ths_calibration: thermal-sensor-calibration@14 {
-+ reg = <0x14 0x4>;
-+ };
- };
-
- crypto: crypto@3040000 {
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
-@@ -179,6 +179,28 @@
- #thermal-sensor-cells = <0>;
+@@ -166,6 +166,28 @@
+ #io-channel-cells = <1>;
};
+ codec: codec@2030000 {
projects / openwrt / staging / linusw.git / commitdiff