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perf/x86/amd: Add support for new IOMMU performance events
author
Suravee Suthikulpanit
<
[email protected]
>
Mon, 29 Feb 2016 04:23:29 +0000
(22:23 -0600)
committer
Ingo Molnar
<
[email protected]
>
Mon, 21 Mar 2016 08:35:28 +0000
(09:35 +0100)
This patch adds new IOMMU performance event based on
the information in table 74 of the AMD I/O Virtualization Technology
(IOMMU) Specification (Document Id: 4882, Rev 2.62, Feb 2015)
Signed-off-by: Suravee Suthikulpanit <
[email protected]
>
Signed-off-by: Peter Zijlstra (Intel) <
[email protected]
>
Reviewed-by: Joerg Roedel <
[email protected]
>
Acked-by: Joerg Roedel <
[email protected]
>
Cc: <
[email protected]
>
Cc: Alexander Shishkin <
[email protected]
>
Cc: Andy Lutomirski <
[email protected]
>
Cc: Arnaldo Carvalho de Melo <
[email protected]
>
Cc: Borislav Petkov <
[email protected]
>
Cc: Brian Gerst <
[email protected]
>
Cc: David Ahern <
[email protected]
>
Cc: Denys Vlasenko <
[email protected]
>
Cc: H. Peter Anvin <
[email protected]
>
Cc: Jiri Olsa <
[email protected]
>
Cc: Linus Torvalds <
[email protected]
>
Cc: Namhyung Kim <
[email protected]
>
Cc: Peter Zijlstra <
[email protected]
>
Cc: Stephane Eranian <
[email protected]
>
Cc: Thomas Gleixner <
[email protected]
>
Cc: Vince Weaver <
[email protected]
>
Link:
http://support.amd.com/TechDocs/48882_IOMMU.pdf
Signed-off-by: Ingo Molnar <
[email protected]
>
arch/x86/events/amd/iommu.c
patch
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diff --git
a/arch/x86/events/amd/iommu.c
b/arch/x86/events/amd/iommu.c
index 635e5eba0caf87f432d97bcf178db025e5cb4cca..40625ca7a190953fc87c386a03017bab96903435 100644
(file)
--- a/
arch/x86/events/amd/iommu.c
+++ b/
arch/x86/events/amd/iommu.c
@@
-118,6
+118,11
@@
static struct amd_iommu_event_desc amd_iommu_v2_event_descs[] = {
AMD_IOMMU_EVENT_DESC(cmd_processed, "csource=0x11"),
AMD_IOMMU_EVENT_DESC(cmd_processed_inv, "csource=0x12"),
AMD_IOMMU_EVENT_DESC(tlb_inv, "csource=0x13"),
+ AMD_IOMMU_EVENT_DESC(ign_rd_wr_mmio_1ff8h, "csource=0x14"),
+ AMD_IOMMU_EVENT_DESC(vapic_int_non_guest, "csource=0x15"),
+ AMD_IOMMU_EVENT_DESC(vapic_int_guest, "csource=0x16"),
+ AMD_IOMMU_EVENT_DESC(smi_recv, "csource=0x17"),
+ AMD_IOMMU_EVENT_DESC(smi_blk, "csource=0x18"),
{ /* end: all zeroes */ },
};