drm/amdgpu: add new flag AMD_PG_SUPPORT_MMHUB

Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3392bd48c6e461caba1289d2fa0e77a2432d7d6c..175ba5f9691c4a5188442d012430e4212bbaee20 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -698,6 +698,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_RAVEN:
                mmhub_v1_0_initialize_power_gating(adev);
+               mmhub_v1_0_update_power_gating(adev, true);
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index c885c0d9344b5da185732aa01053c92820fb41ed..9804318f3488cf67eaf357756dd239425fc27457 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -426,7 +426,7 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
        pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
        pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
 
-       if (enable) {
+       if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
                pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
                                                PCTL0_RENG_EXECUTE,
                                                RENG_EXECUTE_ON_PWR_UP, 1);

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index beb2a81ab7daacae86bc171e5bebf50779c9fff0..70e8c20acb2fd51e63890978483857ef40c4d3b7 100644 (file)
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -184,6 +184,7 @@ enum amd_fan_ctrl_mode {
 #define AMD_PG_SUPPORT_SAMU                    (1 << 10)
 #define AMD_PG_SUPPORT_GFX_QUICK_MG            (1 << 11)
 #define AMD_PG_SUPPORT_GFX_PIPELINE            (1 << 12)
+#define AMD_PG_SUPPORT_MMHUB                   (1 << 13)
 
 enum amd_pm_state_type {
        /* not used for dpm */