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drm/amd/amdgpu: Tidy up gfx_v9_0_enable_gfx_cg_power_gating()
author
Tom St Denis
<
[email protected]
>
Thu, 31 Aug 2017 13:14:41 +0000
(09:14 -0400)
committer
Alex Deucher
<
[email protected]
>
Thu, 31 Aug 2017 19:01:02 +0000
(15:01 -0400)
Make it consistent in style with the other CG/PG enable functions...
Signed-off-by: Tom St Denis <
[email protected]
>
Reviewed-by: Alex Deucher <
[email protected]
>
Signed-off-by: Alex Deucher <
[email protected]
>
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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diff --git
a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 61b3362d3c20f0f8cef502341565da2e13bb3abb..b0805b1e7b299eab40ce86365f467e61a4124b82 100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@
-1883,10
+1883,9
@@
static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
uint32_t data, default_data;
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
- if (enable == true)
- data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
- else
- data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ data = REG_SET_FIELD(data, RLC_PG_CNTL,
+ GFX_POWER_GATING_ENABLE,
+ enable ? 1 : 0);
if(default_data != data)
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
}