ALSA: hda - only sync BCLK to the display clock for Haswell & Broadwell

Only Intel Haswell and Broadwell have a separate HD-A controller (PCI device 3)
for display audio, which needs to get 24MHz HD-A link BCLK from the variable
display core clock through vendor specific registers EM4 & EM5. Other platforms
(Baytrail, Braswell and Skylake) don't have this feature.

So this patch checks the PCI device ID of the controller in haswell_set_bclk()
and only sync BCLK for HSW and BDW.

Signed-off-by: Mengdong Lin <[email protected]>
Signed-off-by: Takashi Iwai <[email protected]>

diff --git a/sound/pci/hda/hda_i915.c b/sound/pci/hda/hda_i915.c
index 52a85d87c23c58ae11cd8985d4a50d808ffe3731..3052a2b095f7a7bd2483add40e4fbc893cdbc184 100644 (file)
--- a/sound/pci/hda/hda_i915.c
+++ b/sound/pci/hda/hda_i915.c
@@ -55,6 +55,12 @@ void haswell_set_bclk(struct hda_intel *hda)
        int cdclk_freq;
        unsigned int bclk_m, bclk_n;
        struct i915_audio_component *acomp = &hda->audio_component;
+       struct pci_dev *pci = hda->chip.pci;
+
+       /* Only Haswell/Broadwell need set BCLK */
+       if (pci->device != 0x0a0c && pci->device != 0x0c0c
+          && pci->device != 0x0d0c && pci->device != 0x160c)
+               return;
 
        if (!acomp->ops)
                return;