MIPS: Use Ingenic-specific write combine attribute on all Ingenic platforms

The Ingenic-specific write combining cache attribute was defined based
on CONFIG_MACH_JZ4740 and therefore not used on JZ4780. Change this to
CONFIG_MACH_INGENIC so that it gets used on all Ingenic platforms.

Signed-off-by: Alex Smith <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10769/
Signed-off-by: Ralf Baechle <[email protected]>

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index c28a8499aec7f4fa18c5bd4c71922812d2ebf143..002eeb224733bc7c16308c7536885d686c57637f 100644 (file)
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -249,7 +249,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
 #define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
 
-#elif defined(CONFIG_MACH_JZ4740)
+#elif defined(CONFIG_MACH_INGENIC)
 
 /* Ingenic uses the WA bit to achieve write-combine memory writes */
 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)