};
};
-&tsens {
- status = "okay";
-};
-
&pcie0_phy {
status = "okay";
};
};
};
-&tsens {
- status = "okay";
-};
-
&q6v5_wcss {
status = "okay";
};
};
-&tsens {
- status = "okay";
-};
-
&q6v5_wcss {
status = "okay";
bias-disable;
};
};
-
-&tsens {
- status = "okay";
-};
};
};
-&tsens {
- status = "okay";
-};
-
&q6v5_wcss {
status = "okay";
};
};
-&tsens {
- status = "okay";
-};
-
/*
* ath11k Wi-Fi consumes too large memory spaces and too few spaces are
* available for users. To prevent OOM when using LuCI or other softwares,
--- /dev/null
+From 450a80623e3b8bb5dae59e0d56046fc3d0a88f3b Mon Sep 17 00:00:00 2001
+Date: Thu, 12 Jun 2025 10:46:14 +0400
+Subject: arm64: dts: qcom: ipq5018: Add tsens node
+
+IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use.
+There is no RPM, so tsens has to be manually enabled. Adding the tsens
+and nvmem nodes and adding 4 thermal sensors (zones). The critical trip
+temperature is set to 120'C with an action to reboot.
+
+In addition, adding a cooling device to the CPU thermal zone which uses
+CPU frequency scaling.
+
+[bjorn: Added tsens-v1 fallback compatible, per binding]
+---
+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 178 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 178 insertions(+)
+
+(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
+
+--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+ #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
++#include <dt-bindings/thermal/thermal.h>
+
+ / {
+ interrupt-parent = <&intc>;
+@@ -39,6 +40,7 @@
+ next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
++ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+@@ -49,6 +51,7 @@
+ next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
++ #cooling-cells = <2>;
+ };
+
+ l2_0: l2-cache {
+@@ -182,6 +185,117 @@
+ status = "disabled";
+ };
+
++ qfprom: qfprom@a0000 {
++ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
++ reg = <0x000a0000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ tsens_mode: mode@249 {
++ reg = <0x249 0x1>;
++ bits = <0 3>;
++ };
++
++ tsens_base1: base1@249 {
++ reg = <0x249 0x2>;
++ bits = <3 8>;
++ };
++
++ tsens_base2: base2@24a {
++ reg = <0x24a 0x2>;
++ bits = <3 8>;
++ };
++
++ tsens_s0_p1: s0-p1@24b {
++ reg = <0x24b 0x2>;
++ bits = <2 6>;
++ };
++
++ tsens_s0_p2: s0-p2@24c {
++ reg = <0x24c 0x1>;
++ bits = <1 6>;
++ };
++
++ tsens_s1_p1: s1-p1@24c {
++ reg = <0x24c 0x2>;
++ bits = <7 6>;
++ };
++
++ tsens_s1_p2: s1-p2@24d {
++ reg = <0x24d 0x2>;
++ bits = <5 6>;
++ };
++
++ tsens_s2_p1: s2-p1@24e {
++ reg = <0x24e 0x2>;
++ bits = <3 6>;
++ };
++
++ tsens_s2_p2: s2-p2@24f {
++ reg = <0x24f 0x1>;
++ bits = <1 6>;
++ };
++
++ tsens_s3_p1: s3-p1@24f {
++ reg = <0x24f 0x2>;
++ bits = <7 6>;
++ };
++
++ tsens_s3_p2: s3-p2@250 {
++ reg = <0x250 0x2>;
++ bits = <5 6>;
++ };
++
++ tsens_s4_p1: s4-p1@251 {
++ reg = <0x251 0x2>;
++ bits = <3 6>;
++ };
++
++ tsens_s4_p2: s4-p2@254 {
++ reg = <0x254 0x1>;
++ bits = <0 6>;
++ };
++ };
++
++ tsens: thermal-sensor@4a9000 {
++ compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
++ reg = <0x004a9000 0x1000>,
++ <0x004a8000 0x1000>;
++
++ nvmem-cells = <&tsens_mode>,
++ <&tsens_base1>,
++ <&tsens_base2>,
++ <&tsens_s0_p1>,
++ <&tsens_s0_p2>,
++ <&tsens_s1_p1>,
++ <&tsens_s1_p2>,
++ <&tsens_s2_p1>,
++ <&tsens_s2_p2>,
++ <&tsens_s3_p1>,
++ <&tsens_s3_p2>,
++ <&tsens_s4_p1>,
++ <&tsens_s4_p2>;
++
++ nvmem-cell-names = "mode",
++ "base1",
++ "base2",
++ "s0_p1",
++ "s0_p2",
++ "s1_p1",
++ "s1_p2",
++ "s2_p1",
++ "s2_p2",
++ "s3_p1",
++ "s3_p2",
++ "s4_p1",
++ "s4_p2";
++
++ interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
++ interrupt-names = "uplow";
++ #qcom,sensors = <5>;
++ #thermal-sensor-cells = <1>;
++ };
++
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5018-tlmm";
+ reg = <0x01000000 0x300000>;
+@@ -630,6 +744,70 @@
+ };
+ };
+ };
++
++ thermal-zones {
++ cpu-thermal {
++ thermal-sensors = <&tsens 2>;
++
++ trips {
++ cpu-critical {
++ temperature = <120000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++
++ cpu_alert: cpu-passive {
++ temperature = <100000>;
++ hysteresis = <1000>;
++ type = "passive";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&cpu_alert>;
++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ };
++ };
++ };
++
++ gephy-thermal {
++ thermal-sensors = <&tsens 4>;
++
++ trips {
++ gephy-critical {
++ temperature = <120000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++ };
++ };
++
++ top-glue-thermal {
++ thermal-sensors = <&tsens 3>;
++
++ trips {
++ top-glue-critical {
++ temperature = <120000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++ };
++ };
++
++ ubi32-thermal {
++ thermal-sensors = <&tsens 1>;
++
++ trips {
++ ubi32-critical {
++ temperature = <120000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++ };
++ };
++ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+++ /dev/null
-Date: Fri, 28 Feb 2025 09:11:39 +0400
-Subject: [PATCH v9 6/6] arm64: dts: qcom: ipq5018: Add tsens node
-
-
-IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use.
-There is no RPM, so tsens has to be manually enabled. Adding the tsens
-and nvmem nodes and adding 4 thermal sensors (zones). With the
-critical temperature being 120'C and action is to reboot.
-
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 169 ++++++++++++++++++++++++++
- 1 file changed, 169 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -182,6 +182,117 @@
- status = "disabled";
- };
-
-+ qfprom: qfprom@a0000 {
-+ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
-+ reg = <0x000a0000 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ tsens_mode: mode@249 {
-+ reg = <0x249 0x1>;
-+ bits = <0 3>;
-+ };
-+
-+ tsens_base1: base1@249 {
-+ reg = <0x249 0x2>;
-+ bits = <3 8>;
-+ };
-+
-+ tsens_base2: base2@24a {
-+ reg = <0x24a 0x2>;
-+ bits = <3 8>;
-+ };
-+
-+ tsens_s0_p1: s0-p1@24b {
-+ reg = <0x24b 0x2>;
-+ bits = <2 6>;
-+ };
-+
-+ tsens_s0_p2: s0-p2@24c {
-+ reg = <0x24c 0x1>;
-+ bits = <1 6>;
-+ };
-+
-+ tsens_s1_p1: s1-p1@24c {
-+ reg = <0x24c 0x2>;
-+ bits = <7 6>;
-+ };
-+
-+ tsens_s1_p2: s1-p2@24d {
-+ reg = <0x24d 0x2>;
-+ bits = <5 6>;
-+ };
-+
-+ tsens_s2_p1: s2-p1@24e {
-+ reg = <0x24e 0x2>;
-+ bits = <3 6>;
-+ };
-+
-+ tsens_s2_p2: s2-p2@24f {
-+ reg = <0x24f 0x1>;
-+ bits = <1 6>;
-+ };
-+
-+ tsens_s3_p1: s3-p1@24f {
-+ reg = <0x24f 0x2>;
-+ bits = <7 6>;
-+ };
-+
-+ tsens_s3_p2: s3-p2@250 {
-+ reg = <0x250 0x2>;
-+ bits = <5 6>;
-+ };
-+
-+ tsens_s4_p1: s4-p1@251 {
-+ reg = <0x251 0x2>;
-+ bits = <3 6>;
-+ };
-+
-+ tsens_s4_p2: s4-p2@254 {
-+ reg = <0x254 0x1>;
-+ bits = <0 6>;
-+ };
-+ };
-+
-+ tsens: thermal-sensor@4a9000 {
-+ compatible = "qcom,ipq5018-tsens";
-+ reg = <0x004a9000 0x1000>, /* TM */
-+ <0x004a8000 0x1000>; /* SROT */
-+
-+ nvmem-cells = <&tsens_mode>,
-+ <&tsens_base1>,
-+ <&tsens_base2>,
-+ <&tsens_s0_p1>,
-+ <&tsens_s0_p2>,
-+ <&tsens_s1_p1>,
-+ <&tsens_s1_p2>,
-+ <&tsens_s2_p1>,
-+ <&tsens_s2_p2>,
-+ <&tsens_s3_p1>,
-+ <&tsens_s3_p2>,
-+ <&tsens_s4_p1>,
-+ <&tsens_s4_p2>;
-+
-+ nvmem-cell-names = "mode",
-+ "base1",
-+ "base2",
-+ "s0_p1",
-+ "s0_p2",
-+ "s1_p1",
-+ "s1_p2",
-+ "s2_p1",
-+ "s2_p2",
-+ "s3_p1",
-+ "s3_p2",
-+ "s4_p1",
-+ "s4_p2";
-+
-+ interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
-+ interrupt-names = "uplow";
-+ #qcom,sensors = <5>;
-+ #thermal-sensor-cells = <1>;
-+ };
-+
- tlmm: pinctrl@1000000 {
- compatible = "qcom,ipq5018-tlmm";
- reg = <0x01000000 0x300000>;
-@@ -630,6 +741,64 @@
- };
- };
- };
-+
-+ thermal-zones {
-+ cpu-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 2>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <120000>;
-+ hysteresis = <2>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ gephy-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 4>;
-+
-+ trips {
-+ gephy-critical {
-+ temperature = <120000>;
-+ hysteresis = <2>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ top-glue-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 3>;
-+
-+ trips {
-+ top_glue-critical {
-+ temperature = <120000>;
-+ hysteresis = <2>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ ubi32-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 1>;
-+
-+ trips {
-+ ubi32-critical {
-+ temperature = <120000>;
-+ hysteresis = <2>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+ };
-
- timer {
- compatible = "arm,armv8-timer";
--- /dev/null
+From patchwork Mon Aug 18 11:33:47 2025
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Id: 14192807
+Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org
+ [10.30.226.201])
+ (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
+ (No client certificate requested)
+ by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEFC62E22A9;
+ Mon, 18 Aug 2025 11:33:51 +0000 (UTC)
+Authentication-Results: smtp.subspace.kernel.org;
+ arc=none smtp.client-ip=10.30.226.201
+ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
+ t=1755516831; cv=none;
+ b=VqLETc4T2um7UBDoagDhE5FaVjJLNoLCW45q/LUrwXoemwWqIFZm7XVzEyPjuUDYlgOw9BuQEdRd7nWhXOVdv1pxkbIOt4gS7MPPVGBilyaXc/sWLyd8qk0KNcIXV1rGmEZ7Ywn0BdnngdNfSAQvSACHhpyMZpGXRodCNPE5cls=
+ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
+ s=arc-20240116; t=1755516831; c=relaxed/simple;
+ bh=ZZKBTpL6UHyciqnKATbtrkmYynWeMCWrFd/2xcp++ww=;
+ h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:
+ In-Reply-To:To:Cc;
+ b=XU6nlgSFgahhOxRhNcFU7wdAqhbLs8Ra7XxTipYaqKQqtp7v39J0ju+HaZOu9YE8a+aN4qG3R/YMTtCxZWejrgk6wU7nT/KBLqhjd1G2f0bWq/4NipYk+S7xYZyfe2lpNpZ2SRUI/1h6BFPoUnMzTeeuH8VjX/qIM3oLVe2s968=
+ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
+ header.b=PKBRtdr/; arc=none smtp.client-ip=10.30.226.201
+Authentication-Results: smtp.subspace.kernel.org;
+ header.b="PKBRtdr/"
+Received: by smtp.kernel.org (Postfix) with ESMTPS id 7CDF3C4CEED;
+ Mon, 18 Aug 2025 11:33:51 +0000 (UTC)
+DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;
+ s=k20201202; t=1755516831;
+ bh=ZZKBTpL6UHyciqnKATbtrkmYynWeMCWrFd/2xcp++ww=;
+ h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;
+ b=PKBRtdr/YTJTrl92zpHzzAovfqaynlZxJFZ667MTjd+V2zpPVbh/Qw2YkWFGl8Zeg
+ JIv0gaRa7PdagA1GA06EbVEy4GO0sNTdf6FR9uMTB8QJLoShXHrFGEgBkV0GrW6GR2
+ l8QjDRsmfKbIfV7udOOmrqR83UfsKpyVH4F39JlEvteIsWQni/6UESQxGlGkBryduS
+ E2cVKO6sKNLJP6QVQf3TJeZsf5Xb+y/3xsqurGnhx7LD7r26jt0UaWQouihdlLn4lj
+ AEw/X1Kg1G29aq65wiw0DT5mBXOiR0gDatBMXU/FSddyoCFlqbrMLijDrt/R6gGmcS
+ tgOzuwrEZQhrA==
+Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org
+ (localhost.localdomain [127.0.0.1])
+ by smtp.lore.kernel.org (Postfix) with ESMTP id 6E9D7CA0EE4;
+ Mon, 18 Aug 2025 11:33:51 +0000 (UTC)
+Date: Mon, 18 Aug 2025 15:33:47 +0400
+Subject: [PATCH 2/2] arm64: dts: qcom: ipq5018: Remove tsens v1 fallback
+ compatible
+Precedence: bulk
+List-Id: <linux-arm-msm.vger.kernel.org>
+MIME-Version: 1.0
+X-Mailer: b4 0.14.2
+X-Developer-Signature: v=1; a=ed25519-sha256; t=1755516829; l=972;
+ bh=HJcOgtw7oiilIyh0aWOOzNZ2iln5P6lSb3GMC6Gave0=;
+ b=uR1EVwZAX79JKZzxxM9N7TA/hO1CtlDORhZ/FGhSsA68dLhwH953wdmIPFDj4vfeWpsTsB3Bh
+ 4W66WWUho9RBMALQ66he3JtRH90AzRDuzcypOj7GRnzE6ehzDO8Gl3R
+ pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk=
+ with auth_id=364
+
+
+Remove qcom,tsens-v1 as fallback compatible since this IP has no RPM
+and, as such, must use its own init routine available in the driver.
+
+---
+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+@@ -340,7 +340,7 @@
+ };
+
+ tsens: thermal-sensor@4a9000 {
+- compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
++ compatible = "qcom,ipq5018-tsens";
+ reg = <0x004a9000 0x1000>,
+ <0x004a8000 0x1000>;
+
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -338,6 +338,16 @@
+@@ -341,6 +341,16 @@
reg = <0x01937000 0x21000>;
};
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -293,6 +293,30 @@
+@@ -296,6 +296,30 @@
#thermal-sensor-cells = <1>;
};
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -254,6 +254,14 @@
+@@ -257,6 +257,14 @@
};
};
+ };
+
tsens: thermal-sensor@4a9000 {
- compatible = "qcom,ipq5018-tsens";
- reg = <0x004a9000 0x1000>, /* TM */
+ compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
+ reg = <0x004a9000 0x1000>,
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -417,6 +417,16 @@
+@@ -420,6 +420,16 @@
status = "disabled";
};
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -441,6 +441,21 @@
+@@ -444,6 +444,21 @@
status = "disabled";
};
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -456,6 +456,36 @@
+@@ -459,6 +459,36 @@
status = "disabled";
};
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -16,6 +16,12 @@
+@@ -17,6 +17,12 @@
#size-cells = <2>;
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
-@@ -182,6 +188,17 @@
+@@ -185,6 +191,17 @@
status = "disabled";
};
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -188,6 +188,30 @@
+@@ -191,6 +191,30 @@
status = "disabled";
};
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -22,6 +22,18 @@
+@@ -23,6 +23,18 @@
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
-@@ -190,7 +202,8 @@
+@@ -193,7 +205,8 @@
mdio0: mdio@88000 {
compatible = "qcom,ipq5018-mdio";
#address-cells = <1>;
#size-cells = <0>;
-@@ -198,6 +211,13 @@
+@@ -201,6 +214,13 @@
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
};
mdio1: mdio@90000 {
-@@ -392,8 +412,8 @@
+@@ -395,8 +415,8 @@
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -201,7 +201,7 @@
+@@ -204,7 +204,7 @@
};
mdio0: mdio@88000 {
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -697,6 +697,225 @@
+@@ -700,6 +700,225 @@
};
};
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -123,6 +123,11 @@
+@@ -126,6 +126,11 @@
#size-cells = <2>;
ranges;
projects / openwrt / staging / thess.git / commitdiff