uboot-hifiveu: clear CSR only on FU740

Having this set on FU540 will result in a bootloader crashing
and burning with:
Error 0x0100000000000002

Signed-off-by: Zoltan HERPAI <[email protected]>

diff --git a/package/boot/uboot-hifiveu/patches/0035-riscv-clear-feature-disable-CSR.patch b/package/boot/uboot-hifiveu/patches/0035-riscv-clear-feature-disable-CSR.patch
new file mode 100644 (file)
index 0000000..f6eb09e
--- /dev/null
+++ b/package/boot/uboot-hifiveu/patches/0035-riscv-clear-feature-disable-CSR.patch
@@ -0,0 +1,30 @@
+From 91ca6d049f7d676069d7ff2c8b1ffa070da5aaa6 Mon Sep 17 00:00:00 2001
+From: Green Wan <[email protected]>
+Date: Mon, 22 Feb 2021 10:56:35 +0000
+Subject: [PATCH 35/52] riscv: clear feature disable CSR
+
+feature disable CSR should be cleared for each core to gain
+performance.
+
+Signed-off-by: Green Wan <[email protected]>
+---
+ arch/riscv/cpu/start.S | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
+index 8589509e01..c3d4647074 100644
+--- a/arch/riscv/cpu/start.S
++++ b/arch/riscv/cpu/start.S
+@@ -41,6 +41,9 @@ secondary_harts_relocation_error:
+ _start:
+ #if CONFIG_IS_ENABLED(RISCV_MMODE)
+       csrr    a0, CSR_MHARTID
++#ifdef CONFIG_TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740
++      csrwi   0x7c1, 0
++#endif
+ #endif
+ 
+       /*
+-- 
+2.30.2
+