realtek: rtl930x: Add support for Plasma Cloud PSX8 Switch
authorHarshal Gohel <[email protected]>
Fri, 11 Jul 2025 15:58:32 +0000 (15:58 +0000)
committerHauke Mehrtens <[email protected]>
Thu, 28 Aug 2025 19:07:57 +0000 (21:07 +0200)
The Plasma Cloud PSX8 Switch is a 8 port multi-GBit switch with
8x 10/100/1000/2500BaseT Ethernet ports.

Hardware:

- RTL9302C SoC
- Macronix MX25L25645G (32MB flash)
- Winbond W632GU6NB-12 (256MB DDR3 SDRAM - only 128 MB configured*)
- 2x RTL8224 4x 10m/100m/1/2.5 Gigabit PHY
- IC+ IP8008 POE+ PSE controller

The switch is powered by 54 Volts 2.77A barrel connector. The internal TTL
serial connector can be used to access the terminal. Pins from 1: TX RX
(unused) GND.  Serial connection is via 115200 baud, 8N1.

A reset button is accessible through a hole in the front panel.

*) Only 128 MB of RAM are currently configured because there were
infrequent random memory corruptions detected when using memtester with a
256 MB DT configuration. This could also be reproduced with RTLSDK.

Installation
------------

* The device can be flashed by using sysupgrade command. Either from the
  original vendor firmware or using an initramfs (see "Debug")
* Connect serial as per the layout above. Connection parameters: 115200 8N1
* The image must be copied using scp to /tmp of the device

      scp openwrt-realtek-rtl930x-plasmacloud_psx8-squashfs-sysupgrade.bin root@[IP address of the device]:/tmp/

* start sysupgrade without saving the original vendor configuration

      sysupgrade -n /tmp/openwrt-realtek-rtl930x-plasmacloud_psx8-squashfs-sysupgrade.bin

Installation via u-boot
-----------------------

If you have an TFTP server connected to the switch, it is possible to
directly install the device using the factory image from u-boot

    # setup networking and IP of TFP server
    rtk network on
    setenv ipaddr 10.100.100.99
    setenv serverip 10.100.100.20

    # get factory image
    tftp 0x84000000 factory.bin

    # erase firmware partitions
    sf probe 0
    sf erase 0x100000 0x01f00000

    # write firmware to both partitions
    sf write ${fileaddr} 0x100000 ${filesize}
    sf write ${fileaddr} 0x1080000 ${filesize}

    # adjust the boot commands
    setenv bootargs "mtdparts=spi0.0:896k(u-boot),64k(u-boot-env),64k(u-boot-env2),15872k(inactive),15872k(firmware2)"
    setenv bootcmd "rtk init; bootm 0xb5080000"

    # restart
    reset

Debug
-----

* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* A tftp server is required, tftpd-hpa works well.
* Power the device, at U-Boot start rapidly hit Esc key to stop autoboot
* Enable network:

      rtk network on

* Change ip address of device:

      setenv ipaddr 192.168.1.6

* Download initramfs from TFTP server:

      tftpboot 0x84000000 192.168.1.111:openwrt-realtek-rtl930x-plasmacloud_psx8-initramfs-kernel.bin

* Boot loaded file:

      bootm 0x84000000

Signed-off-by: Harshal Gohel <[email protected]>
Co-developed-by: Sharadanand Karanjkar <[email protected]>
Signed-off-by: Sharadanand Karanjkar <[email protected]>
Link: https://github.com/openwrt/openwrt/pull/19362
Signed-off-by: Hauke Mehrtens <[email protected]>
target/linux/realtek/base-files/etc/board.d/02_network
target/linux/realtek/base-files/lib/upgrade/platform.sh
target/linux/realtek/base-files/lib/upgrade/upgrade_dualboot_plasmacloud.sh
target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi [new file with mode: 0644]
target/linux/realtek/dts/rtl9302_plasmacloud_psx8.dts [new file with mode: 0644]
target/linux/realtek/image/rtl930x.mk

index fcca2ce6ea39c57bce136c75e1410f2b4501c825..1768d90ee05650dfd3c8de2ad79b41a9a22ce97d 100644 (file)
@@ -47,6 +47,7 @@ hpe,1920-48g-poe)
        lan_mac_start=$(macaddr_add $lan_mac 2)
        lan_mac_end=$(macaddr_add $lan_mac $((mac_count2-mac_count1)))
        ;;
+plasmacloud,psx8|\
 tplink,sg2008p-v1|\
 tplink,sg2210p-v3|\
 tplink,sg2452p-v4|\
index 6faded74b5bbdf93236e0e0ddbf7b37e4cf64d56..4d6da9a7b1790f97dd354aeb9bf137f821f07c60 100644 (file)
@@ -27,6 +27,10 @@ platform_do_upgrade() {
        local board=$(board_name)
 
        case "$board" in
+       plasmacloud,psx8)
+               PART_NAME="inactive"
+               platform_do_upgrade_dualboot_plasmacloud "$1"
+               ;;
        tplink,sg2008p-v1|\
        tplink,sg2210p-v3)
                tplink_sg2xxx_fix_mtdparts
index 0f379952b3afdbc25bf2eb4e96fa1d679690c918..91ffaa03ab0dac57d39d19525911dea4ea6312ef 100644 (file)
@@ -4,6 +4,18 @@ set_boot_part() {
        local board=$(board_name)
 
        case "$board" in
+       plasmacloud,psx8)
+               if [ "$part_num" = "1" ]; then
+                       echo "bootargs mtdparts=spi0.0:896k(u-boot),64k(u-boot-env),64k(u-boot-env2),15872k(firmware1),15872k(inactive)" > $setenv_script
+                       echo "bootcmd rtk init; bootm 0xb4100000" >> $setenv_script
+               elif [ "$part_num" = "2" ]; then
+                       echo "bootargs mtdparts=spi0.0:896k(u-boot),64k(u-boot-env),64k(u-boot-env2),15872k(inactive),15872k(firmware2)" > $setenv_script
+                       echo "bootcmd rtk init; bootm 0xb5080000" >> $setenv_script
+               else
+                       echo "Partition number $part_num is not supported for ${board}" 2>&1
+                       return 1
+               fi
+               ;;
        *)
                echo "${board} is not supported for dual boot" 1>&2
                return 1
@@ -44,6 +56,9 @@ platform_do_upgrade_dualboot_plasmacloud() {
        # identify "inactive" slot id based on the expected partition id
        # of the primary ("firmware1") slot
        case "$(board_name)" in
+       plasmacloud,psx8)
+               primary_firmware_mtd=3
+               ;;
        *)
                echo "failed to detect primary firmware mtd partition for board" 2>&1
                return 1
diff --git a/target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi b/target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi
new file mode 100644 (file)
index 0000000..b20823f
--- /dev/null
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl930x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+       chosen {
+               /* get active mtdparts from u-boot */
+               /delete-property/ bootargs;
+       };
+
+       aliases {
+               led-boot = &led_power;
+               led-running = &led_power;
+               led-failsafe = &led_power;
+               led-upgrade = &led_power;
+               label-mac-device = &ethernet0;
+       };
+
+       keys {
+               compatible = "gpio-keys";
+
+               mode {
+                       label = "reset";
+                       gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RESTART>;
+               };
+       };
+
+       i2c0: i2c-gpio0 {
+               compatible = "i2c-gpio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               sda-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+               scl-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+
+               i2c-gpio,delay-us = <5>;        /* ~100 kHz */
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinmux_disable_sys_led>;
+
+               led_power: led-0 {
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_POWER;
+                       gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+                       default-state = "on";
+               };
+
+               led-1 {
+                       color = <LED_COLOR_ID_RED>;
+                       function = LED_FUNCTION_STATUS;
+                       gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+                       default-state = "on";
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       led_set: led_set@0 {
+               compatible = "realtek,rtl9300-leds";
+               active-low;
+
+               led_set0 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_5G |
+                            RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_1G |
+                            RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M |
+                            RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
+       };
+};
+
+&spi0 {
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "u-boot";
+                               reg = <0x0 0xe0000>;
+                               read-only;
+                       };
+
+                       partition@e0000 {
+                               label = "u-boot-env";
+                               reg = <0xe0000 0x10000>;
+
+                               nvmem-layout {
+                                       compatible = "u-boot,env";
+
+                                       macaddr_ubootenv_ethaddr: ethaddr {
+                                               #nvmem-cell-cells = <1>;
+                                       };
+                               };
+                       };
+
+                       partition@f0000 {
+                               label = "u-boot-env2";
+                               reg = <0xf0000 0x10000>;
+                       };
+
+                       partition@100000 {
+                               label = "firmware1";
+                               reg = <0x100000 0xf80000>;
+                               compatible = "openwrt,uimage", "denx,uimage";
+                               openwrt,ih-magic = <0x93000000>;
+                       };
+
+                       partition@1080000 {
+                               label = "firmware2";
+                               reg = <0x1080000 0xf80000>;
+                               compatible = "openwrt,uimage", "denx,uimage";
+                               openwrt,ih-magic = <0x93000000>;
+                       };
+               };
+       };
+};
+
+&ethernet0 {
+       nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
+       nvmem-cell-names = "mac-address";
+
+       mdio: mdio-bus {
+               compatible = "realtek,rtl838x-mdio";
+               regmap = <&ethernet0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               /* External RTL8224 PHY */
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 0>;
+                       sds = < 2 >;
+               };
+
+               phy1: ethernet-phy@1 {
+                       reg = <1>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 1>;
+                       sds = < 2 >;
+               };
+
+               phy2: ethernet-phy@2 {
+                       reg = <2>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 2>;
+                       sds = < 2 >;
+               };
+
+               phy3: ethernet-phy@3 {
+                       reg = <3>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 3>;
+                       sds = < 2 >;
+               };
+
+               phy8: ethernet-phy@8 {
+                       reg = <8>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 4>;
+                       sds = < 3 >;
+               };
+
+               phy9: ethernet-phy@9 {
+                       reg = <9>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 5>;
+                       sds = < 3 >;
+               };
+
+               phy10: ethernet-phy@10 {
+                       reg = <10>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 6>;
+                       sds = < 3 >;
+               };
+
+               phy11: ethernet-phy@11 {
+                       reg = <11>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 7>;
+                       sds = < 3 >;
+               };
+       };
+};
+
+&switch0 {
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               SWITCH_PORT(0, 1, usxgmii)
+               SWITCH_PORT(1, 2, usxgmii)
+               SWITCH_PORT(2, 3, usxgmii)
+               SWITCH_PORT(3, 4, usxgmii)
+               SWITCH_PORT(8, 5, usxgmii)
+               SWITCH_PORT(9, 6, usxgmii)
+               SWITCH_PORT(10, 7, usxgmii)
+               SWITCH_PORT(11, 8, usxgmii)
+
+               /* CPU-port */
+               port@28 {
+                       ethernet = <&ethernet0>;
+                       reg = <28>;
+                       phy-mode = "internal";
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
+       };
+};
+
+&port0 {
+       nvmem-cells = <&macaddr_ubootenv_ethaddr 1>;
+       nvmem-cell-names = "mac-address";
+};
+
+&port1 {
+       nvmem-cells = <&macaddr_ubootenv_ethaddr 2>;
+       nvmem-cell-names = "mac-address";
+};
+
+&port2 {
+       nvmem-cells = <&macaddr_ubootenv_ethaddr 3>;
+       nvmem-cell-names = "mac-address";
+};
+
+&port3 {
+       nvmem-cells = <&macaddr_ubootenv_ethaddr 4>;
+       nvmem-cell-names = "mac-address";
+};
+
+&port8 {
+       nvmem-cells = <&macaddr_ubootenv_ethaddr 5>;
+       nvmem-cell-names = "mac-address";
+};
+
+&port9 {
+       nvmem-cells = <&macaddr_ubootenv_ethaddr 6>;
+       nvmem-cell-names = "mac-address";
+};
+
+&port10 {
+       nvmem-cells = <&macaddr_ubootenv_ethaddr 7>;
+       nvmem-cell-names = "mac-address";
+};
+
+&port11 {
+       nvmem-cells = <&macaddr_ubootenv_ethaddr 8>;
+       nvmem-cell-names = "mac-address";
+};
diff --git a/target/linux/realtek/dts/rtl9302_plasmacloud_psx8.dts b/target/linux/realtek/dts/rtl9302_plasmacloud_psx8.dts
new file mode 100644 (file)
index 0000000..227a5dc
--- /dev/null
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl9302_plasmacloud_common.dtsi"
+
+/ {
+       compatible = "plasmacloud,psx8", "realtek,rtl838x-soc";
+       model = "Plasma Cloud PSX8";
+};
+
+&led_set {
+       realtek,led-set0-force-port-mask = <0x0c000000>;
+};
index 27ad175b6e125a10f04323d8de438b3aa6bdd384..eb90b4678f6a920e5aa74aa07f57ca54585a7eb6 100644 (file)
@@ -14,6 +14,26 @@ define Device/hasivo_s1100w-8xgt-se
 endef
 TARGET_DEVICES += hasivo_s1100w-8xgt-se
 
+define Device/plasmacloud-common
+  SOC := rtl9302
+  UIMAGE_MAGIC := 0x93000000
+  DEVICE_VENDOR := Plasma Cloud
+  DEVICE_PACKAGES := poemgr
+  IMAGE_SIZE := 15872k
+  BLOCKSIZE := 64k
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma
+  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma | pad-to $$(BLOCKSIZE)
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-kernel | append-rootfs | pad-rootfs | check-size
+  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
+endef
+
+define Device/plasmacloud_psx8
+  $(Device/plasmacloud-common)
+  DEVICE_MODEL := PSX8
+endef
+TARGET_DEVICES += plasmacloud_psx8
+
 define Device/tplink_tl-st1008f_v2
   SOC := rtl9303
   UIMAGE_MAGIC := 0x93030000