rockchip: fixes typo and some bugs for suspend/resume tests

1. Remove the AP_PWROFF in ATF, should configure it in kernel.
2. Save and restore the PWMs pin/regs for suspend/resume.
3. The pmusgrf reset-hold bits needs to be released. since the
   pmusgrf reset-hold bits needs to be held.
4. Configure the PMU power up/down cycles about delay 3ms.
5. With the MMIO register block as one big mapping.
6. Fix the build error with psci_entrypoint since PSCI lib updated.

Fixes the commit
9ec78bd ("rockchip: support the suspend/resume for rk3399").

Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264

diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
index 9f94b0c13ae564fb2913b10a0e729a59be1da549..3378272cde883665df142e1eef88e65486984ce0 100644 (file)
--- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
+++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
@@ -70,7 +70,9 @@ sys_resume:
 psram_data:
        .quad   PSRAM_DT_BASE
 sys_wakeup_entry:
+#if !ERROR_DEPRECATED
        .quad   psci_entrypoint
+#endif
 pmu_cpuson_entrypoint_end:
        .word   0
 endfunc pmu_cpuson_entrypoint

diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index e106211e2d8f2062ffea2da6ce48026fd921228d..72d71bf734e902e0fa6ad570ee51824d9bee30c1 100644 (file)
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -747,9 +747,6 @@ static void sys_slp_config(void)
                      BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) |
                      BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW));
 
-       mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX,
-                     BIT_WITH_WMSK(AP_PWROFF));
-
        slp_mode_cfg = BIT(PMU_PWR_MODE_EN) |
                       BIT(PMU_POWER_OFF_REQ_CFG) |
                       BIT(PMU_CPU0_PD_EN) |
@@ -778,18 +775,18 @@ static void sys_slp_config(void)
        mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN));
        mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg);
 
-       mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_32K_CNT_MS(5));
-       mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(5));
+       mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_24M_CNT_MS(3));
+       mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_24M_CNT_MS(3));
        mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(PMU_24M_EN_CFG));
 
        mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW);
@@ -807,6 +804,72 @@ static void clr_hw_idle(uint32_t hw_idle)
        mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle);
 }
 
+struct pwm_data_s pwm_data;
+
+/*
+ * Save the PWMs data.
+ */
+static void save_pwms(void)
+{
+       uint32_t i;
+
+       pwm_data.iomux_bitmask = 0;
+
+       /* Save all IOMUXes */
+       if (mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX) & GPIO4C2_IOMUX_PWM)
+               pwm_data.iomux_bitmask |= PWM0_IOMUX_PWM_EN;
+       if (mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX) & GPIO4C6_IOMUX_PWM)
+               pwm_data.iomux_bitmask |= PWM1_IOMUX_PWM_EN;
+       if (mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX) &
+                        GPIO1C3_IOMUX_PWM)
+               pwm_data.iomux_bitmask |= PWM2_IOMUX_PWM_EN;
+       if (mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX) &
+                        GPIO0A6_IOMUX_PWM)
+               pwm_data.iomux_bitmask |= PWM3_IOMUX_PWM_EN;
+
+       for (i = 0; i < 4; i++) {
+               /* Save cnt, period, duty and ctrl for PWM i */
+               pwm_data.cnt[i] = mmio_read_32(PWM_BASE + PWM_CNT(i));
+               pwm_data.duty[i] = mmio_read_32(PWM_BASE + PWM_PERIOD_HPR(i));
+               pwm_data.period[i] = mmio_read_32(PWM_BASE + PWM_DUTY_LPR(i));
+               pwm_data.ctrl[i] = mmio_read_32(PWM_BASE + PWM_CTRL(i));
+       }
+
+       /* PWMs all IOMUXes switch to the gpio mode */
+       mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, GPIO4C2_IOMUX_GPIO);
+       mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, GPIO4C6_IOMUX_GPIO);
+       mmio_write_32(PMUGRF_BASE  + PMUGRF_GPIO1C_IOMUX, GPIO1C3_IOMUX_GPIO);
+       mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, GPIO0A6_IOMUX_GPIO);
+}
+
+/*
+ * Restore the PWMs data.
+ */
+static void restore_pwms(void)
+{
+       uint32_t i;
+
+       /* Restore all IOMUXes */
+       if (pwm_data.iomux_bitmask & PWM3_IOMUX_PWM_EN)
+               mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX,
+                             GPIO0A6_IOMUX_PWM);
+       if (pwm_data.iomux_bitmask & PWM2_IOMUX_PWM_EN)
+               mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX,
+                             GPIO1C3_IOMUX_PWM);
+       if (pwm_data.iomux_bitmask & PWM1_IOMUX_PWM_EN)
+               mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, GPIO4C6_IOMUX_PWM);
+       if (pwm_data.iomux_bitmask & PWM0_IOMUX_PWM_EN)
+               mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, GPIO4C2_IOMUX_PWM);
+
+       for (i = 0; i < 4; i++) {
+               /* Restore ctrl, duty, period and cnt for PWM i */
+               mmio_write_32(PWM_BASE + PWM_CTRL(i), pwm_data.ctrl[i]);
+               mmio_write_32(PWM_BASE + PWM_DUTY_LPR(i), pwm_data.period[i]);
+               mmio_write_32(PWM_BASE + PWM_PERIOD_HPR(i), pwm_data.duty[i]);
+               mmio_write_32(PWM_BASE + PWM_CNT(i), pwm_data.cnt[i]);
+       }
+}
+
 static int sys_pwr_domain_suspend(void)
 {
        uint32_t wait_cnt = 0;
@@ -853,8 +916,7 @@ static int sys_pwr_domain_suspend(void)
        }
        mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
 
-       /* TODO: Wait SoC to cut off the logic_center, switch the gpio mode */
-       mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, GPIO0A6_IOMUX_GPIO);
+       save_pwms();
 
        return 0;
 }
@@ -864,8 +926,7 @@ static int sys_pwr_domain_resume(void)
        uint32_t wait_cnt = 0;
        uint32_t status = 0;
 
-       /* TODO: switch the pwm mode */
-       mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, GPIO0A6_IOMUX_PWM);
+       restore_pwms();
 
        pmu_sgrf_rst_hld();
 

diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
index 797282f1fcd9bda0570fc0b3cbee0fabe2631f0c..ddb1c166da08098a707890678b5b766d6bcf9676 100644 (file)
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
@@ -810,10 +810,20 @@ enum pmu_core_pwr_st {
 
 #define PMUGRF_GPIO0A_IOMUX    0x00
 #define PMUGRF_GPIO1A_IOMUX    0x10
+#define PMUGRF_GPIO1C_IOMUX    0x18
+
 #define AP_PWROFF              0x0a
+
 #define GPIO0A6_IOMUX_GPIO     BITS_WITH_WMASK(0, 3, 12)
 #define GPIO0A6_IOMUX_PWM      BITS_WITH_WMASK(1, 3, 12)
+#define GPIO1C3_IOMUX_GPIO     BITS_WITH_WMASK(0, 3, 6)
+#define GPIO1C3_IOMUX_PWM      BITS_WITH_WMASK(1, 3, 6)
+#define GPIO4C2_IOMUX_GPIO     BITS_WITH_WMASK(0, 3, 4)
+#define GPIO4C2_IOMUX_PWM      BITS_WITH_WMASK(1, 3, 4)
+#define GPIO4C6_IOMUX_GPIO     BITS_WITH_WMASK(0, 3, 12)
+#define GPIO4C6_IOMUX_PWM      BITS_WITH_WMASK(1, 3, 12)
 #define GPIO1A6_IOMUX          BITS_WITH_WMASK(0, 3, 12)
+
 #define TSADC_INT_PIN          38
 #define CORES_PM_DISABLE       0x0
 #define CPU_AXI_QOS_ID_COREID          0x00
@@ -867,6 +877,8 @@ enum pmu_core_pwr_st {
 #define MAX_WAIT_COUNT         1000
 
 #define        GRF_SOC_CON4            0x0e210
+#define GRF_GPIO4C_IOMUX       0x0e028
+
 #define PMUGRF_SOC_CON0                0x0180
 
 #define CCI_FORCE_WAKEUP       WMSK_BIT(8)
@@ -901,6 +913,15 @@ enum pmu_core_pwr_st {
        mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \
 } while (0)
 
+/* there are 4 PWMs on rk3399 */
+struct pwm_data_s {
+       uint32_t iomux_bitmask;
+       uint64_t cnt[4];
+       uint64_t duty[4];
+       uint64_t period[4];
+       uint64_t ctrl[4];
+};
+
 struct pmu_slpdata_s {
        uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS];
        uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS];

diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index d11a2f6484b71abe14babe9392656ae2de610646..9ccf90c43cf318d642ddebc8036b2db4b587bdc1 100644 (file)
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -39,43 +39,7 @@
 
 /* Table of regions to map using the MMU.  */
 const mmap_region_t plat_rk_mmap[] = {
-       MAP_REGION_FLAT(GIC500_BASE, GIC500_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(CCI500_BASE, CCI500_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(STIME_BASE, STIME_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(CRUS_BASE, CRUS_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
-                       MT_DEVICE | MT_RW | MT_NS),
-       MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(RK3399_UART2_BASE, RK3399_UART2_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(PMUGRF_BASE, PMUGRF_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(GPIO4_BASE, GPIO4_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(SERVICE_NOC_0_BASE, NOC_0_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(SERVICE_NOC_1_BASE, NOC_1_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(SERVICE_NOC_2_BASE, NOC_2_SIZE,
-                       MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(SERVICE_NOC_3_BASE, NOC_3_SIZE,
+       MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE,
                        MT_DEVICE | MT_RW | MT_SECURE),
 
        { 0 }

diff --git a/plat/rockchip/rk3399/rk3399_def.h b/plat/rockchip/rk3399/rk3399_def.h
index 162869e08c872de562f68cf6b580394ce1ba64ef..787ec0cb105526548d81ae6bab752b2d8032c6a9 100644 (file)
--- a/plat/rockchip/rk3399/rk3399_def.h
+++ b/plat/rockchip/rk3399/rk3399_def.h
@@ -39,72 +39,82 @@
 #define SIZE_K(n)      ((n) * 1024)
 #define SIZE_M(n)      ((n) * 1024 * 1024)
 
-#define CCI500_BASE            0xffb00000
-#define CCI500_SIZE            SIZE_M(1)
+/* Register base address and size */
+#define MMIO_BASE              0xfe000000
 
-#define GIC500_BASE            0xfee00000
+#define GIC500_BASE            (MMIO_BASE + 0xe00000)
 #define GIC500_SIZE            SIZE_M(2)
 
-#define STIME_BASE             0xff860000
-#define STIME_SIZE             SIZE_K(64)
-
-#define CRUS_BASE              0xff750000
-#define CRUS_SIZE                      SIZE_K(128)
+#define PMU_BASE               (MMIO_BASE + 0x1310000)
+#define PMU_SIZE               SIZE_K(64)
 
-#define SGRF_BASE              0xff330000
-#define SGRF_SIZE                      SIZE_K(64)
+#define PMUGRF_BASE            (MMIO_BASE + 0x1320000)
+#define PMUGRF_SIZE            SIZE_K(64)
 
-#define PMU_BASE                       0xff310000
-#define PMU_SIZE                       SIZE_K(64)
+#define SGRF_BASE              (MMIO_BASE + 0x1330000)
+#define SGRF_SIZE              SIZE_K(64)
 
-#define PMUSRAM_BASE           0xff3b0000
+#define PMUSRAM_BASE           (MMIO_BASE + 0x13b0000)
 #define PMUSRAM_SIZE           SIZE_K(64)
 #define PMUSRAM_RSIZE          SIZE_K(8)
 
-#define PMUGRF_BASE            0xff320000
-#define PMUGRF_SIZE            SIZE_K(64)
+#define PWM_BASE               (MMIO_BASE + 0x1420000)
+#define PWM_SIZE               SIZE_K(64)
 
-#define GPIO0_BASE             0xff720000
+#define GPIO0_BASE             (MMIO_BASE + 0x1720000)
 #define GPIO0_SIZE             SIZE_K(64)
 
-#define GPIO1_BASE             0xff730000
+#define GPIO1_BASE             (MMIO_BASE + 0x1730000)
 #define GPIO1_SIZE             SIZE_K(64)
 
-#define GPIO2_BASE             0xff780000
+#define CRUS_BASE              (MMIO_BASE + 0x1750000)
+#define CRUS_SIZE              SIZE_K(128)
+
+#define GRF_BASE               (MMIO_BASE + 0x1770000)
+#define GRF_SIZE               SIZE_K(64)
+
+#define GPIO2_BASE             (MMIO_BASE + 0x1780000)
 #define GPIO2_SIZE             SIZE_K(32)
 
-#define GPIO3_BASE             0xff788000
+#define GPIO3_BASE             (MMIO_BASE + 0x1788000)
 #define GPIO3_SIZE             SIZE_K(32)
 
-#define GPIO4_BASE             0xff790000
+#define GPIO4_BASE             (MMIO_BASE + 0x1790000)
 #define GPIO4_SIZE             SIZE_K(32)
 
-#define GRF_BASE               0xff770000
-#define GRF_SIZE               SIZE_K(64)
+#define STIME_BASE             (MMIO_BASE + 0x1860000)
+#define STIME_SIZE             SIZE_K(64)
 
-#define SERVICE_NOC_0_BASE     0xffa50000
+#define SERVICE_NOC_0_BASE     (MMIO_BASE + 0x1a50000)
 #define NOC_0_SIZE             SIZE_K(192)
 
-#define SERVICE_NOC_1_BASE     0xffa84000
+#define SERVICE_NOC_1_BASE     (MMIO_BASE + 0x1a84000)
 #define NOC_1_SIZE             SIZE_K(16)
 
-#define SERVICE_NOC_2_BASE     0xffa8c000
+#define SERVICE_NOC_2_BASE     (MMIO_BASE + 0x1a8c000)
 #define NOC_2_SIZE             SIZE_K(16)
 
-#define SERVICE_NOC_3_BASE     0xffa90000
+#define SERVICE_NOC_3_BASE     (MMIO_BASE + 0x1a90000)
 #define NOC_3_SIZE             SIZE_K(448)
 
+#define CCI500_BASE            (MMIO_BASE + 0x1b00000)
+#define CCI500_SIZE            SIZE_M(1)
+
+/* Aggregate of all devices in the first GB */
+#define RK3399_DEV_RNG0_BASE   MMIO_BASE
+#define RK3399_DEV_RNG0_SIZE   0x1d00000
+
 /*
  * include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr
  * 0xff650000 -0xff6c0000
  */
-#define PD_BUS0_BASE           0xff650000
-#define PD_BUS0_SIZE           0x70000
+#define PD_BUS0_BASE           (MMIO_BASE + 0x1650000)
+#define PD_BUS0_SIZE           SIZE_K(448)
 
-#define PMUCRU_BASE            0xff750000
-#define CRU_BASE                       0xff760000
+#define PMUCRU_BASE            (MMIO_BASE + 0x1750000)
+#define CRU_BASE               (MMIO_BASE + 0x1760000)
 
-#define COLD_BOOT_BASE         0xffff0000
+#define COLD_BOOT_BASE         (MMIO_BASE + 0x1ff0000)
 
 /**************************************************************************
  * UART related constants
@@ -151,4 +161,14 @@
 #define RK3399_G1S_IRQS                        ARM_IRQ_SEC_PHY_TIMER
 #define RK3399_G0_IRQS                 ARM_IRQ_SEC_SGI_6
 
+#define PWM0_IOMUX_PWM_EN              (1 << 0)
+#define PWM1_IOMUX_PWM_EN              (1 << 1)
+#define PWM2_IOMUX_PWM_EN              (1 << 2)
+#define PWM3_IOMUX_PWM_EN              (1 << 3)
+
+#define PWM_CNT(n)                     0x0000 + 0x10 * n
+#define PWM_PERIOD_HPR(n)              0x0004 + 0x10 * n
+#define PWM_DUTY_LPR(n)                        0x0008 + 0x10 * n
+#define PWM_CTRL(n)                    0x000c + 0x10 * n
+
 #endif /* __PLAT_DEF_H__ */