--- /dev/null
+From 193563a005edc4e54426458ee6e097c8e4b38874 Mon Sep 17 00:00:00 2001
+Date: Sun, 19 Oct 2025 15:47:15 +0000
+Subject: [PATCH] spi: rockchip_sfc: Support sclk_x2 version
+
+SFC after version 8 supports dtr mode, so the IO is the binary output of
+the controller clock.
+
+---
+ drivers/spi/rockchip_sfc.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+--- a/drivers/spi/rockchip_sfc.c
++++ b/drivers/spi/rockchip_sfc.c
+@@ -108,6 +108,7 @@
+ #define SFC_VER_3 0x3
+ #define SFC_VER_4 0x4
+ #define SFC_VER_5 0x5
++#define SFC_VER_8 0x8
+
+ /* Delay line controller resiter */
+ #define SFC_DLL_CTRL0 0x3C
+@@ -589,6 +590,16 @@ static int rockchip_sfc_adjust_op_size(s
+ return 0;
+ }
+
++#if CONFIG_IS_ENABLED(CLK)
++static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, uint speed)
++{
++ if (sfc->version >= SFC_VER_8)
++ return clk_set_rate(&sfc->clk, speed * 2);
++ else
++ return clk_set_rate(&sfc->clk, speed);
++}
++#endif
++
+ static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
+ {
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
+@@ -600,7 +611,7 @@ static int rockchip_sfc_set_speed(struct
+ return 0;
+
+ #if CONFIG_IS_ENABLED(CLK)
+- int ret = clk_set_rate(&sfc->clk, speed);
++ int ret = rockchip_sfc_clk_set_rate(sfc, speed);
+
+ if (ret < 0) {
+ dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
--- /dev/null
+From 20c950de5e0431464b7068fdb2c6ec4ead3940ad Mon Sep 17 00:00:00 2001
+Date: Sun, 19 Oct 2025 15:47:16 +0000
+Subject: [PATCH] rockchip: spl: Add a read_brom_bootsource_id() helper
+
+The bootsource ids reported by BootROM of RK3528 and RK3576 for e.g.
+SPI NOR and USB differs slightly compared to prior SoCs:
+
+- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
+- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
+- Booting from sfc1 M0 has not been tested (no board using this config).
+- Booting from USB report a new bootsource id 0x81 on RK3528 and RK3576.
+
+Add a helper function to read the bootsource id. This helper function
+will be used to translate the new values to the common BROM_BOOTSOURCE
+enum values on RK3528 and RK3576.
+
+---
+ arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++
+ arch/arm/mach-rockchip/spl.c | 7 ++++++-
+ 2 files changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
++++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
+@@ -64,4 +64,6 @@ extern const char * const boot_devices[B
+ */
+ #define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10)
+
++u32 read_brom_bootsource_id(void);
++
+ #endif
+--- a/arch/arm/mach-rockchip/spl.c
++++ b/arch/arm/mach-rockchip/spl.c
+@@ -31,6 +31,11 @@ int board_return_to_bootrom(struct spl_i
+ __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ };
+
++__weak u32 read_brom_bootsource_id(void)
++{
++ return readl(BROM_BOOTSOURCE_ID_ADDR);
++}
++
+ const char *board_spl_was_booted_from(void)
+ {
+ static u32 brom_bootsource_id_cache = BROM_BOOTSOURCE_UNKNOWN;
+@@ -40,7 +45,7 @@ const char *board_spl_was_booted_from(vo
+ if (brom_bootsource_id_cache != BROM_BOOTSOURCE_UNKNOWN)
+ bootdevice_brom_id = brom_bootsource_id_cache;
+ else
+- bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
++ bootdevice_brom_id = read_brom_bootsource_id();
+
+ if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
+ bootdevice_ofpath = boot_devices[bootdevice_brom_id];
--- /dev/null
+From deee6a1cf623a81cb6de9ebe84cc6d1a393881f8 Mon Sep 17 00:00:00 2001
+Date: Sun, 19 Oct 2025 15:47:17 +0000
+Subject: [PATCH] rockchip: rk3528: Implement read_brom_bootsource_id()
+
+The bootsource ids reported by BootROM of RK3528 for e.g. USB differs
+compared to prior SoCs:
+
+- Booting from USB report a new bootsource id 0x81.
+
+Add a RK3528 specific read_brom_bootsource_id() function to help decode
+this new bootsource id value to help support booting from USB on RK3528.
+
+---
+ arch/arm/mach-rockchip/rk3528/rk3528.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/arch/arm/mach-rockchip/rk3528/rk3528.c
++++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
+@@ -49,6 +49,21 @@ void board_debug_uart_init(void)
+ {
+ }
+
++u32 read_brom_bootsource_id(void)
++{
++ u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR);
++
++ /* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE
++ * enum value to avoid having to create a larger boot_devices table.
++ */
++ if (bootsource_id == 0x81)
++ return BROM_BOOTSOURCE_USB;
++ else if (bootsource_id > BROM_LAST_BOOTSOURCE)
++ log_debug("Unknown bootsource %x\n", bootsource_id);
++
++ return bootsource_id;
++}
++
+ int arch_cpu_init(void)
+ {
+ u32 val;
--- /dev/null
+From 06d52d81cbd4275c86a7a150a23ab4d1dee8f435 Mon Sep 17 00:00:00 2001
+Date: Sun, 19 Oct 2025 15:47:18 +0000
+Subject: [PATCH] rockchip: rk3576: Add SPI Flash boot support
+
+The bootsource ids reported by BootROM of RK3576 for SPI NOR and USB
+differs slightly compared to prior SoCs:
+
+- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
+- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
+- Booting from sfc1 M0 has not been tested (no board using this config).
+- Booting from USB report a new bootsource id 0x81.
+
+Add a RK3576 specific read_brom_bootsource_id() function to help decode
+the new bootsource id values and the required boot_devices mapping of
+sfc0 and sfc1 to help support booting from SPI flash on RK3576.
+
+---
+ arch/arm/dts/rk3576-u-boot.dtsi | 46 ++++++++++++++++++++++++++
+ arch/arm/mach-rockchip/rk3576/rk3576.c | 25 ++++++++++++++
+ 2 files changed, 71 insertions(+)
+
+--- a/arch/arm/dts/rk3576-u-boot.dtsi
++++ b/arch/arm/dts/rk3576-u-boot.dtsi
+@@ -6,6 +6,11 @@
+ #include "rockchip-u-boot.dtsi"
+
+ / {
++ aliases {
++ spi5 = &sfc0;
++ spi6 = &sfc1;
++ };
++
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+@@ -16,6 +21,17 @@
+ };
+ };
+
++#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
++&binman {
++ simple-bin-spi {
++ mkimage {
++ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
++ offset = <0x8000>;
++ };
++ };
++};
++#endif
++
+ &cru {
+ bootph-all;
+ };
+@@ -45,6 +61,26 @@
+ bootph-some-ram;
+ };
+
++&fspi0_csn0 {
++ bootph-pre-ram;
++ bootph-some-ram;
++};
++
++&fspi0_pins {
++ bootph-pre-ram;
++ bootph-some-ram;
++};
++
++&fspi1m1_csn0 {
++ bootph-pre-ram;
++ bootph-some-ram;
++};
++
++&fspi1m1_pins {
++ bootph-pre-ram;
++ bootph-some-ram;
++};
++
+ &ioc_grf {
+ bootph-all;
+ };
+@@ -116,6 +152,16 @@
+ bootph-some-ram;
+ };
+
++&sfc0 {
++ bootph-some-ram;
++ u-boot,spl-sfc-no-dma;
++};
++
++&sfc1 {
++ bootph-some-ram;
++ u-boot,spl-sfc-no-dma;
++};
++
+ &sys_grf {
+ bootph-all;
+ };
+--- a/arch/arm/mach-rockchip/rk3576/rk3576.c
++++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
+@@ -36,8 +36,15 @@
+ #define USB_GRF_BASE 0x2601E000
+ #define USB3OTG0_CON1 0x0030
+
++enum {
++ BROM_BOOTSOURCE_FSPI0 = 3,
++ BROM_BOOTSOURCE_FSPI1_M1 = 6,
++};
++
+ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
++ [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0",
++ [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0",
+ [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
+ };
+
+@@ -85,6 +92,24 @@ void board_debug_uart_init(void)
+ {
+ }
+
++u32 read_brom_bootsource_id(void)
++{
++ u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR);
++
++ /* Re-map the raw value read from reg to a redefined or existing
++ * BROM_BOOTSOURCE enum value to avoid having to create a larger
++ * boot_devices table.
++ */
++ if (bootsource_id == 0x23)
++ return BROM_BOOTSOURCE_FSPI1_M1;
++ else if (bootsource_id == 0x81)
++ return BROM_BOOTSOURCE_USB;
++ else if (bootsource_id > BROM_LAST_BOOTSOURCE)
++ log_debug("Unknown bootsource %x\n", bootsource_id);
++
++ return bootsource_id;
++}
++
+ #define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
+ #define HP_CTRL_REG 0x04
+ #define TIMER_EN BIT(0)
--- /dev/null
+From 06cc02fe00d5a6d9ef51aa8852b891c0a5e3cf3e Mon Sep 17 00:00:00 2001
+Date: Sun, 19 Oct 2025 15:47:19 +0000
+Subject: [PATCH] board: rockchip: Add Radxa ROCK 4D
+
+The Radxa ROCK 4D is a compact single-board computer (SBC) featuring
+numerous top-tier functions, features, and expansion options.
+
+Equipped with the Rockchip RK3576 or RK3576J SoC, the ROCK 4D boasts an
+octa-core CPU (4x Cortex-A72 + 4x Cortex-A53), Mali-G52 GPU, and a
+powerful 6 TOPS NPU, making it ideal for AI and multimedia tasks.
+
+Features tested on a Radxa ROCK 4D v1.112:
+- SPI Flash boot
+- Ethernet
+- PCIe/NVMe
+- USB host
+
+ROCK 4D boards with SPI Flash is configured to boot from FSPI0->UFS->USB,
+or directly from USB when the MASKROM button is pressed, booting
+directly from SD-card is not possible on these boards.
+
+---
+ arch/arm/dts/rk3576-rock-4d-u-boot.dtsi | 10 ++++
+ arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++
+ configs/rock-4d-rk3576_defconfig | 68 +++++++++++++++++++++++
+ doc/board/rockchip/rockchip.rst | 1 +
+ 4 files changed, 85 insertions(+)
+ create mode 100644 arch/arm/dts/rk3576-rock-4d-u-boot.dtsi
+ create mode 100644 configs/rock-4d-rk3576_defconfig
+
+--- a/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts
++++ b/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts
+@@ -57,13 +57,13 @@
+ };
+ };
+
+- vcc_12v0_dcin: regulator-vcc-12v0-dcin {
++ vcc_5v0_dcin: regulator-vcc-5v0-dcin {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+- regulator-min-microvolt = <12000000>;
+- regulator-max-microvolt = <12000000>;
+- regulator-name = "vcc_12v0_dcin";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc_5v0_dcin";
+ };
+
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+@@ -166,7 +166,7 @@
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc_5v0_device";
+- vin-supply = <&vcc_12v0_dcin>;
++ vin-supply = <&vcc_5v0_sys>;
+ };
+
+ vcc_5v0_host: regulator-vcc-5v0-host {
+@@ -180,7 +180,21 @@
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc5v0_host";
+- vin-supply = <&vcc_5v0_device>;
++ vin-supply = <&vcc_5v0_sys>;
++ };
++
++ vcc_5v0_otg: regulator-vcc-5v0-otg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_otg_pwren>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v0_otg";
++ vin-supply = <&vcc_5v0_sys>;
+ };
+
+ vcc_5v0_sys: regulator-vcc-5v0-sys {
+@@ -190,10 +204,14 @@
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc_5v0_sys";
+- vin-supply = <&vcc_12v0_dcin>;
++ vin-supply = <&vcc_5v0_dcin>;
+ };
+ };
+
++&combphy0_ps {
++ status = "okay";
++};
++
+ &combphy1_psu {
+ status = "okay";
+ };
+@@ -641,17 +659,27 @@
+
+ &mdio0 {
+ rgmii_phy0: ethernet-phy@1 {
+- compatible = "ethernet-phy-ieee802.3-c22";
++ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ clocks = <&cru REFCLKO25M_GMAC0_OUT>;
++ assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>;
++ assigned-clock-rates = <25000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8211f_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+- reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
++ reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
++&pcie0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_reset>;
++ reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_pcie>;
++ status = "okay";
++};
++
+ &pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+@@ -678,11 +706,18 @@
+ pcie_pwren: pcie-pwren {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
++ pcie_reset: pcie-reset {
++ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
+ };
+
+ usb {
+ usb_host_pwren: usb-host-pwren {
+- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ usb_otg_pwren: usb-otg-pwren {
++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
++
+ };
+ };
+ };
+@@ -721,15 +756,38 @@
+ status = "okay";
+ };
+
++&u2phy0_otg {
++ phy-supply = <&vcc_5v0_otg>;
++ status = "okay";
++};
++
+ &u2phy1 {
+ status = "okay";
+ };
+
++&u2phy1_otg {
++ phy-supply = <&vcc_5v0_host>;
++ status = "okay";
++};
++
+ &uart0 {
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+ };
+
++&ufshc {
++ status = "okay";
++};
++
++&usbdp_phy {
++ status = "okay";
++};
++
++&usb_drd0_dwc3 {
++ dr_mode = "host";
++ status = "okay";
++};
++
+ &usb_drd1_dwc3 {
+ dr_mode = "host";
+ status = "okay";
+--- /dev/null
++++ b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi
+@@ -0,0 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++#include "rk3576-u-boot.dtsi"
++
++&sfc0 {
++ flash@0 {
++ bootph-pre-ram;
++ bootph-some-ram;
++ };
++};
+--- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS
++++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
+@@ -4,6 +4,12 @@ S: Maintained
+ F: arch/arm/dts/rk3576-generic*
+ F: configs/generic-rk3576_defconfig
+
++ROCK-4D-RK3576
++S: Maintained
++F: arch/arm/dts/rk3576-rock-4d*
++F: configs/rock-4d-rk3576_defconfig
++
+ SIGE5-RK3576
+ S: Maintained
+--- /dev/null
++++ b/configs/rock-4d-rk3576_defconfig
+@@ -0,0 +1,68 @@
++CONFIG_ARM=y
++CONFIG_SKIP_LOWLEVEL_INIT=y
++CONFIG_COUNTER_FREQUENCY=24000000
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SF_DEFAULT_SPEED=50000000
++CONFIG_SF_DEFAULT_MODE=0x2000
++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-rock-4d"
++CONFIG_ROCKCHIP_RK3576=y
++CONFIG_ROCKCHIP_SPI_IMAGE=y
++CONFIG_SYS_LOAD_ADDR=0x40c00800
++CONFIG_SF_DEFAULT_BUS=5
++CONFIG_DEBUG_UART_BASE=0x2AD40000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_SPL_SPI_FLASH_SUPPORT=y
++CONFIG_SPL_SPI=y
++CONFIG_PCI=y
++CONFIG_DEBUG_UART=y
++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-rock-4d.dtb"
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_SPL_MAX_SIZE=0x40000
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++CONFIG_SPL_SPI_LOAD=y
++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
++CONFIG_CMD_MEMINFO=y
++CONFIG_CMD_MEMINFO_MAP=y
++CONFIG_CMD_ADC=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MISC=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_RNG=y
++CONFIG_CMD_REGULATOR=y
++# CONFIG_SPL_DOS_PARTITION is not set
++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_LED=y
++CONFIG_LED_GPIO=y
++CONFIG_SUPPORT_EMMC_RPMB=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_SPI_FLASH_SFDP_SUPPORT=y
++CONFIG_SPI_FLASH_MACRONIX=y
++CONFIG_PHY_REALTEK=y
++CONFIG_DWC_ETH_QOS=y
++CONFIG_DWC_ETH_QOS_ROCKCHIP=y
++CONFIG_NVME_PCI=y
++CONFIG_PCIE_DW_ROCKCHIP=y
++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
++CONFIG_PHY_ROCKCHIP_USBDP=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYS_NS16550_MEM32=y
++CONFIG_ROCKCHIP_SFC=y
++CONFIG_SYSRESET_PSCI=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_DWC3=y
++CONFIG_USB_DWC3_GENERIC=y
++CONFIG_ERRNO_STR=y
+--- a/doc/board/rockchip/rockchip.rst
++++ b/doc/board/rockchip/rockchip.rst
+@@ -137,6 +137,7 @@ List of mainline supported Rockchip boar
+ - ArmSoM Sige5 (sige5-rk3576)
+ - Firefly ROC-RK3576-PC (roc-pc-rk3576)
+ - Generic RK3576 (generic-rk3576)
++ - Radxa ROCK 4D (rock-4d-rk3576)
+
+ * rk3588
+ - ArmSoM Sige7 (sige7-rk3588)
--- /dev/null
+From 37a5383059d0c3d8a72394cbffef775042a40acd Mon Sep 17 00:00:00 2001
+Date: Mon, 8 Sep 2025 19:32:18 +0800
+Subject: [PATCH] board: rockchip: add Lunzn FastRhino R66S
+
+Lunzn Fastrhino R66S is a high-performance mini router.
+
+Specification:
+- Rockchip RK3568
+- 1/2GB LPDDR4 RAM
+- SD card slot
+- 2x USB 3.0 Port
+- 2x 2500 Base-T (PCIe, r8125b)
+- 12v DC Jack
+
+---
+ .../arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi | 3 +
+ board/rockchip/evb_rk3568/MAINTAINERS | 7 ++
+ configs/fastrhino-r66s-rk3568_defconfig | 64 +++++++++++++++++++
+ doc/board/rockchip/rockchip.rst | 1 +
+ 4 files changed, 75 insertions(+)
+ create mode 100644 arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
+ create mode 100644 configs/fastrhino-r66s-rk3568_defconfig
+
+--- /dev/null
++++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
+@@ -0,0 +1,3 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++#include "rk356x-u-boot.dtsi"
+--- a/board/rockchip/evb_rk3568/MAINTAINERS
++++ b/board/rockchip/evb_rk3568/MAINTAINERS
+@@ -14,6 +14,13 @@ F: configs/evb-rk3568_defconfig
+ F: arch/arm/dts/rk3568-evb-u-boot.dtsi
+ F: arch/arm/dts/rk3568-evb.dts
+
++FASTRHINO-R66S-RK3568
++S: Maintained
++F: configs/fastrhino-r66s-rk3568_defconfig
++F: arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
++
+ GENERIC-RK3568
+ S: Maintained
+--- /dev/null
++++ b/configs/fastrhino-r66s-rk3568_defconfig
+@@ -0,0 +1,64 @@
++CONFIG_ARM=y
++CONFIG_SKIP_LOWLEVEL_INIT=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_COUNTER_FREQUENCY=24000000
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-fastrhino-r66s"
++CONFIG_ROCKCHIP_RK3568=y
++CONFIG_SPL_SERIAL=y
++CONFIG_SYS_LOAD_ADDR=0xc00800
++CONFIG_DEBUG_UART_BASE=0xFE660000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_PCI=y
++CONFIG_DEBUG_UART=y
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_FIT_SIGNATURE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_LEGACY_IMAGE_FORMAT=y
++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb"
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++CONFIG_SPL_MAX_SIZE=0x40000
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++CONFIG_SPL_ATF=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_PMIC=y
++CONFIG_CMD_REGULATOR=y
++# CONFIG_SPL_DOS_PARTITION is not set
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_OF_LIVE=y
++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_SPL_DM_SEQ_ALIAS=y
++CONFIG_SPL_REGMAP=y
++CONFIG_SPL_SYSCON=y
++CONFIG_SPL_CLK=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MISC=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_RTL8169=y
++CONFIG_PCIE_DW_ROCKCHIP=y
++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
++CONFIG_SPL_PINCTRL=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_SPL_RAM=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYS_NS16550_MEM32=y
++CONFIG_SYSRESET=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_DWC3=y
++CONFIG_USB_DWC3_GENERIC=y
++CONFIG_ERRNO_STR=y
+--- a/doc/board/rockchip/rockchip.rst
++++ b/doc/board/rockchip/rockchip.rst
+@@ -128,6 +128,7 @@ List of mainline supported Rockchip boar
+ - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568)
+ - Generic RK3566/RK3568 (generic-rk3568)
+ - Hardkernel ODROID-M1 (odroid-m1-rk3568)
++ - Lunzn FastRhino R66S (fastrhino-r66s-rk3568)
+ - QNAP TS-433 (qnap-ts433-rk3568)
+ - Radxa E25 Carrier Board (radxa-e25-rk3568)
+ - Radxa ROCK 3A (rock-3a-rk3568)
--- /dev/null
+From 498a9756adf57e94af64e31b144a6698c656c50a Mon Sep 17 00:00:00 2001
+Date: Mon, 14 Jul 2025 20:34:07 +0000
+Subject: [PATCH] mmc: rockchip_sdhci: Set xx_TAP_VALUE for RK3528
+
+eMMC erase and write support on RK3528 is somewhat unreliable, sometime
+e.g. mmc erase and write commands will fail with an error.
+
+Use the delay line lock value for half card clock cycle, DLL_LOCK_VALUE,
+to set a manual xx_TAP_VALUE to fix the unreliable eMMC support.
+
+This is only enabled for RK3528, remaining SoCs still use the automatic
+tap value, (DLL_LOCK_VALUE * 2) % 256, same value we configure manually
+for RK3528.
+
+---
+ drivers/mmc/rockchip_sdhci.c | 27 ++++++++++++++++++++++-----
+ 1 file changed, 22 insertions(+), 5 deletions(-)
+
+--- a/drivers/mmc/rockchip_sdhci.c
++++ b/drivers/mmc/rockchip_sdhci.c
+@@ -9,6 +9,7 @@
+ #include <dm.h>
+ #include <dm/ofnode.h>
+ #include <dt-structs.h>
++#include <linux/bitfield.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/libfdt.h>
+@@ -86,6 +87,9 @@
+ #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
+ #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
+ #define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30)
++#define DLL_TAPVALUE_FROM_SW BIT(25)
++#define DLL_TAP_VALUE_PREP(x) FIELD_PREP(GENMASK(15, 8), (x))
++#define DLL_LOCK_VALUE_GET(x) FIELD_GET(GENMASK(7, 0), (x))
+
+ #define DLL_LOCK_WO_TMOUT(x) \
+ ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
+@@ -93,6 +97,7 @@
+ #define ROCKCHIP_MAX_CLKS 3
+
+ #define FLAG_INVERTER_FLAG_IN_RXCLK BIT(0)
++#define FLAG_TAPVALUE_FROM_SW BIT(1)
+
+ struct rockchip_sdhc_plat {
+ struct mmc_config cfg;
+@@ -317,7 +322,7 @@ static int rk3568_sdhci_config_dll(struc
+ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+ struct mmc *mmc = host->mmc;
+ int val, ret;
+- u32 extra, txclk_tapnum;
++ u32 extra, txclk_tapnum, dll_tap_value;
+
+ if (!enable) {
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
+@@ -347,7 +352,15 @@ static int rk3568_sdhci_config_dll(struc
+ if (ret)
+ return ret;
+
+- extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
++ if (data->flags & FLAG_TAPVALUE_FROM_SW)
++ dll_tap_value = DLL_TAPVALUE_FROM_SW |
++ DLL_TAP_VALUE_PREP(DLL_LOCK_VALUE_GET(val) * 2);
++ else
++ dll_tap_value = 0;
++
++ extra = DWCMSHC_EMMC_DLL_DLYENA |
++ DLL_RXCLK_ORI_GATE |
++ dll_tap_value;
+ if (data->flags & FLAG_INVERTER_FLAG_IN_RXCLK)
+ extra |= DLL_RXCLK_NO_INVERTER;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
+@@ -361,19 +374,22 @@ static int rk3568_sdhci_config_dll(struc
+ DLL_CMDOUT_BOTH_CLK_EDGE |
+ DWCMSHC_EMMC_DLL_DLYENA |
+ data->hs400_cmdout_tapnum |
+- DLL_CMDOUT_TAPNUM_FROM_SW;
++ DLL_CMDOUT_TAPNUM_FROM_SW |
++ dll_tap_value;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
+ }
+
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_TXCLK_TAPNUM_FROM_SW |
+ DLL_TXCLK_NO_INVERTER |
+- txclk_tapnum;
++ txclk_tapnum |
++ dll_tap_value;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
+
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ data->hs400_strbin_tapnum |
+- DLL_STRBIN_TAPNUM_FROM_SW;
++ DLL_STRBIN_TAPNUM_FROM_SW |
++ dll_tap_value;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
+ } else {
+ /*
+@@ -663,6 +679,7 @@ static const struct sdhci_data rk3528_da
+ .set_ios_post = rk3568_sdhci_set_ios_post,
+ .set_clock = rk3568_sdhci_set_clock,
+ .config_dll = rk3568_sdhci_config_dll,
++ .flags = FLAG_TAPVALUE_FROM_SW,
+ .hs200_txclk_tapnum = 0xc,
+ .hs400_txclk_tapnum = 0x6,
+ .hs400_cmdout_tapnum = 0x6,
+++ /dev/null
-From 03610008ce31b7a780b7864a0a916d945b7234ba Mon Sep 17 00:00:00 2001
-Date: Mon, 8 Sep 2025 19:29:55 +0800
-Subject: [PATCH] board: rockchip: add Lunzn FastRhino R66S
-
-Lunzn Fastrhino R66S is a high-performance mini router.
-
-Specification:
-- Rockchip RK3568
-- 1/2GB LPDDR4 RAM
-- SD card slot
-- 2x USB 3.0 Port
-- 2x 2500 Base-T (PCIe, r8125b)
-- 12v DC Jack
-
----
- .../arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi | 3 +
- board/rockchip/evb_rk3568/MAINTAINERS | 7 ++
- configs/fastrhino-r66s-rk3568_defconfig | 64 +++++++++++++++++++
- doc/board/rockchip/rockchip.rst | 1 +
- 4 files changed, 75 insertions(+)
- create mode 100644 arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
- create mode 100644 configs/fastrhino-r66s-rk3568_defconfig
-
---- /dev/null
-+++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
-@@ -0,0 +1,3 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+
-+#include "rk356x-u-boot.dtsi"
---- a/board/rockchip/evb_rk3568/MAINTAINERS
-+++ b/board/rockchip/evb_rk3568/MAINTAINERS
-@@ -14,6 +14,13 @@ F: configs/evb-rk3568_defconfig
- F: arch/arm/dts/rk3568-evb-u-boot.dtsi
- F: arch/arm/dts/rk3568-evb.dts
-
-+FASTRHINO-R66S-RK3568
-+S: Maintained
-+F: configs/fastrhino-r66s-rk3568_defconfig
-+F: arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
-+
- GENERIC-RK3568
- S: Maintained
---- /dev/null
-+++ b/configs/fastrhino-r66s-rk3568_defconfig
-@@ -0,0 +1,64 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
-+CONFIG_COUNTER_FREQUENCY=24000000
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-fastrhino-r66s"
-+CONFIG_ROCKCHIP_RK3568=y
-+CONFIG_SPL_SERIAL=y
-+CONFIG_SYS_LOAD_ADDR=0xc00800
-+CONFIG_DEBUG_UART_BASE=0xFE660000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_PCI=y
-+CONFIG_DEBUG_UART=y
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_SPL_FIT_SIGNATURE=y
-+CONFIG_SPL_LOAD_FIT=y
-+CONFIG_LEGACY_IMAGE_FORMAT=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_DISPLAY_BOARDINFO_LATE=y
-+CONFIG_SPL_MAX_SIZE=0x40000
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_SPL_ATF=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_I2C=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_USB=y
-+CONFIG_CMD_PMIC=y
-+CONFIG_CMD_REGULATOR=y
-+# CONFIG_SPL_DOS_PARTITION is not set
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_OF_LIVE=y
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_SPL_DM_SEQ_ALIAS=y
-+CONFIG_SPL_REGMAP=y
-+CONFIG_SPL_SYSCON=y
-+CONFIG_SPL_CLK=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_MISC=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_RTL8169=y
-+CONFIG_PCIE_DW_ROCKCHIP=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-+CONFIG_SPL_PINCTRL=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_SPL_RAM=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYS_NS16550_MEM32=y
-+CONFIG_SYSRESET=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_DWC3=y
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_ERRNO_STR=y
---- a/doc/board/rockchip/rockchip.rst
-+++ b/doc/board/rockchip/rockchip.rst
-@@ -128,6 +128,7 @@ List of mainline supported Rockchip boar
- - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568)
- - Generic RK3566/RK3568 (generic-rk3568)
- - Hardkernel ODROID-M1 (odroid-m1-rk3568)
-+ - Lunzn FastRhino R66S (fastrhino-r66s-rk3568)
- - QNAP TS-433 (qnap-ts433-rk3568)
- - Radxa E25 Carrier Board (radxa-e25-rk3568)
- - Radxa ROCK 3A (rock-3a-rk3568)
CONFIG_SPL_MAX_SIZE=0x40000
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
-@@ -149,7 +149,7 @@ List of mainline supported Rockchip boar
+@@ -150,7 +150,7 @@ List of mainline supported Rockchip boar
- FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
- FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)
- GameForce Ace (gameforce-ace-rk3588s)
+++ /dev/null
-Subject: [PATCH v3 01/10] spi: rockchip_sfc: Support sclk_x2 version
-Date: Sun, 31 Aug 2025 11:20:22 +0000 [thread overview]
-
-
-SFC after version 8 supports dtr mode, so the IO is the binary output of
-the controller clock.
-
----
-v3: No change
-v2: No change
----
- drivers/spi/rockchip_sfc.c | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
-
---- a/drivers/spi/rockchip_sfc.c
-+++ b/drivers/spi/rockchip_sfc.c
-@@ -108,6 +108,7 @@
- #define SFC_VER_3 0x3
- #define SFC_VER_4 0x4
- #define SFC_VER_5 0x5
-+#define SFC_VER_8 0x8
-
- /* Delay line controller resiter */
- #define SFC_DLL_CTRL0 0x3C
-@@ -589,6 +590,16 @@ static int rockchip_sfc_adjust_op_size(s
- return 0;
- }
-
-+#if CONFIG_IS_ENABLED(CLK)
-+static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, uint speed)
-+{
-+ if (sfc->version >= SFC_VER_8)
-+ return clk_set_rate(&sfc->clk, speed * 2);
-+ else
-+ return clk_set_rate(&sfc->clk, speed);
-+}
-+#endif
-+
- static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
- {
- struct rockchip_sfc *sfc = dev_get_plat(bus);
-@@ -600,7 +611,7 @@ static int rockchip_sfc_set_speed(struct
- return 0;
-
- #if CONFIG_IS_ENABLED(CLK)
-- int ret = clk_set_rate(&sfc->clk, speed);
-+ int ret = rockchip_sfc_clk_set_rate(sfc, speed);
-
- if (ret < 0) {
- dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
+++ /dev/null
-Subject: [PATCH v3 02/10] rockchip: spl: Add a read_brom_bootsource_id() helper
-Date: Sun, 31 Aug 2025 11:20:23 +0000 [thread overview]
-
-The bootsource ids reported by BootROM of RK3528 and RK3576 for e.g.
-SPI NOR and USB differs slightly compared to prior SoCs:
-
-- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
-- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
-- Booting from sfc1 M0 has not been tested (no board using this config).
-- Booting from USB report a new bootsource id 0x81 on RK3528 and RK3576.
-
-Add a helper function to read the bootsource id. This helper function
-will be used to translate the new values to the common BROM_BOOTSOURCE
-enum values on RK3528 and RK3576.
-
----
-v3: Mention RK3528 in commit message
-v2: No change
----
- arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++
- arch/arm/mach-rockchip/spl.c | 7 ++++++-
- 2 files changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm/include/asm/arch-rockchip/bootrom.h
-+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
-@@ -64,4 +64,6 @@ extern const char * const boot_devices[B
- */
- #define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10)
-
-+u32 read_brom_bootsource_id(void);
-+
- #endif
---- a/arch/arm/mach-rockchip/spl.c
-+++ b/arch/arm/mach-rockchip/spl.c
-@@ -31,6 +31,11 @@ int board_return_to_bootrom(struct spl_i
- __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- };
-
-+__weak u32 read_brom_bootsource_id(void)
-+{
-+ return readl(BROM_BOOTSOURCE_ID_ADDR);
-+}
-+
- const char *board_spl_was_booted_from(void)
- {
- static u32 brom_bootsource_id_cache = BROM_BOOTSOURCE_UNKNOWN;
-@@ -40,7 +45,7 @@ const char *board_spl_was_booted_from(vo
- if (brom_bootsource_id_cache != BROM_BOOTSOURCE_UNKNOWN)
- bootdevice_brom_id = brom_bootsource_id_cache;
- else
-- bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
-+ bootdevice_brom_id = read_brom_bootsource_id();
-
- if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
- bootdevice_ofpath = boot_devices[bootdevice_brom_id];
+++ /dev/null
-Subject: [PATCH v3 04/10] rockchip: rk3576: Add SPI Flash boot support
-Date: Sun, 31 Aug 2025 11:20:25 +0000 [thread overview]
-
-The bootsource ids reported by BootROM of RK3576 for SPI NOR and USB
-differs slightly compared to prior SoCs:
-
-- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
-- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
-- Booting from sfc1 M0 has not been tested (no board using this config).
-- Booting from USB report a new bootsource id 0x81.
-
-Add a RK3576 specific read_brom_bootsource_id() function to help decode
-the new bootsource id values and the required boot_devices mapping of
-sfc0 and sfc1 to help support booting from SPI flash on RK3576.
-
----
-Changes in v3:
-- Add fspi1m1 pinctrl bootph- props to SoC u-boot.dtsi
-- Drop the incomplete support for FSPI1_M0
-- Add a short code comment about the re-mapping of bootsource id
-
-v2: No change
----
- arch/arm/dts/rk3576-u-boot.dtsi | 46 ++++++++++++++++++++++++++
- arch/arm/mach-rockchip/rk3576/rk3576.c | 25 ++++++++++++++
- 2 files changed, 71 insertions(+)
-
---- a/arch/arm/dts/rk3576-u-boot.dtsi
-+++ b/arch/arm/dts/rk3576-u-boot.dtsi
-@@ -6,6 +6,11 @@
- #include "rockchip-u-boot.dtsi"
-
- / {
-+ aliases {
-+ spi5 = &sfc0;
-+ spi6 = &sfc1;
-+ };
-+
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
- };
-@@ -16,6 +21,17 @@
- };
- };
-
-+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
-+&binman {
-+ simple-bin-spi {
-+ mkimage {
-+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
-+ offset = <0x8000>;
-+ };
-+ };
-+};
-+#endif
-+
- &cru {
- bootph-all;
- };
-@@ -45,6 +61,26 @@
- bootph-some-ram;
- };
-
-+&fspi0_csn0 {
-+ bootph-pre-ram;
-+ bootph-some-ram;
-+};
-+
-+&fspi0_pins {
-+ bootph-pre-ram;
-+ bootph-some-ram;
-+};
-+
-+&fspi1m1_csn0 {
-+ bootph-pre-ram;
-+ bootph-some-ram;
-+};
-+
-+&fspi1m1_pins {
-+ bootph-pre-ram;
-+ bootph-some-ram;
-+};
-+
- &ioc_grf {
- bootph-all;
- };
-@@ -116,6 +152,16 @@
- bootph-some-ram;
- };
-
-+&sfc0 {
-+ bootph-some-ram;
-+ u-boot,spl-sfc-no-dma;
-+};
-+
-+&sfc1 {
-+ bootph-some-ram;
-+ u-boot,spl-sfc-no-dma;
-+};
-+
- &sys_grf {
- bootph-all;
- };
---- a/arch/arm/mach-rockchip/rk3576/rk3576.c
-+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
-@@ -36,8 +36,15 @@
- #define USB_GRF_BASE 0x2601E000
- #define USB3OTG0_CON1 0x0030
-
-+enum {
-+ BROM_BOOTSOURCE_FSPI0 = 3,
-+ BROM_BOOTSOURCE_FSPI1_M1 = 6,
-+};
-+
- const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
-+ [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0",
-+ [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0",
- [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
- };
-
-@@ -85,6 +92,24 @@ void board_debug_uart_init(void)
- {
- }
-
-+u32 read_brom_bootsource_id(void)
-+{
-+ u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR);
-+
-+ /* Re-map the raw value read from reg to a redefined or existing
-+ * BROM_BOOTSOURCE enum value to avoid having to create a larger
-+ * boot_devices table.
-+ */
-+ if (bootsource_id == 0x23)
-+ return BROM_BOOTSOURCE_FSPI1_M1;
-+ else if (bootsource_id == 0x81)
-+ return BROM_BOOTSOURCE_USB;
-+ else if (bootsource_id > BROM_LAST_BOOTSOURCE)
-+ log_debug("Unknown bootsource %x\n", bootsource_id);
-+
-+ return bootsource_id;
-+}
-+
- #define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
- #define HP_CTRL_REG 0x04
- #define TIMER_EN BIT(0)
+++ /dev/null
-Subject: [PATCH v3 10/10] board: rockchip: Add Radxa ROCK 4D
-Date: Sun, 31 Aug 2025 11:20:31 +0000 [thread overview]
-
-The Radxa ROCK 4D is a compact single-board computer (SBC) featuring
-numerous top-tier functions, features, and expansion options.
-
-Equipped with the Rockchip RK3576 or RK3576J SoC, the ROCK 4D boasts an
-octa-core CPU (4x Cortex-A72 + 4x Cortex-A53), Mali-G52 GPU, and a
-powerful 6 TOPS NPU, making it ideal for AI and multimedia tasks.
-
-Features tested on a Radxa ROCK 4D v1.112:
-- SPI Flash boot
-- Ethernet
-- PCIe/NVMe
-- USB host
-
-ROCK 4D boards with SPI Flash is configured to boot from FSPI0->UFS->USB,
-or directly from USB when the MASKROM button is pressed, booting
-directly from SD-card is not possible on these boards.
-
----
-v3: Drop the reset-gpios prop rename
-v2: Add comment about the reset-gpios prop rename
----
- arch/arm/dts/rk3576-rock-4d-u-boot.dtsi | 10 ++++
- arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++
- configs/rock-4d-rk3576_defconfig | 68 +++++++++++++++++++++++
- doc/board/rockchip/rockchip.rst | 1 +
- 4 files changed, 85 insertions(+)
- create mode 100644 arch/arm/dts/rk3576-rock-4d-u-boot.dtsi
- create mode 100644 configs/rock-4d-rk3576_defconfig
-
---- a/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts
-+++ b/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts
-@@ -57,13 +57,13 @@
- };
- };
-
-- vcc_12v0_dcin: regulator-vcc-12v0-dcin {
-+ vcc_5v0_dcin: regulator-vcc-5v0-dcin {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-boot-on;
-- regulator-min-microvolt = <12000000>;
-- regulator-max-microvolt = <12000000>;
-- regulator-name = "vcc_12v0_dcin";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-name = "vcc_5v0_dcin";
- };
-
- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
-@@ -166,7 +166,7 @@
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "vcc_5v0_device";
-- vin-supply = <&vcc_12v0_dcin>;
-+ vin-supply = <&vcc_5v0_sys>;
- };
-
- vcc_5v0_host: regulator-vcc-5v0-host {
-@@ -180,7 +180,21 @@
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "vcc5v0_host";
-- vin-supply = <&vcc_5v0_device>;
-+ vin-supply = <&vcc_5v0_sys>;
-+ };
-+
-+ vcc_5v0_otg: regulator-vcc-5v0-otg {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb_otg_pwren>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-name = "vcc5v0_otg";
-+ vin-supply = <&vcc_5v0_sys>;
- };
-
- vcc_5v0_sys: regulator-vcc-5v0-sys {
-@@ -190,10 +204,14 @@
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "vcc_5v0_sys";
-- vin-supply = <&vcc_12v0_dcin>;
-+ vin-supply = <&vcc_5v0_dcin>;
- };
- };
-
-+&combphy0_ps {
-+ status = "okay";
-+};
-+
- &combphy1_psu {
- status = "okay";
- };
-@@ -641,17 +659,27 @@
-
- &mdio0 {
- rgmii_phy0: ethernet-phy@1 {
-- compatible = "ethernet-phy-ieee802.3-c22";
-+ compatible = "ethernet-phy-id001c.c916";
- reg = <0x1>;
- clocks = <&cru REFCLKO25M_GMAC0_OUT>;
-+ assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>;
-+ assigned-clock-rates = <25000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&rtl8211f_rst>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
-- reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
-+ reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
- };
- };
-
-+&pcie0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_reset>;
-+ reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc_3v3_pcie>;
-+ status = "okay";
-+};
-+
- &pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
-@@ -678,11 +706,18 @@
- pcie_pwren: pcie-pwren {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-+ pcie_reset: pcie-reset {
-+ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
- };
-
- usb {
- usb_host_pwren: usb-host-pwren {
-- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+ usb_otg_pwren: usb-otg-pwren {
-+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
-+
- };
- };
- };
-@@ -721,15 +756,38 @@
- status = "okay";
- };
-
-+&u2phy0_otg {
-+ phy-supply = <&vcc_5v0_otg>;
-+ status = "okay";
-+};
-+
- &u2phy1 {
- status = "okay";
- };
-
-+&u2phy1_otg {
-+ phy-supply = <&vcc_5v0_host>;
-+ status = "okay";
-+};
-+
- &uart0 {
- pinctrl-0 = <&uart0m0_xfer>;
- status = "okay";
- };
-
-+&ufshc {
-+ status = "okay";
-+};
-+
-+&usbdp_phy {
-+ status = "okay";
-+};
-+
-+&usb_drd0_dwc3 {
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
- &usb_drd1_dwc3 {
- dr_mode = "host";
- status = "okay";
---- /dev/null
-+++ b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi
-@@ -0,0 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include "rk3576-u-boot.dtsi"
-+
-+&sfc0 {
-+ flash@0 {
-+ bootph-pre-ram;
-+ bootph-some-ram;
-+ };
-+};
---- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS
-+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
-@@ -4,6 +4,12 @@ S: Maintained
- F: arch/arm/dts/rk3576-generic*
- F: configs/generic-rk3576_defconfig
-
-+ROCK-4D-RK3576
-+S: Maintained
-+F: arch/arm/dts/rk3576-rock-4d*
-+F: configs/rock-4d-rk3576_defconfig
-+
- SIGE5-RK3576
- S: Maintained
---- /dev/null
-+++ b/configs/rock-4d-rk3576_defconfig
-@@ -0,0 +1,68 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_COUNTER_FREQUENCY=24000000
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_SPEED=50000000
-+CONFIG_SF_DEFAULT_MODE=0x2000
-+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-rock-4d"
-+CONFIG_ROCKCHIP_RK3576=y
-+CONFIG_ROCKCHIP_SPI_IMAGE=y
-+CONFIG_SYS_LOAD_ADDR=0x40c00800
-+CONFIG_SF_DEFAULT_BUS=5
-+CONFIG_DEBUG_UART_BASE=0x2AD40000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_SPL_SPI_FLASH_SUPPORT=y
-+CONFIG_SPL_SPI=y
-+CONFIG_PCI=y
-+CONFIG_DEBUG_UART=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-rock-4d.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_SPL_MAX_SIZE=0x40000
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_SPL_SPI_LOAD=y
-+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
-+CONFIG_CMD_MEMINFO=y
-+CONFIG_CMD_MEMINFO_MAP=y
-+CONFIG_CMD_ADC=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_I2C=y
-+CONFIG_CMD_MISC=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_USB=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_RNG=y
-+CONFIG_CMD_REGULATOR=y
-+# CONFIG_SPL_DOS_PARTITION is not set
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_LED=y
-+CONFIG_LED_GPIO=y
-+CONFIG_SUPPORT_EMMC_RPMB=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-+CONFIG_SPI_FLASH_MACRONIX=y
-+CONFIG_PHY_REALTEK=y
-+CONFIG_DWC_ETH_QOS=y
-+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
-+CONFIG_NVME_PCI=y
-+CONFIG_PCIE_DW_ROCKCHIP=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-+CONFIG_PHY_ROCKCHIP_USBDP=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYS_NS16550_MEM32=y
-+CONFIG_ROCKCHIP_SFC=y
-+CONFIG_SYSRESET_PSCI=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_DWC3=y
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_ERRNO_STR=y
---- a/doc/board/rockchip/rockchip.rst
-+++ b/doc/board/rockchip/rockchip.rst
-@@ -138,6 +138,7 @@ List of mainline supported Rockchip boar
- - ArmSoM Sige5 (sige5-rk3576)
- - Firefly ROC-RK3576-PC (roc-pc-rk3576)
- - Generic RK3576 (generic-rk3576)
-+ - Radxa ROCK 4D (rock-4d-rk3576)
-
- * rk3588
- - ArmSoM Sige7 (sige7-rk3588)
projects / openwrt / openwrt.git / commitdiff