+++ /dev/null
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/bl_common.h>
-#include <common/desc_image_load.h>
-#include <platform_def.h>
-#include <plat/common/platform.h>
-
-
-/*******************************************************************************
- * Following descriptor provides BL image/ep information that gets used
- * by BL2 to load the images and also subset of this information is
- * passed to next BL image. The image loading sequence is managed by
- * populating the images in required loading order. The image execution
- * sequence is managed by populating the `next_handoff_image_id` with
- * the next executable image id.
- ******************************************************************************/
-static bl_mem_params_node_t bl2_mem_params_descs[] = {
-#ifdef SCP_BL2_BASE
- /* Fill SCP_BL2 related information if it exists */
- {
- .image_id = SCP_BL2_IMAGE_ID,
-
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
- VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
- VERSION_2, image_info_t, 0),
- .image_info.image_base = SCP_BL2_BASE,
- .image_info.image_max_size = SCP_BL2_SIZE,
-
- .next_handoff_image_id = INVALID_IMAGE_ID,
- },
-#endif /* SCP_BL2_BASE */
-
-#ifdef EL3_PAYLOAD_BASE
- /* Fill EL3 payload related information (BL31 is EL3 payload)*/
- {
- .image_id = BL31_IMAGE_ID,
-
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t,
- SECURE | EXECUTABLE | EP_FIRST_EXE),
- .ep_info.pc = EL3_PAYLOAD_BASE,
- .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS),
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t,
- IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
-
- .next_handoff_image_id = INVALID_IMAGE_ID,
- },
-
-#else /* EL3_PAYLOAD_BASE */
-
- /* Fill BL31 related information */
- {
- .image_id = BL31_IMAGE_ID,
-
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t,
- SECURE | EXECUTABLE | EP_FIRST_EXE),
- .ep_info.pc = BL31_BASE,
- .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS),
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
- .image_info.image_base = BL31_BASE,
- .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
-
- .next_handoff_image_id = BL33_IMAGE_ID,
- },
-#endif /* EL3_PAYLOAD_BASE */
-
- {
- .image_id = BL33_IMAGE_ID,
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
- .ep_info.pc = PLAT_NS_IMAGE_OFFSET,
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t, 0),
- .image_info.image_base = PLAT_NS_IMAGE_OFFSET,
- .image_info.image_max_size =
- 0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET,
-
- .next_handoff_image_id = INVALID_IMAGE_ID,
- },
-};
-
-REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
lib/cpus/aarch64/cortex_a53.S \
plat/intel/soc/agilex/bl2_plat_setup.c \
plat/intel/soc/agilex/socfpga_storage.c \
- plat/intel/soc/agilex/bl2_plat_mem_params_desc.c \
+ plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_handoff.c \
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/agilex/soc/agilex_memory_controller.c \
- plat/intel/soc/agilex/socfpga_delay_timer.c \
- plat/intel/soc/agilex/socfpga_image_load.c \
+ plat/intel/soc/common/socfpga_delay_timer.c \
+ plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/agilex/soc/agilex_system_manager.c \
plat/intel/soc/agilex/soc/agilex_mailbox.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/agilex/socfpga_sip_svc.c \
plat/intel/soc/agilex/bl31_plat_setup.c \
plat/intel/soc/agilex/socfpga_psci.c \
- plat/intel/soc/agilex/socfpga_topology.c \
- plat/intel/soc/agilex/socfpga_delay_timer.c \
+ plat/intel/soc/common/socfpga_topology.c \
+ plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
+++ /dev/null
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <arch_helpers.h>
-#include <drivers/delay_timer.h>
-#include <lib/mmio.h>
-
-#define AGX_GLOBAL_TIMER 0xffd01000
-#define AGX_GLOBAL_TIMER_EN 0x3
-
-/********************************************************************
- * The timer delay function
- ********************************************************************/
-static uint32_t socfpga_get_timer_value(void)
-{
- /*
- * Generic delay timer implementation expects the timer to be a down
- * counter. We apply bitwise NOT operator to the tick values returned
- * by read_cntpct_el0() to simulate the down counter. The value is
- * clipped from 64 to 32 bits.
- */
- return (uint32_t)(~read_cntpct_el0());
-}
-
-static const timer_ops_t plat_timer_ops = {
- .get_timer_value = socfpga_get_timer_value,
- .clk_mult = 1,
- .clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ,
-};
-
-void socfpga_delay_timer_init(void)
-{
- timer_init(&plat_timer_ops);
- mmio_write_32(AGX_GLOBAL_TIMER, AGX_GLOBAL_TIMER_EN);
-}
+++ /dev/null
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/desc_image_load.h>
-
-/*******************************************************************************
- * This function flushes the data structures so that they are visible
- * in memory for the next BL image.
- ******************************************************************************/
-void plat_flush_next_bl_params(void)
-{
- flush_bl_params_desc();
-}
-
-/*******************************************************************************
- * This function returns the list of loadable images.
- ******************************************************************************/
-bl_load_info_t *plat_get_bl_image_load_info(void)
-{
- return get_bl_load_info_from_mem_params_desc();
-}
-
-/*******************************************************************************
- * This function returns the list of executable images.
- ******************************************************************************/
-bl_params_t *plat_get_next_bl_params(void)
-{
- return get_next_bl_params_from_mem_params_desc();
-}
+++ /dev/null
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <platform_def.h>
-#include <lib/psci/psci.h>
-
-static const unsigned char plat_power_domain_tree_desc[] = {1, 4};
-
-/*******************************************************************************
- * This function returns the default topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return plat_power_domain_tree_desc;
-}
-
-/*******************************************************************************
- * This function implements a part of the critical interface between the psci
- * generic layer and the platform that allows the former to query the platform
- * to convert an MPIDR to a unique linear index. An error code (-1) is returned
- * in case the MPIDR is invalid.
- ******************************************************************************/
-int plat_core_pos_by_mpidr(u_register_t mpidr)
-{
- unsigned int cluster_id, cpu_id;
-
- mpidr &= MPIDR_AFFINITY_MASK;
-
- if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
- return -1;
-
- cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
- cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
-
- if (cluster_id >= PLATFORM_CLUSTER_COUNT)
- return -1;
-
- /*
- * Validate cpu_id by checking whether it represents a CPU in
- * one of the two clusters present on the platform.
- */
- if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
- return -1;
-
- return (cpu_id + (cluster_id * 4));
-}
-
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+#include <platform_def.h>
+#include <plat/common/platform.h>
+
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+#ifdef SCP_BL2_BASE
+ /* Fill SCP_BL2 related information if it exists */
+ {
+ .image_id = SCP_BL2_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = SCP_BL2_BASE,
+ .image_info.image_max_size = SCP_BL2_SIZE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+#endif /* SCP_BL2_BASE */
+
+#ifdef EL3_PAYLOAD_BASE
+ /* Fill EL3 payload related information (BL31 is EL3 payload)*/
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = EL3_PAYLOAD_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+#else /* EL3_PAYLOAD_BASE */
+
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL31_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+ .image_info.image_base = BL31_BASE,
+ .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+#endif /* EL3_PAYLOAD_BASE */
+
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+ .ep_info.pc = PLAT_NS_IMAGE_OFFSET,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = PLAT_NS_IMAGE_OFFSET,
+ .image_info.image_max_size =
+ 0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <arch_helpers.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#define SOCFPGA_GLOBAL_TIMER 0xffd01000
+#define SOCFPGA_GLOBAL_TIMER_EN 0x3
+
+/********************************************************************
+ * The timer delay function
+ ********************************************************************/
+static uint32_t socfpga_get_timer_value(void)
+{
+ /*
+ * Generic delay timer implementation expects the timer to be a down
+ * counter. We apply bitwise NOT operator to the tick values returned
+ * by read_cntpct_el0() to simulate the down counter. The value is
+ * clipped from 64 to 32 bits.
+ */
+ return (uint32_t)(~read_cntpct_el0());
+}
+
+static const timer_ops_t plat_timer_ops = {
+ .get_timer_value = socfpga_get_timer_value,
+ .clk_mult = 1,
+ .clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ,
+};
+
+void socfpga_delay_timer_init(void)
+{
+ timer_init(&plat_timer_ops);
+ mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
+}
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/desc_image_load.h>
+
+/*******************************************************************************
+ * This function flushes the data structures so that they are visible
+ * in memory for the next BL image.
+ ******************************************************************************/
+void plat_flush_next_bl_params(void)
+{
+ flush_bl_params_desc();
+}
+
+/*******************************************************************************
+ * This function returns the list of loadable images.
+ ******************************************************************************/
+bl_load_info_t *plat_get_bl_image_load_info(void)
+{
+ return get_bl_load_info_from_mem_params_desc();
+}
+
+/*******************************************************************************
+ * This function returns the list of executable images.
+ ******************************************************************************/
+bl_params_t *plat_get_next_bl_params(void)
+{
+ return get_next_bl_params_from_mem_params_desc();
+}
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <platform_def.h>
+#include <lib/psci/psci.h>
+
+static const unsigned char plat_power_domain_tree_desc[] = {1, 4};
+
+/*******************************************************************************
+ * This function returns the default topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return plat_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id;
+
+ mpidr &= MPIDR_AFFINITY_MASK;
+
+ if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
+ return -1;
+
+ cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+ if (cluster_id >= PLATFORM_CLUSTER_COUNT)
+ return -1;
+
+ /*
+ * Validate cpu_id by checking whether it represents a CPU in
+ * one of the two clusters present on the platform.
+ */
+ if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
+ return -1;
+
+ return (cpu_id + (cluster_id * 4));
+}
+
+++ /dev/null
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/bl_common.h>
-#include <common/desc_image_load.h>
-#include <platform_def.h>
-#include <plat/common/platform.h>
-
-
-/*******************************************************************************
- * Following descriptor provides BL image/ep information that gets used
- * by BL2 to load the images and also subset of this information is
- * passed to next BL image. The image loading sequence is managed by
- * populating the images in required loading order. The image execution
- * sequence is managed by populating the `next_handoff_image_id` with
- * the next executable image id.
- ******************************************************************************/
-static bl_mem_params_node_t bl2_mem_params_descs[] = {
-#ifdef SCP_BL2_BASE
- /* Fill SCP_BL2 related information if it exists */
- {
- .image_id = SCP_BL2_IMAGE_ID,
-
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
- VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
- VERSION_2, image_info_t, 0),
- .image_info.image_base = SCP_BL2_BASE,
- .image_info.image_max_size = SCP_BL2_SIZE,
-
- .next_handoff_image_id = INVALID_IMAGE_ID,
- },
-#endif /* SCP_BL2_BASE */
-
-#ifdef EL3_PAYLOAD_BASE
- /* Fill EL3 payload related information (BL31 is EL3 payload)*/
- {
- .image_id = BL31_IMAGE_ID,
-
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t,
- SECURE | EXECUTABLE | EP_FIRST_EXE),
- .ep_info.pc = EL3_PAYLOAD_BASE,
- .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS),
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t,
- IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
-
- .next_handoff_image_id = INVALID_IMAGE_ID,
- },
-
-#else /* EL3_PAYLOAD_BASE */
-
- /* Fill BL31 related information */
- {
- .image_id = BL31_IMAGE_ID,
-
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t,
- SECURE | EXECUTABLE | EP_FIRST_EXE),
- .ep_info.pc = BL31_BASE,
- .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS),
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
- .image_info.image_base = BL31_BASE,
- .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
-
- .next_handoff_image_id = BL33_IMAGE_ID,
- },
-#endif /* EL3_PAYLOAD_BASE */
-
- {
- .image_id = BL33_IMAGE_ID,
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
- .ep_info.pc = PLAT_NS_IMAGE_OFFSET,
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t, 0),
- .image_info.image_base = PLAT_NS_IMAGE_OFFSET,
- .image_info.image_max_size =
- 0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET,
-
- .next_handoff_image_id = INVALID_IMAGE_ID,
- },
-};
-
-REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
+++ /dev/null
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <arch_helpers.h>
-#include <drivers/delay_timer.h>
-#include <lib/mmio.h>
-
-#define S10_GLOBAL_TIMER 0xffd01000
-#define S10_GLOBAL_TIMER_EN 0x3
-
-/********************************************************************
- * The timer delay function
- ********************************************************************/
-static uint32_t plat_get_timer_value(void)
-{
- /*
- * Generic delay timer implementation expects the timer to be a down
- * counter. We apply bitwise NOT operator to the tick values returned
- * by read_cntpct_el0() to simulate the down counter. The value is
- * clipped from 64 to 32 bits.
- */
- return (uint32_t)(~read_cntpct_el0());
-}
-
-static const timer_ops_t plat_timer_ops = {
- .get_timer_value = plat_get_timer_value,
- .clk_mult = 1,
- .clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ,
-};
-
-void plat_delay_timer_init(void)
-{
- timer_init(&plat_timer_ops);
- mmio_write_32(S10_GLOBAL_TIMER, S10_GLOBAL_TIMER_EN);
-}
+++ /dev/null
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <platform_def.h>
-#include <lib/psci/psci.h>
-static const unsigned char plat_power_domain_tree_desc[] = {1, 4};
-
-/*******************************************************************************
- * This function returns the default topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return plat_power_domain_tree_desc;
-}
-
-/*******************************************************************************
- * This function implements a part of the critical interface between the psci
- * generic layer and the platform that allows the former to query the platform
- * to convert an MPIDR to a unique linear index. An error code (-1) is returned
- * in case the MPIDR is invalid.
- ******************************************************************************/
-int plat_core_pos_by_mpidr(u_register_t mpidr)
-{
- unsigned int cluster_id, cpu_id;
-
- mpidr &= MPIDR_AFFINITY_MASK;
-
- if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
- return -1;
-
- cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
- cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
-
- if (cluster_id >= PLATFORM_CLUSTER_COUNT)
- return -1;
-
- /*
- * Validate cpu_id by checking whether it represents a CPU in
- * one of the two clusters present on the platform.
- */
- if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
- return -1;
-
- return (cpu_id + (cluster_id * 4));
-}
-
drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
plat/intel/soc/stratix10/bl2_plat_setup.c \
plat/intel/soc/stratix10/plat_storage.c \
- plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c \
+ plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c \
plat/intel/soc/stratix10/soc/s10_handoff.c \
plat/intel/soc/stratix10/soc/s10_clock_manager.c \
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
- plat/intel/soc/stratix10/plat_delay_timer.c \
+ plat/intel/soc/common/socfpga_delay_timer.c \
lib/cpus/aarch64/cortex_a53.S \
- plat/intel/soc/stratix10/stratix10_image_load.c \
+ plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/stratix10/soc/s10_system_manager.c \
common/desc_image_load.c \
plat/intel/soc/stratix10/soc/s10_mailbox.c \
plat/intel/soc/stratix10/plat_sip_svc.c \
plat/intel/soc/stratix10/bl31_plat_setup.c \
plat/intel/soc/stratix10/plat_psci.c \
- plat/intel/soc/stratix10/plat_topology.c \
- plat/intel/soc/stratix10/plat_delay_timer.c \
+ plat/intel/soc/common/socfpga_topology.c \
+ plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c\
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/stratix10/soc/s10_clock_manager.c\
+++ /dev/null
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/desc_image_load.h>
-
-/*******************************************************************************
- * This function flushes the data structures so that they are visible
- * in memory for the next BL image.
- ******************************************************************************/
-void plat_flush_next_bl_params(void)
-{
- flush_bl_params_desc();
-}
-
-/*******************************************************************************
- * This function returns the list of loadable images.
- ******************************************************************************/
-bl_load_info_t *plat_get_bl_image_load_info(void)
-{
- return get_bl_load_info_from_mem_params_desc();
-}
-
-/*******************************************************************************
- * This function returns the list of executable images.
- ******************************************************************************/
-bl_params_t *plat_get_next_bl_params(void)
-{
- return get_next_bl_params_from_mem_params_desc();
-}
projects / project / bcm63xx / atf.git / commitdiff