drm/i915: fix the dequeue logic for single_port_submission context

For a single_port_submission context, GVT expects that it can only be
submitted to port 0, and there shouldn't be any other context in port 1
at the same time. This is required by GVT-g context to have an opportunity
to save/restore some non-hw context render registers.

This patch is to workaround GVT-g.

v2: optimized code by following Chris's advice, and added more comments to
explain the patch.
v3: followed the coding style.

Signed-off-by: Min He <[email protected]>
Reviewed-by: Zhenyu Wang <[email protected]>
Reviewed-by: Chris Wilson <[email protected]>
Signed-off-by: Chris Wilson <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 43526814e042bb87cf3659f100ded0168574bb71..0a09024d6ca3ebc502f0b99cef07ed91f0b4cd64 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -499,7 +499,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
                         * context (even though a different request) to
                         * the second port.
                         */
-                       if (ctx_single_port_submission(cursor->ctx))
+                       if (ctx_single_port_submission(last->ctx) ||
+                           ctx_single_port_submission(cursor->ctx))
                                break;
 
                        GEM_BUG_ON(last->ctx == cursor->ctx);