irqchip/atmel-aic5: Use per chip mask caches in mask/unmask()

When masking/unmasking interrupts, mask_cache is updated and used later
for suspend/resume. Unfortunately, it always was the mask_cache
associated with the first irq chip which was updated. So when performing
resume, only irqs 0-31 could be enabled.

Fixes: b1479ebb7720 ("irqchip: atmel-aic: Add atmel AIC/AIC5 drivers")
Signed-off-by: Ludovic Desroches <[email protected]>
Cc: <[email protected]>
Cc: <[email protected]>
Cc: <[email protected]>
Cc: <[email protected]>
Cc: <[email protected]>
Cc: <[email protected]>
Cc: <[email protected]>
Cc: <[email protected]>
Cc: [email protected] #3.18
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Thomas Gleixner <[email protected]>

diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
index 9da9942ac83c9e4ce861e193061f0f29df8b5700..f6d680485beecaf0ec870a0d7492146e3fb72090 100644 (file)
--- a/drivers/irqchip/irq-atmel-aic5.c
+++ b/drivers/irqchip/irq-atmel-aic5.c
@@ -88,28 +88,36 @@ static void aic5_mask(struct irq_data *d)
 {
        struct irq_domain *domain = d->domain;
        struct irq_domain_chip_generic *dgc = domain->gc;
-       struct irq_chip_generic *gc = dgc->gc[0];
+       struct irq_chip_generic *bgc = dgc->gc[0];
+       struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 
-       /* Disable interrupt on AIC5 */
-       irq_gc_lock(gc);
+       /*
+        * Disable interrupt on AIC5. We always take the lock of the
+        * first irq chip as all chips share the same registers.
+        */
+       irq_gc_lock(bgc);
        irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
        irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
        gc->mask_cache &= ~d->mask;
-       irq_gc_unlock(gc);
+       irq_gc_unlock(bgc);
 }
 
 static void aic5_unmask(struct irq_data *d)
 {
        struct irq_domain *domain = d->domain;
        struct irq_domain_chip_generic *dgc = domain->gc;
-       struct irq_chip_generic *gc = dgc->gc[0];
+       struct irq_chip_generic *bgc = dgc->gc[0];
+       struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 
-       /* Enable interrupt on AIC5 */
-       irq_gc_lock(gc);
+       /*
+        * Enable interrupt on AIC5. We always take the lock of the
+        * first irq chip as all chips share the same registers.
+        */
+       irq_gc_lock(bgc);
        irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
        irq_reg_writel(gc, 1, AT91_AIC5_IECR);
        gc->mask_cache |= d->mask;
-       irq_gc_unlock(gc);
+       irq_gc_unlock(bgc);
 }
 
 static int aic5_retrigger(struct irq_data *d)