These two memory barriers in performance-critical paths are not needed
on x86. Even if some other architecture does buffer PCI I/O space
writes, the existing memory-mapped I/O barriers are unlikely to be what
is needed.
Signed-off-by: John Dykstra <[email protected]>
Acked-by: Don Fry <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
/* Set interrupt enable. */
lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
- mmiowb();
+
spin_unlock_irqrestore(&lp->lock, flags);
}
return work_done;
val = lp->a.read_csr(ioaddr, CSR3);
val |= 0x5f00;
lp->a.write_csr(ioaddr, CSR3, val);
- mmiowb();
+
__napi_schedule(&lp->napi);
break;
}