--- /dev/null
+From dcf4fef6631c302f9bdd188979fe3172e47a29c7 Mon Sep 17 00:00:00 2001
+Date: Tue, 30 Jul 2024 17:11:04 +0100
+Subject: [PATCH] hwrng: rockchip - add hwrng driver for Rockchip RK3568 SoC
+
+Rockchip SoCs used to have a random number generator as part of their
+crypto device, and support for it has to be added to the corresponding
+driver. However newer Rockchip SoCs like the RK3568 have an independent
+True Random Number Generator device. This patch adds a driver for it,
+greatly inspired from the downstream driver.
+
+The TRNG device does not seem to have a signal conditionner and the FIPS
+140-2 test returns a lot of failures. They can be reduced by increasing
+RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value
+has been adjusted to get ~90% of successes and the quality value has
+been set accordingly.
+
+---
+ MAINTAINERS | 1 +
+ drivers/char/hw_random/Kconfig | 14 ++
+ drivers/char/hw_random/Makefile | 1 +
+ drivers/char/hw_random/rockchip-rng.c | 227 ++++++++++++++++++++++++++
+ 4 files changed, 243 insertions(+)
+ create mode 100644 drivers/char/hw_random/rockchip-rng.c
+
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -573,6 +573,20 @@ config HW_RANDOM_JH7110
+ To compile this driver as a module, choose M here.
+ The module will be called jh7110-trng.
+
++config HW_RANDOM_ROCKCHIP
++ tristate "Rockchip True Random Number Generator"
++ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
++ depends on HAS_IOMEM
++ default HW_RANDOM
++ help
++ This driver provides kernel-side support for the True Random Number
++ Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
++
++ To compile this driver as a module, choose M here: the
++ module will be called rockchip-rng.
++
++ If unsure, say Y.
++
+ endif # HW_RANDOM
+
+ config UML_RANDOM
+--- a/drivers/char/hw_random/Makefile
++++ b/drivers/char/hw_random/Makefile
+@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
+ obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
+ obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
+ obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
+ obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
+--- /dev/null
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -0,0 +1,227 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2022, Aurelien Jarno
++ * Authors:
++ */
++#include <linux/clk.h>
++#include <linux/hw_random.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#define RK_RNG_AUTOSUSPEND_DELAY 100
++#define RK_RNG_MAX_BYTE 32
++#define RK_RNG_POLL_PERIOD_US 100
++#define RK_RNG_POLL_TIMEOUT_US 10000
++
++/*
++ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
++ * a tradeoff between speed and quality and has been adjusted to get a quality
++ * of ~900 (~87.5% of FIPS 140-2 successes).
++ */
++#define RK_RNG_SAMPLE_CNT 1000
++
++/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
++#define TRNG_RST_CTL 0x0004
++#define TRNG_RNG_CTL 0x0400
++#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4)
++#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4)
++#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4)
++#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2)
++#define TRNG_RNG_CTL_MASK GENMASK(15, 0)
++#define TRNG_RNG_CTL_ENABLE BIT(1)
++#define TRNG_RNG_CTL_START BIT(0)
++#define TRNG_RNG_SAMPLE_CNT 0x0404
++#define TRNG_RNG_DOUT 0x0410
++
++struct rk_rng {
++ struct hwrng rng;
++ void __iomem *base;
++ struct reset_control *rst;
++ int clk_num;
++ struct clk_bulk_data *clk_bulks;
++};
++
++/* The mask in the upper 16 bits determines the bits that are updated */
++static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
++{
++ writel((mask << 16) | val, rng->base + TRNG_RNG_CTL);
++}
++
++static int rk_rng_init(struct hwrng *rng)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++ int ret;
++
++ /* start clocks */
++ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
++ if (ret < 0) {
++ dev_err((struct device *) rk_rng->rng.priv,
++ "Failed to enable clks %d\n", ret);
++ return ret;
++ }
++
++ /* set the sample period */
++ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
++
++ /* set osc ring speed and enable it */
++ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_LEN_256_BIT |
++ TRNG_RNG_CTL_OSC_RING_SPEED_0 |
++ TRNG_RNG_CTL_ENABLE,
++ TRNG_RNG_CTL_MASK);
++
++ return 0;
++}
++
++static void rk_rng_cleanup(struct hwrng *rng)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++ /* stop TRNG */
++ rk_rng_write_ctl(rk_rng, 0, TRNG_RNG_CTL_MASK);
++
++ /* stop clocks */
++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
++}
++
++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE);
++ u32 reg;
++ int ret = 0;
++
++ ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv);
++ if (ret < 0)
++ return ret;
++
++ /* Start collecting random data */
++ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_START, TRNG_RNG_CTL_START);
++
++ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
++ !(reg & TRNG_RNG_CTL_START),
++ RK_RNG_POLL_PERIOD_US,
++ RK_RNG_POLL_TIMEOUT_US);
++ if (ret < 0)
++ goto out;
++
++ /* Read random data stored in the registers */
++ memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read);
++out:
++ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
++ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
++
++ return (ret < 0) ? ret : to_read;
++}
++
++static int rk_rng_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct rk_rng *rk_rng;
++ int ret;
++
++ rk_rng = devm_kzalloc(dev, sizeof(*rk_rng), GFP_KERNEL);
++ if (!rk_rng)
++ return -ENOMEM;
++
++ rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(rk_rng->base))
++ return PTR_ERR(rk_rng->base);
++
++ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
++ if (rk_rng->clk_num < 0)
++ return dev_err_probe(dev, rk_rng->clk_num,
++ "Failed to get clks property\n");
++
++ rk_rng->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
++ if (IS_ERR(rk_rng->rst))
++ return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
++ "Failed to get reset property\n");
++
++ reset_control_assert(rk_rng->rst);
++ udelay(2);
++ reset_control_deassert(rk_rng->rst);
++
++ platform_set_drvdata(pdev, rk_rng);
++
++ rk_rng->rng.name = dev_driver_string(dev);
++ if (!IS_ENABLED(CONFIG_PM)) {
++ rk_rng->rng.init = rk_rng_init;
++ rk_rng->rng.cleanup = rk_rng_cleanup;
++ }
++ rk_rng->rng.read = rk_rng_read;
++ rk_rng->rng.priv = (unsigned long) dev;
++ rk_rng->rng.quality = 900;
++
++ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
++ pm_runtime_use_autosuspend(dev);
++ devm_pm_runtime_enable(dev);
++
++ ret = devm_hwrng_register(dev, &rk_rng->rng);
++ if (ret)
++ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
++
++ return 0;
++}
++
++static int __maybe_unused rk_rng_runtime_suspend(struct device *dev)
++{
++ struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++ rk_rng_cleanup(&rk_rng->rng);
++
++ return 0;
++}
++
++static int __maybe_unused rk_rng_runtime_resume(struct device *dev)
++{
++ struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++ return rk_rng_init(&rk_rng->rng);
++}
++
++static const struct dev_pm_ops rk_rng_pm_ops = {
++ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
++ rk_rng_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++ pm_runtime_force_resume)
++};
++
++static const struct of_device_id rk_rng_dt_match[] = {
++ { .compatible = "rockchip,rk3568-rng", },
++ { /* sentinel */ },
++};
++
++MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
++
++static struct platform_driver rk_rng_driver = {
++ .driver = {
++ .name = "rockchip-rng",
++ .pm = &rk_rng_pm_ops,
++ .of_match_table = rk_rng_dt_match,
++ },
++ .probe = rk_rng_probe,
++};
++
++module_platform_driver(rk_rng_driver);
++
++MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver");
++MODULE_LICENSE("GPL");
+++ /dev/null
-From 8b9c12757f919157752646faf3821abf2b7d2a64 Mon Sep 17 00:00:00 2001
-Date: Fri, 22 Nov 2024 15:30:05 +0800
-Subject: [PATCH] arm64: dts: rockchip: add reset-names for combphy on rk3568
-
-The reset-names of combphy are missing, add it.
-
-Fixes: fd3ac6e80497 ("dt-bindings: phy: rockchip: rk3588 has two reset lines")
----
- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 +
- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 ++
- 2 files changed, 3 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-@@ -223,6 +223,7 @@
- assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_PIPEPHY0>;
-+ reset-names = "phy";
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
- #phy-cells = <1>;
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1747,6 +1747,7 @@
- assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_PIPEPHY1>;
-+ reset-names = "phy";
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
- #phy-cells = <1>;
-@@ -1763,6 +1764,7 @@
- assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_PIPEPHY2>;
-+ reset-names = "phy";
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
- #phy-cells = <1>;
--- /dev/null
+From afeccc4084963aaa932931b734c8def55613c483 Mon Sep 17 00:00:00 2001
+Date: Tue, 30 Jul 2024 17:11:44 +0100
+Subject: [PATCH] arm64: dts: rockchip: add DT entry for RNG to RK356x
+
+Include the just added Rockchip RNG driver for RK356x SoCs and
+enable it on RK3568.
+
+Link: https://lore.kernel.org/r/d2beb15377dc8b580ca5557b1a4a6f50b74055aa.1722355365.git.daniel@makrotopia.org
+---
+ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++++
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
+ 2 files changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -257,6 +257,10 @@
+ };
+ };
+
++&rng {
++ status = "okay";
++};
++
+ &usb_host0_xhci {
+ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1106,6 +1106,16 @@
+ status = "disabled";
+ };
+
++ rng: rng@fe388000 {
++ compatible = "rockchip,rk3568-rng";
++ reg = <0x0 0xfe388000 0x0 0x4000>;
++ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
++ clock-names = "core", "ahb";
++ resets = <&cru SRST_TRNG_NS>;
++ reset-names = "reset";
++ status = "disabled";
++ };
++
+ i2s0_8ch: i2s@fe400000 {
+ compatible = "rockchip,rk3568-i2s-tdm";
+ reg = <0x0 0xfe400000 0x0 0x1000>;
--- /dev/null
+From ec532f3591ce6e6ed5ec6c35773a66aae118e1f0 Mon Sep 17 00:00:00 2001
+Date: Thu, 15 Aug 2024 18:25:19 +0200
+Subject: [PATCH] arm64: dts: rockchip: drop obsolete reset-names from rk356x
+ rng node
+
+The reset-names property is not part of the binding, so drop it.
+It is also not used by the driver, so that property was likely
+a leftover from some vendor-kernel node.
+
+Fixes: afeccc408496 ("arm64: dts: rockchip: add DT entry for RNG to RK356x")
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1112,7 +1112,6 @@
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+ clock-names = "core", "ahb";
+ resets = <&cru SRST_TRNG_NS>;
+- reset-names = "reset";
+ status = "disabled";
+ };
+
--- /dev/null
+From 8b9c12757f919157752646faf3821abf2b7d2a64 Mon Sep 17 00:00:00 2001
+Date: Fri, 22 Nov 2024 15:30:05 +0800
+Subject: [PATCH] arm64: dts: rockchip: add reset-names for combphy on rk3568
+
+The reset-names of combphy are missing, add it.
+
+Fixes: fd3ac6e80497 ("dt-bindings: phy: rockchip: rk3588 has two reset lines")
+---
+ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 +
+ arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 ++
+ 2 files changed, 3 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -223,6 +223,7 @@
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY0>;
++ reset-names = "phy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ #phy-cells = <1>;
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1756,6 +1756,7 @@
+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY1>;
++ reset-names = "phy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+ #phy-cells = <1>;
+@@ -1772,6 +1773,7 @@
+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY2>;
++ reset-names = "phy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+ #phy-cells = <1>;
+++ /dev/null
-From cea47ad1fbd46d3096fcf5c6905db3d12b5da960 Mon Sep 17 00:00:00 2001
-Date: Sun, 21 Jul 2024 01:48:04 +0100
-Subject: [PATCH 2/3] hwrng: add hwrng driver for Rockchip RK3568 SoC
-
-Rockchip SoCs used to have a random number generator as part of their
-crypto device, and support for it has to be added to the corresponding
-driver. However newer Rockchip SoCs like the RK3568 have an independent
-True Random Number Generator device. This patch adds a driver for it,
-greatly inspired from the downstream driver.
-
-The TRNG device does not seem to have a signal conditionner and the FIPS
-140-2 test returns a lot of failures. They can be reduced by increasing
-rockchip,sample-count in DT, in a tradeoff between quality and speed.
-
----
- drivers/char/hw_random/Kconfig | 14 ++
- drivers/char/hw_random/Makefile | 1 +
- drivers/char/hw_random/rockchip-rng.c | 230 ++++++++++++++++++++++++++
- 4 files changed, 246 insertions(+)
- create mode 100644 drivers/char/hw_random/rockchip-rng.c
-
---- a/drivers/char/hw_random/Kconfig
-+++ b/drivers/char/hw_random/Kconfig
-@@ -573,6 +573,20 @@ config HW_RANDOM_JH7110
- To compile this driver as a module, choose M here.
- The module will be called jh7110-trng.
-
-+config HW_RANDOM_ROCKCHIP
-+ tristate "Rockchip True Random Number Generator"
-+ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
-+ depends on HAS_IOMEM
-+ default HW_RANDOM
-+ help
-+ This driver provides kernel-side support for the True Random Number
-+ Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called rockchip-rng.
-+
-+ If unsure, say Y.
-+
- endif # HW_RANDOM
-
- config UML_RANDOM
---- a/drivers/char/hw_random/Makefile
-+++ b/drivers/char/hw_random/Makefile
-@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
- obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
- obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
- obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
-+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
- obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
---- /dev/null
-+++ b/drivers/char/hw_random/rockchip-rng.c
-@@ -0,0 +1,230 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC
-+ *
-+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
-+ * Copyright (c) 2022, Aurelien Jarno
-+ * Authors:
-+ */
-+#include <linux/clk.h>
-+#include <linux/hw_random.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#define RK_RNG_AUTOSUSPEND_DELAY 100
-+#define RK_RNG_MAX_BYTE 32
-+#define RK_RNG_POLL_PERIOD_US 100
-+#define RK_RNG_POLL_TIMEOUT_US 10000
-+
-+/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
-+#define TRNG_RST_CTL 0x0004
-+#define TRNG_RNG_CTL 0x0400
-+#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4)
-+#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4)
-+#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4)
-+#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2)
-+#define TRNG_RNG_CTL_MASK GENMASK(15, 0)
-+#define TRNG_RNG_CTL_ENABLE BIT(1)
-+#define TRNG_RNG_CTL_START BIT(0)
-+#define TRNG_RNG_SAMPLE_CNT 0x0404
-+#define TRNG_RNG_DOUT 0x0410
-+
-+struct rk_rng {
-+ struct hwrng rng;
-+ void __iomem *base;
-+ struct reset_control *rst;
-+ int clk_num;
-+ struct clk_bulk_data *clk_bulks;
-+ u32 sample_cnt;
-+};
-+
-+/* The mask in the upper 16 bits determines the bits that are updated */
-+static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
-+{
-+ writel((mask << 16) | val, rng->base + TRNG_RNG_CTL);
-+}
-+
-+static int rk_rng_init(struct hwrng *rng)
-+{
-+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+ int ret;
-+
-+ /* start clocks */
-+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
-+ if (ret < 0) {
-+ dev_err((struct device *) rk_rng->rng.priv,
-+ "Failed to enable clks %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* set the sample period */
-+ writel(rk_rng->sample_cnt, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
-+
-+ /* set osc ring speed and enable it */
-+ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_LEN_256_BIT |
-+ TRNG_RNG_CTL_OSC_RING_SPEED_0 |
-+ TRNG_RNG_CTL_ENABLE,
-+ TRNG_RNG_CTL_MASK);
-+
-+ return 0;
-+}
-+
-+static void rk_rng_cleanup(struct hwrng *rng)
-+{
-+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+ /* stop TRNG */
-+ rk_rng_write_ctl(rk_rng, 0, TRNG_RNG_CTL_MASK);
-+
-+ /* stop clocks */
-+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
-+}
-+
-+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE);
-+ u32 reg;
-+ int ret = 0;
-+
-+ ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* Start collecting random data */
-+ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_START, TRNG_RNG_CTL_START);
-+
-+ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
-+ !(reg & TRNG_RNG_CTL_START),
-+ RK_RNG_POLL_PERIOD_US,
-+ RK_RNG_POLL_TIMEOUT_US);
-+ if (ret < 0)
-+ goto out;
-+
-+ /* Read random data stored in the registers */
-+ memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read);
-+out:
-+ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
-+ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
-+
-+ return (ret < 0) ? ret : to_read;
-+}
-+
-+static int rk_rng_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct rk_rng *rk_rng;
-+ u32 quality;
-+ int ret;
-+
-+ rk_rng = devm_kzalloc(dev, sizeof(*rk_rng), GFP_KERNEL);
-+ if (!rk_rng)
-+ return -ENOMEM;
-+
-+ rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(rk_rng->base))
-+ return PTR_ERR(rk_rng->base);
-+
-+ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
-+ if (rk_rng->clk_num < 0)
-+ return dev_err_probe(dev, rk_rng->clk_num,
-+ "Failed to get clks property\n");
-+
-+ rk_rng->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
-+ if (IS_ERR(rk_rng->rst))
-+ return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
-+ "Failed to get reset property\n");
-+
-+ ret = of_property_read_u32(dev->of_node, "rockchip,sample-count", &rk_rng->sample_cnt);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Failed to get sample-count property\n");
-+
-+ ret = of_property_read_u32(dev->of_node, "quality", &quality);
-+ if (ret || quality > 1024)
-+ return dev_err_probe(dev, ret, "Failed to get quality property\n");
-+
-+ reset_control_assert(rk_rng->rst);
-+ udelay(2);
-+ reset_control_deassert(rk_rng->rst);
-+
-+ platform_set_drvdata(pdev, rk_rng);
-+
-+ rk_rng->rng.name = dev_driver_string(dev);
-+ if (!IS_ENABLED(CONFIG_PM)) {
-+ rk_rng->rng.init = rk_rng_init;
-+ rk_rng->rng.cleanup = rk_rng_cleanup;
-+ }
-+ rk_rng->rng.read = rk_rng_read;
-+ rk_rng->rng.priv = (unsigned long) dev;
-+ rk_rng->rng.quality = quality;
-+
-+ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
-+ pm_runtime_use_autosuspend(dev);
-+ devm_pm_runtime_enable(dev);
-+
-+ ret = devm_hwrng_register(dev, &rk_rng->rng);
-+ if (ret)
-+ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused rk_rng_runtime_suspend(struct device *dev)
-+{
-+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+ rk_rng_cleanup(&rk_rng->rng);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused rk_rng_runtime_resume(struct device *dev)
-+{
-+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+ return rk_rng_init(&rk_rng->rng);
-+}
-+
-+static const struct dev_pm_ops rk_rng_pm_ops = {
-+ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
-+ rk_rng_runtime_resume, NULL)
-+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
-+ pm_runtime_force_resume)
-+};
-+
-+static const struct of_device_id rk_rng_dt_match[] = {
-+ { .compatible = "rockchip,rk3568-rng", },
-+ { /* sentinel */ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
-+
-+static struct platform_driver rk_rng_driver = {
-+ .driver = {
-+ .name = "rockchip-rng",
-+ .pm = &rk_rng_pm_ops,
-+ .of_match_table = rk_rng_dt_match,
-+ },
-+ .probe = rk_rng_probe,
-+};
-+
-+module_platform_driver(rk_rng_driver);
-+
-+MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 756e7d3251ad8f6c72e7bf4c476537a89f673e38 Mon Sep 17 00:00:00 2001
-Date: Sun, 21 Jul 2024 01:48:38 +0100
-Subject: [PATCH 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x
-
-Enable the just added Rockchip RNG driver for RK356x SoCs.
-
----
- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 7 +++++++
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
- 2 files changed, 17 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-@@ -258,6 +258,13 @@
- };
- };
-
-+&rng {
-+ rockchip,sample-count = <1000>;
-+ quality = <900>;
-+
-+ status = "okay";
-+};
-+
- &usb_host0_xhci {
- phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1106,6 +1106,16 @@
- status = "disabled";
- };
-
-+ rng: rng@fe388000 {
-+ compatible = "rockchip,rk3568-rng";
-+ reg = <0x0 0xfe388000 0x0 0x4000>;
-+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
-+ clock-names = "core", "ahb";
-+ resets = <&cru SRST_TRNG_NS>;
-+ reset-names = "reset";
-+ status = "disabled";
-+ };
-+
- i2s0_8ch: i2s@fe400000 {
- compatible = "rockchip,rk3568-i2s-tdm";
- reg = <0x0 0xfe400000 0x0 0x1000>;
projects / openwrt / staging / pepe2k.git / commitdiff