spi: cadence_qspi: Fix clearing of pol/pha bits

Or'ing together bit positions is clearly wrong.

Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e285d3c1e761047cd9562dc0520c5fc6350c5a5f..2403e717dc4b9e2437fe61df258b78c5982fbffc 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -311,8 +311,8 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base,
 
        cadence_qspi_apb_controller_disable(reg_base);
        reg = readl(reg_base + CQSPI_REG_CONFIG);
-       reg &= ~(1 <<
-               (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
+       reg &= ~(1 << CQSPI_REG_CONFIG_CLK_POL_LSB);
+       reg &= ~(1 << CQSPI_REG_CONFIG_CLK_PHA_LSB);
 
        reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
        reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);