igb/e1000e: update PSSR_MDIX value to reflect correct bit

The phy port status register has the MDI-X status bit on bit 11, not bit 3
as is currently setup in the define.  This patch corrects that so the
correct bit is checked on igp PHY types.

Signed-off-by: Alexander Duyck <[email protected]>
Acked-by: Bruce Allan <[email protected]>
Signed-off-by: Jeff Kirsher <[email protected]>
Signed-off-by: David S. Miller <[email protected]>

diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index d8b82296f41e042cc3a7c9b486349d58b25e1802..6cdb703be9513816f17fbcaa4096dddd70d1f35d 100644 (file)
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -253,7 +253,7 @@ enum e1e_registers {
 #define IGP01E1000_PLHR_SS_DOWNGRADE   0x8000
 
 #define IGP01E1000_PSSR_POLARITY_REVERSED      0x0002
-#define IGP01E1000_PSSR_MDIX                   0x0008
+#define IGP01E1000_PSSR_MDIX                   0x0800
 #define IGP01E1000_PSSR_SPEED_MASK             0xC000
 #define IGP01E1000_PSSR_SPEED_1000MBPS         0xC000
 

diff --git a/drivers/net/igb/e1000_phy.h b/drivers/net/igb/e1000_phy.h
index 3228a862031f87a231d992458def9c93d1e0d54f..ebe4b616db8a472de823928b8de2109930dec153 100644 (file)
--- a/drivers/net/igb/e1000_phy.h
+++ b/drivers/net/igb/e1000_phy.h
@@ -80,7 +80,7 @@ s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
 #define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
 #define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
-#define IGP01E1000_PSSR_MDIX              0x0008
+#define IGP01E1000_PSSR_MDIX              0x0800
 #define IGP01E1000_PSSR_SPEED_MASK        0xC000
 #define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
 #define IGP02E1000_PHY_CHANNEL_NUM        4