MIPS: remove aliasing alignment if HW has antialising support
authorLeonid Yegoshin <[email protected]>
Fri, 20 Nov 2015 01:38:21 +0000 (17:38 -0800)
committerRalf Baechle <[email protected]>
Fri, 13 May 2016 12:02:16 +0000 (14:02 +0200)
MIPS hardware may have an antialising support and it works even
page size is small.

Setup a shared memory aliasing mask to page size if hardware has
an antialising support. Big shared memory mask forces a disruption
in page address assignment and that corrupts Android library memory
handling.

Signed-off-by: Leonid Yegoshin <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/11516/
Signed-off-by: Ralf Baechle <[email protected]>
arch/mips/mm/c-r4k.c

index d73b304cfe8a218e0c288923467046a5bf7ed26f..ef7f925dd1b0285ee743587962150f1592ac22af 100644 (file)
@@ -1721,7 +1721,7 @@ void r4k_cache_init(void)
         * This code supports virtually indexed processors and will be
         * unnecessarily inefficient on physically indexed processors.
         */
-       if (c->dcache.linesz)
+       if (c->dcache.linesz && cpu_has_dc_aliases)
                shm_align_mask = max_t( unsigned long,
                                        c->dcache.sets * c->dcache.linesz - 1,
                                        PAGE_SIZE - 1);