x86/mce: Add a Scalable MCA vendor flags bit

Scalable MCA (SMCA) is a new feature in AMD Fam17h processors
which indicates presence of MCA extensions.

MCA extensions expands existing register space for the MCE banks
and also introduces a new MSR range to accommodate new banks.

Add the detection bit.

Signed-off-by: Aravind Gopalakrishnan <[email protected]>
[ Reformat mce_vendor_flags definitions and save indentation levels. Improve comments. ]
Signed-off-by: Borislav Petkov <[email protected]>
Cc: Ashok Raj <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: H. Peter Anvin <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Tony Luck <[email protected]>
Cc: linux-edac <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 2dbc0bf2b9f3f7848d10025bb4bcfcf6d36a4d2d..2ea4527e462f133398f178a885a4b920892cd3f5 100644 (file)
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -123,19 +123,27 @@ struct mca_config {
 };
 
 struct mce_vendor_flags {
-                       /*
-                        * overflow recovery cpuid bit indicates that overflow
-                        * conditions are not fatal
-                        */
-       __u64           overflow_recov  : 1,
-
-                       /*
-                        * SUCCOR stands for S/W UnCorrectable error COntainment
-                        * and Recovery. It indicates support for data poisoning
-                        * in HW and deferred error interrupts.
-                        */
-                       succor          : 1,
-                       __reserved_0    : 62;
+       /*
+        * Indicates that overflow conditions are not fatal, when set.
+        */
+       __u64 overflow_recov    : 1,
+
+       /*
+        * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
+        * Recovery. It indicates support for data poisoning in HW and deferred
+        * error interrupts.
+        */
+             succor            : 1,
+
+       /*
+        * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
+        * the register space for each MCA bank and also increases number of
+        * banks. Also, to accommodate the new banks and registers, the MCA
+        * register space is moved to a new MSR range.
+        */
+             smca              : 1,
+
+             __reserved_0      : 61;
 };
 extern struct mce_vendor_flags mce_flags;
 

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 17b5ec6edcb6d016526753d33fb915c932f7564c..3d631c4abf9123c5b74df410209efe077cb0f7ff 100644 (file)
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1605,6 +1605,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
                mce_amd_feature_init(c);
                mce_flags.overflow_recov = !!(ebx & BIT(0));
                mce_flags.succor         = !!(ebx & BIT(1));
+               mce_flags.smca           = !!(ebx & BIT(3));
+
                break;
                }