SUBTARGETS:=generic mikrotik
KERNEL_PATCHVER:=5.4
-KERNEL_TESTING_PATCHVER:=5.4
+KERNEL_TESTING_PATCHVER:=5.10
KERNELNAME:=zImage Image dtbs
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APQ_GCC_8084 is not set
+# CONFIG_APQ_MMCC_8084 is not set
+CONFIG_AR40XX_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IPQ40XX=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+# CONFIG_ARCH_MDM9615 is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MSM8960 is not set
+# CONFIG_ARCH_MSM8974 is not set
+# CONFIG_ARCH_MSM8X60 is not set
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CPUIDLE=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_CRYPTO=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
+# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
+# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT803X_PHY=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BCH=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_QCOM=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_QCE=y
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
+CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
+CONFIG_CRYPTO_DEV_QCOM_RNG=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ESSEDMA=y
+CONFIG_EXTCON=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_74X164=y
+CONFIG_GPIO_WATCHDOG=y
+CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_OPTEE=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+# CONFIG_I2C_QCOM_CCI is not set
+CONFIG_I2C_QUP=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IO_URING=y
+# CONFIG_IPQ_APSS_PLL is not set
+CONFIG_IPQ_GCC_4019=y
+# CONFIG_IPQ_GCC_6018 is not set
+# CONFIG_IPQ_GCC_806X is not set
+# CONFIG_IPQ_GCC_8074 is not set
+# CONFIG_IPQ_LCC_806X is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_KPSS_XCC is not set
+# CONFIG_KRAITCC is not set
+CONFIG_LEDS_LP5523=y
+CONFIG_LEDS_LP5562=y
+CONFIG_LEDS_LP55XX_COMMON=y
+CONFIG_LIBFDT=y
+CONFIG_LLD_VERSION=0
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_IPQ4019=y
+# CONFIG_MDM_GCC_9615 is not set
+# CONFIG_MDM_LCC_9615 is not set
+CONFIG_MEMFD_CREATE=y
+# CONFIG_MFD_HI6421_SPMI is not set
+# CONFIG_MFD_QCOM_RPM is not set
+# CONFIG_MFD_SPMI_PMIC is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_MSM=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MSM_GCC_8660 is not set
+# CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8939 is not set
+# CONFIG_MSM_GCC_8960 is not set
+# CONFIG_MSM_GCC_8974 is not set
+# CONFIG_MSM_GCC_8994 is not set
+# CONFIG_MSM_GCC_8996 is not set
+# CONFIG_MSM_GCC_8998 is not set
+# CONFIG_MSM_GPUCC_8998 is not set
+# CONFIG_MSM_LCC_8960 is not set
+# CONFIG_MSM_MMCC_8960 is not set
+# CONFIG_MSM_MMCC_8974 is not set
+# CONFIG_MSM_MMCC_8996 is not set
+# CONFIG_MSM_MMCC_8998 is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_BCH=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NLS=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+# CONFIG_PHY_QCOM_APQ8064_SATA is not set
+CONFIG_PHY_QCOM_IPQ4019_USB=y
+# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
+# CONFIG_PHY_QCOM_IPQ806X_USB is not set
+# CONFIG_PHY_QCOM_PCIE2 is not set
+# CONFIG_PHY_QCOM_QMP is not set
+# CONFIG_PHY_QCOM_QUSB2 is not set
+# CONFIG_PHY_QCOM_USB_HS_28NM is not set
+# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
+# CONFIG_PHY_QCOM_USB_SS is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_APQ8064 is not set
+# CONFIG_PINCTRL_APQ8084 is not set
+CONFIG_PINCTRL_IPQ4019=y
+# CONFIG_PINCTRL_IPQ6018 is not set
+# CONFIG_PINCTRL_IPQ8064 is not set
+# CONFIG_PINCTRL_IPQ8074 is not set
+# CONFIG_PINCTRL_MDM9615 is not set
+CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8226 is not set
+# CONFIG_PINCTRL_MSM8660 is not set
+# CONFIG_PINCTRL_MSM8916 is not set
+# CONFIG_PINCTRL_MSM8960 is not set
+# CONFIG_PINCTRL_MSM8976 is not set
+# CONFIG_PINCTRL_MSM8994 is not set
+# CONFIG_PINCTRL_MSM8996 is not set
+# CONFIG_PINCTRL_MSM8998 is not set
+# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
+# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
+# CONFIG_PINCTRL_QCS404 is not set
+# CONFIG_PINCTRL_SC7180 is not set
+# CONFIG_PINCTRL_SDM660 is not set
+# CONFIG_PINCTRL_SDM845 is not set
+# CONFIG_PINCTRL_SM8150 is not set
+# CONFIG_PINCTRL_SM8250 is not set
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_QCA807X_PHY=y
+CONFIG_QCOM_A53PLL=y
+CONFIG_QCOM_BAM_DMA=y
+# CONFIG_QCOM_COMMAND_DB is not set
+# CONFIG_QCOM_CPR is not set
+# CONFIG_QCOM_EBI2 is not set
+# CONFIG_QCOM_GENI_SE is not set
+# CONFIG_QCOM_GSBI is not set
+# CONFIG_QCOM_HFPLL is not set
+# CONFIG_QCOM_IOMMU is not set
+# CONFIG_QCOM_LLCC is not set
+# CONFIG_QCOM_OCMEM is not set
+# CONFIG_QCOM_PDC is not set
+CONFIG_QCOM_QFPROM=y
+# CONFIG_QCOM_RMTFS_MEM is not set
+# CONFIG_QCOM_RPMH is not set
+CONFIG_QCOM_SCM=y
+# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
+CONFIG_QCOM_SMEM=y
+# CONFIG_QCOM_SMSM is not set
+# CONFIG_QCOM_SOCINFO is not set
+CONFIG_QCOM_TCSR=y
+# CONFIG_QCOM_TSENS is not set
+CONFIG_QCOM_WDT=y
+# CONFIG_QCS_GCC_404 is not set
+# CONFIG_QCS_Q6SSTOP_404 is not set
+# CONFIG_QCS_TURING_404 is not set
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+CONFIG_REGULATOR_VCTRL=y
+CONFIG_REGULATOR_VQMMC_IPQ4019=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_QCOM_AOSS is not set
+# CONFIG_RESET_QCOM_PDC is not set
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SC_DISPCC_7180 is not set
+# CONFIG_SC_GCC_7180 is not set
+# CONFIG_SC_GPUCC_7180 is not set
+# CONFIG_SC_LPASS_CORECC_7180 is not set
+# CONFIG_SC_MSS_7180 is not set
+# CONFIG_SC_VIDEOCC_7180 is not set
+# CONFIG_SDM_CAMCC_845 is not set
+# CONFIG_SDM_DISPCC_845 is not set
+# CONFIG_SDM_GCC_660 is not set
+# CONFIG_SDM_GCC_845 is not set
+# CONFIG_SDM_GPUCC_845 is not set
+# CONFIG_SDM_LPASSCC_845 is not set
+# CONFIG_SDM_VIDEOCC_845 is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+# CONFIG_SM_GCC_8150 is not set
+# CONFIG_SM_GCC_8250 is not set
+# CONFIG_SM_GPUCC_8150 is not set
+# CONFIG_SM_GPUCC_8250 is not set
+# CONFIG_SM_VIDEOCC_8150 is not set
+# CONFIG_SM_VIDEOCC_8250 is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+CONFIG_SPMI_MSM_PMIC_ARB=y
+# CONFIG_SPMI_PMIC_CLKDIV is not set
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TEE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
#include <linux/sysctl.h>
#include <linux/phy.h>
#include <linux/of_net.h>
+#include <linux/version.h>
#include <net/checksum.h>
#include <net/ip6_checksum.h>
#include <asm-generic/bug.h>
for (i = 0; i < edma_cinfo->num_gmac; i++) {
if (adapter[i]->poll_required) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0)
+ phy_interface_t phy_mode;
+ err = of_get_phy_mode(np, &phy_mode);
+ if (err < 0)
+#else
int phy_mode = of_get_phy_mode(np);
-
if (phy_mode < 0)
+#endif
phy_mode = PHY_INTERFACE_MODE_SGMII;
adapter[i]->phydev =
phy_connect(edma_netdev[i],
.get_ethtool_stats = &edma_get_ethtool_stats,
.get_coalesce = &edma_get_coalesce,
.set_coalesce = &edma_set_coalesce,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,7,0)
+ .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
+#endif
.get_priv_flags = edma_get_priv_flags,
.set_priv_flags = edma_set_priv_flags,
.get_ringparam = edma_get_ringparam,
--- /dev/null
+From 4267880319bc1a2270d352e0ded6d6386242a7ef Mon Sep 17 00:00:00 2001
+Date: Tue, 12 Aug 2014 20:49:27 +0200
+Subject: [PATCH 24/53] GPIO: add named gpio exports
+
+---
+ drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
+ drivers/gpio/gpiolib-sysfs.c | 10 +++++-
+ include/asm-generic/gpio.h | 6 ++++
+ include/linux/gpio/consumer.h | 8 +++++
+ 4 files changed, 91 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/gpiolib-of.c
++++ b/drivers/gpio/gpiolib-of.c
+@@ -19,6 +19,8 @@
+ #include <linux/pinctrl/pinctrl.h>
+ #include <linux/slab.h>
+ #include <linux/gpio/machine.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
+
+ #include "gpiolib.h"
+ #include "gpiolib-of.h"
+@@ -915,3 +917,68 @@ void of_gpiochip_remove(struct gpio_chip
+ {
+ of_node_put(chip->of_node);
+ }
++
++static struct of_device_id gpio_export_ids[] = {
++ { .compatible = "gpio-export" },
++ { /* sentinel */ }
++};
++
++static int of_gpio_export_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct device_node *cnp;
++ u32 val;
++ int nb = 0;
++
++ for_each_child_of_node(np, cnp) {
++ const char *name = NULL;
++ int gpio;
++ bool dmc;
++ int max_gpio = 1;
++ int i;
++
++ of_property_read_string(cnp, "gpio-export,name", &name);
++
++ if (!name)
++ max_gpio = of_gpio_count(cnp);
++
++ for (i = 0; i < max_gpio; i++) {
++ unsigned flags = 0;
++ enum of_gpio_flags of_flags;
++
++ gpio = of_get_gpio_flags(cnp, i, &of_flags);
++ if (!gpio_is_valid(gpio))
++ return gpio;
++
++ if (of_flags == OF_GPIO_ACTIVE_LOW)
++ flags |= GPIOF_ACTIVE_LOW;
++
++ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
++ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++ else
++ flags |= GPIOF_IN;
++
++ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
++ continue;
++
++ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
++ gpio_export_with_name(gpio, dmc, name);
++ nb++;
++ }
++ }
++
++ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
++
++ return 0;
++}
++
++static struct platform_driver gpio_export_driver = {
++ .driver = {
++ .name = "gpio-export",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(gpio_export_ids),
++ },
++ .probe = of_gpio_export_probe,
++};
++
++module_platform_driver(gpio_export_driver);
+--- a/drivers/gpio/gpiolib-sysfs.c
++++ b/drivers/gpio/gpiolib-sysfs.c
+@@ -571,7 +571,7 @@ static struct class gpio_class = {
+ *
+ * Returns zero on success, else an error.
+ */
+-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
+ {
+ struct gpio_chip *chip;
+ struct gpio_device *gdev;
+@@ -633,6 +633,8 @@ int gpiod_export(struct gpio_desc *desc,
+ offset = gpio_chip_hwgpio(desc);
+ if (chip->names && chip->names[offset])
+ ioname = chip->names[offset];
++ if (name)
++ ioname = name;
+
+ dev = device_create_with_groups(&gpio_class, &gdev->dev,
+ MKDEV(0, 0), data, gpio_groups,
+@@ -654,6 +656,12 @@ err_unlock:
+ gpiod_dbg(desc, "%s: status %d\n", __func__, status);
+ return status;
+ }
++EXPORT_SYMBOL_GPL(__gpiod_export);
++
++int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++{
++ return __gpiod_export(desc, direction_may_change, NULL);
++}
+ EXPORT_SYMBOL_GPL(gpiod_export);
+
+ static int match_export(struct device *dev, const void *desc)
+--- a/include/asm-generic/gpio.h
++++ b/include/asm-generic/gpio.h
+@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g
+ return gpiod_export(gpio_to_desc(gpio), direction_may_change);
+ }
+
++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
++static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
++{
++ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
++}
++
+ static inline int gpio_export_link(struct device *dev, const char *name,
+ unsigned gpio)
+ {
+--- a/include/linux/gpio/consumer.h
++++ b/include/linux/gpio/consumer.h
+@@ -668,6 +668,7 @@ static inline void devm_acpi_dev_remove_
+
+ #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
+
++int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
+ int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
+ int gpiod_export_link(struct device *dev, const char *name,
+ struct gpio_desc *desc);
+@@ -675,6 +676,13 @@ void gpiod_unexport(struct gpio_desc *de
+
+ #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
+
++static inline int _gpiod_export(struct gpio_desc *desc,
++ bool direction_may_change,
++ const char *name)
++{
++ return -ENOSYS;
++}
++
+ static inline int gpiod_export(struct gpio_desc *desc,
+ bool direction_may_change)
+ {
--- /dev/null
+From 77d9b11ae7269dcf376c3b9493209f712524e986 Mon Sep 17 00:00:00 2001
+Date: Wed, 22 Jan 2020 12:56:35 +0100
+Subject: [PATCH] arm: dts: IPQ4019: add SDHCI VQMMC LDO node
+
+Since we now have driver for the SDHCI VQMMC LDO needed
+for I/0 voltage levels lets introduce the necessary node for it.
+
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -209,6 +209,16 @@
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
++ vqmmc: regulator@1948000 {
++ compatible = "qcom,vqmmc-ipq4019-regulator";
++ reg = <0x01948000 0x4>;
++ regulator-name = "vqmmc";
++ regulator-min-microvolt = <1500000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-always-on;
++ status = "disabled";
++ };
++
+ sdhci: sdhci@7824900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x7824900 0x11c>, <0x7824000 0x800>;
--- /dev/null
+From 193856b5fe11c50a0b6ff22457dd674c1a45fec6 Mon Sep 17 00:00:00 2001
+Date: Wed, 9 Sep 2020 18:31:03 +0200
+Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
+
+Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
+
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -615,5 +615,79 @@
+ reg = <4>;
+ };
+ };
++
++ usb3_ss_phy: ssphy@9a000 {
++ compatible = "qcom,usb-ss-ipq4019-phy";
++ #phy-cells = <0>;
++ reg = <0x9a000 0x800>;
++ reg-names = "phy_base";
++ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
++ reset-names = "por_rst";
++ status = "disabled";
++ };
++
++ usb3_hs_phy: hsphy@a6000 {
++ compatible = "qcom,usb-hs-ipq4019-phy";
++ #phy-cells = <0>;
++ reg = <0xa6000 0x40>;
++ reg-names = "phy_base";
++ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
++ reset-names = "por_rst", "srif_rst";
++ status = "disabled";
++ };
++
++ usb3: usb3@8af8800 {
++ compatible = "qcom,dwc3";
++ reg = <0x8af8800 0x100>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ clocks = <&gcc GCC_USB3_MASTER_CLK>,
++ <&gcc GCC_USB3_SLEEP_CLK>,
++ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
++ clock-names = "master", "sleep", "mock_utmi";
++ ranges;
++ status = "disabled";
++
++ dwc3@8a00000 {
++ compatible = "snps,dwc3";
++ reg = <0x8a00000 0xf8000>;
++ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
++ phy-names = "usb2-phy", "usb3-phy";
++ dr_mode = "host";
++ };
++ };
++
++ usb2_hs_phy: hsphy@a8000 {
++ compatible = "qcom,usb-hs-ipq4019-phy";
++ #phy-cells = <0>;
++ reg = <0xa8000 0x40>;
++ reg-names = "phy_base";
++ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
++ reset-names = "por_rst", "srif_rst";
++ status = "disabled";
++ };
++
++ usb2: usb2@60f8800 {
++ compatible = "qcom,dwc3";
++ reg = <0x60f8800 0x100>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ clocks = <&gcc GCC_USB2_MASTER_CLK>,
++ <&gcc GCC_USB2_SLEEP_CLK>,
++ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
++ clock-names = "master", "sleep", "mock_utmi";
++ ranges;
++ status = "disabled";
++
++ dwc3@6000000 {
++ compatible = "snps,dwc3";
++ reg = <0x6000000 0xf8000>;
++ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb2_hs_phy>;
++ phy-names = "usb2-phy";
++ dr_mode = "host";
++ };
++ };
+ };
+ };
--- /dev/null
+From caa3ee6b094ee18021943504c938919fcac325ec Mon Sep 17 00:00:00 2001
+Date: Wed, 9 Sep 2020 20:40:33 +0200
+Subject: [PATCH] arm: dts: qcom: ipq4019: add more labels
+
+Lets add labels to more commonly used nodes for easier modification in board DTS files.
+
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -190,7 +190,7 @@
+ reg = <0x1800000 0x60000>;
+ };
+
+- rng@22000 {
++ prng: rng@22000 {
+ compatible = "qcom,prng";
+ reg = <0x22000 0x140>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+@@ -310,7 +310,7 @@
+ status = "disabled";
+ };
+
+- crypto@8e3a000 {
++ crypto: crypto@8e3a000 {
+ compatible = "qcom,crypto-v5.1";
+ reg = <0x08e3a000 0x6000>;
+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
+@@ -396,7 +396,7 @@
+ dma-names = "rx", "tx";
+ };
+
+- watchdog@b017000 {
++ watchdog: watchdog@b017000 {
+ compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
+ reg = <0xb017000 0x40>;
+ clocks = <&sleep_clk>;
--- /dev/null
+From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
+Date: Sun, 11 Mar 2018 14:41:31 +0100
+Subject: [PATCH 2/2] clk: fix apss cpu overclocking
+
+There's an interaction issue between the clk changes:"
+clk: qcom: ipq4019: Add the apss cpu pll divider clock node
+clk: qcom: ipq4019: remove fixed clocks and add pll clocks
+" and the cpufreq-dt.
+
+cpufreq-dt is now spamming the kernel-log with the following:
+
+[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
+for freq 761142857 (-34)
+
+This only happens on certain devices like the Compex WPJ428
+and AVM FritzBox!4040. However, other devices like the Asus
+RT-AC58U and Meraki MR33 work just fine.
+
+The issue stem from the fact that all higher CPU-Clocks
+are achieved by switching the clock-parent to the P_DDRPLLAPSS
+(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
+as part of the DDR calibration.
+
+For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
+at round 533 MHz (ddrpllsdcc = 190285714 Hz).
+
+whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
+clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
+
+This patch attempts to fix the issue by modifying
+clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
+to use a new qcom_find_freq_close() function, which returns the closest
+matching frequency, instead of the next higher. This way, the SoC in
+the FB4040 (with its max clock speed of 710.4 MHz) will no longer
+try to overclock to 761 MHz.
+
+Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
+---
+ drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
+ 1 file changed, 31 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq4019.c
++++ b/drivers/clk/qcom/gcc-ipq4019.c
+@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
+ .reg = 0x2f020,
+ };
+
++
++const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
++ unsigned long rate)
++{
++ const struct freq_tbl *last = NULL;
++
++ for ( ; f->freq; f++) {
++ if (rate == f->freq)
++ return f;
++
++ if (f->freq > rate) {
++ if (!last ||
++ (f->freq - rate) < (rate - last->freq))
++ return f;
++ else
++ return last;
++ }
++ last = f;
++ }
++
++ return last;
++}
++
+ /*
+ * Round rate function for APSS CPU PLL Clock divider.
+ * It looks up the frequency table and returns the next higher frequency
+@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
+ struct clk_hw *p_hw;
+ const struct freq_tbl *f;
+
+- f = qcom_find_freq(pll->freq_tbl, rate);
++ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return -EINVAL;
+
+@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
+ u32 mask;
+ int ret;
+
+- f = qcom_find_freq(pll->freq_tbl, rate);
++ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return -EINVAL;
+
+@@ -1305,6 +1328,7 @@ static unsigned long
+ clk_cpu_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+ {
++ const struct freq_tbl *f;
+ struct clk_fepll *pll = to_clk_fepll(hw);
+ u32 cdiv, pre_div;
+ u64 rate;
+@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
+ rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
+ do_div(rate, pre_div);
+
+- return rate;
++ f = qcom_find_freq_close(pll->freq_tbl, rate);
++ if (!f)
++ return rate;
++
++ return f->freq;
+ };
+
+ static const struct clk_ops clk_regmap_cpu_div_ops = {
--- /dev/null
+From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001
+Date: Tue, 28 Mar 2017 22:35:33 +0530
+Subject: [PATCH] clk: qcom: ipq4019: add ess reset
+
+Added the ESS reset in IPQ4019 GCC.
+
+---
+ drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++
+ include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++
+ 2 files changed, 22 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq4019.c
++++ b/drivers/clk/qcom/gcc-ipq4019.c
+@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i
+ [GCC_TCSR_BCR] = {0x22000, 0},
+ [GCC_MPM_BCR] = {0x24000, 0},
+ [GCC_SPDM_BCR] = {0x25000, 0},
++ [ESS_MAC1_ARES] = {0x1200C, 0},
++ [ESS_MAC2_ARES] = {0x1200C, 1},
++ [ESS_MAC3_ARES] = {0x1200C, 2},
++ [ESS_MAC4_ARES] = {0x1200C, 3},
++ [ESS_MAC5_ARES] = {0x1200C, 4},
++ [ESS_PSGMII_ARES] = {0x1200C, 5},
++ [ESS_MAC1_CLK_DIS] = {0x1200C, 8},
++ [ESS_MAC2_CLK_DIS] = {0x1200C, 9},
++ [ESS_MAC3_CLK_DIS] = {0x1200C, 10},
++ [ESS_MAC4_CLK_DIS] = {0x1200C, 11},
++ [ESS_MAC5_CLK_DIS] = {0x1200C, 12},
+ };
+
+ static const struct regmap_config gcc_ipq4019_regmap_config = {
+--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
++++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+@@ -165,5 +165,16 @@
+ #define GCC_QDSS_BCR 69
+ #define GCC_MPM_BCR 70
+ #define GCC_SPDM_BCR 71
++#define ESS_MAC1_ARES 72
++#define ESS_MAC2_ARES 73
++#define ESS_MAC3_ARES 74
++#define ESS_MAC4_ARES 75
++#define ESS_MAC5_ARES 76
++#define ESS_PSGMII_ARES 77
++#define ESS_MAC1_CLK_DIS 78
++#define ESS_MAC2_CLK_DIS 79
++#define ESS_MAC3_CLK_DIS 80
++#define ESS_MAC4_CLK_DIS 81
++#define ESS_MAC5_CLK_DIS 82
+
+ #endif
--- /dev/null
+From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
+Date: Fri, 30 Oct 2020 13:36:31 +0100
+Subject: [PATCH] arm: compressed: add appended DTB section
+
+This adds a appended_dtb section to the ARM decompressor
+linker script.
+
+This allows using the existing ARM zImage appended DTB support for
+appending a DTB to the raw ELF kernel.
+
+Its size is set to 1MB max to match the zImage appended DTB size limit.
+
+To use it to pass the DTB to the kernel, objcopy is used:
+
+objcopy --set-section-flags=.appended_dtb=alloc,contents \
+ --update-section=.appended_dtb=<target>.dtb vmlinux
+
+This is based off the following patch:
+https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
+
+---
+ arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/compressed/vmlinux.lds.S
++++ b/arch/arm/boot/compressed/vmlinux.lds.S
+@@ -93,6 +93,13 @@ SECTIONS
+
+ _edata = .;
+
++ .appended_dtb : {
++ /* leave space for appended DTB */
++ . += 0x100000;
++ }
++
++ _edata_dtb = .;
++
+ /*
+ * The image_end section appears after any additional loadable sections
+ * that the linker may decide to insert in the binary image. Having
+@@ -132,4 +139,4 @@ SECTIONS
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ }
+-ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
++ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");
--- /dev/null
+From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
+Date: Fri, 23 Oct 2020 19:42:36 +1000
+Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
+
+For IPQ40XX systems where the SoC watchdog is activated before linux,
+the watchdog timer may be too small for linux to finish uncompress,
+boot, and watchdog management start.
+If the watchdog is enabled, set the timeout for it to 30 seconds.
+The functionality and offsets were copied from:
+drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
+The watchdog memory address was taken from:
+arch/arm/boot/dts/qcom-ipq4019.dtsi
+
+This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
+RouterBoot bootloader.
+
+---
+ arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -599,6 +599,41 @@ not_relocated: mov r0, #0
+ bic r4, r4, #1
+ blne cache_on
+
++/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
++ * if it is enabled, so that there is time for kernel
++ * to decompress, boot, and take over the watchdog.
++ * data and functionality from drivers/watchdog/qcom-wdt.c
++ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
++ */
++#ifdef CONFIG_ARCH_IPQ40XX
++watchdog_set:
++ /* offsets:
++ * 0x04 reset (=1 resets countdown)
++ * 0x08 enable (=0 disables)
++ * 0x0c status (=1 when SoC was reset by watchdog)
++ * 0x10 bark (=timeout warning in ticks)
++ * 0x14 bite (=timeout reset in ticks)
++ * clock rate is 1<<15 hertz
++ */
++ .equ watchdog, 0x0b017000 @Store watchdog base address
++ movw r0, #:lower16:watchdog
++ movt r0, #:upper16:watchdog
++ ldr r1, [r0, #0x08] @Get enabled?
++ cmp r1, #1 @If not enabled, do not change
++ bne watchdog_finished
++ mov r1, #0
++ str r1, [r0, #0x08] @Disable the watchdog
++ mov r1, #1
++ str r1, [r0, #0x04] @Pet the watchdog
++ mov r1, #30 @30 seconds timeout
++ lsl r1, r1, #15 @converted to ticks
++ str r1, [r0, #0x10] @Set the bark timeout
++ str r1, [r0, #0x14] @Set the bite timeout
++ mov r1, #1
++ str r1, [r0, #0x08] @Enable the watchdog
++watchdog_finished:
++#endif /* CONFIG_ARCH_IPQ40XX */
++
+ /*
+ * The C runtime environment should now be setup sufficiently.
+ * Set up some pointers, and start decompressing.
--- /dev/null
+From 0e28623a11f3916c1fe5b7e789c7ab8ca932a929 Mon Sep 17 00:00:00 2001
+Date: Wed, 22 Jan 2020 13:02:13 +0100
+Subject: [PATCH] mmc: sdhci: sdhci-msm: use sdhci_set_clock instead of
+ sdhci_msm_set_clock
+
+When using sdhci_msm_set_clock clock setting will fail, so lets
+use the generic sdhci_set_clock.
+
+---
+ drivers/mmc/host/sdhci-msm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mmc/host/sdhci-msm.c
++++ b/drivers/mmc/host/sdhci-msm.c
+@@ -2174,7 +2174,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
+
+ static const struct sdhci_ops sdhci_msm_ops = {
+ .reset = sdhci_msm_reset,
+- .set_clock = sdhci_msm_set_clock,
++ .set_clock = sdhci_set_clock,
+ .get_min_clock = sdhci_msm_get_min_clock,
+ .get_max_clock = sdhci_msm_get_max_clock,
+ .set_bus_width = sdhci_set_bus_width,
--- /dev/null
+From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
+Date: Sun, 20 Nov 2016 02:20:54 +0100
+Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
+
+This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
+nodes which are needed for the ar40xx.c driver to initialize the
+switch.
+
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -616,6 +616,29 @@
+ };
+ };
+
++ ess-switch@c000000 {
++ compatible = "qcom,ess-switch";
++ reg = <0xc000000 0x80000>;
++ switch_access_mode = "local bus";
++ resets = <&gcc ESS_RESET>;
++ reset-names = "ess_rst";
++ clocks = <&gcc GCC_ESS_CLK>;
++ clock-names = "ess_clk";
++ switch_cpu_bmp = <0x1>;
++ switch_lan_bmp = <0x1e>;
++ switch_wan_bmp = <0x20>;
++ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
++ switch_initvlas = <0x7c 0x54>;
++ status = "disabled";
++ };
++
++ ess-psgmii@98000 {
++ compatible = "qcom,ess-psgmii";
++ reg = <0x98000 0x800>;
++ psgmii_access_mode = "local bus";
++ status = "disabled";
++ };
++
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qcom,usb-ss-ipq4019-phy";
+ #phy-cells = <0>;
--- /dev/null
+From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
+Date: Wed, 20 Jul 2016 15:02:01 +0530
+Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
+ netdev_ops
+
+Add callback support to get default vlan tag and register
+receive flow steering filter.
+
+Used by IPQ4019 ess-edma driver.
+
+BUG=chrome-os-partner:33096
+TEST=none
+
+Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
+Reviewed-on: https://chromium-review.googlesource.com/362203
+---
+ include/linux/netdevice.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -776,6 +776,16 @@ struct xps_map {
+ #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
+ - sizeof(struct xps_map)) / sizeof(u16))
+
++#ifdef CONFIG_RFS_ACCEL
++typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
++ __be32 src,
++ __be32 dst,
++ __be16 sport,
++ __be16 dport,
++ u8 proto,
++ u16 rxq_index,
++ u32 action);
++#endif
+ /*
+ * This structure holds all XPS maps for device. Maps are indexed by CPU.
+ */
+@@ -1379,6 +1389,9 @@ struct net_device_ops {
+ const struct sk_buff *skb,
+ u16 rxq_index,
+ u32 flow_id);
++ int (*ndo_register_rfs_filter)(struct net_device *dev,
++ set_rfs_filter_callback_t set_filter);
++ int (*ndo_get_default_vlan_tag)(struct net_device *net);
+ #endif
+ int (*ndo_add_slave)(struct net_device *dev,
+ struct net_device *slave_dev,
--- /dev/null
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -388,6 +388,13 @@ config XILINX_GMII2RGMII
+ the Reduced Gigabit Media Independent Interface(RGMII) between
+ Ethernet physical media devices and the Gigabit Ethernet controller.
+
++config AR40XX_PHY
++ tristate "Driver for Qualcomm Atheros IPQ40XX switches"
++ depends on HAS_IOMEM && OF && OF_MDIO
++ select SWCONFIG
++ help
++ This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
++
+ endif # PHYLIB
+
+ config MICREL_KS8995MA
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -50,6 +50,7 @@ ifdef CONFIG_HWMON
+ aquantia-objs += aquantia_hwmon.o
+ endif
+ obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
++obj-$(CONFIG_AR40XX_PHY) += ar40xx.o
+ obj-$(CONFIG_AT803X_PHY) += at803x.o
+ obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
+ obj-$(CONFIG_BCM54140_PHY) += bcm54140.o
--- /dev/null
+From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001
+Date: Thu, 1 Oct 2020 15:05:35 +0200
+Subject: [PATCH] dt-bindings: net: add QCA807x PHY
+
+Add DT bindings for Qualcomm QCA807x PHY series.
+
+---
+ include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+ create mode 100644 include/dt-bindings/net/qcom-qca807x.h
+
+--- /dev/null
++++ b/include/dt-bindings/net/qcom-qca807x.h
+@@ -0,0 +1,45 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * Device Tree constants for the Qualcomm QCA807X PHYs
++ */
++
++#ifndef _DT_BINDINGS_QCOM_QCA807X_H
++#define _DT_BINDINGS_QCOM_QCA807X_H
++
++#define PSGMII_QSGMII_TX_DRIVER_140MV 0
++#define PSGMII_QSGMII_TX_DRIVER_160MV 1
++#define PSGMII_QSGMII_TX_DRIVER_180MV 2
++#define PSGMII_QSGMII_TX_DRIVER_200MV 3
++#define PSGMII_QSGMII_TX_DRIVER_220MV 4
++#define PSGMII_QSGMII_TX_DRIVER_240MV 5
++#define PSGMII_QSGMII_TX_DRIVER_260MV 6
++#define PSGMII_QSGMII_TX_DRIVER_280MV 7
++#define PSGMII_QSGMII_TX_DRIVER_300MV 8
++#define PSGMII_QSGMII_TX_DRIVER_320MV 9
++#define PSGMII_QSGMII_TX_DRIVER_400MV 10
++#define PSGMII_QSGMII_TX_DRIVER_500MV 11
++/* Default value */
++#define PSGMII_QSGMII_TX_DRIVER_600MV 12
++
++/* Full amplitude, full bias current */
++#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0
++/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */
++#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1
++/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */
++#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2
++/* Both amplitude and bias current follow DSP */
++#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3
++/* Full amplitude, half bias current */
++#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4
++/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,
++ * otherwise half bias current
++ */
++#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5
++/* Full amplitude; same bias current setting with “010” and “011”,
++ * but half more bias is reduced when cable <10m
++ */
++#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6
++/* Amplitude follow DSP; same bias current setting with “110”, default value */
++#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7
++
++#endif
--- /dev/null
+From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001
+Date: Wed, 7 Oct 2020 17:38:48 +0200
+Subject: [PATCH] net: phy: Add Qualcom QCA807x driver
+
+This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
+
+They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
+
+They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.
+
+Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.
+
+Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.
+But some vendors used these to driver generic LED-s controlled by userspace,
+so lets enable registering each PHY as GPIO controller and add driver for it.
+
+These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.
+
+---
+ drivers/net/phy/Kconfig | 6 ++++++
+ drivers/net/phy/Makefile | 1 +
+ 2 files changed, 7 insertions(+)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -537,6 +537,12 @@ config NXP_TJA11XX_PHY
+ ---help---
+ Currently supports the NXP TJA1100 and TJA1101 PHY.
+
++config QCA807X_PHY
++ tristate "Qualcomm QCA807X PHYs"
++ depends on OF_MDIO
++ help
++ Currently supports the QCA8072 and QCA8075 models.
++
+ config QSEMI_PHY
+ tristate "Quality Semiconductor PHYs"
+ ---help---
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -103,6 +103,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc.o
+ obj-$(CONFIG_NATIONAL_PHY) += national.o
+ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
+ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
++obj-$(CONFIG_QCA807X_PHY) += qca807x.o
+ obj-$(CONFIG_REALTEK_PHY) += realtek.o
+ obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
+ obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
--- /dev/null
+From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001
+Date: Fri, 2 Oct 2020 10:43:26 +0200
+Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
+
+This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
+
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/net/qcom-qca807x.h>
+
+ / {
+ #address-cells = <1>;
+@@ -597,22 +598,39 @@
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy3: ethernet-phy@3 {
+ reg = <3>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy4: ethernet-phy@4 {
+ reg = <4>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
++ };
++
++ psgmiiphy: psgmii-phy@5 {
++ reg = <5>;
++
++ qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
++ qcom,psgmii-az;
+ };
+ };
+
--- /dev/null
+From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
+Date: Thu, 19 Jan 2017 02:01:31 +0100
+Subject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver
+
+---
+ drivers/net/ethernet/qualcomm/Kconfig | 9 +++++++++
+ drivers/net/ethernet/qualcomm/Makefile | 1 +
+ 2 files changed, 10 insertions(+)
+
+--- a/drivers/net/ethernet/qualcomm/Kconfig
++++ b/drivers/net/ethernet/qualcomm/Kconfig
+@@ -62,4 +62,14 @@ config QCOM_EMAC
+
+ source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
+
++config ESSEDMA
++ tristate "Qualcomm Atheros ESS Edma support"
++ depends on OF_MDIO
++ help
++ This driver supports ethernet edma adapter.
++ Say Y to build this driver.
++
++ To compile this driver as a module, choose M here. The module
++ will be called essedma.ko.
++
+ endif # NET_VENDOR_QUALCOMM
+--- a/drivers/net/ethernet/qualcomm/Makefile
++++ b/drivers/net/ethernet/qualcomm/Makefile
+@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
+ qcauart-objs := qca_uart.o
+
+ obj-y += emac/
++obj-$(CONFIG_ESSEDMA) += essedma/
+
+ obj-$(CONFIG_RMNET) += rmnet/
--- /dev/null
+From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
+Date: Sun, 20 Nov 2016 01:01:10 +0100
+Subject: [PATCH] dts: ipq4019: add ethernet essedma node
+
+This patch adds the device-tree node for the ethernet
+interfaces.
+
+Note: The driver isn't anywhere close to be upstream,
+so the info might change.
+
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -39,6 +39,8 @@
+ spi1 = &blsp1_spi2;
+ i2c0 = &blsp1_i2c3;
+ i2c1 = &blsp1_i2c4;
++ ethernet0 = &gmac0;
++ ethernet1 = &gmac1;
+ };
+
+ cpus {
+@@ -657,6 +659,64 @@
+ status = "disabled";
+ };
+
++ edma@c080000 {
++ compatible = "qcom,ess-edma";
++ reg = <0xc080000 0x8000>;
++ qcom,page-mode = <0>;
++ qcom,rx_head_buf_size = <1540>;
++ qcom,mdio_supported;
++ qcom,poll_required = <1>;
++ qcom,num_gmac = <2>;
++ interrupts = <0 65 IRQ_TYPE_EDGE_RISING
++ 0 66 IRQ_TYPE_EDGE_RISING
++ 0 67 IRQ_TYPE_EDGE_RISING
++ 0 68 IRQ_TYPE_EDGE_RISING
++ 0 69 IRQ_TYPE_EDGE_RISING
++ 0 70 IRQ_TYPE_EDGE_RISING
++ 0 71 IRQ_TYPE_EDGE_RISING
++ 0 72 IRQ_TYPE_EDGE_RISING
++ 0 73 IRQ_TYPE_EDGE_RISING
++ 0 74 IRQ_TYPE_EDGE_RISING
++ 0 75 IRQ_TYPE_EDGE_RISING
++ 0 76 IRQ_TYPE_EDGE_RISING
++ 0 77 IRQ_TYPE_EDGE_RISING
++ 0 78 IRQ_TYPE_EDGE_RISING
++ 0 79 IRQ_TYPE_EDGE_RISING
++ 0 80 IRQ_TYPE_EDGE_RISING
++ 0 240 IRQ_TYPE_EDGE_RISING
++ 0 241 IRQ_TYPE_EDGE_RISING
++ 0 242 IRQ_TYPE_EDGE_RISING
++ 0 243 IRQ_TYPE_EDGE_RISING
++ 0 244 IRQ_TYPE_EDGE_RISING
++ 0 245 IRQ_TYPE_EDGE_RISING
++ 0 246 IRQ_TYPE_EDGE_RISING
++ 0 247 IRQ_TYPE_EDGE_RISING
++ 0 248 IRQ_TYPE_EDGE_RISING
++ 0 249 IRQ_TYPE_EDGE_RISING
++ 0 250 IRQ_TYPE_EDGE_RISING
++ 0 251 IRQ_TYPE_EDGE_RISING
++ 0 252 IRQ_TYPE_EDGE_RISING
++ 0 253 IRQ_TYPE_EDGE_RISING
++ 0 254 IRQ_TYPE_EDGE_RISING
++ 0 255 IRQ_TYPE_EDGE_RISING>;
++
++ status = "disabled";
++
++ gmac0: gmac0 {
++ local-mac-address = [00 00 00 00 00 00];
++ vlan_tag = <1 0x1f>;
++ };
++
++ gmac1: gmac1 {
++ local-mac-address = [00 00 00 00 00 00];
++ qcom,phy_mdio_addr = <4>;
++ qcom,poll_required = <1>;
++ qcom,forced_speed = <1000>;
++ qcom,forced_duplex = <1>;
++ vlan_tag = <2 0x20>;
++ };
++ };
++
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qcom,usb-ss-ipq4019-phy";
+ #phy-cells = <0>;
--- /dev/null
+Subject: SoC: add qualcomm syscon
+--- a/drivers/soc/qcom/Makefile
++++ b/drivers/soc/qcom/Makefile
+@@ -20,6 +20,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
+ obj-$(CONFIG_QCOM_SMSM) += smsm.o
+ obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
+ obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
++obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
+ obj-$(CONFIG_QCOM_APR) += apr.o
+ obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o
+ obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o
+--- a/drivers/soc/qcom/Kconfig
++++ b/drivers/soc/qcom/Kconfig
+@@ -183,6 +183,13 @@ config QCOM_SOCINFO
+ Say yes here to support the Qualcomm socinfo driver, providing
+ information about the SoC to user space.
+
++config QCOM_TCSR
++ tristate "QCOM Top Control and Status Registers"
++ depends on ARCH_QCOM
++ help
++ Say y here to enable TCSR support. The TCSR provides control
++ functions for various peripherals.
++
+ config QCOM_WCNSS_CTRL
+ tristate "Qualcomm WCNSS control driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+--- /dev/null
++++ b/drivers/soc/qcom/qcom_tcsr.c
+@@ -0,0 +1,98 @@
++/*
++ * Copyright (c) 2014, The Linux foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License rev 2 and
++ * only rev 2 as published by the free Software foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++
++#define TCSR_USB_PORT_SEL 0xb0
++#define TCSR_USB_HSPHY_CONFIG 0xC
++
++#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
++#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
++
++#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
++#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
++#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
++
++static int tcsr_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ const struct device_node *node = pdev->dev.of_node;
++ void __iomem *base;
++ u32 val;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
++ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
++ writel(val, base + TCSR_USB_PORT_SEL);
++ }
++
++ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
++ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
++ writel(val, base + TCSR_USB_HSPHY_CONFIG);
++ }
++
++ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
++ u32 tmp = 0;
++ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
++ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
++ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
++ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
++ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
++ }
++
++ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
++ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
++ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
++ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
++ }
++
++ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
++ dev_info(&pdev->dev,
++ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
++ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
++ }
++
++ return 0;
++}
++
++static const struct of_device_id tcsr_dt_match[] = {
++ { .compatible = "qcom,tcsr", },
++ { },
++};
++
++MODULE_DEVICE_TABLE(of, tcsr_dt_match);
++
++static struct platform_driver tcsr_driver = {
++ .driver = {
++ .name = "tcsr",
++ .owner = THIS_MODULE,
++ .of_match_table = tcsr_dt_match,
++ },
++ .probe = tcsr_probe,
++};
++
++module_platform_driver(tcsr_driver);
++
++MODULE_DESCRIPTION("QCOM TCSR driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/include/dt-bindings/soc/qcom,tcsr.h
+@@ -0,0 +1,48 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++#ifndef __DT_BINDINGS_QCOM_TCSR_H
++#define __DT_BINDINGS_QCOM_TCSR_H
++
++#define TCSR_USB_SELECT_USB3_P0 0x1
++#define TCSR_USB_SELECT_USB3_P1 0x2
++#define TCSR_USB_SELECT_USB3_DUAL 0x3
++
++/* IPQ40xx HS PHY Mode Select */
++#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
++#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
++
++/* IPQ40xx ess interface mode select */
++#define TCSR_ESS_PSGMII 0
++#define TCSR_ESS_PSGMII_RGMII5 1
++#define TCSR_ESS_PSGMII_RMII0 2
++#define TCSR_ESS_PSGMII_RMII1 4
++#define TCSR_ESS_PSGMII_RMII0_RMII1 6
++#define TCSR_ESS_PSGMII_RGMII4 9
++
++/*
++ * IPQ40xx WiFi Global Config
++ * Bit 30:AXID_EN
++ * Enable AXI master bus Axid translating to confirm all txn submitted by order
++ * Bit 24: Use locally generated socslv_wxi_bvalid
++ * 1: use locally generate socslv_wxi_bvalid for performance.
++ * 0: use SNOC socslv_wxi_bvalid.
++ */
++#define TCSR_WIFI_GLB_CFG 0x41000000
++
++/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
++#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
++
++/* TCSR A/B REG */
++#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
++#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
++
++#endif
--- /dev/null
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -15,6 +15,7 @@
+ */
+
+ #include "qcom-ipq4019.dtsi"
++#include <dt-bindings/soc/qcom,tcsr.h>
+
+ / {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+@@ -29,6 +30,32 @@
+ };
+
+ soc {
++ tcsr@194b000 {
++ /* select hostmode */
++ compatible = "qcom,tcsr";
++ reg = <0x194b000 0x100>;
++ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
++ status = "okay";
++ };
++
++ ess_tcsr@1953000 {
++ compatible = "qcom,tcsr";
++ reg = <0x1953000 0x1000>;
++ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
++ };
++
++ tcsr@1949000 {
++ compatible = "qcom,tcsr";
++ reg = <0x1949000 0x100>;
++ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
++ };
++
++ tcsr@1957000 {
++ compatible = "qcom,tcsr";
++ reg = <0x1957000 0x100>;
++ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
++ };
++
+ rng@22000 {
+ status = "ok";
+ };
+@@ -74,14 +101,6 @@
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 54 0>;
+-
+- mx25l25635e@0 {
+- #address-cells = <1>;
+- #size-cells = <1>;
+- reg = <0>;
+- compatible = "mx25l25635e";
+- spi-max-frequency = <24000000>;
+- };
+ };
+
+ serial@78af000 {
+@@ -109,5 +128,41 @@
+ wifi@a800000 {
+ status = "ok";
+ };
++
++ mdio@90000 {
++ status = "okay";
++ };
++
++ ess-switch@c000000 {
++ status = "okay";
++ };
++
++ ess-psgmii@98000 {
++ status = "okay";
++ };
++
++ edma@c080000 {
++ status = "okay";
++ };
++
++ usb3_ss_phy: ssphy@9a000 {
++ status = "okay";
++ };
++
++ usb3_hs_phy: hsphy@a6000 {
++ status = "okay";
++ };
++
++ usb3: usb3@8af8800 {
++ status = "okay";
++ };
++
++ usb2_hs_phy: hsphy@a8000 {
++ status = "okay";
++ };
++
++ usb2: usb2@60f8800 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+@@ -18,5 +18,73 @@
+
+ / {
+ model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
++ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1";
+
++ memory {
++ device_type = "memory";
++ reg = <0x80000000 0x10000000>;
++ };
++};
++
++&blsp1_spi1 {
++ mx25l25635f@0 {
++ compatible = "mx25l25635f", "jedec,spi-nor";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0>;
++ spi-max-frequency = <24000000>;
++
++ SBL1@0 {
++ label = "SBL1";
++ reg = <0x0 0x40000>;
++ read-only;
++ };
++ MIBIB@40000 {
++ label = "MIBIB";
++ reg = <0x40000 0x20000>;
++ read-only;
++ };
++ QSEE@60000 {
++ label = "QSEE";
++ reg = <0x60000 0x60000>;
++ read-only;
++ };
++ CDT@c0000 {
++ label = "CDT";
++ reg = <0xc0000 0x10000>;
++ read-only;
++ };
++ DDRPARAMS@d0000 {
++ label = "DDRPARAMS";
++ reg = <0xd0000 0x10000>;
++ read-only;
++ };
++ APPSBLENV@e0000 {
++ label = "APPSBLENV";
++ reg = <0xe0000 0x10000>;
++ read-only;
++ };
++ APPSBL@f0000 {
++ label = "APPSBL";
++ reg = <0xf0000 0x80000>;
++ read-only;
++ };
++ ART@170000 {
++ label = "ART";
++ reg = <0x170000 0x10000>;
++ read-only;
++ };
++ kernel@180000 {
++ label = "kernel";
++ reg = <0x180000 0x400000>;
++ };
++ rootfs@580000 {
++ label = "rootfs";
++ reg = <0x580000 0x1600000>;
++ };
++ firmware@180000 {
++ label = "firmware";
++ reg = <0x180000 0x1a00000>;
++ };
++ };
+ };
--- /dev/null
+From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001
+Date: Thu, 9 Mar 2017 11:03:18 +0100
+Subject: [PATCH] arm: boot: add dts files
+
+---
+ arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -837,11 +837,60 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+ qcom-apq8074-dragonboard.dtb \
+ qcom-apq8084-ifc6540.dtb \
+ qcom-apq8084-mtp.dtb \
++ qcom-ipq4018-a42.dtb \
++ qcom-ipq4018-ap120c-ac.dtb \
++ qcom-ipq4018-dap-2610.dtb \
++ qcom-ipq4018-cs-w3-wd1200g-eup.dtb \
++ qcom-ipq4018-magic-2-wifi-next.dtb \
++ qcom-ipq4018-ea6350v3.dtb \
++ qcom-ipq4018-eap1300.dtb \
++ qcom-ipq4018-ecw5211.dtb \
++ qcom-ipq4018-emd1.dtb \
++ qcom-ipq4018-emr3500.dtb \
++ qcom-ipq4018-ens620ext.dtb \
++ qcom-ipq4018-ex6100v2.dtb \
++ qcom-ipq4018-ex6150v2.dtb \
++ qcom-ipq4018-fritzbox-4040.dtb \
++ qcom-ipq4018-gl-ap1300.dtb \
++ qcom-ipq4018-jalapeno.dtb \
++ qcom-ipq4018-meshpoint-one.dtb \
++ qcom-ipq4018-hap-ac2.dtb \
++ qcom-ipq4018-sxtsq-5-ac.dtb \
++ qcom-ipq4018-nbg6617.dtb \
++ qcom-ipq4019-oap100.dtb \
++ qcom-ipq4018-pa1200.dtb \
++ qcom-ipq4018-rt-ac58u.dtb \
++ qcom-ipq4018-wre6606.dtb \
++ qcom-ipq4018-wrtq-329acn.dtb \
+ qcom-ipq4019-ap.dk01.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
+ qcom-ipq4019-ap.dk07.1-c1.dtb \
+ qcom-ipq4019-ap.dk07.1-c2.dtb \
++ qcom-ipq4019-a62.dtb \
++ qcom-ipq4019-cm520-79f.dtb \
++ qcom-ipq4019-ea8300.dtb \
++ qcom-ipq4019-eap2200.dtb \
++ qcom-ipq4019-fritzbox-7530.dtb \
++ qcom-ipq4019-fritzrepeater-1200.dtb \
++ qcom-ipq4019-fritzrepeater-3000.dtb \
++ qcom-ipq4019-map-ac2200.dtb \
++ qcom-ipq4019-mr8300.dtb \
++ qcom-ipq4019-e2600ac-c1.dtb \
++ qcom-ipq4019-e2600ac-c2.dtb \
++ qcom-ipq4019-habanero-dvk.dtb \
++ qcom-ipq4019-pa2200.dtb \
++ qcom-ipq4019-rtl30vw.dtb \
++ qcom-ipq4019-u4019-32m.dtb \
++ qcom-ipq4019-wpj419.dtb \
++ qcom-ipq4019-wtr-m2133hp.dtb \
++ qcom-ipq4028-wpj428.dtb \
++ qcom-ipq4029-ap-303.dtb \
++ qcom-ipq4029-ap-303h.dtb \
++ qcom-ipq4029-ap-365.dtb \
++ qcom-ipq4029-gl-b1300.dtb \
++ qcom-ipq4029-gl-s1300.dtb \
++ qcom-ipq4029-mr33.dtb \
+ qcom-ipq8064-ap148.dtb \
+ qcom-msm8660-surf.dtb \
+ qcom-msm8960-cdp.dtb \
--- /dev/null
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+@@ -17,53 +17,79 @@
+ stdout-path = "serial0:115200n8";
+ };
+
+- memory {
+- device_type = "memory";
+- reg = <0x80000000 0x10000000>; /* 256MB */
+- };
+-
+ soc {
++ rng@22000 {
++ status = "okay";
++ };
++
+ pinctrl@1000000 {
+ serial_0_pins: serial0-pinmux {
+- pins = "gpio16", "gpio17";
+- function = "blsp_uart0";
+- bias-disable;
++ mux {
++ pins = "gpio16", "gpio17";
++ function = "blsp_uart0";
++ bias-disable;
++ };
+ };
+
+ serial_1_pins: serial1-pinmux {
+- pins = "gpio8", "gpio9",
+- "gpio10", "gpio11";
+- function = "blsp_uart1";
+- bias-disable;
++ mux {
++ pins = "gpio8", "gpio9";
++ function = "blsp_uart1";
++ bias-disable;
++ };
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+- bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
++ };
++ pinconf {
++ pins = "gpio13", "gpio14", "gpio15";
++ drive-strength = <12>;
++ bias-disable;
++ };
++ pinconf_cs {
++ pins = "gpio12";
++ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+- pins = "gpio20", "gpio21";
+- function = "blsp_i2c0";
+- bias-disable;
++ pinmux {
++ function = "blsp_i2c0";
++ pins = "gpio10", "gpio11";
++ };
++ pinconf {
++ pins = "gpio10", "gpio11";
++ drive-strength = <16>;
++ bias-disable;
++ };
+ };
+
+ nand_pins: nand-pins {
+- pins = "gpio53", "gpio55", "gpio56",
+- "gpio57", "gpio58", "gpio59",
+- "gpio60", "gpio62", "gpio63",
+- "gpio64", "gpio65", "gpio66",
+- "gpio67", "gpio68", "gpio69";
+- function = "qpic";
++ pullups {
++ pins = "gpio52", "gpio53", "gpio58",
++ "gpio59";
++ function = "qpic";
++ bias-pull-up;
++ };
++
++ pulldowns {
++ pins = "gpio54", "gpio55", "gpio56",
++ "gpio57", "gpio60", "gpio61",
++ "gpio62", "gpio63", "gpio64",
++ "gpio65", "gpio66", "gpio67",
++ "gpio68", "gpio69";
++ function = "qpic";
++ bias-pull-down;
++ };
+ };
+ };
+
+@@ -89,11 +115,11 @@
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+- m25p80@0 {
++ mx25l25635e@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+- compatible = "n25q128a11";
++ compatible = "mx25l25635e";
+ spi-max-frequency = <24000000>;
+ };
+ };
+@@ -103,9 +129,48 @@
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
++ i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
++ pinctrl-0 = <&i2c_0_pins>;
++ pinctrl-names = "default";
++
++ status = "okay";
++ };
++
+ qpic-nand@79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ };
++
++ usb3_ss_phy: ssphy@9a000 {
++ status = "okay";
++ };
++
++ usb3_hs_phy: hsphy@a6000 {
++ status = "okay";
++ };
++
++ usb3: usb3@8af8800 {
++ status = "okay";
++ };
++
++ usb2_hs_phy: hsphy@a8000 {
++ status = "okay";
++ };
++
++ usb2: usb2@60f8800 {
++ status = "okay";
++ };
++
++ cryptobam: dma@8e04000 {
++ status = "okay";
++ };
++
++ crypto@8e3a000 {
++ status = "okay";
++ };
++
++ watchdog@b017000 {
++ status = "okay";
++ };
+ };
+ };
--- /dev/null
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1055,6 +1055,9 @@ int __init early_init_dt_scan_chosen(uns
+ p = of_get_flat_dt_prop(node, "bootargs", &l);
+ if (p != NULL && l > 0)
+ strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
++ p = of_get_flat_dt_prop(node, "bootargs-append", &l);
++ if (p != NULL && l > 0)
++ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
+
+ /*
+ * CONFIG_CMDLINE is meant to be a default in case nothing else
projects / openwrt / staging / blocktrron.git / commitdiff