x86/idt: Fix the X86_TRAP_BP gate

Andrei Vagin reported a CRIU regression and bisected it back to:

  90f6225fba0c ("x86/idt: Move IST stack based traps to table init")

This table init conversion loses the system-gate property of X86_TRAP_BP
and erroneously moves it from DPL3 to DPL0.

Fix it.

Reported-by: Andrei Vagin <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Cyrill Gorcunov <[email protected]>
Cc: [email protected]
Cc: tip-bot for Jacob Shin <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]

diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c
index 61b490c69250bcfe47c740364ea45c20888c90a4..6107ee1cb8d56762ab76b0e076b52c3f838b1698 100644 (file)
--- a/arch/x86/kernel/idt.c
+++ b/arch/x86/kernel/idt.c
@@ -44,6 +44,10 @@ struct idt_data {
 #define ISTG(_vector, _addr, _ist)                     \
        G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
 
+/* System interrupt gate with interrupt stack */
+#define SISTG(_vector, _addr, _ist)                    \
+       G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
+
 /* Task gate */
 #define TSKG(_vector, _gdt)                            \
        G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
@@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
 static const __initdata struct idt_data ist_idts[] = {
        ISTG(X86_TRAP_DB,       debug,          DEBUG_STACK),
        ISTG(X86_TRAP_NMI,      nmi,            NMI_STACK),
-       ISTG(X86_TRAP_BP,       int3,           DEBUG_STACK),
+       SISTG(X86_TRAP_BP,      int3,           DEBUG_STACK),
        ISTG(X86_TRAP_DF,       double_fault,   DOUBLEFAULT_STACK),
 #ifdef CONFIG_X86_MCE
        ISTG(X86_TRAP_MC,       &machine_check, MCE_STACK),