pvid = priv->ports[port].pvid;
/* Reset to default if removing the current PVID */
- if (vlan->vid == pvid) {
+ if (vlan->vid == pvid)
rtl83xx_vlan_set_pvid(priv, port, 0);
- }
+
/* Get port memberships of this vlan */
priv->r->vlan_tables_read(vlan->vid, &info);
if (id < 0 || id >= ds->num_lag_ids)
return false;
- if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
+ if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
return false;
- }
+
if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
return false;
rtpcs_930x_sds_set(ctrl, sds, mode);
/* Set the submode if needed. */
- if (phy_mode == PHY_INTERFACE_MODE_10G_QXGMII) {
+ if (phy_mode == PHY_INTERFACE_MODE_10G_QXGMII)
rtpcs_930x_sds_submode_set(ctrl, sds, submode);
- }
}
return;
}
- for (size_t i = 0; i < count; ++i) {
+ for (size_t i = 0; i < count; ++i)
rtpcs_sds_write(ctrl, sds, config[i].page, config[i].reg, config[i].data);
- }
if (mode == PHY_INTERFACE_MODE_10G_QXGMII) {
/* Default configuration */
pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x28, 0x7));
rtpcs_sds_write_bits(ctrl, sds, cmu_page, 0x7, 15, 15, 0);
pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x28, 0x7));
- if (chiptype) {
+ if (chiptype)
rtpcs_sds_write_bits(ctrl, sds, cmu_page, 0xd, 14, 14, 0);
- }
rtpcs_sds_write_bits(ctrl, evenSds, 0x20, 0x12, 3, 2, 0x3);
rtpcs_sds_write_bits(ctrl, evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
val = 0xa0000;
regmap_write(ctrl->map, RTL93XX_CHIP_INFO, val);
regmap_read(ctrl->map, RTL93XX_CHIP_INFO, &val);
+
if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
- {
rtpcs_sds_write(ctrl, sds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
- } else {
+ else
rtpcs_sds_write(ctrl, sds, 0x2E, 0x1, board_sds_tx[sds - 2]);
- }
+
val = 0;
regmap_write(ctrl->map, RTL93XX_CHIP_INFO, val);
}