armv7: Add workaround for USB erratum A-009798

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.

Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.

Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Suresh Gupta <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <[email protected]>

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index be30dd8442184083f306f34d1d3ff8e2ef5736e6..a9fc65ff11af822eeb7ec9d89dbf19f0070dda97 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -4,6 +4,7 @@ config ARCH_LS1021A
        select SYS_FSL_ERRATUM_A008407
        select SYS_FSL_ERRATUM_A009008
        select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009798
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_HAS_CCI400
@@ -64,6 +65,11 @@ config SYS_FSL_ERRATUM_A009008
        help
          Workaround for USB PHY erratum A009008
 
+config SYS_FSL_ERRATUM_A009798
+       bool
+       help
+         Workaround for USB PHY erratum A009798
+
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index eed06a3c7cee0c9fa8d62990273b78253dd87a81..4f94df79f83dff4edd4f067b707b4f7796325b92 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -71,6 +71,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+       clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
+                       SCFG_USB_SQRXTUNE_MASK << 23);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
 
 void s_init(void)
 {
@@ -161,6 +170,7 @@ int arch_soc_init(void)
 
        /* Erratum */
        erratum_a009008();
+       erratum_a009798();
 
        return 0;
 }

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 28c1a984182e46ec28374474c366f56aa8f842af..bc5125d83317a2bc89b9425a2408e694da204156 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,7 @@ struct ccsr_gur {
 #define SCFG_BASE                      0x01570000
 #define SCFG_USB3PRM1CR                        0x070
 #define SCFG_USB_TXVREFTUNE            0x9
+#define SCFG_USB_SQRXTUNE_MASK         0x7
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {