--- /dev/null
+From 4043b0c45f8555a079bdac69a19ed08695a47a7b Mon Sep 17 00:00:00 2001
+Date: Fri, 7 Nov 2025 00:57:04 +0100
+Subject: [PATCH 1/5] pinctrl: airoha: generalize pins/group/function/confs
+ handling
+
+In preparation for support of Airoha AN7583, generalize
+pins/group/function/confs handling and move them in match_data.
+Inner function will base the values on the pinctrl priv struct instead of
+relying on hardcoded struct.
+
+This permits to use different PIN data while keeping the same logic.
+
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 567 ++++++++++++----------
+ 1 file changed, 318 insertions(+), 249 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
++++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -30,20 +30,20 @@
+ #include "../pinconf.h"
+ #include "../pinmux.h"
+
+-#define PINCTRL_PIN_GROUP(id) \
+- PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins))
++#define PINCTRL_PIN_GROUP(id, table) \
++ PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
+
+-#define PINCTRL_FUNC_DESC(id) \
++#define PINCTRL_FUNC_DESC(id, table) \
+ { \
+ .desc = { \
+ .func = { \
+ .name = #id, \
+- .groups = id##_groups, \
+- .ngroups = ARRAY_SIZE(id##_groups), \
++ .groups = table##_groups, \
++ .ngroups = ARRAY_SIZE(table##_groups), \
+ } \
+ }, \
+- .groups = id##_func_group, \
+- .group_size = ARRAY_SIZE(id##_func_group), \
++ .groups = table##_func_group, \
++ .group_size = ARRAY_SIZE(table##_func_group), \
+ }
+
+ #define PINCTRL_CONF_DESC(p, offset, mask) \
+@@ -362,16 +362,46 @@ struct airoha_pinctrl_gpiochip {
+ u32 irq_type[AIROHA_NUM_PINS];
+ };
+
++struct airoha_pinctrl_confs_info {
++ const struct airoha_pinctrl_conf *confs;
++ unsigned int num_confs;
++};
++
++enum airoha_pinctrl_confs_type {
++ AIROHA_PINCTRL_CONFS_PULLUP,
++ AIROHA_PINCTRL_CONFS_PULLDOWN,
++ AIROHA_PINCTRL_CONFS_DRIVE_E2,
++ AIROHA_PINCTRL_CONFS_DRIVE_E4,
++ AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
++
++ AIROHA_PINCTRL_CONFS_MAX,
++};
++
+ struct airoha_pinctrl {
+ struct pinctrl_dev *ctrl;
+
++ struct pinctrl_desc desc;
++ const struct pingroup *grps;
++ const struct airoha_pinctrl_func *funcs;
++ const struct airoha_pinctrl_confs_info *confs_info;
++
+ struct regmap *chip_scu;
+ struct regmap *regmap;
+
+ struct airoha_pinctrl_gpiochip gpiochip;
+ };
+
+-static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
++struct airoha_pinctrl_match_data {
++ const struct pinctrl_pin_desc *pins;
++ const unsigned int num_pins;
++ const struct pingroup *grps;
++ const unsigned int num_grps;
++ const struct airoha_pinctrl_func *funcs;
++ const unsigned int num_funcs;
++ const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
++};
++
++static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+ PINCTRL_PIN(0, "uart1_txd"),
+ PINCTRL_PIN(1, "uart1_rxd"),
+ PINCTRL_PIN(2, "i2c_scl"),
+@@ -432,172 +462,172 @@ static struct pinctrl_pin_desc airoha_pi
+ PINCTRL_PIN(63, "pcie_reset2"),
+ };
+
+-static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+-static const int pon_tod_1pps_pins[] = { 46 };
+-static const int gsw_tod_1pps_pins[] = { 46 };
+-static const int sipo_pins[] = { 16, 17 };
+-static const int sipo_rclk_pins[] = { 16, 17, 43 };
+-static const int mdio_pins[] = { 14, 15 };
+-static const int uart2_pins[] = { 48, 55 };
+-static const int uart2_cts_rts_pins[] = { 46, 47 };
+-static const int hsuart_pins[] = { 28, 29 };
+-static const int hsuart_cts_rts_pins[] = { 26, 27 };
+-static const int uart4_pins[] = { 38, 39 };
+-static const int uart5_pins[] = { 18, 19 };
+-static const int i2c0_pins[] = { 2, 3 };
+-static const int i2c1_pins[] = { 14, 15 };
+-static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+-static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+-static const int i2s_pins[] = { 26, 27, 28, 29 };
+-static const int pcm1_pins[] = { 22, 23, 24, 25 };
+-static const int pcm2_pins[] = { 18, 19, 20, 21 };
+-static const int spi_quad_pins[] = { 32, 33 };
+-static const int spi_pins[] = { 4, 5, 6, 7 };
+-static const int spi_cs1_pins[] = { 34 };
+-static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+-static const int pcm_spi_int_pins[] = { 14 };
+-static const int pcm_spi_rst_pins[] = { 15 };
+-static const int pcm_spi_cs1_pins[] = { 43 };
+-static const int pcm_spi_cs2_pins[] = { 40 };
+-static const int pcm_spi_cs2_p128_pins[] = { 40 };
+-static const int pcm_spi_cs2_p156_pins[] = { 40 };
+-static const int pcm_spi_cs3_pins[] = { 41 };
+-static const int pcm_spi_cs4_pins[] = { 42 };
+-static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
+-static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
+-static const int gpio0_pins[] = { 13 };
+-static const int gpio1_pins[] = { 14 };
+-static const int gpio2_pins[] = { 15 };
+-static const int gpio3_pins[] = { 16 };
+-static const int gpio4_pins[] = { 17 };
+-static const int gpio5_pins[] = { 18 };
+-static const int gpio6_pins[] = { 19 };
+-static const int gpio7_pins[] = { 20 };
+-static const int gpio8_pins[] = { 21 };
+-static const int gpio9_pins[] = { 22 };
+-static const int gpio10_pins[] = { 23 };
+-static const int gpio11_pins[] = { 24 };
+-static const int gpio12_pins[] = { 25 };
+-static const int gpio13_pins[] = { 26 };
+-static const int gpio14_pins[] = { 27 };
+-static const int gpio15_pins[] = { 28 };
+-static const int gpio16_pins[] = { 29 };
+-static const int gpio17_pins[] = { 30 };
+-static const int gpio18_pins[] = { 31 };
+-static const int gpio19_pins[] = { 32 };
+-static const int gpio20_pins[] = { 33 };
+-static const int gpio21_pins[] = { 34 };
+-static const int gpio22_pins[] = { 35 };
+-static const int gpio23_pins[] = { 36 };
+-static const int gpio24_pins[] = { 37 };
+-static const int gpio25_pins[] = { 38 };
+-static const int gpio26_pins[] = { 39 };
+-static const int gpio27_pins[] = { 40 };
+-static const int gpio28_pins[] = { 41 };
+-static const int gpio29_pins[] = { 42 };
+-static const int gpio30_pins[] = { 43 };
+-static const int gpio31_pins[] = { 44 };
+-static const int gpio33_pins[] = { 46 };
+-static const int gpio34_pins[] = { 47 };
+-static const int gpio35_pins[] = { 48 };
+-static const int gpio36_pins[] = { 49 };
+-static const int gpio37_pins[] = { 50 };
+-static const int gpio38_pins[] = { 51 };
+-static const int gpio39_pins[] = { 52 };
+-static const int gpio40_pins[] = { 53 };
+-static const int gpio41_pins[] = { 54 };
+-static const int gpio42_pins[] = { 55 };
+-static const int gpio43_pins[] = { 56 };
+-static const int gpio44_pins[] = { 57 };
+-static const int gpio45_pins[] = { 58 };
+-static const int gpio46_pins[] = { 59 };
+-static const int pcie_reset0_pins[] = { 61 };
+-static const int pcie_reset1_pins[] = { 62 };
+-static const int pcie_reset2_pins[] = { 63 };
+-
+-static const struct pingroup airoha_pinctrl_groups[] = {
+- PINCTRL_PIN_GROUP(pon),
+- PINCTRL_PIN_GROUP(pon_tod_1pps),
+- PINCTRL_PIN_GROUP(gsw_tod_1pps),
+- PINCTRL_PIN_GROUP(sipo),
+- PINCTRL_PIN_GROUP(sipo_rclk),
+- PINCTRL_PIN_GROUP(mdio),
+- PINCTRL_PIN_GROUP(uart2),
+- PINCTRL_PIN_GROUP(uart2_cts_rts),
+- PINCTRL_PIN_GROUP(hsuart),
+- PINCTRL_PIN_GROUP(hsuart_cts_rts),
+- PINCTRL_PIN_GROUP(uart4),
+- PINCTRL_PIN_GROUP(uart5),
+- PINCTRL_PIN_GROUP(i2c0),
+- PINCTRL_PIN_GROUP(i2c1),
+- PINCTRL_PIN_GROUP(jtag_udi),
+- PINCTRL_PIN_GROUP(jtag_dfd),
+- PINCTRL_PIN_GROUP(i2s),
+- PINCTRL_PIN_GROUP(pcm1),
+- PINCTRL_PIN_GROUP(pcm2),
+- PINCTRL_PIN_GROUP(spi),
+- PINCTRL_PIN_GROUP(spi_quad),
+- PINCTRL_PIN_GROUP(spi_cs1),
+- PINCTRL_PIN_GROUP(pcm_spi),
+- PINCTRL_PIN_GROUP(pcm_spi_int),
+- PINCTRL_PIN_GROUP(pcm_spi_rst),
+- PINCTRL_PIN_GROUP(pcm_spi_cs1),
+- PINCTRL_PIN_GROUP(pcm_spi_cs2_p128),
+- PINCTRL_PIN_GROUP(pcm_spi_cs2_p156),
+- PINCTRL_PIN_GROUP(pcm_spi_cs2),
+- PINCTRL_PIN_GROUP(pcm_spi_cs3),
+- PINCTRL_PIN_GROUP(pcm_spi_cs4),
+- PINCTRL_PIN_GROUP(emmc),
+- PINCTRL_PIN_GROUP(pnand),
+- PINCTRL_PIN_GROUP(gpio0),
+- PINCTRL_PIN_GROUP(gpio1),
+- PINCTRL_PIN_GROUP(gpio2),
+- PINCTRL_PIN_GROUP(gpio3),
+- PINCTRL_PIN_GROUP(gpio4),
+- PINCTRL_PIN_GROUP(gpio5),
+- PINCTRL_PIN_GROUP(gpio6),
+- PINCTRL_PIN_GROUP(gpio7),
+- PINCTRL_PIN_GROUP(gpio8),
+- PINCTRL_PIN_GROUP(gpio9),
+- PINCTRL_PIN_GROUP(gpio10),
+- PINCTRL_PIN_GROUP(gpio11),
+- PINCTRL_PIN_GROUP(gpio12),
+- PINCTRL_PIN_GROUP(gpio13),
+- PINCTRL_PIN_GROUP(gpio14),
+- PINCTRL_PIN_GROUP(gpio15),
+- PINCTRL_PIN_GROUP(gpio16),
+- PINCTRL_PIN_GROUP(gpio17),
+- PINCTRL_PIN_GROUP(gpio18),
+- PINCTRL_PIN_GROUP(gpio19),
+- PINCTRL_PIN_GROUP(gpio20),
+- PINCTRL_PIN_GROUP(gpio21),
+- PINCTRL_PIN_GROUP(gpio22),
+- PINCTRL_PIN_GROUP(gpio23),
+- PINCTRL_PIN_GROUP(gpio24),
+- PINCTRL_PIN_GROUP(gpio25),
+- PINCTRL_PIN_GROUP(gpio26),
+- PINCTRL_PIN_GROUP(gpio27),
+- PINCTRL_PIN_GROUP(gpio28),
+- PINCTRL_PIN_GROUP(gpio29),
+- PINCTRL_PIN_GROUP(gpio30),
+- PINCTRL_PIN_GROUP(gpio31),
+- PINCTRL_PIN_GROUP(gpio33),
+- PINCTRL_PIN_GROUP(gpio34),
+- PINCTRL_PIN_GROUP(gpio35),
+- PINCTRL_PIN_GROUP(gpio36),
+- PINCTRL_PIN_GROUP(gpio37),
+- PINCTRL_PIN_GROUP(gpio38),
+- PINCTRL_PIN_GROUP(gpio39),
+- PINCTRL_PIN_GROUP(gpio40),
+- PINCTRL_PIN_GROUP(gpio41),
+- PINCTRL_PIN_GROUP(gpio42),
+- PINCTRL_PIN_GROUP(gpio43),
+- PINCTRL_PIN_GROUP(gpio44),
+- PINCTRL_PIN_GROUP(gpio45),
+- PINCTRL_PIN_GROUP(gpio46),
+- PINCTRL_PIN_GROUP(pcie_reset0),
+- PINCTRL_PIN_GROUP(pcie_reset1),
+- PINCTRL_PIN_GROUP(pcie_reset2),
++static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
++static const int en7581_pon_tod_1pps_pins[] = { 46 };
++static const int en7581_gsw_tod_1pps_pins[] = { 46 };
++static const int en7581_sipo_pins[] = { 16, 17 };
++static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
++static const int en7581_mdio_pins[] = { 14, 15 };
++static const int en7581_uart2_pins[] = { 48, 55 };
++static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
++static const int en7581_hsuart_pins[] = { 28, 29 };
++static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
++static const int en7581_uart4_pins[] = { 38, 39 };
++static const int en7581_uart5_pins[] = { 18, 19 };
++static const int en7581_i2c0_pins[] = { 2, 3 };
++static const int en7581_i2c1_pins[] = { 14, 15 };
++static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
++static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
++static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
++static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
++static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
++static const int en7581_spi_quad_pins[] = { 32, 33 };
++static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
++static const int en7581_spi_cs1_pins[] = { 34 };
++static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
++static const int en7581_pcm_spi_int_pins[] = { 14 };
++static const int en7581_pcm_spi_rst_pins[] = { 15 };
++static const int en7581_pcm_spi_cs1_pins[] = { 43 };
++static const int en7581_pcm_spi_cs2_pins[] = { 40 };
++static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
++static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
++static const int en7581_pcm_spi_cs3_pins[] = { 41 };
++static const int en7581_pcm_spi_cs4_pins[] = { 42 };
++static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
++static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
++static const int en7581_gpio0_pins[] = { 13 };
++static const int en7581_gpio1_pins[] = { 14 };
++static const int en7581_gpio2_pins[] = { 15 };
++static const int en7581_gpio3_pins[] = { 16 };
++static const int en7581_gpio4_pins[] = { 17 };
++static const int en7581_gpio5_pins[] = { 18 };
++static const int en7581_gpio6_pins[] = { 19 };
++static const int en7581_gpio7_pins[] = { 20 };
++static const int en7581_gpio8_pins[] = { 21 };
++static const int en7581_gpio9_pins[] = { 22 };
++static const int en7581_gpio10_pins[] = { 23 };
++static const int en7581_gpio11_pins[] = { 24 };
++static const int en7581_gpio12_pins[] = { 25 };
++static const int en7581_gpio13_pins[] = { 26 };
++static const int en7581_gpio14_pins[] = { 27 };
++static const int en7581_gpio15_pins[] = { 28 };
++static const int en7581_gpio16_pins[] = { 29 };
++static const int en7581_gpio17_pins[] = { 30 };
++static const int en7581_gpio18_pins[] = { 31 };
++static const int en7581_gpio19_pins[] = { 32 };
++static const int en7581_gpio20_pins[] = { 33 };
++static const int en7581_gpio21_pins[] = { 34 };
++static const int en7581_gpio22_pins[] = { 35 };
++static const int en7581_gpio23_pins[] = { 36 };
++static const int en7581_gpio24_pins[] = { 37 };
++static const int en7581_gpio25_pins[] = { 38 };
++static const int en7581_gpio26_pins[] = { 39 };
++static const int en7581_gpio27_pins[] = { 40 };
++static const int en7581_gpio28_pins[] = { 41 };
++static const int en7581_gpio29_pins[] = { 42 };
++static const int en7581_gpio30_pins[] = { 43 };
++static const int en7581_gpio31_pins[] = { 44 };
++static const int en7581_gpio33_pins[] = { 46 };
++static const int en7581_gpio34_pins[] = { 47 };
++static const int en7581_gpio35_pins[] = { 48 };
++static const int en7581_gpio36_pins[] = { 49 };
++static const int en7581_gpio37_pins[] = { 50 };
++static const int en7581_gpio38_pins[] = { 51 };
++static const int en7581_gpio39_pins[] = { 52 };
++static const int en7581_gpio40_pins[] = { 53 };
++static const int en7581_gpio41_pins[] = { 54 };
++static const int en7581_gpio42_pins[] = { 55 };
++static const int en7581_gpio43_pins[] = { 56 };
++static const int en7581_gpio44_pins[] = { 57 };
++static const int en7581_gpio45_pins[] = { 58 };
++static const int en7581_gpio46_pins[] = { 59 };
++static const int en7581_pcie_reset0_pins[] = { 61 };
++static const int en7581_pcie_reset1_pins[] = { 62 };
++static const int en7581_pcie_reset2_pins[] = { 63 };
++
++static const struct pingroup en7581_pinctrl_groups[] = {
++ PINCTRL_PIN_GROUP("pon", en7581_pon),
++ PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
++ PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
++ PINCTRL_PIN_GROUP("sipo", en7581_sipo),
++ PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
++ PINCTRL_PIN_GROUP("mdio", en7581_mdio),
++ PINCTRL_PIN_GROUP("uart2", en7581_uart2),
++ PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
++ PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
++ PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
++ PINCTRL_PIN_GROUP("uart4", en7581_uart4),
++ PINCTRL_PIN_GROUP("uart5", en7581_uart5),
++ PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
++ PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
++ PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
++ PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
++ PINCTRL_PIN_GROUP("i2s", en7581_i2s),
++ PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
++ PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
++ PINCTRL_PIN_GROUP("spi", en7581_spi),
++ PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
++ PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
++ PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
++ PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
++ PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
++ PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
++ PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
++ PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
++ PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
++ PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
++ PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
++ PINCTRL_PIN_GROUP("emmc", en7581_emmc),
++ PINCTRL_PIN_GROUP("pnand", en7581_pnand),
++ PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
++ PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
++ PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
++ PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
++ PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
++ PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
++ PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
++ PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
++ PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
++ PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
++ PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
++ PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
++ PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
++ PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
++ PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
++ PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
++ PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
++ PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
++ PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
++ PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
++ PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
++ PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
++ PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
++ PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
++ PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
++ PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
++ PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
++ PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
++ PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
++ PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
++ PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
++ PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
++ PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
++ PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
++ PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
++ PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
++ PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
++ PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
++ PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
++ PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
++ PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
++ PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
++ PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
++ PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
++ PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
++ PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
++ PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
++ PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
++ PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+ };
+
+ static const char *const pon_groups[] = { "pon" };
+@@ -1960,33 +1990,33 @@ static const struct airoha_pinctrl_func_
+ },
+ };
+
+-static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
+- PINCTRL_FUNC_DESC(pon),
+- PINCTRL_FUNC_DESC(tod_1pps),
+- PINCTRL_FUNC_DESC(sipo),
+- PINCTRL_FUNC_DESC(mdio),
+- PINCTRL_FUNC_DESC(uart),
+- PINCTRL_FUNC_DESC(i2c),
+- PINCTRL_FUNC_DESC(jtag),
+- PINCTRL_FUNC_DESC(pcm),
+- PINCTRL_FUNC_DESC(spi),
+- PINCTRL_FUNC_DESC(pcm_spi),
+- PINCTRL_FUNC_DESC(i2s),
+- PINCTRL_FUNC_DESC(emmc),
+- PINCTRL_FUNC_DESC(pnand),
+- PINCTRL_FUNC_DESC(pcie_reset),
+- PINCTRL_FUNC_DESC(pwm),
+- PINCTRL_FUNC_DESC(phy1_led0),
+- PINCTRL_FUNC_DESC(phy2_led0),
+- PINCTRL_FUNC_DESC(phy3_led0),
+- PINCTRL_FUNC_DESC(phy4_led0),
+- PINCTRL_FUNC_DESC(phy1_led1),
+- PINCTRL_FUNC_DESC(phy2_led1),
+- PINCTRL_FUNC_DESC(phy3_led1),
+- PINCTRL_FUNC_DESC(phy4_led1),
++static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
++ PINCTRL_FUNC_DESC("pon", pon),
++ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
++ PINCTRL_FUNC_DESC("sipo", sipo),
++ PINCTRL_FUNC_DESC("mdio", mdio),
++ PINCTRL_FUNC_DESC("uart", uart),
++ PINCTRL_FUNC_DESC("i2c", i2c),
++ PINCTRL_FUNC_DESC("jtag", jtag),
++ PINCTRL_FUNC_DESC("pcm", pcm),
++ PINCTRL_FUNC_DESC("spi", spi),
++ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
++ PINCTRL_FUNC_DESC("i2s", i2s),
++ PINCTRL_FUNC_DESC("emmc", emmc),
++ PINCTRL_FUNC_DESC("pnand", pnand),
++ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
++ PINCTRL_FUNC_DESC("pwm", pwm),
++ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
++ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
++ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
++ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
++ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
++ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
++ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
++ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+ };
+
+-static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
++static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+@@ -2047,7 +2077,7 @@ static const struct airoha_pinctrl_conf
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
+ };
+
+-static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
++static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+@@ -2108,7 +2138,7 @@ static const struct airoha_pinctrl_conf
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
+ };
+
+-static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
++static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+@@ -2169,7 +2199,7 @@ static const struct airoha_pinctrl_conf
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
+ };
+
+-static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
++static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+@@ -2230,7 +2260,7 @@ static const struct airoha_pinctrl_conf
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
+ };
+
+-static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = {
++static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+ PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+@@ -2552,12 +2582,17 @@ airoha_pinctrl_get_conf_reg(const struct
+ }
+
+ static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
+- const struct airoha_pinctrl_conf *conf,
+- int conf_size, int pin, u32 *val)
++ enum airoha_pinctrl_confs_type conf_type,
++ int pin, u32 *val)
+ {
++ const struct airoha_pinctrl_confs_info *confs_info;
+ const struct airoha_pinctrl_reg *reg;
+
+- reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
++ confs_info = &pinctrl->confs_info[conf_type];
++
++ reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
++ confs_info->num_confs,
++ pin);
+ if (!reg)
+ return -EINVAL;
+
+@@ -2570,12 +2605,17 @@ static int airoha_pinctrl_get_conf(struc
+ }
+
+ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
+- const struct airoha_pinctrl_conf *conf,
+- int conf_size, int pin, u32 val)
++ enum airoha_pinctrl_confs_type conf_type,
++ int pin, u32 val)
+ {
++ const struct airoha_pinctrl_confs_info *confs_info;
+ const struct airoha_pinctrl_reg *reg = NULL;
+
+- reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
++ confs_info = &pinctrl->confs_info[conf_type];
++
++ reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
++ confs_info->num_confs,
++ pin);
+ if (!reg)
+ return -EINVAL;
+
+@@ -2588,44 +2628,34 @@ static int airoha_pinctrl_set_conf(struc
+ }
+
+ #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
+- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf, \
+- ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
++ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
+ (pin), (val))
+ #define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \
+- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
+- ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
++ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
+ (pin), (val))
+ #define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \
+- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
+- ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
++ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
+ (pin), (val))
+ #define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \
+- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
+- ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
++ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
+ (pin), (val))
+ #define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \
+- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
+- ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
++ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
+ (pin), (val))
+ #define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \
+- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf, \
+- ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
++ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
+ (pin), (val))
+ #define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \
+- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
+- ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
++ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
+ (pin), (val))
+ #define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \
+- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
+- ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
++ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
+ (pin), (val))
+ #define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \
+- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
+- ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
++ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
+ (pin), (val))
+ #define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \
+- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
+- ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
++ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
+ (pin), (val))
+
+ static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
+@@ -2804,12 +2834,13 @@ static int airoha_pinconf_set(struct pin
+ static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
+ unsigned int group, unsigned long *config)
+ {
++ struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ u32 cur_config = 0;
+ int i;
+
+- for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
++ for (i = 0; i < pinctrl->grps[group].npins; i++) {
+ if (airoha_pinconf_get(pctrl_dev,
+- airoha_pinctrl_groups[group].pins[i],
++ pinctrl->grps[group].pins[i],
+ config))
+ return -ENOTSUPP;
+
+@@ -2826,13 +2857,14 @@ static int airoha_pinconf_group_set(stru
+ unsigned int group, unsigned long *configs,
+ unsigned int num_configs)
+ {
++ struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ int i;
+
+- for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
++ for (i = 0; i < pinctrl->grps[group].npins; i++) {
+ int err;
+
+ err = airoha_pinconf_set(pctrl_dev,
+- airoha_pinctrl_groups[group].pins[i],
++ pinctrl->grps[group].pins[i],
+ configs, num_configs);
+ if (err)
+ return err;
+@@ -2858,23 +2890,16 @@ static const struct pinctrl_ops airoha_p
+ .dt_free_map = pinconf_generic_dt_free_map,
+ };
+
+-static struct pinctrl_desc airoha_pinctrl_desc = {
+- .name = KBUILD_MODNAME,
+- .owner = THIS_MODULE,
+- .pctlops = &airoha_pctlops,
+- .pmxops = &airoha_pmxops,
+- .confops = &airoha_confops,
+- .pins = airoha_pinctrl_pins,
+- .npins = ARRAY_SIZE(airoha_pinctrl_pins),
+-};
+-
+ static int airoha_pinctrl_probe(struct platform_device *pdev)
+ {
++ const struct airoha_pinctrl_match_data *data;
+ struct device *dev = &pdev->dev;
+ struct airoha_pinctrl *pinctrl;
+ struct regmap *map;
+ int err, i;
+
++ data = device_get_match_data(dev);
++
+ pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
+ if (!pinctrl)
+ return -ENOMEM;
+@@ -2889,14 +2914,23 @@ static int airoha_pinctrl_probe(struct p
+
+ pinctrl->chip_scu = map;
+
+- err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc,
++ /* Init pinctrl desc struct */
++ pinctrl->desc.name = KBUILD_MODNAME;
++ pinctrl->desc.owner = THIS_MODULE,
++ pinctrl->desc.pctlops = &airoha_pctlops,
++ pinctrl->desc.pmxops = &airoha_pmxops,
++ pinctrl->desc.confops = &airoha_confops,
++ pinctrl->desc.pins = data->pins,
++ pinctrl->desc.npins = data->num_pins,
++
++ err = devm_pinctrl_register_and_init(dev, &pinctrl->desc,
+ pinctrl, &pinctrl->ctrl);
+ if (err)
+ return err;
+
+ /* build pin groups */
+- for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) {
+- const struct pingroup *grp = &airoha_pinctrl_groups[i];
++ for (i = 0; i < data->num_grps; i++) {
++ const struct pingroup *grp = &data->grps[i];
+
+ err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
+ grp->pins, grp->npins,
+@@ -2909,10 +2943,10 @@ static int airoha_pinctrl_probe(struct p
+ }
+
+ /* build functions */
+- for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) {
++ for (i = 0; i < data->num_funcs; i++) {
+ const struct airoha_pinctrl_func *func;
+
+- func = &airoha_pinctrl_funcs[i];
++ func = &data->funcs[i];
+ err = pinmux_generic_add_function(pinctrl->ctrl,
+ func->desc.func.name,
+ func->desc.func.groups,
+@@ -2925,6 +2959,10 @@ static int airoha_pinctrl_probe(struct p
+ }
+ }
+
++ pinctrl->grps = data->grps;
++ pinctrl->funcs = data->funcs;
++ pinctrl->confs_info = data->confs_info;
++
+ err = pinctrl_enable(pinctrl->ctrl);
+ if (err)
+ return err;
+@@ -2933,8 +2971,39 @@ static int airoha_pinctrl_probe(struct p
+ return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
+ }
+
++static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
++ .pins = en7581_pinctrl_pins,
++ .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
++ .grps = en7581_pinctrl_groups,
++ .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
++ .funcs = en7581_pinctrl_funcs,
++ .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
++ .confs_info = {
++ [AIROHA_PINCTRL_CONFS_PULLUP] = {
++ .confs = en7581_pinctrl_pullup_conf,
++ .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
++ },
++ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
++ .confs = en7581_pinctrl_pulldown_conf,
++ .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
++ },
++ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
++ .confs = en7581_pinctrl_drive_e2_conf,
++ .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
++ },
++ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
++ .confs = en7581_pinctrl_drive_e4_conf,
++ .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
++ },
++ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
++ .confs = en7581_pinctrl_pcie_rst_od_conf,
++ .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
++ },
++ },
++};
++
+ static const struct of_device_id airoha_pinctrl_of_match[] = {
+- { .compatible = "airoha,en7581-pinctrl" },
++ { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
--- /dev/null
+From 579839c9548cf2a85e873ad787bc2fa6610bf8ab Mon Sep 17 00:00:00 2001
+Date: Fri, 7 Nov 2025 00:57:05 +0100
+Subject: [PATCH 2/5] pinctrl: airoha: convert PHY LED GPIO to macro
+
+PHY LED GPIO pinctrl struct definition is very similar across the
+different 4 PHY and 2 LED and it can be generelized to a macro.
+
+To reduce code size, convert them to a common macro.
+
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 588 ++++------------------
+ 1 file changed, 100 insertions(+), 488 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
++++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -1478,516 +1478,128 @@ static const struct airoha_pinctrl_func_
+ },
+ };
+
++#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
++ { \
++ .name = (gpio), \
++ .regmap[0] = { \
++ AIROHA_FUNC_MUX, \
++ REG_GPIO_2ND_I2C_MODE, \
++ (mux_val), \
++ (mux_val), \
++ }, \
++ .regmap[1] = { \
++ AIROHA_FUNC_MUX, \
++ REG_LAN_LED0_MAPPING, \
++ (map_mask), \
++ (map_val), \
++ }, \
++ .regmap_size = 2, \
++ }
++
++#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
++ { \
++ .name = (gpio), \
++ .regmap[0] = { \
++ AIROHA_FUNC_MUX, \
++ REG_GPIO_2ND_I2C_MODE, \
++ (mux_val), \
++ (mux_val), \
++ }, \
++ .regmap[1] = { \
++ AIROHA_FUNC_MUX, \
++ REG_LAN_LED1_MAPPING, \
++ (map_mask), \
++ (map_val), \
++ }, \
++ .regmap_size = 2, \
++ }
++
+ static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+- {
+- .name = "gpio33",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN0_LED0_MODE_MASK,
+- GPIO_LAN0_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN0_LED_MAPPING_MASK,
+- LAN0_PHY_LED_MAP(0)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio34",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN1_LED0_MODE_MASK,
+- GPIO_LAN1_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN1_LED_MAPPING_MASK,
+- LAN1_PHY_LED_MAP(0)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio35",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN2_LED0_MODE_MASK,
+- GPIO_LAN2_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN2_LED_MAPPING_MASK,
+- LAN2_PHY_LED_MAP(0)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio42",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED0_MODE_MASK,
+- GPIO_LAN3_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN3_LED_MAPPING_MASK,
+- LAN3_PHY_LED_MAP(0)
+- },
+- .regmap_size = 2,
+- },
++ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+ };
+
+ static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+- {
+- .name = "gpio33",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN0_LED0_MODE_MASK,
+- GPIO_LAN0_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN0_LED_MAPPING_MASK,
+- LAN0_PHY_LED_MAP(1)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio34",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN1_LED0_MODE_MASK,
+- GPIO_LAN1_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN1_LED_MAPPING_MASK,
+- LAN1_PHY_LED_MAP(1)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio35",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN2_LED0_MODE_MASK,
+- GPIO_LAN2_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN2_LED_MAPPING_MASK,
+- LAN2_PHY_LED_MAP(1)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio42",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED0_MODE_MASK,
+- GPIO_LAN3_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN3_LED_MAPPING_MASK,
+- LAN3_PHY_LED_MAP(1)
+- },
+- .regmap_size = 2,
+- },
++ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+ };
+
+ static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+- {
+- .name = "gpio33",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN0_LED0_MODE_MASK,
+- GPIO_LAN0_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN0_LED_MAPPING_MASK,
+- LAN0_PHY_LED_MAP(2)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio34",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN1_LED0_MODE_MASK,
+- GPIO_LAN1_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN1_LED_MAPPING_MASK,
+- LAN1_PHY_LED_MAP(2)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio35",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN2_LED0_MODE_MASK,
+- GPIO_LAN2_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN2_LED_MAPPING_MASK,
+- LAN2_PHY_LED_MAP(2)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio42",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED0_MODE_MASK,
+- GPIO_LAN3_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN3_LED_MAPPING_MASK,
+- LAN3_PHY_LED_MAP(2)
+- },
+- .regmap_size = 2,
+- },
++ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+ };
+
+ static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+- {
+- .name = "gpio33",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN0_LED0_MODE_MASK,
+- GPIO_LAN0_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN0_LED_MAPPING_MASK,
+- LAN0_PHY_LED_MAP(3)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio34",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN1_LED0_MODE_MASK,
+- GPIO_LAN1_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN1_LED_MAPPING_MASK,
+- LAN1_PHY_LED_MAP(3)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio35",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN2_LED0_MODE_MASK,
+- GPIO_LAN2_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN2_LED_MAPPING_MASK,
+- LAN2_PHY_LED_MAP(3)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio42",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED0_MODE_MASK,
+- GPIO_LAN3_LED0_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED0_MAPPING,
+- LAN3_LED_MAPPING_MASK,
+- LAN3_PHY_LED_MAP(3)
+- },
+- .regmap_size = 2,
+- },
++ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+ };
+
+ static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+- {
+- .name = "gpio43",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN0_LED1_MODE_MASK,
+- GPIO_LAN0_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN0_LED_MAPPING_MASK,
+- LAN0_PHY_LED_MAP(0)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio44",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN1_LED1_MODE_MASK,
+- GPIO_LAN1_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN1_LED_MAPPING_MASK,
+- LAN1_PHY_LED_MAP(0)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio45",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN2_LED1_MODE_MASK,
+- GPIO_LAN2_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN2_LED_MAPPING_MASK,
+- LAN2_PHY_LED_MAP(0)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio46",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED1_MODE_MASK,
+- GPIO_LAN3_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN3_LED_MAPPING_MASK,
+- LAN3_PHY_LED_MAP(0)
+- },
+- .regmap_size = 2,
+- },
++ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+ };
+
+ static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+- {
+- .name = "gpio43",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN0_LED1_MODE_MASK,
+- GPIO_LAN0_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN0_LED_MAPPING_MASK,
+- LAN0_PHY_LED_MAP(1)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio44",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN1_LED1_MODE_MASK,
+- GPIO_LAN1_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN1_LED_MAPPING_MASK,
+- LAN1_PHY_LED_MAP(1)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio45",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN2_LED1_MODE_MASK,
+- GPIO_LAN2_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN2_LED_MAPPING_MASK,
+- LAN2_PHY_LED_MAP(1)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio46",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED1_MODE_MASK,
+- GPIO_LAN3_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN3_LED_MAPPING_MASK,
+- LAN3_PHY_LED_MAP(1)
+- },
+- .regmap_size = 2,
+- },
++ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+ };
+
+ static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+- {
+- .name = "gpio43",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN0_LED1_MODE_MASK,
+- GPIO_LAN0_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN0_LED_MAPPING_MASK,
+- LAN0_PHY_LED_MAP(2)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio44",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN1_LED1_MODE_MASK,
+- GPIO_LAN1_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN1_LED_MAPPING_MASK,
+- LAN1_PHY_LED_MAP(2)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio45",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN2_LED1_MODE_MASK,
+- GPIO_LAN2_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN2_LED_MAPPING_MASK,
+- LAN2_PHY_LED_MAP(2)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio46",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED1_MODE_MASK,
+- GPIO_LAN3_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN3_LED_MAPPING_MASK,
+- LAN3_PHY_LED_MAP(2)
+- },
+- .regmap_size = 2,
+- },
++ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+ };
+
+ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+- {
+- .name = "gpio43",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN0_LED1_MODE_MASK,
+- GPIO_LAN0_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN0_LED_MAPPING_MASK,
+- LAN0_PHY_LED_MAP(3)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio44",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN1_LED1_MODE_MASK,
+- GPIO_LAN1_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN1_LED_MAPPING_MASK,
+- LAN1_PHY_LED_MAP(3)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio45",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN2_LED1_MODE_MASK,
+- GPIO_LAN2_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN2_LED_MAPPING_MASK,
+- LAN2_PHY_LED_MAP(3)
+- },
+- .regmap_size = 2,
+- }, {
+- .name = "gpio46",
+- .regmap[0] = {
+- AIROHA_FUNC_MUX,
+- REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED1_MODE_MASK,
+- GPIO_LAN3_LED1_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+- REG_LAN_LED1_MAPPING,
+- LAN3_LED_MAPPING_MASK,
+- LAN3_PHY_LED_MAP(3)
+- },
+- .regmap_size = 2,
+- },
++ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+ };
+
+ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
--- /dev/null
+From 1552ad5d649cff9d170e5bc1d13ab1487333b4b7 Mon Sep 17 00:00:00 2001
+Date: Fri, 7 Nov 2025 00:57:06 +0100
+Subject: [PATCH 3/5] pinctrl: airoha: convert PWM GPIO to macro
+
+The PWM GPIO struct definition follow the same pattern for every GPIO
+pin hence it can be converted to a macro.
+
+Create 2 macro one for normal mux and one for ext mux and convert all
+the entry to these new macro to reduce code size.
+
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 465 ++++------------------
+ 1 file changed, 68 insertions(+), 397 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
++++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -1078,404 +1078,75 @@ static const struct airoha_pinctrl_func_
+ };
+
+ /* PWM */
++#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
++ { \
++ .name = (gpio), \
++ .regmap[0] = { \
++ AIROHA_FUNC_PWM_MUX, \
++ REG_GPIO_FLASH_MODE_CFG, \
++ (mux_val), \
++ (mux_val) \
++ }, \
++ .regmap_size = 1, \
++ } \
++
++#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
++ { \
++ .name = (gpio), \
++ .regmap[0] = { \
++ AIROHA_FUNC_PWM_EXT_MUX, \
++ REG_GPIO_FLASH_MODE_CFG_EXT, \
++ (mux_val), \
++ (mux_val) \
++ }, \
++ .regmap_size = 1, \
++ } \
++
+ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+- {
+- .name = "gpio0",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO0_FLASH_MODE_CFG,
+- GPIO0_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio1",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO1_FLASH_MODE_CFG,
+- GPIO1_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio2",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO2_FLASH_MODE_CFG,
+- GPIO2_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio3",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO3_FLASH_MODE_CFG,
+- GPIO3_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio4",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO4_FLASH_MODE_CFG,
+- GPIO4_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio5",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO5_FLASH_MODE_CFG,
+- GPIO5_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio6",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO6_FLASH_MODE_CFG,
+- GPIO6_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio7",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO7_FLASH_MODE_CFG,
+- GPIO7_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio8",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO8_FLASH_MODE_CFG,
+- GPIO8_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio9",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO9_FLASH_MODE_CFG,
+- GPIO9_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio10",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO10_FLASH_MODE_CFG,
+- GPIO10_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio11",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO11_FLASH_MODE_CFG,
+- GPIO11_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio12",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO12_FLASH_MODE_CFG,
+- GPIO12_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio13",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO13_FLASH_MODE_CFG,
+- GPIO13_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio14",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO14_FLASH_MODE_CFG,
+- GPIO14_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio15",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_MUX,
+- REG_GPIO_FLASH_MODE_CFG,
+- GPIO15_FLASH_MODE_CFG,
+- GPIO15_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio16",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO16_FLASH_MODE_CFG,
+- GPIO16_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio17",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO17_FLASH_MODE_CFG,
+- GPIO17_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio18",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO18_FLASH_MODE_CFG,
+- GPIO18_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio19",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO19_FLASH_MODE_CFG,
+- GPIO19_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio20",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO20_FLASH_MODE_CFG,
+- GPIO20_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio21",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO21_FLASH_MODE_CFG,
+- GPIO21_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio22",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO22_FLASH_MODE_CFG,
+- GPIO22_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio23",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO23_FLASH_MODE_CFG,
+- GPIO23_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio24",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO24_FLASH_MODE_CFG,
+- GPIO24_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio25",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO25_FLASH_MODE_CFG,
+- GPIO25_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio26",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO26_FLASH_MODE_CFG,
+- GPIO26_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio27",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO27_FLASH_MODE_CFG,
+- GPIO27_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio28",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO28_FLASH_MODE_CFG,
+- GPIO28_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio29",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO29_FLASH_MODE_CFG,
+- GPIO29_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio30",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO30_FLASH_MODE_CFG,
+- GPIO30_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio31",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO31_FLASH_MODE_CFG,
+- GPIO31_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio36",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO36_FLASH_MODE_CFG,
+- GPIO36_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio37",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO37_FLASH_MODE_CFG,
+- GPIO37_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio38",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO38_FLASH_MODE_CFG,
+- GPIO38_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio39",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO39_FLASH_MODE_CFG,
+- GPIO39_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio40",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO40_FLASH_MODE_CFG,
+- GPIO40_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio41",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO41_FLASH_MODE_CFG,
+- GPIO41_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio42",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO42_FLASH_MODE_CFG,
+- GPIO42_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio43",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO43_FLASH_MODE_CFG,
+- GPIO43_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio44",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO44_FLASH_MODE_CFG,
+- GPIO44_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio45",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO45_FLASH_MODE_CFG,
+- GPIO45_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio46",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO46_FLASH_MODE_CFG,
+- GPIO46_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- }, {
+- .name = "gpio47",
+- .regmap[0] = {
+- AIROHA_FUNC_PWM_EXT_MUX,
+- REG_GPIO_FLASH_MODE_CFG_EXT,
+- GPIO47_FLASH_MODE_CFG,
+- GPIO47_FLASH_MODE_CFG
+- },
+- .regmap_size = 1,
+- },
++ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
++ AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),
+ };
+
+ #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
--- /dev/null
+From 3ffeb17a9a27a668efb6fbd074835e187910a9bb Mon Sep 17 00:00:00 2001
+Date: Fri, 7 Nov 2025 00:57:08 +0100
+Subject: [PATCH 5/5] pinctrl: airoha: add support for Airoha AN7583 PINs
+
+Add all the required entry to add suppot for Airoha AN7583 PINs.
+
+Where possible the same function group are used from Airoha EN7581 to
+reduce code duplication.
+
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 747 +++++++++++++++++++++-
+ 1 file changed, 740 insertions(+), 7 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
++++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -75,6 +75,7 @@
+ #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
+ #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
+ #define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
++#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
+ #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
+ #define GPIO_PCM_SPI_MODE_MASK BIT(16)
+ #define GPIO_PCM2_MODE_MASK BIT(13)
+@@ -132,6 +133,8 @@
+
+ /* CONF */
+ #define REG_I2C_SDA_E2 0x001c
++#define AN7583_I2C1_SCL_E2_MASK BIT(16)
++#define AN7583_I2C1_SDA_E2_MASK BIT(15)
+ #define SPI_MISO_E2_MASK BIT(14)
+ #define SPI_MOSI_E2_MASK BIT(13)
+ #define SPI_CLK_E2_MASK BIT(12)
+@@ -139,12 +142,16 @@
+ #define PCIE2_RESET_E2_MASK BIT(10)
+ #define PCIE1_RESET_E2_MASK BIT(9)
+ #define PCIE0_RESET_E2_MASK BIT(8)
++#define AN7583_MDIO_0_E2_MASK BIT(5)
++#define AN7583_MDC_0_E2_MASK BIT(4)
+ #define UART1_RXD_E2_MASK BIT(3)
+ #define UART1_TXD_E2_MASK BIT(2)
+ #define I2C_SCL_E2_MASK BIT(1)
+ #define I2C_SDA_E2_MASK BIT(0)
+
+ #define REG_I2C_SDA_E4 0x0020
++#define AN7583_I2C1_SCL_E4_MASK BIT(16)
++#define AN7583_I2C1_SDA_E4_MASK BIT(15)
+ #define SPI_MISO_E4_MASK BIT(14)
+ #define SPI_MOSI_E4_MASK BIT(13)
+ #define SPI_CLK_E4_MASK BIT(12)
+@@ -152,6 +159,8 @@
+ #define PCIE2_RESET_E4_MASK BIT(10)
+ #define PCIE1_RESET_E4_MASK BIT(9)
+ #define PCIE0_RESET_E4_MASK BIT(8)
++#define AN7583_MDIO_0_E4_MASK BIT(5)
++#define AN7583_MDC_0_E4_MASK BIT(4)
+ #define UART1_RXD_E4_MASK BIT(3)
+ #define UART1_TXD_E4_MASK BIT(2)
+ #define I2C_SCL_E4_MASK BIT(1)
+@@ -163,6 +172,8 @@
+ #define REG_GPIO_H_E4 0x0030
+
+ #define REG_I2C_SDA_PU 0x0044
++#define AN7583_I2C1_SCL_PU_MASK BIT(16)
++#define AN7583_I2C1_SDA_PU_MASK BIT(15)
+ #define SPI_MISO_PU_MASK BIT(14)
+ #define SPI_MOSI_PU_MASK BIT(13)
+ #define SPI_CLK_PU_MASK BIT(12)
+@@ -170,12 +181,16 @@
+ #define PCIE2_RESET_PU_MASK BIT(10)
+ #define PCIE1_RESET_PU_MASK BIT(9)
+ #define PCIE0_RESET_PU_MASK BIT(8)
++#define AN7583_MDIO_0_PU_MASK BIT(5)
++#define AN7583_MDC_0_PU_MASK BIT(4)
+ #define UART1_RXD_PU_MASK BIT(3)
+ #define UART1_TXD_PU_MASK BIT(2)
+ #define I2C_SCL_PU_MASK BIT(1)
+ #define I2C_SDA_PU_MASK BIT(0)
+
+ #define REG_I2C_SDA_PD 0x0048
++#define AN7583_I2C1_SDA_PD_MASK BIT(16)
++#define AN7583_I2C1_SCL_PD_MASK BIT(15)
+ #define SPI_MISO_PD_MASK BIT(14)
+ #define SPI_MOSI_PD_MASK BIT(13)
+ #define SPI_CLK_PD_MASK BIT(12)
+@@ -183,6 +198,8 @@
+ #define PCIE2_RESET_PD_MASK BIT(10)
+ #define PCIE1_RESET_PD_MASK BIT(9)
+ #define PCIE0_RESET_PD_MASK BIT(8)
++#define AN7583_MDIO_0_PD_MASK BIT(5)
++#define AN7583_MDC_0_PD_MASK BIT(4)
+ #define UART1_RXD_PD_MASK BIT(3)
+ #define UART1_TXD_PD_MASK BIT(2)
+ #define I2C_SCL_PD_MASK BIT(1)
+@@ -630,10 +647,223 @@ static const struct pingroup en7581_pinc
+ PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+ };
+
++static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
++ PINCTRL_PIN(2, "gpio0"),
++ PINCTRL_PIN(3, "gpio1"),
++ PINCTRL_PIN(4, "gpio2"),
++ PINCTRL_PIN(5, "gpio3"),
++ PINCTRL_PIN(6, "gpio4"),
++ PINCTRL_PIN(7, "gpio5"),
++ PINCTRL_PIN(8, "gpio6"),
++ PINCTRL_PIN(9, "gpio7"),
++ PINCTRL_PIN(10, "gpio8"),
++ PINCTRL_PIN(11, "gpio9"),
++ PINCTRL_PIN(12, "gpio10"),
++ PINCTRL_PIN(13, "gpio11"),
++ PINCTRL_PIN(14, "gpio12"),
++ PINCTRL_PIN(15, "gpio13"),
++ PINCTRL_PIN(16, "gpio14"),
++ PINCTRL_PIN(17, "gpio15"),
++ PINCTRL_PIN(18, "gpio16"),
++ PINCTRL_PIN(19, "gpio17"),
++ PINCTRL_PIN(20, "gpio18"),
++ PINCTRL_PIN(21, "gpio19"),
++ PINCTRL_PIN(22, "gpio20"),
++ PINCTRL_PIN(23, "gpio21"),
++ PINCTRL_PIN(24, "gpio22"),
++ PINCTRL_PIN(25, "gpio23"),
++ PINCTRL_PIN(26, "gpio24"),
++ PINCTRL_PIN(27, "gpio25"),
++ PINCTRL_PIN(28, "gpio26"),
++ PINCTRL_PIN(29, "gpio27"),
++ PINCTRL_PIN(30, "gpio28"),
++ PINCTRL_PIN(31, "gpio29"),
++ PINCTRL_PIN(32, "gpio30"),
++ PINCTRL_PIN(33, "gpio31"),
++ PINCTRL_PIN(34, "gpio32"),
++ PINCTRL_PIN(35, "gpio33"),
++ PINCTRL_PIN(36, "gpio34"),
++ PINCTRL_PIN(37, "gpio35"),
++ PINCTRL_PIN(38, "gpio36"),
++ PINCTRL_PIN(39, "gpio37"),
++ PINCTRL_PIN(40, "gpio38"),
++ PINCTRL_PIN(41, "i2c0_scl"),
++ PINCTRL_PIN(42, "i2c0_sda"),
++ PINCTRL_PIN(43, "i2c1_scl"),
++ PINCTRL_PIN(44, "i2c1_sda"),
++ PINCTRL_PIN(45, "spi_clk"),
++ PINCTRL_PIN(46, "spi_cs"),
++ PINCTRL_PIN(47, "spi_mosi"),
++ PINCTRL_PIN(48, "spi_miso"),
++ PINCTRL_PIN(49, "uart_txd"),
++ PINCTRL_PIN(50, "uart_rxd"),
++ PINCTRL_PIN(51, "pcie_reset0"),
++ PINCTRL_PIN(52, "pcie_reset1"),
++ PINCTRL_PIN(53, "mdc_0"),
++ PINCTRL_PIN(54, "mdio_0"),
++};
++
++static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
++static const int an7583_pon_tod_1pps_pins[] = { 32 };
++static const int an7583_gsw_tod_1pps_pins[] = { 32 };
++static const int an7583_sipo_pins[] = { 34, 35 };
++static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
++static const int an7583_mdio_pins[] = { 43, 44 };
++static const int an7583_uart2_pins[] = { 34, 35 };
++static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
++static const int an7583_hsuart_pins[] = { 30, 31 };
++static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
++static const int an7583_npu_uart_pins[] = { 7, 8 };
++static const int an7583_uart4_pins[] = { 7, 8 };
++static const int an7583_uart5_pins[] = { 23, 24 };
++static const int an7583_i2c0_pins[] = { 41, 42 };
++static const int an7583_i2c1_pins[] = { 43, 44 };
++static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
++static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
++static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
++static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
++static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
++static const int an7583_spi_quad_pins[] = { 25, 26 };
++static const int an7583_spi_cs1_pins[] = { 27 };
++static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
++static const int an7583_pcm_spi_rst_pins[] = { 14 };
++static const int an7583_pcm_spi_cs1_pins[] = { 24 };
++static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
++static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
++static const int an7583_gpio0_pins[] = { 2 };
++static const int an7583_gpio1_pins[] = { 3 };
++static const int an7583_gpio2_pins[] = { 4 };
++static const int an7583_gpio3_pins[] = { 5 };
++static const int an7583_gpio4_pins[] = { 6 };
++static const int an7583_gpio5_pins[] = { 7 };
++static const int an7583_gpio6_pins[] = { 8 };
++static const int an7583_gpio7_pins[] = { 9 };
++static const int an7583_gpio8_pins[] = { 10 };
++static const int an7583_gpio9_pins[] = { 11 };
++static const int an7583_gpio10_pins[] = { 12 };
++static const int an7583_gpio11_pins[] = { 13 };
++static const int an7583_gpio12_pins[] = { 14 };
++static const int an7583_gpio13_pins[] = { 15 };
++static const int an7583_gpio14_pins[] = { 16 };
++static const int an7583_gpio15_pins[] = { 17 };
++static const int an7583_gpio16_pins[] = { 18 };
++static const int an7583_gpio17_pins[] = { 19 };
++static const int an7583_gpio18_pins[] = { 20 };
++static const int an7583_gpio19_pins[] = { 21 };
++static const int an7583_gpio20_pins[] = { 22 };
++static const int an7583_gpio21_pins[] = { 24 };
++static const int an7583_gpio23_pins[] = { 25 };
++static const int an7583_gpio24_pins[] = { 26 };
++static const int an7583_gpio25_pins[] = { 27 };
++static const int an7583_gpio26_pins[] = { 28 };
++static const int an7583_gpio27_pins[] = { 29 };
++static const int an7583_gpio28_pins[] = { 30 };
++static const int an7583_gpio29_pins[] = { 31 };
++static const int an7583_gpio30_pins[] = { 32 };
++static const int an7583_gpio31_pins[] = { 33 };
++static const int an7583_gpio33_pins[] = { 35 };
++static const int an7583_gpio34_pins[] = { 36 };
++static const int an7583_gpio35_pins[] = { 37 };
++static const int an7583_gpio36_pins[] = { 38 };
++static const int an7583_gpio37_pins[] = { 39 };
++static const int an7583_gpio38_pins[] = { 40 };
++static const int an7583_gpio39_pins[] = { 41 };
++static const int an7583_gpio40_pins[] = { 42 };
++static const int an7583_gpio41_pins[] = { 43 };
++static const int an7583_gpio42_pins[] = { 44 };
++static const int an7583_gpio43_pins[] = { 45 };
++static const int an7583_gpio44_pins[] = { 46 };
++static const int an7583_gpio45_pins[] = { 47 };
++static const int an7583_gpio46_pins[] = { 48 };
++static const int an7583_gpio47_pins[] = { 49 };
++static const int an7583_gpio48_pins[] = { 50 };
++static const int an7583_pcie_reset0_pins[] = { 51 };
++static const int an7583_pcie_reset1_pins[] = { 52 };
++
++static const struct pingroup an7583_pinctrl_groups[] = {
++ PINCTRL_PIN_GROUP("pon", an7583_pon),
++ PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
++ PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
++ PINCTRL_PIN_GROUP("sipo", an7583_sipo),
++ PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
++ PINCTRL_PIN_GROUP("mdio", an7583_mdio),
++ PINCTRL_PIN_GROUP("uart2", an7583_uart2),
++ PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
++ PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
++ PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
++ PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
++ PINCTRL_PIN_GROUP("uart4", an7583_uart4),
++ PINCTRL_PIN_GROUP("uart5", an7583_uart5),
++ PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
++ PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
++ PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
++ PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
++ PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
++ PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
++ PINCTRL_PIN_GROUP("spi", an7583_spi),
++ PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
++ PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
++ PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
++ PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
++ PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
++ PINCTRL_PIN_GROUP("emmc", an7583_emmc),
++ PINCTRL_PIN_GROUP("pnand", an7583_pnand),
++ PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
++ PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
++ PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
++ PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
++ PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
++ PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
++ PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
++ PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
++ PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
++ PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
++ PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
++ PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
++ PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
++ PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
++ PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
++ PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
++ PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
++ PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
++ PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
++ PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
++ PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
++ PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
++ PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
++ PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
++ PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
++ PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
++ PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
++ PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
++ PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
++ PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
++ PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
++ PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
++ PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
++ PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
++ PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
++ PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
++ PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
++ PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
++ PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
++ PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
++ PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
++ PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
++ PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
++ PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
++ PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
++ PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
++ PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
++ PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
++ PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
++};
++
+ static const char *const pon_groups[] = { "pon" };
+ static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
+ static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+ static const char *const mdio_groups[] = { "mdio" };
++static const char *const an7583_mdio_groups[] = { "mdio" };
+ static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
+ "hsuart_cts_rts", "uart4",
+ "uart5" };
+@@ -646,11 +876,16 @@ static const char *const pcm_spi_groups[
+ "pcm_spi_cs2_p156",
+ "pcm_spi_cs2_p128",
+ "pcm_spi_cs3", "pcm_spi_cs4" };
++static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
++ "pcm_spi_rst", "pcm_spi_cs1",
++ "pcm_spi_cs2", "pcm_spi_cs3",
++ "pcm_spi_cs4" };
+ static const char *const i2s_groups[] = { "i2s" };
+ static const char *const emmc_groups[] = { "emmc" };
+ static const char *const pnand_groups[] = { "pnand" };
+ static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
+ "pcie_reset2" };
++static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
+ static const char *const pwm_groups[] = { "gpio0", "gpio1",
+ "gpio2", "gpio3",
+ "gpio4", "gpio5",
+@@ -689,6 +924,22 @@ static const char *const phy3_led1_group
+ "gpio45", "gpio46" };
+ static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
+ "gpio45", "gpio46" };
++static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
++ "gpio3", "gpio4" };
++static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
++ "gpio3", "gpio4" };
++static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
++ "gpio3", "gpio4" };
++static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
++ "gpio3", "gpio4" };
++static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
++ "gpio10", "gpio11" };
++static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
++ "gpio10", "gpio11" };
++static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
++ "gpio10", "gpio11" };
++static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
++ "gpio10", "gpio11" };
+
+ static const struct airoha_pinctrl_func_group pon_func_group[] = {
+ {
+@@ -766,6 +1017,25 @@ static const struct airoha_pinctrl_func_
+ },
+ };
+
++static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
++ {
++ .name = "mdio",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_PON_MODE,
++ GPIO_SGMII_MDIO_MODE_MASK,
++ GPIO_SGMII_MDIO_MODE_MASK
++ },
++ .regmap[1] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ GPIO_MDC_IO_MASTER_MODE_MODE,
++ GPIO_MDC_IO_MASTER_MODE_MODE
++ },
++ .regmap_size = 2,
++ },
++};
++
+ static const struct airoha_pinctrl_func_group uart_func_group[] = {
+ {
+ .name = "uart2",
+@@ -1007,6 +1277,73 @@ static const struct airoha_pinctrl_func_
+ },
+ };
+
++static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
++ {
++ .name = "pcm_spi",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ GPIO_PCM_SPI_MODE_MASK,
++ GPIO_PCM_SPI_MODE_MASK
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "pcm_spi_int",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ GPIO_PCM_INT_MODE_MASK,
++ GPIO_PCM_INT_MODE_MASK
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "pcm_spi_rst",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ GPIO_PCM_RESET_MODE_MASK,
++ GPIO_PCM_RESET_MODE_MASK
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "pcm_spi_cs1",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ GPIO_PCM_SPI_CS1_MODE_MASK,
++ GPIO_PCM_SPI_CS1_MODE_MASK
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "pcm_spi_cs2",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
++ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "pcm_spi_cs3",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ GPIO_PCM_SPI_CS3_MODE_MASK,
++ GPIO_PCM_SPI_CS3_MODE_MASK
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "pcm_spi_cs4",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_SPI_CS1_MODE,
++ GPIO_PCM_SPI_CS4_MODE_MASK,
++ GPIO_PCM_SPI_CS4_MODE_MASK
++ },
++ .regmap_size = 1,
++ },
++};
++
+ static const struct airoha_pinctrl_func_group i2s_func_group[] = {
+ {
+ .name = "i2s",
+@@ -1077,6 +1414,28 @@ static const struct airoha_pinctrl_func_
+ },
+ };
+
++static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
++ {
++ .name = "pcie_reset0",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_PON_MODE,
++ GPIO_PCIE_RESET0_MASK,
++ GPIO_PCIE_RESET0_MASK
++ },
++ .regmap_size = 1,
++ }, {
++ .name = "pcie_reset1",
++ .regmap[0] = {
++ AIROHA_FUNC_MUX,
++ REG_GPIO_PON_MODE,
++ GPIO_PCIE_RESET1_MASK,
++ GPIO_PCIE_RESET1_MASK
++ },
++ .regmap_size = 1,
++ },
++};
++
+ /* PWM */
+ #define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+@@ -1273,6 +1632,94 @@ static const struct airoha_pinctrl_func_
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+ };
+
++static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
++ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
++ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
++ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
++ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
++ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio1", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
++ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
++ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
++ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++};
++
+ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+@@ -1299,6 +1746,31 @@ static const struct airoha_pinctrl_func
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+ };
+
++static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
++ PINCTRL_FUNC_DESC("pon", pon),
++ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
++ PINCTRL_FUNC_DESC("sipo", sipo),
++ PINCTRL_FUNC_DESC("mdio", an7583_mdio),
++ PINCTRL_FUNC_DESC("uart", uart),
++ PINCTRL_FUNC_DESC("i2c", i2c),
++ PINCTRL_FUNC_DESC("jtag", jtag),
++ PINCTRL_FUNC_DESC("pcm", pcm),
++ PINCTRL_FUNC_DESC("spi", spi),
++ PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
++ PINCTRL_FUNC_DESC("emmc", emmc),
++ PINCTRL_FUNC_DESC("pnand", pnand),
++ PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
++ PINCTRL_FUNC_DESC("pwm", pwm),
++ PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
++ PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
++ PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
++ PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
++ PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
++ PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
++ PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
++ PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
++};
++
+ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+@@ -1360,6 +1832,62 @@ static const struct airoha_pinctrl_conf
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
+ };
+
++static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
++ PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
++ PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
++ PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
++ PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
++ PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
++ PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
++ PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
++ PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
++ PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
++ PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
++ PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
++ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
++ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
++ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
++ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
++ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
++ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
++ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
++ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
++ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)),
++ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
++ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
++ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
++ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
++ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
++ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
++ PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
++ PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
++ PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
++ PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
++ PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
++ PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
++ PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
++ PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
++ PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
++ PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
++ PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
++ PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
++ PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
++ PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
++ PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
++ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
++ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
++ PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
++ PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
++ PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
++ PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
++ PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
++ PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
++ PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
++ PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
++ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
++ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
++};
++
+ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+@@ -1421,6 +1949,62 @@ static const struct airoha_pinctrl_conf
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
+ };
+
++static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
++ PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
++ PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
++ PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
++ PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
++ PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
++ PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
++ PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
++ PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
++ PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
++ PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
++ PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
++ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
++ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
++ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
++ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
++ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
++ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
++ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
++ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
++ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)),
++ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
++ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
++ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
++ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
++ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
++ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
++ PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
++ PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
++ PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
++ PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
++ PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
++ PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
++ PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
++ PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
++ PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
++ PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
++ PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
++ PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
++ PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
++ PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
++ PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
++ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
++ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
++ PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
++ PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
++ PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
++ PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
++ PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
++ PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
++ PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
++ PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
++ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
++ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
++};
++
+ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+@@ -1482,6 +2066,62 @@ static const struct airoha_pinctrl_conf
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
+ };
+
++static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
++ PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
++ PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
++ PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
++ PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
++ PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
++ PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
++ PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
++ PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
++ PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
++ PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
++ PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
++ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
++ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
++ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
++ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
++ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
++ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
++ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
++ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
++ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)),
++ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
++ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
++ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
++ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
++ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
++ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
++ PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
++ PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
++ PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
++ PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
++ PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
++ PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
++ PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
++ PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
++ PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
++ PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
++ PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
++ PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
++ PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
++ PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
++ PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
++ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
++ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
++ PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
++ PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
++ PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
++ PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
++ PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
++ PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
++ PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
++ PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
++ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
++ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
++};
++
+ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+@@ -1543,12 +2183,73 @@ static const struct airoha_pinctrl_conf
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
+ };
+
++static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
++ PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
++ PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
++ PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
++ PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
++ PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
++ PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
++ PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
++ PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
++ PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
++ PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
++ PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
++ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
++ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
++ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
++ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
++ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
++ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
++ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
++ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
++ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)),
++ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
++ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
++ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
++ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
++ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
++ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
++ PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
++ PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
++ PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
++ PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
++ PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
++ PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
++ PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
++ PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
++ PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
++ PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
++ PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
++ PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
++ PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
++ PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
++ PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
++ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
++ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
++ PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
++ PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
++ PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
++ PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
++ PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
++ PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
++ PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
++ PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
++ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
++ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
++};
++
+ static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+ PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+ };
+
++static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
++ PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
++ PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
++};
++
+ static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
+ struct pinctrl_gpio_range *range,
+ int pin)
+@@ -1714,7 +2415,7 @@ static const struct irq_chip airoha_gpio
+ };
+
+ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
+- struct platform_device *pdev)
++ struct platform_device *pdev)
+ {
+ struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
+ struct gpio_chip *gc = &chip->chip;
+@@ -1749,7 +2450,7 @@ static int airoha_pinctrl_add_gpiochip(s
+ return irq;
+
+ err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
+- dev_name(dev), pinctrl);
++ dev_name(dev), pinctrl);
+ if (err) {
+ dev_err(dev, "error requesting irq %d: %d\n", irq, err);
+ return err;
+@@ -1813,8 +2514,8 @@ static int airoha_pinmux_set_mux(struct
+ }
+
+ static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev,
+- struct pinctrl_gpio_range *range,
+- unsigned int p, bool input)
++ struct pinctrl_gpio_range *range,
++ unsigned int p, bool input)
+ {
+ struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ u32 mask, index;
+@@ -1904,7 +2605,7 @@ static int airoha_pinctrl_set_conf(struc
+
+
+ if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,
+- val << __ffs(reg->mask)))
++ val << __ffs(reg->mask)))
+ return -EINVAL;
+
+ return 0;
+@@ -2123,8 +2824,8 @@ static int airoha_pinconf_group_get(stru
+
+ for (i = 0; i < pinctrl->grps[group].npins; i++) {
+ if (airoha_pinconf_get(pctrl_dev,
+- pinctrl->grps[group].pins[i],
+- config))
++ pinctrl->grps[group].pins[i],
++ config))
+ return -ENOTSUPP;
+
+ if (i && cur_config != *config)
+@@ -2285,8 +2986,40 @@ static const struct airoha_pinctrl_match
+ },
+ };
+
++static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
++ .pins = an7583_pinctrl_pins,
++ .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
++ .grps = an7583_pinctrl_groups,
++ .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
++ .funcs = an7583_pinctrl_funcs,
++ .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
++ .confs_info = {
++ [AIROHA_PINCTRL_CONFS_PULLUP] = {
++ .confs = an7583_pinctrl_pullup_conf,
++ .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
++ },
++ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
++ .confs = an7583_pinctrl_pulldown_conf,
++ .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
++ },
++ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
++ .confs = en7581_pinctrl_drive_e2_conf,
++ .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
++ },
++ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
++ .confs = an7583_pinctrl_drive_e4_conf,
++ .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
++ },
++ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
++ .confs = an7583_pinctrl_pcie_rst_od_conf,
++ .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
++ },
++ },
++};
++
+ static const struct of_device_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
++ { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+++ /dev/null
-From e77c958d8eab1c29008ab57a2be82daefe886e0a Mon Sep 17 00:00:00 2001
-Date: Sun, 25 May 2025 19:25:20 +0200
-Subject: [PATCH 2/5] pinctrl: mediatek: airoha: generalize
- pins/group/function/confs handling
-
-In preparation for support of Airoha AN7583, generalize
-pins/group/function/confs handling and move them in match_data.
-Inner function will base the values on the pinctrl priv struct instead of
-relying on hardcoded struct.
-
-This permits to use different PIN data while keeping the same logic.
-
----
- drivers/pinctrl/mediatek/pinctrl-airoha.c | 569 ++++++++++++----------
- 1 file changed, 319 insertions(+), 250 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -30,20 +30,20 @@
- #include "../pinconf.h"
- #include "../pinmux.h"
-
--#define PINCTRL_PIN_GROUP(id) \
-- PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins))
-+#define PINCTRL_PIN_GROUP(id, table) \
-+ PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
-
--#define PINCTRL_FUNC_DESC(id) \
-+#define PINCTRL_FUNC_DESC(id, table) \
- { \
- .desc = { \
- .func = { \
-- .name = #id, \
-- .groups = id##_groups, \
-- .ngroups = ARRAY_SIZE(id##_groups), \
-+ .name = id, \
-+ .groups = table##_groups, \
-+ .ngroups = ARRAY_SIZE(table##_groups), \
- } \
- }, \
-- .groups = id##_func_group, \
-- .group_size = ARRAY_SIZE(id##_func_group), \
-+ .groups = table##_func_group, \
-+ .group_size = ARRAY_SIZE(table##_func_group), \
- }
-
- #define PINCTRL_CONF_DESC(p, offset, mask) \
-@@ -362,16 +362,46 @@ struct airoha_pinctrl_gpiochip {
- u32 irq_type[AIROHA_NUM_PINS];
- };
-
-+struct airoha_pinctrl_confs_info {
-+ const struct airoha_pinctrl_conf *confs;
-+ unsigned int num_confs;
-+};
-+
-+enum airoha_pinctrl_confs_type {
-+ AIROHA_PINCTRL_CONFS_PULLUP,
-+ AIROHA_PINCTRL_CONFS_PULLDOWN,
-+ AIROHA_PINCTRL_CONFS_DRIVE_E2,
-+ AIROHA_PINCTRL_CONFS_DRIVE_E4,
-+ AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
-+
-+ AIROHA_PINCTRL_CONFS_MAX,
-+};
-+
- struct airoha_pinctrl {
- struct pinctrl_dev *ctrl;
-
-+ struct pinctrl_desc desc;
-+ const struct pingroup *grps;
-+ const struct airoha_pinctrl_func *funcs;
-+ const struct airoha_pinctrl_confs_info *confs_info;
-+
- struct regmap *chip_scu;
- struct regmap *regmap;
-
- struct airoha_pinctrl_gpiochip gpiochip;
- };
-
--static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
-+struct airoha_pinctrl_match_data {
-+ const struct pinctrl_pin_desc *pins;
-+ const unsigned int num_pins;
-+ const struct pingroup *grps;
-+ const unsigned int num_grps;
-+ const struct airoha_pinctrl_func *funcs;
-+ const unsigned int num_funcs;
-+ const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
-+};
-+
-+static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
- PINCTRL_PIN(0, "uart1_txd"),
- PINCTRL_PIN(1, "uart1_rxd"),
- PINCTRL_PIN(2, "i2c_scl"),
-@@ -432,172 +462,172 @@ static struct pinctrl_pin_desc airoha_pi
- PINCTRL_PIN(63, "pcie_reset2"),
- };
-
--static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
--static const int pon_tod_1pps_pins[] = { 46 };
--static const int gsw_tod_1pps_pins[] = { 46 };
--static const int sipo_pins[] = { 16, 17 };
--static const int sipo_rclk_pins[] = { 16, 17, 43 };
--static const int mdio_pins[] = { 14, 15 };
--static const int uart2_pins[] = { 48, 55 };
--static const int uart2_cts_rts_pins[] = { 46, 47 };
--static const int hsuart_pins[] = { 28, 29 };
--static const int hsuart_cts_rts_pins[] = { 26, 27 };
--static const int uart4_pins[] = { 38, 39 };
--static const int uart5_pins[] = { 18, 19 };
--static const int i2c0_pins[] = { 2, 3 };
--static const int i2c1_pins[] = { 14, 15 };
--static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
--static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
--static const int i2s_pins[] = { 26, 27, 28, 29 };
--static const int pcm1_pins[] = { 22, 23, 24, 25 };
--static const int pcm2_pins[] = { 18, 19, 20, 21 };
--static const int spi_quad_pins[] = { 32, 33 };
--static const int spi_pins[] = { 4, 5, 6, 7 };
--static const int spi_cs1_pins[] = { 34 };
--static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
--static const int pcm_spi_int_pins[] = { 14 };
--static const int pcm_spi_rst_pins[] = { 15 };
--static const int pcm_spi_cs1_pins[] = { 43 };
--static const int pcm_spi_cs2_pins[] = { 40 };
--static const int pcm_spi_cs2_p128_pins[] = { 40 };
--static const int pcm_spi_cs2_p156_pins[] = { 40 };
--static const int pcm_spi_cs3_pins[] = { 41 };
--static const int pcm_spi_cs4_pins[] = { 42 };
--static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
--static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
--static const int gpio0_pins[] = { 13 };
--static const int gpio1_pins[] = { 14 };
--static const int gpio2_pins[] = { 15 };
--static const int gpio3_pins[] = { 16 };
--static const int gpio4_pins[] = { 17 };
--static const int gpio5_pins[] = { 18 };
--static const int gpio6_pins[] = { 19 };
--static const int gpio7_pins[] = { 20 };
--static const int gpio8_pins[] = { 21 };
--static const int gpio9_pins[] = { 22 };
--static const int gpio10_pins[] = { 23 };
--static const int gpio11_pins[] = { 24 };
--static const int gpio12_pins[] = { 25 };
--static const int gpio13_pins[] = { 26 };
--static const int gpio14_pins[] = { 27 };
--static const int gpio15_pins[] = { 28 };
--static const int gpio16_pins[] = { 29 };
--static const int gpio17_pins[] = { 30 };
--static const int gpio18_pins[] = { 31 };
--static const int gpio19_pins[] = { 32 };
--static const int gpio20_pins[] = { 33 };
--static const int gpio21_pins[] = { 34 };
--static const int gpio22_pins[] = { 35 };
--static const int gpio23_pins[] = { 36 };
--static const int gpio24_pins[] = { 37 };
--static const int gpio25_pins[] = { 38 };
--static const int gpio26_pins[] = { 39 };
--static const int gpio27_pins[] = { 40 };
--static const int gpio28_pins[] = { 41 };
--static const int gpio29_pins[] = { 42 };
--static const int gpio30_pins[] = { 43 };
--static const int gpio31_pins[] = { 44 };
--static const int gpio33_pins[] = { 46 };
--static const int gpio34_pins[] = { 47 };
--static const int gpio35_pins[] = { 48 };
--static const int gpio36_pins[] = { 49 };
--static const int gpio37_pins[] = { 50 };
--static const int gpio38_pins[] = { 51 };
--static const int gpio39_pins[] = { 52 };
--static const int gpio40_pins[] = { 53 };
--static const int gpio41_pins[] = { 54 };
--static const int gpio42_pins[] = { 55 };
--static const int gpio43_pins[] = { 56 };
--static const int gpio44_pins[] = { 57 };
--static const int gpio45_pins[] = { 58 };
--static const int gpio46_pins[] = { 59 };
--static const int pcie_reset0_pins[] = { 61 };
--static const int pcie_reset1_pins[] = { 62 };
--static const int pcie_reset2_pins[] = { 63 };
--
--static const struct pingroup airoha_pinctrl_groups[] = {
-- PINCTRL_PIN_GROUP(pon),
-- PINCTRL_PIN_GROUP(pon_tod_1pps),
-- PINCTRL_PIN_GROUP(gsw_tod_1pps),
-- PINCTRL_PIN_GROUP(sipo),
-- PINCTRL_PIN_GROUP(sipo_rclk),
-- PINCTRL_PIN_GROUP(mdio),
-- PINCTRL_PIN_GROUP(uart2),
-- PINCTRL_PIN_GROUP(uart2_cts_rts),
-- PINCTRL_PIN_GROUP(hsuart),
-- PINCTRL_PIN_GROUP(hsuart_cts_rts),
-- PINCTRL_PIN_GROUP(uart4),
-- PINCTRL_PIN_GROUP(uart5),
-- PINCTRL_PIN_GROUP(i2c0),
-- PINCTRL_PIN_GROUP(i2c1),
-- PINCTRL_PIN_GROUP(jtag_udi),
-- PINCTRL_PIN_GROUP(jtag_dfd),
-- PINCTRL_PIN_GROUP(i2s),
-- PINCTRL_PIN_GROUP(pcm1),
-- PINCTRL_PIN_GROUP(pcm2),
-- PINCTRL_PIN_GROUP(spi),
-- PINCTRL_PIN_GROUP(spi_quad),
-- PINCTRL_PIN_GROUP(spi_cs1),
-- PINCTRL_PIN_GROUP(pcm_spi),
-- PINCTRL_PIN_GROUP(pcm_spi_int),
-- PINCTRL_PIN_GROUP(pcm_spi_rst),
-- PINCTRL_PIN_GROUP(pcm_spi_cs1),
-- PINCTRL_PIN_GROUP(pcm_spi_cs2_p128),
-- PINCTRL_PIN_GROUP(pcm_spi_cs2_p156),
-- PINCTRL_PIN_GROUP(pcm_spi_cs2),
-- PINCTRL_PIN_GROUP(pcm_spi_cs3),
-- PINCTRL_PIN_GROUP(pcm_spi_cs4),
-- PINCTRL_PIN_GROUP(emmc),
-- PINCTRL_PIN_GROUP(pnand),
-- PINCTRL_PIN_GROUP(gpio0),
-- PINCTRL_PIN_GROUP(gpio1),
-- PINCTRL_PIN_GROUP(gpio2),
-- PINCTRL_PIN_GROUP(gpio3),
-- PINCTRL_PIN_GROUP(gpio4),
-- PINCTRL_PIN_GROUP(gpio5),
-- PINCTRL_PIN_GROUP(gpio6),
-- PINCTRL_PIN_GROUP(gpio7),
-- PINCTRL_PIN_GROUP(gpio8),
-- PINCTRL_PIN_GROUP(gpio9),
-- PINCTRL_PIN_GROUP(gpio10),
-- PINCTRL_PIN_GROUP(gpio11),
-- PINCTRL_PIN_GROUP(gpio12),
-- PINCTRL_PIN_GROUP(gpio13),
-- PINCTRL_PIN_GROUP(gpio14),
-- PINCTRL_PIN_GROUP(gpio15),
-- PINCTRL_PIN_GROUP(gpio16),
-- PINCTRL_PIN_GROUP(gpio17),
-- PINCTRL_PIN_GROUP(gpio18),
-- PINCTRL_PIN_GROUP(gpio19),
-- PINCTRL_PIN_GROUP(gpio20),
-- PINCTRL_PIN_GROUP(gpio21),
-- PINCTRL_PIN_GROUP(gpio22),
-- PINCTRL_PIN_GROUP(gpio23),
-- PINCTRL_PIN_GROUP(gpio24),
-- PINCTRL_PIN_GROUP(gpio25),
-- PINCTRL_PIN_GROUP(gpio26),
-- PINCTRL_PIN_GROUP(gpio27),
-- PINCTRL_PIN_GROUP(gpio28),
-- PINCTRL_PIN_GROUP(gpio29),
-- PINCTRL_PIN_GROUP(gpio30),
-- PINCTRL_PIN_GROUP(gpio31),
-- PINCTRL_PIN_GROUP(gpio33),
-- PINCTRL_PIN_GROUP(gpio34),
-- PINCTRL_PIN_GROUP(gpio35),
-- PINCTRL_PIN_GROUP(gpio36),
-- PINCTRL_PIN_GROUP(gpio37),
-- PINCTRL_PIN_GROUP(gpio38),
-- PINCTRL_PIN_GROUP(gpio39),
-- PINCTRL_PIN_GROUP(gpio40),
-- PINCTRL_PIN_GROUP(gpio41),
-- PINCTRL_PIN_GROUP(gpio42),
-- PINCTRL_PIN_GROUP(gpio43),
-- PINCTRL_PIN_GROUP(gpio44),
-- PINCTRL_PIN_GROUP(gpio45),
-- PINCTRL_PIN_GROUP(gpio46),
-- PINCTRL_PIN_GROUP(pcie_reset0),
-- PINCTRL_PIN_GROUP(pcie_reset1),
-- PINCTRL_PIN_GROUP(pcie_reset2),
-+static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
-+static const int en7581_pon_tod_1pps_pins[] = { 46 };
-+static const int en7581_gsw_tod_1pps_pins[] = { 46 };
-+static const int en7581_sipo_pins[] = { 16, 17 };
-+static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
-+static const int en7581_mdio_pins[] = { 14, 15 };
-+static const int en7581_uart2_pins[] = { 48, 55 };
-+static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
-+static const int en7581_hsuart_pins[] = { 28, 29 };
-+static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
-+static const int en7581_uart4_pins[] = { 38, 39 };
-+static const int en7581_uart5_pins[] = { 18, 19 };
-+static const int en7581_i2c0_pins[] = { 2, 3 };
-+static const int en7581_i2c1_pins[] = { 14, 15 };
-+static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
-+static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
-+static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
-+static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
-+static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
-+static const int en7581_spi_quad_pins[] = { 32, 33 };
-+static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
-+static const int en7581_spi_cs1_pins[] = { 34 };
-+static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
-+static const int en7581_pcm_spi_int_pins[] = { 14 };
-+static const int en7581_pcm_spi_rst_pins[] = { 15 };
-+static const int en7581_pcm_spi_cs1_pins[] = { 43 };
-+static const int en7581_pcm_spi_cs2_pins[] = { 40 };
-+static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
-+static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
-+static const int en7581_pcm_spi_cs3_pins[] = { 41 };
-+static const int en7581_pcm_spi_cs4_pins[] = { 42 };
-+static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
-+static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
-+static const int en7581_gpio0_pins[] = { 13 };
-+static const int en7581_gpio1_pins[] = { 14 };
-+static const int en7581_gpio2_pins[] = { 15 };
-+static const int en7581_gpio3_pins[] = { 16 };
-+static const int en7581_gpio4_pins[] = { 17 };
-+static const int en7581_gpio5_pins[] = { 18 };
-+static const int en7581_gpio6_pins[] = { 19 };
-+static const int en7581_gpio7_pins[] = { 20 };
-+static const int en7581_gpio8_pins[] = { 21 };
-+static const int en7581_gpio9_pins[] = { 22 };
-+static const int en7581_gpio10_pins[] = { 23 };
-+static const int en7581_gpio11_pins[] = { 24 };
-+static const int en7581_gpio12_pins[] = { 25 };
-+static const int en7581_gpio13_pins[] = { 26 };
-+static const int en7581_gpio14_pins[] = { 27 };
-+static const int en7581_gpio15_pins[] = { 28 };
-+static const int en7581_gpio16_pins[] = { 29 };
-+static const int en7581_gpio17_pins[] = { 30 };
-+static const int en7581_gpio18_pins[] = { 31 };
-+static const int en7581_gpio19_pins[] = { 32 };
-+static const int en7581_gpio20_pins[] = { 33 };
-+static const int en7581_gpio21_pins[] = { 34 };
-+static const int en7581_gpio22_pins[] = { 35 };
-+static const int en7581_gpio23_pins[] = { 36 };
-+static const int en7581_gpio24_pins[] = { 37 };
-+static const int en7581_gpio25_pins[] = { 38 };
-+static const int en7581_gpio26_pins[] = { 39 };
-+static const int en7581_gpio27_pins[] = { 40 };
-+static const int en7581_gpio28_pins[] = { 41 };
-+static const int en7581_gpio29_pins[] = { 42 };
-+static const int en7581_gpio30_pins[] = { 43 };
-+static const int en7581_gpio31_pins[] = { 44 };
-+static const int en7581_gpio33_pins[] = { 46 };
-+static const int en7581_gpio34_pins[] = { 47 };
-+static const int en7581_gpio35_pins[] = { 48 };
-+static const int en7581_gpio36_pins[] = { 49 };
-+static const int en7581_gpio37_pins[] = { 50 };
-+static const int en7581_gpio38_pins[] = { 51 };
-+static const int en7581_gpio39_pins[] = { 52 };
-+static const int en7581_gpio40_pins[] = { 53 };
-+static const int en7581_gpio41_pins[] = { 54 };
-+static const int en7581_gpio42_pins[] = { 55 };
-+static const int en7581_gpio43_pins[] = { 56 };
-+static const int en7581_gpio44_pins[] = { 57 };
-+static const int en7581_gpio45_pins[] = { 58 };
-+static const int en7581_gpio46_pins[] = { 59 };
-+static const int en7581_pcie_reset0_pins[] = { 61 };
-+static const int en7581_pcie_reset1_pins[] = { 62 };
-+static const int en7581_pcie_reset2_pins[] = { 63 };
-+
-+static const struct pingroup en7581_pinctrl_groups[] = {
-+ PINCTRL_PIN_GROUP("pon", en7581_pon),
-+ PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
-+ PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
-+ PINCTRL_PIN_GROUP("sipo", en7581_sipo),
-+ PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
-+ PINCTRL_PIN_GROUP("mdio", en7581_mdio),
-+ PINCTRL_PIN_GROUP("uart2", en7581_uart2),
-+ PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
-+ PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
-+ PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
-+ PINCTRL_PIN_GROUP("uart4", en7581_uart4),
-+ PINCTRL_PIN_GROUP("uart5", en7581_uart5),
-+ PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
-+ PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
-+ PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
-+ PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
-+ PINCTRL_PIN_GROUP("i2s", en7581_i2s),
-+ PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
-+ PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
-+ PINCTRL_PIN_GROUP("spi", en7581_spi),
-+ PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
-+ PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
-+ PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
-+ PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
-+ PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
-+ PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
-+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
-+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
-+ PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
-+ PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
-+ PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
-+ PINCTRL_PIN_GROUP("emmc", en7581_emmc),
-+ PINCTRL_PIN_GROUP("pnand", en7581_pnand),
-+ PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
-+ PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
-+ PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
-+ PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
-+ PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
-+ PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
-+ PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
-+ PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
-+ PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
-+ PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
-+ PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
-+ PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
-+ PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
-+ PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
-+ PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
-+ PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
-+ PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
-+ PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
-+ PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
-+ PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
-+ PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
-+ PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
-+ PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
-+ PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
-+ PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
-+ PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
-+ PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
-+ PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
-+ PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
-+ PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
-+ PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
-+ PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
-+ PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
-+ PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
-+ PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
-+ PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
-+ PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
-+ PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
-+ PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
-+ PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
-+ PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
-+ PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
-+ PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
-+ PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
-+ PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
-+ PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
-+ PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
-+ PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
-+ PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
- };
-
- static const char *const pon_groups[] = { "pon" };
-@@ -1960,33 +1990,33 @@ static const struct airoha_pinctrl_func_
- },
- };
-
--static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
-- PINCTRL_FUNC_DESC(pon),
-- PINCTRL_FUNC_DESC(tod_1pps),
-- PINCTRL_FUNC_DESC(sipo),
-- PINCTRL_FUNC_DESC(mdio),
-- PINCTRL_FUNC_DESC(uart),
-- PINCTRL_FUNC_DESC(i2c),
-- PINCTRL_FUNC_DESC(jtag),
-- PINCTRL_FUNC_DESC(pcm),
-- PINCTRL_FUNC_DESC(spi),
-- PINCTRL_FUNC_DESC(pcm_spi),
-- PINCTRL_FUNC_DESC(i2s),
-- PINCTRL_FUNC_DESC(emmc),
-- PINCTRL_FUNC_DESC(pnand),
-- PINCTRL_FUNC_DESC(pcie_reset),
-- PINCTRL_FUNC_DESC(pwm),
-- PINCTRL_FUNC_DESC(phy1_led0),
-- PINCTRL_FUNC_DESC(phy2_led0),
-- PINCTRL_FUNC_DESC(phy3_led0),
-- PINCTRL_FUNC_DESC(phy4_led0),
-- PINCTRL_FUNC_DESC(phy1_led1),
-- PINCTRL_FUNC_DESC(phy2_led1),
-- PINCTRL_FUNC_DESC(phy3_led1),
-- PINCTRL_FUNC_DESC(phy4_led1),
-+static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
-+ PINCTRL_FUNC_DESC("pon", pon),
-+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
-+ PINCTRL_FUNC_DESC("sipo", sipo),
-+ PINCTRL_FUNC_DESC("mdio", mdio),
-+ PINCTRL_FUNC_DESC("uart", uart),
-+ PINCTRL_FUNC_DESC("i2c", i2c),
-+ PINCTRL_FUNC_DESC("jtag", jtag),
-+ PINCTRL_FUNC_DESC("pcm", pcm),
-+ PINCTRL_FUNC_DESC("spi", spi),
-+ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
-+ PINCTRL_FUNC_DESC("i2s", i2s),
-+ PINCTRL_FUNC_DESC("emmc", emmc),
-+ PINCTRL_FUNC_DESC("pnand", pnand),
-+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
-+ PINCTRL_FUNC_DESC("pwm", pwm),
-+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
-+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
-+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
-+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
-+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
-+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
-+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
-+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
- };
-
--static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
-+static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
-@@ -2047,7 +2077,7 @@ static const struct airoha_pinctrl_conf
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
- };
-
--static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
-+static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
-@@ -2108,7 +2138,7 @@ static const struct airoha_pinctrl_conf
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
- };
-
--static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
-+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
-@@ -2169,7 +2199,7 @@ static const struct airoha_pinctrl_conf
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
- };
-
--static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
-+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
-@@ -2230,7 +2260,7 @@ static const struct airoha_pinctrl_conf
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
- };
-
--static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = {
-+static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
- PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
- PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
- PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
-@@ -2552,12 +2582,17 @@ airoha_pinctrl_get_conf_reg(const struct
- }
-
- static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
-- const struct airoha_pinctrl_conf *conf,
-- int conf_size, int pin, u32 *val)
-+ enum airoha_pinctrl_confs_type conf_type,
-+ int pin, u32 *val)
- {
-+ const struct airoha_pinctrl_confs_info *confs_info;
- const struct airoha_pinctrl_reg *reg;
-
-- reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
-+ confs_info = &pinctrl->confs_info[conf_type];
-+
-+ reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
-+ confs_info->num_confs,
-+ pin);
- if (!reg)
- return -EINVAL;
-
-@@ -2570,12 +2605,17 @@ static int airoha_pinctrl_get_conf(struc
- }
-
- static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
-- const struct airoha_pinctrl_conf *conf,
-- int conf_size, int pin, u32 val)
-+ enum airoha_pinctrl_confs_type conf_type,
-+ int pin, u32 val)
- {
-+ const struct airoha_pinctrl_confs_info *confs_info;
- const struct airoha_pinctrl_reg *reg = NULL;
-
-- reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
-+ confs_info = &pinctrl->confs_info[conf_type];
-+
-+ reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
-+ confs_info->num_confs,
-+ pin);
- if (!reg)
- return -EINVAL;
-
-@@ -2588,44 +2628,34 @@ static int airoha_pinctrl_set_conf(struc
- }
-
- #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
-- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf, \
-- ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
-+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
- (pin), (val))
- #define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \
-- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
-- ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
-+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
- (pin), (val))
- #define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \
-- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
-- ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
-+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
- (pin), (val))
- #define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \
-- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
-- ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
-+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
- (pin), (val))
- #define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \
-- airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
-- ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
-+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
- (pin), (val))
- #define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \
-- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf, \
-- ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
-+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
- (pin), (val))
- #define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \
-- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
-- ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
-+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
- (pin), (val))
- #define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \
-- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
-- ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
-+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
- (pin), (val))
- #define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \
-- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
-- ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
-+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
- (pin), (val))
- #define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \
-- airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
-- ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
-+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
- (pin), (val))
-
- static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
-@@ -2804,12 +2834,13 @@ static int airoha_pinconf_set(struct pin
- static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
- unsigned int group, unsigned long *config)
- {
-+ struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
- u32 cur_config = 0;
- int i;
-
-- for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
-+ for (i = 0; i < pinctrl->grps[group].npins; i++) {
- if (airoha_pinconf_get(pctrl_dev,
-- airoha_pinctrl_groups[group].pins[i],
-+ pinctrl->grps[group].pins[i],
- config))
- return -ENOTSUPP;
-
-@@ -2826,13 +2857,14 @@ static int airoha_pinconf_group_set(stru
- unsigned int group, unsigned long *configs,
- unsigned int num_configs)
- {
-+ struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
- int i;
-
-- for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
-+ for (i = 0; i < pinctrl->grps[group].npins; i++) {
- int err;
-
- err = airoha_pinconf_set(pctrl_dev,
-- airoha_pinctrl_groups[group].pins[i],
-+ pinctrl->grps[group].pins[i],
- configs, num_configs);
- if (err)
- return err;
-@@ -2858,23 +2890,16 @@ static const struct pinctrl_ops airoha_p
- .dt_free_map = pinconf_generic_dt_free_map,
- };
-
--static struct pinctrl_desc airoha_pinctrl_desc = {
-- .name = KBUILD_MODNAME,
-- .owner = THIS_MODULE,
-- .pctlops = &airoha_pctlops,
-- .pmxops = &airoha_pmxops,
-- .confops = &airoha_confops,
-- .pins = airoha_pinctrl_pins,
-- .npins = ARRAY_SIZE(airoha_pinctrl_pins),
--};
--
- static int airoha_pinctrl_probe(struct platform_device *pdev)
- {
-+ const struct airoha_pinctrl_match_data *data;
- struct device *dev = &pdev->dev;
- struct airoha_pinctrl *pinctrl;
- struct regmap *map;
- int err, i;
-
-+ data = device_get_match_data(dev);
-+
- pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
- if (!pinctrl)
- return -ENOMEM;
-@@ -2889,14 +2914,23 @@ static int airoha_pinctrl_probe(struct p
-
- pinctrl->chip_scu = map;
-
-- err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc,
-+ /* Init pinctrl desc struct */
-+ pinctrl->desc.name = KBUILD_MODNAME;
-+ pinctrl->desc.owner = THIS_MODULE,
-+ pinctrl->desc.pctlops = &airoha_pctlops,
-+ pinctrl->desc.pmxops = &airoha_pmxops,
-+ pinctrl->desc.confops = &airoha_confops,
-+ pinctrl->desc.pins = data->pins,
-+ pinctrl->desc.npins = data->num_pins,
-+
-+ err = devm_pinctrl_register_and_init(dev, &pinctrl->desc,
- pinctrl, &pinctrl->ctrl);
- if (err)
- return err;
-
- /* build pin groups */
-- for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) {
-- const struct pingroup *grp = &airoha_pinctrl_groups[i];
-+ for (i = 0; i < data->num_grps; i++) {
-+ const struct pingroup *grp = &data->grps[i];
-
- err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
- grp->pins, grp->npins,
-@@ -2909,10 +2943,10 @@ static int airoha_pinctrl_probe(struct p
- }
-
- /* build functions */
-- for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) {
-+ for (i = 0; i < data->num_funcs; i++) {
- const struct airoha_pinctrl_func *func;
-
-- func = &airoha_pinctrl_funcs[i];
-+ func = &data->funcs[i];
- err = pinmux_generic_add_function(pinctrl->ctrl,
- func->desc.func.name,
- func->desc.func.groups,
-@@ -2925,6 +2959,10 @@ static int airoha_pinctrl_probe(struct p
- }
- }
-
-+ pinctrl->grps = data->grps;
-+ pinctrl->funcs = data->funcs;
-+ pinctrl->confs_info = data->confs_info;
-+
- err = pinctrl_enable(pinctrl->ctrl);
- if (err)
- return err;
-@@ -2933,8 +2971,39 @@ static int airoha_pinctrl_probe(struct p
- return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
- }
-
-+static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
-+ .pins = en7581_pinctrl_pins,
-+ .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
-+ .grps = en7581_pinctrl_groups,
-+ .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
-+ .funcs = en7581_pinctrl_funcs,
-+ .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
-+ .confs_info = {
-+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
-+ .confs = en7581_pinctrl_pullup_conf,
-+ .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
-+ },
-+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
-+ .confs = en7581_pinctrl_pulldown_conf,
-+ .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
-+ },
-+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
-+ .confs = en7581_pinctrl_drive_e2_conf,
-+ .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
-+ },
-+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
-+ .confs = en7581_pinctrl_drive_e4_conf,
-+ .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
-+ },
-+ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
-+ .confs = en7581_pinctrl_pcie_rst_od_conf,
-+ .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
-+ },
-+ },
-+};
-+
- static const struct of_device_id airoha_pinctrl_of_match[] = {
-- { .compatible = "airoha,en7581-pinctrl" },
-+ { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
- { /* sentinel */ }
- };
- MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+++ /dev/null
-From ee980d96b6ecd385691f101e641f3e15513ce8c3 Mon Sep 17 00:00:00 2001
-Date: Sun, 25 May 2025 20:28:34 +0200
-Subject: [PATCH 3/5] pinctrl: airoha: convert PHY LED GPIO to macro
-
-PHY LED GPIO pinctrl struct definition is very similar across the
-different 4 PHY and 2 LED and it can be generelized to a macro.
-
-To reduce code size, convert them to a common macro.
-
----
- drivers/pinctrl/mediatek/pinctrl-airoha.c | 570 ++++------------------
- 1 file changed, 82 insertions(+), 488 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -1478,516 +1478,110 @@ static const struct airoha_pinctrl_func_
- },
- };
-
-+#define AIROHA_PINCTRL_PHY_LED(gpio, mux_val, map_mask, map_val) \
-+ { \
-+ .name = (gpio), \
-+ .regmap[0] = { \
-+ AIROHA_FUNC_MUX, \
-+ REG_GPIO_2ND_I2C_MODE, \
-+ (mux_val), \
-+ (mux_val), \
-+ }, \
-+ .regmap[1] = { \
-+ AIROHA_FUNC_MUX, \
-+ REG_LAN_LED0_MAPPING, \
-+ (map_mask), \
-+ (map_val), \
-+ }, \
-+ .regmap_size = 2, \
-+ }
-+
- static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
-- {
-- .name = "gpio33",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN0_LED0_MODE_MASK,
-- GPIO_LAN0_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN0_LED_MAPPING_MASK,
-- LAN0_PHY_LED_MAP(0)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio34",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN1_LED0_MODE_MASK,
-- GPIO_LAN1_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN1_LED_MAPPING_MASK,
-- LAN1_PHY_LED_MAP(0)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio35",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN2_LED0_MODE_MASK,
-- GPIO_LAN2_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN2_LED_MAPPING_MASK,
-- LAN2_PHY_LED_MAP(0)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio42",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN3_LED0_MODE_MASK,
-- GPIO_LAN3_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN3_LED_MAPPING_MASK,
-- LAN3_PHY_LED_MAP(0)
-- },
-- .regmap_size = 2,
-- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
- };
-
- static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
-- {
-- .name = "gpio33",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN0_LED0_MODE_MASK,
-- GPIO_LAN0_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN0_LED_MAPPING_MASK,
-- LAN0_PHY_LED_MAP(1)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio34",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN1_LED0_MODE_MASK,
-- GPIO_LAN1_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN1_LED_MAPPING_MASK,
-- LAN1_PHY_LED_MAP(1)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio35",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN2_LED0_MODE_MASK,
-- GPIO_LAN2_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN2_LED_MAPPING_MASK,
-- LAN2_PHY_LED_MAP(1)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio42",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN3_LED0_MODE_MASK,
-- GPIO_LAN3_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN3_LED_MAPPING_MASK,
-- LAN3_PHY_LED_MAP(1)
-- },
-- .regmap_size = 2,
-- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
- };
-
- static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
-- {
-- .name = "gpio33",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN0_LED0_MODE_MASK,
-- GPIO_LAN0_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN0_LED_MAPPING_MASK,
-- LAN0_PHY_LED_MAP(2)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio34",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN1_LED0_MODE_MASK,
-- GPIO_LAN1_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN1_LED_MAPPING_MASK,
-- LAN1_PHY_LED_MAP(2)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio35",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN2_LED0_MODE_MASK,
-- GPIO_LAN2_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN2_LED_MAPPING_MASK,
-- LAN2_PHY_LED_MAP(2)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio42",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN3_LED0_MODE_MASK,
-- GPIO_LAN3_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN3_LED_MAPPING_MASK,
-- LAN3_PHY_LED_MAP(2)
-- },
-- .regmap_size = 2,
-- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
- };
-
- static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
-- {
-- .name = "gpio33",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN0_LED0_MODE_MASK,
-- GPIO_LAN0_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN0_LED_MAPPING_MASK,
-- LAN0_PHY_LED_MAP(3)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio34",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN1_LED0_MODE_MASK,
-- GPIO_LAN1_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN1_LED_MAPPING_MASK,
-- LAN1_PHY_LED_MAP(3)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio35",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN2_LED0_MODE_MASK,
-- GPIO_LAN2_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN2_LED_MAPPING_MASK,
-- LAN2_PHY_LED_MAP(3)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio42",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN3_LED0_MODE_MASK,
-- GPIO_LAN3_LED0_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED0_MAPPING,
-- LAN3_LED_MAPPING_MASK,
-- LAN3_PHY_LED_MAP(3)
-- },
-- .regmap_size = 2,
-- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
- };
-
- static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
-- {
-- .name = "gpio43",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN0_LED1_MODE_MASK,
-- GPIO_LAN0_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN0_LED_MAPPING_MASK,
-- LAN0_PHY_LED_MAP(0)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio44",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN1_LED1_MODE_MASK,
-- GPIO_LAN1_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN1_LED_MAPPING_MASK,
-- LAN1_PHY_LED_MAP(0)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio45",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN2_LED1_MODE_MASK,
-- GPIO_LAN2_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN2_LED_MAPPING_MASK,
-- LAN2_PHY_LED_MAP(0)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio46",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN3_LED1_MODE_MASK,
-- GPIO_LAN3_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN3_LED_MAPPING_MASK,
-- LAN3_PHY_LED_MAP(0)
-- },
-- .regmap_size = 2,
-- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
- };
-
- static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
-- {
-- .name = "gpio43",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN0_LED1_MODE_MASK,
-- GPIO_LAN0_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN0_LED_MAPPING_MASK,
-- LAN0_PHY_LED_MAP(1)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio44",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN1_LED1_MODE_MASK,
-- GPIO_LAN1_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN1_LED_MAPPING_MASK,
-- LAN1_PHY_LED_MAP(1)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio45",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN2_LED1_MODE_MASK,
-- GPIO_LAN2_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN2_LED_MAPPING_MASK,
-- LAN2_PHY_LED_MAP(1)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio46",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN3_LED1_MODE_MASK,
-- GPIO_LAN3_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN3_LED_MAPPING_MASK,
-- LAN3_PHY_LED_MAP(1)
-- },
-- .regmap_size = 2,
-- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
- };
-
- static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
-- {
-- .name = "gpio43",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN0_LED1_MODE_MASK,
-- GPIO_LAN0_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN0_LED_MAPPING_MASK,
-- LAN0_PHY_LED_MAP(2)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio44",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN1_LED1_MODE_MASK,
-- GPIO_LAN1_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN1_LED_MAPPING_MASK,
-- LAN1_PHY_LED_MAP(2)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio45",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN2_LED1_MODE_MASK,
-- GPIO_LAN2_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN2_LED_MAPPING_MASK,
-- LAN2_PHY_LED_MAP(2)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio46",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN3_LED1_MODE_MASK,
-- GPIO_LAN3_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN3_LED_MAPPING_MASK,
-- LAN3_PHY_LED_MAP(2)
-- },
-- .regmap_size = 2,
-- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
- };
-
- static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
-- {
-- .name = "gpio43",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN0_LED1_MODE_MASK,
-- GPIO_LAN0_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN0_LED_MAPPING_MASK,
-- LAN0_PHY_LED_MAP(3)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio44",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN1_LED1_MODE_MASK,
-- GPIO_LAN1_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN1_LED_MAPPING_MASK,
-- LAN1_PHY_LED_MAP(3)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio45",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN2_LED1_MODE_MASK,
-- GPIO_LAN2_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN2_LED_MAPPING_MASK,
-- LAN2_PHY_LED_MAP(3)
-- },
-- .regmap_size = 2,
-- }, {
-- .name = "gpio46",
-- .regmap[0] = {
-- AIROHA_FUNC_MUX,
-- REG_GPIO_2ND_I2C_MODE,
-- GPIO_LAN3_LED1_MODE_MASK,
-- GPIO_LAN3_LED1_MODE_MASK
-- },
-- .regmap[1] = {
-- AIROHA_FUNC_MUX,
-- REG_LAN_LED1_MAPPING,
-- LAN3_LED_MAPPING_MASK,
-- LAN3_PHY_LED_MAP(3)
-- },
-- .regmap_size = 2,
-- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
- };
-
- static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+++ /dev/null
-From 83c79d127c610063e1b86c3f7f8d5e0145ffe9c6 Mon Sep 17 00:00:00 2001
-Date: Sun, 25 May 2025 20:43:47 +0200
-Subject: [PATCH 4/5] pinctrl: airoha: convert PWM GPIO to macro
-
-The PWM GPIO struct definition follow the same pattern for every GPIO
-pin hence it can be converted to a macro.
-
-Create 2 macro one for normal mux and one for ext mux and convert all
-the entry to these new macro to reduce code size.
-
----
- drivers/pinctrl/mediatek/pinctrl-airoha.c | 465 ++++------------------
- 1 file changed, 68 insertions(+), 397 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -1078,404 +1078,75 @@ static const struct airoha_pinctrl_func_
- };
-
- /* PWM */
-+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
-+ { \
-+ .name = (gpio), \
-+ .regmap[0] = { \
-+ AIROHA_FUNC_PWM_MUX, \
-+ REG_GPIO_FLASH_MODE_CFG, \
-+ (mux_val), \
-+ (mux_val) \
-+ }, \
-+ .regmap_size = 1, \
-+ } \
-+
-+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
-+ { \
-+ .name = (gpio), \
-+ .regmap[0] = { \
-+ AIROHA_FUNC_PWM_EXT_MUX, \
-+ REG_GPIO_FLASH_MODE_CFG_EXT, \
-+ (mux_val), \
-+ (mux_val) \
-+ }, \
-+ .regmap_size = 1, \
-+ } \
-+
- static const struct airoha_pinctrl_func_group pwm_func_group[] = {
-- {
-- .name = "gpio0",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO0_FLASH_MODE_CFG,
-- GPIO0_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio1",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO1_FLASH_MODE_CFG,
-- GPIO1_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio2",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO2_FLASH_MODE_CFG,
-- GPIO2_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio3",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO3_FLASH_MODE_CFG,
-- GPIO3_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio4",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO4_FLASH_MODE_CFG,
-- GPIO4_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio5",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO5_FLASH_MODE_CFG,
-- GPIO5_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio6",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO6_FLASH_MODE_CFG,
-- GPIO6_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio7",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO7_FLASH_MODE_CFG,
-- GPIO7_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio8",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO8_FLASH_MODE_CFG,
-- GPIO8_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio9",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO9_FLASH_MODE_CFG,
-- GPIO9_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio10",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO10_FLASH_MODE_CFG,
-- GPIO10_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio11",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO11_FLASH_MODE_CFG,
-- GPIO11_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio12",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO12_FLASH_MODE_CFG,
-- GPIO12_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio13",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO13_FLASH_MODE_CFG,
-- GPIO13_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio14",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO14_FLASH_MODE_CFG,
-- GPIO14_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio15",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_MUX,
-- REG_GPIO_FLASH_MODE_CFG,
-- GPIO15_FLASH_MODE_CFG,
-- GPIO15_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio16",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO16_FLASH_MODE_CFG,
-- GPIO16_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio17",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO17_FLASH_MODE_CFG,
-- GPIO17_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio18",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO18_FLASH_MODE_CFG,
-- GPIO18_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio19",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO19_FLASH_MODE_CFG,
-- GPIO19_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio20",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO20_FLASH_MODE_CFG,
-- GPIO20_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio21",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO21_FLASH_MODE_CFG,
-- GPIO21_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio22",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO22_FLASH_MODE_CFG,
-- GPIO22_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio23",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO23_FLASH_MODE_CFG,
-- GPIO23_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio24",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO24_FLASH_MODE_CFG,
-- GPIO24_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio25",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO25_FLASH_MODE_CFG,
-- GPIO25_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio26",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO26_FLASH_MODE_CFG,
-- GPIO26_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio27",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO27_FLASH_MODE_CFG,
-- GPIO27_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio28",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO28_FLASH_MODE_CFG,
-- GPIO28_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio29",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO29_FLASH_MODE_CFG,
-- GPIO29_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio30",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO30_FLASH_MODE_CFG,
-- GPIO30_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio31",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO31_FLASH_MODE_CFG,
-- GPIO31_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio36",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO36_FLASH_MODE_CFG,
-- GPIO36_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio37",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO37_FLASH_MODE_CFG,
-- GPIO37_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio38",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO38_FLASH_MODE_CFG,
-- GPIO38_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio39",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO39_FLASH_MODE_CFG,
-- GPIO39_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio40",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO40_FLASH_MODE_CFG,
-- GPIO40_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio41",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO41_FLASH_MODE_CFG,
-- GPIO41_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio42",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO42_FLASH_MODE_CFG,
-- GPIO42_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio43",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO43_FLASH_MODE_CFG,
-- GPIO43_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio44",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO44_FLASH_MODE_CFG,
-- GPIO44_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio45",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO45_FLASH_MODE_CFG,
-- GPIO45_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio46",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO46_FLASH_MODE_CFG,
-- GPIO46_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- }, {
-- .name = "gpio47",
-- .regmap[0] = {
-- AIROHA_FUNC_PWM_EXT_MUX,
-- REG_GPIO_FLASH_MODE_CFG_EXT,
-- GPIO47_FLASH_MODE_CFG,
-- GPIO47_FLASH_MODE_CFG
-- },
-- .regmap_size = 1,
-- },
-+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
-+ AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),
- };
-
- #define AIROHA_PINCTRL_PHY_LED(gpio, mux_val, map_mask, map_val) \
+++ /dev/null
-From cc92581b44cc3a6821c540ddbe27d4c009a7d312 Mon Sep 17 00:00:00 2001
-Date: Sun, 25 May 2025 21:32:25 +0200
-Subject: [PATCH 5/5] pinctrl: airoha: add support for Airoha AN7583 PINs
-
-Add all the required entry to add suppot for Airoha AN7583 PINs.
-
-Where possible the same function group are used from Airoha EN7581 to
-reduce code duplication.
-
----
- drivers/pinctrl/mediatek/pinctrl-airoha.c | 733 ++++++++++++++++++++++
- 1 file changed, 733 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -75,6 +75,7 @@
- #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
- #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
- #define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
-+#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
- #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
- #define GPIO_PCM_SPI_MODE_MASK BIT(16)
- #define GPIO_PCM2_MODE_MASK BIT(13)
-@@ -132,6 +133,8 @@
-
- /* CONF */
- #define REG_I2C_SDA_E2 0x001c
-+#define AN7583_I2C1_SCL_E2_MASK BIT(16)
-+#define AN7583_I2C1_SDA_E2_MASK BIT(15)
- #define SPI_MISO_E2_MASK BIT(14)
- #define SPI_MOSI_E2_MASK BIT(13)
- #define SPI_CLK_E2_MASK BIT(12)
-@@ -139,12 +142,16 @@
- #define PCIE2_RESET_E2_MASK BIT(10)
- #define PCIE1_RESET_E2_MASK BIT(9)
- #define PCIE0_RESET_E2_MASK BIT(8)
-+#define AN7583_MDIO_0_E2_MASK BIT(5)
-+#define AN7583_MDC_0_E2_MASK BIT(4)
- #define UART1_RXD_E2_MASK BIT(3)
- #define UART1_TXD_E2_MASK BIT(2)
- #define I2C_SCL_E2_MASK BIT(1)
- #define I2C_SDA_E2_MASK BIT(0)
-
- #define REG_I2C_SDA_E4 0x0020
-+#define AN7583_I2C1_SCL_E4_MASK BIT(16)
-+#define AN7583_I2C1_SDA_E4_MASK BIT(15)
- #define SPI_MISO_E4_MASK BIT(14)
- #define SPI_MOSI_E4_MASK BIT(13)
- #define SPI_CLK_E4_MASK BIT(12)
-@@ -152,6 +159,8 @@
- #define PCIE2_RESET_E4_MASK BIT(10)
- #define PCIE1_RESET_E4_MASK BIT(9)
- #define PCIE0_RESET_E4_MASK BIT(8)
-+#define AN7583_MDIO_0_E4_MASK BIT(5)
-+#define AN7583_MDC_0_E4_MASK BIT(4)
- #define UART1_RXD_E4_MASK BIT(3)
- #define UART1_TXD_E4_MASK BIT(2)
- #define I2C_SCL_E4_MASK BIT(1)
-@@ -163,6 +172,8 @@
- #define REG_GPIO_H_E4 0x0030
-
- #define REG_I2C_SDA_PU 0x0044
-+#define AN7583_I2C1_SCL_PU_MASK BIT(16)
-+#define AN7583_I2C1_SDA_PU_MASK BIT(15)
- #define SPI_MISO_PU_MASK BIT(14)
- #define SPI_MOSI_PU_MASK BIT(13)
- #define SPI_CLK_PU_MASK BIT(12)
-@@ -170,12 +181,16 @@
- #define PCIE2_RESET_PU_MASK BIT(10)
- #define PCIE1_RESET_PU_MASK BIT(9)
- #define PCIE0_RESET_PU_MASK BIT(8)
-+#define AN7583_MDIO_0_PU_MASK BIT(5)
-+#define AN7583_MDC_0_PU_MASK BIT(4)
- #define UART1_RXD_PU_MASK BIT(3)
- #define UART1_TXD_PU_MASK BIT(2)
- #define I2C_SCL_PU_MASK BIT(1)
- #define I2C_SDA_PU_MASK BIT(0)
-
- #define REG_I2C_SDA_PD 0x0048
-+#define AN7583_I2C1_SDA_PD_MASK BIT(16)
-+#define AN7583_I2C1_SCL_PD_MASK BIT(15)
- #define SPI_MISO_PD_MASK BIT(14)
- #define SPI_MOSI_PD_MASK BIT(13)
- #define SPI_CLK_PD_MASK BIT(12)
-@@ -183,6 +198,8 @@
- #define PCIE2_RESET_PD_MASK BIT(10)
- #define PCIE1_RESET_PD_MASK BIT(9)
- #define PCIE0_RESET_PD_MASK BIT(8)
-+#define AN7583_MDIO_0_PD_MASK BIT(5)
-+#define AN7583_MDC_0_PD_MASK BIT(4)
- #define UART1_RXD_PD_MASK BIT(3)
- #define UART1_TXD_PD_MASK BIT(2)
- #define I2C_SCL_PD_MASK BIT(1)
-@@ -630,10 +647,223 @@ static const struct pingroup en7581_pinc
- PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
- };
-
-+static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
-+ PINCTRL_PIN(2, "gpio0"),
-+ PINCTRL_PIN(3, "gpio1"),
-+ PINCTRL_PIN(4, "gpio2"),
-+ PINCTRL_PIN(5, "gpio3"),
-+ PINCTRL_PIN(6, "gpio4"),
-+ PINCTRL_PIN(7, "gpio5"),
-+ PINCTRL_PIN(8, "gpio6"),
-+ PINCTRL_PIN(9, "gpio7"),
-+ PINCTRL_PIN(10, "gpio8"),
-+ PINCTRL_PIN(11, "gpio9"),
-+ PINCTRL_PIN(12, "gpio10"),
-+ PINCTRL_PIN(13, "gpio11"),
-+ PINCTRL_PIN(14, "gpio12"),
-+ PINCTRL_PIN(15, "gpio13"),
-+ PINCTRL_PIN(16, "gpio14"),
-+ PINCTRL_PIN(17, "gpio15"),
-+ PINCTRL_PIN(18, "gpio16"),
-+ PINCTRL_PIN(19, "gpio17"),
-+ PINCTRL_PIN(20, "gpio18"),
-+ PINCTRL_PIN(21, "gpio19"),
-+ PINCTRL_PIN(22, "gpio20"),
-+ PINCTRL_PIN(23, "gpio21"),
-+ PINCTRL_PIN(24, "gpio22"),
-+ PINCTRL_PIN(25, "gpio23"),
-+ PINCTRL_PIN(26, "gpio24"),
-+ PINCTRL_PIN(27, "gpio25"),
-+ PINCTRL_PIN(28, "gpio26"),
-+ PINCTRL_PIN(29, "gpio27"),
-+ PINCTRL_PIN(30, "gpio28"),
-+ PINCTRL_PIN(31, "gpio29"),
-+ PINCTRL_PIN(32, "gpio30"),
-+ PINCTRL_PIN(33, "gpio31"),
-+ PINCTRL_PIN(34, "gpio32"),
-+ PINCTRL_PIN(35, "gpio33"),
-+ PINCTRL_PIN(36, "gpio34"),
-+ PINCTRL_PIN(37, "gpio35"),
-+ PINCTRL_PIN(38, "gpio36"),
-+ PINCTRL_PIN(39, "gpio37"),
-+ PINCTRL_PIN(40, "gpio38"),
-+ PINCTRL_PIN(41, "i2c0_scl"),
-+ PINCTRL_PIN(42, "i2c0_sda"),
-+ PINCTRL_PIN(43, "i2c1_scl"),
-+ PINCTRL_PIN(44, "i2c1_sda"),
-+ PINCTRL_PIN(45, "spi_clk"),
-+ PINCTRL_PIN(46, "spi_cs"),
-+ PINCTRL_PIN(47, "spi_mosi"),
-+ PINCTRL_PIN(48, "spi_miso"),
-+ PINCTRL_PIN(49, "uart_txd"),
-+ PINCTRL_PIN(50, "uart_rxd"),
-+ PINCTRL_PIN(51, "pcie_reset0"),
-+ PINCTRL_PIN(52, "pcie_reset1"),
-+ PINCTRL_PIN(53, "mdc_0"),
-+ PINCTRL_PIN(54, "mdio_0"),
-+};
-+
-+static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
-+static const int an7583_pon_tod_1pps_pins[] = { 32 };
-+static const int an7583_gsw_tod_1pps_pins[] = { 32 };
-+static const int an7583_sipo_pins[] = { 34, 35 };
-+static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
-+static const int an7583_mdio_pins[] = { 43, 44 };
-+static const int an7583_uart2_pins[] = { 34, 35 };
-+static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
-+static const int an7583_hsuart_pins[] = { 30, 31 };
-+static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
-+static const int an7583_npu_uart_pins[] = { 7, 8 };
-+static const int an7583_uart4_pins[] = { 7, 8 };
-+static const int an7583_uart5_pins[] = { 23, 24 };
-+static const int an7583_i2c0_pins[] = { 41, 42 };
-+static const int an7583_i2c1_pins[] = { 43, 44 };
-+static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
-+static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
-+static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
-+static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
-+static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
-+static const int an7583_spi_quad_pins[] = { 25, 26 };
-+static const int an7583_spi_cs1_pins[] = { 27 };
-+static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
-+static const int an7583_pcm_spi_rst_pins[] = { 14 };
-+static const int an7583_pcm_spi_cs1_pins[] = { 24 };
-+static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
-+static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
-+static const int an7583_gpio0_pins[] = { 2 };
-+static const int an7583_gpio1_pins[] = { 3 };
-+static const int an7583_gpio2_pins[] = { 4 };
-+static const int an7583_gpio3_pins[] = { 5 };
-+static const int an7583_gpio4_pins[] = { 6 };
-+static const int an7583_gpio5_pins[] = { 7 };
-+static const int an7583_gpio6_pins[] = { 8 };
-+static const int an7583_gpio7_pins[] = { 9 };
-+static const int an7583_gpio8_pins[] = { 10 };
-+static const int an7583_gpio9_pins[] = { 11 };
-+static const int an7583_gpio10_pins[] = { 12 };
-+static const int an7583_gpio11_pins[] = { 13 };
-+static const int an7583_gpio12_pins[] = { 14 };
-+static const int an7583_gpio13_pins[] = { 15 };
-+static const int an7583_gpio14_pins[] = { 16 };
-+static const int an7583_gpio15_pins[] = { 17 };
-+static const int an7583_gpio16_pins[] = { 18 };
-+static const int an7583_gpio17_pins[] = { 19 };
-+static const int an7583_gpio18_pins[] = { 20 };
-+static const int an7583_gpio19_pins[] = { 21 };
-+static const int an7583_gpio20_pins[] = { 22 };
-+static const int an7583_gpio21_pins[] = { 24 };
-+static const int an7583_gpio23_pins[] = { 25 };
-+static const int an7583_gpio24_pins[] = { 26 };
-+static const int an7583_gpio25_pins[] = { 27 };
-+static const int an7583_gpio26_pins[] = { 28 };
-+static const int an7583_gpio27_pins[] = { 29 };
-+static const int an7583_gpio28_pins[] = { 30 };
-+static const int an7583_gpio29_pins[] = { 31 };
-+static const int an7583_gpio30_pins[] = { 32 };
-+static const int an7583_gpio31_pins[] = { 33 };
-+static const int an7583_gpio33_pins[] = { 35 };
-+static const int an7583_gpio34_pins[] = { 36 };
-+static const int an7583_gpio35_pins[] = { 37 };
-+static const int an7583_gpio36_pins[] = { 38 };
-+static const int an7583_gpio37_pins[] = { 39 };
-+static const int an7583_gpio38_pins[] = { 40 };
-+static const int an7583_gpio39_pins[] = { 41 };
-+static const int an7583_gpio40_pins[] = { 42 };
-+static const int an7583_gpio41_pins[] = { 43 };
-+static const int an7583_gpio42_pins[] = { 44 };
-+static const int an7583_gpio43_pins[] = { 45 };
-+static const int an7583_gpio44_pins[] = { 46 };
-+static const int an7583_gpio45_pins[] = { 47 };
-+static const int an7583_gpio46_pins[] = { 48 };
-+static const int an7583_gpio47_pins[] = { 49 };
-+static const int an7583_gpio48_pins[] = { 50 };
-+static const int an7583_pcie_reset0_pins[] = { 51 };
-+static const int an7583_pcie_reset1_pins[] = { 52 };
-+
-+static const struct pingroup an7583_pinctrl_groups[] = {
-+ PINCTRL_PIN_GROUP("pon", an7583_pon),
-+ PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
-+ PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
-+ PINCTRL_PIN_GROUP("sipo", an7583_sipo),
-+ PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
-+ PINCTRL_PIN_GROUP("mdio", an7583_mdio),
-+ PINCTRL_PIN_GROUP("uart2", an7583_uart2),
-+ PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
-+ PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
-+ PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
-+ PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
-+ PINCTRL_PIN_GROUP("uart4", an7583_uart4),
-+ PINCTRL_PIN_GROUP("uart5", an7583_uart5),
-+ PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
-+ PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
-+ PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
-+ PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
-+ PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
-+ PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
-+ PINCTRL_PIN_GROUP("spi", an7583_spi),
-+ PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
-+ PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
-+ PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
-+ PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
-+ PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
-+ PINCTRL_PIN_GROUP("emmc", an7583_emmc),
-+ PINCTRL_PIN_GROUP("pnand", an7583_pnand),
-+ PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
-+ PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
-+ PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
-+ PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
-+ PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
-+ PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
-+ PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
-+ PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
-+ PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
-+ PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
-+ PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
-+ PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
-+ PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
-+ PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
-+ PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
-+ PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
-+ PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
-+ PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
-+ PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
-+ PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
-+ PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
-+ PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
-+ PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
-+ PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
-+ PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
-+ PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
-+ PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
-+ PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
-+ PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
-+ PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
-+ PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
-+ PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
-+ PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
-+ PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
-+ PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
-+ PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
-+ PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
-+ PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
-+ PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
-+ PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
-+ PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
-+ PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
-+ PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
-+ PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
-+ PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
-+ PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
-+ PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
-+ PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
-+ PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
-+};
-+
- static const char *const pon_groups[] = { "pon" };
- static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
- static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
- static const char *const mdio_groups[] = { "mdio" };
-+static const char *const an7583_mdio_groups[] = { "mdio" };
- static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
- "hsuart_cts_rts", "uart4",
- "uart5" };
-@@ -646,11 +876,16 @@ static const char *const pcm_spi_groups[
- "pcm_spi_cs2_p156",
- "pcm_spi_cs2_p128",
- "pcm_spi_cs3", "pcm_spi_cs4" };
-+static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
-+ "pcm_spi_rst", "pcm_spi_cs1",
-+ "pcm_spi_cs2", "pcm_spi_cs3",
-+ "pcm_spi_cs4" };
- static const char *const i2s_groups[] = { "i2s" };
- static const char *const emmc_groups[] = { "emmc" };
- static const char *const pnand_groups[] = { "pnand" };
- static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
- "pcie_reset2" };
-+static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
- static const char *const pwm_groups[] = { "gpio0", "gpio1",
- "gpio2", "gpio3",
- "gpio4", "gpio5",
-@@ -689,6 +924,22 @@ static const char *const phy3_led1_group
- "gpio45", "gpio46" };
- static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
- "gpio45", "gpio46" };
-+static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
-+ "gpio3", "gpio4" };
-+static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
-+ "gpio3", "gpio4" };
-+static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
-+ "gpio3", "gpio4" };
-+static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
-+ "gpio3", "gpio4" };
-+static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
-+ "gpio10", "gpio11" };
-+static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
-+ "gpio10", "gpio11" };
-+static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
-+ "gpio10", "gpio11" };
-+static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
-+ "gpio10", "gpio11" };
-
- static const struct airoha_pinctrl_func_group pon_func_group[] = {
- {
-@@ -766,6 +1017,25 @@ static const struct airoha_pinctrl_func_
- },
- };
-
-+static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
-+ {
-+ .name = "mdio",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_PON_MODE,
-+ GPIO_SGMII_MDIO_MODE_MASK,
-+ GPIO_SGMII_MDIO_MODE_MASK
-+ },
-+ .regmap[1] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_SPI_CS1_MODE,
-+ GPIO_MDC_IO_MASTER_MODE_MODE,
-+ GPIO_MDC_IO_MASTER_MODE_MODE
-+ },
-+ .regmap_size = 2,
-+ },
-+};
-+
- static const struct airoha_pinctrl_func_group uart_func_group[] = {
- {
- .name = "uart2",
-@@ -1007,6 +1277,73 @@ static const struct airoha_pinctrl_func_
- },
- };
-
-+static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
-+ {
-+ .name = "pcm_spi",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_SPI_CS1_MODE,
-+ GPIO_PCM_SPI_MODE_MASK,
-+ GPIO_PCM_SPI_MODE_MASK
-+ },
-+ .regmap_size = 1,
-+ }, {
-+ .name = "pcm_spi_int",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_SPI_CS1_MODE,
-+ GPIO_PCM_INT_MODE_MASK,
-+ GPIO_PCM_INT_MODE_MASK
-+ },
-+ .regmap_size = 1,
-+ }, {
-+ .name = "pcm_spi_rst",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_SPI_CS1_MODE,
-+ GPIO_PCM_RESET_MODE_MASK,
-+ GPIO_PCM_RESET_MODE_MASK
-+ },
-+ .regmap_size = 1,
-+ }, {
-+ .name = "pcm_spi_cs1",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_SPI_CS1_MODE,
-+ GPIO_PCM_SPI_CS1_MODE_MASK,
-+ GPIO_PCM_SPI_CS1_MODE_MASK
-+ },
-+ .regmap_size = 1,
-+ }, {
-+ .name = "pcm_spi_cs2",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_SPI_CS1_MODE,
-+ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
-+ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
-+ },
-+ .regmap_size = 1,
-+ }, {
-+ .name = "pcm_spi_cs3",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_SPI_CS1_MODE,
-+ GPIO_PCM_SPI_CS3_MODE_MASK,
-+ GPIO_PCM_SPI_CS3_MODE_MASK
-+ },
-+ .regmap_size = 1,
-+ }, {
-+ .name = "pcm_spi_cs4",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_SPI_CS1_MODE,
-+ GPIO_PCM_SPI_CS4_MODE_MASK,
-+ GPIO_PCM_SPI_CS4_MODE_MASK
-+ },
-+ .regmap_size = 1,
-+ },
-+};
-+
- static const struct airoha_pinctrl_func_group i2s_func_group[] = {
- {
- .name = "i2s",
-@@ -1077,6 +1414,28 @@ static const struct airoha_pinctrl_func_
- },
- };
-
-+static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
-+ {
-+ .name = "pcie_reset0",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_PON_MODE,
-+ GPIO_PCIE_RESET0_MASK,
-+ GPIO_PCIE_RESET0_MASK
-+ },
-+ .regmap_size = 1,
-+ }, {
-+ .name = "pcie_reset1",
-+ .regmap[0] = {
-+ AIROHA_FUNC_MUX,
-+ REG_GPIO_PON_MODE,
-+ GPIO_PCIE_RESET1_MASK,
-+ GPIO_PCIE_RESET1_MASK
-+ },
-+ .regmap_size = 1,
-+ },
-+};
-+
- /* PWM */
- #define AIROHA_PINCTRL_PWM(gpio, mux_val) \
- { \
-@@ -1255,6 +1614,94 @@ static const struct airoha_pinctrl_func_
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
- };
-
-+static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-+};
-+
-+static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-+};
-+
-+static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-+};
-+
-+static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-+};
-+
-+static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-+};
-+
-+static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-+};
-+
-+static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-+};
-+
-+static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-+};
-+
- static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
- PINCTRL_FUNC_DESC("pon", pon),
- PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
-@@ -1281,6 +1728,31 @@ static const struct airoha_pinctrl_func
- PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
- };
-
-+static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
-+ PINCTRL_FUNC_DESC("pon", pon),
-+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
-+ PINCTRL_FUNC_DESC("sipo", sipo),
-+ PINCTRL_FUNC_DESC("mdio", an7583_mdio),
-+ PINCTRL_FUNC_DESC("uart", uart),
-+ PINCTRL_FUNC_DESC("i2c", i2c),
-+ PINCTRL_FUNC_DESC("jtag", jtag),
-+ PINCTRL_FUNC_DESC("pcm", pcm),
-+ PINCTRL_FUNC_DESC("spi", spi),
-+ PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
-+ PINCTRL_FUNC_DESC("emmc", emmc),
-+ PINCTRL_FUNC_DESC("pnand", pnand),
-+ PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
-+ PINCTRL_FUNC_DESC("pwm", pwm),
-+ PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
-+ PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
-+ PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
-+ PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
-+ PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
-+ PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
-+ PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
-+ PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
-+};
-+
- static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
-@@ -1342,6 +1814,62 @@ static const struct airoha_pinctrl_conf
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
- };
-
-+static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
-+ PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
-+ PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
-+ PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
-+ PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
-+ PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
-+ PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
-+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
-+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
-+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
-+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
-+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
-+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
-+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
-+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
-+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
-+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
-+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
-+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
-+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
-+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)),
-+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
-+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
-+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
-+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
-+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
-+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
-+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
-+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
-+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
-+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
-+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
-+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
-+ PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
-+ PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
-+ PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
-+ PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
-+ PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
-+ PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
-+ PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
-+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
-+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
-+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
-+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
-+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
-+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
-+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
-+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
-+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
-+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
-+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
-+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
-+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
-+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
-+};
-+
- static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
-@@ -1403,6 +1931,62 @@ static const struct airoha_pinctrl_conf
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
- };
-
-+static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
-+ PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
-+ PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
-+ PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
-+ PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
-+ PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
-+ PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
-+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
-+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
-+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
-+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
-+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
-+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
-+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
-+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
-+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
-+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
-+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
-+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
-+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
-+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)),
-+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
-+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
-+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
-+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
-+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
-+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
-+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
-+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
-+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
-+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
-+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
-+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
-+ PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
-+ PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
-+ PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
-+ PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
-+ PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
-+ PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
-+ PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
-+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
-+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
-+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
-+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
-+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
-+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
-+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
-+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
-+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
-+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
-+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
-+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
-+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
-+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
-+};
-+
- static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
-@@ -1464,6 +2048,62 @@ static const struct airoha_pinctrl_conf
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
- };
-
-+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
-+ PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
-+ PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
-+ PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
-+ PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
-+ PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
-+ PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
-+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
-+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
-+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
-+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
-+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
-+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
-+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
-+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
-+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
-+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
-+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
-+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
-+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
-+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)),
-+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
-+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
-+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
-+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
-+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
-+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
-+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
-+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
-+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
-+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
-+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
-+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
-+ PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
-+ PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
-+ PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
-+ PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
-+ PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
-+ PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
-+ PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
-+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
-+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
-+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
-+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
-+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
-+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
-+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
-+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
-+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
-+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
-+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
-+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
-+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
-+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
-+};
-+
- static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
-@@ -1525,12 +2165,73 @@ static const struct airoha_pinctrl_conf
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
- };
-
-+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
-+ PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
-+ PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
-+ PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
-+ PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
-+ PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
-+ PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
-+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
-+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
-+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
-+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
-+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
-+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
-+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
-+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
-+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
-+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
-+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
-+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
-+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
-+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)),
-+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
-+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
-+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
-+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
-+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
-+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
-+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
-+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
-+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
-+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
-+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
-+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
-+ PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
-+ PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
-+ PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
-+ PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
-+ PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
-+ PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
-+ PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
-+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
-+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
-+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
-+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
-+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
-+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
-+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
-+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
-+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
-+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
-+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
-+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
-+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
-+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
-+};
-+
- static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
- PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
- PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
- PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
- };
-
-+static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
-+ PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
-+ PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
-+};
-+
- static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
- struct pinctrl_gpio_range *range,
- int pin)
-@@ -2267,8 +2968,40 @@ static const struct airoha_pinctrl_match
- },
- };
-
-+static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
-+ .pins = an7583_pinctrl_pins,
-+ .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
-+ .grps = an7583_pinctrl_groups,
-+ .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
-+ .funcs = an7583_pinctrl_funcs,
-+ .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
-+ .confs_info = {
-+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
-+ .confs = an7583_pinctrl_pullup_conf,
-+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
-+ },
-+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
-+ .confs = an7583_pinctrl_pulldown_conf,
-+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
-+ },
-+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
-+ .confs = en7581_pinctrl_drive_e2_conf,
-+ .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
-+ },
-+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
-+ .confs = an7583_pinctrl_drive_e4_conf,
-+ .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
-+ },
-+ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
-+ .confs = an7583_pinctrl_pcie_rst_od_conf,
-+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
-+ },
-+ },
-+};
-+
- static const struct of_device_id airoha_pinctrl_of_match[] = {
- { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
-+ { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
- { /* sentinel */ }
- };
- MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
projects / openwrt / staging / blocktrron.git / commitdiff