lib: cpu: Add L2 cache aux control register definition to CA72

Add definition of EL1 L2 Auxilary Control register to
Cortex A72 library headers.

Signed-off-by: Konstantin Porotchkin <[email protected]>

diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index 9f1847061ded40eefdd9610cfbca90227c9d26ab..f5ca2ee7a41b44ad6ecd1c203fdeaca7b3d5f03a 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -37,6 +37,13 @@
 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI                    (ULL(1) << 44)
 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH             (ULL(1) << 32)
 
+/*******************************************************************************
+ *  L2 Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A72_L2ACTLR_EL1                                 S3_1_C15_C0_0
+
+#define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN                 (ULL(1) << 14)
+
 /*******************************************************************************
  * L2 Control register specific definitions.
  ******************************************************************************/