drm/i915: Enable PM Interrupts target via Display Interface.

In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.

v2: Add (1<<31) mask (Ville)

v3: Add Gen check for the mask (ville)

Reviewed-by: Ville Syrjälä <[email protected]>
Signed-off-by: Deepak S <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 76fdfc2fb835cbbf31c888bfe3c7fc251fbb059b..ac90786dbb25687ccb2699d74366a9411223bd8f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5311,6 +5311,7 @@ enum punit_power_well {
 #define VLV_RCEDATA                            0xA0BC
 #define GEN6_RC6pp_THRESHOLD                   0xA0C0
 #define GEN6_PMINTRMSK                         0xA168
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP       (1<<31)
 #define VLV_PWRDWNUPCTL                                0xA294
 
 #define GEN6_PMISR                             0x44020

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c72cd421deed5fa4468d30bc788ac0c7df36f5d7..bc23ab9491247bfa0433c632f38e21bc94c629a8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3114,6 +3114,9 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
        if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
                mask |= GEN6_PM_RP_UP_EI_EXPIRED;
 
+       if (IS_GEN8(dev_priv->dev))
+               mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
        return ~mask;
 }