drm/amdgpu/gmc: use proper register for vram type on Fiji

The offset changed on Fiji.

Reviewed-by: Harish Kasiviswanathan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 2611e8533be1888c67276149f21d731c994c284e..02deb322940565baa6d1d3e3f648fe7cf152e6aa 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -873,6 +873,8 @@ static int gmc_v8_0_late_init(void *handle)
        return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 }
 
+#define mmMC_SEQ_MISC0_FIJI 0xA71
+
 static int gmc_v8_0_sw_init(void *handle)
 {
        int r;
@@ -882,7 +884,12 @@ static int gmc_v8_0_sw_init(void *handle)
        if (adev->flags & AMD_IS_APU) {
                adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
        } else {
-               u32 tmp = RREG32(mmMC_SEQ_MISC0);
+               u32 tmp;
+
+               if (adev->asic_type == CHIP_FIJI)
+                       tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
+               else
+                       tmp = RREG32(mmMC_SEQ_MISC0);
                tmp &= MC_SEQ_MISC0__MT__MASK;
                adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
        }