Update marvell platform to not rely on undefined overflow behaviour

This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57
Signed-off-by: Justin Chadwell <[email protected]>

diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c
index 3a9859c98c79af9a2fe373cc6de41644ccea0d74..06fe88e13adc2ac2a70b4bf71662578958695124 100644 (file)
--- a/drivers/marvell/mci.c
+++ b/drivers/marvell/mci.c
@@ -245,7 +245,7 @@
                                MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET)
 #define MCI_PHY_CTRL_PIDI_MODE_OFFSET                  31
 #define MCI_PHY_CTRL_PIDI_MODE                         \
-                               (1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
+                               (1U << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
 
 /* Number of times to wait for the MCI link ready after MCI configurations
  * Normally takes 34-35 successive reads

diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index d7d7373180bcf87bb26615dd41e38b61e41afa01..b4b4e0c82d66298e99e36d5b0e0fe4feeb789085 100644 (file)
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c
@@ -56,11 +56,11 @@
                                (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET    16
 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK      \
-                               (0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
+                               (0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
 
 #define MVEBU_SAMPLE_AT_RESET_REG      (0x440600)
 #define SAR_PCIE1_CLK_CFG_OFFSET       31
-#define SAR_PCIE1_CLK_CFG_MASK         (0x1 << SAR_PCIE1_CLK_CFG_OFFSET)
+#define SAR_PCIE1_CLK_CFG_MASK         (0x1u << SAR_PCIE1_CLK_CFG_OFFSET)
 #define SAR_PCIE0_CLK_CFG_OFFSET       30
 #define SAR_PCIE0_CLK_CFG_MASK         (0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
 #define SAR_I2C_INIT_EN_OFFSET         24

diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h
index 8b7cd6486e6179f5466a099ec273462d60f0a4f1..de8031536c0d2b3cd6276d14a41072a7f1c441fe 100644 (file)
--- a/plat/marvell/a8k/common/include/a8k_plat_def.h
+++ b/plat/marvell/a8k/common/include/a8k_plat_def.h
@@ -18,7 +18,7 @@
 #define GWD_IIDR2_REV_ID_OFFSET                12
 #define GWD_IIDR2_REV_ID_MASK          0xF
 #define GWD_IIDR2_CHIP_ID_OFFSET       20
-#define GWD_IIDR2_CHIP_ID_MASK         (0xFFF << GWD_IIDR2_CHIP_ID_OFFSET)
+#define GWD_IIDR2_CHIP_ID_MASK         (0xFFFu << GWD_IIDR2_CHIP_ID_OFFSET)
 
 #define CHIP_ID_AP806                  0x806
 #define CHIP_ID_AP807                  0x807

diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c
index 0590cc0aef96c5135fbeb1e5d58727a20396b2bb..7f9e242786c88a1230b22183d155d72dec635f1c 100644 (file)
--- a/plat/marvell/a8k/common/plat_ble_setup.c
+++ b/plat/marvell/a8k/common/plat_ble_setup.c
@@ -77,13 +77,13 @@
 /* VDD limit is 0.82V for all A3900 devices
  * AVS offsets are not the same as in A70x0
  */
-#define AVS_A3900_CLK_VALUE            ((0x80 << 24) | \
+#define AVS_A3900_CLK_VALUE            ((0x80u << 24) | \
                                         (0x2c2 << 13) | \
                                         (0x2c2 << 3) | \
                                         (0x1 << AVS_SOFT_RESET_OFFSET) | \
                                         (0x1 << AVS_ENABLE_OFFSET))
 /* VDD is 0.88V for 2GHz clock */
-#define AVS_A3900_HIGH_CLK_VALUE       ((0x80 << 24) | \
+#define AVS_A3900_HIGH_CLK_VALUE       ((0x80u << 24) | \
                                         (0x2f5 << 13) | \
                                         (0x2f5 << 3) | \
                                         (0x1 << AVS_SOFT_RESET_OFFSET) | \

diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c
index e2575b13c16790617bf8807b445535c69fc4b717..d07601a5f7708413bee5275214571b31f0fd98e1 100644 (file)
--- a/plat/marvell/a8k/common/plat_pm.c
+++ b/plat/marvell/a8k/common/plat_pm.c
@@ -93,7 +93,7 @@ enum CPU_ID {
 #define PWRC_CPUN_CR_ISO_ENABLE_MASK           \
                        (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)
 #define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK       \
-                       (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)
+                       (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)
 
 #define CCU_B_PRCRN_REG(cpu_id)                        \
                        (MVEBU_REGS_BASE + 0x1A50 + \
@@ -253,7 +253,7 @@ static int plat_marvell_cpu_powerup(u_register_t mpidr)
 
        /* 3. Assert power ready */
        reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
-       reg_val |= 0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET;
+       reg_val |= 0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET;
        mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);
 
        /* 4. Read & Validate power ready
@@ -262,7 +262,7 @@ static int plat_marvell_cpu_powerup(u_register_t mpidr)
        do {
                reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
                exit_loop--;
-       } while (!(reg_val & (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) &&
+       } while (!(reg_val & (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) &&
                 exit_loop > 0);
 
        if (exit_loop <= 0)