Fixup bug in PMIC TPS65217 register address definition

The addresses of the registers in TI TPS65217 are not continuous.
     There is a gap between ENABLE(0x16) and DEFUVLO(0x18). No 0x17
     register available.

     Fixup the enum values by adding a 'reserved' placeholder to correct
     the addresses higher than 0x17.

     Series-to: Heiko Schocher <[email protected]>
Signed-off-by: Brock Zheng Techyauld Ltd <[email protected]>
Reviewed-by: Lukasz Majewski <[email protected]>

diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index 69a49f76fefb372b7e6b15c2eed33d4875118292..cb07ea5ce622204988bcde2f89e091d1fdbc7b5d 100644 (file)
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -38,6 +38,7 @@ enum {
        TPS65217_DEFLS1,
        TPS65217_DEFLS2,
        TPS65217_ENABLE,
+       TPS65217_RESERVED0, /* no 0x17 register available */
        TPS65217_DEFUVLO,
        TPS65217_SEQ1,
        TPS65217_SEQ2,