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clk: tegra: Fix vic03 mux index
author
Peter De Schrijver
<
[email protected]
>
Wed, 19 Feb 2014 18:48:56 +0000
(20:48 +0200)
committer
Peter De Schrijver
<
[email protected]
>
Thu, 20 Feb 2014 08:45:28 +0000
(10:45 +0200)
The vic03 mux uses a linear mapping.
Signed-off-by: Peter De Schrijver <
[email protected]
>
drivers/clk/tegra/clk-tegra-periph.c
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diff --git
a/drivers/clk/tegra/clk-tegra-periph.c
b/drivers/clk/tegra/clk-tegra-periph.c
index f5376a3ca538a7bc8fa66a52da9910845512b71e..1fa5c3f33b2033a5e4a32716706d2221d548adf1 100644
(file)
--- a/
drivers/clk/tegra/clk-tegra-periph.c
+++ b/
drivers/clk/tegra/clk-tegra-periph.c
@@
-371,9
+371,7
@@
static const char *mux_pllp3_pllc_clkm[] = {
static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
"pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
};
-static u32 mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx[] = {
- [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
-};
+#define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",