drm/i915: Assume 400MHz cdclk for the rest of gen4-7

We don't currently have cdclk extraction code for 965g,snb,ivb.
Let's assume 400 MHz until we know better. That seems to match hints
in various vague documents. Whether that's good enough is not
entirely clear.

Signed-off-by: Ville Syrjälä <[email protected]>
Signed-off-by: Mika Kahola <[email protected]>
Acked-by: Damien Lespiau <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c43716a3ad2e1018b443e06779580e1f8510bf60..44a146b27c2fc6355f6d9b8ecd255bc71c2060b6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13506,7 +13506,8 @@ static void intel_init_display(struct drm_device *dev)
        else if (IS_GEN5(dev))
                dev_priv->display.get_display_clock_speed =
                        ilk_get_display_clock_speed;
-       else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
+       else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
+                IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
                dev_priv->display.get_display_clock_speed =
                        i945_get_display_clock_speed;
        else if (IS_I915G(dev))