ARM: Rework and correct barrier definitions

As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions.  This was causing a failure to
boot of the Linux kernel.

In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things.  First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions.  This however introduces another complexity.  Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form.  Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it.  Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier.  The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.

Reviewed-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
Acked-by: Ziyuan Xu <[email protected]>
Acked-by: Sandy Patterson <[email protected]>
Reported-by: Ziyuan Xu <[email protected]>
Reported-by: Sandy Patterson <[email protected]>
Signed-off-by: Tom Rini <[email protected]>

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6a07cd178e64109480a93cfe388e7d15ca320248..82f2fd0839d381b459487b0550908eeae12eb145 100644 (file)
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -20,6 +20,14 @@ arch-$(CONFIG_CPU_V7)                =$(call cc-option, -march=armv7-a, \
                                 $(call cc-option, -march=armv7, -march=armv5))
 arch-$(CONFIG_ARM64)           =-march=armv8-a
 
+# On Tegra systems we must build SPL for the armv4 core on the device
+# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+arch-y += -D__LINUX_ARM_ARCH__=4
+else
+arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
+endif
+
 # Evaluate arch cc-option calls now
 arch-y := $(arch-y)
 

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 52f18565db2726844a075b82e15b60a8978c16f7..c4bbcc3cc3ebd2caafbcf4035dce4e98293189e6 100644 (file)
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -75,7 +75,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
        }
 
        /* DSB to make sure the operation is complete */
-       DSB;
+       dsb();
 }
 
 /* Invalidate TLB */
@@ -88,9 +88,9 @@ static void v7_inval_tlb(void)
        /* Invalidate entire instruction TLB */
        asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
        /* Full system DSB - make sure that the invalidation is complete */
-       DSB;
+       dsb();
        /* Full system ISB - make sure the instruction stream sees it */
-       ISB;
+       isb();
 }
 
 void invalidate_dcache_all(void)
@@ -194,10 +194,10 @@ void invalidate_icache_all(void)
        asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
 
        /* Full system DSB - make sure that the invalidation is complete */
-       DSB;
+       dsb();
 
        /* ISB - make sure the instruction stream sees it */
-       ISB;
+       isb();
 }
 #else
 void invalidate_icache_all(void)

diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c
index d14b6937473f08af0e4dca8733d0c7366383eedf..8cb4107be616766c891e380b66510fd716d99216 100644 (file)
--- a/arch/arm/cpu/armv7/psci-common.c
+++ b/arch/arm/cpu/armv7/psci-common.c
@@ -29,7 +29,7 @@ static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 };
 void __secure psci_save_target_pc(int cpu, u32 pc)
 {
        psci_target_pc[cpu] = pc;
-       DSB;
+       dsb();
 }
 
 u32 __secure psci_get_target_pc(int cpu)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 7ac84065f4ab99fbf822f47984117525396b2e6d..766b8c79d93d05949845b85e421b7dbd2e8a473a 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -53,16 +53,16 @@ static void __secure __mdelay(u32 ms)
        u32 reg = ONE_MS * ms;
 
        cp15_write_cntp_tval(reg);
-       ISB;
+       isb();
        cp15_write_cntp_ctl(3);
 
        do {
-               ISB;
+               isb();
                reg = cp15_read_cntp_ctl();
        } while (!(reg & BIT(2)));
 
        cp15_write_cntp_ctl(0);
-       ISB;
+       isb();
 }
 
 static void __secure clamp_release(u32 __maybe_unused *clamp)
@@ -164,7 +164,7 @@ static u32 __secure cp15_read_scr(void)
 static void __secure cp15_write_scr(u32 scr)
 {
        asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
-       ISB;
+       isb();
 }
 
 /*
@@ -190,7 +190,7 @@ void __secure __irq psci_fiq_enter(void)
 
        /* End of interrupt */
        writel(reg, GICC_BASE + GICC_EOIR);
-       DSB;
+       dsb();
 
        /* Get CPU number */
        cpu = (reg >> 10) & 0x7;
@@ -242,7 +242,7 @@ void __secure psci_cpu_off(void)
 
        /* Ask CPU0 via SGI15 to pull the rug... */
        writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
-       DSB;
+       dsb();
 
        /* Wait to be turned off */
        while (1)

diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h
index 37870f9d717e092924f6a572bc61709f430bb687..04784b7cb62a4e8c896853c643fec74305376465 100644 (file)
--- a/arch/arm/include/asm/barriers.h
+++ b/arch/arm/include/asm/barriers.h
@@ -30,15 +30,22 @@
 
 #endif /* !CONFIG_ARM64 */
 
-#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64)
+#if __LINUX_ARM_ARCH__ >= 7
 #define ISB    asm volatile ("isb sy" : : : "memory")
 #define DSB    asm volatile ("dsb sy" : : : "memory")
 #define DMB    asm volatile ("dmb sy" : : : "memory")
-#else
+#elif __LINUX_ARM_ARCH__ == 6
 #define ISB    CP15ISB
 #define DSB    CP15DSB
 #define DMB    CP15DMB
+#else
+#define ISB    asm volatile ("" : : : "memory")
+#define DSB    CP15DSB
+#define DMB    asm volatile ("" : : : "memory")
 #endif
 
+#define isb()  ISB
+#define dsb()  DSB
+#define dmb()  DMB
 #endif /* __ASSEMBLY__ */
 #endif /* __BARRIERS_H__ */

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 6121f1ddcac49febcd6ccf2a8d834aec00c6a148..5834f5b3dc9ae8a18c4ef9bde183e719fcc627c5 100644 (file)
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -25,6 +25,7 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 #include <asm/memory.h>
+#include <asm/barriers.h>
 #if 0  /* XXX###XXX */
 #include <asm/arch/hardware.h>
 #endif /* XXX###XXX */
@@ -136,8 +137,7 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
  * TODO: The kernel offers some more advanced versions of barriers, it might
  * have some advantages to use them instead of the simple one here.
  */
-#define mb()           asm volatile("dsb sy" : : : "memory")
-#define dmb()          __asm__ __volatile__ ("" : : : "memory")
+#define mb()           dsb()
 #define __iormb()      dmb()
 #define __iowmb()      dmb()
 

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0bec824e1c81dc358f1cf1955717e37cb0db..7b7b8675215e60c893f93eff8c8ec623cb23d529 100644 (file)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -3,6 +3,7 @@
 
 #include <common.h>
 #include <linux/compiler.h>
+#include <asm/barriers.h>
 
 #ifdef CONFIG_ARM64
 
@@ -34,11 +35,6 @@ enum dcache_option {
        DCACHE_WRITEALLOC = 4 << 2,
 };
 
-#define isb()                          \
-       ({asm volatile(                 \
-       "isb" : : : "memory");          \
-       })
-
 #define wfi()                          \
        ({asm volatile(                 \
        "wfi" : : : "memory");          \
@@ -227,8 +223,6 @@ void __noreturn psci_system_reset(bool smc);
  */
 void save_boot_params_ret(void);
 
-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
 #ifdef __ARM_ARCH_7A__

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 9f71376d30af4a54692e0c4be252af4215d00d4e..a8d1557629375ebb1ed8c9b20dd2ab905061d628 100644 (file)
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -67,11 +67,6 @@ extra-y      += eabi_compat.o
 endif
 
 asflags-y += -DCONFIG_ARM_ASM_UNIFIED
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
-asflags-y += -D__LINUX_ARM_ARCH__=4
-else
-asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
-endif
 
 # some files can only build in ARM or THUMB2, not THUMB1
 

diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
index 3ffb296a57fc1c97085d885b4ecfcb56ade5f945..2c94a6bea0b3679461576f69a25c977486df34de 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -37,16 +37,6 @@ struct exynos5_sysreg {
 
 #define USB20_PHY_CFG_HOST_LINK_EN     (1 << 0)
 
-/*
- * Data Synchronization Barrier acts as a special kind of memory barrier.
- * No instruction in program order after this instruction executes until
- * this instruction completes. This instruction completes when:
- * - All explicit memory accesses before this instruction complete.
- * - All Cache, Branch predictor and TLB maintenance operations before
- *   this instruction complete.
- */
-#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
-
 /*
  * This instruction causes an event to be signaled to all cores
  * within a multiprocessor system. If SEV is implemented,

diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index 20b430f859afd7a05128d3502285e44c62dfb450..95143d19ab50fa4f86c41888fad6ee0c9ae492dd 100644 (file)
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -32,7 +32,7 @@ bool mctl_mem_matches(u32 offset)
        /* Try to write different values to RAM at two addresses */
        writel(0, CONFIG_SYS_SDRAM_BASE);
        writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
-       DSB;
+       dsb();
        /* Check if the same value is actually observed when reading back */
        return readl(CONFIG_SYS_SDRAM_BASE) ==
               readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);

diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile
index 17c19900e216f0e537ea6ccc353f6c82e1cb09b5..72d82a5218f6a8795fe073e31968b6f11a5b2eb5 100644 (file)
--- a/arch/arm/mach-tegra/tegra20/Makefile
+++ b/arch/arm/mach-tegra/tegra20/Makefile
@@ -10,7 +10,8 @@ endif
 
 # The AVP is ARMv4T architecture so we must use special compiler
 # flags for any startup files it might use.
-CFLAGS_warmboot_avp.o += -march=armv4t
+CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \
+       -D__LINUX_ARM_ARCH__=4
 
 obj-y  += clock.o funcmux.o pinmux.o
 obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o